Pileus Git - ~andy/linux/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2011 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mdio.h>
  36 #include <linux/mii.h>
  37 #include <linux/phy.h>
  38 #include <linux/brcmphy.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/ip.h>
  41 #include <linux/tcp.h>
  42 #include <linux/workqueue.h>
  43 #include <linux/prefetch.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/firmware.h>
  46
  47 #include <net/checksum.h>
  48 #include <net/ip.h>
  49
  50 #include <asm/system.h>
  51 #include <linux/io.h>
  52 #include <asm/byteorder.h>
  53 #include <linux/uaccess.h>
  54
  55 #ifdef CONFIG_SPARC
  56 #include <asm/idprom.h>
  57 #include <asm/prom.h>
  58 #endif
  59
  60 #define BAR_0   0
  61 #define BAR_2   2
  62
  63 #include "tg3.h"
  64
  65 #define DRV_MODULE_NAME         "tg3"
  66 #define TG3_MAJ_NUM                     3
  67 #define TG3_MIN_NUM                     117
  68 #define DRV_MODULE_VERSION      \
  69         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  70 #define DRV_MODULE_RELDATE      "January 25, 2011"
  71
  72 #define TG3_DEF_MAC_MODE        0
  73 #define TG3_DEF_RX_MODE         0
  74 #define TG3_DEF_TX_MODE         0
  75 #define TG3_DEF_MSG_ENABLE        \
  76         (NETIF_MSG_DRV          | \
  77          NETIF_MSG_PROBE        | \
  78          NETIF_MSG_LINK         | \
  79          NETIF_MSG_TIMER        | \
  80          NETIF_MSG_IFDOWN       | \
  81          NETIF_MSG_IFUP         | \
  82          NETIF_MSG_RX_ERR       | \
  83          NETIF_MSG_TX_ERR)
  84
  85 /* length of time before we decide the hardware is borked,
  86  * and dev->tx_timeout() should be called to fix the problem
  87  */
  88 #define TG3_TX_TIMEOUT                  (5 * HZ)
  89
  90 /* hardware minimum and maximum for a single frame's data payload */
  91 #define TG3_MIN_MTU                     60
  92 #define TG3_MAX_MTU(tp) \
  93         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  94
  95 /* These numbers seem to be hard coded in the NIC firmware somehow.
  96  * You can't change the ring sizes, but you can change where you place
  97  * them in the NIC onboard memory.
  98  */
  99 #define TG3_RX_STD_RING_SIZE(tp) \
 100         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
 101          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JMB_RING_SIZE(tp) \
 104         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
 105          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
 106 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 107 #define TG3_RSS_INDIR_TBL_SIZE          128
 108
 109 /* Do not place this n-ring entries value into the tp struct itself,
 110  * we really want to expose these constants to GCC so that modulo et
 111  * al.  operations are done with shifts and masks instead of with
 112  * hw multiply/modulo instructions.  Another solution would be to
 113  * replace things like '% foo' with '& (foo - 1)'.
 114  */
 115
 116 #define TG3_TX_RING_SIZE                512
 117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 118
 119 #define TG3_RX_STD_RING_BYTES(tp) \
 120         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 121 #define TG3_RX_JMB_RING_BYTES(tp) \
 122         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 123 #define TG3_RX_RCB_RING_BYTES(tp) \
 124         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
 125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 126                                  TG3_TX_RING_SIZE)
 127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 128
 129 #define TG3_DMA_BYTE_ENAB               64
 130
 131 #define TG3_RX_STD_DMA_SZ               1536
 132 #define TG3_RX_JMB_DMA_SZ               9046
 133
 134 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 135
 136 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 137 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 138
 139 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 140         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 141
 142 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 143         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 144
 145 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 146  * that are at least dword aligned when used in PCIX mode.  The driver
 147  * works around this bug by double copying the packet.  This workaround
 148  * is built into the normal double copy length check for efficiency.
 149  *
 150  * However, the double copy is only necessary on those architectures
 151  * where unaligned memory accesses are inefficient.  For those architectures
 152  * where unaligned memory accesses incur little penalty, we can reintegrate
 153  * the 5701 in the normal rx path.  Doing so saves a device structure
 154  * dereference by hardcoding the double copy threshold in place.
 155  */
 156 #define TG3_RX_COPY_THRESHOLD           256
 157 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 158         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 159 #else
 160         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 161 #endif
 162
 163 /* minimum number of free TX descriptors required to wake up TX process */
 164 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 165
 166 #define TG3_RAW_IP_ALIGN 2
 167
 168 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 169
 170 #define FIRMWARE_TG3            "tigon/tg3.bin"
 171 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 172 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 173
 174 static char version[] __devinitdata =
 175         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 176
 177 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 178 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 179 MODULE_LICENSE("GPL");
 180 MODULE_VERSION(DRV_MODULE_VERSION);
 181 MODULE_FIRMWARE(FIRMWARE_TG3);
 182 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 183 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 184
 185 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 186 module_param(tg3_debug, int, 0);
 187 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 188
 189 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 270         {}
 271 };
 272
 273 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 274
 275 static const struct {
 276         const char string[ETH_GSTRING_LEN];
 277 } ethtool_stats_keys[] = {
 278         { "rx_octets" },
 279         { "rx_fragments" },
 280         { "rx_ucast_packets" },
 281         { "rx_mcast_packets" },
 282         { "rx_bcast_packets" },
 283         { "rx_fcs_errors" },
 284         { "rx_align_errors" },
 285         { "rx_xon_pause_rcvd" },
 286         { "rx_xoff_pause_rcvd" },
 287         { "rx_mac_ctrl_rcvd" },
 288         { "rx_xoff_entered" },
 289         { "rx_frame_too_long_errors" },
 290         { "rx_jabbers" },
 291         { "rx_undersize_packets" },
 292         { "rx_in_length_errors" },
 293         { "rx_out_length_errors" },
 294         { "rx_64_or_less_octet_packets" },
 295         { "rx_65_to_127_octet_packets" },
 296         { "rx_128_to_255_octet_packets" },
 297         { "rx_256_to_511_octet_packets" },
 298         { "rx_512_to_1023_octet_packets" },
 299         { "rx_1024_to_1522_octet_packets" },
 300         { "rx_1523_to_2047_octet_packets" },
 301         { "rx_2048_to_4095_octet_packets" },
 302         { "rx_4096_to_8191_octet_packets" },
 303         { "rx_8192_to_9022_octet_packets" },
 304
 305         { "tx_octets" },
 306         { "tx_collisions" },
 307
 308         { "tx_xon_sent" },
 309         { "tx_xoff_sent" },
 310         { "tx_flow_control" },
 311         { "tx_mac_errors" },
 312         { "tx_single_collisions" },
 313         { "tx_mult_collisions" },
 314         { "tx_deferred" },
 315         { "tx_excessive_collisions" },
 316         { "tx_late_collisions" },
 317         { "tx_collide_2times" },
 318         { "tx_collide_3times" },
 319         { "tx_collide_4times" },
 320         { "tx_collide_5times" },
 321         { "tx_collide_6times" },
 322         { "tx_collide_7times" },
 323         { "tx_collide_8times" },
 324         { "tx_collide_9times" },
 325         { "tx_collide_10times" },
 326         { "tx_collide_11times" },
 327         { "tx_collide_12times" },
 328         { "tx_collide_13times" },
 329         { "tx_collide_14times" },
 330         { "tx_collide_15times" },
 331         { "tx_ucast_packets" },
 332         { "tx_mcast_packets" },
 333         { "tx_bcast_packets" },
 334         { "tx_carrier_sense_errors" },
 335         { "tx_discards" },
 336         { "tx_errors" },
 337
 338         { "dma_writeq_full" },
 339         { "dma_write_prioq_full" },
 340         { "rxbds_empty" },
 341         { "rx_discards" },
 342         { "rx_errors" },
 343         { "rx_threshold_hit" },
 344
 345         { "dma_readq_full" },
 346         { "dma_read_prioq_full" },
 347         { "tx_comp_queue_full" },
 348
 349         { "ring_set_send_prod_index" },
 350         { "ring_status_update" },
 351         { "nic_irqs" },
 352         { "nic_avoided_irqs" },
 353         { "nic_tx_threshold_hit" }
 354 };
 355
 356 #define TG3_NUM_STATS   ARRAY_SIZE(ethtool_stats_keys)
 357
 358
 359 static const struct {
 360         const char string[ETH_GSTRING_LEN];
 361 } ethtool_test_keys[] = {
 362         { "nvram test     (online) " },
 363         { "link test      (online) " },
 364         { "register test  (offline)" },
 365         { "memory test    (offline)" },
 366         { "loopback test  (offline)" },
 367         { "interrupt test (offline)" },
 368 };
 369
 370 #define TG3_NUM_TEST    ARRAY_SIZE(ethtool_test_keys)
 371
 372
 373 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 374 {
 375         writel(val, tp->regs + off);
 376 }
 377
 378 static u32 tg3_read32(struct tg3 *tp, u32 off)
 379 {
 380         return readl(tp->regs + off);
 381 }
 382
 383 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 384 {
 385         writel(val, tp->aperegs + off);
 386 }
 387
 388 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 389 {
 390         return readl(tp->aperegs + off);
 391 }
 392
 393 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 394 {
 395         unsigned long flags;
 396
 397         spin_lock_irqsave(&tp->indirect_lock, flags);
 398         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 399         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 400         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 401 }
 402
 403 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 404 {
 405         writel(val, tp->regs + off);
 406         readl(tp->regs + off);
 407 }
 408
 409 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 410 {
 411         unsigned long flags;
 412         u32 val;
 413
 414         spin_lock_irqsave(&tp->indirect_lock, flags);
 415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 416         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 418         return val;
 419 }
 420
 421 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 422 {
 423         unsigned long flags;
 424
 425         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 426                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 427                                        TG3_64BIT_REG_LOW, val);
 428                 return;
 429         }
 430         if (off == TG3_RX_STD_PROD_IDX_REG) {
 431                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 432                                        TG3_64BIT_REG_LOW, val);
 433                 return;
 434         }
 435
 436         spin_lock_irqsave(&tp->indirect_lock, flags);
 437         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 438         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 439         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 440
 441         /* In indirect mode when disabling interrupts, we also need
 442          * to clear the interrupt bit in the GRC local ctrl register.
 443          */
 444         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 445             (val == 0x1)) {
 446                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 447                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 448         }
 449 }
 450
 451 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 452 {
 453         unsigned long flags;
 454         u32 val;
 455
 456         spin_lock_irqsave(&tp->indirect_lock, flags);
 457         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 458         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 459         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 460         return val;
 461 }
 462
 463 /* usec_wait specifies the wait time in usec when writing to certain registers
 464  * where it is unsafe to read back the register without some delay.
 465  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 466  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 467  */
 468 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 469 {
 470         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 471             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 472                 /* Non-posted methods */
 473                 tp->write32(tp, off, val);
 474         else {
 475                 /* Posted method */
 476                 tg3_write32(tp, off, val);
 477                 if (usec_wait)
 478                         udelay(usec_wait);
 479                 tp->read32(tp, off);
 480         }
 481         /* Wait again after the read for the posted method to guarantee that
 482          * the wait time is met.
 483          */
 484         if (usec_wait)
 485                 udelay(usec_wait);
 486 }
 487
 488 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 489 {
 490         tp->write32_mbox(tp, off, val);
 491         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 492             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 493                 tp->read32_mbox(tp, off);
 494 }
 495
 496 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         void __iomem *mbox = tp->regs + off;
 499         writel(val, mbox);
 500         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 501                 writel(val, mbox);
 502         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 503                 readl(mbox);
 504 }
 505
 506 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 507 {
 508         return readl(tp->regs + off + GRCMBOX_BASE);
 509 }
 510
 511 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 512 {
 513         writel(val, tp->regs + off + GRCMBOX_BASE);
 514 }
 515
 516 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 517 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 518 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 519 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 520 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 521
 522 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 523 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 524 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 525 #define tr32(reg)                       tp->read32(tp, reg)
 526
 527 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 528 {
 529         unsigned long flags;
 530
 531         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 532             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 533                 return;
 534
 535         spin_lock_irqsave(&tp->indirect_lock, flags);
 536         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 538                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 539
 540                 /* Always leave this as zero. */
 541                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 542         } else {
 543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 544                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 545
 546                 /* Always leave this as zero. */
 547                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 548         }
 549         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 550 }
 551
 552 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 553 {
 554         unsigned long flags;
 555
 556         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 557             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 558                 *val = 0;
 559                 return;
 560         }
 561
 562         spin_lock_irqsave(&tp->indirect_lock, flags);
 563         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 564                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 565                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 566
 567                 /* Always leave this as zero. */
 568                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 569         } else {
 570                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 571                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 572
 573                 /* Always leave this as zero. */
 574                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 575         }
 576         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 577 }
 578
 579 static void tg3_ape_lock_init(struct tg3 *tp)
 580 {
 581         int i;
 582         u32 regbase;
 583
 584         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 585                 regbase = TG3_APE_LOCK_GRANT;
 586         else
 587                 regbase = TG3_APE_PER_LOCK_GRANT;
 588
 589         /* Make sure the driver hasn't any stale locks. */
 590         for (i = 0; i < 8; i++)
 591                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 592 }
 593
 594 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 595 {
 596         int i, off;
 597         int ret = 0;
 598         u32 status, req, gnt;
 599
 600         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 601                 return 0;
 602
 603         switch (locknum) {
 604         case TG3_APE_LOCK_GRC:
 605         case TG3_APE_LOCK_MEM:
 606                 break;
 607         default:
 608                 return -EINVAL;
 609         }
 610
 611         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 612                 req = TG3_APE_LOCK_REQ;
 613                 gnt = TG3_APE_LOCK_GRANT;
 614         } else {
 615                 req = TG3_APE_PER_LOCK_REQ;
 616                 gnt = TG3_APE_PER_LOCK_GRANT;
 617         }
 618
 619         off = 4 * locknum;
 620
 621         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 622
 623         /* Wait for up to 1 millisecond to acquire lock. */
 624         for (i = 0; i < 100; i++) {
 625                 status = tg3_ape_read32(tp, gnt + off);
 626                 if (status == APE_LOCK_GRANT_DRIVER)
 627                         break;
 628                 udelay(10);
 629         }
 630
 631         if (status != APE_LOCK_GRANT_DRIVER) {
 632                 /* Revoke the lock request. */
 633                 tg3_ape_write32(tp, gnt + off,
 634                                 APE_LOCK_GRANT_DRIVER);
 635
 636                 ret = -EBUSY;
 637         }
 638
 639         return ret;
 640 }
 641
 642 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 643 {
 644         u32 gnt;
 645
 646         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 647                 return;
 648
 649         switch (locknum) {
 650         case TG3_APE_LOCK_GRC:
 651         case TG3_APE_LOCK_MEM:
 652                 break;
 653         default:
 654                 return;
 655         }
 656
 657         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 658                 gnt = TG3_APE_LOCK_GRANT;
 659         else
 660                 gnt = TG3_APE_PER_LOCK_GRANT;
 661
 662         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 663 }
 664
 665 static void tg3_disable_ints(struct tg3 *tp)
 666 {
 667         int i;
 668
 669         tw32(TG3PCI_MISC_HOST_CTRL,
 670              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 671         for (i = 0; i < tp->irq_max; i++)
 672                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 673 }
 674
 675 static void tg3_enable_ints(struct tg3 *tp)
 676 {
 677         int i;
 678
 679         tp->irq_sync = 0;
 680         wmb();
 681
 682         tw32(TG3PCI_MISC_HOST_CTRL,
 683              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 684
 685         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 686         for (i = 0; i < tp->irq_cnt; i++) {
 687                 struct tg3_napi *tnapi = &tp->napi[i];
 688
 689                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 690                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 691                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 692
 693                 tp->coal_now |= tnapi->coal_now;
 694         }
 695
 696         /* Force an initial interrupt */
 697         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 698             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 699                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 700         else
 701                 tw32(HOSTCC_MODE, tp->coal_now);
 702
 703         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 704 }
 705
 706 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 707 {
 708         struct tg3 *tp = tnapi->tp;
 709         struct tg3_hw_status *sblk = tnapi->hw_status;
 710         unsigned int work_exists = 0;
 711
 712         /* check for phy events */
 713         if (!(tp->tg3_flags &
 714               (TG3_FLAG_USE_LINKCHG_REG |
 715                TG3_FLAG_POLL_SERDES))) {
 716                 if (sblk->status & SD_STATUS_LINK_CHG)
 717                         work_exists = 1;
 718         }
 719         /* check for RX/TX work to do */
 720         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 721             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 722                 work_exists = 1;
 723
 724         return work_exists;
 725 }
 726
 727 /* tg3_int_reenable
 728  *  similar to tg3_enable_ints, but it accurately determines whether there
 729  *  is new work pending and can return without flushing the PIO write
 730  *  which reenables interrupts
 731  */
 732 static void tg3_int_reenable(struct tg3_napi *tnapi)
 733 {
 734         struct tg3 *tp = tnapi->tp;
 735
 736         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 737         mmiowb();
 738
 739         /* When doing tagged status, this work check is unnecessary.
 740          * The last_tag we write above tells the chip which piece of
 741          * work we've completed.
 742          */
 743         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 744             tg3_has_work(tnapi))
 745                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 746                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 747 }
 748
 749 static void tg3_switch_clocks(struct tg3 *tp)
 750 {
 751         u32 clock_ctrl;
 752         u32 orig_clock_ctrl;
 753
 754         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 755             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 756                 return;
 757
 758         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 759
 760         orig_clock_ctrl = clock_ctrl;
 761         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 762                        CLOCK_CTRL_CLKRUN_OENABLE |
 763                        0x1f);
 764         tp->pci_clock_ctrl = clock_ctrl;
 765
 766         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 767                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 768                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 769                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 770                 }
 771         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 772                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 773                             clock_ctrl |
 774                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 775                             40);
 776                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 777                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 778                             40);
 779         }
 780         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 781 }
 782
 783 #define PHY_BUSY_LOOPS  5000
 784
 785 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 786 {
 787         u32 frame_val;
 788         unsigned int loops;
 789         int ret;
 790
 791         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 792                 tw32_f(MAC_MI_MODE,
 793                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 794                 udelay(80);
 795         }
 796
 797         *val = 0x0;
 798
 799         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 800                       MI_COM_PHY_ADDR_MASK);
 801         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 802                       MI_COM_REG_ADDR_MASK);
 803         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 804
 805         tw32_f(MAC_MI_COM, frame_val);
 806
 807         loops = PHY_BUSY_LOOPS;
 808         while (loops != 0) {
 809                 udelay(10);
 810                 frame_val = tr32(MAC_MI_COM);
 811
 812                 if ((frame_val & MI_COM_BUSY) == 0) {
 813                         udelay(5);
 814                         frame_val = tr32(MAC_MI_COM);
 815                         break;
 816                 }
 817                 loops -= 1;
 818         }
 819
 820         ret = -EBUSY;
 821         if (loops != 0) {
 822                 *val = frame_val & MI_COM_DATA_MASK;
 823                 ret = 0;
 824         }
 825
 826         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 827                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 828                 udelay(80);
 829         }
 830
 831         return ret;
 832 }
 833
 834 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 835 {
 836         u32 frame_val;
 837         unsigned int loops;
 838         int ret;
 839
 840         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 841             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 842                 return 0;
 843
 844         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 845                 tw32_f(MAC_MI_MODE,
 846                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 847                 udelay(80);
 848         }
 849
 850         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 851                       MI_COM_PHY_ADDR_MASK);
 852         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 853                       MI_COM_REG_ADDR_MASK);
 854         frame_val |= (val & MI_COM_DATA_MASK);
 855         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 856
 857         tw32_f(MAC_MI_COM, frame_val);
 858
 859         loops = PHY_BUSY_LOOPS;
 860         while (loops != 0) {
 861                 udelay(10);
 862                 frame_val = tr32(MAC_MI_COM);
 863                 if ((frame_val & MI_COM_BUSY) == 0) {
 864                         udelay(5);
 865                         frame_val = tr32(MAC_MI_COM);
 866                         break;
 867                 }
 868                 loops -= 1;
 869         }
 870
 871         ret = -EBUSY;
 872         if (loops != 0)
 873                 ret = 0;
 874
 875         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 876                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 877                 udelay(80);
 878         }
 879
 880         return ret;
 881 }
 882
 883 static int tg3_bmcr_reset(struct tg3 *tp)
 884 {
 885         u32 phy_control;
 886         int limit, err;
 887
 888         /* OK, reset it, and poll the BMCR_RESET bit until it
 889          * clears or we time out.
 890          */
 891         phy_control = BMCR_RESET;
 892         err = tg3_writephy(tp, MII_BMCR, phy_control);
 893         if (err != 0)
 894                 return -EBUSY;
 895
 896         limit = 5000;
 897         while (limit--) {
 898                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 899                 if (err != 0)
 900                         return -EBUSY;
 901
 902                 if ((phy_control & BMCR_RESET) == 0) {
 903                         udelay(40);
 904                         break;
 905                 }
 906                 udelay(10);
 907         }
 908         if (limit < 0)
 909                 return -EBUSY;
 910
 911         return 0;
 912 }
 913
 914 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 915 {
 916         struct tg3 *tp = bp->priv;
 917         u32 val;
 918
 919         spin_lock_bh(&tp->lock);
 920
 921         if (tg3_readphy(tp, reg, &val))
 922                 val = -EIO;
 923
 924         spin_unlock_bh(&tp->lock);
 925
 926         return val;
 927 }
 928
 929 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 930 {
 931         struct tg3 *tp = bp->priv;
 932         u32 ret = 0;
 933
 934         spin_lock_bh(&tp->lock);
 935
 936         if (tg3_writephy(tp, reg, val))
 937                 ret = -EIO;
 938
 939         spin_unlock_bh(&tp->lock);
 940
 941         return ret;
 942 }
 943
 944 static int tg3_mdio_reset(struct mii_bus *bp)
 945 {
 946         return 0;
 947 }
 948
 949 static void tg3_mdio_config_5785(struct tg3 *tp)
 950 {
 951         u32 val;
 952         struct phy_device *phydev;
 953
 954         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 955         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 956         case PHY_ID_BCM50610:
 957         case PHY_ID_BCM50610M:
 958                 val = MAC_PHYCFG2_50610_LED_MODES;
 959                 break;
 960         case PHY_ID_BCMAC131:
 961                 val = MAC_PHYCFG2_AC131_LED_MODES;
 962                 break;
 963         case PHY_ID_RTL8211C:
 964                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 965                 break;
 966         case PHY_ID_RTL8201E:
 967                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 968                 break;
 969         default:
 970                 return;
 971         }
 972
 973         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 974                 tw32(MAC_PHYCFG2, val);
 975
 976                 val = tr32(MAC_PHYCFG1);
 977                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 978                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 979                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 980                 tw32(MAC_PHYCFG1, val);
 981
 982                 return;
 983         }
 984
 985         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 986                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 987                        MAC_PHYCFG2_FMODE_MASK_MASK |
 988                        MAC_PHYCFG2_GMODE_MASK_MASK |
 989                        MAC_PHYCFG2_ACT_MASK_MASK   |
 990                        MAC_PHYCFG2_QUAL_MASK_MASK |
 991                        MAC_PHYCFG2_INBAND_ENABLE;
 992
 993         tw32(MAC_PHYCFG2, val);
 994
 995         val = tr32(MAC_PHYCFG1);
 996         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 997                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 998         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
 999                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1000                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1001                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1002                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1003         }
1004         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1005                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1006         tw32(MAC_PHYCFG1, val);
1007
1008         val = tr32(MAC_EXT_RGMII_MODE);
1009         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1010                  MAC_RGMII_MODE_RX_QUALITY |
1011                  MAC_RGMII_MODE_RX_ACTIVITY |
1012                  MAC_RGMII_MODE_RX_ENG_DET |
1013                  MAC_RGMII_MODE_TX_ENABLE |
1014                  MAC_RGMII_MODE_TX_LOWPWR |
1015                  MAC_RGMII_MODE_TX_RESET);
1016         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1017                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1018                         val |= MAC_RGMII_MODE_RX_INT_B |
1019                                MAC_RGMII_MODE_RX_QUALITY |
1020                                MAC_RGMII_MODE_RX_ACTIVITY |
1021                                MAC_RGMII_MODE_RX_ENG_DET;
1022                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1023                         val |= MAC_RGMII_MODE_TX_ENABLE |
1024                                MAC_RGMII_MODE_TX_LOWPWR |
1025                                MAC_RGMII_MODE_TX_RESET;
1026         }
1027         tw32(MAC_EXT_RGMII_MODE, val);
1028 }
1029
1030 static void tg3_mdio_start(struct tg3 *tp)
1031 {
1032         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1033         tw32_f(MAC_MI_MODE, tp->mi_mode);
1034         udelay(80);
1035
1036         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1038                 tg3_mdio_config_5785(tp);
1039 }
1040
1041 static int tg3_mdio_init(struct tg3 *tp)
1042 {
1043         int i;
1044         u32 reg;
1045         struct phy_device *phydev;
1046
1047         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
1048                 u32 is_serdes;
1049
1050                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1051
1052                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1053                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1054                 else
1055                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1056                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1057                 if (is_serdes)
1058                         tp->phy_addr += 7;
1059         } else
1060                 tp->phy_addr = TG3_PHY_MII_ADDR;
1061
1062         tg3_mdio_start(tp);
1063
1064         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1065             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1066                 return 0;
1067
1068         tp->mdio_bus = mdiobus_alloc();
1069         if (tp->mdio_bus == NULL)
1070                 return -ENOMEM;
1071
1072         tp->mdio_bus->name     = "tg3 mdio bus";
1073         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1074                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1075         tp->mdio_bus->priv     = tp;
1076         tp->mdio_bus->parent   = &tp->pdev->dev;
1077         tp->mdio_bus->read     = &tg3_mdio_read;
1078         tp->mdio_bus->write    = &tg3_mdio_write;
1079         tp->mdio_bus->reset    = &tg3_mdio_reset;
1080         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1081         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1082
1083         for (i = 0; i < PHY_MAX_ADDR; i++)
1084                 tp->mdio_bus->irq[i] = PHY_POLL;
1085
1086         /* The bus registration will look for all the PHYs on the mdio bus.
1087          * Unfortunately, it does not ensure the PHY is powered up before
1088          * accessing the PHY ID registers.  A chip reset is the
1089          * quickest way to bring the device back to an operational state..
1090          */
1091         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1092                 tg3_bmcr_reset(tp);
1093
1094         i = mdiobus_register(tp->mdio_bus);
1095         if (i) {
1096                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1097                 mdiobus_free(tp->mdio_bus);
1098                 return i;
1099         }
1100
1101         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1102
1103         if (!phydev || !phydev->drv) {
1104                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1105                 mdiobus_unregister(tp->mdio_bus);
1106                 mdiobus_free(tp->mdio_bus);
1107                 return -ENODEV;
1108         }
1109
1110         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1111         case PHY_ID_BCM57780:
1112                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1113                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1114                 break;
1115         case PHY_ID_BCM50610:
1116         case PHY_ID_BCM50610M:
1117                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1118                                      PHY_BRCM_RX_REFCLK_UNUSED |
1119                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1120                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1121                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1122                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1123                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1124                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1125                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1126                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1127                 /* fallthru */
1128         case PHY_ID_RTL8211C:
1129                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1130                 break;
1131         case PHY_ID_RTL8201E:
1132         case PHY_ID_BCMAC131:
1133                 phydev->interface = PHY_INTERFACE_MODE_MII;
1134                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1135                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1136                 break;
1137         }
1138
1139         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1140
1141         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1142                 tg3_mdio_config_5785(tp);
1143
1144         return 0;
1145 }
1146
1147 static void tg3_mdio_fini(struct tg3 *tp)
1148 {
1149         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1150                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1151                 mdiobus_unregister(tp->mdio_bus);
1152                 mdiobus_free(tp->mdio_bus);
1153         }
1154 }
1155
1156 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1157 {
1158         int err;
1159
1160         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1161         if (err)
1162                 goto done;
1163
1164         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1165         if (err)
1166                 goto done;
1167
1168         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1169                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1170         if (err)
1171                 goto done;
1172
1173         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1174
1175 done:
1176         return err;
1177 }
1178
1179 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1180 {
1181         int err;
1182
1183         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1184         if (err)
1185                 goto done;
1186
1187         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1188         if (err)
1189                 goto done;
1190
1191         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1192                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1193         if (err)
1194                 goto done;
1195
1196         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1197
1198 done:
1199         return err;
1200 }
1201
1202 /* tp->lock is held. */
1203 static inline void tg3_generate_fw_event(struct tg3 *tp)
1204 {
1205         u32 val;
1206
1207         val = tr32(GRC_RX_CPU_EVENT);
1208         val |= GRC_RX_CPU_DRIVER_EVENT;
1209         tw32_f(GRC_RX_CPU_EVENT, val);
1210
1211         tp->last_event_jiffies = jiffies;
1212 }
1213
1214 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1215
1216 /* tp->lock is held. */
1217 static void tg3_wait_for_event_ack(struct tg3 *tp)
1218 {
1219         int i;
1220         unsigned int delay_cnt;
1221         long time_remain;
1222
1223         /* If enough time has passed, no wait is necessary. */
1224         time_remain = (long)(tp->last_event_jiffies + 1 +
1225                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1226                       (long)jiffies;
1227         if (time_remain < 0)
1228                 return;
1229
1230         /* Check if we can shorten the wait time. */
1231         delay_cnt = jiffies_to_usecs(time_remain);
1232         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1233                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1234         delay_cnt = (delay_cnt >> 3) + 1;
1235
1236         for (i = 0; i < delay_cnt; i++) {
1237                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1238                         break;
1239                 udelay(8);
1240         }
1241 }
1242
1243 /* tp->lock is held. */
1244 static void tg3_ump_link_report(struct tg3 *tp)
1245 {
1246         u32 reg;
1247         u32 val;
1248
1249         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1250             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1251                 return;
1252
1253         tg3_wait_for_event_ack(tp);
1254
1255         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1256
1257         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1258
1259         val = 0;
1260         if (!tg3_readphy(tp, MII_BMCR, &reg))
1261                 val = reg << 16;
1262         if (!tg3_readphy(tp, MII_BMSR, &reg))
1263                 val |= (reg & 0xffff);
1264         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1265
1266         val = 0;
1267         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1268                 val = reg << 16;
1269         if (!tg3_readphy(tp, MII_LPA, &reg))
1270                 val |= (reg & 0xffff);
1271         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1272
1273         val = 0;
1274         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1275                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1276                         val = reg << 16;
1277                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1278                         val |= (reg & 0xffff);
1279         }
1280         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1281
1282         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1283                 val = reg << 16;
1284         else
1285                 val = 0;
1286         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1287
1288         tg3_generate_fw_event(tp);
1289 }
1290
1291 static void tg3_link_report(struct tg3 *tp)
1292 {
1293         if (!netif_carrier_ok(tp->dev)) {
1294                 netif_info(tp, link, tp->dev, "Link is down\n");
1295                 tg3_ump_link_report(tp);
1296         } else if (netif_msg_link(tp)) {
1297                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1298                             (tp->link_config.active_speed == SPEED_1000 ?
1299                              1000 :
1300                              (tp->link_config.active_speed == SPEED_100 ?
1301                               100 : 10)),
1302                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1303                              "full" : "half"));
1304
1305                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1306                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1307                             "on" : "off",
1308                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1309                             "on" : "off");
1310                 tg3_ump_link_report(tp);
1311         }
1312 }
1313
1314 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1315 {
1316         u16 miireg;
1317
1318         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1319                 miireg = ADVERTISE_PAUSE_CAP;
1320         else if (flow_ctrl & FLOW_CTRL_TX)
1321                 miireg = ADVERTISE_PAUSE_ASYM;
1322         else if (flow_ctrl & FLOW_CTRL_RX)
1323                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1324         else
1325                 miireg = 0;
1326
1327         return miireg;
1328 }
1329
1330 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1331 {
1332         u16 miireg;
1333
1334         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1335                 miireg = ADVERTISE_1000XPAUSE;
1336         else if (flow_ctrl & FLOW_CTRL_TX)
1337                 miireg = ADVERTISE_1000XPSE_ASYM;
1338         else if (flow_ctrl & FLOW_CTRL_RX)
1339                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1340         else
1341                 miireg = 0;
1342
1343         return miireg;
1344 }
1345
1346 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1347 {
1348         u8 cap = 0;
1349
1350         if (lcladv & ADVERTISE_1000XPAUSE) {
1351                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1352                         if (rmtadv & LPA_1000XPAUSE)
1353                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1354                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1355                                 cap = FLOW_CTRL_RX;
1356                 } else {
1357                         if (rmtadv & LPA_1000XPAUSE)
1358                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1359                 }
1360         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1361                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1362                         cap = FLOW_CTRL_TX;
1363         }
1364
1365         return cap;
1366 }
1367
1368 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1369 {
1370         u8 autoneg;
1371         u8 flowctrl = 0;
1372         u32 old_rx_mode = tp->rx_mode;
1373         u32 old_tx_mode = tp->tx_mode;
1374
1375         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1376                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1377         else
1378                 autoneg = tp->link_config.autoneg;
1379
1380         if (autoneg == AUTONEG_ENABLE &&
1381             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1382                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1383                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1384                 else
1385                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1386         } else
1387                 flowctrl = tp->link_config.flowctrl;
1388
1389         tp->link_config.active_flowctrl = flowctrl;
1390
1391         if (flowctrl & FLOW_CTRL_RX)
1392                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1393         else
1394                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1395
1396         if (old_rx_mode != tp->rx_mode)
1397                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1398
1399         if (flowctrl & FLOW_CTRL_TX)
1400                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1401         else
1402                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1403
1404         if (old_tx_mode != tp->tx_mode)
1405                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1406 }
1407
1408 static void tg3_adjust_link(struct net_device *dev)
1409 {
1410         u8 oldflowctrl, linkmesg = 0;
1411         u32 mac_mode, lcl_adv, rmt_adv;
1412         struct tg3 *tp = netdev_priv(dev);
1413         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1414
1415         spin_lock_bh(&tp->lock);
1416
1417         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1418                                     MAC_MODE_HALF_DUPLEX);
1419
1420         oldflowctrl = tp->link_config.active_flowctrl;
1421
1422         if (phydev->link) {
1423                 lcl_adv = 0;
1424                 rmt_adv = 0;
1425
1426                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1427                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1428                 else if (phydev->speed == SPEED_1000 ||
1429                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1430                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1431                 else
1432                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1433
1434                 if (phydev->duplex == DUPLEX_HALF)
1435                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1436                 else {
1437                         lcl_adv = tg3_advert_flowctrl_1000T(
1438                                   tp->link_config.flowctrl);
1439
1440                         if (phydev->pause)
1441                                 rmt_adv = LPA_PAUSE_CAP;
1442                         if (phydev->asym_pause)
1443                                 rmt_adv |= LPA_PAUSE_ASYM;
1444                 }
1445
1446                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1447         } else
1448                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1449
1450         if (mac_mode != tp->mac_mode) {
1451                 tp->mac_mode = mac_mode;
1452                 tw32_f(MAC_MODE, tp->mac_mode);
1453                 udelay(40);
1454         }
1455
1456         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1457                 if (phydev->speed == SPEED_10)
1458                         tw32(MAC_MI_STAT,
1459                              MAC_MI_STAT_10MBPS_MODE |
1460                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1461                 else
1462                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1463         }
1464
1465         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1466                 tw32(MAC_TX_LENGTHS,
1467                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1468                       (6 << TX_LENGTHS_IPG_SHIFT) |
1469                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1470         else
1471                 tw32(MAC_TX_LENGTHS,
1472                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1473                       (6 << TX_LENGTHS_IPG_SHIFT) |
1474                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1475
1476         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1477             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1478             phydev->speed != tp->link_config.active_speed ||
1479             phydev->duplex != tp->link_config.active_duplex ||
1480             oldflowctrl != tp->link_config.active_flowctrl)
1481                 linkmesg = 1;
1482
1483         tp->link_config.active_speed = phydev->speed;
1484         tp->link_config.active_duplex = phydev->duplex;
1485
1486         spin_unlock_bh(&tp->lock);
1487
1488         if (linkmesg)
1489                 tg3_link_report(tp);
1490 }
1491
1492 static int tg3_phy_init(struct tg3 *tp)
1493 {
1494         struct phy_device *phydev;
1495
1496         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1497                 return 0;
1498
1499         /* Bring the PHY back to a known state. */
1500         tg3_bmcr_reset(tp);
1501
1502         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1503
1504         /* Attach the MAC to the PHY. */
1505         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1506                              phydev->dev_flags, phydev->interface);
1507         if (IS_ERR(phydev)) {
1508                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1509                 return PTR_ERR(phydev);
1510         }
1511
1512         /* Mask with MAC supported features. */
1513         switch (phydev->interface) {
1514         case PHY_INTERFACE_MODE_GMII:
1515         case PHY_INTERFACE_MODE_RGMII:
1516                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1517                         phydev->supported &= (PHY_GBIT_FEATURES |
1518                                               SUPPORTED_Pause |
1519                                               SUPPORTED_Asym_Pause);
1520                         break;
1521                 }
1522                 /* fallthru */
1523         case PHY_INTERFACE_MODE_MII:
1524                 phydev->supported &= (PHY_BASIC_FEATURES |
1525                                       SUPPORTED_Pause |
1526                                       SUPPORTED_Asym_Pause);
1527                 break;
1528         default:
1529                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1530                 return -EINVAL;
1531         }
1532
1533         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1534
1535         phydev->advertising = phydev->supported;
1536
1537         return 0;
1538 }
1539
1540 static void tg3_phy_start(struct tg3 *tp)
1541 {
1542         struct phy_device *phydev;
1543
1544         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1545                 return;
1546
1547         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1548
1549         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1550                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1551                 phydev->speed = tp->link_config.orig_speed;
1552                 phydev->duplex = tp->link_config.orig_duplex;
1553                 phydev->autoneg = tp->link_config.orig_autoneg;
1554                 phydev->advertising = tp->link_config.orig_advertising;
1555         }
1556
1557         phy_start(phydev);
1558
1559         phy_start_aneg(phydev);
1560 }
1561
1562 static void tg3_phy_stop(struct tg3 *tp)
1563 {
1564         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1565                 return;
1566
1567         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1568 }
1569
1570 static void tg3_phy_fini(struct tg3 *tp)
1571 {
1572         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1573                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1574                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1575         }
1576 }
1577
1578 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1579 {
1580         int err;
1581
1582         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1583         if (!err)
1584                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1585
1586         return err;
1587 }
1588
1589 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1590 {
1591         int err;
1592
1593         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1594         if (!err)
1595                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1596
1597         return err;
1598 }
1599
1600 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1601 {
1602         u32 phytest;
1603
1604         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1605                 u32 phy;
1606
1607                 tg3_writephy(tp, MII_TG3_FET_TEST,
1608                              phytest | MII_TG3_FET_SHADOW_EN);
1609                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1610                         if (enable)
1611                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1612                         else
1613                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1614                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1615                 }
1616                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1617         }
1618 }
1619
1620 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1621 {
1622         u32 reg;
1623
1624         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1625             ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
1626              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1627                 return;
1628
1629         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1630                 tg3_phy_fet_toggle_apd(tp, enable);
1631                 return;
1632         }
1633
1634         reg = MII_TG3_MISC_SHDW_WREN |
1635               MII_TG3_MISC_SHDW_SCR5_SEL |
1636               MII_TG3_MISC_SHDW_SCR5_LPED |
1637               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1638               MII_TG3_MISC_SHDW_SCR5_SDTL |
1639               MII_TG3_MISC_SHDW_SCR5_C125OE;
1640         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1641                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1642
1643         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1644
1645
1646         reg = MII_TG3_MISC_SHDW_WREN |
1647               MII_TG3_MISC_SHDW_APD_SEL |
1648               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1649         if (enable)
1650                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1651
1652         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1653 }
1654
1655 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1656 {
1657         u32 phy;
1658
1659         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1660             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1661                 return;
1662
1663         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1664                 u32 ephy;
1665
1666                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1667                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1668
1669                         tg3_writephy(tp, MII_TG3_FET_TEST,
1670                                      ephy | MII_TG3_FET_SHADOW_EN);
1671                         if (!tg3_readphy(tp, reg, &phy)) {
1672                                 if (enable)
1673                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1674                                 else
1675                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1676                                 tg3_writephy(tp, reg, phy);
1677                         }
1678                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1679                 }
1680         } else {
1681                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1682                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1683                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1684                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1685                         if (enable)
1686                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1687                         else
1688                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1689                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1690                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1691                 }
1692         }
1693 }
1694
1695 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1696 {
1697         u32 val;
1698
1699         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1700                 return;
1701
1702         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1703             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1704                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1705                              (val | (1 << 15) | (1 << 4)));
1706 }
1707
1708 static void tg3_phy_apply_otp(struct tg3 *tp)
1709 {
1710         u32 otp, phy;
1711
1712         if (!tp->phy_otp)
1713                 return;
1714
1715         otp = tp->phy_otp;
1716
1717         /* Enable SM_DSP clock and tx 6dB coding. */
1718         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1719               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1720               MII_TG3_AUXCTL_ACTL_TX_6DB;
1721         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1722
1723         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1724         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1725         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1726
1727         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1728               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1729         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1730
1731         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1732         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1733         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1734
1735         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1736         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1737
1738         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1739         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1740
1741         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1742               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1743         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1744
1745         /* Turn off SM_DSP clock. */
1746         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1747               MII_TG3_AUXCTL_ACTL_TX_6DB;
1748         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1749 }
1750
1751 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1752 {
1753         u32 val;
1754
1755         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1756                 return;
1757
1758         tp->setlpicnt = 0;
1759
1760         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1761             current_link_up == 1 &&
1762             tp->link_config.active_duplex == DUPLEX_FULL &&
1763             (tp->link_config.active_speed == SPEED_100 ||
1764              tp->link_config.active_speed == SPEED_1000)) {
1765                 u32 eeectl;
1766
1767                 if (tp->link_config.active_speed == SPEED_1000)
1768                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1769                 else
1770                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1771
1772                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1773
1774                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1775                                   TG3_CL45_D7_EEERES_STAT, &val);
1776
1777                 switch (val) {
1778                 case TG3_CL45_D7_EEERES_STAT_LP_1000T:
1779                         switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
1780                         case ASIC_REV_5717:
1781                         case ASIC_REV_5719:
1782                         case ASIC_REV_57765:
1783                                 /* Enable SM_DSP clock and tx 6dB coding. */
1784                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1785                                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1786                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1787                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1788
1789                                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
1790
1791                                 /* Turn off SM_DSP clock. */
1792                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1793                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1794                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1795                         }
1796                         /* Fallthrough */
1797                 case TG3_CL45_D7_EEERES_STAT_LP_100TX:
1798                         tp->setlpicnt = 2;
1799                 }
1800         }
1801
1802         if (!tp->setlpicnt) {
1803                 val = tr32(TG3_CPMU_EEE_MODE);
1804                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1805         }
1806 }
1807
1808 static int tg3_wait_macro_done(struct tg3 *tp)
1809 {
1810         int limit = 100;
1811
1812         while (limit--) {
1813                 u32 tmp32;
1814
1815                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1816                         if ((tmp32 & 0x1000) == 0)
1817                                 break;
1818                 }
1819         }
1820         if (limit < 0)
1821                 return -EBUSY;
1822
1823         return 0;
1824 }
1825
1826 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1827 {
1828         static const u32 test_pat[4][6] = {
1829         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1830         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1831         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1832         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1833         };
1834         int chan;
1835
1836         for (chan = 0; chan < 4; chan++) {
1837                 int i;
1838
1839                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1840                              (chan * 0x2000) | 0x0200);
1841                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1842
1843                 for (i = 0; i < 6; i++)
1844                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1845                                      test_pat[chan][i]);
1846
1847                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1848                 if (tg3_wait_macro_done(tp)) {
1849                         *resetp = 1;
1850                         return -EBUSY;
1851                 }
1852
1853                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1854                              (chan * 0x2000) | 0x0200);
1855                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1856                 if (tg3_wait_macro_done(tp)) {
1857                         *resetp = 1;
1858                         return -EBUSY;
1859                 }
1860
1861                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1862                 if (tg3_wait_macro_done(tp)) {
1863                         *resetp = 1;
1864                         return -EBUSY;
1865                 }
1866
1867                 for (i = 0; i < 6; i += 2) {
1868                         u32 low, high;
1869
1870                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1871                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1872                             tg3_wait_macro_done(tp)) {
1873                                 *resetp = 1;
1874                                 return -EBUSY;
1875                         }
1876                         low &= 0x7fff;
1877                         high &= 0x000f;
1878                         if (low != test_pat[chan][i] ||
1879                             high != test_pat[chan][i+1]) {
1880                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1881                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1882                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1883
1884                                 return -EBUSY;
1885                         }
1886                 }
1887         }
1888
1889         return 0;
1890 }
1891
1892 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1893 {
1894         int chan;
1895
1896         for (chan = 0; chan < 4; chan++) {
1897                 int i;
1898
1899                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1900                              (chan * 0x2000) | 0x0200);
1901                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1902                 for (i = 0; i < 6; i++)
1903                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1904                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1905                 if (tg3_wait_macro_done(tp))
1906                         return -EBUSY;
1907         }
1908
1909         return 0;
1910 }
1911
1912 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1913 {
1914         u32 reg32, phy9_orig;
1915         int retries, do_phy_reset, err;
1916
1917         retries = 10;
1918         do_phy_reset = 1;
1919         do {
1920                 if (do_phy_reset) {
1921                         err = tg3_bmcr_reset(tp);
1922                         if (err)
1923                                 return err;
1924                         do_phy_reset = 0;
1925                 }
1926
1927                 /* Disable transmitter and interrupt.  */
1928                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1929                         continue;
1930
1931                 reg32 |= 0x3000;
1932                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1933
1934                 /* Set full-duplex, 1000 mbps.  */
1935                 tg3_writephy(tp, MII_BMCR,
1936                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1937
1938                 /* Set to master mode.  */
1939                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1940                         continue;
1941
1942                 tg3_writephy(tp, MII_TG3_CTRL,
1943                              (MII_TG3_CTRL_AS_MASTER |
1944                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1945
1946                 /* Enable SM_DSP_CLOCK and 6dB.  */
1947                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1948
1949                 /* Block the PHY control access.  */
1950                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1951
1952                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1953                 if (!err)
1954                         break;
1955         } while (--retries);
1956
1957         err = tg3_phy_reset_chanpat(tp);
1958         if (err)
1959                 return err;
1960
1961         tg3_phydsp_write(tp, 0x8005, 0x0000);
1962
1963         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1964         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1965
1966         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1967             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1968                 /* Set Extended packet length bit for jumbo frames */
1969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1970         } else {
1971                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1972         }
1973
1974         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1975
1976         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1977                 reg32 &= ~0x3000;
1978                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1979         } else if (!err)
1980                 err = -EBUSY;
1981
1982         return err;
1983 }
1984
1985 /* This will reset the tigon3 PHY if there is no valid
1986  * link unless the FORCE argument is non-zero.
1987  */
1988 static int tg3_phy_reset(struct tg3 *tp)
1989 {
1990         u32 val, cpmuctrl;
1991         int err;
1992
1993         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1994                 val = tr32(GRC_MISC_CFG);
1995                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1996                 udelay(40);
1997         }
1998         err  = tg3_readphy(tp, MII_BMSR, &val);
1999         err |= tg3_readphy(tp, MII_BMSR, &val);
2000         if (err != 0)
2001                 return -EBUSY;
2002
2003         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2004                 netif_carrier_off(tp->dev);
2005                 tg3_link_report(tp);
2006         }
2007
2008         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2010             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2011                 err = tg3_phy_reset_5703_4_5(tp);
2012                 if (err)
2013                         return err;
2014                 goto out;
2015         }
2016
2017         cpmuctrl = 0;
2018         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2019             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2020                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2021                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2022                         tw32(TG3_CPMU_CTRL,
2023                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2024         }
2025
2026         err = tg3_bmcr_reset(tp);
2027         if (err)
2028                 return err;
2029
2030         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2031                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2032                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2033
2034                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2035         }
2036
2037         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2038             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2039                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2040                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2041                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2042                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2043                         udelay(40);
2044                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2045                 }
2046         }
2047
2048         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
2049             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2050                 return 0;
2051
2052         tg3_phy_apply_otp(tp);
2053
2054         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2055                 tg3_phy_toggle_apd(tp, true);
2056         else
2057                 tg3_phy_toggle_apd(tp, false);
2058
2059 out:
2060         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2061                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2062                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2063                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2064                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2065         }
2066         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2067                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2068                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2069         }
2070         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2071                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2072                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2073                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2074                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2075                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2076         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2077                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2078                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2079                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2080                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2081                         tg3_writephy(tp, MII_TG3_TEST1,
2082                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2083                 } else
2084                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2085                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2086         }
2087         /* Set Extended packet length bit (bit 14) on all chips that */
2088         /* support jumbo frames */
2089         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2090                 /* Cannot do read-modify-write on 5401 */
2091                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2092         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2093                 /* Set bit 14 with read-modify-write to preserve other bits */
2094                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2095                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2096                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2097         }
2098
2099         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2100          * jumbo frames transmission.
2101          */
2102         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2103                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2104                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2105                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2106         }
2107
2108         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2109                 /* adjust output voltage */
2110                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2111         }
2112
2113         tg3_phy_toggle_automdix(tp, 1);
2114         tg3_phy_set_wirespeed(tp);
2115         return 0;
2116 }
2117
2118 static void tg3_frob_aux_power(struct tg3 *tp)
2119 {
2120         bool need_vaux = false;
2121
2122         /* The GPIOs do something completely different on 57765. */
2123         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2124             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2125             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2126                 return;
2127
2128         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2129              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2130              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2131              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
2132             tp->pdev_peer != tp->pdev) {
2133                 struct net_device *dev_peer;
2134
2135                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2136
2137                 /* remove_one() may have been run on the peer. */
2138                 if (dev_peer) {
2139                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2140
2141                         if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE)
2142                                 return;
2143
2144                         if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2145                             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF))
2146                                 need_vaux = true;
2147                 }
2148         }
2149
2150         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2151             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2152                 need_vaux = true;
2153
2154         if (need_vaux) {
2155                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2156                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2157                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2158                                     (GRC_LCLCTRL_GPIO_OE0 |
2159                                      GRC_LCLCTRL_GPIO_OE1 |
2160                                      GRC_LCLCTRL_GPIO_OE2 |
2161                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2162                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2163                                     100);
2164                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2165                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2166                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2167                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2168                                              GRC_LCLCTRL_GPIO_OE1 |
2169                                              GRC_LCLCTRL_GPIO_OE2 |
2170                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2171                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2172                                              tp->grc_local_ctrl;
2173                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2174
2175                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2176                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2177
2178                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2179                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2180                 } else {
2181                         u32 no_gpio2;
2182                         u32 grc_local_ctrl = 0;
2183
2184                         /* Workaround to prevent overdrawing Amps. */
2185                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2186                             ASIC_REV_5714) {
2187                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2188                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2189                                             grc_local_ctrl, 100);
2190                         }
2191
2192                         /* On 5753 and variants, GPIO2 cannot be used. */
2193                         no_gpio2 = tp->nic_sram_data_cfg &
2194                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2195
2196                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2197                                          GRC_LCLCTRL_GPIO_OE1 |
2198                                          GRC_LCLCTRL_GPIO_OE2 |
2199                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2200                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2201                         if (no_gpio2) {
2202                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2203                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2204                         }
2205                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2206                                                     grc_local_ctrl, 100);
2207
2208                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2209
2210                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2211                                                     grc_local_ctrl, 100);
2212
2213                         if (!no_gpio2) {
2214                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2215                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2216                                             grc_local_ctrl, 100);
2217                         }
2218                 }
2219         } else {
2220                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2221                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2222                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2223                                     (GRC_LCLCTRL_GPIO_OE1 |
2224                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2225
2226                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2227                                     GRC_LCLCTRL_GPIO_OE1, 100);
2228
2229                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2230                                     (GRC_LCLCTRL_GPIO_OE1 |
2231                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2232                 }
2233         }
2234 }
2235
2236 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2237 {
2238         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2239                 return 1;
2240         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2241                 if (speed != SPEED_10)
2242                         return 1;
2243         } else if (speed == SPEED_10)
2244                 return 1;
2245
2246         return 0;
2247 }
2248
2249 static int tg3_setup_phy(struct tg3 *, int);
2250
2251 #define RESET_KIND_SHUTDOWN     0
2252 #define RESET_KIND_INIT         1
2253 #define RESET_KIND_SUSPEND      2
2254
2255 static void tg3_write_sig_post_reset(struct tg3 *, int);
2256 static int tg3_halt_cpu(struct tg3 *, u32);
2257
2258 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2259 {
2260         u32 val;
2261
2262         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2263                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2264                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2265                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2266
2267                         sg_dig_ctrl |=
2268                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2269                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2270                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2271                 }
2272                 return;
2273         }
2274
2275         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2276                 tg3_bmcr_reset(tp);
2277                 val = tr32(GRC_MISC_CFG);
2278                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2279                 udelay(40);
2280                 return;
2281         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2282                 u32 phytest;
2283                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2284                         u32 phy;
2285
2286                         tg3_writephy(tp, MII_ADVERTISE, 0);
2287                         tg3_writephy(tp, MII_BMCR,
2288                                      BMCR_ANENABLE | BMCR_ANRESTART);
2289
2290                         tg3_writephy(tp, MII_TG3_FET_TEST,
2291                                      phytest | MII_TG3_FET_SHADOW_EN);
2292                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2293                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2294                                 tg3_writephy(tp,
2295                                              MII_TG3_FET_SHDW_AUXMODE4,
2296                                              phy);
2297                         }
2298                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2299                 }
2300                 return;
2301         } else if (do_low_power) {
2302                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2303                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2304
2305                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2306                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2307                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2308                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2309                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2310         }
2311
2312         /* The PHY should not be powered down on some chips because
2313          * of bugs.
2314          */
2315         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2316             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2317             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2318              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2319                 return;
2320
2321         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2322             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2323                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2324                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2325                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2326                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2327         }
2328
2329         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2330 }
2331
2332 /* tp->lock is held. */
2333 static int tg3_nvram_lock(struct tg3 *tp)
2334 {
2335         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2336                 int i;
2337
2338                 if (tp->nvram_lock_cnt == 0) {
2339                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2340                         for (i = 0; i < 8000; i++) {
2341                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2342                                         break;
2343                                 udelay(20);
2344                         }
2345                         if (i == 8000) {
2346                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2347                                 return -ENODEV;
2348                         }
2349                 }
2350                 tp->nvram_lock_cnt++;
2351         }
2352         return 0;
2353 }
2354
2355 /* tp->lock is held. */
2356 static void tg3_nvram_unlock(struct tg3 *tp)
2357 {
2358         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2359                 if (tp->nvram_lock_cnt > 0)
2360                         tp->nvram_lock_cnt--;
2361                 if (tp->nvram_lock_cnt == 0)
2362                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2363         }
2364 }
2365
2366 /* tp->lock is held. */
2367 static void tg3_enable_nvram_access(struct tg3 *tp)
2368 {
2369         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2370             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2371                 u32 nvaccess = tr32(NVRAM_ACCESS);
2372
2373                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2374         }
2375 }
2376
2377 /* tp->lock is held. */
2378 static void tg3_disable_nvram_access(struct tg3 *tp)
2379 {
2380         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2381             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2382                 u32 nvaccess = tr32(NVRAM_ACCESS);
2383
2384                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2385         }
2386 }
2387
2388 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2389                                         u32 offset, u32 *val)
2390 {
2391         u32 tmp;
2392         int i;
2393
2394         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2395                 return -EINVAL;
2396
2397         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2398                                         EEPROM_ADDR_DEVID_MASK |
2399                                         EEPROM_ADDR_READ);
2400         tw32(GRC_EEPROM_ADDR,
2401              tmp |
2402              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2403              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2404               EEPROM_ADDR_ADDR_MASK) |
2405              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2406
2407         for (i = 0; i < 1000; i++) {
2408                 tmp = tr32(GRC_EEPROM_ADDR);
2409
2410                 if (tmp & EEPROM_ADDR_COMPLETE)
2411                         break;
2412                 msleep(1);
2413         }
2414         if (!(tmp & EEPROM_ADDR_COMPLETE))
2415                 return -EBUSY;
2416
2417         tmp = tr32(GRC_EEPROM_DATA);
2418
2419         /*
2420          * The data will always be opposite the native endian
2421          * format.  Perform a blind byteswap to compensate.
2422          */
2423         *val = swab32(tmp);
2424
2425         return 0;
2426 }
2427
2428 #define NVRAM_CMD_TIMEOUT 10000
2429
2430 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2431 {
2432         int i;
2433
2434         tw32(NVRAM_CMD, nvram_cmd);
2435         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2436                 udelay(10);
2437                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2438                         udelay(10);
2439                         break;
2440                 }
2441         }
2442
2443         if (i == NVRAM_CMD_TIMEOUT)
2444                 return -EBUSY;
2445
2446         return 0;
2447 }
2448
2449 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2450 {
2451         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2452             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2453             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2454            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2455             (tp->nvram_jedecnum == JEDEC_ATMEL))
2456
2457                 addr = ((addr / tp->nvram_pagesize) <<
2458                         ATMEL_AT45DB0X1B_PAGE_POS) +
2459                        (addr % tp->nvram_pagesize);
2460
2461         return addr;
2462 }
2463
2464 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2465 {
2466         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2467             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2468             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2469            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2470             (tp->nvram_jedecnum == JEDEC_ATMEL))
2471
2472                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2473                         tp->nvram_pagesize) +
2474                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2475
2476         return addr;
2477 }
2478
2479 /* NOTE: Data read in from NVRAM is byteswapped according to
2480  * the byteswapping settings for all other register accesses.
2481  * tg3 devices are BE devices, so on a BE machine, the data
2482  * returned will be exactly as it is seen in NVRAM.  On a LE
2483  * machine, the 32-bit value will be byteswapped.
2484  */
2485 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2486 {
2487         int ret;
2488
2489         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2490                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2491
2492         offset = tg3_nvram_phys_addr(tp, offset);
2493
2494         if (offset > NVRAM_ADDR_MSK)
2495                 return -EINVAL;
2496
2497         ret = tg3_nvram_lock(tp);
2498         if (ret)
2499                 return ret;
2500
2501         tg3_enable_nvram_access(tp);
2502
2503         tw32(NVRAM_ADDR, offset);
2504         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2505                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2506
2507         if (ret == 0)
2508                 *val = tr32(NVRAM_RDDATA);
2509
2510         tg3_disable_nvram_access(tp);
2511
2512         tg3_nvram_unlock(tp);
2513
2514         return ret;
2515 }
2516
2517 /* Ensures NVRAM data is in bytestream format. */
2518 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2519 {
2520         u32 v;
2521         int res = tg3_nvram_read(tp, offset, &v);
2522         if (!res)
2523                 *val = cpu_to_be32(v);
2524         return res;
2525 }
2526
2527 /* tp->lock is held. */
2528 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2529 {
2530         u32 addr_high, addr_low;
2531         int i;
2532
2533         addr_high = ((tp->dev->dev_addr[0] << 8) |
2534                      tp->dev->dev_addr[1]);
2535         addr_low = ((tp->dev->dev_addr[2] << 24) |
2536                     (tp->dev->dev_addr[3] << 16) |
2537                     (tp->dev->dev_addr[4] <<  8) |
2538                     (tp->dev->dev_addr[5] <<  0));
2539         for (i = 0; i < 4; i++) {
2540                 if (i == 1 && skip_mac_1)
2541                         continue;
2542                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2543                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2544         }
2545
2546         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2547             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2548                 for (i = 0; i < 12; i++) {
2549                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2550                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2551                 }
2552         }
2553
2554         addr_high = (tp->dev->dev_addr[0] +
2555                      tp->dev->dev_addr[1] +
2556                      tp->dev->dev_addr[2] +
2557                      tp->dev->dev_addr[3] +
2558                      tp->dev->dev_addr[4] +
2559                      tp->dev->dev_addr[5]) &
2560                 TX_BACKOFF_SEED_MASK;
2561         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2562 }
2563
2564 static void tg3_enable_register_access(struct tg3 *tp)
2565 {
2566         /*
2567          * Make sure register accesses (indirect or otherwise) will function
2568          * correctly.
2569          */
2570         pci_write_config_dword(tp->pdev,
2571                                TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2572 }
2573
2574 static int tg3_power_up(struct tg3 *tp)
2575 {
2576         tg3_enable_register_access(tp);
2577
2578         pci_set_power_state(tp->pdev, PCI_D0);
2579
2580         /* Switch out of Vaux if it is a NIC */
2581         if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2582                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2583
2584         return 0;
2585 }
2586
2587 static int tg3_power_down_prepare(struct tg3 *tp)
2588 {
2589         u32 misc_host_ctrl;
2590         bool device_should_wake, do_low_power;
2591
2592         tg3_enable_register_access(tp);
2593
2594         /* Restore the CLKREQ setting. */
2595         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2596                 u16 lnkctl;
2597
2598                 pci_read_config_word(tp->pdev,
2599                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2600                                      &lnkctl);
2601                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2602                 pci_write_config_word(tp->pdev,
2603                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2604                                       lnkctl);
2605         }
2606
2607         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2608         tw32(TG3PCI_MISC_HOST_CTRL,
2609              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2610
2611         device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2612                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2613
2614         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2615                 do_low_power = false;
2616                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2617                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2618                         struct phy_device *phydev;
2619                         u32 phyid, advertising;
2620
2621                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2622
2623                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2624
2625                         tp->link_config.orig_speed = phydev->speed;
2626                         tp->link_config.orig_duplex = phydev->duplex;
2627                         tp->link_config.orig_autoneg = phydev->autoneg;
2628                         tp->link_config.orig_advertising = phydev->advertising;
2629
2630                         advertising = ADVERTISED_TP |
2631                                       ADVERTISED_Pause |
2632                                       ADVERTISED_Autoneg |
2633                                       ADVERTISED_10baseT_Half;
2634
2635                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2636                             device_should_wake) {
2637                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2638                                         advertising |=
2639                                                 ADVERTISED_100baseT_Half |
2640                                                 ADVERTISED_100baseT_Full |
2641                                                 ADVERTISED_10baseT_Full;
2642                                 else
2643                                         advertising |= ADVERTISED_10baseT_Full;
2644                         }
2645
2646                         phydev->advertising = advertising;
2647
2648                         phy_start_aneg(phydev);
2649
2650                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2651                         if (phyid != PHY_ID_BCMAC131) {
2652                                 phyid &= PHY_BCM_OUI_MASK;
2653                                 if (phyid == PHY_BCM_OUI_1 ||
2654                                     phyid == PHY_BCM_OUI_2 ||
2655                                     phyid == PHY_BCM_OUI_3)
2656                                         do_low_power = true;
2657                         }
2658                 }
2659         } else {
2660                 do_low_power = true;
2661
2662                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2663                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2664                         tp->link_config.orig_speed = tp->link_config.speed;
2665                         tp->link_config.orig_duplex = tp->link_config.duplex;
2666                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2667                 }
2668
2669                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2670                         tp->link_config.speed = SPEED_10;
2671                         tp->link_config.duplex = DUPLEX_HALF;
2672                         tp->link_config.autoneg = AUTONEG_ENABLE;
2673                         tg3_setup_phy(tp, 0);
2674                 }
2675         }
2676
2677         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2678                 u32 val;
2679
2680                 val = tr32(GRC_VCPU_EXT_CTRL);
2681                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2682         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2683                 int i;
2684                 u32 val;
2685
2686                 for (i = 0; i < 200; i++) {
2687                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2688                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2689                                 break;
2690                         msleep(1);
2691                 }
2692         }
2693         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2694                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2695                                                      WOL_DRV_STATE_SHUTDOWN |
2696                                                      WOL_DRV_WOL |
2697                                                      WOL_SET_MAGIC_PKT);
2698
2699         if (device_should_wake) {
2700                 u32 mac_mode;
2701
2702                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2703                         if (do_low_power) {
2704                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2705                                 udelay(40);
2706                         }
2707
2708                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2709                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2710                         else
2711                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2712
2713                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2714                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2715                             ASIC_REV_5700) {
2716                                 u32 speed = (tp->tg3_flags &
2717                                              TG3_FLAG_WOL_SPEED_100MB) ?
2718                                              SPEED_100 : SPEED_10;
2719                                 if (tg3_5700_link_polarity(tp, speed))
2720                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2721                                 else
2722                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2723                         }
2724                 } else {
2725                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2726                 }
2727
2728                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2729                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2730
2731                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2732                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2733                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2734                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2735                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2736                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2737
2738                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2739                         mac_mode |= MAC_MODE_APE_TX_EN |
2740                                     MAC_MODE_APE_RX_EN |
2741                                     MAC_MODE_TDE_ENABLE;
2742
2743                 tw32_f(MAC_MODE, mac_mode);
2744                 udelay(100);
2745
2746                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2747                 udelay(10);
2748         }
2749
2750         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2751             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2752              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2753                 u32 base_val;
2754
2755                 base_val = tp->pci_clock_ctrl;
2756                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2757                              CLOCK_CTRL_TXCLK_DISABLE);
2758
2759                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2760                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2761         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2762                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2763                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2764                 /* do nothing */
2765         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2766                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2767                 u32 newbits1, newbits2;
2768
2769                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2770                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2771                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2772                                     CLOCK_CTRL_TXCLK_DISABLE |
2773                                     CLOCK_CTRL_ALTCLK);
2774                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2775                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2776                         newbits1 = CLOCK_CTRL_625_CORE;
2777                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2778                 } else {
2779                         newbits1 = CLOCK_CTRL_ALTCLK;
2780                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2781                 }
2782
2783                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2784                             40);
2785
2786                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2787                             40);
2788
2789                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2790                         u32 newbits3;
2791
2792                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2793                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2794                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2795                                             CLOCK_CTRL_TXCLK_DISABLE |
2796                                             CLOCK_CTRL_44MHZ_CORE);
2797                         } else {
2798                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2799                         }
2800
2801                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2802                                     tp->pci_clock_ctrl | newbits3, 40);
2803                 }
2804         }
2805
2806         if (!(device_should_wake) &&
2807             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2808                 tg3_power_down_phy(tp, do_low_power);
2809
2810         tg3_frob_aux_power(tp);
2811
2812         /* Workaround for unstable PLL clock */
2813         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2814             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2815                 u32 val = tr32(0x7d00);
2816
2817                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2818                 tw32(0x7d00, val);
2819                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2820                         int err;
2821
2822                         err = tg3_nvram_lock(tp);
2823                         tg3_halt_cpu(tp, RX_CPU_BASE);
2824                         if (!err)
2825                                 tg3_nvram_unlock(tp);
2826                 }
2827         }
2828
2829         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2830
2831         return 0;
2832 }
2833
2834 static void tg3_power_down(struct tg3 *tp)
2835 {
2836         tg3_power_down_prepare(tp);
2837
2838         pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2839         pci_set_power_state(tp->pdev, PCI_D3hot);
2840 }
2841
2842 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2843 {
2844         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2845         case MII_TG3_AUX_STAT_10HALF:
2846                 *speed = SPEED_10;
2847                 *duplex = DUPLEX_HALF;
2848                 break;
2849
2850         case MII_TG3_AUX_STAT_10FULL:
2851                 *speed = SPEED_10;
2852                 *duplex = DUPLEX_FULL;
2853                 break;
2854
2855         case MII_TG3_AUX_STAT_100HALF:
2856                 *speed = SPEED_100;
2857                 *duplex = DUPLEX_HALF;
2858                 break;
2859
2860         case MII_TG3_AUX_STAT_100FULL:
2861                 *speed = SPEED_100;
2862                 *duplex = DUPLEX_FULL;
2863                 break;
2864
2865         case MII_TG3_AUX_STAT_1000HALF:
2866                 *speed = SPEED_1000;
2867                 *duplex = DUPLEX_HALF;
2868                 break;
2869
2870         case MII_TG3_AUX_STAT_1000FULL:
2871                 *speed = SPEED_1000;
2872                 *duplex = DUPLEX_FULL;
2873                 break;
2874
2875         default:
2876                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2877                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2878                                  SPEED_10;
2879                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2880                                   DUPLEX_HALF;
2881                         break;
2882                 }
2883                 *speed = SPEED_INVALID;
2884                 *duplex = DUPLEX_INVALID;
2885                 break;
2886         }
2887 }
2888
2889 static void tg3_phy_copper_begin(struct tg3 *tp)
2890 {
2891         u32 new_adv;
2892         int i;
2893
2894         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2895                 /* Entering low power mode.  Disable gigabit and
2896                  * 100baseT advertisements.
2897                  */
2898                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2899
2900                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2901                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2902                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2903                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2904
2905                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2906         } else if (tp->link_config.speed == SPEED_INVALID) {
2907                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2908                         tp->link_config.advertising &=
2909                                 ~(ADVERTISED_1000baseT_Half |
2910                                   ADVERTISED_1000baseT_Full);
2911
2912                 new_adv = ADVERTISE_CSMA;
2913                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2914                         new_adv |= ADVERTISE_10HALF;
2915                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2916                         new_adv |= ADVERTISE_10FULL;
2917                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2918                         new_adv |= ADVERTISE_100HALF;
2919                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2920                         new_adv |= ADVERTISE_100FULL;
2921
2922                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2923
2924                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2925
2926                 if (tp->link_config.advertising &
2927                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2928                         new_adv = 0;
2929                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2930                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2931                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2932                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2933                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2934                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2935                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2936                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2937                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2938                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2939                 } else {
2940                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2941                 }
2942         } else {
2943                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2944                 new_adv |= ADVERTISE_CSMA;
2945
2946                 /* Asking for a specific link mode. */
2947                 if (tp->link_config.speed == SPEED_1000) {
2948                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2949
2950                         if (tp->link_config.duplex == DUPLEX_FULL)
2951                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2952                         else
2953                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2954                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2955                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2956                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2957                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2958                 } else {
2959                         if (tp->link_config.speed == SPEED_100) {
2960                                 if (tp->link_config.duplex == DUPLEX_FULL)
2961                                         new_adv |= ADVERTISE_100FULL;
2962                                 else
2963                                         new_adv |= ADVERTISE_100HALF;
2964                         } else {
2965                                 if (tp->link_config.duplex == DUPLEX_FULL)
2966                                         new_adv |= ADVERTISE_10FULL;
2967                                 else
2968                                         new_adv |= ADVERTISE_10HALF;
2969                         }
2970                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2971
2972                         new_adv = 0;
2973                 }
2974
2975                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2976         }
2977
2978         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2979                 u32 val;
2980
2981                 tw32(TG3_CPMU_EEE_MODE,
2982                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2983
2984                 /* Enable SM_DSP clock and tx 6dB coding. */
2985                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2986                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2987                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2988                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2989
2990                 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
2991                 case ASIC_REV_5717:
2992                 case ASIC_REV_57765:
2993                         if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2994                                 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
2995                                                  MII_TG3_DSP_CH34TP2_HIBW01);
2996                         /* Fall through */
2997                 case ASIC_REV_5719:
2998                         val = MII_TG3_DSP_TAP26_ALNOKO |
2999                               MII_TG3_DSP_TAP26_RMRXSTO |
3000                               MII_TG3_DSP_TAP26_OPCSINPT;
3001                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3002                 }
3003
3004                 val = 0;
3005                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3006                         /* Advertise 100-BaseTX EEE ability */
3007                         if (tp->link_config.advertising &
3008                             ADVERTISED_100baseT_Full)
3009                                 val |= MDIO_AN_EEE_ADV_100TX;
3010                         /* Advertise 1000-BaseT EEE ability */
3011                         if (tp->link_config.advertising &
3012                             ADVERTISED_1000baseT_Full)
3013                                 val |= MDIO_AN_EEE_ADV_1000T;
3014                 }
3015                 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3016
3017                 /* Turn off SM_DSP clock. */
3018                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3019                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3020                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3021         }
3022
3023         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3024             tp->link_config.speed != SPEED_INVALID) {
3025                 u32 bmcr, orig_bmcr;
3026
3027                 tp->link_config.active_speed = tp->link_config.speed;
3028                 tp->link_config.active_duplex = tp->link_config.duplex;
3029
3030                 bmcr = 0;
3031                 switch (tp->link_config.speed) {
3032                 default:
3033                 case SPEED_10:
3034                         break;
3035
3036                 case SPEED_100:
3037                         bmcr |= BMCR_SPEED100;
3038                         break;
3039
3040                 case SPEED_1000:
3041                         bmcr |= TG3_BMCR_SPEED1000;
3042                         break;
3043                 }
3044
3045                 if (tp->link_config.duplex == DUPLEX_FULL)
3046                         bmcr |= BMCR_FULLDPLX;
3047
3048                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3049                     (bmcr != orig_bmcr)) {
3050                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3051                         for (i = 0; i < 1500; i++) {
3052                                 u32 tmp;
3053
3054                                 udelay(10);
3055                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3056                                     tg3_readphy(tp, MII_BMSR, &tmp))
3057                                         continue;
3058                                 if (!(tmp & BMSR_LSTATUS)) {
3059                                         udelay(40);
3060                                         break;
3061                                 }
3062                         }
3063                         tg3_writephy(tp, MII_BMCR, bmcr);
3064                         udelay(40);
3065                 }
3066         } else {
3067                 tg3_writephy(tp, MII_BMCR,
3068                              BMCR_ANENABLE | BMCR_ANRESTART);
3069         }
3070 }
3071
3072 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3073 {
3074         int err;
3075
3076         /* Turn off tap power management. */
3077         /* Set Extended packet length bit */
3078         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3079
3080         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3081         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3082         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3083         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3084         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3085
3086         udelay(40);
3087
3088         return err;
3089 }
3090
3091 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3092 {
3093         u32 adv_reg, all_mask = 0;
3094
3095         if (mask & ADVERTISED_10baseT_Half)
3096                 all_mask |= ADVERTISE_10HALF;
3097         if (mask & ADVERTISED_10baseT_Full)
3098                 all_mask |= ADVERTISE_10FULL;
3099         if (mask & ADVERTISED_100baseT_Half)
3100                 all_mask |= ADVERTISE_100HALF;
3101         if (mask & ADVERTISED_100baseT_Full)
3102                 all_mask |= ADVERTISE_100FULL;
3103
3104         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3105                 return 0;
3106
3107         if ((adv_reg & all_mask) != all_mask)
3108                 return 0;
3109         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3110                 u32 tg3_ctrl;
3111
3112                 all_mask = 0;
3113                 if (mask & ADVERTISED_1000baseT_Half)
3114                         all_mask |= ADVERTISE_1000HALF;
3115                 if (mask & ADVERTISED_1000baseT_Full)
3116                         all_mask |= ADVERTISE_1000FULL;
3117
3118                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3119                         return 0;
3120
3121                 if ((tg3_ctrl & all_mask) != all_mask)
3122                         return 0;
3123         }
3124         return 1;
3125 }
3126
3127 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3128 {
3129         u32 curadv, reqadv;
3130
3131         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3132                 return 1;
3133
3134         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3135         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3136
3137         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3138                 if (curadv != reqadv)
3139                         return 0;
3140
3141                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3142                         tg3_readphy(tp, MII_LPA, rmtadv);
3143         } else {
3144                 /* Reprogram the advertisement register, even if it
3145                  * does not affect the current link.  If the link
3146                  * gets renegotiated in the future, we can save an
3147                  * additional renegotiation cycle by advertising
3148                  * it correctly in the first place.
3149                  */
3150                 if (curadv != reqadv) {
3151                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3152                                      ADVERTISE_PAUSE_ASYM);
3153                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3154                 }
3155         }
3156
3157         return 1;
3158 }
3159
3160 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3161 {
3162         int current_link_up;
3163         u32 bmsr, val;
3164         u32 lcl_adv, rmt_adv;
3165         u16 current_speed;
3166         u8 current_duplex;
3167         int i, err;
3168
3169         tw32(MAC_EVENT, 0);
3170
3171         tw32_f(MAC_STATUS,
3172              (MAC_STATUS_SYNC_CHANGED |
3173               MAC_STATUS_CFG_CHANGED |
3174               MAC_STATUS_MI_COMPLETION |
3175               MAC_STATUS_LNKSTATE_CHANGED));
3176         udelay(40);
3177
3178         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3179                 tw32_f(MAC_MI_MODE,
3180                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3181                 udelay(80);
3182         }
3183
3184         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3185
3186         /* Some third-party PHYs need to be reset on link going
3187          * down.
3188          */
3189         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3190              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3191              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3192             netif_carrier_ok(tp->dev)) {
3193                 tg3_readphy(tp, MII_BMSR, &bmsr);
3194                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3195                     !(bmsr & BMSR_LSTATUS))
3196                         force_reset = 1;
3197         }
3198         if (force_reset)
3199                 tg3_phy_reset(tp);
3200
3201         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3202                 tg3_readphy(tp, MII_BMSR, &bmsr);
3203                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3204                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3205                         bmsr = 0;
3206
3207                 if (!(bmsr & BMSR_LSTATUS)) {
3208                         err = tg3_init_5401phy_dsp(tp);
3209                         if (err)
3210                                 return err;
3211
3212                         tg3_readphy(tp, MII_BMSR, &bmsr);
3213                         for (i = 0; i < 1000; i++) {
3214                                 udelay(10);
3215                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3216                                     (bmsr & BMSR_LSTATUS)) {
3217                                         udelay(40);
3218                                         break;
3219                                 }
3220                         }
3221
3222                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3223                             TG3_PHY_REV_BCM5401_B0 &&
3224                             !(bmsr & BMSR_LSTATUS) &&
3225                             tp->link_config.active_speed == SPEED_1000) {
3226                                 err = tg3_phy_reset(tp);
3227                                 if (!err)
3228                                         err = tg3_init_5401phy_dsp(tp);
3229                                 if (err)
3230                                         return err;
3231                         }
3232                 }
3233         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3234                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3235                 /* 5701 {A0,B0} CRC bug workaround */
3236                 tg3_writephy(tp, 0x15, 0x0a75);
3237                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3238                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3239                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3240         }
3241
3242         /* Clear pending interrupts... */
3243         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3244         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3245
3246         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3247                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3248         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3249                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3250
3251         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3252             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3253                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3254                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3255                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3256                 else
3257                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3258         }
3259
3260         current_link_up = 0;
3261         current_speed = SPEED_INVALID;
3262         current_duplex = DUPLEX_INVALID;
3263
3264         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3265                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3266                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3267                 if (!(val & (1 << 10))) {
3268                         val |= (1 << 10);
3269                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3270                         goto relink;
3271                 }
3272         }
3273
3274         bmsr = 0;
3275         for (i = 0; i < 100; i++) {
3276                 tg3_readphy(tp, MII_BMSR, &bmsr);
3277                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3278                     (bmsr & BMSR_LSTATUS))
3279                         break;
3280                 udelay(40);
3281         }
3282
3283         if (bmsr & BMSR_LSTATUS) {
3284                 u32 aux_stat, bmcr;
3285
3286                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3287                 for (i = 0; i < 2000; i++) {
3288                         udelay(10);
3289                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3290                             aux_stat)
3291                                 break;
3292                 }
3293
3294                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3295                                              &current_speed,
3296                                              &current_duplex);
3297
3298                 bmcr = 0;
3299                 for (i = 0; i < 200; i++) {
3300                         tg3_readphy(tp, MII_BMCR, &bmcr);
3301                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3302                                 continue;
3303                         if (bmcr && bmcr != 0x7fff)
3304                                 break;
3305                         udelay(10);
3306                 }
3307
3308                 lcl_adv = 0;
3309                 rmt_adv = 0;
3310
3311                 tp->link_config.active_speed = current_speed;
3312                 tp->link_config.active_duplex = current_duplex;
3313
3314                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3315                         if ((bmcr & BMCR_ANENABLE) &&
3316                             tg3_copper_is_advertising_all(tp,
3317                                                 tp->link_config.advertising)) {
3318                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3319                                                                   &rmt_adv))
3320                                         current_link_up = 1;
3321                         }
3322                 } else {
3323                         if (!(bmcr & BMCR_ANENABLE) &&
3324                             tp->link_config.speed == current_speed &&
3325                             tp->link_config.duplex == current_duplex &&
3326                             tp->link_config.flowctrl ==
3327                             tp->link_config.active_flowctrl) {
3328                                 current_link_up = 1;
3329                         }
3330                 }
3331
3332                 if (current_link_up == 1 &&
3333                     tp->link_config.active_duplex == DUPLEX_FULL)
3334                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3335         }
3336
3337 relink:
3338         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3339                 tg3_phy_copper_begin(tp);
3340
3341                 tg3_readphy(tp, MII_BMSR, &bmsr);
3342                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3343                     (bmsr & BMSR_LSTATUS))
3344                         current_link_up = 1;
3345         }
3346
3347         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3348         if (current_link_up == 1) {
3349                 if (tp->link_config.active_speed == SPEED_100 ||
3350                     tp->link_config.active_speed == SPEED_10)
3351                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3352                 else
3353                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3354         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3355                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3356         else
3357                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3358
3359         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3360         if (tp->link_config.active_duplex == DUPLEX_HALF)
3361                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3362
3363         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3364                 if (current_link_up == 1 &&
3365                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3366                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3367                 else
3368                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3369         }
3370
3371         /* ??? Without this setting Netgear GA302T PHY does not
3372          * ??? send/receive packets...
3373          */
3374         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3375             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3376                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3377                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3378                 udelay(80);
3379         }
3380
3381         tw32_f(MAC_MODE, tp->mac_mode);
3382         udelay(40);
3383
3384         tg3_phy_eee_adjust(tp, current_link_up);
3385
3386         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3387                 /* Polled via timer. */
3388                 tw32_f(MAC_EVENT, 0);
3389         } else {
3390                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3391         }
3392         udelay(40);
3393
3394         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3395             current_link_up == 1 &&
3396             tp->link_config.active_speed == SPEED_1000 &&
3397             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3398              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3399                 udelay(120);
3400                 tw32_f(MAC_STATUS,
3401                      (MAC_STATUS_SYNC_CHANGED |
3402                       MAC_STATUS_CFG_CHANGED));
3403                 udelay(40);
3404                 tg3_write_mem(tp,
3405                               NIC_SRAM_FIRMWARE_MBOX,
3406                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3407         }
3408
3409         /* Prevent send BD corruption. */
3410         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3411                 u16 oldlnkctl, newlnkctl;
3412
3413                 pci_read_config_word(tp->pdev,
3414                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3415                                      &oldlnkctl);
3416                 if (tp->link_config.active_speed == SPEED_100 ||
3417                     tp->link_config.active_speed == SPEED_10)
3418                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3419                 else
3420                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3421                 if (newlnkctl != oldlnkctl)
3422                         pci_write_config_word(tp->pdev,
3423                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3424                                               newlnkctl);
3425         }
3426
3427         if (current_link_up != netif_carrier_ok(tp->dev)) {
3428                 if (current_link_up)
3429                         netif_carrier_on(tp->dev);
3430                 else
3431                         netif_carrier_off(tp->dev);
3432                 tg3_link_report(tp);
3433         }
3434
3435         return 0;
3436 }
3437
3438 struct tg3_fiber_aneginfo {
3439         int state;
3440 #define ANEG_STATE_UNKNOWN              0
3441 #define ANEG_STATE_AN_ENABLE            1
3442 #define ANEG_STATE_RESTART_INIT         2
3443 #define ANEG_STATE_RESTART              3
3444 #define ANEG_STATE_DISABLE_LINK_OK      4
3445 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3446 #define ANEG_STATE_ABILITY_DETECT       6
3447 #define ANEG_STATE_ACK_DETECT_INIT      7
3448 #define ANEG_STATE_ACK_DETECT           8
3449 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3450 #define ANEG_STATE_COMPLETE_ACK         10
3451 #define ANEG_STATE_IDLE_DETECT_INIT     11
3452 #define ANEG_STATE_IDLE_DETECT          12
3453 #define ANEG_STATE_LINK_OK              13
3454 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3455 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3456
3457         u32 flags;
3458 #define MR_AN_ENABLE            0x00000001
3459 #define MR_RESTART_AN           0x00000002
3460 #define MR_AN_COMPLETE          0x00000004
3461 #define MR_PAGE_RX              0x00000008
3462 #define MR_NP_LOADED            0x00000010
3463 #define MR_TOGGLE_TX            0x00000020
3464 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3465 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3466 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3467 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3468 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3469 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3470 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3471 #define MR_TOGGLE_RX            0x00002000
3472 #define MR_NP_RX                0x00004000
3473
3474 #define MR_LINK_OK              0x80000000
3475
3476         unsigned long link_time, cur_time;
3477
3478         u32 ability_match_cfg;
3479         int ability_match_count;
3480
3481         char ability_match, idle_match, ack_match;
3482
3483         u32 txconfig, rxconfig;
3484 #define ANEG_CFG_NP             0x00000080
3485 #define ANEG_CFG_ACK            0x00000040
3486 #define ANEG_CFG_RF2            0x00000020
3487 #define ANEG_CFG_RF1            0x00000010
3488 #define ANEG_CFG_PS2            0x00000001
3489 #define ANEG_CFG_PS1            0x00008000
3490 #define ANEG_CFG_HD             0x00004000
3491 #define ANEG_CFG_FD             0x00002000
3492 #define ANEG_CFG_INVAL          0x00001f06
3493
3494 };
3495 #define ANEG_OK         0
3496 #define ANEG_DONE       1
3497 #define ANEG_TIMER_ENAB 2
3498 #define ANEG_FAILED     -1
3499
3500 #define ANEG_STATE_SETTLE_TIME  10000
3501
3502 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3503                                    struct tg3_fiber_aneginfo *ap)
3504 {
3505         u16 flowctrl;
3506         unsigned long delta;
3507         u32 rx_cfg_reg;
3508         int ret;
3509
3510         if (ap->state == ANEG_STATE_UNKNOWN) {
3511                 ap->rxconfig = 0;
3512                 ap->link_time = 0;
3513                 ap->cur_time = 0;
3514                 ap->ability_match_cfg = 0;
3515                 ap->ability_match_count = 0;
3516                 ap->ability_match = 0;
3517                 ap->idle_match = 0;
3518                 ap->ack_match = 0;
3519         }
3520         ap->cur_time++;
3521
3522         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3523                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3524
3525                 if (rx_cfg_reg != ap->ability_match_cfg) {
3526                         ap->ability_match_cfg = rx_cfg_reg;
3527                         ap->ability_match = 0;
3528                         ap->ability_match_count = 0;
3529                 } else {
3530                         if (++ap->ability_match_count > 1) {
3531                                 ap->ability_match = 1;
3532                                 ap->ability_match_cfg = rx_cfg_reg;
3533                         }
3534                 }
3535                 if (rx_cfg_reg & ANEG_CFG_ACK)
3536                         ap->ack_match = 1;
3537                 else
3538                         ap->ack_match = 0;
3539
3540                 ap->idle_match = 0;
3541         } else {
3542                 ap->idle_match = 1;
3543                 ap->ability_match_cfg = 0;
3544                 ap->ability_match_count = 0;
3545                 ap->ability_match = 0;
3546                 ap->ack_match = 0;
3547
3548                 rx_cfg_reg = 0;
3549         }
3550
3551         ap->rxconfig = rx_cfg_reg;
3552         ret = ANEG_OK;
3553
3554         switch (ap->state) {
3555         case ANEG_STATE_UNKNOWN:
3556                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3557                         ap->state = ANEG_STATE_AN_ENABLE;
3558
3559                 /* fallthru */
3560         case ANEG_STATE_AN_ENABLE:
3561                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3562                 if (ap->flags & MR_AN_ENABLE) {
3563                         ap->link_time = 0;
3564                         ap->cur_time = 0;
3565                         ap->ability_match_cfg = 0;
3566                         ap->ability_match_count = 0;
3567                         ap->ability_match = 0;
3568                         ap->idle_match = 0;
3569                         ap->ack_match = 0;
3570
3571                         ap->state = ANEG_STATE_RESTART_INIT;
3572                 } else {
3573                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3574                 }
3575                 break;
3576
3577         case ANEG_STATE_RESTART_INIT:
3578                 ap->link_time = ap->cur_time;
3579                 ap->flags &= ~(MR_NP_LOADED);
3580                 ap->txconfig = 0;
3581                 tw32(MAC_TX_AUTO_NEG, 0);
3582                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3583                 tw32_f(MAC_MODE, tp->mac_mode);
3584                 udelay(40);
3585
3586                 ret = ANEG_TIMER_ENAB;
3587                 ap->state = ANEG_STATE_RESTART;
3588
3589                 /* fallthru */
3590         case ANEG_STATE_RESTART:
3591                 delta = ap->cur_time - ap->link_time;
3592                 if (delta > ANEG_STATE_SETTLE_TIME)
3593                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3594                 else
3595                         ret = ANEG_TIMER_ENAB;
3596                 break;
3597
3598         case ANEG_STATE_DISABLE_LINK_OK:
3599                 ret = ANEG_DONE;
3600                 break;
3601
3602         case ANEG_STATE_ABILITY_DETECT_INIT:
3603                 ap->flags &= ~(MR_TOGGLE_TX);
3604                 ap->txconfig = ANEG_CFG_FD;
3605                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3606                 if (flowctrl & ADVERTISE_1000XPAUSE)
3607                         ap->txconfig |= ANEG_CFG_PS1;
3608                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3609                         ap->txconfig |= ANEG_CFG_PS2;
3610                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3611                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3612                 tw32_f(MAC_MODE, tp->mac_mode);
3613                 udelay(40);
3614
3615                 ap->state = ANEG_STATE_ABILITY_DETECT;
3616                 break;
3617
3618         case ANEG_STATE_ABILITY_DETECT:
3619                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3620                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3621                 break;
3622
3623         case ANEG_STATE_ACK_DETECT_INIT:
3624                 ap->txconfig |= ANEG_CFG_ACK;
3625                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3626                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3627                 tw32_f(MAC_MODE, tp->mac_mode);
3628                 udelay(40);
3629
3630                 ap->state = ANEG_STATE_ACK_DETECT;
3631
3632                 /* fallthru */
3633         case ANEG_STATE_ACK_DETECT:
3634                 if (ap->ack_match != 0) {
3635                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3636                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3637                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3638                         } else {
3639                                 ap->state = ANEG_STATE_AN_ENABLE;
3640                         }
3641                 } else if (ap->ability_match != 0 &&
3642                            ap->rxconfig == 0) {
3643                         ap->state = ANEG_STATE_AN_ENABLE;
3644                 }
3645                 break;
3646
3647         case ANEG_STATE_COMPLETE_ACK_INIT:
3648                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3649                         ret = ANEG_FAILED;
3650                         break;
3651                 }
3652                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3653                                MR_LP_ADV_HALF_DUPLEX |
3654                                MR_LP_ADV_SYM_PAUSE |
3655                                MR_LP_ADV_ASYM_PAUSE |
3656                                MR_LP_ADV_REMOTE_FAULT1 |
3657                                MR_LP_ADV_REMOTE_FAULT2 |
3658                                MR_LP_ADV_NEXT_PAGE |
3659                                MR_TOGGLE_RX |
3660                                MR_NP_RX);
3661                 if (ap->rxconfig & ANEG_CFG_FD)
3662                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3663                 if (ap->rxconfig & ANEG_CFG_HD)
3664                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3665                 if (ap->rxconfig & ANEG_CFG_PS1)
3666                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3667                 if (ap->rxconfig & ANEG_CFG_PS2)
3668                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3669                 if (ap->rxconfig & ANEG_CFG_RF1)
3670                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3671                 if (ap->rxconfig & ANEG_CFG_RF2)
3672                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3673                 if (ap->rxconfig & ANEG_CFG_NP)
3674                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3675
3676                 ap->link_time = ap->cur_time;
3677
3678                 ap->flags ^= (MR_TOGGLE_TX);
3679                 if (ap->rxconfig & 0x0008)
3680                         ap->flags |= MR_TOGGLE_RX;
3681                 if (ap->rxconfig & ANEG_CFG_NP)
3682                         ap->flags |= MR_NP_RX;
3683                 ap->flags |= MR_PAGE_RX;
3684
3685                 ap->state = ANEG_STATE_COMPLETE_ACK;
3686                 ret = ANEG_TIMER_ENAB;
3687                 break;
3688
3689         case ANEG_STATE_COMPLETE_ACK:
3690                 if (ap->ability_match != 0 &&
3691                     ap->rxconfig == 0) {
3692                         ap->state = ANEG_STATE_AN_ENABLE;
3693                         break;
3694                 }
3695                 delta = ap->cur_time - ap->link_time;
3696                 if (delta > ANEG_STATE_SETTLE_TIME) {
3697                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3698                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3699                         } else {
3700                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3701                                     !(ap->flags & MR_NP_RX)) {
3702                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3703                                 } else {
3704                                         ret = ANEG_FAILED;
3705                                 }
3706                         }
3707                 }
3708                 break;
3709
3710         case ANEG_STATE_IDLE_DETECT_INIT:
3711                 ap->link_time = ap->cur_time;
3712                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3713                 tw32_f(MAC_MODE, tp->mac_mode);
3714                 udelay(40);
3715
3716                 ap->state = ANEG_STATE_IDLE_DETECT;
3717                 ret = ANEG_TIMER_ENAB;
3718                 break;
3719
3720         case ANEG_STATE_IDLE_DETECT:
3721                 if (ap->ability_match != 0 &&
3722                     ap->rxconfig == 0) {
3723                         ap->state = ANEG_STATE_AN_ENABLE;
3724                         break;
3725                 }
3726                 delta = ap->cur_time - ap->link_time;
3727                 if (delta > ANEG_STATE_SETTLE_TIME) {
3728                         /* XXX another gem from the Broadcom driver :( */
3729                         ap->state = ANEG_STATE_LINK_OK;
3730                 }
3731                 break;
3732
3733         case ANEG_STATE_LINK_OK:
3734                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3735                 ret = ANEG_DONE;
3736                 break;
3737
3738         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3739                 /* ??? unimplemented */
3740                 break;
3741
3742         case ANEG_STATE_NEXT_PAGE_WAIT:
3743                 /* ??? unimplemented */
3744                 break;
3745
3746         default:
3747                 ret = ANEG_FAILED;
3748                 break;
3749         }
3750
3751         return ret;
3752 }
3753
3754 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3755 {
3756         int res = 0;
3757         struct tg3_fiber_aneginfo aninfo;
3758         int status = ANEG_FAILED;
3759         unsigned int tick;
3760         u32 tmp;
3761
3762         tw32_f(MAC_TX_AUTO_NEG, 0);
3763
3764         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3765         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3766         udelay(40);
3767
3768         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3769         udelay(40);
3770
3771         memset(&aninfo, 0, sizeof(aninfo));
3772         aninfo.flags |= MR_AN_ENABLE;
3773         aninfo.state = ANEG_STATE_UNKNOWN;
3774         aninfo.cur_time = 0;
3775         tick = 0;
3776         while (++tick < 195000) {
3777                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3778                 if (status == ANEG_DONE || status == ANEG_FAILED)
3779                         break;
3780
3781                 udelay(1);
3782         }
3783
3784         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3785         tw32_f(MAC_MODE, tp->mac_mode);
3786         udelay(40);
3787
3788         *txflags = aninfo.txconfig;
3789         *rxflags = aninfo.flags;
3790
3791         if (status == ANEG_DONE &&
3792             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3793                              MR_LP_ADV_FULL_DUPLEX)))
3794                 res = 1;
3795
3796         return res;
3797 }
3798
3799 static void tg3_init_bcm8002(struct tg3 *tp)
3800 {
3801         u32 mac_status = tr32(MAC_STATUS);
3802         int i;
3803
3804         /* Reset when initting first time or we have a link. */
3805         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3806             !(mac_status & MAC_STATUS_PCS_SYNCED))
3807                 return;
3808
3809         /* Set PLL lock range. */
3810         tg3_writephy(tp, 0x16, 0x8007);
3811
3812         /* SW reset */
3813         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3814
3815         /* Wait for reset to complete. */
3816         /* XXX schedule_timeout() ... */
3817         for (i = 0; i < 500; i++)
3818                 udelay(10);
3819
3820         /* Config mode; select PMA/Ch 1 regs. */
3821         tg3_writephy(tp, 0x10, 0x8411);
3822
3823         /* Enable auto-lock and comdet, select txclk for tx. */
3824         tg3_writephy(tp, 0x11, 0x0a10);
3825
3826         tg3_writephy(tp, 0x18, 0x00a0);
3827         tg3_writephy(tp, 0x16, 0x41ff);
3828
3829         /* Assert and deassert POR. */
3830         tg3_writephy(tp, 0x13, 0x0400);
3831         udelay(40);
3832         tg3_writephy(tp, 0x13, 0x0000);
3833
3834         tg3_writephy(tp, 0x11, 0x0a50);
3835         udelay(40);
3836         tg3_writephy(tp, 0x11, 0x0a10);
3837
3838         /* Wait for signal to stabilize */
3839         /* XXX schedule_timeout() ... */
3840         for (i = 0; i < 15000; i++)
3841                 udelay(10);
3842
3843         /* Deselect the channel register so we can read the PHYID
3844          * later.
3845          */
3846         tg3_writephy(tp, 0x10, 0x8011);
3847 }
3848
3849 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3850 {
3851         u16 flowctrl;
3852         u32 sg_dig_ctrl, sg_dig_status;
3853         u32 serdes_cfg, expected_sg_dig_ctrl;
3854         int workaround, port_a;
3855         int current_link_up;
3856
3857         serdes_cfg = 0;
3858         expected_sg_dig_ctrl = 0;
3859         workaround = 0;
3860         port_a = 1;
3861         current_link_up = 0;
3862
3863         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3864             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3865                 workaround = 1;
3866                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3867                         port_a = 0;
3868
3869                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3870                 /* preserve bits 20-23 for voltage regulator */
3871                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3872         }
3873
3874         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3875
3876         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3877                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3878                         if (workaround) {
3879                                 u32 val = serdes_cfg;
3880
3881                                 if (port_a)
3882                                         val |= 0xc010000;
3883                                 else
3884                                         val |= 0x4010000;
3885                                 tw32_f(MAC_SERDES_CFG, val);
3886                         }
3887
3888                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3889                 }
3890                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3891                         tg3_setup_flow_control(tp, 0, 0);
3892                         current_link_up = 1;
3893                 }
3894                 goto out;
3895         }
3896
3897         /* Want auto-negotiation.  */
3898         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3899
3900         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3901         if (flowctrl & ADVERTISE_1000XPAUSE)
3902                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3903         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3904                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3905
3906         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3907                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3908                     tp->serdes_counter &&
3909                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3910                                     MAC_STATUS_RCVD_CFG)) ==
3911                      MAC_STATUS_PCS_SYNCED)) {
3912                         tp->serdes_counter--;
3913                         current_link_up = 1;
3914                         goto out;
3915                 }
3916 restart_autoneg:
3917                 if (workaround)
3918                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3919                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3920                 udelay(5);
3921                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3922
3923                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3924                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3925         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3926                                  MAC_STATUS_SIGNAL_DET)) {
3927                 sg_dig_status = tr32(SG_DIG_STATUS);
3928                 mac_status = tr32(MAC_STATUS);
3929
3930                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3931                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3932                         u32 local_adv = 0, remote_adv = 0;
3933
3934                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3935                                 local_adv |= ADVERTISE_1000XPAUSE;
3936                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3937                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3938
3939                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3940                                 remote_adv |= LPA_1000XPAUSE;
3941                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3942                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3943
3944                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3945                         current_link_up = 1;
3946                         tp->serdes_counter = 0;
3947                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3948                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3949                         if (tp->serdes_counter)
3950                                 tp->serdes_counter--;
3951                         else {
3952                                 if (workaround) {
3953                                         u32 val = serdes_cfg;
3954
3955                                         if (port_a)
3956                                                 val |= 0xc010000;
3957                                         else
3958                                                 val |= 0x4010000;
3959
3960                                         tw32_f(MAC_SERDES_CFG, val);
3961                                 }
3962
3963                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3964                                 udelay(40);
3965
3966                                 /* Link parallel detection - link is up */
3967                                 /* only if we have PCS_SYNC and not */
3968                                 /* receiving config code words */
3969                                 mac_status = tr32(MAC_STATUS);
3970                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3971                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3972                                         tg3_setup_flow_control(tp, 0, 0);
3973                                         current_link_up = 1;
3974                                         tp->phy_flags |=
3975                                                 TG3_PHYFLG_PARALLEL_DETECT;
3976                                         tp->serdes_counter =
3977                                                 SERDES_PARALLEL_DET_TIMEOUT;
3978                                 } else
3979                                         goto restart_autoneg;
3980                         }
3981                 }
3982         } else {
3983                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3984                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3985         }
3986
3987 out:
3988         return current_link_up;
3989 }
3990
3991 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3992 {
3993         int current_link_up = 0;
3994
3995         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3996                 goto out;
3997
3998         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3999                 u32 txflags, rxflags;
4000                 int i;
4001
4002                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4003                         u32 local_adv = 0, remote_adv = 0;
4004
4005                         if (txflags & ANEG_CFG_PS1)
4006                                 local_adv |= ADVERTISE_1000XPAUSE;
4007                         if (txflags & ANEG_CFG_PS2)
4008                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
4009
4010                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
4011                                 remote_adv |= LPA_1000XPAUSE;
4012                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4013                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4014
4015                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4016
4017                         current_link_up = 1;
4018                 }
4019                 for (i = 0; i < 30; i++) {
4020                         udelay(20);
4021                         tw32_f(MAC_STATUS,
4022                                (MAC_STATUS_SYNC_CHANGED |
4023                                 MAC_STATUS_CFG_CHANGED));
4024                         udelay(40);
4025                         if ((tr32(MAC_STATUS) &
4026                              (MAC_STATUS_SYNC_CHANGED |
4027                               MAC_STATUS_CFG_CHANGED)) == 0)
4028                                 break;
4029                 }
4030
4031                 mac_status = tr32(MAC_STATUS);
4032                 if (current_link_up == 0 &&
4033                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4034                     !(mac_status & MAC_STATUS_RCVD_CFG))
4035                         current_link_up = 1;
4036         } else {
4037                 tg3_setup_flow_control(tp, 0, 0);
4038
4039                 /* Forcing 1000FD link up. */
4040                 current_link_up = 1;
4041
4042                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4043                 udelay(40);
4044
4045                 tw32_f(MAC_MODE, tp->mac_mode);
4046                 udelay(40);
4047         }
4048
4049 out:
4050         return current_link_up;
4051 }
4052
4053 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4054 {
4055         u32 orig_pause_cfg;
4056         u16 orig_active_speed;
4057         u8 orig_active_duplex;
4058         u32 mac_status;
4059         int current_link_up;
4060         int i;
4061
4062         orig_pause_cfg = tp->link_config.active_flowctrl;
4063         orig_active_speed = tp->link_config.active_speed;
4064         orig_active_duplex = tp->link_config.active_duplex;
4065
4066         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4067             netif_carrier_ok(tp->dev) &&
4068             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4069                 mac_status = tr32(MAC_STATUS);
4070                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4071                                MAC_STATUS_SIGNAL_DET |
4072                                MAC_STATUS_CFG_CHANGED |
4073                                MAC_STATUS_RCVD_CFG);
4074                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4075                                    MAC_STATUS_SIGNAL_DET)) {
4076                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4077                                             MAC_STATUS_CFG_CHANGED));
4078                         return 0;
4079                 }
4080         }
4081
4082         tw32_f(MAC_TX_AUTO_NEG, 0);
4083
4084         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4085         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4086         tw32_f(MAC_MODE, tp->mac_mode);
4087         udelay(40);
4088
4089         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4090                 tg3_init_bcm8002(tp);
4091
4092         /* Enable link change event even when serdes polling.  */
4093         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4094         udelay(40);
4095
4096         current_link_up = 0;
4097         mac_status = tr32(MAC_STATUS);
4098
4099         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4100                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4101         else
4102                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4103
4104         tp->napi[0].hw_status->status =
4105                 (SD_STATUS_UPDATED |
4106                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4107
4108         for (i = 0; i < 100; i++) {
4109                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4110                                     MAC_STATUS_CFG_CHANGED));
4111                 udelay(5);
4112                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4113                                          MAC_STATUS_CFG_CHANGED |
4114                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4115                         break;
4116         }
4117
4118         mac_status = tr32(MAC_STATUS);
4119         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4120                 current_link_up = 0;
4121                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4122                     tp->serdes_counter == 0) {
4123                         tw32_f(MAC_MODE, (tp->mac_mode |
4124                                           MAC_MODE_SEND_CONFIGS));
4125                         udelay(1);
4126                         tw32_f(MAC_MODE, tp->mac_mode);
4127                 }
4128         }
4129
4130         if (current_link_up == 1) {
4131                 tp->link_config.active_speed = SPEED_1000;
4132                 tp->link_config.active_duplex = DUPLEX_FULL;
4133                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4134                                     LED_CTRL_LNKLED_OVERRIDE |
4135                                     LED_CTRL_1000MBPS_ON));
4136         } else {
4137                 tp->link_config.active_speed = SPEED_INVALID;
4138                 tp->link_config.active_duplex = DUPLEX_INVALID;
4139                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4140                                     LED_CTRL_LNKLED_OVERRIDE |
4141                                     LED_CTRL_TRAFFIC_OVERRIDE));
4142         }
4143
4144         if (current_link_up != netif_carrier_ok(tp->dev)) {
4145                 if (current_link_up)
4146                         netif_carrier_on(tp->dev);
4147                 else
4148                         netif_carrier_off(tp->dev);
4149                 tg3_link_report(tp);
4150         } else {
4151                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4152                 if (orig_pause_cfg != now_pause_cfg ||
4153                     orig_active_speed != tp->link_config.active_speed ||
4154                     orig_active_duplex != tp->link_config.active_duplex)
4155                         tg3_link_report(tp);
4156         }
4157
4158         return 0;
4159 }
4160
4161 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4162 {
4163         int current_link_up, err = 0;
4164         u32 bmsr, bmcr;
4165         u16 current_speed;
4166         u8 current_duplex;
4167         u32 local_adv, remote_adv;
4168
4169         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4170         tw32_f(MAC_MODE, tp->mac_mode);
4171         udelay(40);
4172
4173         tw32(MAC_EVENT, 0);
4174
4175         tw32_f(MAC_STATUS,
4176              (MAC_STATUS_SYNC_CHANGED |
4177               MAC_STATUS_CFG_CHANGED |
4178               MAC_STATUS_MI_COMPLETION |
4179               MAC_STATUS_LNKSTATE_CHANGED));
4180         udelay(40);
4181
4182         if (force_reset)
4183                 tg3_phy_reset(tp);
4184
4185         current_link_up = 0;
4186         current_speed = SPEED_INVALID;
4187         current_duplex = DUPLEX_INVALID;
4188
4189         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4190         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4191         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4192                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4193                         bmsr |= BMSR_LSTATUS;
4194                 else
4195                         bmsr &= ~BMSR_LSTATUS;
4196         }
4197
4198         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4199
4200         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4201             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4202                 /* do nothing, just check for link up at the end */
4203         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4204                 u32 adv, new_adv;
4205
4206                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4207                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4208                                   ADVERTISE_1000XPAUSE |
4209                                   ADVERTISE_1000XPSE_ASYM |
4210                                   ADVERTISE_SLCT);
4211
4212                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4213
4214                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4215                         new_adv |= ADVERTISE_1000XHALF;
4216                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4217                         new_adv |= ADVERTISE_1000XFULL;
4218
4219                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4220                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4221                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4222                         tg3_writephy(tp, MII_BMCR, bmcr);
4223
4224                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4225                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4226                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4227
4228                         return err;
4229                 }
4230         } else {
4231                 u32 new_bmcr;
4232
4233                 bmcr &= ~BMCR_SPEED1000;
4234                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4235
4236                 if (tp->link_config.duplex == DUPLEX_FULL)
4237                         new_bmcr |= BMCR_FULLDPLX;
4238
4239                 if (new_bmcr != bmcr) {
4240                         /* BMCR_SPEED1000 is a reserved bit that needs
4241                          * to be set on write.
4242                          */
4243                         new_bmcr |= BMCR_SPEED1000;
4244
4245                         /* Force a linkdown */
4246                         if (netif_carrier_ok(tp->dev)) {
4247                                 u32 adv;
4248
4249                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4250                                 adv &= ~(ADVERTISE_1000XFULL |
4251                                          ADVERTISE_1000XHALF |
4252                                          ADVERTISE_SLCT);
4253                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4254                                 tg3_writephy(tp, MII_BMCR, bmcr |
4255                                                            BMCR_ANRESTART |
4256                                                            BMCR_ANENABLE);
4257                                 udelay(10);
4258                                 netif_carrier_off(tp->dev);
4259                         }
4260                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4261                         bmcr = new_bmcr;
4262                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4263                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4264                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4265                             ASIC_REV_5714) {
4266                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4267                                         bmsr |= BMSR_LSTATUS;
4268                                 else
4269                                         bmsr &= ~BMSR_LSTATUS;
4270                         }
4271                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4272                 }
4273         }
4274
4275         if (bmsr & BMSR_LSTATUS) {
4276                 current_speed = SPEED_1000;
4277                 current_link_up = 1;
4278                 if (bmcr & BMCR_FULLDPLX)
4279                         current_duplex = DUPLEX_FULL;
4280                 else
4281                         current_duplex = DUPLEX_HALF;
4282
4283                 local_adv = 0;
4284                 remote_adv = 0;
4285
4286                 if (bmcr & BMCR_ANENABLE) {
4287                         u32 common;
4288
4289                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4290                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4291                         common = local_adv & remote_adv;
4292                         if (common & (ADVERTISE_1000XHALF |
4293                                       ADVERTISE_1000XFULL)) {
4294                                 if (common & ADVERTISE_1000XFULL)
4295                                         current_duplex = DUPLEX_FULL;
4296                                 else
4297                                         current_duplex = DUPLEX_HALF;
4298                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4299                                 /* Link is up via parallel detect */
4300                         } else {
4301                                 current_link_up = 0;
4302                         }
4303                 }
4304         }
4305
4306         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4307                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4308
4309         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4310         if (tp->link_config.active_duplex == DUPLEX_HALF)
4311                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4312
4313         tw32_f(MAC_MODE, tp->mac_mode);
4314         udelay(40);
4315
4316         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4317
4318         tp->link_config.active_speed = current_speed;
4319         tp->link_config.active_duplex = current_duplex;
4320
4321         if (current_link_up != netif_carrier_ok(tp->dev)) {
4322                 if (current_link_up)
4323                         netif_carrier_on(tp->dev);
4324                 else {
4325                         netif_carrier_off(tp->dev);
4326                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4327                 }
4328                 tg3_link_report(tp);
4329         }
4330         return err;
4331 }
4332
4333 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4334 {
4335         if (tp->serdes_counter) {
4336                 /* Give autoneg time to complete. */
4337                 tp->serdes_counter--;
4338                 return;
4339         }
4340
4341         if (!netif_carrier_ok(tp->dev) &&
4342             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4343                 u32 bmcr;
4344
4345                 tg3_readphy(tp, MII_BMCR, &bmcr);
4346                 if (bmcr & BMCR_ANENABLE) {
4347                         u32 phy1, phy2;
4348
4349                         /* Select shadow register 0x1f */
4350                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4351                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4352
4353                         /* Select expansion interrupt status register */
4354                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4355                                          MII_TG3_DSP_EXP1_INT_STAT);
4356                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4357                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4358
4359                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4360                                 /* We have signal detect and not receiving
4361                                  * config code words, link is up by parallel
4362                                  * detection.
4363                                  */
4364
4365                                 bmcr &= ~BMCR_ANENABLE;
4366                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4367                                 tg3_writephy(tp, MII_BMCR, bmcr);
4368                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4369                         }
4370                 }
4371         } else if (netif_carrier_ok(tp->dev) &&
4372                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4373                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4374                 u32 phy2;
4375
4376                 /* Select expansion interrupt status register */
4377                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4378                                  MII_TG3_DSP_EXP1_INT_STAT);
4379                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4380                 if (phy2 & 0x20) {
4381                         u32 bmcr;
4382
4383                         /* Config code words received, turn on autoneg. */
4384                         tg3_readphy(tp, MII_BMCR, &bmcr);
4385                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4386
4387                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4388
4389                 }
4390         }
4391 }
4392
4393 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4394 {
4395         u32 val;
4396         int err;
4397
4398         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4399                 err = tg3_setup_fiber_phy(tp, force_reset);
4400         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4401                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4402         else
4403                 err = tg3_setup_copper_phy(tp, force_reset);
4404
4405         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4406                 u32 scale;
4407
4408                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4409                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4410                         scale = 65;
4411                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4412                         scale = 6;
4413                 else
4414                         scale = 12;
4415
4416                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4417                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4418                 tw32(GRC_MISC_CFG, val);
4419         }
4420
4421         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4422               (6 << TX_LENGTHS_IPG_SHIFT);
4423         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
4424                 val |= tr32(MAC_TX_LENGTHS) &
4425                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
4426                         TX_LENGTHS_CNT_DWN_VAL_MSK);
4427
4428         if (tp->link_config.active_speed == SPEED_1000 &&
4429             tp->link_config.active_duplex == DUPLEX_HALF)
4430                 tw32(MAC_TX_LENGTHS, val |
4431                      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
4432         else
4433                 tw32(MAC_TX_LENGTHS, val |
4434                      (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
4435
4436         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4437                 if (netif_carrier_ok(tp->dev)) {
4438                         tw32(HOSTCC_STAT_COAL_TICKS,
4439                              tp->coal.stats_block_coalesce_usecs);
4440                 } else {
4441                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4442                 }
4443         }
4444
4445         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4446                 val = tr32(PCIE_PWR_MGMT_THRESH);
4447                 if (!netif_carrier_ok(tp->dev))
4448                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4449                               tp->pwrmgmt_thresh;
4450                 else
4451                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4452                 tw32(PCIE_PWR_MGMT_THRESH, val);
4453         }
4454
4455         return err;
4456 }
4457
4458 static inline int tg3_irq_sync(struct tg3 *tp)
4459 {
4460         return tp->irq_sync;
4461 }
4462
4463 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
4464 {
4465         int i;
4466
4467         dst = (u32 *)((u8 *)dst + off);
4468         for (i = 0; i < len; i += sizeof(u32))
4469                 *dst++ = tr32(off + i);
4470 }
4471
4472 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
4473 {
4474         tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
4475         tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
4476         tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
4477         tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
4478         tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
4479         tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
4480         tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
4481         tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
4482         tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
4483         tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
4484         tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
4485         tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
4486         tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
4487         tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
4488         tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
4489         tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
4490         tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
4491         tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
4492         tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
4493
4494         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)
4495                 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
4496
4497         tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
4498         tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
4499         tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
4500         tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
4501         tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
4502         tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
4503         tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
4504         tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
4505
4506         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4507                 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
4508                 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
4509                 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
4510         }
4511
4512         tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
4513         tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
4514         tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
4515         tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
4516         tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
4517
4518         if (tp->tg3_flags & TG3_FLAG_NVRAM)
4519                 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
4520 }
4521
4522 static void tg3_dump_state(struct tg3 *tp)
4523 {
4524         int i;
4525         u32 *regs;
4526
4527         regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
4528         if (!regs) {
4529                 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
4530                 return;
4531         }
4532
4533         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4534                 /* Read up to but not including private PCI registers */
4535                 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
4536                         regs[i / sizeof(u32)] = tr32(i);
4537         } else
4538                 tg3_dump_legacy_regs(tp, regs);
4539
4540         for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
4541                 if (!regs[i + 0] && !regs[i + 1] &&
4542                     !regs[i + 2] && !regs[i + 3])
4543                         continue;
4544
4545                 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
4546                            i * 4,
4547                            regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
4548         }
4549
4550         kfree(regs);
4551
4552         for (i = 0; i < tp->irq_cnt; i++) {
4553                 struct tg3_napi *tnapi = &tp->napi[i];
4554
4555                 /* SW status block */
4556                 netdev_err(tp->dev,
4557                          "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
4558                            i,
4559                            tnapi->hw_status->status,
4560                            tnapi->hw_status->status_tag,
4561                            tnapi->hw_status->rx_jumbo_consumer,
4562                            tnapi->hw_status->rx_consumer,
4563                            tnapi->hw_status->rx_mini_consumer,
4564                            tnapi->hw_status->idx[0].rx_producer,
4565                            tnapi->hw_status->idx[0].tx_consumer);
4566
4567                 netdev_err(tp->dev,
4568                 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
4569                            i,
4570                            tnapi->last_tag, tnapi->last_irq_tag,
4571                            tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
4572                            tnapi->rx_rcb_ptr,
4573                            tnapi->prodring.rx_std_prod_idx,
4574                            tnapi->prodring.rx_std_cons_idx,
4575                            tnapi->prodring.rx_jmb_prod_idx,
4576                            tnapi->prodring.rx_jmb_cons_idx);
4577         }
4578 }
4579
4580 /* This is called whenever we suspect that the system chipset is re-
4581  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4582  * is bogus tx completions. We try to recover by setting the
4583  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4584  * in the workqueue.
4585  */
4586 static void tg3_tx_recover(struct tg3 *tp)
4587 {
4588         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4589                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4590
4591         netdev_warn(tp->dev,
4592                     "The system may be re-ordering memory-mapped I/O "
4593                     "cycles to the network device, attempting to recover. "
4594                     "Please report the problem to the driver maintainer "
4595                     "and include system chipset information.\n");
4596
4597         spin_lock(&tp->lock);
4598         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4599         spin_unlock(&tp->lock);
4600 }
4601
4602 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4603 {
4604         /* Tell compiler to fetch tx indices from memory. */
4605         barrier();
4606         return tnapi->tx_pending -
4607                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4608 }
4609
4610 /* Tigon3 never reports partial packet sends.  So we do not
4611  * need special logic to handle SKBs that have not had all
4612  * of their frags sent yet, like SunGEM does.
4613  */
4614 static void tg3_tx(struct tg3_napi *tnapi)
4615 {
4616         struct tg3 *tp = tnapi->tp;
4617         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4618         u32 sw_idx = tnapi->tx_cons;
4619         struct netdev_queue *txq;
4620         int index = tnapi - tp->napi;
4621
4622         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4623                 index--;
4624
4625         txq = netdev_get_tx_queue(tp->dev, index);
4626
4627         while (sw_idx != hw_idx) {
4628                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4629                 struct sk_buff *skb = ri->skb;
4630                 int i, tx_bug = 0;
4631
4632                 if (unlikely(skb == NULL)) {
4633                         tg3_tx_recover(tp);
4634                         return;
4635                 }
4636
4637                 pci_unmap_single(tp->pdev,
4638                                  dma_unmap_addr(ri, mapping),
4639                                  skb_headlen(skb),
4640                                  PCI_DMA_TODEVICE);
4641
4642                 ri->skb = NULL;
4643
4644                 sw_idx = NEXT_TX(sw_idx);
4645
4646                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4647                         ri = &tnapi->tx_buffers[sw_idx];
4648                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4649                                 tx_bug = 1;
4650
4651                         pci_unmap_page(tp->pdev,
4652                                        dma_unmap_addr(ri, mapping),
4653                                        skb_shinfo(skb)->frags[i].size,
4654                                        PCI_DMA_TODEVICE);
4655                         sw_idx = NEXT_TX(sw_idx);
4656                 }
4657
4658                 dev_kfree_skb(skb);
4659
4660                 if (unlikely(tx_bug)) {
4661                         tg3_tx_recover(tp);
4662                         return;
4663                 }
4664         }
4665
4666         tnapi->tx_cons = sw_idx;
4667
4668         /* Need to make the tx_cons update visible to tg3_start_xmit()
4669          * before checking for netif_queue_stopped().  Without the
4670          * memory barrier, there is a small possibility that tg3_start_xmit()
4671          * will miss it and cause the queue to be stopped forever.
4672          */
4673         smp_mb();
4674
4675         if (unlikely(netif_tx_queue_stopped(txq) &&
4676                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4677                 __netif_tx_lock(txq, smp_processor_id());
4678                 if (netif_tx_queue_stopped(txq) &&
4679                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4680                         netif_tx_wake_queue(txq);
4681                 __netif_tx_unlock(txq);
4682         }
4683 }
4684
4685 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4686 {
4687         if (!ri->skb)
4688                 return;
4689
4690         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4691                          map_sz, PCI_DMA_FROMDEVICE);
4692         dev_kfree_skb_any(ri->skb);
4693         ri->skb = NULL;
4694 }
4695
4696 /* Returns size of skb allocated or < 0 on error.
4697  *
4698  * We only need to fill in the address because the other members
4699  * of the RX descriptor are invariant, see tg3_init_rings.
4700  *
4701  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4702  * posting buffers we only dirty the first cache line of the RX
4703  * descriptor (containing the address).  Whereas for the RX status
4704  * buffers the cpu only reads the last cacheline of the RX descriptor
4705  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4706  */
4707 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4708                             u32 opaque_key, u32 dest_idx_unmasked)
4709 {
4710         struct tg3_rx_buffer_desc *desc;
4711         struct ring_info *map;
4712         struct sk_buff *skb;
4713         dma_addr_t mapping;
4714         int skb_size, dest_idx;
4715
4716         switch (opaque_key) {
4717         case RXD_OPAQUE_RING_STD:
4718                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4719                 desc = &tpr->rx_std[dest_idx];
4720                 map = &tpr->rx_std_buffers[dest_idx];
4721                 skb_size = tp->rx_pkt_map_sz;
4722                 break;
4723
4724         case RXD_OPAQUE_RING_JUMBO:
4725                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4726                 desc = &tpr->rx_jmb[dest_idx].std;
4727                 map = &tpr->rx_jmb_buffers[dest_idx];
4728                 skb_size = TG3_RX_JMB_MAP_SZ;
4729                 break;
4730
4731         default:
4732                 return -EINVAL;
4733         }
4734
4735         /* Do not overwrite any of the map or rp information
4736          * until we are sure we can commit to a new buffer.
4737          *
4738          * Callers depend upon this behavior and assume that
4739          * we leave everything unchanged if we fail.
4740          */
4741         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4742         if (skb == NULL)
4743                 return -ENOMEM;
4744
4745         skb_reserve(skb, tp->rx_offset);
4746
4747         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4748                                  PCI_DMA_FROMDEVICE);
4749         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4750                 dev_kfree_skb(skb);
4751                 return -EIO;
4752         }
4753
4754         map->skb = skb;
4755         dma_unmap_addr_set(map, mapping, mapping);
4756
4757         desc->addr_hi = ((u64)mapping >> 32);
4758         desc->addr_lo = ((u64)mapping & 0xffffffff);
4759
4760         return skb_size;
4761 }
4762
4763 /* We only need to move over in the address because the other
4764  * members of the RX descriptor are invariant.  See notes above
4765  * tg3_alloc_rx_skb for full details.
4766  */
4767 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4768                            struct tg3_rx_prodring_set *dpr,
4769                            u32 opaque_key, int src_idx,
4770                            u32 dest_idx_unmasked)
4771 {
4772         struct tg3 *tp = tnapi->tp;
4773         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4774         struct ring_info *src_map, *dest_map;
4775         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4776         int dest_idx;
4777
4778         switch (opaque_key) {
4779         case RXD_OPAQUE_RING_STD:
4780                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4781                 dest_desc = &dpr->rx_std[dest_idx];
4782                 dest_map = &dpr->rx_std_buffers[dest_idx];
4783                 src_desc = &spr->rx_std[src_idx];
4784                 src_map = &spr->rx_std_buffers[src_idx];
4785                 break;
4786
4787         case RXD_OPAQUE_RING_JUMBO:
4788                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4789                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4790                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4791                 src_desc = &spr->rx_jmb[src_idx].std;
4792                 src_map = &spr->rx_jmb_buffers[src_idx];
4793                 break;
4794
4795         default:
4796                 return;
4797         }
4798
4799         dest_map->skb = src_map->skb;
4800         dma_unmap_addr_set(dest_map, mapping,
4801                            dma_unmap_addr(src_map, mapping));
4802         dest_desc->addr_hi = src_desc->addr_hi;
4803         dest_desc->addr_lo = src_desc->addr_lo;
4804
4805         /* Ensure that the update to the skb happens after the physical
4806          * addresses have been transferred to the new BD location.
4807          */
4808         smp_wmb();
4809
4810         src_map->skb = NULL;
4811 }
4812
4813 /* The RX ring scheme is composed of multiple rings which post fresh
4814  * buffers to the chip, and one special ring the chip uses to report
4815  * status back to the host.
4816  *
4817  * The special ring reports the status of received packets to the
4818  * host.  The chip does not write into the original descriptor the
4819  * RX buffer was obtained from.  The chip simply takes the original
4820  * descriptor as provided by the host, updates the status and length
4821  * field, then writes this into the next status ring entry.
4822  *
4823  * Each ring the host uses to post buffers to the chip is described
4824  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4825  * it is first placed into the on-chip ram.  When the packet's length
4826  * is known, it walks down the TG3_BDINFO entries to select the ring.
4827  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4828  * which is within the range of the new packet's length is chosen.
4829  *
4830  * The "separate ring for rx status" scheme may sound queer, but it makes
4831  * sense from a cache coherency perspective.  If only the host writes
4832  * to the buffer post rings, and only the chip writes to the rx status
4833  * rings, then cache lines never move beyond shared-modified state.
4834  * If both the host and chip were to write into the same ring, cache line
4835  * eviction could occur since both entities want it in an exclusive state.
4836  */
4837 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4838 {
4839         struct tg3 *tp = tnapi->tp;
4840         u32 work_mask, rx_std_posted = 0;
4841         u32 std_prod_idx, jmb_prod_idx;
4842         u32 sw_idx = tnapi->rx_rcb_ptr;
4843         u16 hw_idx;
4844         int received;
4845         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4846
4847         hw_idx = *(tnapi->rx_rcb_prod_idx);
4848         /*
4849          * We need to order the read of hw_idx and the read of
4850          * the opaque cookie.
4851          */
4852         rmb();
4853         work_mask = 0;
4854         received = 0;
4855         std_prod_idx = tpr->rx_std_prod_idx;
4856         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4857         while (sw_idx != hw_idx && budget > 0) {
4858                 struct ring_info *ri;
4859                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4860                 unsigned int len;
4861                 struct sk_buff *skb;
4862                 dma_addr_t dma_addr;
4863                 u32 opaque_key, desc_idx, *post_ptr;
4864
4865                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4866                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4867                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4868                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4869                         dma_addr = dma_unmap_addr(ri, mapping);
4870                         skb = ri->skb;
4871                         post_ptr = &std_prod_idx;
4872                         rx_std_posted++;
4873                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4874                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4875                         dma_addr = dma_unmap_addr(ri, mapping);
4876                         skb = ri->skb;
4877                         post_ptr = &jmb_prod_idx;
4878                 } else
4879                         goto next_pkt_nopost;
4880
4881                 work_mask |= opaque_key;
4882
4883                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4884                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4885                 drop_it:
4886                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4887                                        desc_idx, *post_ptr);
4888                 drop_it_no_recycle:
4889                         /* Other statistics kept track of by card. */
4890                         tp->rx_dropped++;
4891                         goto next_pkt;
4892                 }
4893
4894                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4895                       ETH_FCS_LEN;
4896
4897                 if (len > TG3_RX_COPY_THRESH(tp)) {
4898                         int skb_size;
4899
4900                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4901                                                     *post_ptr);
4902                         if (skb_size < 0)
4903                                 goto drop_it;
4904
4905                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4906                                          PCI_DMA_FROMDEVICE);
4907
4908                         /* Ensure that the update to the skb happens
4909                          * after the usage of the old DMA mapping.
4910                          */
4911                         smp_wmb();
4912
4913                         ri->skb = NULL;
4914
4915                         skb_put(skb, len);
4916                 } else {
4917                         struct sk_buff *copy_skb;
4918
4919                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4920                                        desc_idx, *post_ptr);
4921
4922                         copy_skb = netdev_alloc_skb(tp->dev, len +
4923                                                     TG3_RAW_IP_ALIGN);
4924                         if (copy_skb == NULL)
4925                                 goto drop_it_no_recycle;
4926
4927                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4928                         skb_put(copy_skb, len);
4929                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4930                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4931                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4932
4933                         /* We'll reuse the original ring buffer. */
4934                         skb = copy_skb;
4935                 }
4936
4937                 if ((tp->dev->features & NETIF_F_RXCSUM) &&
4938                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4939                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4940                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4941                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4942                 else
4943                         skb_checksum_none_assert(skb);
4944
4945                 skb->protocol = eth_type_trans(skb, tp->dev);
4946
4947                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4948                     skb->protocol != htons(ETH_P_8021Q)) {
4949                         dev_kfree_skb(skb);
4950                         goto drop_it_no_recycle;
4951                 }
4952
4953                 if (desc->type_flags & RXD_FLAG_VLAN &&
4954                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4955                         __vlan_hwaccel_put_tag(skb,
4956                                                desc->err_vlan & RXD_VLAN_MASK);
4957
4958                 napi_gro_receive(&tnapi->napi, skb);
4959
4960                 received++;
4961                 budget--;
4962
4963 next_pkt:
4964                 (*post_ptr)++;
4965
4966                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4967                         tpr->rx_std_prod_idx = std_prod_idx &
4968                                                tp->rx_std_ring_mask;
4969                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4970                                      tpr->rx_std_prod_idx);
4971                         work_mask &= ~RXD_OPAQUE_RING_STD;
4972                         rx_std_posted = 0;
4973                 }
4974 next_pkt_nopost:
4975                 sw_idx++;
4976                 sw_idx &= tp->rx_ret_ring_mask;
4977
4978                 /* Refresh hw_idx to see if there is new work */
4979                 if (sw_idx == hw_idx) {
4980                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4981                         rmb();
4982                 }
4983         }
4984
4985         /* ACK the status ring. */
4986         tnapi->rx_rcb_ptr = sw_idx;
4987         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4988
4989         /* Refill RX ring(s). */
4990         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4991                 if (work_mask & RXD_OPAQUE_RING_STD) {
4992                         tpr->rx_std_prod_idx = std_prod_idx &
4993                                                tp->rx_std_ring_mask;
4994                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4995                                      tpr->rx_std_prod_idx);
4996                 }
4997                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4998                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4999                                                tp->rx_jmb_ring_mask;
5000                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5001                                      tpr->rx_jmb_prod_idx);
5002                 }
5003                 mmiowb();
5004         } else if (work_mask) {
5005                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5006                  * updated before the producer indices can be updated.
5007                  */
5008                 smp_wmb();
5009
5010                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5011                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5012
5013                 if (tnapi != &tp->napi[1])
5014                         napi_schedule(&tp->napi[1].napi);
5015         }
5016
5017         return received;
5018 }
5019
5020 static void tg3_poll_link(struct tg3 *tp)
5021 {
5022         /* handle link change and other phy events */
5023         if (!(tp->tg3_flags &
5024               (TG3_FLAG_USE_LINKCHG_REG |
5025                TG3_FLAG_POLL_SERDES))) {
5026                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5027
5028                 if (sblk->status & SD_STATUS_LINK_CHG) {
5029                         sblk->status = SD_STATUS_UPDATED |
5030                                        (sblk->status & ~SD_STATUS_LINK_CHG);
5031                         spin_lock(&tp->lock);
5032                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
5033                                 tw32_f(MAC_STATUS,
5034                                      (MAC_STATUS_SYNC_CHANGED |
5035                                       MAC_STATUS_CFG_CHANGED |
5036                                       MAC_STATUS_MI_COMPLETION |
5037                                       MAC_STATUS_LNKSTATE_CHANGED));
5038                                 udelay(40);
5039                         } else
5040                                 tg3_setup_phy(tp, 0);
5041                         spin_unlock(&tp->lock);
5042                 }
5043         }
5044 }
5045
5046 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5047                                 struct tg3_rx_prodring_set *dpr,
5048                                 struct tg3_rx_prodring_set *spr)
5049 {
5050         u32 si, di, cpycnt, src_prod_idx;
5051         int i, err = 0;
5052
5053         while (1) {
5054                 src_prod_idx = spr->rx_std_prod_idx;
5055
5056                 /* Make sure updates to the rx_std_buffers[] entries and the
5057                  * standard producer index are seen in the correct order.
5058                  */
5059                 smp_rmb();
5060
5061                 if (spr->rx_std_cons_idx == src_prod_idx)
5062                         break;
5063
5064                 if (spr->rx_std_cons_idx < src_prod_idx)
5065                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5066                 else
5067                         cpycnt = tp->rx_std_ring_mask + 1 -
5068                                  spr->rx_std_cons_idx;
5069
5070                 cpycnt = min(cpycnt,
5071                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5072
5073                 si = spr->rx_std_cons_idx;
5074                 di = dpr->rx_std_prod_idx;
5075
5076                 for (i = di; i < di + cpycnt; i++) {
5077                         if (dpr->rx_std_buffers[i].skb) {
5078                                 cpycnt = i - di;
5079                                 err = -ENOSPC;
5080                                 break;
5081                         }
5082                 }
5083
5084                 if (!cpycnt)
5085                         break;
5086
5087                 /* Ensure that updates to the rx_std_buffers ring and the
5088                  * shadowed hardware producer ring from tg3_recycle_skb() are
5089                  * ordered correctly WRT the skb check above.
5090                  */
5091                 smp_rmb();
5092
5093                 memcpy(&dpr->rx_std_buffers[di],
5094                        &spr->rx_std_buffers[si],
5095                        cpycnt * sizeof(struct ring_info));
5096
5097                 for (i = 0; i < cpycnt; i++, di++, si++) {
5098                         struct tg3_rx_buffer_desc *sbd, *dbd;
5099                         sbd = &spr->rx_std[si];
5100                         dbd = &dpr->rx_std[di];
5101                         dbd->addr_hi = sbd->addr_hi;
5102                         dbd->addr_lo = sbd->addr_lo;
5103                 }
5104
5105                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5106                                        tp->rx_std_ring_mask;
5107                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5108                                        tp->rx_std_ring_mask;
5109         }
5110
5111         while (1) {
5112                 src_prod_idx = spr->rx_jmb_prod_idx;
5113
5114                 /* Make sure updates to the rx_jmb_buffers[] entries and
5115                  * the jumbo producer index are seen in the correct order.
5116                  */
5117                 smp_rmb();
5118
5119                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5120                         break;
5121
5122                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5123                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5124                 else
5125                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5126                                  spr->rx_jmb_cons_idx;
5127
5128                 cpycnt = min(cpycnt,
5129                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5130
5131                 si = spr->rx_jmb_cons_idx;
5132                 di = dpr->rx_jmb_prod_idx;
5133
5134                 for (i = di; i < di + cpycnt; i++) {
5135                         if (dpr->rx_jmb_buffers[i].skb) {
5136                                 cpycnt = i - di;
5137                                 err = -ENOSPC;
5138                                 break;
5139                         }
5140                 }
5141
5142                 if (!cpycnt)
5143                         break;
5144
5145                 /* Ensure that updates to the rx_jmb_buffers ring and the
5146                  * shadowed hardware producer ring from tg3_recycle_skb() are
5147                  * ordered correctly WRT the skb check above.
5148                  */
5149                 smp_rmb();
5150
5151                 memcpy(&dpr->rx_jmb_buffers[di],
5152                        &spr->rx_jmb_buffers[si],
5153                        cpycnt * sizeof(struct ring_info));
5154
5155                 for (i = 0; i < cpycnt; i++, di++, si++) {
5156                         struct tg3_rx_buffer_desc *sbd, *dbd;
5157                         sbd = &spr->rx_jmb[si].std;
5158                         dbd = &dpr->rx_jmb[di].std;
5159                         dbd->addr_hi = sbd->addr_hi;
5160                         dbd->addr_lo = sbd->addr_lo;
5161                 }
5162
5163                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5164                                        tp->rx_jmb_ring_mask;
5165                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5166                                        tp->rx_jmb_ring_mask;
5167         }
5168
5169         return err;
5170 }
5171
5172 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5173 {
5174         struct tg3 *tp = tnapi->tp;
5175
5176         /* run TX completion thread */
5177         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5178                 tg3_tx(tnapi);
5179                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5180                         return work_done;
5181         }
5182
5183         /* run RX thread, within the bounds set by NAPI.
5184          * All RX "locking" is done by ensuring outside
5185          * code synchronizes with tg3->napi.poll()
5186          */
5187         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5188                 work_done += tg3_rx(tnapi, budget - work_done);
5189
5190         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5191                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5192                 int i, err = 0;
5193                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5194                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5195
5196                 for (i = 1; i < tp->irq_cnt; i++)
5197                         err |= tg3_rx_prodring_xfer(tp, dpr,
5198                                                     &tp->napi[i].prodring);
5199
5200                 wmb();
5201
5202                 if (std_prod_idx != dpr->rx_std_prod_idx)
5203                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5204                                      dpr->rx_std_prod_idx);
5205
5206                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5207                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5208                                      dpr->rx_jmb_prod_idx);
5209
5210                 mmiowb();
5211
5212                 if (err)
5213                         tw32_f(HOSTCC_MODE, tp->coal_now);
5214         }
5215
5216         return work_done;
5217 }
5218
5219 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5220 {
5221         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5222         struct tg3 *tp = tnapi->tp;
5223         int work_done = 0;
5224         struct tg3_hw_status *sblk = tnapi->hw_status;
5225
5226         while (1) {
5227                 work_done = tg3_poll_work(tnapi, work_done, budget);
5228
5229                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5230                         goto tx_recovery;
5231
5232                 if (unlikely(work_done >= budget))
5233                         break;
5234
5235                 /* tp->last_tag is used in tg3_int_reenable() below
5236                  * to tell the hw how much work has been processed,
5237                  * so we must read it before checking for more work.
5238                  */
5239                 tnapi->last_tag = sblk->status_tag;
5240                 tnapi->last_irq_tag = tnapi->last_tag;
5241                 rmb();
5242
5243                 /* check for RX/TX work to do */
5244                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5245                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5246                         napi_complete(napi);
5247                         /* Reenable interrupts. */
5248                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5249                         mmiowb();
5250                         break;
5251                 }
5252         }
5253
5254         return work_done;
5255
5256 tx_recovery:
5257         /* work_done is guaranteed to be less than budget. */
5258         napi_complete(napi);
5259         schedule_work(&tp->reset_task);
5260         return work_done;
5261 }
5262
5263 static void tg3_process_error(struct tg3 *tp)
5264 {
5265         u32 val;
5266         bool real_error = false;
5267
5268         if (tp->tg3_flags & TG3_FLAG_ERROR_PROCESSED)
5269                 return;
5270
5271         /* Check Flow Attention register */
5272         val = tr32(HOSTCC_FLOW_ATTN);
5273         if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5274                 netdev_err(tp->dev, "FLOW Attention error.  Resetting chip.\n");
5275                 real_error = true;
5276         }
5277
5278         if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
5279                 netdev_err(tp->dev, "MSI Status error.  Resetting chip.\n");
5280                 real_error = true;
5281         }
5282
5283         if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
5284                 netdev_err(tp->dev, "DMA Status error.  Resetting chip.\n");
5285                 real_error = true;
5286         }
5287
5288         if (!real_error)
5289                 return;
5290
5291         tg3_dump_state(tp);
5292
5293         tp->tg3_flags |= TG3_FLAG_ERROR_PROCESSED;
5294         schedule_work(&tp->reset_task);
5295 }
5296
5297 static int tg3_poll(struct napi_struct *napi, int budget)
5298 {
5299         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5300         struct tg3 *tp = tnapi->tp;
5301         int work_done = 0;
5302         struct tg3_hw_status *sblk = tnapi->hw_status;
5303
5304         while (1) {
5305                 if (sblk->status & SD_STATUS_ERROR)
5306                         tg3_process_error(tp);
5307
5308                 tg3_poll_link(tp);
5309
5310                 work_done = tg3_poll_work(tnapi, work_done, budget);
5311
5312                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5313                         goto tx_recovery;
5314
5315                 if (unlikely(work_done >= budget))
5316                         break;
5317
5318                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5319                         /* tp->last_tag is used in tg3_int_reenable() below
5320                          * to tell the hw how much work has been processed,
5321                          * so we must read it before checking for more work.
5322                          */
5323                         tnapi->last_tag = sblk->status_tag;
5324                         tnapi->last_irq_tag = tnapi->last_tag;
5325                         rmb();
5326                 } else
5327                         sblk->status &= ~SD_STATUS_UPDATED;
5328
5329                 if (likely(!tg3_has_work(tnapi))) {
5330                         napi_complete(napi);
5331                         tg3_int_reenable(tnapi);
5332                         break;
5333                 }
5334         }
5335
5336         return work_done;
5337
5338 tx_recovery:
5339         /* work_done is guaranteed to be less than budget. */
5340         napi_complete(napi);
5341         schedule_work(&tp->reset_task);
5342         return work_done;
5343 }
5344
5345 static void tg3_napi_disable(struct tg3 *tp)
5346 {
5347         int i;
5348
5349         for (i = tp->irq_cnt - 1; i >= 0; i--)
5350                 napi_disable(&tp->napi[i].napi);
5351 }
5352
5353 static void tg3_napi_enable(struct tg3 *tp)
5354 {
5355         int i;
5356
5357         for (i = 0; i < tp->irq_cnt; i++)
5358                 napi_enable(&tp->napi[i].napi);
5359 }
5360
5361 static void tg3_napi_init(struct tg3 *tp)
5362 {
5363         int i;
5364
5365         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5366         for (i = 1; i < tp->irq_cnt; i++)
5367                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5368 }
5369
5370 static void tg3_napi_fini(struct tg3 *tp)
5371 {
5372         int i;
5373
5374         for (i = 0; i < tp->irq_cnt; i++)
5375                 netif_napi_del(&tp->napi[i].napi);
5376 }
5377
5378 static inline void tg3_netif_stop(struct tg3 *tp)
5379 {
5380         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5381         tg3_napi_disable(tp);
5382         netif_tx_disable(tp->dev);
5383 }
5384
5385 static inline void tg3_netif_start(struct tg3 *tp)
5386 {
5387         /* NOTE: unconditional netif_tx_wake_all_queues is only
5388          * appropriate so long as all callers are assured to
5389          * have free tx slots (such as after tg3_init_hw)
5390          */
5391         netif_tx_wake_all_queues(tp->dev);
5392
5393         tg3_napi_enable(tp);
5394         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5395         tg3_enable_ints(tp);
5396 }
5397
5398 static void tg3_irq_quiesce(struct tg3 *tp)
5399 {
5400         int i;
5401
5402         BUG_ON(tp->irq_sync);
5403
5404         tp->irq_sync = 1;
5405         smp_mb();
5406
5407         for (i = 0; i < tp->irq_cnt; i++)
5408                 synchronize_irq(tp->napi[i].irq_vec);
5409 }
5410
5411 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5412  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5413  * with as well.  Most of the time, this is not necessary except when
5414  * shutting down the device.
5415  */
5416 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5417 {
5418         spin_lock_bh(&tp->lock);
5419         if (irq_sync)
5420                 tg3_irq_quiesce(tp);
5421 }
5422
5423 static inline void tg3_full_unlock(struct tg3 *tp)
5424 {
5425         spin_unlock_bh(&tp->lock);
5426 }
5427
5428 /* One-shot MSI handler - Chip automatically disables interrupt
5429  * after sending MSI so driver doesn't have to do it.
5430  */
5431 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5432 {
5433         struct tg3_napi *tnapi = dev_id;
5434         struct tg3 *tp = tnapi->tp;
5435
5436         prefetch(tnapi->hw_status);
5437         if (tnapi->rx_rcb)
5438                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5439
5440         if (likely(!tg3_irq_sync(tp)))
5441                 napi_schedule(&tnapi->napi);
5442
5443         return IRQ_HANDLED;
5444 }
5445
5446 /* MSI ISR - No need to check for interrupt sharing and no need to
5447  * flush status block and interrupt mailbox. PCI ordering rules
5448  * guarantee that MSI will arrive after the status block.
5449  */
5450 static irqreturn_t tg3_msi(int irq, void *dev_id)
5451 {
5452         struct tg3_napi *tnapi = dev_id;
5453         struct tg3 *tp = tnapi->tp;
5454
5455         prefetch(tnapi->hw_status);
5456         if (tnapi->rx_rcb)
5457                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5458         /*
5459          * Writing any value to intr-mbox-0 clears PCI INTA# and
5460          * chip-internal interrupt pending events.
5461          * Writing non-zero to intr-mbox-0 additional tells the
5462          * NIC to stop sending us irqs, engaging "in-intr-handler"
5463          * event coalescing.
5464          */
5465         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5466         if (likely(!tg3_irq_sync(tp)))
5467                 napi_schedule(&tnapi->napi);
5468
5469         return IRQ_RETVAL(1);
5470 }
5471
5472 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5473 {
5474         struct tg3_napi *tnapi = dev_id;
5475         struct tg3 *tp = tnapi->tp;
5476         struct tg3_hw_status *sblk = tnapi->hw_status;
5477         unsigned int handled = 1;
5478
5479         /* In INTx mode, it is possible for the interrupt to arrive at
5480          * the CPU before the status block posted prior to the interrupt.
5481          * Reading the PCI State register will confirm whether the
5482          * interrupt is ours and will flush the status block.
5483          */
5484         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5485                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5486                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5487                         handled = 0;
5488                         goto out;
5489                 }
5490         }
5491
5492         /*
5493          * Writing any value to intr-mbox-0 clears PCI INTA# and
5494          * chip-internal interrupt pending events.
5495          * Writing non-zero to intr-mbox-0 additional tells the
5496          * NIC to stop sending us irqs, engaging "in-intr-handler"
5497          * event coalescing.
5498          *
5499          * Flush the mailbox to de-assert the IRQ immediately to prevent
5500          * spurious interrupts.  The flush impacts performance but
5501          * excessive spurious interrupts can be worse in some cases.
5502          */
5503         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5504         if (tg3_irq_sync(tp))
5505                 goto out;
5506         sblk->status &= ~SD_STATUS_UPDATED;
5507         if (likely(tg3_has_work(tnapi))) {
5508                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5509                 napi_schedule(&tnapi->napi);
5510         } else {
5511                 /* No work, shared interrupt perhaps?  re-enable
5512                  * interrupts, and flush that PCI write
5513                  */
5514                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5515                                0x00000000);
5516         }
5517 out:
5518         return IRQ_RETVAL(handled);
5519 }
5520
5521 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5522 {
5523         struct tg3_napi *tnapi = dev_id;
5524         struct tg3 *tp = tnapi->tp;
5525         struct tg3_hw_status *sblk = tnapi->hw_status;
5526         unsigned int handled = 1;
5527
5528         /* In INTx mode, it is possible for the interrupt to arrive at
5529          * the CPU before the status block posted prior to the interrupt.
5530          * Reading the PCI State register will confirm whether the
5531          * interrupt is ours and will flush the status block.
5532          */
5533         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5534                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5535                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5536                         handled = 0;
5537                         goto out;
5538                 }
5539         }
5540
5541         /*
5542          * writing any value to intr-mbox-0 clears PCI INTA# and
5543          * chip-internal interrupt pending events.
5544          * writing non-zero to intr-mbox-0 additional tells the
5545          * NIC to stop sending us irqs, engaging "in-intr-handler"
5546          * event coalescing.
5547          *
5548          * Flush the mailbox to de-assert the IRQ immediately to prevent
5549          * spurious interrupts.  The flush impacts performance but
5550          * excessive spurious interrupts can be worse in some cases.
5551          */
5552         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5553
5554         /*
5555          * In a shared interrupt configuration, sometimes other devices'
5556          * interrupts will scream.  We record the current status tag here
5557          * so that the above check can report that the screaming interrupts
5558          * are unhandled.  Eventually they will be silenced.
5559          */
5560         tnapi->last_irq_tag = sblk->status_tag;
5561
5562         if (tg3_irq_sync(tp))
5563                 goto out;
5564
5565         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5566
5567         napi_schedule(&tnapi->napi);
5568
5569 out:
5570         return IRQ_RETVAL(handled);
5571 }
5572
5573 /* ISR for interrupt test */
5574 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5575 {
5576         struct tg3_napi *tnapi = dev_id;
5577         struct tg3 *tp = tnapi->tp;
5578         struct tg3_hw_status *sblk = tnapi->hw_status;
5579
5580         if ((sblk->status & SD_STATUS_UPDATED) ||
5581             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5582                 tg3_disable_ints(tp);
5583                 return IRQ_RETVAL(1);
5584         }
5585         return IRQ_RETVAL(0);
5586 }
5587
5588 static int tg3_init_hw(struct tg3 *, int);
5589 static int tg3_halt(struct tg3 *, int, int);
5590
5591 /* Restart hardware after configuration changes, self-test, etc.
5592  * Invoked with tp->lock held.
5593  */
5594 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5595         __releases(tp->lock)
5596         __acquires(tp->lock)
5597 {
5598         int err;
5599
5600         err = tg3_init_hw(tp, reset_phy);
5601         if (err) {
5602                 netdev_err(tp->dev,
5603                            "Failed to re-initialize device, aborting\n");
5604                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5605                 tg3_full_unlock(tp);
5606                 del_timer_sync(&tp->timer);
5607                 tp->irq_sync = 0;
5608                 tg3_napi_enable(tp);
5609                 dev_close(tp->dev);
5610                 tg3_full_lock(tp, 0);
5611         }
5612         return err;
5613 }
5614
5615 #ifdef CONFIG_NET_POLL_CONTROLLER
5616 static void tg3_poll_controller(struct net_device *dev)
5617 {
5618         int i;
5619         struct tg3 *tp = netdev_priv(dev);
5620
5621         for (i = 0; i < tp->irq_cnt; i++)
5622                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5623 }
5624 #endif
5625
5626 static void tg3_reset_task(struct work_struct *work)
5627 {
5628         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5629         int err;
5630         unsigned int restart_timer;
5631
5632         tg3_full_lock(tp, 0);
5633
5634         if (!netif_running(tp->dev)) {
5635                 tg3_full_unlock(tp);
5636                 return;
5637         }
5638
5639         tg3_full_unlock(tp);
5640
5641         tg3_phy_stop(tp);
5642
5643         tg3_netif_stop(tp);
5644
5645         tg3_full_lock(tp, 1);
5646
5647         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5648         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5649
5650         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5651                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5652                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5653                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5654                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5655         }
5656
5657         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5658         err = tg3_init_hw(tp, 1);
5659         if (err)
5660                 goto out;
5661
5662         tg3_netif_start(tp);
5663
5664         if (restart_timer)
5665                 mod_timer(&tp->timer, jiffies + 1);
5666
5667 out:
5668         tg3_full_unlock(tp);
5669
5670         if (!err)
5671                 tg3_phy_start(tp);
5672 }
5673
5674 static void tg3_tx_timeout(struct net_device *dev)
5675 {
5676         struct tg3 *tp = netdev_priv(dev);
5677
5678         if (netif_msg_tx_err(tp)) {
5679                 netdev_err(dev, "transmit timed out, resetting\n");
5680                 tg3_dump_state(tp);
5681         }
5682
5683         schedule_work(&tp->reset_task);
5684 }
5685
5686 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5687 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5688 {
5689         u32 base = (u32) mapping & 0xffffffff;
5690
5691         return (base > 0xffffdcc0) && (base + len + 8 < base);
5692 }
5693
5694 /* Test for DMA addresses > 40-bit */
5695 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5696                                           int len)
5697 {
5698 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5699         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5700                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5701         return 0;
5702 #else
5703         return 0;
5704 #endif
5705 }
5706
5707 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5708
5709 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5710 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5711                                        struct sk_buff *skb, u32 last_plus_one,
5712                                        u32 *start, u32 base_flags, u32 mss)
5713 {
5714         struct tg3 *tp = tnapi->tp;
5715         struct sk_buff *new_skb;
5716         dma_addr_t new_addr = 0;
5717         u32 entry = *start;
5718         int i, ret = 0;
5719
5720         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5721                 new_skb = skb_copy(skb, GFP_ATOMIC);
5722         else {
5723                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5724
5725                 new_skb = skb_copy_expand(skb,
5726                                           skb_headroom(skb) + more_headroom,
5727                                           skb_tailroom(skb), GFP_ATOMIC);
5728         }
5729
5730         if (!new_skb) {
5731                 ret = -1;
5732         } else {
5733                 /* New SKB is guaranteed to be linear. */
5734                 entry = *start;
5735                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5736                                           PCI_DMA_TODEVICE);
5737                 /* Make sure the mapping succeeded */
5738                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5739                         ret = -1;
5740                         dev_kfree_skb(new_skb);
5741                         new_skb = NULL;
5742
5743                 /* Make sure new skb does not cross any 4G boundaries.
5744                  * Drop the packet if it does.
5745                  */
5746                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5747                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5748                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5749                                          PCI_DMA_TODEVICE);
5750                         ret = -1;
5751                         dev_kfree_skb(new_skb);
5752                         new_skb = NULL;
5753                 } else {
5754                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5755                                     base_flags, 1 | (mss << 1));
5756                         *start = NEXT_TX(entry);
5757                 }
5758         }
5759
5760         /* Now clean up the sw ring entries. */
5761         i = 0;
5762         while (entry != last_plus_one) {
5763                 int len;
5764
5765                 if (i == 0)
5766                         len = skb_headlen(skb);
5767                 else
5768                         len = skb_shinfo(skb)->frags[i-1].size;
5769
5770                 pci_unmap_single(tp->pdev,
5771                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5772                                                 mapping),
5773                                  len, PCI_DMA_TODEVICE);
5774                 if (i == 0) {
5775                         tnapi->tx_buffers[entry].skb = new_skb;
5776                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5777                                            new_addr);
5778                 } else {
5779                         tnapi->tx_buffers[entry].skb = NULL;
5780                 }
5781                 entry = NEXT_TX(entry);
5782                 i++;
5783         }
5784
5785         dev_kfree_skb(skb);
5786
5787         return ret;
5788 }
5789
5790 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5791                         dma_addr_t mapping, int len, u32 flags,
5792                         u32 mss_and_is_end)
5793 {
5794         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5795         int is_end = (mss_and_is_end & 0x1);
5796         u32 mss = (mss_and_is_end >> 1);
5797         u32 vlan_tag = 0;
5798
5799         if (is_end)
5800                 flags |= TXD_FLAG_END;
5801         if (flags & TXD_FLAG_VLAN) {
5802                 vlan_tag = flags >> 16;
5803                 flags &= 0xffff;
5804         }
5805         vlan_tag |= (mss << TXD_MSS_SHIFT);
5806
5807         txd->addr_hi = ((u64) mapping >> 32);
5808         txd->addr_lo = ((u64) mapping & 0xffffffff);
5809         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5810         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5811 }
5812
5813 /* hard_start_xmit for devices that don't have any bugs and
5814  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5815  */
5816 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5817                                   struct net_device *dev)
5818 {
5819         struct tg3 *tp = netdev_priv(dev);
5820         u32 len, entry, base_flags, mss;
5821         dma_addr_t mapping;
5822         struct tg3_napi *tnapi;
5823         struct netdev_queue *txq;
5824         unsigned int i, last;
5825
5826         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5827         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5828         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5829                 tnapi++;
5830
5831         /* We are running in BH disabled context with netif_tx_lock
5832          * and TX reclaim runs via tp->napi.poll inside of a software
5833          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5834          * no IRQ context deadlocks to worry about either.  Rejoice!
5835          */
5836         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5837                 if (!netif_tx_queue_stopped(txq)) {
5838                         netif_tx_stop_queue(txq);
5839
5840                         /* This is a hard error, log it. */
5841                         netdev_err(dev,
5842                                    "BUG! Tx Ring full when queue awake!\n");
5843                 }
5844                 return NETDEV_TX_BUSY;
5845         }
5846
5847         entry = tnapi->tx_prod;
5848         base_flags = 0;
5849         mss = skb_shinfo(skb)->gso_size;
5850         if (mss) {
5851                 int tcp_opt_len, ip_tcp_len;
5852                 u32 hdrlen;
5853
5854                 if (skb_header_cloned(skb) &&
5855                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5856                         dev_kfree_skb(skb);
5857                         goto out_unlock;
5858                 }
5859
5860                 if (skb_is_gso_v6(skb)) {
5861                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5862                 } else {
5863                         struct iphdr *iph = ip_hdr(skb);
5864
5865                         tcp_opt_len = tcp_optlen(skb);
5866                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5867
5868                         iph->check = 0;
5869                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5870                         hdrlen = ip_tcp_len + tcp_opt_len;
5871                 }
5872
5873                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5874                         mss |= (hdrlen & 0xc) << 12;
5875                         if (hdrlen & 0x10)
5876                                 base_flags |= 0x00000010;
5877                         base_flags |= (hdrlen & 0x3e0) << 5;
5878                 } else
5879                         mss |= hdrlen << 9;
5880
5881                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5882                                TXD_FLAG_CPU_POST_DMA);
5883
5884                 tcp_hdr(skb)->check = 0;
5885
5886         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5887                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5888         }
5889
5890         if (vlan_tx_tag_present(skb))
5891                 base_flags |= (TXD_FLAG_VLAN |
5892                                (vlan_tx_tag_get(skb) << 16));
5893
5894         len = skb_headlen(skb);
5895
5896         /* Queue skb data, a.k.a. the main skb fragment. */
5897         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5898         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5899                 dev_kfree_skb(skb);
5900                 goto out_unlock;
5901         }
5902
5903         tnapi->tx_buffers[entry].skb = skb;
5904         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5905
5906         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5907             !mss && skb->len > VLAN_ETH_FRAME_LEN)
5908                 base_flags |= TXD_FLAG_JMB_PKT;
5909
5910         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5911                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5912
5913         entry = NEXT_TX(entry);
5914
5915         /* Now loop through additional data fragments, and queue them. */
5916         if (skb_shinfo(skb)->nr_frags > 0) {
5917                 last = skb_shinfo(skb)->nr_frags - 1;
5918                 for (i = 0; i <= last; i++) {
5919                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5920
5921                         len = frag->size;
5922                         mapping = pci_map_page(tp->pdev,
5923                                                frag->page,
5924                                                frag->page_offset,
5925                                                len, PCI_DMA_TODEVICE);
5926                         if (pci_dma_mapping_error(tp->pdev, mapping))
5927                                 goto dma_error;
5928
5929                         tnapi->tx_buffers[entry].skb = NULL;
5930                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5931                                            mapping);
5932
5933                         tg3_set_txd(tnapi, entry, mapping, len,
5934                                     base_flags, (i == last) | (mss << 1));
5935
5936                         entry = NEXT_TX(entry);
5937                 }
5938         }
5939
5940         /* Packets are ready, update Tx producer idx local and on card. */
5941         tw32_tx_mbox(tnapi->prodmbox, entry);
5942
5943         tnapi->tx_prod = entry;
5944         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5945                 netif_tx_stop_queue(txq);
5946
5947                 /* netif_tx_stop_queue() must be done before checking
5948                  * checking tx index in tg3_tx_avail() below, because in
5949                  * tg3_tx(), we update tx index before checking for
5950                  * netif_tx_queue_stopped().
5951                  */
5952                 smp_mb();
5953                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5954                         netif_tx_wake_queue(txq);
5955         }
5956
5957 out_unlock:
5958         mmiowb();
5959
5960         return NETDEV_TX_OK;
5961
5962 dma_error:
5963         last = i;
5964         entry = tnapi->tx_prod;
5965         tnapi->tx_buffers[entry].skb = NULL;
5966         pci_unmap_single(tp->pdev,
5967                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5968                          skb_headlen(skb),
5969                          PCI_DMA_TODEVICE);
5970         for (i = 0; i <= last; i++) {
5971                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5972                 entry = NEXT_TX(entry);
5973
5974                 pci_unmap_page(tp->pdev,
5975                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5976                                               mapping),
5977                                frag->size, PCI_DMA_TODEVICE);
5978         }
5979
5980         dev_kfree_skb(skb);
5981         return NETDEV_TX_OK;
5982 }
5983
5984 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5985                                           struct net_device *);
5986
5987 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5988  * TSO header is greater than 80 bytes.
5989  */
5990 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5991 {
5992         struct sk_buff *segs, *nskb;
5993         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5994
5995         /* Estimate the number of fragments in the worst case */
5996         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5997                 netif_stop_queue(tp->dev);
5998
5999                 /* netif_tx_stop_queue() must be done before checking
6000                  * checking tx index in tg3_tx_avail() below, because in
6001                  * tg3_tx(), we update tx index before checking for
6002                  * netif_tx_queue_stopped().
6003                  */
6004                 smp_mb();
6005                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
6006                         return NETDEV_TX_BUSY;
6007
6008                 netif_wake_queue(tp->dev);
6009         }
6010
6011         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
6012         if (IS_ERR(segs))
6013                 goto tg3_tso_bug_end;
6014
6015         do {
6016                 nskb = segs;
6017                 segs = segs->next;
6018                 nskb->next = NULL;
6019                 tg3_start_xmit_dma_bug(nskb, tp->dev);
6020         } while (segs);
6021
6022 tg3_tso_bug_end:
6023         dev_kfree_skb(skb);
6024
6025         return NETDEV_TX_OK;
6026 }
6027
6028 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6029  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
6030  */
6031 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
6032                                           struct net_device *dev)
6033 {
6034         struct tg3 *tp = netdev_priv(dev);
6035         u32 len, entry, base_flags, mss;
6036         int would_hit_hwbug;
6037         dma_addr_t mapping;
6038         struct tg3_napi *tnapi;
6039         struct netdev_queue *txq;
6040         unsigned int i, last;
6041
6042         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6043         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6044         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
6045                 tnapi++;
6046
6047         /* We are running in BH disabled context with netif_tx_lock
6048          * and TX reclaim runs via tp->napi.poll inside of a software
6049          * interrupt.  Furthermore, IRQ processing runs lockless so we have
6050          * no IRQ context deadlocks to worry about either.  Rejoice!
6051          */
6052         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
6053                 if (!netif_tx_queue_stopped(txq)) {
6054                         netif_tx_stop_queue(txq);
6055
6056                         /* This is a hard error, log it. */
6057                         netdev_err(dev,
6058                                    "BUG! Tx Ring full when queue awake!\n");
6059                 }
6060                 return NETDEV_TX_BUSY;
6061         }
6062
6063         entry = tnapi->tx_prod;
6064         base_flags = 0;
6065         if (skb->ip_summed == CHECKSUM_PARTIAL)
6066                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
6067
6068         mss = skb_shinfo(skb)->gso_size;
6069         if (mss) {
6070                 struct iphdr *iph;
6071                 u32 tcp_opt_len, hdr_len;
6072
6073                 if (skb_header_cloned(skb) &&
6074                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
6075                         dev_kfree_skb(skb);
6076                         goto out_unlock;
6077                 }
6078
6079                 iph = ip_hdr(skb);
6080                 tcp_opt_len = tcp_optlen(skb);
6081
6082                 if (skb_is_gso_v6(skb)) {
6083                         hdr_len = skb_headlen(skb) - ETH_HLEN;
6084                 } else {
6085                         u32 ip_tcp_len;
6086
6087                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
6088                         hdr_len = ip_tcp_len + tcp_opt_len;
6089
6090                         iph->check = 0;
6091                         iph->tot_len = htons(mss + hdr_len);
6092                 }
6093
6094                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
6095                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
6096                         return tg3_tso_bug(tp, skb);
6097
6098                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6099                                TXD_FLAG_CPU_POST_DMA);
6100
6101                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
6102                         tcp_hdr(skb)->check = 0;
6103                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
6104                 } else
6105                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6106                                                                  iph->daddr, 0,
6107                                                                  IPPROTO_TCP,
6108                                                                  0);
6109
6110                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
6111                         mss |= (hdr_len & 0xc) << 12;
6112                         if (hdr_len & 0x10)
6113                                 base_flags |= 0x00000010;
6114                         base_flags |= (hdr_len & 0x3e0) << 5;
6115                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
6116                         mss |= hdr_len << 9;
6117                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
6118                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6119                         if (tcp_opt_len || iph->ihl > 5) {
6120                                 int tsflags;
6121
6122                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6123                                 mss |= (tsflags << 11);
6124                         }
6125                 } else {
6126                         if (tcp_opt_len || iph->ihl > 5) {
6127                                 int tsflags;
6128
6129                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6130                                 base_flags |= tsflags << 12;
6131                         }
6132                 }
6133         }
6134
6135         if (vlan_tx_tag_present(skb))
6136                 base_flags |= (TXD_FLAG_VLAN |
6137                                (vlan_tx_tag_get(skb) << 16));
6138
6139         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
6140             !mss && skb->len > VLAN_ETH_FRAME_LEN)
6141                 base_flags |= TXD_FLAG_JMB_PKT;
6142
6143         len = skb_headlen(skb);
6144
6145         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6146         if (pci_dma_mapping_error(tp->pdev, mapping)) {
6147                 dev_kfree_skb(skb);
6148                 goto out_unlock;
6149         }
6150
6151         tnapi->tx_buffers[entry].skb = skb;
6152         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6153
6154         would_hit_hwbug = 0;
6155
6156         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6157                 would_hit_hwbug = 1;
6158
6159         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6160             tg3_4g_overflow_test(mapping, len))
6161                 would_hit_hwbug = 1;
6162
6163         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6164             tg3_40bit_overflow_test(tp, mapping, len))
6165                 would_hit_hwbug = 1;
6166
6167         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6168                 would_hit_hwbug = 1;
6169
6170         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6171                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6172
6173         entry = NEXT_TX(entry);
6174
6175         /* Now loop through additional data fragments, and queue them. */
6176         if (skb_shinfo(skb)->nr_frags > 0) {
6177                 last = skb_shinfo(skb)->nr_frags - 1;
6178                 for (i = 0; i <= last; i++) {
6179                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6180
6181                         len = frag->size;
6182                         mapping = pci_map_page(tp->pdev,
6183                                                frag->page,
6184                                                frag->page_offset,
6185                                                len, PCI_DMA_TODEVICE);
6186
6187                         tnapi->tx_buffers[entry].skb = NULL;
6188                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6189                                            mapping);
6190                         if (pci_dma_mapping_error(tp->pdev, mapping))
6191                                 goto dma_error;
6192
6193                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6194                             len <= 8)
6195                                 would_hit_hwbug = 1;
6196
6197                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6198                             tg3_4g_overflow_test(mapping, len))
6199                                 would_hit_hwbug = 1;
6200
6201                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6202                             tg3_40bit_overflow_test(tp, mapping, len))
6203                                 would_hit_hwbug = 1;
6204
6205                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6206                                 tg3_set_txd(tnapi, entry, mapping, len,
6207                                             base_flags, (i == last)|(mss << 1));
6208                         else
6209                                 tg3_set_txd(tnapi, entry, mapping, len,
6210                                             base_flags, (i == last));
6211
6212                         entry = NEXT_TX(entry);
6213                 }
6214         }
6215
6216         if (would_hit_hwbug) {
6217                 u32 last_plus_one = entry;
6218                 u32 start;
6219
6220                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6221                 start &= (TG3_TX_RING_SIZE - 1);
6222
6223                 /* If the workaround fails due to memory/mapping
6224                  * failure, silently drop this packet.
6225                  */
6226                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6227                                                 &start, base_flags, mss))
6228                         goto out_unlock;
6229
6230                 entry = start;
6231         }
6232
6233         /* Packets are ready, update Tx producer idx local and on card. */
6234         tw32_tx_mbox(tnapi->prodmbox, entry);
6235
6236         tnapi->tx_prod = entry;
6237         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6238                 netif_tx_stop_queue(txq);
6239
6240                 /* netif_tx_stop_queue() must be done before checking
6241                  * checking tx index in tg3_tx_avail() below, because in
6242                  * tg3_tx(), we update tx index before checking for
6243                  * netif_tx_queue_stopped().
6244                  */
6245                 smp_mb();
6246                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6247                         netif_tx_wake_queue(txq);
6248         }
6249
6250 out_unlock:
6251         mmiowb();
6252
6253         return NETDEV_TX_OK;
6254
6255 dma_error:
6256         last = i;
6257         entry = tnapi->tx_prod;
6258         tnapi->tx_buffers[entry].skb = NULL;
6259         pci_unmap_single(tp->pdev,
6260                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6261                          skb_headlen(skb),
6262                          PCI_DMA_TODEVICE);
6263         for (i = 0; i <= last; i++) {
6264                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6265                 entry = NEXT_TX(entry);
6266
6267                 pci_unmap_page(tp->pdev,
6268                                dma_unmap_addr(&tnapi->tx_buffers[entry],
6269                                               mapping),
6270                                frag->size, PCI_DMA_TODEVICE);
6271         }
6272
6273         dev_kfree_skb(skb);
6274         return NETDEV_TX_OK;
6275 }
6276
6277 static u32 tg3_fix_features(struct net_device *dev, u32 features)
6278 {
6279         struct tg3 *tp = netdev_priv(dev);
6280
6281         if (dev->mtu > ETH_DATA_LEN && (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6282                 features &= ~NETIF_F_ALL_TSO;
6283
6284         return features;
6285 }
6286
6287 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6288                                int new_mtu)
6289 {
6290         dev->mtu = new_mtu;
6291
6292         if (new_mtu > ETH_DATA_LEN) {
6293                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6294                         netdev_update_features(dev);
6295                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6296                 } else {
6297                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6298                 }
6299         } else {
6300                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6301                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6302                         netdev_update_features(dev);
6303                 }
6304                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6305         }
6306 }
6307
6308 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6309 {
6310         struct tg3 *tp = netdev_priv(dev);
6311         int err;
6312
6313         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6314                 return -EINVAL;
6315
6316         if (!netif_running(dev)) {
6317                 /* We'll just catch it later when the
6318                  * device is up'd.
6319                  */
6320                 tg3_set_mtu(dev, tp, new_mtu);
6321                 return 0;
6322         }
6323
6324         tg3_phy_stop(tp);
6325
6326         tg3_netif_stop(tp);
6327
6328         tg3_full_lock(tp, 1);
6329
6330         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6331
6332         tg3_set_mtu(dev, tp, new_mtu);
6333
6334         err = tg3_restart_hw(tp, 0);
6335
6336         if (!err)
6337                 tg3_netif_start(tp);
6338
6339         tg3_full_unlock(tp);
6340
6341         if (!err)
6342                 tg3_phy_start(tp);
6343
6344         return err;
6345 }
6346
6347 static void tg3_rx_prodring_free(struct tg3 *tp,
6348                                  struct tg3_rx_prodring_set *tpr)
6349 {
6350         int i;
6351
6352         if (tpr != &tp->napi[0].prodring) {
6353                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6354                      i = (i + 1) & tp->rx_std_ring_mask)
6355                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6356                                         tp->rx_pkt_map_sz);
6357
6358                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6359                         for (i = tpr->rx_jmb_cons_idx;
6360                              i != tpr->rx_jmb_prod_idx;
6361                              i = (i + 1) & tp->rx_jmb_ring_mask) {
6362                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6363                                                 TG3_RX_JMB_MAP_SZ);
6364                         }
6365                 }
6366
6367                 return;
6368         }
6369
6370         for (i = 0; i <= tp->rx_std_ring_mask; i++)
6371                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6372                                 tp->rx_pkt_map_sz);
6373
6374         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6375             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6376                 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6377                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6378                                         TG3_RX_JMB_MAP_SZ);
6379         }
6380 }
6381
6382 /* Initialize rx rings for packet processing.
6383  *
6384  * The chip has been shut down and the driver detached from
6385  * the networking, so no interrupts or new tx packets will
6386  * end up in the driver.  tp->{tx,}lock are held and thus
6387  * we may not sleep.
6388  */
6389 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6390                                  struct tg3_rx_prodring_set *tpr)
6391 {
6392         u32 i, rx_pkt_dma_sz;
6393
6394         tpr->rx_std_cons_idx = 0;
6395         tpr->rx_std_prod_idx = 0;
6396         tpr->rx_jmb_cons_idx = 0;
6397         tpr->rx_jmb_prod_idx = 0;
6398
6399         if (tpr != &tp->napi[0].prodring) {
6400                 memset(&tpr->rx_std_buffers[0], 0,
6401                        TG3_RX_STD_BUFF_RING_SIZE(tp));
6402                 if (tpr->rx_jmb_buffers)
6403                         memset(&tpr->rx_jmb_buffers[0], 0,
6404                                TG3_RX_JMB_BUFF_RING_SIZE(tp));
6405                 goto done;
6406         }
6407
6408         /* Zero out all descriptors. */
6409         memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6410
6411         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6412         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6413             tp->dev->mtu > ETH_DATA_LEN)
6414                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6415         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6416
6417         /* Initialize invariants of the rings, we only set this
6418          * stuff once.  This works because the card does not
6419          * write into the rx buffer posting rings.
6420          */
6421         for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6422                 struct tg3_rx_buffer_desc *rxd;
6423
6424                 rxd = &tpr->rx_std[i];
6425                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6426                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6427                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6428                                (i << RXD_OPAQUE_INDEX_SHIFT));
6429         }
6430
6431         /* Now allocate fresh SKBs for each rx ring. */
6432         for (i = 0; i < tp->rx_pending; i++) {
6433                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6434                         netdev_warn(tp->dev,
6435                                     "Using a smaller RX standard ring. Only "
6436                                     "%d out of %d buffers were allocated "
6437                                     "successfully\n", i, tp->rx_pending);
6438                         if (i == 0)
6439                                 goto initfail;
6440                         tp->rx_pending = i;
6441                         break;
6442                 }
6443         }
6444
6445         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6446             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6447                 goto done;
6448
6449         memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6450
6451         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6452                 goto done;
6453
6454         for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6455                 struct tg3_rx_buffer_desc *rxd;
6456
6457                 rxd = &tpr->rx_jmb[i].std;
6458                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6459                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6460                                   RXD_FLAG_JUMBO;
6461                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6462                        (i << RXD_OPAQUE_INDEX_SHIFT));
6463         }
6464
6465         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6466                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6467                         netdev_warn(tp->dev,
6468                                     "Using a smaller RX jumbo ring. Only %d "
6469                                     "out of %d buffers were allocated "
6470                                     "successfully\n", i, tp->rx_jumbo_pending);
6471                         if (i == 0)
6472                                 goto initfail;
6473                         tp->rx_jumbo_pending = i;
6474                         break;
6475                 }
6476         }
6477
6478 done:
6479         return 0;
6480
6481 initfail:
6482         tg3_rx_prodring_free(tp, tpr);
6483         return -ENOMEM;
6484 }
6485
6486 static void tg3_rx_prodring_fini(struct tg3 *tp,
6487                                  struct tg3_rx_prodring_set *tpr)
6488 {
6489         kfree(tpr->rx_std_buffers);
6490         tpr->rx_std_buffers = NULL;
6491         kfree(tpr->rx_jmb_buffers);
6492         tpr->rx_jmb_buffers = NULL;
6493         if (tpr->rx_std) {
6494                 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6495                                   tpr->rx_std, tpr->rx_std_mapping);
6496                 tpr->rx_std = NULL;
6497         }
6498         if (tpr->rx_jmb) {
6499                 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6500                                   tpr->rx_jmb, tpr->rx_jmb_mapping);
6501                 tpr->rx_jmb = NULL;
6502         }
6503 }
6504
6505 static int tg3_rx_prodring_init(struct tg3 *tp,
6506                                 struct tg3_rx_prodring_set *tpr)
6507 {
6508         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6509                                       GFP_KERNEL);
6510         if (!tpr->rx_std_buffers)
6511                 return -ENOMEM;
6512
6513         tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6514                                          TG3_RX_STD_RING_BYTES(tp),
6515                                          &tpr->rx_std_mapping,
6516                                          GFP_KERNEL);
6517         if (!tpr->rx_std)
6518                 goto err_out;
6519
6520         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6521             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6522                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6523                                               GFP_KERNEL);
6524                 if (!tpr->rx_jmb_buffers)
6525                         goto err_out;
6526
6527                 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6528                                                  TG3_RX_JMB_RING_BYTES(tp),
6529                                                  &tpr->rx_jmb_mapping,
6530                                                  GFP_KERNEL);
6531                 if (!tpr->rx_jmb)
6532                         goto err_out;
6533         }
6534
6535         return 0;
6536
6537 err_out:
6538         tg3_rx_prodring_fini(tp, tpr);
6539         return -ENOMEM;
6540 }
6541
6542 /* Free up pending packets in all rx/tx rings.
6543  *
6544  * The chip has been shut down and the driver detached from
6545  * the networking, so no interrupts or new tx packets will
6546  * end up in the driver.  tp->{tx,}lock is not held and we are not
6547  * in an interrupt context and thus may sleep.
6548  */
6549 static void tg3_free_rings(struct tg3 *tp)
6550 {
6551         int i, j;
6552
6553         for (j = 0; j < tp->irq_cnt; j++) {
6554                 struct tg3_napi *tnapi = &tp->napi[j];
6555
6556                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6557
6558                 if (!tnapi->tx_buffers)
6559                         continue;
6560
6561                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6562                         struct ring_info *txp;
6563                         struct sk_buff *skb;
6564                         unsigned int k;
6565
6566                         txp = &tnapi->tx_buffers[i];
6567                         skb = txp->skb;
6568
6569                         if (skb == NULL) {
6570                                 i++;
6571                                 continue;
6572                         }
6573
6574                         pci_unmap_single(tp->pdev,
6575                                          dma_unmap_addr(txp, mapping),
6576                                          skb_headlen(skb),
6577                                          PCI_DMA_TODEVICE);
6578                         txp->skb = NULL;
6579
6580                         i++;
6581
6582                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6583                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6584                                 pci_unmap_page(tp->pdev,
6585                                                dma_unmap_addr(txp, mapping),
6586                                                skb_shinfo(skb)->frags[k].size,
6587                                                PCI_DMA_TODEVICE);
6588                                 i++;
6589                         }
6590
6591                         dev_kfree_skb_any(skb);
6592                 }
6593         }
6594 }
6595
6596 /* Initialize tx/rx rings for packet processing.
6597  *
6598  * The chip has been shut down and the driver detached from
6599  * the networking, so no interrupts or new tx packets will
6600  * end up in the driver.  tp->{tx,}lock are held and thus
6601  * we may not sleep.
6602  */
6603 static int tg3_init_rings(struct tg3 *tp)
6604 {
6605         int i;
6606
6607         /* Free up all the SKBs. */
6608         tg3_free_rings(tp);
6609
6610         for (i = 0; i < tp->irq_cnt; i++) {
6611                 struct tg3_napi *tnapi = &tp->napi[i];
6612
6613                 tnapi->last_tag = 0;
6614                 tnapi->last_irq_tag = 0;
6615                 tnapi->hw_status->status = 0;
6616                 tnapi->hw_status->status_tag = 0;
6617                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6618
6619                 tnapi->tx_prod = 0;
6620                 tnapi->tx_cons = 0;
6621                 if (tnapi->tx_ring)
6622                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6623
6624                 tnapi->rx_rcb_ptr = 0;
6625                 if (tnapi->rx_rcb)
6626                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6627
6628                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6629                         tg3_free_rings(tp);
6630                         return -ENOMEM;
6631                 }
6632         }
6633
6634         return 0;
6635 }
6636
6637 /*
6638  * Must not be invoked with interrupt sources disabled and
6639  * the hardware shutdown down.
6640  */
6641 static void tg3_free_consistent(struct tg3 *tp)
6642 {
6643         int i;
6644
6645         for (i = 0; i < tp->irq_cnt; i++) {
6646                 struct tg3_napi *tnapi = &tp->napi[i];
6647
6648                 if (tnapi->tx_ring) {
6649                         dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
6650                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6651                         tnapi->tx_ring = NULL;
6652                 }
6653
6654                 kfree(tnapi->tx_buffers);
6655                 tnapi->tx_buffers = NULL;
6656
6657                 if (tnapi->rx_rcb) {
6658                         dma_free_coherent(&tp->pdev->dev,
6659                                           TG3_RX_RCB_RING_BYTES(tp),
6660                                           tnapi->rx_rcb,
6661                                           tnapi->rx_rcb_mapping);
6662                         tnapi->rx_rcb = NULL;
6663                 }
6664
6665                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6666
6667                 if (tnapi->hw_status) {
6668                         dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6669                                           tnapi->hw_status,
6670                                           tnapi->status_mapping);
6671                         tnapi->hw_status = NULL;
6672                 }
6673         }
6674
6675         if (tp->hw_stats) {
6676                 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6677                                   tp->hw_stats, tp->stats_mapping);
6678                 tp->hw_stats = NULL;
6679         }
6680 }
6681
6682 /*
6683  * Must not be invoked with interrupt sources disabled and
6684  * the hardware shutdown down.  Can sleep.
6685  */
6686 static int tg3_alloc_consistent(struct tg3 *tp)
6687 {
6688         int i;
6689
6690         tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6691                                           sizeof(struct tg3_hw_stats),
6692                                           &tp->stats_mapping,
6693                                           GFP_KERNEL);
6694         if (!tp->hw_stats)
6695                 goto err_out;
6696
6697         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6698
6699         for (i = 0; i < tp->irq_cnt; i++) {
6700                 struct tg3_napi *tnapi = &tp->napi[i];
6701                 struct tg3_hw_status *sblk;
6702
6703                 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6704                                                       TG3_HW_STATUS_SIZE,
6705                                                       &tnapi->status_mapping,
6706                                                       GFP_KERNEL);
6707                 if (!tnapi->hw_status)
6708                         goto err_out;
6709
6710                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6711                 sblk = tnapi->hw_status;
6712
6713                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6714                         goto err_out;
6715
6716                 /* If multivector TSS is enabled, vector 0 does not handle
6717                  * tx interrupts.  Don't allocate any resources for it.
6718                  */
6719                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6720                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6721                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6722                                                     TG3_TX_RING_SIZE,
6723                                                     GFP_KERNEL);
6724                         if (!tnapi->tx_buffers)
6725                                 goto err_out;
6726
6727                         tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6728                                                             TG3_TX_RING_BYTES,
6729                                                         &tnapi->tx_desc_mapping,
6730                                                             GFP_KERNEL);
6731                         if (!tnapi->tx_ring)
6732                                 goto err_out;
6733                 }
6734
6735                 /*
6736                  * When RSS is enabled, the status block format changes
6737                  * slightly.  The "rx_jumbo_consumer", "reserved",
6738                  * and "rx_mini_consumer" members get mapped to the
6739                  * other three rx return ring producer indexes.
6740                  */
6741                 switch (i) {
6742                 default:
6743                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6744                         break;
6745                 case 2:
6746                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6747                         break;
6748                 case 3:
6749                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6750                         break;
6751                 case 4:
6752                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6753                         break;
6754                 }
6755
6756                 /*
6757                  * If multivector RSS is enabled, vector 0 does not handle
6758                  * rx or tx interrupts.  Don't allocate any resources for it.
6759                  */
6760                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6761                         continue;
6762
6763                 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6764                                                    TG3_RX_RCB_RING_BYTES(tp),
6765                                                    &tnapi->rx_rcb_mapping,
6766                                                    GFP_KERNEL);
6767                 if (!tnapi->rx_rcb)
6768                         goto err_out;
6769
6770                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6771         }
6772
6773         return 0;
6774
6775 err_out:
6776         tg3_free_consistent(tp);
6777         return -ENOMEM;
6778 }
6779
6780 #define MAX_WAIT_CNT 1000
6781
6782 /* To stop a block, clear the enable bit and poll till it
6783  * clears.  tp->lock is held.
6784  */
6785 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6786 {
6787         unsigned int i;
6788         u32 val;
6789
6790         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6791                 switch (ofs) {
6792                 case RCVLSC_MODE:
6793                 case DMAC_MODE:
6794                 case MBFREE_MODE:
6795                 case BUFMGR_MODE:
6796                 case MEMARB_MODE:
6797                         /* We can't enable/disable these bits of the
6798                          * 5705/5750, just say success.
6799                          */
6800                         return 0;
6801
6802                 default:
6803                         break;
6804                 }
6805         }
6806
6807         val = tr32(ofs);
6808         val &= ~enable_bit;
6809         tw32_f(ofs, val);
6810
6811         for (i = 0; i < MAX_WAIT_CNT; i++) {
6812                 udelay(100);
6813                 val = tr32(ofs);
6814                 if ((val & enable_bit) == 0)
6815                         break;
6816         }
6817
6818         if (i == MAX_WAIT_CNT && !silent) {
6819                 dev_err(&tp->pdev->dev,
6820                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6821                         ofs, enable_bit);
6822                 return -ENODEV;
6823         }
6824
6825         return 0;
6826 }
6827
6828 /* tp->lock is held. */
6829 static int tg3_abort_hw(struct tg3 *tp, int silent)
6830 {
6831         int i, err;
6832
6833         tg3_disable_ints(tp);
6834
6835         tp->rx_mode &= ~RX_MODE_ENABLE;
6836         tw32_f(MAC_RX_MODE, tp->rx_mode);
6837         udelay(10);
6838
6839         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6840         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6841         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6842         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6843         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6844         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6845
6846         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6847         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6848         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6849         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6850         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6851         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6852         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6853
6854         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6855         tw32_f(MAC_MODE, tp->mac_mode);
6856         udelay(40);
6857
6858         tp->tx_mode &= ~TX_MODE_ENABLE;
6859         tw32_f(MAC_TX_MODE, tp->tx_mode);
6860
6861         for (i = 0; i < MAX_WAIT_CNT; i++) {
6862                 udelay(100);
6863                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6864                         break;
6865         }
6866         if (i >= MAX_WAIT_CNT) {
6867                 dev_err(&tp->pdev->dev,
6868                         "%s timed out, TX_MODE_ENABLE will not clear "
6869                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6870                 err |= -ENODEV;
6871         }
6872
6873         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6874         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6875         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6876
6877         tw32(FTQ_RESET, 0xffffffff);
6878         tw32(FTQ_RESET, 0x00000000);
6879
6880         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6881         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6882
6883         for (i = 0; i < tp->irq_cnt; i++) {
6884                 struct tg3_napi *tnapi = &tp->napi[i];
6885                 if (tnapi->hw_status)
6886                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6887         }
6888         if (tp->hw_stats)
6889                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6890
6891         return err;
6892 }
6893
6894 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6895 {
6896         int i;
6897         u32 apedata;
6898
6899         /* NCSI does not support APE events */
6900         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6901                 return;
6902
6903         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6904         if (apedata != APE_SEG_SIG_MAGIC)
6905                 return;
6906
6907         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6908         if (!(apedata & APE_FW_STATUS_READY))
6909                 return;
6910
6911         /* Wait for up to 1 millisecond for APE to service previous event. */
6912         for (i = 0; i < 10; i++) {
6913                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6914                         return;
6915
6916                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6917
6918                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6919                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6920                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6921
6922                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6923
6924                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6925                         break;
6926
6927                 udelay(100);
6928         }
6929
6930         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6931                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6932 }
6933
6934 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6935 {
6936         u32 event;
6937         u32 apedata;
6938
6939         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6940                 return;
6941
6942         switch (kind) {
6943         case RESET_KIND_INIT:
6944                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6945                                 APE_HOST_SEG_SIG_MAGIC);
6946                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6947                                 APE_HOST_SEG_LEN_MAGIC);
6948                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6949                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6950                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6951                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6952                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6953                                 APE_HOST_BEHAV_NO_PHYLOCK);
6954                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6955                                     TG3_APE_HOST_DRVR_STATE_START);
6956
6957                 event = APE_EVENT_STATUS_STATE_START;
6958                 break;
6959         case RESET_KIND_SHUTDOWN:
6960                 /* With the interface we are currently using,
6961                  * APE does not track driver state.  Wiping
6962                  * out the HOST SEGMENT SIGNATURE forces
6963                  * the APE to assume OS absent status.
6964                  */
6965                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6966
6967                 if (device_may_wakeup(&tp->pdev->dev) &&
6968                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6969                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6970                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6971                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6972                 } else
6973                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6974
6975                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6976
6977                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6978                 break;
6979         case RESET_KIND_SUSPEND:
6980                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6981                 break;
6982         default:
6983                 return;
6984         }
6985
6986         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6987
6988         tg3_ape_send_event(tp, event);
6989 }
6990
6991 /* tp->lock is held. */
6992 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6993 {
6994         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6995                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6996
6997         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6998                 switch (kind) {
6999                 case RESET_KIND_INIT:
7000                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7001                                       DRV_STATE_START);
7002                         break;
7003
7004                 case RESET_KIND_SHUTDOWN:
7005                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7006                                       DRV_STATE_UNLOAD);
7007                         break;
7008
7009                 case RESET_KIND_SUSPEND:
7010                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7011                                       DRV_STATE_SUSPEND);
7012                         break;
7013
7014                 default:
7015                         break;
7016                 }
7017         }
7018
7019         if (kind == RESET_KIND_INIT ||
7020             kind == RESET_KIND_SUSPEND)
7021                 tg3_ape_driver_state_change(tp, kind);
7022 }
7023
7024 /* tp->lock is held. */
7025 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
7026 {
7027         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
7028                 switch (kind) {
7029                 case RESET_KIND_INIT:
7030                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7031                                       DRV_STATE_START_DONE);
7032                         break;
7033
7034                 case RESET_KIND_SHUTDOWN:
7035                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7036                                       DRV_STATE_UNLOAD_DONE);
7037                         break;
7038
7039                 default:
7040                         break;
7041                 }
7042         }
7043
7044         if (kind == RESET_KIND_SHUTDOWN)
7045                 tg3_ape_driver_state_change(tp, kind);
7046 }
7047
7048 /* tp->lock is held. */
7049 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
7050 {
7051         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7052                 switch (kind) {
7053                 case RESET_KIND_INIT:
7054                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7055                                       DRV_STATE_START);
7056                         break;
7057
7058                 case RESET_KIND_SHUTDOWN:
7059                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7060                                       DRV_STATE_UNLOAD);
7061                         break;
7062
7063                 case RESET_KIND_SUSPEND:
7064                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7065                                       DRV_STATE_SUSPEND);
7066                         break;
7067
7068                 default:
7069                         break;
7070                 }
7071         }
7072 }
7073
7074 static int tg3_poll_fw(struct tg3 *tp)
7075 {
7076         int i;
7077         u32 val;
7078
7079         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7080                 /* Wait up to 20ms for init done. */
7081                 for (i = 0; i < 200; i++) {
7082                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
7083                                 return 0;
7084                         udelay(100);
7085                 }
7086                 return -ENODEV;
7087         }
7088
7089         /* Wait for firmware initialization to complete. */
7090         for (i = 0; i < 100000; i++) {
7091                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
7092                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
7093                         break;
7094                 udelay(10);
7095         }
7096
7097         /* Chip might not be fitted with firmware.  Some Sun onboard
7098          * parts are configured like that.  So don't signal the timeout
7099          * of the above loop as an error, but do report the lack of
7100          * running firmware once.
7101          */
7102         if (i >= 100000 &&
7103             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
7104                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
7105
7106                 netdev_info(tp->dev, "No firmware running\n");
7107         }
7108
7109         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7110                 /* The 57765 A0 needs a little more
7111                  * time to do some important work.
7112                  */
7113                 mdelay(10);
7114         }
7115
7116         return 0;
7117 }
7118
7119 /* Save PCI command register before chip reset */
7120 static void tg3_save_pci_state(struct tg3 *tp)
7121 {
7122         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7123 }
7124
7125 /* Restore PCI state after chip reset */
7126 static void tg3_restore_pci_state(struct tg3 *tp)
7127 {
7128         u32 val;
7129
7130         /* Re-enable indirect register accesses. */
7131         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7132                                tp->misc_host_ctrl);
7133
7134         /* Set MAX PCI retry to zero. */
7135         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7136         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7137             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
7138                 val |= PCISTATE_RETRY_SAME_DMA;
7139         /* Allow reads and writes to the APE register and memory space. */
7140         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7141                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7142                        PCISTATE_ALLOW_APE_SHMEM_WR |
7143                        PCISTATE_ALLOW_APE_PSPACE_WR;
7144         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7145
7146         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7147
7148         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7149                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7150                         pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7151                 else {
7152                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7153                                               tp->pci_cacheline_sz);
7154                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7155                                               tp->pci_lat_timer);
7156                 }
7157         }
7158
7159         /* Make sure PCI-X relaxed ordering bit is clear. */
7160         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7161                 u16 pcix_cmd;
7162
7163                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7164                                      &pcix_cmd);
7165                 pcix_cmd &= ~PCI_X_CMD_ERO;
7166                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7167                                       pcix_cmd);
7168         }
7169
7170         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7171
7172                 /* Chip reset on 5780 will reset MSI enable bit,
7173                  * so need to restore it.
7174                  */
7175                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7176                         u16 ctrl;
7177
7178                         pci_read_config_word(tp->pdev,
7179                                              tp->msi_cap + PCI_MSI_FLAGS,
7180                                              &ctrl);
7181                         pci_write_config_word(tp->pdev,
7182                                               tp->msi_cap + PCI_MSI_FLAGS,
7183                                               ctrl | PCI_MSI_FLAGS_ENABLE);
7184                         val = tr32(MSGINT_MODE);
7185                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7186                 }
7187         }
7188 }
7189
7190 static void tg3_stop_fw(struct tg3 *);
7191
7192 /* tp->lock is held. */
7193 static int tg3_chip_reset(struct tg3 *tp)
7194 {
7195         u32 val;
7196         void (*write_op)(struct tg3 *, u32, u32);
7197         int i, err;
7198
7199         tg3_nvram_lock(tp);
7200
7201         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7202
7203         /* No matching tg3_nvram_unlock() after this because
7204          * chip reset below will undo the nvram lock.
7205          */
7206         tp->nvram_lock_cnt = 0;
7207
7208         /* GRC_MISC_CFG core clock reset will clear the memory
7209          * enable bit in PCI register 4 and the MSI enable bit
7210          * on some chips, so we save relevant registers here.
7211          */
7212         tg3_save_pci_state(tp);
7213
7214         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7215             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7216                 tw32(GRC_FASTBOOT_PC, 0);
7217
7218         /*
7219          * We must avoid the readl() that normally takes place.
7220          * It locks machines, causes machine checks, and other
7221          * fun things.  So, temporarily disable the 5701
7222          * hardware workaround, while we do the reset.
7223          */
7224         write_op = tp->write32;
7225         if (write_op == tg3_write_flush_reg32)
7226                 tp->write32 = tg3_write32;
7227
7228         /* Prevent the irq handler from reading or writing PCI registers
7229          * during chip reset when the memory enable bit in the PCI command
7230          * register may be cleared.  The chip does not generate interrupt
7231          * at this time, but the irq handler may still be called due to irq
7232          * sharing or irqpoll.
7233          */
7234         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7235         for (i = 0; i < tp->irq_cnt; i++) {
7236                 struct tg3_napi *tnapi = &tp->napi[i];
7237                 if (tnapi->hw_status) {
7238                         tnapi->hw_status->status = 0;
7239                         tnapi->hw_status->status_tag = 0;
7240                 }
7241                 tnapi->last_tag = 0;
7242                 tnapi->last_irq_tag = 0;
7243         }
7244         smp_mb();
7245
7246         for (i = 0; i < tp->irq_cnt; i++)
7247                 synchronize_irq(tp->napi[i].irq_vec);
7248
7249         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7250                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7251                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7252         }
7253
7254         /* do the reset */
7255         val = GRC_MISC_CFG_CORECLK_RESET;
7256
7257         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7258                 /* Force PCIe 1.0a mode */
7259                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7260                     !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
7261                     tr32(TG3_PCIE_PHY_TSTCTL) ==
7262                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7263                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7264
7265                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7266                         tw32(GRC_MISC_CFG, (1 << 29));
7267                         val |= (1 << 29);
7268                 }
7269         }
7270
7271         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7272                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7273                 tw32(GRC_VCPU_EXT_CTRL,
7274                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7275         }
7276
7277         /* Manage gphy power for all CPMU absent PCIe devices. */
7278         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7279             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7280                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7281
7282         tw32(GRC_MISC_CFG, val);
7283
7284         /* restore 5701 hardware bug workaround write method */
7285         tp->write32 = write_op;
7286
7287         /* Unfortunately, we have to delay before the PCI read back.
7288          * Some 575X chips even will not respond to a PCI cfg access
7289          * when the reset command is given to the chip.
7290          *
7291          * How do these hardware designers expect things to work
7292          * properly if the PCI write is posted for a long period
7293          * of time?  It is always necessary to have some method by
7294          * which a register read back can occur to push the write
7295          * out which does the reset.
7296          *
7297          * For most tg3 variants the trick below was working.
7298          * Ho hum...
7299          */
7300         udelay(120);
7301
7302         /* Flush PCI posted writes.  The normal MMIO registers
7303          * are inaccessible at this time so this is the only
7304          * way to make this reliably (actually, this is no longer
7305          * the case, see above).  I tried to use indirect
7306          * register read/write but this upset some 5701 variants.
7307          */
7308         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7309
7310         udelay(120);
7311
7312         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7313                 u16 val16;
7314
7315                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7316                         int i;
7317                         u32 cfg_val;
7318
7319                         /* Wait for link training to complete.  */
7320                         for (i = 0; i < 5000; i++)
7321                                 udelay(100);
7322
7323                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7324                         pci_write_config_dword(tp->pdev, 0xc4,
7325                                                cfg_val | (1 << 15));
7326                 }
7327
7328                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7329                 pci_read_config_word(tp->pdev,
7330                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7331                                      &val16);
7332                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7333                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7334                 /*
7335                  * Older PCIe devices only support the 128 byte
7336                  * MPS setting.  Enforce the restriction.
7337                  */
7338                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7339                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7340                 pci_write_config_word(tp->pdev,
7341                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7342                                       val16);
7343
7344                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7345
7346                 /* Clear error status */
7347                 pci_write_config_word(tp->pdev,
7348                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7349                                       PCI_EXP_DEVSTA_CED |
7350                                       PCI_EXP_DEVSTA_NFED |
7351                                       PCI_EXP_DEVSTA_FED |
7352                                       PCI_EXP_DEVSTA_URD);
7353         }
7354
7355         tg3_restore_pci_state(tp);
7356
7357         tp->tg3_flags &= ~(TG3_FLAG_CHIP_RESETTING |
7358                            TG3_FLAG_ERROR_PROCESSED);
7359
7360         val = 0;
7361         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7362                 val = tr32(MEMARB_MODE);
7363         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7364
7365         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7366                 tg3_stop_fw(tp);
7367                 tw32(0x5000, 0x400);
7368         }
7369
7370         tw32(GRC_MODE, tp->grc_mode);
7371
7372         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7373                 val = tr32(0xc4);
7374
7375                 tw32(0xc4, val | (1 << 15));
7376         }
7377
7378         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7379             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7380                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7381                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7382                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7383                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7384         }
7385
7386         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7387                 tp->mac_mode = MAC_MODE_APE_TX_EN |
7388                                MAC_MODE_APE_RX_EN |
7389                                MAC_MODE_TDE_ENABLE;
7390
7391         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7392                 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
7393                 val = tp->mac_mode;
7394         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7395                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7396                 val = tp->mac_mode;
7397         } else
7398                 val = 0;
7399
7400         tw32_f(MAC_MODE, val);
7401         udelay(40);
7402
7403         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7404
7405         err = tg3_poll_fw(tp);
7406         if (err)
7407                 return err;
7408
7409         tg3_mdio_start(tp);
7410
7411         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7412             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7413             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7414             !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
7415                 val = tr32(0x7c00);
7416
7417                 tw32(0x7c00, val | (1 << 25));
7418         }
7419
7420         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7421                 val = tr32(TG3_CPMU_CLCK_ORIDE);
7422                 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7423         }
7424
7425         /* Reprobe ASF enable state.  */
7426         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7427         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7428         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7429         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7430                 u32 nic_cfg;
7431
7432                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7433                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7434                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7435                         tp->last_event_jiffies = jiffies;
7436                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7437                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7438                 }
7439         }
7440
7441         return 0;
7442 }
7443
7444 /* tp->lock is held. */
7445 static void tg3_stop_fw(struct tg3 *tp)
7446 {
7447         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7448            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7449                 /* Wait for RX cpu to ACK the previous event. */
7450                 tg3_wait_for_event_ack(tp);
7451
7452                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7453
7454                 tg3_generate_fw_event(tp);
7455
7456                 /* Wait for RX cpu to ACK this event. */
7457                 tg3_wait_for_event_ack(tp);
7458         }
7459 }
7460
7461 /* tp->lock is held. */
7462 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7463 {
7464         int err;
7465
7466         tg3_stop_fw(tp);
7467
7468         tg3_write_sig_pre_reset(tp, kind);
7469
7470         tg3_abort_hw(tp, silent);
7471         err = tg3_chip_reset(tp);
7472
7473         __tg3_set_mac_addr(tp, 0);
7474
7475         tg3_write_sig_legacy(tp, kind);
7476         tg3_write_sig_post_reset(tp, kind);
7477
7478         if (err)
7479                 return err;
7480
7481         return 0;
7482 }
7483
7484 #define RX_CPU_SCRATCH_BASE     0x30000
7485 #define RX_CPU_SCRATCH_SIZE     0x04000
7486 #define TX_CPU_SCRATCH_BASE     0x34000
7487 #define TX_CPU_SCRATCH_SIZE     0x04000
7488
7489 /* tp->lock is held. */
7490 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7491 {
7492         int i;
7493
7494         BUG_ON(offset == TX_CPU_BASE &&
7495             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7496
7497         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7498                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7499
7500                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7501                 return 0;
7502         }
7503         if (offset == RX_CPU_BASE) {
7504                 for (i = 0; i < 10000; i++) {
7505                         tw32(offset + CPU_STATE, 0xffffffff);
7506                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7507                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7508                                 break;
7509                 }
7510
7511                 tw32(offset + CPU_STATE, 0xffffffff);
7512                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7513                 udelay(10);
7514         } else {
7515                 for (i = 0; i < 10000; i++) {
7516                         tw32(offset + CPU_STATE, 0xffffffff);
7517                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7518                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7519                                 break;
7520                 }
7521         }
7522
7523         if (i >= 10000) {
7524                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7525                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7526                 return -ENODEV;
7527         }
7528
7529         /* Clear firmware's nvram arbitration. */
7530         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7531                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7532         return 0;
7533 }
7534
7535 struct fw_info {
7536         unsigned int fw_base;
7537         unsigned int fw_len;
7538         const __be32 *fw_data;
7539 };
7540
7541 /* tp->lock is held. */
7542 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7543                                  int cpu_scratch_size, struct fw_info *info)
7544 {
7545         int err, lock_err, i;
7546         void (*write_op)(struct tg3 *, u32, u32);
7547
7548         if (cpu_base == TX_CPU_BASE &&
7549             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7550                 netdev_err(tp->dev,
7551                            "%s: Trying to load TX cpu firmware which is 5705\n",
7552                            __func__);
7553                 return -EINVAL;
7554         }
7555
7556         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7557                 write_op = tg3_write_mem;
7558         else
7559                 write_op = tg3_write_indirect_reg32;
7560
7561         /* It is possible that bootcode is still loading at this point.
7562          * Get the nvram lock first before halting the cpu.
7563          */
7564         lock_err = tg3_nvram_lock(tp);
7565         err = tg3_halt_cpu(tp, cpu_base);
7566         if (!lock_err)
7567                 tg3_nvram_unlock(tp);
7568         if (err)
7569                 goto out;
7570
7571         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7572                 write_op(tp, cpu_scratch_base + i, 0);
7573         tw32(cpu_base + CPU_STATE, 0xffffffff);
7574         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7575         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7576                 write_op(tp, (cpu_scratch_base +
7577                               (info->fw_base & 0xffff) +
7578                               (i * sizeof(u32))),
7579                               be32_to_cpu(info->fw_data[i]));
7580
7581         err = 0;
7582
7583 out:
7584         return err;
7585 }
7586
7587 /* tp->lock is held. */
7588 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7589 {
7590         struct fw_info info;
7591         const __be32 *fw_data;
7592         int err, i;
7593
7594         fw_data = (void *)tp->fw->data;
7595
7596         /* Firmware blob starts with version numbers, followed by
7597            start address and length. We are setting complete length.
7598            length = end_address_of_bss - start_address_of_text.
7599            Remainder is the blob to be loaded contiguously
7600            from start address. */
7601
7602         info.fw_base = be32_to_cpu(fw_data[1]);
7603         info.fw_len = tp->fw->size - 12;
7604         info.fw_data = &fw_data[3];
7605
7606         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7607                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7608                                     &info);
7609         if (err)
7610                 return err;
7611
7612         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7613                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7614                                     &info);
7615         if (err)
7616                 return err;
7617
7618         /* Now startup only the RX cpu. */
7619         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7620         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7621
7622         for (i = 0; i < 5; i++) {
7623                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7624                         break;
7625                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7626                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7627                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7628                 udelay(1000);
7629         }
7630         if (i >= 5) {
7631                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7632                            "should be %08x\n", __func__,
7633                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7634                 return -ENODEV;
7635         }
7636         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7637         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7638
7639         return 0;
7640 }
7641
7642 /* 5705 needs a special version of the TSO firmware.  */
7643
7644 /* tp->lock is held. */
7645 static int tg3_load_tso_firmware(struct tg3 *tp)
7646 {
7647         struct fw_info info;
7648         const __be32 *fw_data;
7649         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7650         int err, i;
7651
7652         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7653                 return 0;
7654
7655         fw_data = (void *)tp->fw->data;
7656
7657         /* Firmware blob starts with version numbers, followed by
7658            start address and length. We are setting complete length.
7659            length = end_address_of_bss - start_address_of_text.
7660            Remainder is the blob to be loaded contiguously
7661            from start address. */
7662
7663         info.fw_base = be32_to_cpu(fw_data[1]);
7664         cpu_scratch_size = tp->fw_len;
7665         info.fw_len = tp->fw->size - 12;
7666         info.fw_data = &fw_data[3];
7667
7668         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7669                 cpu_base = RX_CPU_BASE;
7670                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7671         } else {
7672                 cpu_base = TX_CPU_BASE;
7673                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7674                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7675         }
7676
7677         err = tg3_load_firmware_cpu(tp, cpu_base,
7678                                     cpu_scratch_base, cpu_scratch_size,
7679                                     &info);
7680         if (err)
7681                 return err;
7682
7683         /* Now startup the cpu. */
7684         tw32(cpu_base + CPU_STATE, 0xffffffff);
7685         tw32_f(cpu_base + CPU_PC, info.fw_base);
7686
7687         for (i = 0; i < 5; i++) {
7688                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7689                         break;
7690                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7691                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7692                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7693                 udelay(1000);
7694         }
7695         if (i >= 5) {
7696                 netdev_err(tp->dev,
7697                            "%s fails to set CPU PC, is %08x should be %08x\n",
7698                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7699                 return -ENODEV;
7700         }
7701         tw32(cpu_base + CPU_STATE, 0xffffffff);
7702         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7703         return 0;
7704 }
7705
7706
7707 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7708 {
7709         struct tg3 *tp = netdev_priv(dev);
7710         struct sockaddr *addr = p;
7711         int err = 0, skip_mac_1 = 0;
7712
7713         if (!is_valid_ether_addr(addr->sa_data))
7714                 return -EINVAL;
7715
7716         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7717
7718         if (!netif_running(dev))
7719                 return 0;
7720
7721         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7722                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7723
7724                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7725                 addr0_low = tr32(MAC_ADDR_0_LOW);
7726                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7727                 addr1_low = tr32(MAC_ADDR_1_LOW);
7728
7729                 /* Skip MAC addr 1 if ASF is using it. */
7730                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7731                     !(addr1_high == 0 && addr1_low == 0))
7732                         skip_mac_1 = 1;
7733         }
7734         spin_lock_bh(&tp->lock);
7735         __tg3_set_mac_addr(tp, skip_mac_1);
7736         spin_unlock_bh(&tp->lock);
7737
7738         return err;
7739 }
7740
7741 /* tp->lock is held. */
7742 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7743                            dma_addr_t mapping, u32 maxlen_flags,
7744                            u32 nic_addr)
7745 {
7746         tg3_write_mem(tp,
7747                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7748                       ((u64) mapping >> 32));
7749         tg3_write_mem(tp,
7750                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7751                       ((u64) mapping & 0xffffffff));
7752         tg3_write_mem(tp,
7753                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7754                        maxlen_flags);
7755
7756         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7757                 tg3_write_mem(tp,
7758                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7759                               nic_addr);
7760 }
7761
7762 static void __tg3_set_rx_mode(struct net_device *);
7763 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7764 {
7765         int i;
7766
7767         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7768                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7769                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7770                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7771         } else {
7772                 tw32(HOSTCC_TXCOL_TICKS, 0);
7773                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7774                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7775         }
7776
7777         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7778                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7779                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7780                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7781         } else {
7782                 tw32(HOSTCC_RXCOL_TICKS, 0);
7783                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7784                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7785         }
7786
7787         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7788                 u32 val = ec->stats_block_coalesce_usecs;
7789
7790                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7791                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7792
7793                 if (!netif_carrier_ok(tp->dev))
7794                         val = 0;
7795
7796                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7797         }
7798
7799         for (i = 0; i < tp->irq_cnt - 1; i++) {
7800                 u32 reg;
7801
7802                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7803                 tw32(reg, ec->rx_coalesce_usecs);
7804                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7805                 tw32(reg, ec->rx_max_coalesced_frames);
7806                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7807                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7808
7809                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7810                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7811                         tw32(reg, ec->tx_coalesce_usecs);
7812                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7813                         tw32(reg, ec->tx_max_coalesced_frames);
7814                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7815                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7816                 }
7817         }
7818
7819         for (; i < tp->irq_max - 1; i++) {
7820                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7821                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7822                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7823
7824                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7825                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7826                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7827                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7828                 }
7829         }
7830 }
7831
7832 /* tp->lock is held. */
7833 static void tg3_rings_reset(struct tg3 *tp)
7834 {
7835         int i;
7836         u32 stblk, txrcb, rxrcb, limit;
7837         struct tg3_napi *tnapi = &tp->napi[0];
7838
7839         /* Disable all transmit rings but the first. */
7840         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7841                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7842         else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7843                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7844         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7845                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7846         else
7847                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7848
7849         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7850              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7851                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7852                               BDINFO_FLAGS_DISABLED);
7853
7854
7855         /* Disable all receive return rings but the first. */
7856         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7857                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7858         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7859                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7860         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7861                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7862                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7863         else
7864                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7865
7866         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7867              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7868                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7869                               BDINFO_FLAGS_DISABLED);
7870
7871         /* Disable interrupts */
7872         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7873
7874         /* Zero mailbox registers. */
7875         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7876                 for (i = 1; i < tp->irq_max; i++) {
7877                         tp->napi[i].tx_prod = 0;
7878                         tp->napi[i].tx_cons = 0;
7879                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7880                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7881                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7882                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7883                 }
7884                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7885                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7886         } else {
7887                 tp->napi[0].tx_prod = 0;
7888                 tp->napi[0].tx_cons = 0;
7889                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7890                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7891         }
7892
7893         /* Make sure the NIC-based send BD rings are disabled. */
7894         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7895                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7896                 for (i = 0; i < 16; i++)
7897                         tw32_tx_mbox(mbox + i * 8, 0);
7898         }
7899
7900         txrcb = NIC_SRAM_SEND_RCB;
7901         rxrcb = NIC_SRAM_RCV_RET_RCB;
7902
7903         /* Clear status block in ram. */
7904         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7905
7906         /* Set status block DMA address */
7907         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7908              ((u64) tnapi->status_mapping >> 32));
7909         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7910              ((u64) tnapi->status_mapping & 0xffffffff));
7911
7912         if (tnapi->tx_ring) {
7913                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7914                                (TG3_TX_RING_SIZE <<
7915                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7916                                NIC_SRAM_TX_BUFFER_DESC);
7917                 txrcb += TG3_BDINFO_SIZE;
7918         }
7919
7920         if (tnapi->rx_rcb) {
7921                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7922                                (tp->rx_ret_ring_mask + 1) <<
7923                                 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7924                 rxrcb += TG3_BDINFO_SIZE;
7925         }
7926
7927         stblk = HOSTCC_STATBLCK_RING1;
7928
7929         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7930                 u64 mapping = (u64)tnapi->status_mapping;
7931                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7932                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7933
7934                 /* Clear status block in ram. */
7935                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7936
7937                 if (tnapi->tx_ring) {
7938                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7939                                        (TG3_TX_RING_SIZE <<
7940                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7941                                        NIC_SRAM_TX_BUFFER_DESC);
7942                         txrcb += TG3_BDINFO_SIZE;
7943                 }
7944
7945                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7946                                ((tp->rx_ret_ring_mask + 1) <<
7947                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7948
7949                 stblk += 8;
7950                 rxrcb += TG3_BDINFO_SIZE;
7951         }
7952 }
7953
7954 /* tp->lock is held. */
7955 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7956 {
7957         u32 val, rdmac_mode;
7958         int i, err, limit;
7959         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7960
7961         tg3_disable_ints(tp);
7962
7963         tg3_stop_fw(tp);
7964
7965         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7966
7967         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7968                 tg3_abort_hw(tp, 1);
7969
7970         /* Enable MAC control of LPI */
7971         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7972                 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7973                        TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7974                        TG3_CPMU_EEE_LNKIDL_UART_IDL);
7975
7976                 tw32_f(TG3_CPMU_EEE_CTRL,
7977                        TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7978
7979                 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7980                       TG3_CPMU_EEEMD_LPI_IN_TX |
7981                       TG3_CPMU_EEEMD_LPI_IN_RX |
7982                       TG3_CPMU_EEEMD_EEE_ENABLE;
7983
7984                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7985                         val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
7986
7987                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7988                         val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
7989
7990                 tw32_f(TG3_CPMU_EEE_MODE, val);
7991
7992                 tw32_f(TG3_CPMU_EEE_DBTMR1,
7993                        TG3_CPMU_DBTMR1_PCIEXIT_2047US |
7994                        TG3_CPMU_DBTMR1_LNKIDLE_2047US);
7995
7996                 tw32_f(TG3_CPMU_EEE_DBTMR2,
7997                        TG3_CPMU_DBTMR2_APE_TX_2047US |
7998                        TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
7999         }
8000
8001         if (reset_phy)
8002                 tg3_phy_reset(tp);
8003
8004         err = tg3_chip_reset(tp);
8005         if (err)
8006                 return err;
8007
8008         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8009
8010         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
8011                 val = tr32(TG3_CPMU_CTRL);
8012                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8013                 tw32(TG3_CPMU_CTRL, val);
8014
8015                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8016                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8017                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8018                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8019
8020                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8021                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8022                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8023                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8024
8025                 val = tr32(TG3_CPMU_HST_ACC);
8026                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8027                 val |= CPMU_HST_ACC_MACCLK_6_25;
8028                 tw32(TG3_CPMU_HST_ACC, val);
8029         }
8030
8031         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8032                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8033                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8034                        PCIE_PWR_MGMT_L1_THRESH_4MS;
8035                 tw32(PCIE_PWR_MGMT_THRESH, val);
8036
8037                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8038                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8039
8040                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
8041
8042                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8043                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8044         }
8045
8046         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
8047                 u32 grc_mode = tr32(GRC_MODE);
8048
8049                 /* Access the lower 1K of PL PCIE block registers. */
8050                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8051                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8052
8053                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8054                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8055                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8056
8057                 tw32(GRC_MODE, grc_mode);
8058         }
8059
8060         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
8061                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8062                         u32 grc_mode = tr32(GRC_MODE);
8063
8064                         /* Access the lower 1K of PL PCIE block registers. */
8065                         val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8066                         tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8067
8068                         val = tr32(TG3_PCIE_TLDLPL_PORT +
8069                                    TG3_PCIE_PL_LO_PHYCTL5);
8070                         tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8071                              val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
8072
8073                         tw32(GRC_MODE, grc_mode);
8074                 }
8075
8076                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8077                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8078                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8079                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8080         }
8081
8082         /* This works around an issue with Athlon chipsets on
8083          * B3 tigon3 silicon.  This bit has no effect on any
8084          * other revision.  But do not set this on PCI Express
8085          * chips and don't even touch the clocks if the CPMU is present.
8086          */
8087         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
8088                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
8089                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8090                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8091         }
8092
8093         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8094             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
8095                 val = tr32(TG3PCI_PCISTATE);
8096                 val |= PCISTATE_RETRY_SAME_DMA;
8097                 tw32(TG3PCI_PCISTATE, val);
8098         }
8099
8100         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
8101                 /* Allow reads and writes to the
8102                  * APE register and memory space.
8103                  */
8104                 val = tr32(TG3PCI_PCISTATE);
8105                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8106                        PCISTATE_ALLOW_APE_SHMEM_WR |
8107                        PCISTATE_ALLOW_APE_PSPACE_WR;
8108                 tw32(TG3PCI_PCISTATE, val);
8109         }
8110
8111         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8112                 /* Enable some hw fixes.  */
8113                 val = tr32(TG3PCI_MSI_DATA);
8114                 val |= (1 << 26) | (1 << 28) | (1 << 29);
8115                 tw32(TG3PCI_MSI_DATA, val);
8116         }
8117
8118         /* Descriptor ring init may make accesses to the
8119          * NIC SRAM area to setup the TX descriptors, so we
8120          * can only do this after the hardware has been
8121          * successfully reset.
8122          */
8123         err = tg3_init_rings(tp);
8124         if (err)
8125                 return err;
8126
8127         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
8128                 val = tr32(TG3PCI_DMA_RW_CTRL) &
8129                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8130                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8131                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8132                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8133         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8134                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8135                 /* This value is determined during the probe time DMA
8136                  * engine test, tg3_test_dma.
8137                  */
8138                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8139         }
8140
8141         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8142                           GRC_MODE_4X_NIC_SEND_RINGS |
8143                           GRC_MODE_NO_TX_PHDR_CSUM |
8144                           GRC_MODE_NO_RX_PHDR_CSUM);
8145         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8146
8147         /* Pseudo-header checksum is done by hardware logic and not
8148          * the offload processers, so make the chip do the pseudo-
8149          * header checksums on receive.  For transmit it is more
8150          * convenient to do the pseudo-header checksum in software
8151          * as Linux does that on transmit for us in all cases.
8152          */
8153         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8154
8155         tw32(GRC_MODE,
8156              tp->grc_mode |
8157              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8158
8159         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
8160         val = tr32(GRC_MISC_CFG);
8161         val &= ~0xff;
8162         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8163         tw32(GRC_MISC_CFG, val);
8164
8165         /* Initialize MBUF/DESC pool. */
8166         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8167                 /* Do nothing.  */
8168         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8169                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8170                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8171                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8172                 else
8173                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8174                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8175                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8176         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8177                 int fw_len;
8178
8179                 fw_len = tp->fw_len;
8180                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8181                 tw32(BUFMGR_MB_POOL_ADDR,
8182                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8183                 tw32(BUFMGR_MB_POOL_SIZE,
8184                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8185         }
8186
8187         if (tp->dev->mtu <= ETH_DATA_LEN) {
8188                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8189                      tp->bufmgr_config.mbuf_read_dma_low_water);
8190                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8191                      tp->bufmgr_config.mbuf_mac_rx_low_water);
8192                 tw32(BUFMGR_MB_HIGH_WATER,
8193                      tp->bufmgr_config.mbuf_high_water);
8194         } else {
8195                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8196                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8197                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8198                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8199                 tw32(BUFMGR_MB_HIGH_WATER,
8200                      tp->bufmgr_config.mbuf_high_water_jumbo);
8201         }
8202         tw32(BUFMGR_DMA_LOW_WATER,
8203              tp->bufmgr_config.dma_low_water);
8204         tw32(BUFMGR_DMA_HIGH_WATER,
8205              tp->bufmgr_config.dma_high_water);
8206
8207         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8208         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8209                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8210         tw32(BUFMGR_MODE, val);
8211         for (i = 0; i < 2000; i++) {
8212                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8213                         break;
8214                 udelay(10);
8215         }
8216         if (i >= 2000) {
8217                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8218                 return -ENODEV;
8219         }
8220
8221         /* Setup replenish threshold. */
8222         val = tp->rx_pending / 8;
8223         if (val == 0)
8224                 val = 1;
8225         else if (val > tp->rx_std_max_post)
8226                 val = tp->rx_std_max_post;
8227         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8228                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8229                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8230
8231                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8232                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8233         }
8234
8235         tw32(RCVBDI_STD_THRESH, val);
8236
8237         /* Initialize TG3_BDINFO's at:
8238          *  RCVDBDI_STD_BD:     standard eth size rx ring
8239          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
8240          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
8241          *
8242          * like so:
8243          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
8244          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
8245          *                              ring attribute flags
8246          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
8247          *
8248          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8249          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8250          *
8251          * The size of each ring is fixed in the firmware, but the location is
8252          * configurable.
8253          */
8254         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8255              ((u64) tpr->rx_std_mapping >> 32));
8256         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8257              ((u64) tpr->rx_std_mapping & 0xffffffff));
8258         if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
8259                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8260                      NIC_SRAM_RX_BUFFER_DESC);
8261
8262         /* Disable the mini ring */
8263         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8264                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8265                      BDINFO_FLAGS_DISABLED);
8266
8267         /* Program the jumbo buffer descriptor ring control
8268          * blocks on those devices that have them.
8269          */
8270         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8271             ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8272             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) {
8273                 /* Setup replenish threshold. */
8274                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8275
8276                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8277                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8278                              ((u64) tpr->rx_jmb_mapping >> 32));
8279                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8280                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8281                         val = TG3_RX_JMB_RING_SIZE(tp) <<
8282                               BDINFO_FLAGS_MAXLEN_SHIFT;
8283                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8284                              val | BDINFO_FLAGS_USE_EXT_RECV);
8285                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8286                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8287                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8288                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8289                 } else {
8290                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8291                              BDINFO_FLAGS_DISABLED);
8292                 }
8293
8294                 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
8295                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8296                                 val = TG3_RX_STD_MAX_SIZE_5700;
8297                         else
8298                                 val = TG3_RX_STD_MAX_SIZE_5717;
8299                         val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8300                         val |= (TG3_RX_STD_DMA_SZ << 2);
8301                 } else
8302                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8303         } else
8304                 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8305
8306         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8307
8308         tpr->rx_std_prod_idx = tp->rx_pending;
8309         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8310
8311         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8312                           tp->rx_jumbo_pending : 0;
8313         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8314
8315         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
8316                 tw32(STD_REPLENISH_LWM, 32);
8317                 tw32(JMB_REPLENISH_LWM, 16);
8318         }
8319
8320         tg3_rings_reset(tp);
8321
8322         /* Initialize MAC address and backoff seed. */
8323         __tg3_set_mac_addr(tp, 0);
8324
8325         /* MTU + ethernet header + FCS + optional VLAN tag */
8326         tw32(MAC_RX_MTU_SIZE,
8327              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8328
8329         /* The slot time is changed by tg3_setup_phy if we
8330          * run at gigabit with half duplex.
8331          */
8332         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8333               (6 << TX_LENGTHS_IPG_SHIFT) |
8334               (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8335
8336         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8337                 val |= tr32(MAC_TX_LENGTHS) &
8338                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
8339                         TX_LENGTHS_CNT_DWN_VAL_MSK);
8340
8341         tw32(MAC_TX_LENGTHS, val);
8342
8343         /* Receive rules. */
8344         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8345         tw32(RCVLPC_CONFIG, 0x0181);
8346
8347         /* Calculate RDMAC_MODE setting early, we need it to determine
8348          * the RCVLPC_STATE_ENABLE mask.
8349          */
8350         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8351                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8352                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8353                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8354                       RDMAC_MODE_LNGREAD_ENAB);
8355
8356         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8357                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8358
8359         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8360             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8361             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8362                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8363                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8364                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8365
8366         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8367             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8368                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8369                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8370                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8371                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8372                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8373                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8374                 }
8375         }
8376
8377         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8378                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8379
8380         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8381                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8382
8383         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8384             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8385             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8386                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8387
8388         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8389                 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8390
8391         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8392             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8393             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8394             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8395             (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
8396                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8397                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8398                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8399                         val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8400                                  TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8401                                  TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8402                         val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8403                                TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8404                                TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8405                 }
8406                 tw32(TG3_RDMA_RSRVCTRL_REG,
8407                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8408         }
8409
8410         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8411             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8412                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8413                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8414                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8415                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8416         }
8417
8418         /* Receive/send statistics. */
8419         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8420                 val = tr32(RCVLPC_STATS_ENABLE);
8421                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8422                 tw32(RCVLPC_STATS_ENABLE, val);
8423         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8424                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8425                 val = tr32(RCVLPC_STATS_ENABLE);
8426                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8427                 tw32(RCVLPC_STATS_ENABLE, val);
8428         } else {
8429                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8430         }
8431         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8432         tw32(SNDDATAI_STATSENAB, 0xffffff);
8433         tw32(SNDDATAI_STATSCTRL,
8434              (SNDDATAI_SCTRL_ENABLE |
8435               SNDDATAI_SCTRL_FASTUPD));
8436
8437         /* Setup host coalescing engine. */
8438         tw32(HOSTCC_MODE, 0);
8439         for (i = 0; i < 2000; i++) {
8440                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8441                         break;
8442                 udelay(10);
8443         }
8444
8445         __tg3_set_coalesce(tp, &tp->coal);
8446
8447         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8448                 /* Status/statistics block address.  See tg3_timer,
8449                  * the tg3_periodic_fetch_stats call there, and
8450                  * tg3_get_stats to see how this works for 5705/5750 chips.
8451                  */
8452                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8453                      ((u64) tp->stats_mapping >> 32));
8454                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8455                      ((u64) tp->stats_mapping & 0xffffffff));
8456                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8457
8458                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8459
8460                 /* Clear statistics and status block memory areas */
8461                 for (i = NIC_SRAM_STATS_BLK;
8462                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8463                      i += sizeof(u32)) {
8464                         tg3_write_mem(tp, i, 0);
8465                         udelay(40);
8466                 }
8467         }
8468
8469         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8470
8471         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8472         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8473         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8474                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8475
8476         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8477                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8478                 /* reset to prevent losing 1st rx packet intermittently */
8479                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8480                 udelay(10);
8481         }
8482
8483         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8484                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8485         else
8486                 tp->mac_mode = 0;
8487         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8488                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8489         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8490             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8491             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8492                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8493         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8494         udelay(40);
8495
8496         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8497          * If TG3_FLG2_IS_NIC is zero, we should read the
8498          * register to preserve the GPIO settings for LOMs. The GPIOs,
8499          * whether used as inputs or outputs, are set by boot code after
8500          * reset.
8501          */
8502         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8503                 u32 gpio_mask;
8504
8505                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8506                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8507                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8508
8509                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8510                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8511                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8512
8513                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8514                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8515
8516                 tp->grc_local_ctrl &= ~gpio_mask;
8517                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8518
8519                 /* GPIO1 must be driven high for eeprom write protect */
8520                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8521                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8522                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8523         }
8524         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8525         udelay(100);
8526
8527         if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
8528                 tp->irq_cnt > 1) {
8529                 val = tr32(MSGINT_MODE);
8530                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8531                 tw32(MSGINT_MODE, val);
8532         }
8533
8534         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8535                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8536                 udelay(40);
8537         }
8538
8539         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8540                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8541                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8542                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8543                WDMAC_MODE_LNGREAD_ENAB);
8544
8545         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8546             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8547                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8548                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8549                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8550                         /* nothing */
8551                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8552                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8553                         val |= WDMAC_MODE_RX_ACCEL;
8554                 }
8555         }
8556
8557         /* Enable host coalescing bug fix */
8558         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8559                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8560
8561         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8562                 val |= WDMAC_MODE_BURST_ALL_DATA;
8563
8564         tw32_f(WDMAC_MODE, val);
8565         udelay(40);
8566
8567         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8568                 u16 pcix_cmd;
8569
8570                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8571                                      &pcix_cmd);
8572                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8573                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8574                         pcix_cmd |= PCI_X_CMD_READ_2K;
8575                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8576                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8577                         pcix_cmd |= PCI_X_CMD_READ_2K;
8578                 }
8579                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8580                                       pcix_cmd);
8581         }
8582
8583         tw32_f(RDMAC_MODE, rdmac_mode);
8584         udelay(40);
8585
8586         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8587         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8588                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8589
8590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8591                 tw32(SNDDATAC_MODE,
8592                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8593         else
8594                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8595
8596         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8597         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8598         val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8599         if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
8600                 val |= RCVDBDI_MODE_LRG_RING_SZ;
8601         tw32(RCVDBDI_MODE, val);
8602         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8603         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8604                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8605         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8606         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8607                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8608         tw32(SNDBDI_MODE, val);
8609         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8610
8611         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8612                 err = tg3_load_5701_a0_firmware_fix(tp);
8613                 if (err)
8614                         return err;
8615         }
8616
8617         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8618                 err = tg3_load_tso_firmware(tp);
8619                 if (err)
8620                         return err;
8621         }
8622
8623         tp->tx_mode = TX_MODE_ENABLE;
8624
8625         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8626             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8627                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8628
8629         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8630                 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8631                 tp->tx_mode &= ~val;
8632                 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8633         }
8634
8635         tw32_f(MAC_TX_MODE, tp->tx_mode);
8636         udelay(100);
8637
8638         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8639                 u32 reg = MAC_RSS_INDIR_TBL_0;
8640                 u8 *ent = (u8 *)&val;
8641
8642                 /* Setup the indirection table */
8643                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8644                         int idx = i % sizeof(val);
8645
8646                         ent[idx] = i % (tp->irq_cnt - 1);
8647                         if (idx == sizeof(val) - 1) {
8648                                 tw32(reg, val);
8649                                 reg += 4;
8650                         }
8651                 }
8652
8653                 /* Setup the "secret" hash key. */
8654                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8655                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8656                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8657                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8658                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8659                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8660                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8661                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8662                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8663                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8664         }
8665
8666         tp->rx_mode = RX_MODE_ENABLE;
8667         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8668                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8669
8670         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8671                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8672                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8673                                RX_MODE_RSS_IPV6_HASH_EN |
8674                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8675                                RX_MODE_RSS_IPV4_HASH_EN |
8676                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8677
8678         tw32_f(MAC_RX_MODE, tp->rx_mode);
8679         udelay(10);
8680
8681         tw32(MAC_LED_CTRL, tp->led_ctrl);
8682
8683         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8684         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8685                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8686                 udelay(10);
8687         }
8688         tw32_f(MAC_RX_MODE, tp->rx_mode);
8689         udelay(10);
8690
8691         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8692                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8693                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8694                         /* Set drive transmission level to 1.2V  */
8695                         /* only if the signal pre-emphasis bit is not set  */
8696                         val = tr32(MAC_SERDES_CFG);
8697                         val &= 0xfffff000;
8698                         val |= 0x880;
8699                         tw32(MAC_SERDES_CFG, val);
8700                 }
8701                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8702                         tw32(MAC_SERDES_CFG, 0x616000);
8703         }
8704
8705         /* Prevent chip from dropping frames when flow control
8706          * is enabled.
8707          */
8708         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8709                 val = 1;
8710         else
8711                 val = 2;
8712         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8713
8714         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8715             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8716                 /* Use hardware link auto-negotiation */
8717                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8718         }
8719
8720         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8721             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8722                 u32 tmp;
8723
8724                 tmp = tr32(SERDES_RX_CTRL);
8725                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8726                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8727                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8728                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8729         }
8730
8731         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8732                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8733                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8734                         tp->link_config.speed = tp->link_config.orig_speed;
8735                         tp->link_config.duplex = tp->link_config.orig_duplex;
8736                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8737                 }
8738
8739                 err = tg3_setup_phy(tp, 0);
8740                 if (err)
8741                         return err;
8742
8743                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8744                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8745                         u32 tmp;
8746
8747                         /* Clear CRC stats. */
8748                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8749                                 tg3_writephy(tp, MII_TG3_TEST1,
8750                                              tmp | MII_TG3_TEST1_CRC_EN);
8751                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8752                         }
8753                 }
8754         }
8755
8756         __tg3_set_rx_mode(tp->dev);
8757
8758         /* Initialize receive rules. */
8759         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8760         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8761         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8762         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8763
8764         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8765             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8766                 limit = 8;
8767         else
8768                 limit = 16;
8769         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8770                 limit -= 4;
8771         switch (limit) {
8772         case 16:
8773                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8774         case 15:
8775                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8776         case 14:
8777                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8778         case 13:
8779                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8780         case 12:
8781                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8782         case 11:
8783                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8784         case 10:
8785                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8786         case 9:
8787                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8788         case 8:
8789                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8790         case 7:
8791                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8792         case 6:
8793                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8794         case 5:
8795                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8796         case 4:
8797                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8798         case 3:
8799                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8800         case 2:
8801         case 1:
8802
8803         default:
8804                 break;
8805         }
8806
8807         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8808                 /* Write our heartbeat update interval to APE. */
8809                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8810                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8811
8812         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8813
8814         return 0;
8815 }
8816
8817 /* Called at device open time to get the chip ready for
8818  * packet processing.  Invoked with tp->lock held.
8819  */
8820 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8821 {
8822         tg3_switch_clocks(tp);
8823
8824         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8825
8826         return tg3_reset_hw(tp, reset_phy);
8827 }
8828
8829 #define TG3_STAT_ADD32(PSTAT, REG) \
8830 do {    u32 __val = tr32(REG); \
8831         (PSTAT)->low += __val; \
8832         if ((PSTAT)->low < __val) \
8833                 (PSTAT)->high += 1; \
8834 } while (0)
8835
8836 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8837 {
8838         struct tg3_hw_stats *sp = tp->hw_stats;
8839
8840         if (!netif_carrier_ok(tp->dev))
8841                 return;
8842
8843         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8844         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8845         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8846         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8847         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8848         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8849         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8850         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8851         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8852         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8853         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8854         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8855         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8856
8857         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8858         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8859         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8860         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8861         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8862         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8863         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8864         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8865         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8866         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8867         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8868         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8869         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8870         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8871
8872         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8873         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8874         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8875 }
8876
8877 static void tg3_timer(unsigned long __opaque)
8878 {
8879         struct tg3 *tp = (struct tg3 *) __opaque;
8880
8881         if (tp->irq_sync)
8882                 goto restart_timer;
8883
8884         spin_lock(&tp->lock);
8885
8886         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8887                 /* All of this garbage is because when using non-tagged
8888                  * IRQ status the mailbox/status_block protocol the chip
8889                  * uses with the cpu is race prone.
8890                  */
8891                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8892                         tw32(GRC_LOCAL_CTRL,
8893                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8894                 } else {
8895                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8896                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8897                 }
8898
8899                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8900                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8901                         spin_unlock(&tp->lock);
8902                         schedule_work(&tp->reset_task);
8903                         return;
8904                 }
8905         }
8906
8907         /* This part only runs once per second. */
8908         if (!--tp->timer_counter) {
8909                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8910                         tg3_periodic_fetch_stats(tp);
8911
8912                 if (tp->setlpicnt && !--tp->setlpicnt) {
8913                         u32 val = tr32(TG3_CPMU_EEE_MODE);
8914                         tw32(TG3_CPMU_EEE_MODE,
8915                              val | TG3_CPMU_EEEMD_LPI_ENABLE);
8916                 }
8917
8918                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8919                         u32 mac_stat;
8920                         int phy_event;
8921
8922                         mac_stat = tr32(MAC_STATUS);
8923
8924                         phy_event = 0;
8925                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8926                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8927                                         phy_event = 1;
8928                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8929                                 phy_event = 1;
8930
8931                         if (phy_event)
8932                                 tg3_setup_phy(tp, 0);
8933                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8934                         u32 mac_stat = tr32(MAC_STATUS);
8935                         int need_setup = 0;
8936
8937                         if (netif_carrier_ok(tp->dev) &&
8938                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8939                                 need_setup = 1;
8940                         }
8941                         if (!netif_carrier_ok(tp->dev) &&
8942                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8943                                          MAC_STATUS_SIGNAL_DET))) {
8944                                 need_setup = 1;
8945                         }
8946                         if (need_setup) {
8947                                 if (!tp->serdes_counter) {
8948                                         tw32_f(MAC_MODE,
8949                                              (tp->mac_mode &
8950                                               ~MAC_MODE_PORT_MODE_MASK));
8951                                         udelay(40);
8952                                         tw32_f(MAC_MODE, tp->mac_mode);
8953                                         udelay(40);
8954                                 }
8955                                 tg3_setup_phy(tp, 0);
8956                         }
8957                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8958                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8959                         tg3_serdes_parallel_detect(tp);
8960                 }
8961
8962                 tp->timer_counter = tp->timer_multiplier;
8963         }
8964
8965         /* Heartbeat is only sent once every 2 seconds.
8966          *
8967          * The heartbeat is to tell the ASF firmware that the host
8968          * driver is still alive.  In the event that the OS crashes,
8969          * ASF needs to reset the hardware to free up the FIFO space
8970          * that may be filled with rx packets destined for the host.
8971          * If the FIFO is full, ASF will no longer function properly.
8972          *
8973          * Unintended resets have been reported on real time kernels
8974          * where the timer doesn't run on time.  Netpoll will also have
8975          * same problem.
8976          *
8977          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8978          * to check the ring condition when the heartbeat is expiring
8979          * before doing the reset.  This will prevent most unintended
8980          * resets.
8981          */
8982         if (!--tp->asf_counter) {
8983                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8984                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8985                         tg3_wait_for_event_ack(tp);
8986
8987                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8988                                       FWCMD_NICDRV_ALIVE3);
8989                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8990                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8991                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8992
8993                         tg3_generate_fw_event(tp);
8994                 }
8995                 tp->asf_counter = tp->asf_multiplier;
8996         }
8997
8998         spin_unlock(&tp->lock);
8999
9000 restart_timer:
9001         tp->timer.expires = jiffies + tp->timer_offset;
9002         add_timer(&tp->timer);
9003 }
9004
9005 static int tg3_request_irq(struct tg3 *tp, int irq_num)
9006 {
9007         irq_handler_t fn;
9008         unsigned long flags;
9009         char *name;
9010         struct tg3_napi *tnapi = &tp->napi[irq_num];
9011
9012         if (tp->irq_cnt == 1)
9013                 name = tp->dev->name;
9014         else {
9015                 name = &tnapi->irq_lbl[0];
9016                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
9017                 name[IFNAMSIZ-1] = 0;
9018         }
9019
9020         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9021                 fn = tg3_msi;
9022                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
9023                         fn = tg3_msi_1shot;
9024                 flags = 0;
9025         } else {
9026                 fn = tg3_interrupt;
9027                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9028                         fn = tg3_interrupt_tagged;
9029                 flags = IRQF_SHARED;
9030         }
9031
9032         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
9033 }
9034
9035 static int tg3_test_interrupt(struct tg3 *tp)
9036 {
9037         struct tg3_napi *tnapi = &tp->napi[0];
9038         struct net_device *dev = tp->dev;
9039         int err, i, intr_ok = 0;
9040         u32 val;
9041
9042         if (!netif_running(dev))
9043                 return -ENODEV;
9044
9045         tg3_disable_ints(tp);
9046
9047         free_irq(tnapi->irq_vec, tnapi);
9048
9049         /*
9050          * Turn off MSI one shot mode.  Otherwise this test has no
9051          * observable way to know whether the interrupt was delivered.
9052          */
9053         if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
9054             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9055                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9056                 tw32(MSGINT_MODE, val);
9057         }
9058
9059         err = request_irq(tnapi->irq_vec, tg3_test_isr,
9060                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
9061         if (err)
9062                 return err;
9063
9064         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
9065         tg3_enable_ints(tp);
9066
9067         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9068                tnapi->coal_now);
9069
9070         for (i = 0; i < 5; i++) {
9071                 u32 int_mbox, misc_host_ctrl;
9072
9073                 int_mbox = tr32_mailbox(tnapi->int_mbox);
9074                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9075
9076                 if ((int_mbox != 0) ||
9077                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9078                         intr_ok = 1;
9079                         break;
9080                 }
9081
9082                 msleep(10);
9083         }
9084
9085         tg3_disable_ints(tp);
9086
9087         free_irq(tnapi->irq_vec, tnapi);
9088
9089         err = tg3_request_irq(tp, 0);
9090
9091         if (err)
9092                 return err;
9093
9094         if (intr_ok) {
9095                 /* Reenable MSI one shot mode. */
9096                 if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
9097                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9098                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9099                         tw32(MSGINT_MODE, val);
9100                 }
9101                 return 0;
9102         }
9103
9104         return -EIO;
9105 }
9106
9107 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9108  * successfully restored
9109  */
9110 static int tg3_test_msi(struct tg3 *tp)
9111 {
9112         int err;
9113         u16 pci_cmd;
9114
9115         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
9116                 return 0;
9117
9118         /* Turn off SERR reporting in case MSI terminates with Master
9119          * Abort.
9120          */
9121         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9122         pci_write_config_word(tp->pdev, PCI_COMMAND,
9123                               pci_cmd & ~PCI_COMMAND_SERR);
9124
9125         err = tg3_test_interrupt(tp);
9126
9127         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9128
9129         if (!err)
9130                 return 0;
9131
9132         /* other failures */
9133         if (err != -EIO)
9134                 return err;
9135
9136         /* MSI test failed, go back to INTx mode */
9137         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9138                     "to INTx mode. Please report this failure to the PCI "
9139                     "maintainer and include system chipset information\n");
9140
9141         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9142
9143         pci_disable_msi(tp->pdev);
9144
9145         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
9146         tp->napi[0].irq_vec = tp->pdev->irq;
9147
9148         err = tg3_request_irq(tp, 0);
9149         if (err)
9150                 return err;
9151
9152         /* Need to reset the chip because the MSI cycle may have terminated
9153          * with Master Abort.
9154          */
9155         tg3_full_lock(tp, 1);
9156
9157         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9158         err = tg3_init_hw(tp, 1);
9159
9160         tg3_full_unlock(tp);
9161
9162         if (err)
9163                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9164
9165         return err;
9166 }
9167
9168 static int tg3_request_firmware(struct tg3 *tp)
9169 {
9170         const __be32 *fw_data;
9171
9172         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9173                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9174                            tp->fw_needed);
9175                 return -ENOENT;
9176         }
9177
9178         fw_data = (void *)tp->fw->data;
9179
9180         /* Firmware blob starts with version numbers, followed by
9181          * start address and _full_ length including BSS sections
9182          * (which must be longer than the actual data, of course
9183          */
9184
9185         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
9186         if (tp->fw_len < (tp->fw->size - 12)) {
9187                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9188                            tp->fw_len, tp->fw_needed);
9189                 release_firmware(tp->fw);
9190                 tp->fw = NULL;
9191                 return -EINVAL;
9192         }
9193
9194         /* We no longer need firmware; we have it. */
9195         tp->fw_needed = NULL;
9196         return 0;
9197 }
9198
9199 static bool tg3_enable_msix(struct tg3 *tp)
9200 {
9201         int i, rc, cpus = num_online_cpus();
9202         struct msix_entry msix_ent[tp->irq_max];
9203
9204         if (cpus == 1)
9205                 /* Just fallback to the simpler MSI mode. */
9206                 return false;
9207
9208         /*
9209          * We want as many rx rings enabled as there are cpus.
9210          * The first MSIX vector only deals with link interrupts, etc,
9211          * so we add one to the number of vectors we are requesting.
9212          */
9213         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9214
9215         for (i = 0; i < tp->irq_max; i++) {
9216                 msix_ent[i].entry  = i;
9217                 msix_ent[i].vector = 0;
9218         }
9219
9220         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9221         if (rc < 0) {
9222                 return false;
9223         } else if (rc != 0) {
9224                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9225                         return false;
9226                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9227                               tp->irq_cnt, rc);
9228                 tp->irq_cnt = rc;
9229         }
9230
9231         for (i = 0; i < tp->irq_max; i++)
9232                 tp->napi[i].irq_vec = msix_ent[i].vector;
9233
9234         netif_set_real_num_tx_queues(tp->dev, 1);
9235         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9236         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9237                 pci_disable_msix(tp->pdev);
9238                 return false;
9239         }
9240
9241         if (tp->irq_cnt > 1) {
9242                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9243
9244                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9245                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9246                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
9247                         netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9248                 }
9249         }
9250
9251         return true;
9252 }
9253
9254 static void tg3_ints_init(struct tg3 *tp)
9255 {
9256         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9257             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9258                 /* All MSI supporting chips should support tagged
9259                  * status.  Assert that this is the case.
9260                  */
9261                 netdev_warn(tp->dev,
9262                             "MSI without TAGGED_STATUS? Not using MSI\n");
9263                 goto defcfg;
9264         }
9265
9266         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9267                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9268         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9269                  pci_enable_msi(tp->pdev) == 0)
9270                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9271
9272         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9273                 u32 msi_mode = tr32(MSGINT_MODE);
9274                 if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
9275                     tp->irq_cnt > 1)
9276                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9277                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9278         }
9279 defcfg:
9280         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9281                 tp->irq_cnt = 1;
9282                 tp->napi[0].irq_vec = tp->pdev->irq;
9283                 netif_set_real_num_tx_queues(tp->dev, 1);
9284                 netif_set_real_num_rx_queues(tp->dev, 1);
9285         }
9286 }
9287
9288 static void tg3_ints_fini(struct tg3 *tp)
9289 {
9290         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9291                 pci_disable_msix(tp->pdev);
9292         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9293                 pci_disable_msi(tp->pdev);
9294         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9295         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9296 }
9297
9298 static int tg3_open(struct net_device *dev)
9299 {
9300         struct tg3 *tp = netdev_priv(dev);
9301         int i, err;
9302
9303         if (tp->fw_needed) {
9304                 err = tg3_request_firmware(tp);
9305                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9306                         if (err)
9307                                 return err;
9308                 } else if (err) {
9309                         netdev_warn(tp->dev, "TSO capability disabled\n");
9310                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9311                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9312                         netdev_notice(tp->dev, "TSO capability restored\n");
9313                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9314                 }
9315         }
9316
9317         netif_carrier_off(tp->dev);
9318
9319         err = tg3_power_up(tp);
9320         if (err)
9321                 return err;
9322
9323         tg3_full_lock(tp, 0);
9324
9325         tg3_disable_ints(tp);
9326         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9327
9328         tg3_full_unlock(tp);
9329
9330         /*
9331          * Setup interrupts first so we know how
9332          * many NAPI resources to allocate
9333          */
9334         tg3_ints_init(tp);
9335
9336         /* The placement of this call is tied
9337          * to the setup and use of Host TX descriptors.
9338          */
9339         err = tg3_alloc_consistent(tp);
9340         if (err)
9341                 goto err_out1;
9342
9343         tg3_napi_init(tp);
9344
9345         tg3_napi_enable(tp);
9346
9347         for (i = 0; i < tp->irq_cnt; i++) {
9348                 struct tg3_napi *tnapi = &tp->napi[i];
9349                 err = tg3_request_irq(tp, i);
9350                 if (err) {
9351                         for (i--; i >= 0; i--)
9352                                 free_irq(tnapi->irq_vec, tnapi);
9353                         break;
9354                 }
9355         }
9356
9357         if (err)
9358                 goto err_out2;
9359
9360         tg3_full_lock(tp, 0);
9361
9362         err = tg3_init_hw(tp, 1);
9363         if (err) {
9364                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9365                 tg3_free_rings(tp);
9366         } else {
9367                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9368                         tp->timer_offset = HZ;
9369                 else
9370                         tp->timer_offset = HZ / 10;
9371
9372                 BUG_ON(tp->timer_offset > HZ);
9373                 tp->timer_counter = tp->timer_multiplier =
9374                         (HZ / tp->timer_offset);
9375                 tp->asf_counter = tp->asf_multiplier =
9376                         ((HZ / tp->timer_offset) * 2);
9377
9378                 init_timer(&tp->timer);
9379                 tp->timer.expires = jiffies + tp->timer_offset;
9380                 tp->timer.data = (unsigned long) tp;
9381                 tp->timer.function = tg3_timer;
9382         }
9383
9384         tg3_full_unlock(tp);
9385
9386         if (err)
9387                 goto err_out3;
9388
9389         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9390                 err = tg3_test_msi(tp);
9391
9392                 if (err) {
9393                         tg3_full_lock(tp, 0);
9394                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9395                         tg3_free_rings(tp);
9396                         tg3_full_unlock(tp);
9397
9398                         goto err_out2;
9399                 }
9400
9401                 if (!(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
9402                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9403                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9404
9405                         tw32(PCIE_TRANSACTION_CFG,
9406                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9407                 }
9408         }
9409
9410         tg3_phy_start(tp);
9411
9412         tg3_full_lock(tp, 0);
9413
9414         add_timer(&tp->timer);
9415         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9416         tg3_enable_ints(tp);
9417
9418         tg3_full_unlock(tp);
9419
9420         netif_tx_start_all_queues(dev);
9421
9422         return 0;
9423
9424 err_out3:
9425         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9426                 struct tg3_napi *tnapi = &tp->napi[i];
9427                 free_irq(tnapi->irq_vec, tnapi);
9428         }
9429
9430 err_out2:
9431         tg3_napi_disable(tp);
9432         tg3_napi_fini(tp);
9433         tg3_free_consistent(tp);
9434
9435 err_out1:
9436         tg3_ints_fini(tp);
9437         return err;
9438 }
9439
9440 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9441                                                  struct rtnl_link_stats64 *);
9442 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9443
9444 static int tg3_close(struct net_device *dev)
9445 {
9446         int i;
9447         struct tg3 *tp = netdev_priv(dev);
9448
9449         tg3_napi_disable(tp);
9450         cancel_work_sync(&tp->reset_task);
9451
9452         netif_tx_stop_all_queues(dev);
9453
9454         del_timer_sync(&tp->timer);
9455
9456         tg3_phy_stop(tp);
9457
9458         tg3_full_lock(tp, 1);
9459
9460         tg3_disable_ints(tp);
9461
9462         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9463         tg3_free_rings(tp);
9464         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9465
9466         tg3_full_unlock(tp);
9467
9468         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9469                 struct tg3_napi *tnapi = &tp->napi[i];
9470                 free_irq(tnapi->irq_vec, tnapi);
9471         }
9472
9473         tg3_ints_fini(tp);
9474
9475         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9476
9477         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9478                sizeof(tp->estats_prev));
9479
9480         tg3_napi_fini(tp);
9481
9482         tg3_free_consistent(tp);
9483
9484         tg3_power_down(tp);
9485
9486         netif_carrier_off(tp->dev);
9487
9488         return 0;
9489 }
9490
9491 static inline u64 get_stat64(tg3_stat64_t *val)
9492 {
9493        return ((u64)val->high << 32) | ((u64)val->low);
9494 }
9495
9496 static u64 calc_crc_errors(struct tg3 *tp)
9497 {
9498         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9499
9500         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9501             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9502              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9503                 u32 val;
9504
9505                 spin_lock_bh(&tp->lock);
9506                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9507                         tg3_writephy(tp, MII_TG3_TEST1,
9508                                      val | MII_TG3_TEST1_CRC_EN);
9509                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9510                 } else
9511                         val = 0;
9512                 spin_unlock_bh(&tp->lock);
9513
9514                 tp->phy_crc_errors += val;
9515
9516                 return tp->phy_crc_errors;
9517         }
9518
9519         return get_stat64(&hw_stats->rx_fcs_errors);
9520 }
9521
9522 #define ESTAT_ADD(member) \
9523         estats->member =        old_estats->member + \
9524                                 get_stat64(&hw_stats->member)
9525
9526 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9527 {
9528         struct tg3_ethtool_stats *estats = &tp->estats;
9529         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9530         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9531
9532         if (!hw_stats)
9533                 return old_estats;
9534
9535         ESTAT_ADD(rx_octets);
9536         ESTAT_ADD(rx_fragments);
9537         ESTAT_ADD(rx_ucast_packets);
9538         ESTAT_ADD(rx_mcast_packets);
9539         ESTAT_ADD(rx_bcast_packets);
9540         ESTAT_ADD(rx_fcs_errors);
9541         ESTAT_ADD(rx_align_errors);
9542         ESTAT_ADD(rx_xon_pause_rcvd);
9543         ESTAT_ADD(rx_xoff_pause_rcvd);
9544         ESTAT_ADD(rx_mac_ctrl_rcvd);
9545         ESTAT_ADD(rx_xoff_entered);
9546         ESTAT_ADD(rx_frame_too_long_errors);
9547         ESTAT_ADD(rx_jabbers);
9548         ESTAT_ADD(rx_undersize_packets);
9549         ESTAT_ADD(rx_in_length_errors);
9550         ESTAT_ADD(rx_out_length_errors);
9551         ESTAT_ADD(rx_64_or_less_octet_packets);
9552         ESTAT_ADD(rx_65_to_127_octet_packets);
9553         ESTAT_ADD(rx_128_to_255_octet_packets);
9554         ESTAT_ADD(rx_256_to_511_octet_packets);
9555         ESTAT_ADD(rx_512_to_1023_octet_packets);
9556         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9557         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9558         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9559         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9560         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9561
9562         ESTAT_ADD(tx_octets);
9563         ESTAT_ADD(tx_collisions);
9564         ESTAT_ADD(tx_xon_sent);
9565         ESTAT_ADD(tx_xoff_sent);
9566         ESTAT_ADD(tx_flow_control);
9567         ESTAT_ADD(tx_mac_errors);
9568         ESTAT_ADD(tx_single_collisions);
9569         ESTAT_ADD(tx_mult_collisions);
9570         ESTAT_ADD(tx_deferred);
9571         ESTAT_ADD(tx_excessive_collisions);
9572         ESTAT_ADD(tx_late_collisions);
9573         ESTAT_ADD(tx_collide_2times);
9574         ESTAT_ADD(tx_collide_3times);
9575         ESTAT_ADD(tx_collide_4times);
9576         ESTAT_ADD(tx_collide_5times);
9577         ESTAT_ADD(tx_collide_6times);
9578         ESTAT_ADD(tx_collide_7times);
9579         ESTAT_ADD(tx_collide_8times);
9580         ESTAT_ADD(tx_collide_9times);
9581         ESTAT_ADD(tx_collide_10times);
9582         ESTAT_ADD(tx_collide_11times);
9583         ESTAT_ADD(tx_collide_12times);
9584         ESTAT_ADD(tx_collide_13times);
9585         ESTAT_ADD(tx_collide_14times);
9586         ESTAT_ADD(tx_collide_15times);
9587         ESTAT_ADD(tx_ucast_packets);
9588         ESTAT_ADD(tx_mcast_packets);
9589         ESTAT_ADD(tx_bcast_packets);
9590         ESTAT_ADD(tx_carrier_sense_errors);
9591         ESTAT_ADD(tx_discards);
9592         ESTAT_ADD(tx_errors);
9593
9594         ESTAT_ADD(dma_writeq_full);
9595         ESTAT_ADD(dma_write_prioq_full);
9596         ESTAT_ADD(rxbds_empty);
9597         ESTAT_ADD(rx_discards);
9598         ESTAT_ADD(rx_errors);
9599         ESTAT_ADD(rx_threshold_hit);
9600
9601         ESTAT_ADD(dma_readq_full);
9602         ESTAT_ADD(dma_read_prioq_full);
9603         ESTAT_ADD(tx_comp_queue_full);
9604
9605         ESTAT_ADD(ring_set_send_prod_index);
9606         ESTAT_ADD(ring_status_update);
9607         ESTAT_ADD(nic_irqs);
9608         ESTAT_ADD(nic_avoided_irqs);
9609         ESTAT_ADD(nic_tx_threshold_hit);
9610
9611         return estats;
9612 }
9613
9614 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9615                                                  struct rtnl_link_stats64 *stats)
9616 {
9617         struct tg3 *tp = netdev_priv(dev);
9618         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9619         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9620
9621         if (!hw_stats)
9622                 return old_stats;
9623
9624         stats->rx_packets = old_stats->rx_packets +
9625                 get_stat64(&hw_stats->rx_ucast_packets) +
9626                 get_stat64(&hw_stats->rx_mcast_packets) +
9627                 get_stat64(&hw_stats->rx_bcast_packets);
9628
9629         stats->tx_packets = old_stats->tx_packets +
9630                 get_stat64(&hw_stats->tx_ucast_packets) +
9631                 get_stat64(&hw_stats->tx_mcast_packets) +
9632                 get_stat64(&hw_stats->tx_bcast_packets);
9633
9634         stats->rx_bytes = old_stats->rx_bytes +
9635                 get_stat64(&hw_stats->rx_octets);
9636         stats->tx_bytes = old_stats->tx_bytes +
9637                 get_stat64(&hw_stats->tx_octets);
9638
9639         stats->rx_errors = old_stats->rx_errors +
9640                 get_stat64(&hw_stats->rx_errors);
9641         stats->tx_errors = old_stats->tx_errors +
9642                 get_stat64(&hw_stats->tx_errors) +
9643                 get_stat64(&hw_stats->tx_mac_errors) +
9644                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9645                 get_stat64(&hw_stats->tx_discards);
9646
9647         stats->multicast = old_stats->multicast +
9648                 get_stat64(&hw_stats->rx_mcast_packets);
9649         stats->collisions = old_stats->collisions +
9650                 get_stat64(&hw_stats->tx_collisions);
9651
9652         stats->rx_length_errors = old_stats->rx_length_errors +
9653                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9654                 get_stat64(&hw_stats->rx_undersize_packets);
9655
9656         stats->rx_over_errors = old_stats->rx_over_errors +
9657                 get_stat64(&hw_stats->rxbds_empty);
9658         stats->rx_frame_errors = old_stats->rx_frame_errors +
9659                 get_stat64(&hw_stats->rx_align_errors);
9660         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9661                 get_stat64(&hw_stats->tx_discards);
9662         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9663                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9664
9665         stats->rx_crc_errors = old_stats->rx_crc_errors +
9666                 calc_crc_errors(tp);
9667
9668         stats->rx_missed_errors = old_stats->rx_missed_errors +
9669                 get_stat64(&hw_stats->rx_discards);
9670
9671         stats->rx_dropped = tp->rx_dropped;
9672
9673         return stats;
9674 }
9675
9676 static inline u32 calc_crc(unsigned char *buf, int len)
9677 {
9678         u32 reg;
9679         u32 tmp;
9680         int j, k;
9681
9682         reg = 0xffffffff;
9683
9684         for (j = 0; j < len; j++) {
9685                 reg ^= buf[j];
9686
9687                 for (k = 0; k < 8; k++) {
9688                         tmp = reg & 0x01;
9689
9690                         reg >>= 1;
9691
9692                         if (tmp)
9693                                 reg ^= 0xedb88320;
9694                 }
9695         }
9696
9697         return ~reg;
9698 }
9699
9700 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9701 {
9702         /* accept or reject all multicast frames */
9703         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9704         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9705         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9706         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9707 }
9708
9709 static void __tg3_set_rx_mode(struct net_device *dev)
9710 {
9711         struct tg3 *tp = netdev_priv(dev);
9712         u32 rx_mode;
9713
9714         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9715                                   RX_MODE_KEEP_VLAN_TAG);
9716
9717 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9718         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9719          * flag clear.
9720          */
9721         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9722                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9723 #endif
9724
9725         if (dev->flags & IFF_PROMISC) {
9726                 /* Promiscuous mode. */
9727                 rx_mode |= RX_MODE_PROMISC;
9728         } else if (dev->flags & IFF_ALLMULTI) {
9729                 /* Accept all multicast. */
9730                 tg3_set_multi(tp, 1);
9731         } else if (netdev_mc_empty(dev)) {
9732                 /* Reject all multicast. */
9733                 tg3_set_multi(tp, 0);
9734         } else {
9735                 /* Accept one or more multicast(s). */
9736                 struct netdev_hw_addr *ha;
9737                 u32 mc_filter[4] = { 0, };
9738                 u32 regidx;
9739                 u32 bit;
9740                 u32 crc;
9741
9742                 netdev_for_each_mc_addr(ha, dev) {
9743                         crc = calc_crc(ha->addr, ETH_ALEN);
9744                         bit = ~crc & 0x7f;
9745                         regidx = (bit & 0x60) >> 5;
9746                         bit &= 0x1f;
9747                         mc_filter[regidx] |= (1 << bit);
9748                 }
9749
9750                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9751                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9752                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9753                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9754         }
9755
9756         if (rx_mode != tp->rx_mode) {
9757                 tp->rx_mode = rx_mode;
9758                 tw32_f(MAC_RX_MODE, rx_mode);
9759                 udelay(10);
9760         }
9761 }
9762
9763 static void tg3_set_rx_mode(struct net_device *dev)
9764 {
9765         struct tg3 *tp = netdev_priv(dev);
9766
9767         if (!netif_running(dev))
9768                 return;
9769
9770         tg3_full_lock(tp, 0);
9771         __tg3_set_rx_mode(dev);
9772         tg3_full_unlock(tp);
9773 }
9774
9775 static int tg3_get_regs_len(struct net_device *dev)
9776 {
9777         return TG3_REG_BLK_SIZE;
9778 }
9779
9780 static void tg3_get_regs(struct net_device *dev,
9781                 struct ethtool_regs *regs, void *_p)
9782 {
9783         struct tg3 *tp = netdev_priv(dev);
9784
9785         regs->version = 0;
9786
9787         memset(_p, 0, TG3_REG_BLK_SIZE);
9788
9789         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9790                 return;
9791
9792         tg3_full_lock(tp, 0);
9793
9794         tg3_dump_legacy_regs(tp, (u32 *)_p);
9795
9796         tg3_full_unlock(tp);
9797 }
9798
9799 static int tg3_get_eeprom_len(struct net_device *dev)
9800 {
9801         struct tg3 *tp = netdev_priv(dev);
9802
9803         return tp->nvram_size;
9804 }
9805
9806 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9807 {
9808         struct tg3 *tp = netdev_priv(dev);
9809         int ret;
9810         u8  *pd;
9811         u32 i, offset, len, b_offset, b_count;
9812         __be32 val;
9813
9814         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9815                 return -EINVAL;
9816
9817         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9818                 return -EAGAIN;
9819
9820         offset = eeprom->offset;
9821         len = eeprom->len;
9822         eeprom->len = 0;
9823
9824         eeprom->magic = TG3_EEPROM_MAGIC;
9825
9826         if (offset & 3) {
9827                 /* adjustments to start on required 4 byte boundary */
9828                 b_offset = offset & 3;
9829                 b_count = 4 - b_offset;
9830                 if (b_count > len) {
9831                         /* i.e. offset=1 len=2 */
9832                         b_count = len;
9833                 }
9834                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9835                 if (ret)
9836                         return ret;
9837                 memcpy(data, ((char *)&val) + b_offset, b_count);
9838                 len -= b_count;
9839                 offset += b_count;
9840                 eeprom->len += b_count;
9841         }
9842
9843         /* read bytes up to the last 4 byte boundary */
9844         pd = &data[eeprom->len];
9845         for (i = 0; i < (len - (len & 3)); i += 4) {
9846                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9847                 if (ret) {
9848                         eeprom->len += i;
9849                         return ret;
9850                 }
9851                 memcpy(pd + i, &val, 4);
9852         }
9853         eeprom->len += i;
9854
9855         if (len & 3) {
9856                 /* read last bytes not ending on 4 byte boundary */
9857                 pd = &data[eeprom->len];
9858                 b_count = len & 3;
9859                 b_offset = offset + len - b_count;
9860                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9861                 if (ret)
9862                         return ret;
9863                 memcpy(pd, &val, b_count);
9864                 eeprom->len += b_count;
9865         }
9866         return 0;
9867 }
9868
9869 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9870
9871 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9872 {
9873         struct tg3 *tp = netdev_priv(dev);
9874         int ret;
9875         u32 offset, len, b_offset, odd_len;
9876         u8 *buf;
9877         __be32 start, end;
9878
9879         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9880                 return -EAGAIN;
9881
9882         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9883             eeprom->magic != TG3_EEPROM_MAGIC)
9884                 return -EINVAL;
9885
9886         offset = eeprom->offset;
9887         len = eeprom->len;
9888
9889         if ((b_offset = (offset & 3))) {
9890                 /* adjustments to start on required 4 byte boundary */
9891                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9892                 if (ret)
9893                         return ret;
9894                 len += b_offset;
9895                 offset &= ~3;
9896                 if (len < 4)
9897                         len = 4;
9898         }
9899
9900         odd_len = 0;
9901         if (len & 3) {
9902                 /* adjustments to end on required 4 byte boundary */
9903                 odd_len = 1;
9904                 len = (len + 3) & ~3;
9905                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9906                 if (ret)
9907                         return ret;
9908         }
9909
9910         buf = data;
9911         if (b_offset || odd_len) {
9912                 buf = kmalloc(len, GFP_KERNEL);
9913                 if (!buf)
9914                         return -ENOMEM;
9915                 if (b_offset)
9916                         memcpy(buf, &start, 4);
9917                 if (odd_len)
9918                         memcpy(buf+len-4, &end, 4);
9919                 memcpy(buf + b_offset, data, eeprom->len);
9920         }
9921
9922         ret = tg3_nvram_write_block(tp, offset, len, buf);
9923
9924         if (buf != data)
9925                 kfree(buf);
9926
9927         return ret;
9928 }
9929
9930 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9931 {
9932         struct tg3 *tp = netdev_priv(dev);
9933
9934         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9935                 struct phy_device *phydev;
9936                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9937                         return -EAGAIN;
9938                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9939                 return phy_ethtool_gset(phydev, cmd);
9940         }
9941
9942         cmd->supported = (SUPPORTED_Autoneg);
9943
9944         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9945                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9946                                    SUPPORTED_1000baseT_Full);
9947
9948         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9949                 cmd->supported |= (SUPPORTED_100baseT_Half |
9950                                   SUPPORTED_100baseT_Full |
9951                                   SUPPORTED_10baseT_Half |
9952                                   SUPPORTED_10baseT_Full |
9953                                   SUPPORTED_TP);
9954                 cmd->port = PORT_TP;
9955         } else {
9956                 cmd->supported |= SUPPORTED_FIBRE;
9957                 cmd->port = PORT_FIBRE;
9958         }
9959
9960         cmd->advertising = tp->link_config.advertising;
9961         if (netif_running(dev)) {
9962                 cmd->speed = tp->link_config.active_speed;
9963                 cmd->duplex = tp->link_config.active_duplex;
9964         } else {
9965                 cmd->speed = SPEED_INVALID;
9966                 cmd->duplex = DUPLEX_INVALID;
9967         }
9968         cmd->phy_address = tp->phy_addr;
9969         cmd->transceiver = XCVR_INTERNAL;
9970         cmd->autoneg = tp->link_config.autoneg;
9971         cmd->maxtxpkt = 0;
9972         cmd->maxrxpkt = 0;
9973         return 0;
9974 }
9975
9976 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9977 {
9978         struct tg3 *tp = netdev_priv(dev);
9979
9980         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9981                 struct phy_device *phydev;
9982                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9983                         return -EAGAIN;
9984                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9985                 return phy_ethtool_sset(phydev, cmd);
9986         }
9987
9988         if (cmd->autoneg != AUTONEG_ENABLE &&
9989             cmd->autoneg != AUTONEG_DISABLE)
9990                 return -EINVAL;
9991
9992         if (cmd->autoneg == AUTONEG_DISABLE &&
9993             cmd->duplex != DUPLEX_FULL &&
9994             cmd->duplex != DUPLEX_HALF)
9995                 return -EINVAL;
9996
9997         if (cmd->autoneg == AUTONEG_ENABLE) {
9998                 u32 mask = ADVERTISED_Autoneg |
9999                            ADVERTISED_Pause |
10000                            ADVERTISED_Asym_Pause;
10001
10002                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10003                         mask |= ADVERTISED_1000baseT_Half |
10004                                 ADVERTISED_1000baseT_Full;
10005
10006                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
10007                         mask |= ADVERTISED_100baseT_Half |
10008                                 ADVERTISED_100baseT_Full |
10009                                 ADVERTISED_10baseT_Half |
10010                                 ADVERTISED_10baseT_Full |
10011                                 ADVERTISED_TP;
10012                 else
10013                         mask |= ADVERTISED_FIBRE;
10014
10015                 if (cmd->advertising & ~mask)
10016                         return -EINVAL;
10017
10018                 mask &= (ADVERTISED_1000baseT_Half |
10019                          ADVERTISED_1000baseT_Full |
10020                          ADVERTISED_100baseT_Half |
10021                          ADVERTISED_100baseT_Full |
10022                          ADVERTISED_10baseT_Half |
10023                          ADVERTISED_10baseT_Full);
10024
10025                 cmd->advertising &= mask;
10026         } else {
10027                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
10028                         if (cmd->speed != SPEED_1000)
10029                                 return -EINVAL;
10030
10031                         if (cmd->duplex != DUPLEX_FULL)
10032                                 return -EINVAL;
10033                 } else {
10034                         if (cmd->speed != SPEED_100 &&
10035                             cmd->speed != SPEED_10)
10036                                 return -EINVAL;
10037                 }
10038         }
10039
10040         tg3_full_lock(tp, 0);
10041
10042         tp->link_config.autoneg = cmd->autoneg;
10043         if (cmd->autoneg == AUTONEG_ENABLE) {
10044                 tp->link_config.advertising = (cmd->advertising |
10045                                               ADVERTISED_Autoneg);
10046                 tp->link_config.speed = SPEED_INVALID;
10047                 tp->link_config.duplex = DUPLEX_INVALID;
10048         } else {
10049                 tp->link_config.advertising = 0;
10050                 tp->link_config.speed = cmd->speed;
10051                 tp->link_config.duplex = cmd->duplex;
10052         }
10053
10054         tp->link_config.orig_speed = tp->link_config.speed;
10055         tp->link_config.orig_duplex = tp->link_config.duplex;
10056         tp->link_config.orig_autoneg = tp->link_config.autoneg;
10057
10058         if (netif_running(dev))
10059                 tg3_setup_phy(tp, 1);
10060
10061         tg3_full_unlock(tp);
10062
10063         return 0;
10064 }
10065
10066 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10067 {
10068         struct tg3 *tp = netdev_priv(dev);
10069
10070         strcpy(info->driver, DRV_MODULE_NAME);
10071         strcpy(info->version, DRV_MODULE_VERSION);
10072         strcpy(info->fw_version, tp->fw_ver);
10073         strcpy(info->bus_info, pci_name(tp->pdev));
10074 }
10075
10076 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10077 {
10078         struct tg3 *tp = netdev_priv(dev);
10079
10080         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
10081             device_can_wakeup(&tp->pdev->dev))
10082                 wol->supported = WAKE_MAGIC;
10083         else
10084                 wol->supported = 0;
10085         wol->wolopts = 0;
10086         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
10087             device_can_wakeup(&tp->pdev->dev))
10088                 wol->wolopts = WAKE_MAGIC;
10089         memset(&wol->sopass, 0, sizeof(wol->sopass));
10090 }
10091
10092 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10093 {
10094         struct tg3 *tp = netdev_priv(dev);
10095         struct device *dp = &tp->pdev->dev;
10096
10097         if (wol->wolopts & ~WAKE_MAGIC)
10098                 return -EINVAL;
10099         if ((wol->wolopts & WAKE_MAGIC) &&
10100             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
10101                 return -EINVAL;
10102
10103         device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10104
10105         spin_lock_bh(&tp->lock);
10106         if (device_may_wakeup(dp))
10107                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10108         else
10109                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10110         spin_unlock_bh(&tp->lock);
10111
10112
10113         return 0;
10114 }
10115
10116 static u32 tg3_get_msglevel(struct net_device *dev)
10117 {
10118         struct tg3 *tp = netdev_priv(dev);
10119         return tp->msg_enable;
10120 }
10121
10122 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10123 {
10124         struct tg3 *tp = netdev_priv(dev);
10125         tp->msg_enable = value;
10126 }
10127
10128 static int tg3_nway_reset(struct net_device *dev)
10129 {
10130         struct tg3 *tp = netdev_priv(dev);
10131         int r;
10132
10133         if (!netif_running(dev))
10134                 return -EAGAIN;
10135
10136         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10137                 return -EINVAL;
10138
10139         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10140                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10141                         return -EAGAIN;
10142                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10143         } else {
10144                 u32 bmcr;
10145
10146                 spin_lock_bh(&tp->lock);
10147                 r = -EINVAL;
10148                 tg3_readphy(tp, MII_BMCR, &bmcr);
10149                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10150                     ((bmcr & BMCR_ANENABLE) ||
10151                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10152                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10153                                                    BMCR_ANENABLE);
10154                         r = 0;
10155                 }
10156                 spin_unlock_bh(&tp->lock);
10157         }
10158
10159         return r;
10160 }
10161
10162 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10163 {
10164         struct tg3 *tp = netdev_priv(dev);
10165
10166         ering->rx_max_pending = tp->rx_std_ring_mask;
10167         ering->rx_mini_max_pending = 0;
10168         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10169                 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10170         else
10171                 ering->rx_jumbo_max_pending = 0;
10172
10173         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10174
10175         ering->rx_pending = tp->rx_pending;
10176         ering->rx_mini_pending = 0;
10177         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10178                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10179         else
10180                 ering->rx_jumbo_pending = 0;
10181
10182         ering->tx_pending = tp->napi[0].tx_pending;
10183 }
10184
10185 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10186 {
10187         struct tg3 *tp = netdev_priv(dev);
10188         int i, irq_sync = 0, err = 0;
10189
10190         if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10191             (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10192             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10193             (ering->tx_pending <= MAX_SKB_FRAGS) ||
10194             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10195              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10196                 return -EINVAL;
10197
10198         if (netif_running(dev)) {
10199                 tg3_phy_stop(tp);
10200                 tg3_netif_stop(tp);
10201                 irq_sync = 1;
10202         }
10203
10204         tg3_full_lock(tp, irq_sync);
10205
10206         tp->rx_pending = ering->rx_pending;
10207
10208         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10209             tp->rx_pending > 63)
10210                 tp->rx_pending = 63;
10211         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10212
10213         for (i = 0; i < tp->irq_max; i++)
10214                 tp->napi[i].tx_pending = ering->tx_pending;
10215
10216         if (netif_running(dev)) {
10217                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10218                 err = tg3_restart_hw(tp, 1);
10219                 if (!err)
10220                         tg3_netif_start(tp);
10221         }
10222
10223         tg3_full_unlock(tp);
10224
10225         if (irq_sync && !err)
10226                 tg3_phy_start(tp);
10227
10228         return err;
10229 }
10230
10231 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10232 {
10233         struct tg3 *tp = netdev_priv(dev);
10234
10235         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10236
10237         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10238                 epause->rx_pause = 1;
10239         else
10240                 epause->rx_pause = 0;
10241
10242         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10243                 epause->tx_pause = 1;
10244         else
10245                 epause->tx_pause = 0;
10246 }
10247
10248 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10249 {
10250         struct tg3 *tp = netdev_priv(dev);
10251         int err = 0;
10252
10253         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10254                 u32 newadv;
10255                 struct phy_device *phydev;
10256
10257                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10258
10259                 if (!(phydev->supported & SUPPORTED_Pause) ||
10260                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10261                      (epause->rx_pause != epause->tx_pause)))
10262                         return -EINVAL;
10263
10264                 tp->link_config.flowctrl = 0;
10265                 if (epause->rx_pause) {
10266                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10267
10268                         if (epause->tx_pause) {
10269                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10270                                 newadv = ADVERTISED_Pause;
10271                         } else
10272                                 newadv = ADVERTISED_Pause |
10273                                          ADVERTISED_Asym_Pause;
10274                 } else if (epause->tx_pause) {
10275                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10276                         newadv = ADVERTISED_Asym_Pause;
10277                 } else
10278                         newadv = 0;
10279
10280                 if (epause->autoneg)
10281                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10282                 else
10283                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10284
10285                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10286                         u32 oldadv = phydev->advertising &
10287                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10288                         if (oldadv != newadv) {
10289                                 phydev->advertising &=
10290                                         ~(ADVERTISED_Pause |
10291                                           ADVERTISED_Asym_Pause);
10292                                 phydev->advertising |= newadv;
10293                                 if (phydev->autoneg) {
10294                                         /*
10295                                          * Always renegotiate the link to
10296                                          * inform our link partner of our
10297                                          * flow control settings, even if the
10298                                          * flow control is forced.  Let
10299                                          * tg3_adjust_link() do the final
10300                                          * flow control setup.
10301                                          */
10302                                         return phy_start_aneg(phydev);
10303                                 }
10304                         }
10305
10306                         if (!epause->autoneg)
10307                                 tg3_setup_flow_control(tp, 0, 0);
10308                 } else {
10309                         tp->link_config.orig_advertising &=
10310                                         ~(ADVERTISED_Pause |
10311                                           ADVERTISED_Asym_Pause);
10312                         tp->link_config.orig_advertising |= newadv;
10313                 }
10314         } else {
10315                 int irq_sync = 0;
10316
10317                 if (netif_running(dev)) {
10318                         tg3_netif_stop(tp);
10319                         irq_sync = 1;
10320                 }
10321
10322                 tg3_full_lock(tp, irq_sync);
10323
10324                 if (epause->autoneg)
10325                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10326                 else
10327                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10328                 if (epause->rx_pause)
10329                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10330                 else
10331                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10332                 if (epause->tx_pause)
10333                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10334                 else
10335                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10336
10337                 if (netif_running(dev)) {
10338                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10339                         err = tg3_restart_hw(tp, 1);
10340                         if (!err)
10341                                 tg3_netif_start(tp);
10342                 }
10343
10344                 tg3_full_unlock(tp);
10345         }
10346
10347         return err;
10348 }
10349
10350 static int tg3_get_sset_count(struct net_device *dev, int sset)
10351 {
10352         switch (sset) {
10353         case ETH_SS_TEST:
10354                 return TG3_NUM_TEST;
10355         case ETH_SS_STATS:
10356                 return TG3_NUM_STATS;
10357         default:
10358                 return -EOPNOTSUPP;
10359         }
10360 }
10361
10362 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10363 {
10364         switch (stringset) {
10365         case ETH_SS_STATS:
10366                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10367                 break;
10368         case ETH_SS_TEST:
10369                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10370                 break;
10371         default:
10372                 WARN_ON(1);     /* we need a WARN() */
10373                 break;
10374         }
10375 }
10376
10377 static int tg3_set_phys_id(struct net_device *dev,
10378                             enum ethtool_phys_id_state state)
10379 {
10380         struct tg3 *tp = netdev_priv(dev);
10381
10382         if (!netif_running(tp->dev))
10383                 return -EAGAIN;
10384
10385         switch (state) {
10386         case ETHTOOL_ID_ACTIVE:
10387                 return 1;       /* cycle on/off once per second */
10388
10389         case ETHTOOL_ID_ON:
10390                 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10391                      LED_CTRL_1000MBPS_ON |
10392                      LED_CTRL_100MBPS_ON |
10393                      LED_CTRL_10MBPS_ON |
10394                      LED_CTRL_TRAFFIC_OVERRIDE |
10395                      LED_CTRL_TRAFFIC_BLINK |
10396                      LED_CTRL_TRAFFIC_LED);
10397                 break;
10398
10399         case ETHTOOL_ID_OFF:
10400                 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10401                      LED_CTRL_TRAFFIC_OVERRIDE);
10402                 break;
10403
10404         case ETHTOOL_ID_INACTIVE:
10405                 tw32(MAC_LED_CTRL, tp->led_ctrl);
10406                 break;
10407         }
10408
10409         return 0;
10410 }
10411
10412 static void tg3_get_ethtool_stats(struct net_device *dev,
10413                                    struct ethtool_stats *estats, u64 *tmp_stats)
10414 {
10415         struct tg3 *tp = netdev_priv(dev);
10416         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10417 }
10418
10419 static __be32 * tg3_vpd_readblock(struct tg3 *tp)
10420 {
10421         int i;
10422         __be32 *buf;
10423         u32 offset = 0, len = 0;
10424         u32 magic, val;
10425
10426         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10427             tg3_nvram_read(tp, 0, &magic))
10428                 return NULL;
10429
10430         if (magic == TG3_EEPROM_MAGIC) {
10431                 for (offset = TG3_NVM_DIR_START;
10432                      offset < TG3_NVM_DIR_END;
10433                      offset += TG3_NVM_DIRENT_SIZE) {
10434                         if (tg3_nvram_read(tp, offset, &val))
10435                                 return NULL;
10436
10437                         if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
10438                             TG3_NVM_DIRTYPE_EXTVPD)
10439                                 break;
10440                 }
10441
10442                 if (offset != TG3_NVM_DIR_END) {
10443                         len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
10444                         if (tg3_nvram_read(tp, offset + 4, &offset))
10445                                 return NULL;
10446
10447                         offset = tg3_nvram_logical_addr(tp, offset);
10448                 }
10449         }
10450
10451         if (!offset || !len) {
10452                 offset = TG3_NVM_VPD_OFF;
10453                 len = TG3_NVM_VPD_LEN;
10454         }
10455
10456         buf = kmalloc(len, GFP_KERNEL);
10457         if (buf == NULL)
10458                 return NULL;
10459
10460         if (magic == TG3_EEPROM_MAGIC) {
10461                 for (i = 0; i < len; i += 4) {
10462                         /* The data is in little-endian format in NVRAM.
10463                          * Use the big-endian read routines to preserve
10464                          * the byte order as it exists in NVRAM.
10465                          */
10466                         if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
10467                                 goto error;
10468                 }
10469         } else {
10470                 u8 *ptr;
10471                 ssize_t cnt;
10472                 unsigned int pos = 0;
10473
10474                 ptr = (u8 *)&buf[0];
10475                 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
10476                         cnt = pci_read_vpd(tp->pdev, pos,
10477                                            len - pos, ptr);
10478                         if (cnt == -ETIMEDOUT || cnt == -EINTR)
10479                                 cnt = 0;
10480                         else if (cnt < 0)
10481                                 goto error;
10482                 }
10483                 if (pos != len)
10484                         goto error;
10485         }
10486
10487         return buf;
10488
10489 error:
10490         kfree(buf);
10491         return NULL;
10492 }
10493
10494 #define NVRAM_TEST_SIZE 0x100
10495 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10496 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10497 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10498 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10499 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10500
10501 static int tg3_test_nvram(struct tg3 *tp)
10502 {
10503         u32 csum, magic;
10504         __be32 *buf;
10505         int i, j, k, err = 0, size;
10506
10507         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10508                 return 0;
10509
10510         if (tg3_nvram_read(tp, 0, &magic) != 0)
10511                 return -EIO;
10512
10513         if (magic == TG3_EEPROM_MAGIC)
10514                 size = NVRAM_TEST_SIZE;
10515         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10516                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10517                     TG3_EEPROM_SB_FORMAT_1) {
10518                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10519                         case TG3_EEPROM_SB_REVISION_0:
10520                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10521                                 break;
10522                         case TG3_EEPROM_SB_REVISION_2:
10523                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10524                                 break;
10525                         case TG3_EEPROM_SB_REVISION_3:
10526                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10527                                 break;
10528                         default:
10529                                 return 0;
10530                         }
10531                 } else
10532                         return 0;
10533         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10534                 size = NVRAM_SELFBOOT_HW_SIZE;
10535         else
10536                 return -EIO;
10537
10538         buf = kmalloc(size, GFP_KERNEL);
10539         if (buf == NULL)
10540                 return -ENOMEM;
10541
10542         err = -EIO;
10543         for (i = 0, j = 0; i < size; i += 4, j++) {
10544                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10545                 if (err)
10546                         break;
10547         }
10548         if (i < size)
10549                 goto out;
10550
10551         /* Selfboot format */
10552         magic = be32_to_cpu(buf[0]);
10553         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10554             TG3_EEPROM_MAGIC_FW) {
10555                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10556
10557                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10558                     TG3_EEPROM_SB_REVISION_2) {
10559                         /* For rev 2, the csum doesn't include the MBA. */
10560                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10561                                 csum8 += buf8[i];
10562                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10563                                 csum8 += buf8[i];
10564                 } else {
10565                         for (i = 0; i < size; i++)
10566                                 csum8 += buf8[i];
10567                 }
10568
10569                 if (csum8 == 0) {
10570                         err = 0;
10571                         goto out;
10572                 }
10573
10574                 err = -EIO;
10575                 goto out;
10576         }
10577
10578         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10579             TG3_EEPROM_MAGIC_HW) {
10580                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10581                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10582                 u8 *buf8 = (u8 *) buf;
10583
10584                 /* Separate the parity bits and the data bytes.  */
10585                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10586                         if ((i == 0) || (i == 8)) {
10587                                 int l;
10588                                 u8 msk;
10589
10590                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10591                                         parity[k++] = buf8[i] & msk;
10592                                 i++;
10593                         } else if (i == 16) {
10594                                 int l;
10595                                 u8 msk;
10596
10597                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10598                                         parity[k++] = buf8[i] & msk;
10599                                 i++;
10600
10601                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10602                                         parity[k++] = buf8[i] & msk;
10603                                 i++;
10604                         }
10605                         data[j++] = buf8[i];
10606                 }
10607
10608                 err = -EIO;
10609                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10610                         u8 hw8 = hweight8(data[i]);
10611
10612                         if ((hw8 & 0x1) && parity[i])
10613                                 goto out;
10614                         else if (!(hw8 & 0x1) && !parity[i])
10615                                 goto out;
10616                 }
10617                 err = 0;
10618                 goto out;
10619         }
10620
10621         err = -EIO;
10622
10623         /* Bootstrap checksum at offset 0x10 */
10624         csum = calc_crc((unsigned char *) buf, 0x10);
10625         if (csum != le32_to_cpu(buf[0x10/4]))
10626                 goto out;
10627
10628         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10629         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10630         if (csum != le32_to_cpu(buf[0xfc/4]))
10631                 goto out;
10632
10633         kfree(buf);
10634
10635         buf = tg3_vpd_readblock(tp);
10636         if (!buf)
10637                 return -ENOMEM;
10638
10639         i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
10640                              PCI_VPD_LRDT_RO_DATA);
10641         if (i > 0) {
10642                 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
10643                 if (j < 0)
10644                         goto out;
10645
10646                 if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
10647                         goto out;
10648
10649                 i += PCI_VPD_LRDT_TAG_SIZE;
10650                 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
10651                                               PCI_VPD_RO_KEYWORD_CHKSUM);
10652                 if (j > 0) {
10653                         u8 csum8 = 0;
10654
10655                         j += PCI_VPD_INFO_FLD_HDR_SIZE;
10656
10657                         for (i = 0; i <= j; i++)
10658                                 csum8 += ((u8 *)buf)[i];
10659
10660                         if (csum8)
10661                                 goto out;
10662                 }
10663         }
10664
10665         err = 0;
10666
10667 out:
10668         kfree(buf);
10669         return err;
10670 }
10671
10672 #define TG3_SERDES_TIMEOUT_SEC  2
10673 #define TG3_COPPER_TIMEOUT_SEC  6
10674
10675 static int tg3_test_link(struct tg3 *tp)
10676 {
10677         int i, max;
10678
10679         if (!netif_running(tp->dev))
10680                 return -ENODEV;
10681
10682         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10683                 max = TG3_SERDES_TIMEOUT_SEC;
10684         else
10685                 max = TG3_COPPER_TIMEOUT_SEC;
10686
10687         for (i = 0; i < max; i++) {
10688                 if (netif_carrier_ok(tp->dev))
10689                         return 0;
10690
10691                 if (msleep_interruptible(1000))
10692                         break;
10693         }
10694
10695         return -EIO;
10696 }
10697
10698 /* Only test the commonly used registers */
10699 static int tg3_test_registers(struct tg3 *tp)
10700 {
10701         int i, is_5705, is_5750;
10702         u32 offset, read_mask, write_mask, val, save_val, read_val;
10703         static struct {
10704                 u16 offset;
10705                 u16 flags;
10706 #define TG3_FL_5705     0x1
10707 #define TG3_FL_NOT_5705 0x2
10708 #define TG3_FL_NOT_5788 0x4
10709 #define TG3_FL_NOT_5750 0x8
10710                 u32 read_mask;
10711                 u32 write_mask;
10712         } reg_tbl[] = {
10713                 /* MAC Control Registers */
10714                 { MAC_MODE, TG3_FL_NOT_5705,
10715                         0x00000000, 0x00ef6f8c },
10716                 { MAC_MODE, TG3_FL_5705,
10717                         0x00000000, 0x01ef6b8c },
10718                 { MAC_STATUS, TG3_FL_NOT_5705,
10719                         0x03800107, 0x00000000 },
10720                 { MAC_STATUS, TG3_FL_5705,
10721                         0x03800100, 0x00000000 },
10722                 { MAC_ADDR_0_HIGH, 0x0000,
10723                         0x00000000, 0x0000ffff },
10724                 { MAC_ADDR_0_LOW, 0x0000,
10725                         0x00000000, 0xffffffff },
10726                 { MAC_RX_MTU_SIZE, 0x0000,
10727                         0x00000000, 0x0000ffff },
10728                 { MAC_TX_MODE, 0x0000,
10729                         0x00000000, 0x00000070 },
10730                 { MAC_TX_LENGTHS, 0x0000,
10731                         0x00000000, 0x00003fff },
10732                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10733                         0x00000000, 0x000007fc },
10734                 { MAC_RX_MODE, TG3_FL_5705,
10735                         0x00000000, 0x000007dc },
10736                 { MAC_HASH_REG_0, 0x0000,
10737                         0x00000000, 0xffffffff },
10738                 { MAC_HASH_REG_1, 0x0000,
10739                         0x00000000, 0xffffffff },
10740                 { MAC_HASH_REG_2, 0x0000,
10741                         0x00000000, 0xffffffff },
10742                 { MAC_HASH_REG_3, 0x0000,
10743                         0x00000000, 0xffffffff },
10744
10745                 /* Receive Data and Receive BD Initiator Control Registers. */
10746                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10747                         0x00000000, 0xffffffff },
10748                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10749                         0x00000000, 0xffffffff },
10750                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10751                         0x00000000, 0x00000003 },
10752                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10753                         0x00000000, 0xffffffff },
10754                 { RCVDBDI_STD_BD+0, 0x0000,
10755                         0x00000000, 0xffffffff },
10756                 { RCVDBDI_STD_BD+4, 0x0000,
10757                         0x00000000, 0xffffffff },
10758                 { RCVDBDI_STD_BD+8, 0x0000,
10759                         0x00000000, 0xffff0002 },
10760                 { RCVDBDI_STD_BD+0xc, 0x0000,
10761                         0x00000000, 0xffffffff },
10762
10763                 /* Receive BD Initiator Control Registers. */
10764                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10765                         0x00000000, 0xffffffff },
10766                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10767                         0x00000000, 0x000003ff },
10768                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10769                         0x00000000, 0xffffffff },
10770
10771                 /* Host Coalescing Control Registers. */
10772                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10773                         0x00000000, 0x00000004 },
10774                 { HOSTCC_MODE, TG3_FL_5705,
10775                         0x00000000, 0x000000f6 },
10776                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10777                         0x00000000, 0xffffffff },
10778                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10779                         0x00000000, 0x000003ff },
10780                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10781                         0x00000000, 0xffffffff },
10782                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10783                         0x00000000, 0x000003ff },
10784                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10785                         0x00000000, 0xffffffff },
10786                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10787                         0x00000000, 0x000000ff },
10788                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10789                         0x00000000, 0xffffffff },
10790                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10791                         0x00000000, 0x000000ff },
10792                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10793                         0x00000000, 0xffffffff },
10794                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10795                         0x00000000, 0xffffffff },
10796                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10797                         0x00000000, 0xffffffff },
10798                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10799                         0x00000000, 0x000000ff },
10800                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10801                         0x00000000, 0xffffffff },
10802                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10803                         0x00000000, 0x000000ff },
10804                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10805                         0x00000000, 0xffffffff },
10806                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10807                         0x00000000, 0xffffffff },
10808                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10809                         0x00000000, 0xffffffff },
10810                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10811                         0x00000000, 0xffffffff },
10812                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10813                         0x00000000, 0xffffffff },
10814                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10815                         0xffffffff, 0x00000000 },
10816                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10817                         0xffffffff, 0x00000000 },
10818
10819                 /* Buffer Manager Control Registers. */
10820                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10821                         0x00000000, 0x007fff80 },
10822                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10823                         0x00000000, 0x007fffff },
10824                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10825                         0x00000000, 0x0000003f },
10826                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10827                         0x00000000, 0x000001ff },
10828                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10829                         0x00000000, 0x000001ff },
10830                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10831                         0xffffffff, 0x00000000 },
10832                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10833                         0xffffffff, 0x00000000 },
10834
10835                 /* Mailbox Registers */
10836                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10837                         0x00000000, 0x000001ff },
10838                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10839                         0x00000000, 0x000001ff },
10840                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10841                         0x00000000, 0x000007ff },
10842                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10843                         0x00000000, 0x000001ff },
10844
10845                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10846         };
10847
10848         is_5705 = is_5750 = 0;
10849         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10850                 is_5705 = 1;
10851                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10852                         is_5750 = 1;
10853         }
10854
10855         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10856                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10857                         continue;
10858
10859                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10860                         continue;
10861
10862                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10863                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10864                         continue;
10865
10866                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10867                         continue;
10868
10869                 offset = (u32) reg_tbl[i].offset;
10870                 read_mask = reg_tbl[i].read_mask;
10871                 write_mask = reg_tbl[i].write_mask;
10872
10873                 /* Save the original register content */
10874                 save_val = tr32(offset);
10875
10876                 /* Determine the read-only value. */
10877                 read_val = save_val & read_mask;
10878
10879                 /* Write zero to the register, then make sure the read-only bits
10880                  * are not changed and the read/write bits are all zeros.
10881                  */
10882                 tw32(offset, 0);
10883
10884                 val = tr32(offset);
10885
10886                 /* Test the read-only and read/write bits. */
10887                 if (((val & read_mask) != read_val) || (val & write_mask))
10888                         goto out;
10889
10890                 /* Write ones to all the bits defined by RdMask and WrMask, then
10891                  * make sure the read-only bits are not changed and the
10892                  * read/write bits are all ones.
10893                  */
10894                 tw32(offset, read_mask | write_mask);
10895
10896                 val = tr32(offset);
10897
10898                 /* Test the read-only bits. */
10899                 if ((val & read_mask) != read_val)
10900                         goto out;
10901
10902                 /* Test the read/write bits. */
10903                 if ((val & write_mask) != write_mask)
10904                         goto out;
10905
10906                 tw32(offset, save_val);
10907         }
10908
10909         return 0;
10910
10911 out:
10912         if (netif_msg_hw(tp))
10913                 netdev_err(tp->dev,
10914                            "Register test failed at offset %x\n", offset);
10915         tw32(offset, save_val);
10916         return -EIO;
10917 }
10918
10919 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10920 {
10921         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10922         int i;
10923         u32 j;
10924
10925         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10926                 for (j = 0; j < len; j += 4) {
10927                         u32 val;
10928
10929                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10930                         tg3_read_mem(tp, offset + j, &val);
10931                         if (val != test_pattern[i])
10932                                 return -EIO;
10933                 }
10934         }
10935         return 0;
10936 }
10937
10938 static int tg3_test_memory(struct tg3 *tp)
10939 {
10940         static struct mem_entry {
10941                 u32 offset;
10942                 u32 len;
10943         } mem_tbl_570x[] = {
10944                 { 0x00000000, 0x00b50},
10945                 { 0x00002000, 0x1c000},
10946                 { 0xffffffff, 0x00000}
10947         }, mem_tbl_5705[] = {
10948                 { 0x00000100, 0x0000c},
10949                 { 0x00000200, 0x00008},
10950                 { 0x00004000, 0x00800},
10951                 { 0x00006000, 0x01000},
10952                 { 0x00008000, 0x02000},
10953                 { 0x00010000, 0x0e000},
10954                 { 0xffffffff, 0x00000}
10955         }, mem_tbl_5755[] = {
10956                 { 0x00000200, 0x00008},
10957                 { 0x00004000, 0x00800},
10958                 { 0x00006000, 0x00800},
10959                 { 0x00008000, 0x02000},
10960                 { 0x00010000, 0x0c000},
10961                 { 0xffffffff, 0x00000}
10962         }, mem_tbl_5906[] = {
10963                 { 0x00000200, 0x00008},
10964                 { 0x00004000, 0x00400},
10965                 { 0x00006000, 0x00400},
10966                 { 0x00008000, 0x01000},
10967                 { 0x00010000, 0x01000},
10968                 { 0xffffffff, 0x00000}
10969         }, mem_tbl_5717[] = {
10970                 { 0x00000200, 0x00008},
10971                 { 0x00010000, 0x0a000},
10972                 { 0x00020000, 0x13c00},
10973                 { 0xffffffff, 0x00000}
10974         }, mem_tbl_57765[] = {
10975                 { 0x00000200, 0x00008},
10976                 { 0x00004000, 0x00800},
10977                 { 0x00006000, 0x09800},
10978                 { 0x00010000, 0x0a000},
10979                 { 0xffffffff, 0x00000}
10980         };
10981         struct mem_entry *mem_tbl;
10982         int err = 0;
10983         int i;
10984
10985         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
10986                 mem_tbl = mem_tbl_5717;
10987         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10988                 mem_tbl = mem_tbl_57765;
10989         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10990                 mem_tbl = mem_tbl_5755;
10991         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10992                 mem_tbl = mem_tbl_5906;
10993         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10994                 mem_tbl = mem_tbl_5705;
10995         else
10996                 mem_tbl = mem_tbl_570x;
10997
10998         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10999                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
11000                 if (err)
11001                         break;
11002         }
11003
11004         return err;
11005 }
11006
11007 #define TG3_MAC_LOOPBACK        0
11008 #define TG3_PHY_LOOPBACK        1
11009
11010 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode)
11011 {
11012         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
11013         u32 desc_idx, coal_now;
11014         struct sk_buff *skb, *rx_skb;
11015         u8 *tx_data;
11016         dma_addr_t map;
11017         int num_pkts, tx_len, rx_len, i, err;
11018         struct tg3_rx_buffer_desc *desc;
11019         struct tg3_napi *tnapi, *rnapi;
11020         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
11021
11022         tnapi = &tp->napi[0];
11023         rnapi = &tp->napi[0];
11024         if (tp->irq_cnt > 1) {
11025                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
11026                         rnapi = &tp->napi[1];
11027                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
11028                         tnapi = &tp->napi[1];
11029         }
11030         coal_now = tnapi->coal_now | rnapi->coal_now;
11031
11032         if (loopback_mode == TG3_MAC_LOOPBACK) {
11033                 /* HW errata - mac loopback fails in some cases on 5780.
11034                  * Normal traffic and PHY loopback are not affected by
11035                  * errata.  Also, the MAC loopback test is deprecated for
11036                  * all newer ASIC revisions.
11037                  */
11038                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11039                     (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
11040                         return 0;
11041
11042                 mac_mode = tp->mac_mode &
11043                            ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
11044                 mac_mode |= MAC_MODE_PORT_INT_LPBACK;
11045                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11046                         mac_mode |= MAC_MODE_LINK_POLARITY;
11047                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
11048                         mac_mode |= MAC_MODE_PORT_MODE_MII;
11049                 else
11050                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
11051                 tw32(MAC_MODE, mac_mode);
11052         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
11053                 u32 val;
11054
11055                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
11056                         tg3_phy_fet_toggle_apd(tp, false);
11057                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
11058                 } else
11059                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
11060
11061                 tg3_phy_toggle_automdix(tp, 0);
11062
11063                 tg3_writephy(tp, MII_BMCR, val);
11064                 udelay(40);
11065
11066                 mac_mode = tp->mac_mode &
11067                            ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
11068                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
11069                         tg3_writephy(tp, MII_TG3_FET_PTEST,
11070                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
11071                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
11072                         /* The write needs to be flushed for the AC131 */
11073                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11074                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
11075                         mac_mode |= MAC_MODE_PORT_MODE_MII;
11076                 } else
11077                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
11078
11079                 /* reset to prevent losing 1st rx packet intermittently */
11080                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
11081                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
11082                         udelay(10);
11083                         tw32_f(MAC_RX_MODE, tp->rx_mode);
11084                 }
11085                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
11086                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
11087                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
11088                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
11089                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
11090                                 mac_mode |= MAC_MODE_LINK_POLARITY;
11091                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
11092                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
11093                 }
11094                 tw32(MAC_MODE, mac_mode);
11095
11096                 /* Wait for link */
11097                 for (i = 0; i < 100; i++) {
11098                         if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11099                                 break;
11100                         mdelay(1);
11101                 }
11102         } else {
11103                 return -EINVAL;
11104         }
11105
11106         err = -EIO;
11107
11108         tx_len = pktsz;
11109         skb = netdev_alloc_skb(tp->dev, tx_len);
11110         if (!skb)
11111                 return -ENOMEM;
11112
11113         tx_data = skb_put(skb, tx_len);
11114         memcpy(tx_data, tp->dev->dev_addr, 6);
11115         memset(tx_data + 6, 0x0, 8);
11116
11117         tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
11118
11119         for (i = 14; i < tx_len; i++)
11120                 tx_data[i] = (u8) (i & 0xff);
11121
11122         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11123         if (pci_dma_mapping_error(tp->pdev, map)) {
11124                 dev_kfree_skb(skb);
11125                 return -EIO;
11126         }
11127
11128         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11129                rnapi->coal_now);
11130
11131         udelay(10);
11132
11133         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11134
11135         num_pkts = 0;
11136
11137         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
11138
11139         tnapi->tx_prod++;
11140         num_pkts++;
11141
11142         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11143         tr32_mailbox(tnapi->prodmbox);
11144
11145         udelay(10);
11146
11147         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
11148         for (i = 0; i < 35; i++) {
11149                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11150                        coal_now);
11151
11152                 udelay(10);
11153
11154                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11155                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11156                 if ((tx_idx == tnapi->tx_prod) &&
11157                     (rx_idx == (rx_start_idx + num_pkts)))
11158                         break;
11159         }
11160
11161         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
11162         dev_kfree_skb(skb);
11163
11164         if (tx_idx != tnapi->tx_prod)
11165                 goto out;
11166
11167         if (rx_idx != rx_start_idx + num_pkts)
11168                 goto out;
11169
11170         desc = &rnapi->rx_rcb[rx_start_idx];
11171         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11172         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11173
11174         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11175             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11176                 goto out;
11177
11178         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
11179         if (rx_len != tx_len)
11180                 goto out;
11181
11182         if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
11183                 if (opaque_key != RXD_OPAQUE_RING_STD)
11184                         goto out;
11185
11186                 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11187                 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
11188         } else {
11189                 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
11190                         goto out;
11191
11192                 rx_skb = tpr->rx_jmb_buffers[desc_idx].skb;
11193                 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], mapping);
11194         }
11195
11196         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
11197
11198         for (i = 14; i < tx_len; i++) {
11199                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
11200                         goto out;
11201         }
11202         err = 0;
11203
11204         /* tg3_free_rings will unmap and free the rx_skb */
11205 out:
11206         return err;
11207 }
11208
11209 #define TG3_MAC_LOOPBACK_FAILED         1
11210 #define TG3_PHY_LOOPBACK_FAILED         2
11211 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
11212                                          TG3_PHY_LOOPBACK_FAILED)
11213
11214 static int tg3_test_loopback(struct tg3 *tp)
11215 {
11216         int err = 0;
11217         u32 eee_cap, cpmuctrl = 0;
11218
11219         if (!netif_running(tp->dev))
11220                 return TG3_LOOPBACK_FAILED;
11221
11222         eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11223         tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11224
11225         err = tg3_reset_hw(tp, 1);
11226         if (err) {
11227                 err = TG3_LOOPBACK_FAILED;
11228                 goto done;
11229         }
11230
11231         /* Turn off gphy autopowerdown. */
11232         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11233                 tg3_phy_toggle_apd(tp, false);
11234
11235         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11236                 int i;
11237                 u32 status;
11238
11239                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11240
11241                 /* Wait for up to 40 microseconds to acquire lock. */
11242                 for (i = 0; i < 4; i++) {
11243                         status = tr32(TG3_CPMU_MUTEX_GNT);
11244                         if (status == CPMU_MUTEX_GNT_DRIVER)
11245                                 break;
11246                         udelay(10);
11247                 }
11248
11249                 if (status != CPMU_MUTEX_GNT_DRIVER) {
11250                         err = TG3_LOOPBACK_FAILED;
11251                         goto done;
11252                 }
11253
11254                 /* Turn off link-based power management. */
11255                 cpmuctrl = tr32(TG3_CPMU_CTRL);
11256                 tw32(TG3_CPMU_CTRL,
11257                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11258                                   CPMU_CTRL_LINK_AWARE_MODE));
11259         }
11260
11261         if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_MAC_LOOPBACK))
11262                 err |= TG3_MAC_LOOPBACK_FAILED;
11263
11264         if ((tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) &&
11265             tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_MAC_LOOPBACK))
11266                 err |= (TG3_MAC_LOOPBACK_FAILED << 2);
11267
11268         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11269                 tw32(TG3_CPMU_CTRL, cpmuctrl);
11270
11271                 /* Release the mutex */
11272                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11273         }
11274
11275         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11276             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11277                 if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_PHY_LOOPBACK))
11278                         err |= TG3_PHY_LOOPBACK_FAILED;
11279                 if ((tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) &&
11280                     tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_PHY_LOOPBACK))
11281                         err |= (TG3_PHY_LOOPBACK_FAILED << 2);
11282         }
11283
11284         /* Re-enable gphy autopowerdown. */
11285         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11286                 tg3_phy_toggle_apd(tp, true);
11287
11288 done:
11289         tp->phy_flags |= eee_cap;
11290
11291         return err;
11292 }
11293
11294 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11295                           u64 *data)
11296 {
11297         struct tg3 *tp = netdev_priv(dev);
11298
11299         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11300                 tg3_power_up(tp);
11301
11302         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11303
11304         if (tg3_test_nvram(tp) != 0) {
11305                 etest->flags |= ETH_TEST_FL_FAILED;
11306                 data[0] = 1;
11307         }
11308         if (tg3_test_link(tp) != 0) {
11309                 etest->flags |= ETH_TEST_FL_FAILED;
11310                 data[1] = 1;
11311         }
11312         if (etest->flags & ETH_TEST_FL_OFFLINE) {
11313                 int err, err2 = 0, irq_sync = 0;
11314
11315                 if (netif_running(dev)) {
11316                         tg3_phy_stop(tp);
11317                         tg3_netif_stop(tp);
11318                         irq_sync = 1;
11319                 }
11320
11321                 tg3_full_lock(tp, irq_sync);
11322
11323                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11324                 err = tg3_nvram_lock(tp);
11325                 tg3_halt_cpu(tp, RX_CPU_BASE);
11326                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11327                         tg3_halt_cpu(tp, TX_CPU_BASE);
11328                 if (!err)
11329                         tg3_nvram_unlock(tp);
11330
11331                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11332                         tg3_phy_reset(tp);
11333
11334                 if (tg3_test_registers(tp) != 0) {
11335                         etest->flags |= ETH_TEST_FL_FAILED;
11336                         data[2] = 1;
11337                 }
11338                 if (tg3_test_memory(tp) != 0) {
11339                         etest->flags |= ETH_TEST_FL_FAILED;
11340                         data[3] = 1;
11341                 }
11342                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11343                         etest->flags |= ETH_TEST_FL_FAILED;
11344
11345                 tg3_full_unlock(tp);
11346
11347                 if (tg3_test_interrupt(tp) != 0) {
11348                         etest->flags |= ETH_TEST_FL_FAILED;
11349                         data[5] = 1;
11350                 }
11351
11352                 tg3_full_lock(tp, 0);
11353
11354                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11355                 if (netif_running(dev)) {
11356                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11357                         err2 = tg3_restart_hw(tp, 1);
11358                         if (!err2)
11359                                 tg3_netif_start(tp);
11360                 }
11361
11362                 tg3_full_unlock(tp);
11363
11364                 if (irq_sync && !err2)
11365                         tg3_phy_start(tp);
11366         }
11367         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11368                 tg3_power_down(tp);
11369
11370 }
11371
11372 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11373 {
11374         struct mii_ioctl_data *data = if_mii(ifr);
11375         struct tg3 *tp = netdev_priv(dev);
11376         int err;
11377
11378         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11379                 struct phy_device *phydev;
11380                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11381                         return -EAGAIN;
11382                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11383                 return phy_mii_ioctl(phydev, ifr, cmd);
11384         }
11385
11386         switch (cmd) {
11387         case SIOCGMIIPHY:
11388                 data->phy_id = tp->phy_addr;
11389
11390                 /* fallthru */
11391         case SIOCGMIIREG: {
11392                 u32 mii_regval;
11393
11394                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11395                         break;                  /* We have no PHY */
11396
11397                 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
11398                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
11399                      !netif_running(dev)))
11400                         return -EAGAIN;
11401
11402                 spin_lock_bh(&tp->lock);
11403                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11404                 spin_unlock_bh(&tp->lock);
11405
11406                 data->val_out = mii_regval;
11407
11408                 return err;
11409         }
11410
11411         case SIOCSMIIREG:
11412                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11413                         break;                  /* We have no PHY */
11414
11415                 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
11416                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
11417                      !netif_running(dev)))
11418                         return -EAGAIN;
11419
11420                 spin_lock_bh(&tp->lock);
11421                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11422                 spin_unlock_bh(&tp->lock);
11423
11424                 return err;
11425
11426         default:
11427                 /* do nothing */
11428                 break;
11429         }
11430         return -EOPNOTSUPP;
11431 }
11432
11433 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11434 {
11435         struct tg3 *tp = netdev_priv(dev);
11436
11437         memcpy(ec, &tp->coal, sizeof(*ec));
11438         return 0;
11439 }
11440
11441 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11442 {
11443         struct tg3 *tp = netdev_priv(dev);
11444         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11445         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11446
11447         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11448                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11449                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11450                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11451                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11452         }
11453
11454         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11455             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11456             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11457             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11458             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11459             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11460             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11461             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11462             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11463             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11464                 return -EINVAL;
11465
11466         /* No rx interrupts will be generated if both are zero */
11467         if ((ec->rx_coalesce_usecs == 0) &&
11468             (ec->rx_max_coalesced_frames == 0))
11469                 return -EINVAL;
11470
11471         /* No tx interrupts will be generated if both are zero */
11472         if ((ec->tx_coalesce_usecs == 0) &&
11473             (ec->tx_max_coalesced_frames == 0))
11474                 return -EINVAL;
11475
11476         /* Only copy relevant parameters, ignore all others. */
11477         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11478         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11479         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11480         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11481         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11482         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11483         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11484         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11485         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11486
11487         if (netif_running(dev)) {
11488                 tg3_full_lock(tp, 0);
11489                 __tg3_set_coalesce(tp, &tp->coal);
11490                 tg3_full_unlock(tp);
11491         }
11492         return 0;
11493 }
11494
11495 static const struct ethtool_ops tg3_ethtool_ops = {
11496         .get_settings           = tg3_get_settings,
11497         .set_settings           = tg3_set_settings,
11498         .get_drvinfo            = tg3_get_drvinfo,
11499         .get_regs_len           = tg3_get_regs_len,
11500         .get_regs               = tg3_get_regs,
11501         .get_wol                = tg3_get_wol,
11502         .set_wol                = tg3_set_wol,
11503         .get_msglevel           = tg3_get_msglevel,
11504         .set_msglevel           = tg3_set_msglevel,
11505         .nway_reset             = tg3_nway_reset,
11506         .get_link               = ethtool_op_get_link,
11507         .get_eeprom_len         = tg3_get_eeprom_len,
11508         .get_eeprom             = tg3_get_eeprom,
11509         .set_eeprom             = tg3_set_eeprom,
11510         .get_ringparam          = tg3_get_ringparam,
11511         .set_ringparam          = tg3_set_ringparam,
11512         .get_pauseparam         = tg3_get_pauseparam,
11513         .set_pauseparam         = tg3_set_pauseparam,
11514         .self_test              = tg3_self_test,
11515         .get_strings            = tg3_get_strings,
11516         .set_phys_id            = tg3_set_phys_id,
11517         .get_ethtool_stats      = tg3_get_ethtool_stats,
11518         .get_coalesce           = tg3_get_coalesce,
11519         .set_coalesce           = tg3_set_coalesce,
11520         .get_sset_count         = tg3_get_sset_count,
11521 };
11522
11523 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11524 {
11525         u32 cursize, val, magic;
11526
11527         tp->nvram_size = EEPROM_CHIP_SIZE;
11528
11529         if (tg3_nvram_read(tp, 0, &magic) != 0)
11530                 return;
11531
11532         if ((magic != TG3_EEPROM_MAGIC) &&
11533             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11534             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11535                 return;
11536
11537         /*
11538          * Size the chip by reading offsets at increasing powers of two.
11539          * When we encounter our validation signature, we know the addressing
11540          * has wrapped around, and thus have our chip size.
11541          */
11542         cursize = 0x10;
11543
11544         while (cursize < tp->nvram_size) {
11545                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11546                         return;
11547
11548                 if (val == magic)
11549                         break;
11550
11551                 cursize <<= 1;
11552         }
11553
11554         tp->nvram_size = cursize;
11555 }
11556
11557 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11558 {
11559         u32 val;
11560
11561         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11562             tg3_nvram_read(tp, 0, &val) != 0)
11563                 return;
11564
11565         /* Selfboot format */
11566         if (val != TG3_EEPROM_MAGIC) {
11567                 tg3_get_eeprom_size(tp);
11568                 return;
11569         }
11570
11571         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11572                 if (val != 0) {
11573                         /* This is confusing.  We want to operate on the
11574                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11575                          * call will read from NVRAM and byteswap the data
11576                          * according to the byteswapping settings for all
11577                          * other register accesses.  This ensures the data we
11578                          * want will always reside in the lower 16-bits.
11579                          * However, the data in NVRAM is in LE format, which
11580                          * means the data from the NVRAM read will always be
11581                          * opposite the endianness of the CPU.  The 16-bit
11582                          * byteswap then brings the data to CPU endianness.
11583                          */
11584                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11585                         return;
11586                 }
11587         }
11588         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11589 }
11590
11591 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11592 {
11593         u32 nvcfg1;
11594
11595         nvcfg1 = tr32(NVRAM_CFG1);
11596         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11597                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11598         } else {
11599                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11600                 tw32(NVRAM_CFG1, nvcfg1);
11601         }
11602
11603         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11604             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11605                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11606                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11607                         tp->nvram_jedecnum = JEDEC_ATMEL;
11608                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11609                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11610                         break;
11611                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11612                         tp->nvram_jedecnum = JEDEC_ATMEL;
11613                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11614                         break;
11615                 case FLASH_VENDOR_ATMEL_EEPROM:
11616                         tp->nvram_jedecnum = JEDEC_ATMEL;
11617                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11618                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11619                         break;
11620                 case FLASH_VENDOR_ST:
11621                         tp->nvram_jedecnum = JEDEC_ST;
11622                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11623                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11624                         break;
11625                 case FLASH_VENDOR_SAIFUN:
11626                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11627                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11628                         break;
11629                 case FLASH_VENDOR_SST_SMALL:
11630                 case FLASH_VENDOR_SST_LARGE:
11631                         tp->nvram_jedecnum = JEDEC_SST;
11632                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11633                         break;
11634                 }
11635         } else {
11636                 tp->nvram_jedecnum = JEDEC_ATMEL;
11637                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11638                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11639         }
11640 }
11641
11642 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11643 {
11644         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11645         case FLASH_5752PAGE_SIZE_256:
11646                 tp->nvram_pagesize = 256;
11647                 break;
11648         case FLASH_5752PAGE_SIZE_512:
11649                 tp->nvram_pagesize = 512;
11650                 break;
11651         case FLASH_5752PAGE_SIZE_1K:
11652                 tp->nvram_pagesize = 1024;
11653                 break;
11654         case FLASH_5752PAGE_SIZE_2K:
11655                 tp->nvram_pagesize = 2048;
11656                 break;
11657         case FLASH_5752PAGE_SIZE_4K:
11658                 tp->nvram_pagesize = 4096;
11659                 break;
11660         case FLASH_5752PAGE_SIZE_264:
11661                 tp->nvram_pagesize = 264;
11662                 break;
11663         case FLASH_5752PAGE_SIZE_528:
11664                 tp->nvram_pagesize = 528;
11665                 break;
11666         }
11667 }
11668
11669 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11670 {
11671         u32 nvcfg1;
11672
11673         nvcfg1 = tr32(NVRAM_CFG1);
11674
11675         /* NVRAM protection for TPM */
11676         if (nvcfg1 & (1 << 27))
11677                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11678
11679         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11680         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11681         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11682                 tp->nvram_jedecnum = JEDEC_ATMEL;
11683                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11684                 break;
11685         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11686                 tp->nvram_jedecnum = JEDEC_ATMEL;
11687                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11688                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11689                 break;
11690         case FLASH_5752VENDOR_ST_M45PE10:
11691         case FLASH_5752VENDOR_ST_M45PE20:
11692         case FLASH_5752VENDOR_ST_M45PE40:
11693                 tp->nvram_jedecnum = JEDEC_ST;
11694                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11695                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11696                 break;
11697         }
11698
11699         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11700                 tg3_nvram_get_pagesize(tp, nvcfg1);
11701         } else {
11702                 /* For eeprom, set pagesize to maximum eeprom size */
11703                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11704
11705                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11706                 tw32(NVRAM_CFG1, nvcfg1);
11707         }
11708 }
11709
11710 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11711 {
11712         u32 nvcfg1, protect = 0;
11713
11714         nvcfg1 = tr32(NVRAM_CFG1);
11715
11716         /* NVRAM protection for TPM */
11717         if (nvcfg1 & (1 << 27)) {
11718                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11719                 protect = 1;
11720         }
11721
11722         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11723         switch (nvcfg1) {
11724         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11725         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11726         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11727         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11728                 tp->nvram_jedecnum = JEDEC_ATMEL;
11729                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11730                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11731                 tp->nvram_pagesize = 264;
11732                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11733                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11734                         tp->nvram_size = (protect ? 0x3e200 :
11735                                           TG3_NVRAM_SIZE_512KB);
11736                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11737                         tp->nvram_size = (protect ? 0x1f200 :
11738                                           TG3_NVRAM_SIZE_256KB);
11739                 else
11740                         tp->nvram_size = (protect ? 0x1f200 :
11741                                           TG3_NVRAM_SIZE_128KB);
11742                 break;
11743         case FLASH_5752VENDOR_ST_M45PE10:
11744         case FLASH_5752VENDOR_ST_M45PE20:
11745         case FLASH_5752VENDOR_ST_M45PE40:
11746                 tp->nvram_jedecnum = JEDEC_ST;
11747                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11748                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11749                 tp->nvram_pagesize = 256;
11750                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11751                         tp->nvram_size = (protect ?
11752                                           TG3_NVRAM_SIZE_64KB :
11753                                           TG3_NVRAM_SIZE_128KB);
11754                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11755                         tp->nvram_size = (protect ?
11756                                           TG3_NVRAM_SIZE_64KB :
11757                                           TG3_NVRAM_SIZE_256KB);
11758                 else
11759                         tp->nvram_size = (protect ?
11760                                           TG3_NVRAM_SIZE_128KB :
11761                                           TG3_NVRAM_SIZE_512KB);
11762                 break;
11763         }
11764 }
11765
11766 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11767 {
11768         u32 nvcfg1;
11769
11770         nvcfg1 = tr32(NVRAM_CFG1);
11771
11772         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11773         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11774         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11775         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11776         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11777                 tp->nvram_jedecnum = JEDEC_ATMEL;
11778                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11779                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11780
11781                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11782                 tw32(NVRAM_CFG1, nvcfg1);
11783                 break;
11784         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11785         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11786         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11787         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11788                 tp->nvram_jedecnum = JEDEC_ATMEL;
11789                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11790                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11791                 tp->nvram_pagesize = 264;
11792                 break;
11793         case FLASH_5752VENDOR_ST_M45PE10:
11794         case FLASH_5752VENDOR_ST_M45PE20:
11795         case FLASH_5752VENDOR_ST_M45PE40:
11796                 tp->nvram_jedecnum = JEDEC_ST;
11797                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11798                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11799                 tp->nvram_pagesize = 256;
11800                 break;
11801         }
11802 }
11803
11804 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11805 {
11806         u32 nvcfg1, protect = 0;
11807
11808         nvcfg1 = tr32(NVRAM_CFG1);
11809
11810         /* NVRAM protection for TPM */
11811         if (nvcfg1 & (1 << 27)) {
11812                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11813                 protect = 1;
11814         }
11815
11816         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11817         switch (nvcfg1) {
11818         case FLASH_5761VENDOR_ATMEL_ADB021D:
11819         case FLASH_5761VENDOR_ATMEL_ADB041D:
11820         case FLASH_5761VENDOR_ATMEL_ADB081D:
11821         case FLASH_5761VENDOR_ATMEL_ADB161D:
11822         case FLASH_5761VENDOR_ATMEL_MDB021D:
11823         case FLASH_5761VENDOR_ATMEL_MDB041D:
11824         case FLASH_5761VENDOR_ATMEL_MDB081D:
11825         case FLASH_5761VENDOR_ATMEL_MDB161D:
11826                 tp->nvram_jedecnum = JEDEC_ATMEL;
11827                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11828                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11829                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11830                 tp->nvram_pagesize = 256;
11831                 break;
11832         case FLASH_5761VENDOR_ST_A_M45PE20:
11833         case FLASH_5761VENDOR_ST_A_M45PE40:
11834         case FLASH_5761VENDOR_ST_A_M45PE80:
11835         case FLASH_5761VENDOR_ST_A_M45PE16:
11836         case FLASH_5761VENDOR_ST_M_M45PE20:
11837         case FLASH_5761VENDOR_ST_M_M45PE40:
11838         case FLASH_5761VENDOR_ST_M_M45PE80:
11839         case FLASH_5761VENDOR_ST_M_M45PE16:
11840                 tp->nvram_jedecnum = JEDEC_ST;
11841                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11842                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11843                 tp->nvram_pagesize = 256;
11844                 break;
11845         }
11846
11847         if (protect) {
11848                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11849         } else {
11850                 switch (nvcfg1) {
11851                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11852                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11853                 case FLASH_5761VENDOR_ST_A_M45PE16:
11854                 case FLASH_5761VENDOR_ST_M_M45PE16:
11855                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11856                         break;
11857                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11858                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11859                 case FLASH_5761VENDOR_ST_A_M45PE80:
11860                 case FLASH_5761VENDOR_ST_M_M45PE80:
11861                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11862                         break;
11863                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11864                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11865                 case FLASH_5761VENDOR_ST_A_M45PE40:
11866                 case FLASH_5761VENDOR_ST_M_M45PE40:
11867                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11868                         break;
11869                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11870                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11871                 case FLASH_5761VENDOR_ST_A_M45PE20:
11872                 case FLASH_5761VENDOR_ST_M_M45PE20:
11873                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11874                         break;
11875                 }
11876         }
11877 }
11878
11879 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11880 {
11881         tp->nvram_jedecnum = JEDEC_ATMEL;
11882         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11883         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11884 }
11885
11886 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11887 {
11888         u32 nvcfg1;
11889
11890         nvcfg1 = tr32(NVRAM_CFG1);
11891
11892         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11893         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11894         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11895                 tp->nvram_jedecnum = JEDEC_ATMEL;
11896                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11897                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11898
11899                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11900                 tw32(NVRAM_CFG1, nvcfg1);
11901                 return;
11902         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11903         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11904         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11905         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11906         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11907         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11908         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11909                 tp->nvram_jedecnum = JEDEC_ATMEL;
11910                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11911                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11912
11913                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11914                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11915                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11916                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11917                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11918                         break;
11919                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11920                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11921                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11922                         break;
11923                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11924                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11925                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11926                         break;
11927                 }
11928                 break;
11929         case FLASH_5752VENDOR_ST_M45PE10:
11930         case FLASH_5752VENDOR_ST_M45PE20:
11931         case FLASH_5752VENDOR_ST_M45PE40:
11932                 tp->nvram_jedecnum = JEDEC_ST;
11933                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11934                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11935
11936                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11937                 case FLASH_5752VENDOR_ST_M45PE10:
11938                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11939                         break;
11940                 case FLASH_5752VENDOR_ST_M45PE20:
11941                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11942                         break;
11943                 case FLASH_5752VENDOR_ST_M45PE40:
11944                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11945                         break;
11946                 }
11947                 break;
11948         default:
11949                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11950                 return;
11951         }
11952
11953         tg3_nvram_get_pagesize(tp, nvcfg1);
11954         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11955                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11956 }
11957
11958
11959 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11960 {
11961         u32 nvcfg1;
11962
11963         nvcfg1 = tr32(NVRAM_CFG1);
11964
11965         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11966         case FLASH_5717VENDOR_ATMEL_EEPROM:
11967         case FLASH_5717VENDOR_MICRO_EEPROM:
11968                 tp->nvram_jedecnum = JEDEC_ATMEL;
11969                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11970                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11971
11972                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11973                 tw32(NVRAM_CFG1, nvcfg1);
11974                 return;
11975         case FLASH_5717VENDOR_ATMEL_MDB011D:
11976         case FLASH_5717VENDOR_ATMEL_ADB011B:
11977         case FLASH_5717VENDOR_ATMEL_ADB011D:
11978         case FLASH_5717VENDOR_ATMEL_MDB021D:
11979         case FLASH_5717VENDOR_ATMEL_ADB021B:
11980         case FLASH_5717VENDOR_ATMEL_ADB021D:
11981         case FLASH_5717VENDOR_ATMEL_45USPT:
11982                 tp->nvram_jedecnum = JEDEC_ATMEL;
11983                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11984                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11985
11986                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11987                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11988                         /* Detect size with tg3_nvram_get_size() */
11989                         break;
11990                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11991                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11992                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11993                         break;
11994                 default:
11995                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11996                         break;
11997                 }
11998                 break;
11999         case FLASH_5717VENDOR_ST_M_M25PE10:
12000         case FLASH_5717VENDOR_ST_A_M25PE10:
12001         case FLASH_5717VENDOR_ST_M_M45PE10:
12002         case FLASH_5717VENDOR_ST_A_M45PE10:
12003         case FLASH_5717VENDOR_ST_M_M25PE20:
12004         case FLASH_5717VENDOR_ST_A_M25PE20:
12005         case FLASH_5717VENDOR_ST_M_M45PE20:
12006         case FLASH_5717VENDOR_ST_A_M45PE20:
12007         case FLASH_5717VENDOR_ST_25USPT:
12008         case FLASH_5717VENDOR_ST_45USPT:
12009                 tp->nvram_jedecnum = JEDEC_ST;
12010                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
12011                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
12012
12013                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12014                 case FLASH_5717VENDOR_ST_M_M25PE20:
12015                 case FLASH_5717VENDOR_ST_M_M45PE20:
12016                         /* Detect size with tg3_nvram_get_size() */
12017                         break;
12018                 case FLASH_5717VENDOR_ST_A_M25PE20:
12019                 case FLASH_5717VENDOR_ST_A_M45PE20:
12020                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12021                         break;
12022                 default:
12023                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12024                         break;
12025                 }
12026                 break;
12027         default:
12028                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
12029                 return;
12030         }
12031
12032         tg3_nvram_get_pagesize(tp, nvcfg1);
12033         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12034                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
12035 }
12036
12037 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12038 {
12039         u32 nvcfg1, nvmpinstrp;
12040
12041         nvcfg1 = tr32(NVRAM_CFG1);
12042         nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
12043
12044         switch (nvmpinstrp) {
12045         case FLASH_5720_EEPROM_HD:
12046         case FLASH_5720_EEPROM_LD:
12047                 tp->nvram_jedecnum = JEDEC_ATMEL;
12048                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
12049
12050                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12051                 tw32(NVRAM_CFG1, nvcfg1);
12052                 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
12053                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12054                 else
12055                         tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
12056                 return;
12057         case FLASH_5720VENDOR_M_ATMEL_DB011D:
12058         case FLASH_5720VENDOR_A_ATMEL_DB011B:
12059         case FLASH_5720VENDOR_A_ATMEL_DB011D:
12060         case FLASH_5720VENDOR_M_ATMEL_DB021D:
12061         case FLASH_5720VENDOR_A_ATMEL_DB021B:
12062         case FLASH_5720VENDOR_A_ATMEL_DB021D:
12063         case FLASH_5720VENDOR_M_ATMEL_DB041D:
12064         case FLASH_5720VENDOR_A_ATMEL_DB041B:
12065         case FLASH_5720VENDOR_A_ATMEL_DB041D:
12066         case FLASH_5720VENDOR_M_ATMEL_DB081D:
12067         case FLASH_5720VENDOR_A_ATMEL_DB081D:
12068         case FLASH_5720VENDOR_ATMEL_45USPT:
12069                 tp->nvram_jedecnum = JEDEC_ATMEL;
12070                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
12071                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
12072
12073                 switch (nvmpinstrp) {
12074                 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12075                 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12076                 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12077                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12078                         break;
12079                 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12080                 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12081                 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12082                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12083                         break;
12084                 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12085                 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12086                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12087                         break;
12088                 default:
12089                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12090                         break;
12091                 }
12092                 break;
12093         case FLASH_5720VENDOR_M_ST_M25PE10:
12094         case FLASH_5720VENDOR_M_ST_M45PE10:
12095         case FLASH_5720VENDOR_A_ST_M25PE10:
12096         case FLASH_5720VENDOR_A_ST_M45PE10:
12097         case FLASH_5720VENDOR_M_ST_M25PE20:
12098         case FLASH_5720VENDOR_M_ST_M45PE20:
12099         case FLASH_5720VENDOR_A_ST_M25PE20:
12100         case FLASH_5720VENDOR_A_ST_M45PE20:
12101         case FLASH_5720VENDOR_M_ST_M25PE40:
12102         case FLASH_5720VENDOR_M_ST_M45PE40:
12103         case FLASH_5720VENDOR_A_ST_M25PE40:
12104         case FLASH_5720VENDOR_A_ST_M45PE40:
12105         case FLASH_5720VENDOR_M_ST_M25PE80:
12106         case FLASH_5720VENDOR_M_ST_M45PE80:
12107         case FLASH_5720VENDOR_A_ST_M25PE80:
12108         case FLASH_5720VENDOR_A_ST_M45PE80:
12109         case FLASH_5720VENDOR_ST_25USPT:
12110         case FLASH_5720VENDOR_ST_45USPT:
12111                 tp->nvram_jedecnum = JEDEC_ST;
12112                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
12113                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
12114
12115                 switch (nvmpinstrp) {
12116                 case FLASH_5720VENDOR_M_ST_M25PE20:
12117                 case FLASH_5720VENDOR_M_ST_M45PE20:
12118                 case FLASH_5720VENDOR_A_ST_M25PE20:
12119                 case FLASH_5720VENDOR_A_ST_M45PE20:
12120                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12121                         break;
12122                 case FLASH_5720VENDOR_M_ST_M25PE40:
12123                 case FLASH_5720VENDOR_M_ST_M45PE40:
12124                 case FLASH_5720VENDOR_A_ST_M25PE40:
12125                 case FLASH_5720VENDOR_A_ST_M45PE40:
12126                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12127                         break;
12128                 case FLASH_5720VENDOR_M_ST_M25PE80:
12129                 case FLASH_5720VENDOR_M_ST_M45PE80:
12130                 case FLASH_5720VENDOR_A_ST_M25PE80:
12131                 case FLASH_5720VENDOR_A_ST_M45PE80:
12132                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12133                         break;
12134                 default:
12135                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12136                         break;
12137                 }
12138                 break;
12139         default:
12140                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
12141                 return;
12142         }
12143
12144         tg3_nvram_get_pagesize(tp, nvcfg1);
12145         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12146                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
12147 }
12148
12149 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12150 static void __devinit tg3_nvram_init(struct tg3 *tp)
12151 {
12152         tw32_f(GRC_EEPROM_ADDR,
12153              (EEPROM_ADDR_FSM_RESET |
12154               (EEPROM_DEFAULT_CLOCK_PERIOD <<
12155                EEPROM_ADDR_CLKPERD_SHIFT)));
12156
12157         msleep(1);
12158
12159         /* Enable seeprom accesses. */
12160         tw32_f(GRC_LOCAL_CTRL,
12161              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12162         udelay(100);
12163
12164         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12165             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12166                 tp->tg3_flags |= TG3_FLAG_NVRAM;
12167
12168                 if (tg3_nvram_lock(tp)) {
12169                         netdev_warn(tp->dev,
12170                                     "Cannot get nvram lock, %s failed\n",
12171                                     __func__);
12172                         return;
12173                 }
12174                 tg3_enable_nvram_access(tp);
12175
12176                 tp->nvram_size = 0;
12177
12178                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12179                         tg3_get_5752_nvram_info(tp);
12180                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12181                         tg3_get_5755_nvram_info(tp);
12182                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12183                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12184                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12185                         tg3_get_5787_nvram_info(tp);
12186                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12187                         tg3_get_5761_nvram_info(tp);
12188                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12189                         tg3_get_5906_nvram_info(tp);
12190                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12191                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12192                         tg3_get_57780_nvram_info(tp);
12193                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12194                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12195                         tg3_get_5717_nvram_info(tp);
12196                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12197                         tg3_get_5720_nvram_info(tp);
12198                 else
12199                         tg3_get_nvram_info(tp);
12200
12201                 if (tp->nvram_size == 0)
12202                         tg3_get_nvram_size(tp);
12203
12204                 tg3_disable_nvram_access(tp);
12205                 tg3_nvram_unlock(tp);
12206
12207         } else {
12208                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
12209
12210                 tg3_get_eeprom_size(tp);
12211         }
12212 }
12213
12214 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12215                                     u32 offset, u32 len, u8 *buf)
12216 {
12217         int i, j, rc = 0;
12218         u32 val;
12219
12220         for (i = 0; i < len; i += 4) {
12221                 u32 addr;
12222                 __be32 data;
12223
12224                 addr = offset + i;
12225
12226                 memcpy(&data, buf + i, 4);
12227
12228                 /*
12229                  * The SEEPROM interface expects the data to always be opposite
12230                  * the native endian format.  We accomplish this by reversing
12231                  * all the operations that would have been performed on the
12232                  * data from a call to tg3_nvram_read_be32().
12233                  */
12234                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
12235
12236                 val = tr32(GRC_EEPROM_ADDR);
12237                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12238
12239                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12240                         EEPROM_ADDR_READ);
12241                 tw32(GRC_EEPROM_ADDR, val |
12242                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
12243                         (addr & EEPROM_ADDR_ADDR_MASK) |
12244                         EEPROM_ADDR_START |
12245                         EEPROM_ADDR_WRITE);
12246
12247                 for (j = 0; j < 1000; j++) {
12248                         val = tr32(GRC_EEPROM_ADDR);
12249
12250                         if (val & EEPROM_ADDR_COMPLETE)
12251                                 break;
12252                         msleep(1);
12253                 }
12254                 if (!(val & EEPROM_ADDR_COMPLETE)) {
12255                         rc = -EBUSY;
12256                         break;
12257                 }
12258         }
12259
12260         return rc;
12261 }
12262
12263 /* offset and length are dword aligned */
12264 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12265                 u8 *buf)
12266 {
12267         int ret = 0;
12268         u32 pagesize = tp->nvram_pagesize;
12269         u32 pagemask = pagesize - 1;
12270         u32 nvram_cmd;
12271         u8 *tmp;
12272
12273         tmp = kmalloc(pagesize, GFP_KERNEL);
12274         if (tmp == NULL)
12275                 return -ENOMEM;
12276
12277         while (len) {
12278                 int j;
12279                 u32 phy_addr, page_off, size;
12280
12281                 phy_addr = offset & ~pagemask;
12282
12283                 for (j = 0; j < pagesize; j += 4) {
12284                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
12285                                                   (__be32 *) (tmp + j));
12286                         if (ret)
12287                                 break;
12288                 }
12289                 if (ret)
12290                         break;
12291
12292                 page_off = offset & pagemask;
12293                 size = pagesize;
12294                 if (len < size)
12295                         size = len;
12296
12297                 len -= size;
12298
12299                 memcpy(tmp + page_off, buf, size);
12300
12301                 offset = offset + (pagesize - page_off);
12302
12303                 tg3_enable_nvram_access(tp);
12304
12305                 /*
12306                  * Before we can erase the flash page, we need
12307                  * to issue a special "write enable" command.
12308                  */
12309                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12310
12311                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12312                         break;
12313
12314                 /* Erase the target page */
12315                 tw32(NVRAM_ADDR, phy_addr);
12316
12317                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12318                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12319
12320                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12321                         break;
12322
12323                 /* Issue another write enable to start the write. */
12324                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12325
12326                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12327                         break;
12328
12329                 for (j = 0; j < pagesize; j += 4) {
12330                         __be32 data;
12331
12332                         data = *((__be32 *) (tmp + j));
12333
12334                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
12335
12336                         tw32(NVRAM_ADDR, phy_addr + j);
12337
12338                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12339                                 NVRAM_CMD_WR;
12340
12341                         if (j == 0)
12342                                 nvram_cmd |= NVRAM_CMD_FIRST;
12343                         else if (j == (pagesize - 4))
12344                                 nvram_cmd |= NVRAM_CMD_LAST;
12345
12346                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12347                                 break;
12348                 }
12349                 if (ret)
12350                         break;
12351         }
12352
12353         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12354         tg3_nvram_exec_cmd(tp, nvram_cmd);
12355
12356         kfree(tmp);
12357
12358         return ret;
12359 }
12360
12361 /* offset and length are dword aligned */
12362 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12363                 u8 *buf)
12364 {
12365         int i, ret = 0;
12366
12367         for (i = 0; i < len; i += 4, offset += 4) {
12368                 u32 page_off, phy_addr, nvram_cmd;
12369                 __be32 data;
12370
12371                 memcpy(&data, buf + i, 4);
12372                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12373
12374                 page_off = offset % tp->nvram_pagesize;
12375
12376                 phy_addr = tg3_nvram_phys_addr(tp, offset);
12377
12378                 tw32(NVRAM_ADDR, phy_addr);
12379
12380                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12381
12382                 if (page_off == 0 || i == 0)
12383                         nvram_cmd |= NVRAM_CMD_FIRST;
12384                 if (page_off == (tp->nvram_pagesize - 4))
12385                         nvram_cmd |= NVRAM_CMD_LAST;
12386
12387                 if (i == (len - 4))
12388                         nvram_cmd |= NVRAM_CMD_LAST;
12389
12390                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12391                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12392                     (tp->nvram_jedecnum == JEDEC_ST) &&
12393                     (nvram_cmd & NVRAM_CMD_FIRST)) {
12394
12395                         if ((ret = tg3_nvram_exec_cmd(tp,
12396                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12397                                 NVRAM_CMD_DONE)))
12398
12399                                 break;
12400                 }
12401                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12402                         /* We always do complete word writes to eeprom. */
12403                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12404                 }
12405
12406                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12407                         break;
12408         }
12409         return ret;
12410 }
12411
12412 /* offset and length are dword aligned */
12413 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12414 {
12415         int ret;
12416
12417         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12418                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12419                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
12420                 udelay(40);
12421         }
12422
12423         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12424                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12425         } else {
12426                 u32 grc_mode;
12427
12428                 ret = tg3_nvram_lock(tp);
12429                 if (ret)
12430                         return ret;
12431
12432                 tg3_enable_nvram_access(tp);
12433                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12434                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12435                         tw32(NVRAM_WRITE1, 0x406);
12436
12437                 grc_mode = tr32(GRC_MODE);
12438                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12439
12440                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12441                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12442
12443                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12444                                 buf);
12445                 } else {
12446                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12447                                 buf);
12448                 }
12449
12450                 grc_mode = tr32(GRC_MODE);
12451                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12452
12453                 tg3_disable_nvram_access(tp);
12454                 tg3_nvram_unlock(tp);
12455         }
12456
12457         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12458                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12459                 udelay(40);
12460         }
12461
12462         return ret;
12463 }
12464
12465 struct subsys_tbl_ent {
12466         u16 subsys_vendor, subsys_devid;
12467         u32 phy_id;
12468 };
12469
12470 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12471         /* Broadcom boards. */
12472         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12473           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12474         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12475           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12476         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12477           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12478         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12479           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12480         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12481           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12482         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12483           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12484         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12485           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12486         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12487           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12488         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12489           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12490         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12491           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12492         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12493           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12494
12495         /* 3com boards. */
12496         { TG3PCI_SUBVENDOR_ID_3COM,
12497           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12498         { TG3PCI_SUBVENDOR_ID_3COM,
12499           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12500         { TG3PCI_SUBVENDOR_ID_3COM,
12501           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12502         { TG3PCI_SUBVENDOR_ID_3COM,
12503           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12504         { TG3PCI_SUBVENDOR_ID_3COM,
12505           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12506
12507         /* DELL boards. */
12508         { TG3PCI_SUBVENDOR_ID_DELL,
12509           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12510         { TG3PCI_SUBVENDOR_ID_DELL,
12511           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12512         { TG3PCI_SUBVENDOR_ID_DELL,
12513           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12514         { TG3PCI_SUBVENDOR_ID_DELL,
12515           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12516
12517         /* Compaq boards. */
12518         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12519           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12520         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12521           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12522         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12523           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12524         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12525           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12526         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12527           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12528
12529         /* IBM boards. */
12530         { TG3PCI_SUBVENDOR_ID_IBM,
12531           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12532 };
12533
12534 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12535 {
12536         int i;
12537
12538         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12539                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12540                      tp->pdev->subsystem_vendor) &&
12541                     (subsys_id_to_phy_id[i].subsys_devid ==
12542                      tp->pdev->subsystem_device))
12543                         return &subsys_id_to_phy_id[i];
12544         }
12545         return NULL;
12546 }
12547
12548 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12549 {
12550         u32 val;
12551         u16 pmcsr;
12552
12553         /* On some early chips the SRAM cannot be accessed in D3hot state,
12554          * so need make sure we're in D0.
12555          */
12556         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12557         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12558         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12559         msleep(1);
12560
12561         /* Make sure register accesses (indirect or otherwise)
12562          * will function correctly.
12563          */
12564         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12565                                tp->misc_host_ctrl);
12566
12567         /* The memory arbiter has to be enabled in order for SRAM accesses
12568          * to succeed.  Normally on powerup the tg3 chip firmware will make
12569          * sure it is enabled, but other entities such as system netboot
12570          * code might disable it.
12571          */
12572         val = tr32(MEMARB_MODE);
12573         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12574
12575         tp->phy_id = TG3_PHY_ID_INVALID;
12576         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12577
12578         /* Assume an onboard device and WOL capable by default.  */
12579         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12580
12581         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12582                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12583                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12584                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12585                 }
12586                 val = tr32(VCPU_CFGSHDW);
12587                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12588                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12589                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12590                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12591                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12592                 goto done;
12593         }
12594
12595         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12596         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12597                 u32 nic_cfg, led_cfg;
12598                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12599                 int eeprom_phy_serdes = 0;
12600
12601                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12602                 tp->nic_sram_data_cfg = nic_cfg;
12603
12604                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12605                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12606                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12607                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12608                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12609                     (ver > 0) && (ver < 0x100))
12610                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12611
12612                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12613                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12614
12615                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12616                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12617                         eeprom_phy_serdes = 1;
12618
12619                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12620                 if (nic_phy_id != 0) {
12621                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12622                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12623
12624                         eeprom_phy_id  = (id1 >> 16) << 10;
12625                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12626                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12627                 } else
12628                         eeprom_phy_id = 0;
12629
12630                 tp->phy_id = eeprom_phy_id;
12631                 if (eeprom_phy_serdes) {
12632                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12633                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12634                         else
12635                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12636                 }
12637
12638                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12639                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12640                                     SHASTA_EXT_LED_MODE_MASK);
12641                 else
12642                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12643
12644                 switch (led_cfg) {
12645                 default:
12646                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12647                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12648                         break;
12649
12650                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12651                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12652                         break;
12653
12654                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12655                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12656
12657                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12658                          * read on some older 5700/5701 bootcode.
12659                          */
12660                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12661                             ASIC_REV_5700 ||
12662                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12663                             ASIC_REV_5701)
12664                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12665
12666                         break;
12667
12668                 case SHASTA_EXT_LED_SHARED:
12669                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12670                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12671                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12672                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12673                                                  LED_CTRL_MODE_PHY_2);
12674                         break;
12675
12676                 case SHASTA_EXT_LED_MAC:
12677                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12678                         break;
12679
12680                 case SHASTA_EXT_LED_COMBO:
12681                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12682                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12683                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12684                                                  LED_CTRL_MODE_PHY_2);
12685                         break;
12686
12687                 }
12688
12689                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12690                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12691                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12692                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12693
12694                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12695                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12696
12697                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12698                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12699                         if ((tp->pdev->subsystem_vendor ==
12700                              PCI_VENDOR_ID_ARIMA) &&
12701                             (tp->pdev->subsystem_device == 0x205a ||
12702                              tp->pdev->subsystem_device == 0x2063))
12703                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12704                 } else {
12705                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12706                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12707                 }
12708
12709                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12710                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12711                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12712                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12713                 }
12714
12715                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12716                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12717                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12718
12719                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12720                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12721                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12722
12723                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12724                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12725                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12726
12727                 if (cfg2 & (1 << 17))
12728                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12729
12730                 /* serdes signal pre-emphasis in register 0x590 set by */
12731                 /* bootcode if bit 18 is set */
12732                 if (cfg2 & (1 << 18))
12733                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12734
12735                 if (((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) ||
12736                     ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12737                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
12738                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12739                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12740
12741                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12742                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12743                     !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
12744                         u32 cfg3;
12745
12746                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12747                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12748                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12749                 }
12750
12751                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12752                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12753                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12754                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12755                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12756                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12757         }
12758 done:
12759         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
12760                 device_set_wakeup_enable(&tp->pdev->dev,
12761                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12762         else
12763                 device_set_wakeup_capable(&tp->pdev->dev, false);
12764 }
12765
12766 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12767 {
12768         int i;
12769         u32 val;
12770
12771         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12772         tw32(OTP_CTRL, cmd);
12773
12774         /* Wait for up to 1 ms for command to execute. */
12775         for (i = 0; i < 100; i++) {
12776                 val = tr32(OTP_STATUS);
12777                 if (val & OTP_STATUS_CMD_DONE)
12778                         break;
12779                 udelay(10);
12780         }
12781
12782         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12783 }
12784
12785 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12786  * configuration is a 32-bit value that straddles the alignment boundary.
12787  * We do two 32-bit reads and then shift and merge the results.
12788  */
12789 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12790 {
12791         u32 bhalf_otp, thalf_otp;
12792
12793         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12794
12795         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12796                 return 0;
12797
12798         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12799
12800         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12801                 return 0;
12802
12803         thalf_otp = tr32(OTP_READ_DATA);
12804
12805         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12806
12807         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12808                 return 0;
12809
12810         bhalf_otp = tr32(OTP_READ_DATA);
12811
12812         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12813 }
12814
12815 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
12816 {
12817         u32 adv = ADVERTISED_Autoneg |
12818                   ADVERTISED_Pause;
12819
12820         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12821                 adv |= ADVERTISED_1000baseT_Half |
12822                        ADVERTISED_1000baseT_Full;
12823
12824         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12825                 adv |= ADVERTISED_100baseT_Half |
12826                        ADVERTISED_100baseT_Full |
12827                        ADVERTISED_10baseT_Half |
12828                        ADVERTISED_10baseT_Full |
12829                        ADVERTISED_TP;
12830         else
12831                 adv |= ADVERTISED_FIBRE;
12832
12833         tp->link_config.advertising = adv;
12834         tp->link_config.speed = SPEED_INVALID;
12835         tp->link_config.duplex = DUPLEX_INVALID;
12836         tp->link_config.autoneg = AUTONEG_ENABLE;
12837         tp->link_config.active_speed = SPEED_INVALID;
12838         tp->link_config.active_duplex = DUPLEX_INVALID;
12839         tp->link_config.orig_speed = SPEED_INVALID;
12840         tp->link_config.orig_duplex = DUPLEX_INVALID;
12841         tp->link_config.orig_autoneg = AUTONEG_INVALID;
12842 }
12843
12844 static int __devinit tg3_phy_probe(struct tg3 *tp)
12845 {
12846         u32 hw_phy_id_1, hw_phy_id_2;
12847         u32 hw_phy_id, hw_phy_id_masked;
12848         int err;
12849
12850         /* flow control autonegotiation is default behavior */
12851         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12852         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
12853
12854         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12855                 return tg3_phy_init(tp);
12856
12857         /* Reading the PHY ID register can conflict with ASF
12858          * firmware access to the PHY hardware.
12859          */
12860         err = 0;
12861         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12862             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12863                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12864         } else {
12865                 /* Now read the physical PHY_ID from the chip and verify
12866                  * that it is sane.  If it doesn't look good, we fall back
12867                  * to either the hard-coded table based PHY_ID and failing
12868                  * that the value found in the eeprom area.
12869                  */
12870                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12871                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12872
12873                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12874                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12875                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12876
12877                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12878         }
12879
12880         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12881                 tp->phy_id = hw_phy_id;
12882                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12883                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12884                 else
12885                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12886         } else {
12887                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12888                         /* Do nothing, phy ID already set up in
12889                          * tg3_get_eeprom_hw_cfg().
12890                          */
12891                 } else {
12892                         struct subsys_tbl_ent *p;
12893
12894                         /* No eeprom signature?  Try the hardcoded
12895                          * subsys device table.
12896                          */
12897                         p = tg3_lookup_by_subsys(tp);
12898                         if (!p)
12899                                 return -ENODEV;
12900
12901                         tp->phy_id = p->phy_id;
12902                         if (!tp->phy_id ||
12903                             tp->phy_id == TG3_PHY_ID_BCM8002)
12904                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12905                 }
12906         }
12907
12908         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12909             ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
12910               tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
12911              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12912               tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
12913                 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12914
12915         tg3_phy_init_link_config(tp);
12916
12917         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12918             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12919             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12920                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12921
12922                 tg3_readphy(tp, MII_BMSR, &bmsr);
12923                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12924                     (bmsr & BMSR_LSTATUS))
12925                         goto skip_phy_reset;
12926
12927                 err = tg3_phy_reset(tp);
12928                 if (err)
12929                         return err;
12930
12931                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12932                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12933                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12934                 tg3_ctrl = 0;
12935                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12936                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12937                                     MII_TG3_CTRL_ADV_1000_FULL);
12938                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12939                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12940                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12941                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12942                 }
12943
12944                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12945                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12946                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12947                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12948                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12949
12950                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12951                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12952
12953                         tg3_writephy(tp, MII_BMCR,
12954                                      BMCR_ANENABLE | BMCR_ANRESTART);
12955                 }
12956                 tg3_phy_set_wirespeed(tp);
12957
12958                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12959                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12960                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12961         }
12962
12963 skip_phy_reset:
12964         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12965                 err = tg3_init_5401phy_dsp(tp);
12966                 if (err)
12967                         return err;
12968
12969                 err = tg3_init_5401phy_dsp(tp);
12970         }
12971
12972         return err;
12973 }
12974
12975 static void __devinit tg3_read_vpd(struct tg3 *tp)
12976 {
12977         u8 *vpd_data;
12978         unsigned int block_end, rosize, len;
12979         int j, i = 0;
12980
12981         vpd_data = (u8 *)tg3_vpd_readblock(tp);
12982         if (!vpd_data)
12983                 goto out_no_vpd;
12984
12985         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12986                              PCI_VPD_LRDT_RO_DATA);
12987         if (i < 0)
12988                 goto out_not_found;
12989
12990         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12991         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12992         i += PCI_VPD_LRDT_TAG_SIZE;
12993
12994         if (block_end > TG3_NVM_VPD_LEN)
12995                 goto out_not_found;
12996
12997         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12998                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12999         if (j > 0) {
13000                 len = pci_vpd_info_field_size(&vpd_data[j]);
13001
13002                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13003                 if (j + len > block_end || len != 4 ||
13004                     memcmp(&vpd_data[j], "1028", 4))
13005                         goto partno;
13006
13007                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13008                                               PCI_VPD_RO_KEYWORD_VENDOR0);
13009                 if (j < 0)
13010                         goto partno;
13011
13012                 len = pci_vpd_info_field_size(&vpd_data[j]);
13013
13014                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13015                 if (j + len > block_end)
13016                         goto partno;
13017
13018                 memcpy(tp->fw_ver, &vpd_data[j], len);
13019                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
13020         }
13021
13022 partno:
13023         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13024                                       PCI_VPD_RO_KEYWORD_PARTNO);
13025         if (i < 0)
13026                 goto out_not_found;
13027
13028         len = pci_vpd_info_field_size(&vpd_data[i]);
13029
13030         i += PCI_VPD_INFO_FLD_HDR_SIZE;
13031         if (len > TG3_BPN_SIZE ||
13032             (len + i) > TG3_NVM_VPD_LEN)
13033                 goto out_not_found;
13034
13035         memcpy(tp->board_part_number, &vpd_data[i], len);
13036
13037 out_not_found:
13038         kfree(vpd_data);
13039         if (tp->board_part_number[0])
13040                 return;
13041
13042 out_no_vpd:
13043         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13044                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13045                         strcpy(tp->board_part_number, "BCM5717");
13046                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13047                         strcpy(tp->board_part_number, "BCM5718");
13048                 else
13049                         goto nomatch;
13050         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13051                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13052                         strcpy(tp->board_part_number, "BCM57780");
13053                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13054                         strcpy(tp->board_part_number, "BCM57760");
13055                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13056                         strcpy(tp->board_part_number, "BCM57790");
13057                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13058                         strcpy(tp->board_part_number, "BCM57788");
13059                 else
13060                         goto nomatch;
13061         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13062                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13063                         strcpy(tp->board_part_number, "BCM57761");
13064                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13065                         strcpy(tp->board_part_number, "BCM57765");
13066                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13067                         strcpy(tp->board_part_number, "BCM57781");
13068                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13069                         strcpy(tp->board_part_number, "BCM57785");
13070                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13071                         strcpy(tp->board_part_number, "BCM57791");
13072                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13073                         strcpy(tp->board_part_number, "BCM57795");
13074                 else
13075                         goto nomatch;
13076         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13077                 strcpy(tp->board_part_number, "BCM95906");
13078         } else {
13079 nomatch:
13080                 strcpy(tp->board_part_number, "none");
13081         }
13082 }
13083
13084 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13085 {
13086         u32 val;
13087
13088         if (tg3_nvram_read(tp, offset, &val) ||
13089             (val & 0xfc000000) != 0x0c000000 ||
13090             tg3_nvram_read(tp, offset + 4, &val) ||
13091             val != 0)
13092                 return 0;
13093
13094         return 1;
13095 }
13096
13097 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13098 {
13099         u32 val, offset, start, ver_offset;
13100         int i, dst_off;
13101         bool newver = false;
13102
13103         if (tg3_nvram_read(tp, 0xc, &offset) ||
13104             tg3_nvram_read(tp, 0x4, &start))
13105                 return;
13106
13107         offset = tg3_nvram_logical_addr(tp, offset);
13108
13109         if (tg3_nvram_read(tp, offset, &val))
13110                 return;
13111
13112         if ((val & 0xfc000000) == 0x0c000000) {
13113                 if (tg3_nvram_read(tp, offset + 4, &val))
13114                         return;
13115
13116                 if (val == 0)
13117                         newver = true;
13118         }
13119
13120         dst_off = strlen(tp->fw_ver);
13121
13122         if (newver) {
13123                 if (TG3_VER_SIZE - dst_off < 16 ||
13124                     tg3_nvram_read(tp, offset + 8, &ver_offset))
13125                         return;
13126
13127                 offset = offset + ver_offset - start;
13128                 for (i = 0; i < 16; i += 4) {
13129                         __be32 v;
13130                         if (tg3_nvram_read_be32(tp, offset + i, &v))
13131                                 return;
13132
13133                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13134                 }
13135         } else {
13136                 u32 major, minor;
13137
13138                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13139                         return;
13140
13141                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13142                         TG3_NVM_BCVER_MAJSFT;
13143                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13144                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13145                          "v%d.%02d", major, minor);
13146         }
13147 }
13148
13149 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13150 {
13151         u32 val, major, minor;
13152
13153         /* Use native endian representation */
13154         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13155                 return;
13156
13157         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13158                 TG3_NVM_HWSB_CFG1_MAJSFT;
13159         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13160                 TG3_NVM_HWSB_CFG1_MINSFT;
13161
13162         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13163 }
13164
13165 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13166 {
13167         u32 offset, major, minor, build;
13168
13169         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13170
13171         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13172                 return;
13173
13174         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13175         case TG3_EEPROM_SB_REVISION_0:
13176                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13177                 break;
13178         case TG3_EEPROM_SB_REVISION_2:
13179                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13180                 break;
13181         case TG3_EEPROM_SB_REVISION_3:
13182                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13183                 break;
13184         case TG3_EEPROM_SB_REVISION_4:
13185                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13186                 break;
13187         case TG3_EEPROM_SB_REVISION_5:
13188                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13189                 break;
13190         case TG3_EEPROM_SB_REVISION_6:
13191                 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13192                 break;
13193         default:
13194                 return;
13195         }
13196
13197         if (tg3_nvram_read(tp, offset, &val))
13198                 return;
13199
13200         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13201                 TG3_EEPROM_SB_EDH_BLD_SHFT;
13202         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13203                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13204         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
13205
13206         if (minor > 99 || build > 26)
13207                 return;
13208
13209         offset = strlen(tp->fw_ver);
13210         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13211                  " v%d.%02d", major, minor);
13212
13213         if (build > 0) {
13214                 offset = strlen(tp->fw_ver);
13215                 if (offset < TG3_VER_SIZE - 1)
13216                         tp->fw_ver[offset] = 'a' + build - 1;
13217         }
13218 }
13219
13220 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13221 {
13222         u32 val, offset, start;
13223         int i, vlen;
13224
13225         for (offset = TG3_NVM_DIR_START;
13226              offset < TG3_NVM_DIR_END;
13227              offset += TG3_NVM_DIRENT_SIZE) {
13228                 if (tg3_nvram_read(tp, offset, &val))
13229                         return;
13230
13231                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13232                         break;
13233         }
13234
13235         if (offset == TG3_NVM_DIR_END)
13236                 return;
13237
13238         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
13239                 start = 0x08000000;
13240         else if (tg3_nvram_read(tp, offset - 4, &start))
13241                 return;
13242
13243         if (tg3_nvram_read(tp, offset + 4, &offset) ||
13244             !tg3_fw_img_is_valid(tp, offset) ||
13245             tg3_nvram_read(tp, offset + 8, &val))
13246                 return;
13247
13248         offset += val - start;
13249
13250         vlen = strlen(tp->fw_ver);
13251
13252         tp->fw_ver[vlen++] = ',';
13253         tp->fw_ver[vlen++] = ' ';
13254
13255         for (i = 0; i < 4; i++) {
13256                 __be32 v;
13257                 if (tg3_nvram_read_be32(tp, offset, &v))
13258                         return;
13259
13260                 offset += sizeof(v);
13261
13262                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13263                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13264                         break;
13265                 }
13266
13267                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13268                 vlen += sizeof(v);
13269         }
13270 }
13271
13272 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13273 {
13274         int vlen;
13275         u32 apedata;
13276         char *fwtype;
13277
13278         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
13279             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
13280                 return;
13281
13282         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13283         if (apedata != APE_SEG_SIG_MAGIC)
13284                 return;
13285
13286         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13287         if (!(apedata & APE_FW_STATUS_READY))
13288                 return;
13289
13290         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13291
13292         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13293                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
13294                 fwtype = "NCSI";
13295         } else {
13296                 fwtype = "DASH";
13297         }
13298
13299         vlen = strlen(tp->fw_ver);
13300
13301         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13302                  fwtype,
13303                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13304                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13305                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13306                  (apedata & APE_FW_VERSION_BLDMSK));
13307 }
13308
13309 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13310 {
13311         u32 val;
13312         bool vpd_vers = false;
13313
13314         if (tp->fw_ver[0] != 0)
13315                 vpd_vers = true;
13316
13317         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
13318                 strcat(tp->fw_ver, "sb");
13319                 return;
13320         }
13321
13322         if (tg3_nvram_read(tp, 0, &val))
13323                 return;
13324
13325         if (val == TG3_EEPROM_MAGIC)
13326                 tg3_read_bc_ver(tp);
13327         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13328                 tg3_read_sb_ver(tp, val);
13329         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13330                 tg3_read_hwsb_ver(tp);
13331         else
13332                 return;
13333
13334         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13335              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13336                 goto done;
13337
13338         tg3_read_mgmtfw_ver(tp);
13339
13340 done:
13341         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13342 }
13343
13344 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13345
13346 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13347 {
13348         if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
13349                 return TG3_RX_RET_MAX_SIZE_5717;
13350         else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13351                  !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13352                 return TG3_RX_RET_MAX_SIZE_5700;
13353         else
13354                 return TG3_RX_RET_MAX_SIZE_5705;
13355 }
13356
13357 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13358         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13359         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13360         { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13361         { },
13362 };
13363
13364 static int __devinit tg3_get_invariants(struct tg3 *tp)
13365 {
13366         u32 misc_ctrl_reg;
13367         u32 pci_state_reg, grc_misc_cfg;
13368         u32 val;
13369         u16 pci_cmd;
13370         int err;
13371
13372         /* Force memory write invalidate off.  If we leave it on,
13373          * then on 5700_BX chips we have to enable a workaround.
13374          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13375          * to match the cacheline size.  The Broadcom driver have this
13376          * workaround but turns MWI off all the times so never uses
13377          * it.  This seems to suggest that the workaround is insufficient.
13378          */
13379         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13380         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13381         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13382
13383         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13384          * has the register indirect write enable bit set before
13385          * we try to access any of the MMIO registers.  It is also
13386          * critical that the PCI-X hw workaround situation is decided
13387          * before that as well.
13388          */
13389         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13390                               &misc_ctrl_reg);
13391
13392         tp->pci_chip_rev_id = (misc_ctrl_reg >>
13393                                MISC_HOST_CTRL_CHIPREV_SHIFT);
13394         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13395                 u32 prod_id_asic_rev;
13396
13397                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13398                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13399                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13400                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13401                         pci_read_config_dword(tp->pdev,
13402                                               TG3PCI_GEN2_PRODID_ASICREV,
13403                                               &prod_id_asic_rev);
13404                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13405                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13406                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13407                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13408                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13409                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13410                         pci_read_config_dword(tp->pdev,
13411                                               TG3PCI_GEN15_PRODID_ASICREV,
13412                                               &prod_id_asic_rev);
13413                 else
13414                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13415                                               &prod_id_asic_rev);
13416
13417                 tp->pci_chip_rev_id = prod_id_asic_rev;
13418         }
13419
13420         /* Wrong chip ID in 5752 A0. This code can be removed later
13421          * as A0 is not in production.
13422          */
13423         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13424                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13425
13426         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13427          * we need to disable memory and use config. cycles
13428          * only to access all registers. The 5702/03 chips
13429          * can mistakenly decode the special cycles from the
13430          * ICH chipsets as memory write cycles, causing corruption
13431          * of register and memory space. Only certain ICH bridges
13432          * will drive special cycles with non-zero data during the
13433          * address phase which can fall within the 5703's address
13434          * range. This is not an ICH bug as the PCI spec allows
13435          * non-zero address during special cycles. However, only
13436          * these ICH bridges are known to drive non-zero addresses
13437          * during special cycles.
13438          *
13439          * Since special cycles do not cross PCI bridges, we only
13440          * enable this workaround if the 5703 is on the secondary
13441          * bus of these ICH bridges.
13442          */
13443         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13444             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13445                 static struct tg3_dev_id {
13446                         u32     vendor;
13447                         u32     device;
13448                         u32     rev;
13449                 } ich_chipsets[] = {
13450                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13451                           PCI_ANY_ID },
13452                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13453                           PCI_ANY_ID },
13454                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13455                           0xa },
13456                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13457                           PCI_ANY_ID },
13458                         { },
13459                 };
13460                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13461                 struct pci_dev *bridge = NULL;
13462
13463                 while (pci_id->vendor != 0) {
13464                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
13465                                                 bridge);
13466                         if (!bridge) {
13467                                 pci_id++;
13468                                 continue;
13469                         }
13470                         if (pci_id->rev != PCI_ANY_ID) {
13471                                 if (bridge->revision > pci_id->rev)
13472                                         continue;
13473                         }
13474                         if (bridge->subordinate &&
13475                             (bridge->subordinate->number ==
13476                              tp->pdev->bus->number)) {
13477
13478                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13479                                 pci_dev_put(bridge);
13480                                 break;
13481                         }
13482                 }
13483         }
13484
13485         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13486                 static struct tg3_dev_id {
13487                         u32     vendor;
13488                         u32     device;
13489                 } bridge_chipsets[] = {
13490                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13491                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13492                         { },
13493                 };
13494                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13495                 struct pci_dev *bridge = NULL;
13496
13497                 while (pci_id->vendor != 0) {
13498                         bridge = pci_get_device(pci_id->vendor,
13499                                                 pci_id->device,
13500                                                 bridge);
13501                         if (!bridge) {
13502                                 pci_id++;
13503                                 continue;
13504                         }
13505                         if (bridge->subordinate &&
13506                             (bridge->subordinate->number <=
13507                              tp->pdev->bus->number) &&
13508                             (bridge->subordinate->subordinate >=
13509                              tp->pdev->bus->number)) {
13510                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13511                                 pci_dev_put(bridge);
13512                                 break;
13513                         }
13514                 }
13515         }
13516
13517         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13518          * DMA addresses > 40-bit. This bridge may have other additional
13519          * 57xx devices behind it in some 4-port NIC designs for example.
13520          * Any tg3 device found behind the bridge will also need the 40-bit
13521          * DMA workaround.
13522          */
13523         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13524             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13525                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13526                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13527                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13528         } else {
13529                 struct pci_dev *bridge = NULL;
13530
13531                 do {
13532                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13533                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13534                                                 bridge);
13535                         if (bridge && bridge->subordinate &&
13536                             (bridge->subordinate->number <=
13537                              tp->pdev->bus->number) &&
13538                             (bridge->subordinate->subordinate >=
13539                              tp->pdev->bus->number)) {
13540                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13541                                 pci_dev_put(bridge);
13542                                 break;
13543                         }
13544                 } while (bridge);
13545         }
13546
13547         /* Initialize misc host control in PCI block. */
13548         tp->misc_host_ctrl |= (misc_ctrl_reg &
13549                                MISC_HOST_CTRL_CHIPREV);
13550         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13551                                tp->misc_host_ctrl);
13552
13553         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13554             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13555             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13556             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13557                 tp->pdev_peer = tg3_find_peer(tp);
13558
13559         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13560             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13561             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13562                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13563
13564         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13565             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13566                 tp->tg3_flags3 |= TG3_FLG3_57765_PLUS;
13567
13568         /* Intentionally exclude ASIC_REV_5906 */
13569         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13570             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13571             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13572             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13573             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13574             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13575             (tp->tg3_flags3 & TG3_FLG3_57765_PLUS))
13576                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13577
13578         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13579             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13580             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13581             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13582             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13583                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13584
13585         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13586             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13587                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13588
13589         /* 5700 B0 chips do not support checksumming correctly due
13590          * to hardware bugs.
13591          */
13592         if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
13593                 u32 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
13594
13595                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13596                         features |= NETIF_F_IPV6_CSUM;
13597                 tp->dev->features |= features;
13598                 tp->dev->hw_features |= features;
13599                 tp->dev->vlan_features |= features;
13600         }
13601
13602         /* Determine TSO capabilities */
13603         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13604                 ; /* Do nothing. HW bug. */
13605         else if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
13606                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13607         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13608                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13609                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13610         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13611                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13612                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13613                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13614                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13615         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13616                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13617                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13618                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13619                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13620                         tp->fw_needed = FIRMWARE_TG3TSO5;
13621                 else
13622                         tp->fw_needed = FIRMWARE_TG3TSO;
13623         }
13624
13625         tp->irq_max = 1;
13626
13627         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13628                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13629                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13630                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13631                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13632                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13633                      tp->pdev_peer == tp->pdev))
13634                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13635
13636                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13637                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13638                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13639                 }
13640
13641                 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
13642                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13643                         tp->irq_max = TG3_IRQ_MAX_VECS;
13644                 }
13645         }
13646
13647         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13648             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13649             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13650                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13651         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13652                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13653                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13654         }
13655
13656         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13657                 tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP;
13658
13659         if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
13660             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
13661                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13662
13663         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13664             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13665             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13666                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13667
13668         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13669                               &pci_state_reg);
13670
13671         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13672         if (tp->pcie_cap != 0) {
13673                 u16 lnkctl;
13674
13675                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13676
13677                 tp->pcie_readrq = 4096;
13678                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13679                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13680                         tp->pcie_readrq = 2048;
13681
13682                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13683
13684                 pci_read_config_word(tp->pdev,
13685                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13686                                      &lnkctl);
13687                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13688                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13689                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13690                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13691                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13692                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13693                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13694                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13695                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13696                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13697                 }
13698         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13699                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13700         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13701                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13702                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13703                 if (!tp->pcix_cap) {
13704                         dev_err(&tp->pdev->dev,
13705                                 "Cannot find PCI-X capability, aborting\n");
13706                         return -EIO;
13707                 }
13708
13709                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13710                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13711         }
13712
13713         /* If we have an AMD 762 or VIA K8T800 chipset, write
13714          * reordering to the mailbox registers done by the host
13715          * controller can cause major troubles.  We read back from
13716          * every mailbox register write to force the writes to be
13717          * posted to the chip in order.
13718          */
13719         if (pci_dev_present(tg3_write_reorder_chipsets) &&
13720             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13721                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13722
13723         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13724                              &tp->pci_cacheline_sz);
13725         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13726                              &tp->pci_lat_timer);
13727         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13728             tp->pci_lat_timer < 64) {
13729                 tp->pci_lat_timer = 64;
13730                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13731                                       tp->pci_lat_timer);
13732         }
13733
13734         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13735                 /* 5700 BX chips need to have their TX producer index
13736                  * mailboxes written twice to workaround a bug.
13737                  */
13738                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13739
13740                 /* If we are in PCI-X mode, enable register write workaround.
13741                  *
13742                  * The workaround is to use indirect register accesses
13743                  * for all chip writes not to mailbox registers.
13744                  */
13745                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13746                         u32 pm_reg;
13747
13748                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13749
13750                         /* The chip can have it's power management PCI config
13751                          * space registers clobbered due to this bug.
13752                          * So explicitly force the chip into D0 here.
13753                          */
13754                         pci_read_config_dword(tp->pdev,
13755                                               tp->pm_cap + PCI_PM_CTRL,
13756                                               &pm_reg);
13757                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13758                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13759                         pci_write_config_dword(tp->pdev,
13760                                                tp->pm_cap + PCI_PM_CTRL,
13761                                                pm_reg);
13762
13763                         /* Also, force SERR#/PERR# in PCI command. */
13764                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13765                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13766                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13767                 }
13768         }
13769
13770         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13771                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13772         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13773                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13774
13775         /* Chip-specific fixup from Broadcom driver */
13776         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13777             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13778                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13779                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13780         }
13781
13782         /* Default fast path register access methods */
13783         tp->read32 = tg3_read32;
13784         tp->write32 = tg3_write32;
13785         tp->read32_mbox = tg3_read32;
13786         tp->write32_mbox = tg3_write32;
13787         tp->write32_tx_mbox = tg3_write32;
13788         tp->write32_rx_mbox = tg3_write32;
13789
13790         /* Various workaround register access methods */
13791         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13792                 tp->write32 = tg3_write_indirect_reg32;
13793         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13794                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13795                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13796                 /*
13797                  * Back to back register writes can cause problems on these
13798                  * chips, the workaround is to read back all reg writes
13799                  * except those to mailbox regs.
13800                  *
13801                  * See tg3_write_indirect_reg32().
13802                  */
13803                 tp->write32 = tg3_write_flush_reg32;
13804         }
13805
13806         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13807             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13808                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13809                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13810                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13811         }
13812
13813         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13814                 tp->read32 = tg3_read_indirect_reg32;
13815                 tp->write32 = tg3_write_indirect_reg32;
13816                 tp->read32_mbox = tg3_read_indirect_mbox;
13817                 tp->write32_mbox = tg3_write_indirect_mbox;
13818                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13819                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13820
13821                 iounmap(tp->regs);
13822                 tp->regs = NULL;
13823
13824                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13825                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13826                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13827         }
13828         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13829                 tp->read32_mbox = tg3_read32_mbox_5906;
13830                 tp->write32_mbox = tg3_write32_mbox_5906;
13831                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13832                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13833         }
13834
13835         if (tp->write32 == tg3_write_indirect_reg32 ||
13836             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13837              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13838               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13839                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13840
13841         /* Get eeprom hw config before calling tg3_set_power_state().
13842          * In particular, the TG3_FLG2_IS_NIC flag must be
13843          * determined before calling tg3_set_power_state() so that
13844          * we know whether or not to switch out of Vaux power.
13845          * When the flag is set, it means that GPIO1 is used for eeprom
13846          * write protect and also implies that it is a LOM where GPIOs
13847          * are not used to switch power.
13848          */
13849         tg3_get_eeprom_hw_cfg(tp);
13850
13851         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13852                 /* Allow reads and writes to the
13853                  * APE register and memory space.
13854                  */
13855                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13856                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13857                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13858                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13859                                        pci_state_reg);
13860         }
13861
13862         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13863             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13864             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13865             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13866             (tp->tg3_flags3 & TG3_FLG3_57765_PLUS))
13867                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13868
13869         /* Set up tp->grc_local_ctrl before calling tg_power_up().
13870          * GPIO1 driven high will bring 5700's external PHY out of reset.
13871          * It is also used as eeprom write protect on LOMs.
13872          */
13873         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13874         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13875             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13876                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13877                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13878         /* Unused GPIO3 must be driven as output on 5752 because there
13879          * are no pull-up resistors on unused GPIO pins.
13880          */
13881         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13882                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13883
13884         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13885             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13886             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13887                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13888
13889         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13890             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13891                 /* Turn off the debug UART. */
13892                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13893                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13894                         /* Keep VMain power. */
13895                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13896                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13897         }
13898
13899         /* Force the chip into D0. */
13900         err = tg3_power_up(tp);
13901         if (err) {
13902                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13903                 return err;
13904         }
13905
13906         /* Derive initial jumbo mode from MTU assigned in
13907          * ether_setup() via the alloc_etherdev() call
13908          */
13909         if (tp->dev->mtu > ETH_DATA_LEN &&
13910             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13911                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13912
13913         /* Determine WakeOnLan speed to use. */
13914         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13915             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13916             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13917             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13918                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13919         } else {
13920                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13921         }
13922
13923         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13924                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13925
13926         /* A few boards don't want Ethernet@WireSpeed phy feature */
13927         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13928             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13929              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13930              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13931             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13932             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13933                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13934
13935         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13936             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13937                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13938         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13939                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13940
13941         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13942             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13943             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13944             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13945             !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
13946                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13947                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13948                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13949                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13950                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13951                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13952                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13953                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13954                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13955                 } else
13956                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13957         }
13958
13959         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13960             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13961                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13962                 if (tp->phy_otp == 0)
13963                         tp->phy_otp = TG3_OTP_DEFAULT;
13964         }
13965
13966         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13967                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13968         else
13969                 tp->mi_mode = MAC_MI_MODE_BASE;
13970
13971         tp->coalesce_mode = 0;
13972         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13973             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13974                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13975
13976         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13977             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13978                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13979
13980         err = tg3_mdio_init(tp);
13981         if (err)
13982                 return err;
13983
13984         /* Initialize data/descriptor byte/word swapping. */
13985         val = tr32(GRC_MODE);
13986         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13987                 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
13988                         GRC_MODE_WORD_SWAP_B2HRX_DATA |
13989                         GRC_MODE_B2HRX_ENABLE |
13990                         GRC_MODE_HTX2B_ENABLE |
13991                         GRC_MODE_HOST_STACKUP);
13992         else
13993                 val &= GRC_MODE_HOST_STACKUP;
13994
13995         tw32(GRC_MODE, val | tp->grc_mode);
13996
13997         tg3_switch_clocks(tp);
13998
13999         /* Clear this out for sanity. */
14000         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14001
14002         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14003                               &pci_state_reg);
14004         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14005             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
14006                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14007
14008                 if (chiprevid == CHIPREV_ID_5701_A0 ||
14009                     chiprevid == CHIPREV_ID_5701_B0 ||
14010                     chiprevid == CHIPREV_ID_5701_B2 ||
14011                     chiprevid == CHIPREV_ID_5701_B5) {
14012                         void __iomem *sram_base;
14013
14014                         /* Write some dummy words into the SRAM status block
14015                          * area, see if it reads back correctly.  If the return
14016                          * value is bad, force enable the PCIX workaround.
14017                          */
14018                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14019
14020                         writel(0x00000000, sram_base);
14021                         writel(0x00000000, sram_base + 4);
14022                         writel(0xffffffff, sram_base + 4);
14023                         if (readl(sram_base) != 0x00000000)
14024                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
14025                 }
14026         }
14027
14028         udelay(50);
14029         tg3_nvram_init(tp);
14030
14031         grc_misc_cfg = tr32(GRC_MISC_CFG);
14032         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14033
14034         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14035             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14036              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14037                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
14038
14039         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
14040             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
14041                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
14042         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
14043                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14044                                       HOSTCC_MODE_CLRTICK_TXBD);
14045
14046                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14047                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14048                                        tp->misc_host_ctrl);
14049         }
14050
14051         /* Preserve the APE MAC_MODE bits */
14052         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
14053                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14054         else
14055                 tp->mac_mode = TG3_DEF_MAC_MODE;
14056
14057         /* these are limited to 10/100 only */
14058         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14059              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14060             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14061              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14062              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14063               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14064               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14065             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14066              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
14067               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14068               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
14069             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
14070             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14071             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14072             (tp->phy_flags & TG3_PHYFLG_IS_FET))
14073                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
14074
14075         err = tg3_phy_probe(tp);
14076         if (err) {
14077                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
14078                 /* ... but do not return immediately ... */
14079                 tg3_mdio_fini(tp);
14080         }
14081
14082         tg3_read_vpd(tp);
14083         tg3_read_fw_ver(tp);
14084
14085         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14086                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14087         } else {
14088                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14089                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14090                 else
14091                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14092         }
14093
14094         /* 5700 {AX,BX} chips have a broken status block link
14095          * change bit implementation, so we must use the
14096          * status register in those cases.
14097          */
14098         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14099                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
14100         else
14101                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
14102
14103         /* The led_ctrl is set during tg3_phy_probe, here we might
14104          * have to force the link status polling mechanism based
14105          * upon subsystem IDs.
14106          */
14107         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14108             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14109             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14110                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14111                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
14112         }
14113
14114         /* For all SERDES we poll the MAC status register. */
14115         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14116                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
14117         else
14118                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
14119
14120         tp->rx_offset = NET_IP_ALIGN;
14121         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14122         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14123             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
14124                 tp->rx_offset = 0;
14125 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14126                 tp->rx_copy_thresh = ~(u16)0;
14127 #endif
14128         }
14129
14130         tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14131         tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14132         tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14133
14134         tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14135
14136         /* Increment the rx prod index on the rx std ring by at most
14137          * 8 for these chips to workaround hw errata.
14138          */
14139         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14140             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14141             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14142                 tp->rx_std_max_post = 8;
14143
14144         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
14145                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14146                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
14147
14148         return err;
14149 }
14150
14151 #ifdef CONFIG_SPARC
14152 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14153 {
14154         struct net_device *dev = tp->dev;
14155         struct pci_dev *pdev = tp->pdev;
14156         struct device_node *dp = pci_device_to_OF_node(pdev);
14157         const unsigned char *addr;
14158         int len;
14159
14160         addr = of_get_property(dp, "local-mac-address", &len);
14161         if (addr && len == 6) {
14162                 memcpy(dev->dev_addr, addr, 6);
14163                 memcpy(dev->perm_addr, dev->dev_addr, 6);
14164                 return 0;
14165         }
14166         return -ENODEV;
14167 }
14168
14169 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14170 {
14171         struct net_device *dev = tp->dev;
14172
14173         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14174         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14175         return 0;
14176 }
14177 #endif
14178
14179 static int __devinit tg3_get_device_address(struct tg3 *tp)
14180 {
14181         struct net_device *dev = tp->dev;
14182         u32 hi, lo, mac_offset;
14183         int addr_ok = 0;
14184
14185 #ifdef CONFIG_SPARC
14186         if (!tg3_get_macaddr_sparc(tp))
14187                 return 0;
14188 #endif
14189
14190         mac_offset = 0x7c;
14191         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
14192             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
14193                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14194                         mac_offset = 0xcc;
14195                 if (tg3_nvram_lock(tp))
14196                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14197                 else
14198                         tg3_nvram_unlock(tp);
14199         } else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14200                 if (PCI_FUNC(tp->pdev->devfn) & 1)
14201                         mac_offset = 0xcc;
14202                 if (PCI_FUNC(tp->pdev->devfn) > 1)
14203                         mac_offset += 0x18c;
14204         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14205                 mac_offset = 0x10;
14206
14207         /* First try to get it from MAC address mailbox. */
14208         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14209         if ((hi >> 16) == 0x484b) {
14210                 dev->dev_addr[0] = (hi >>  8) & 0xff;
14211                 dev->dev_addr[1] = (hi >>  0) & 0xff;
14212
14213                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14214                 dev->dev_addr[2] = (lo >> 24) & 0xff;
14215                 dev->dev_addr[3] = (lo >> 16) & 0xff;
14216                 dev->dev_addr[4] = (lo >>  8) & 0xff;
14217                 dev->dev_addr[5] = (lo >>  0) & 0xff;
14218
14219                 /* Some old bootcode may report a 0 MAC address in SRAM */
14220                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14221         }
14222         if (!addr_ok) {
14223                 /* Next, try NVRAM. */
14224                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
14225                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14226                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14227                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14228                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14229                 }
14230                 /* Finally just fetch it out of the MAC control regs. */
14231                 else {
14232                         hi = tr32(MAC_ADDR_0_HIGH);
14233                         lo = tr32(MAC_ADDR_0_LOW);
14234
14235                         dev->dev_addr[5] = lo & 0xff;
14236                         dev->dev_addr[4] = (lo >> 8) & 0xff;
14237                         dev->dev_addr[3] = (lo >> 16) & 0xff;
14238                         dev->dev_addr[2] = (lo >> 24) & 0xff;
14239                         dev->dev_addr[1] = hi & 0xff;
14240                         dev->dev_addr[0] = (hi >> 8) & 0xff;
14241                 }
14242         }
14243
14244         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14245 #ifdef CONFIG_SPARC
14246                 if (!tg3_get_default_macaddr_sparc(tp))
14247                         return 0;
14248 #endif
14249                 return -EINVAL;
14250         }
14251         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14252         return 0;
14253 }
14254
14255 #define BOUNDARY_SINGLE_CACHELINE       1
14256 #define BOUNDARY_MULTI_CACHELINE        2
14257
14258 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14259 {
14260         int cacheline_size;
14261         u8 byte;
14262         int goal;
14263
14264         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14265         if (byte == 0)
14266                 cacheline_size = 1024;
14267         else
14268                 cacheline_size = (int) byte * 4;
14269
14270         /* On 5703 and later chips, the boundary bits have no
14271          * effect.
14272          */
14273         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14274             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14275             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
14276                 goto out;
14277
14278 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14279         goal = BOUNDARY_MULTI_CACHELINE;
14280 #else
14281 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14282         goal = BOUNDARY_SINGLE_CACHELINE;
14283 #else
14284         goal = 0;
14285 #endif
14286 #endif
14287
14288         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
14289                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14290                 goto out;
14291         }
14292
14293         if (!goal)
14294                 goto out;
14295
14296         /* PCI controllers on most RISC systems tend to disconnect
14297          * when a device tries to burst across a cache-line boundary.
14298          * Therefore, letting tg3 do so just wastes PCI bandwidth.
14299          *
14300          * Unfortunately, for PCI-E there are only limited
14301          * write-side controls for this, and thus for reads
14302          * we will still get the disconnects.  We'll also waste
14303          * these PCI cycles for both read and write for chips
14304          * other than 5700 and 5701 which do not implement the
14305          * boundary bits.
14306          */
14307         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
14308             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
14309                 switch (cacheline_size) {
14310                 case 16:
14311                 case 32:
14312                 case 64:
14313                 case 128:
14314                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14315                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14316                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14317                         } else {
14318                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14319                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14320                         }
14321                         break;
14322
14323                 case 256:
14324                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14325                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14326                         break;
14327
14328                 default:
14329                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14330                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14331                         break;
14332                 }
14333         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14334                 switch (cacheline_size) {
14335                 case 16:
14336                 case 32:
14337                 case 64:
14338                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14339                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14340                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14341                                 break;
14342                         }
14343                         /* fallthrough */
14344                 case 128:
14345                 default:
14346                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14347                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14348                         break;
14349                 }
14350         } else {
14351                 switch (cacheline_size) {
14352                 case 16:
14353                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14354                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14355                                         DMA_RWCTRL_WRITE_BNDRY_16);
14356                                 break;
14357                         }
14358                         /* fallthrough */
14359                 case 32:
14360                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14361                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14362                                         DMA_RWCTRL_WRITE_BNDRY_32);
14363                                 break;
14364                         }
14365                         /* fallthrough */
14366                 case 64:
14367                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14368                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14369                                         DMA_RWCTRL_WRITE_BNDRY_64);
14370                                 break;
14371                         }
14372                         /* fallthrough */
14373                 case 128:
14374                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14375                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14376                                         DMA_RWCTRL_WRITE_BNDRY_128);
14377                                 break;
14378                         }
14379                         /* fallthrough */
14380                 case 256:
14381                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
14382                                 DMA_RWCTRL_WRITE_BNDRY_256);
14383                         break;
14384                 case 512:
14385                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
14386                                 DMA_RWCTRL_WRITE_BNDRY_512);
14387                         break;
14388                 case 1024:
14389                 default:
14390                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14391                                 DMA_RWCTRL_WRITE_BNDRY_1024);
14392                         break;
14393                 }
14394         }
14395
14396 out:
14397         return val;
14398 }
14399
14400 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14401 {
14402         struct tg3_internal_buffer_desc test_desc;
14403         u32 sram_dma_descs;
14404         int i, ret;
14405
14406         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14407
14408         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14409         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14410         tw32(RDMAC_STATUS, 0);
14411         tw32(WDMAC_STATUS, 0);
14412
14413         tw32(BUFMGR_MODE, 0);
14414         tw32(FTQ_RESET, 0);
14415
14416         test_desc.addr_hi = ((u64) buf_dma) >> 32;
14417         test_desc.addr_lo = buf_dma & 0xffffffff;
14418         test_desc.nic_mbuf = 0x00002100;
14419         test_desc.len = size;
14420
14421         /*
14422          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14423          * the *second* time the tg3 driver was getting loaded after an
14424          * initial scan.
14425          *
14426          * Broadcom tells me:
14427          *   ...the DMA engine is connected to the GRC block and a DMA
14428          *   reset may affect the GRC block in some unpredictable way...
14429          *   The behavior of resets to individual blocks has not been tested.
14430          *
14431          * Broadcom noted the GRC reset will also reset all sub-components.
14432          */
14433         if (to_device) {
14434                 test_desc.cqid_sqid = (13 << 8) | 2;
14435
14436                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14437                 udelay(40);
14438         } else {
14439                 test_desc.cqid_sqid = (16 << 8) | 7;
14440
14441                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14442                 udelay(40);
14443         }
14444         test_desc.flags = 0x00000005;
14445
14446         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14447                 u32 val;
14448
14449                 val = *(((u32 *)&test_desc) + i);
14450                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14451                                        sram_dma_descs + (i * sizeof(u32)));
14452                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14453         }
14454         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14455
14456         if (to_device)
14457                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14458         else
14459                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14460
14461         ret = -ENODEV;
14462         for (i = 0; i < 40; i++) {
14463                 u32 val;
14464
14465                 if (to_device)
14466                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14467                 else
14468                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14469                 if ((val & 0xffff) == sram_dma_descs) {
14470                         ret = 0;
14471                         break;
14472                 }
14473
14474                 udelay(100);
14475         }
14476
14477         return ret;
14478 }
14479
14480 #define TEST_BUFFER_SIZE        0x2000
14481
14482 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
14483         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14484         { },
14485 };
14486
14487 static int __devinit tg3_test_dma(struct tg3 *tp)
14488 {
14489         dma_addr_t buf_dma;
14490         u32 *buf, saved_dma_rwctrl;
14491         int ret = 0;
14492
14493         buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14494                                  &buf_dma, GFP_KERNEL);
14495         if (!buf) {
14496                 ret = -ENOMEM;
14497                 goto out_nofree;
14498         }
14499
14500         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14501                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14502
14503         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14504
14505         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
14506                 goto out;
14507
14508         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14509                 /* DMA read watermark not used on PCIE */
14510                 tp->dma_rwctrl |= 0x00180000;
14511         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14512                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14513                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14514                         tp->dma_rwctrl |= 0x003f0000;
14515                 else
14516                         tp->dma_rwctrl |= 0x003f000f;
14517         } else {
14518                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14519                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14520                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14521                         u32 read_water = 0x7;
14522
14523                         /* If the 5704 is behind the EPB bridge, we can
14524                          * do the less restrictive ONE_DMA workaround for
14525                          * better performance.
14526                          */
14527                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14528                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14529                                 tp->dma_rwctrl |= 0x8000;
14530                         else if (ccval == 0x6 || ccval == 0x7)
14531                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14532
14533                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14534                                 read_water = 4;
14535                         /* Set bit 23 to enable PCIX hw bug fix */
14536                         tp->dma_rwctrl |=
14537                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14538                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14539                                 (1 << 23);
14540                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14541                         /* 5780 always in PCIX mode */
14542                         tp->dma_rwctrl |= 0x00144000;
14543                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14544                         /* 5714 always in PCIX mode */
14545                         tp->dma_rwctrl |= 0x00148000;
14546                 } else {
14547                         tp->dma_rwctrl |= 0x001b000f;
14548                 }
14549         }
14550
14551         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14552             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14553                 tp->dma_rwctrl &= 0xfffffff0;
14554
14555         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14556             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14557                 /* Remove this if it causes problems for some boards. */
14558                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14559
14560                 /* On 5700/5701 chips, we need to set this bit.
14561                  * Otherwise the chip will issue cacheline transactions
14562                  * to streamable DMA memory with not all the byte
14563                  * enables turned on.  This is an error on several
14564                  * RISC PCI controllers, in particular sparc64.
14565                  *
14566                  * On 5703/5704 chips, this bit has been reassigned
14567                  * a different meaning.  In particular, it is used
14568                  * on those chips to enable a PCI-X workaround.
14569                  */
14570                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14571         }
14572
14573         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14574
14575 #if 0
14576         /* Unneeded, already done by tg3_get_invariants.  */
14577         tg3_switch_clocks(tp);
14578 #endif
14579
14580         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14581             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14582                 goto out;
14583
14584         /* It is best to perform DMA test with maximum write burst size
14585          * to expose the 5700/5701 write DMA bug.
14586          */
14587         saved_dma_rwctrl = tp->dma_rwctrl;
14588         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14589         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14590
14591         while (1) {
14592                 u32 *p = buf, i;
14593
14594                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14595                         p[i] = i;
14596
14597                 /* Send the buffer to the chip. */
14598                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14599                 if (ret) {
14600                         dev_err(&tp->pdev->dev,
14601                                 "%s: Buffer write failed. err = %d\n",
14602                                 __func__, ret);
14603                         break;
14604                 }
14605
14606 #if 0
14607                 /* validate data reached card RAM correctly. */
14608                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14609                         u32 val;
14610                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14611                         if (le32_to_cpu(val) != p[i]) {
14612                                 dev_err(&tp->pdev->dev,
14613                                         "%s: Buffer corrupted on device! "
14614                                         "(%d != %d)\n", __func__, val, i);
14615                                 /* ret = -ENODEV here? */
14616                         }
14617                         p[i] = 0;
14618                 }
14619 #endif
14620                 /* Now read it back. */
14621                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14622                 if (ret) {
14623                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14624                                 "err = %d\n", __func__, ret);
14625                         break;
14626                 }
14627
14628                 /* Verify it. */
14629                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14630                         if (p[i] == i)
14631                                 continue;
14632
14633                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14634                             DMA_RWCTRL_WRITE_BNDRY_16) {
14635                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14636                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14637                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14638                                 break;
14639                         } else {
14640                                 dev_err(&tp->pdev->dev,
14641                                         "%s: Buffer corrupted on read back! "
14642                                         "(%d != %d)\n", __func__, p[i], i);
14643                                 ret = -ENODEV;
14644                                 goto out;
14645                         }
14646                 }
14647
14648                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14649                         /* Success. */
14650                         ret = 0;
14651                         break;
14652                 }
14653         }
14654         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14655             DMA_RWCTRL_WRITE_BNDRY_16) {
14656
14657                 /* DMA test passed without adjusting DMA boundary,
14658                  * now look for chipsets that are known to expose the
14659                  * DMA bug without failing the test.
14660                  */
14661                 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
14662                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14663                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14664                 } else {
14665                         /* Safe to use the calculated DMA boundary. */
14666                         tp->dma_rwctrl = saved_dma_rwctrl;
14667                 }
14668
14669                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14670         }
14671
14672 out:
14673         dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
14674 out_nofree:
14675         return ret;
14676 }
14677
14678 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14679 {
14680         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
14681                 tp->bufmgr_config.mbuf_read_dma_low_water =
14682                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14683                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14684                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14685                 tp->bufmgr_config.mbuf_high_water =
14686                         DEFAULT_MB_HIGH_WATER_57765;
14687
14688                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14689                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14690                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14691                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14692                 tp->bufmgr_config.mbuf_high_water_jumbo =
14693                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14694         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14695                 tp->bufmgr_config.mbuf_read_dma_low_water =
14696                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14697                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14698                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14699                 tp->bufmgr_config.mbuf_high_water =
14700                         DEFAULT_MB_HIGH_WATER_5705;
14701                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14702                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14703                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14704                         tp->bufmgr_config.mbuf_high_water =
14705                                 DEFAULT_MB_HIGH_WATER_5906;
14706                 }
14707
14708                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14709                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14710                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14711                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14712                 tp->bufmgr_config.mbuf_high_water_jumbo =
14713                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14714         } else {
14715                 tp->bufmgr_config.mbuf_read_dma_low_water =
14716                         DEFAULT_MB_RDMA_LOW_WATER;
14717                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14718                         DEFAULT_MB_MACRX_LOW_WATER;
14719                 tp->bufmgr_config.mbuf_high_water =
14720                         DEFAULT_MB_HIGH_WATER;
14721
14722                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14723                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14724                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14725                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14726                 tp->bufmgr_config.mbuf_high_water_jumbo =
14727                         DEFAULT_MB_HIGH_WATER_JUMBO;
14728         }
14729
14730         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14731         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14732 }
14733
14734 static char * __devinit tg3_phy_string(struct tg3 *tp)
14735 {
14736         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14737         case TG3_PHY_ID_BCM5400:        return "5400";
14738         case TG3_PHY_ID_BCM5401:        return "5401";
14739         case TG3_PHY_ID_BCM5411:        return "5411";
14740         case TG3_PHY_ID_BCM5701:        return "5701";
14741         case TG3_PHY_ID_BCM5703:        return "5703";
14742         case TG3_PHY_ID_BCM5704:        return "5704";
14743         case TG3_PHY_ID_BCM5705:        return "5705";
14744         case TG3_PHY_ID_BCM5750:        return "5750";
14745         case TG3_PHY_ID_BCM5752:        return "5752";
14746         case TG3_PHY_ID_BCM5714:        return "5714";
14747         case TG3_PHY_ID_BCM5780:        return "5780";
14748         case TG3_PHY_ID_BCM5755:        return "5755";
14749         case TG3_PHY_ID_BCM5787:        return "5787";
14750         case TG3_PHY_ID_BCM5784:        return "5784";
14751         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14752         case TG3_PHY_ID_BCM5906:        return "5906";
14753         case TG3_PHY_ID_BCM5761:        return "5761";
14754         case TG3_PHY_ID_BCM5718C:       return "5718C";
14755         case TG3_PHY_ID_BCM5718S:       return "5718S";
14756         case TG3_PHY_ID_BCM57765:       return "57765";
14757         case TG3_PHY_ID_BCM5719C:       return "5719C";
14758         case TG3_PHY_ID_BCM5720C:       return "5720C";
14759         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14760         case 0:                 return "serdes";
14761         default:                return "unknown";
14762         }
14763 }
14764
14765 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14766 {
14767         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14768                 strcpy(str, "PCI Express");
14769                 return str;
14770         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14771                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14772
14773                 strcpy(str, "PCIX:");
14774
14775                 if ((clock_ctrl == 7) ||
14776                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14777                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14778                         strcat(str, "133MHz");
14779                 else if (clock_ctrl == 0)
14780                         strcat(str, "33MHz");
14781                 else if (clock_ctrl == 2)
14782                         strcat(str, "50MHz");
14783                 else if (clock_ctrl == 4)
14784                         strcat(str, "66MHz");
14785                 else if (clock_ctrl == 6)
14786                         strcat(str, "100MHz");
14787         } else {
14788                 strcpy(str, "PCI:");
14789                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14790                         strcat(str, "66MHz");
14791                 else
14792                         strcat(str, "33MHz");
14793         }
14794         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14795                 strcat(str, ":32-bit");
14796         else
14797                 strcat(str, ":64-bit");
14798         return str;
14799 }
14800
14801 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14802 {
14803         struct pci_dev *peer;
14804         unsigned int func, devnr = tp->pdev->devfn & ~7;
14805
14806         for (func = 0; func < 8; func++) {
14807                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14808                 if (peer && peer != tp->pdev)
14809                         break;
14810                 pci_dev_put(peer);
14811         }
14812         /* 5704 can be configured in single-port mode, set peer to
14813          * tp->pdev in that case.
14814          */
14815         if (!peer) {
14816                 peer = tp->pdev;
14817                 return peer;
14818         }
14819
14820         /*
14821          * We don't need to keep the refcount elevated; there's no way
14822          * to remove one half of this device without removing the other
14823          */
14824         pci_dev_put(peer);
14825
14826         return peer;
14827 }
14828
14829 static void __devinit tg3_init_coal(struct tg3 *tp)
14830 {
14831         struct ethtool_coalesce *ec = &tp->coal;
14832
14833         memset(ec, 0, sizeof(*ec));
14834         ec->cmd = ETHTOOL_GCOALESCE;
14835         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14836         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14837         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14838         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14839         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14840         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14841         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14842         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14843         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14844
14845         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14846                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14847                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14848                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14849                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14850                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14851         }
14852
14853         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14854                 ec->rx_coalesce_usecs_irq = 0;
14855                 ec->tx_coalesce_usecs_irq = 0;
14856                 ec->stats_block_coalesce_usecs = 0;
14857         }
14858 }
14859
14860 static const struct net_device_ops tg3_netdev_ops = {
14861         .ndo_open               = tg3_open,
14862         .ndo_stop               = tg3_close,
14863         .ndo_start_xmit         = tg3_start_xmit,
14864         .ndo_get_stats64        = tg3_get_stats64,
14865         .ndo_validate_addr      = eth_validate_addr,
14866         .ndo_set_multicast_list = tg3_set_rx_mode,
14867         .ndo_set_mac_address    = tg3_set_mac_addr,
14868         .ndo_do_ioctl           = tg3_ioctl,
14869         .ndo_tx_timeout         = tg3_tx_timeout,
14870         .ndo_change_mtu         = tg3_change_mtu,
14871         .ndo_fix_features       = tg3_fix_features,
14872 #ifdef CONFIG_NET_POLL_CONTROLLER
14873         .ndo_poll_controller    = tg3_poll_controller,
14874 #endif
14875 };
14876
14877 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14878         .ndo_open               = tg3_open,
14879         .ndo_stop               = tg3_close,
14880         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14881         .ndo_get_stats64        = tg3_get_stats64,
14882         .ndo_validate_addr      = eth_validate_addr,
14883         .ndo_set_multicast_list = tg3_set_rx_mode,
14884         .ndo_set_mac_address    = tg3_set_mac_addr,
14885         .ndo_do_ioctl           = tg3_ioctl,
14886         .ndo_tx_timeout         = tg3_tx_timeout,
14887         .ndo_change_mtu         = tg3_change_mtu,
14888 #ifdef CONFIG_NET_POLL_CONTROLLER
14889         .ndo_poll_controller    = tg3_poll_controller,
14890 #endif
14891 };
14892
14893 static int __devinit tg3_init_one(struct pci_dev *pdev,
14894                                   const struct pci_device_id *ent)
14895 {
14896         struct net_device *dev;
14897         struct tg3 *tp;
14898         int i, err, pm_cap;
14899         u32 sndmbx, rcvmbx, intmbx;
14900         char str[40];
14901         u64 dma_mask, persist_dma_mask;
14902         u32 hw_features = 0;
14903
14904         printk_once(KERN_INFO "%s\n", version);
14905
14906         err = pci_enable_device(pdev);
14907         if (err) {
14908                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14909                 return err;
14910         }
14911
14912         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14913         if (err) {
14914                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14915                 goto err_out_disable_pdev;
14916         }
14917
14918         pci_set_master(pdev);
14919
14920         /* Find power-management capability. */
14921         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14922         if (pm_cap == 0) {
14923                 dev_err(&pdev->dev,
14924                         "Cannot find Power Management capability, aborting\n");
14925                 err = -EIO;
14926                 goto err_out_free_res;
14927         }
14928
14929         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14930         if (!dev) {
14931                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14932                 err = -ENOMEM;
14933                 goto err_out_free_res;
14934         }
14935
14936         SET_NETDEV_DEV(dev, &pdev->dev);
14937
14938         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14939
14940         tp = netdev_priv(dev);
14941         tp->pdev = pdev;
14942         tp->dev = dev;
14943         tp->pm_cap = pm_cap;
14944         tp->rx_mode = TG3_DEF_RX_MODE;
14945         tp->tx_mode = TG3_DEF_TX_MODE;
14946
14947         if (tg3_debug > 0)
14948                 tp->msg_enable = tg3_debug;
14949         else
14950                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14951
14952         /* The word/byte swap controls here control register access byte
14953          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14954          * setting below.
14955          */
14956         tp->misc_host_ctrl =
14957                 MISC_HOST_CTRL_MASK_PCI_INT |
14958                 MISC_HOST_CTRL_WORD_SWAP |
14959                 MISC_HOST_CTRL_INDIR_ACCESS |
14960                 MISC_HOST_CTRL_PCISTATE_RW;
14961
14962         /* The NONFRM (non-frame) byte/word swap controls take effect
14963          * on descriptor entries, anything which isn't packet data.
14964          *
14965          * The StrongARM chips on the board (one for tx, one for rx)
14966          * are running in big-endian mode.
14967          */
14968         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14969                         GRC_MODE_WSWAP_NONFRM_DATA);
14970 #ifdef __BIG_ENDIAN
14971         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14972 #endif
14973         spin_lock_init(&tp->lock);
14974         spin_lock_init(&tp->indirect_lock);
14975         INIT_WORK(&tp->reset_task, tg3_reset_task);
14976
14977         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14978         if (!tp->regs) {
14979                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14980                 err = -ENOMEM;
14981                 goto err_out_free_dev;
14982         }
14983
14984         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14985         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14986
14987         dev->ethtool_ops = &tg3_ethtool_ops;
14988         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14989         dev->irq = pdev->irq;
14990
14991         err = tg3_get_invariants(tp);
14992         if (err) {
14993                 dev_err(&pdev->dev,
14994                         "Problem fetching invariants of chip, aborting\n");
14995                 goto err_out_iounmap;
14996         }
14997
14998         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14999             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
15000                 dev->netdev_ops = &tg3_netdev_ops;
15001         else
15002                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
15003
15004
15005         /* The EPB bridge inside 5714, 5715, and 5780 and any
15006          * device behind the EPB cannot support DMA addresses > 40-bit.
15007          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15008          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15009          * do DMA address check in tg3_start_xmit().
15010          */
15011         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
15012                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15013         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
15014                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15015 #ifdef CONFIG_HIGHMEM
15016                 dma_mask = DMA_BIT_MASK(64);
15017 #endif
15018         } else
15019                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
15020
15021         /* Configure DMA attributes. */
15022         if (dma_mask > DMA_BIT_MASK(32)) {
15023                 err = pci_set_dma_mask(pdev, dma_mask);
15024                 if (!err) {
15025                         dev->features |= NETIF_F_HIGHDMA;
15026                         err = pci_set_consistent_dma_mask(pdev,
15027                                                           persist_dma_mask);
15028                         if (err < 0) {
15029                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15030                                         "DMA for consistent allocations\n");
15031                                 goto err_out_iounmap;
15032                         }
15033                 }
15034         }
15035         if (err || dma_mask == DMA_BIT_MASK(32)) {
15036                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
15037                 if (err) {
15038                         dev_err(&pdev->dev,
15039                                 "No usable DMA configuration, aborting\n");
15040                         goto err_out_iounmap;
15041                 }
15042         }
15043
15044         tg3_init_bufmgr_config(tp);
15045
15046         /* Selectively allow TSO based on operating conditions */
15047         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
15048             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
15049                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
15050         else {
15051                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
15052                 tp->fw_needed = NULL;
15053         }
15054
15055         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
15056                 tp->fw_needed = FIRMWARE_TG3;
15057
15058         /* TSO is on by default on chips that support hardware TSO.
15059          * Firmware TSO on older chips gives lower performance, so it
15060          * is off by default, but can be enabled using ethtool.
15061          */
15062         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
15063             (dev->features & NETIF_F_IP_CSUM))
15064                 hw_features |= NETIF_F_TSO;
15065         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
15066             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
15067                 if (dev->features & NETIF_F_IPV6_CSUM)
15068                         hw_features |= NETIF_F_TSO6;
15069                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
15070                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15071                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15072                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15073                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15074                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15075                         hw_features |= NETIF_F_TSO_ECN;
15076         }
15077
15078         dev->hw_features |= hw_features;
15079         dev->features |= hw_features;
15080         dev->vlan_features |= hw_features;
15081
15082         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15083             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
15084             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15085                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
15086                 tp->rx_pending = 63;
15087         }
15088
15089         err = tg3_get_device_address(tp);
15090         if (err) {
15091                 dev_err(&pdev->dev,
15092                         "Could not obtain valid ethernet address, aborting\n");
15093                 goto err_out_iounmap;
15094         }
15095
15096         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
15097                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15098                 if (!tp->aperegs) {
15099                         dev_err(&pdev->dev,
15100                                 "Cannot map APE registers, aborting\n");
15101                         err = -ENOMEM;
15102                         goto err_out_iounmap;
15103                 }
15104
15105                 tg3_ape_lock_init(tp);
15106
15107                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
15108                         tg3_read_dash_ver(tp);
15109         }
15110
15111         /*
15112          * Reset chip in case UNDI or EFI driver did not shutdown
15113          * DMA self test will enable WDMAC and we'll see (spurious)
15114          * pending DMA on the PCI bus at that point.
15115          */
15116         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15117             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15118                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15119                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15120         }
15121
15122         err = tg3_test_dma(tp);
15123         if (err) {
15124                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15125                 goto err_out_apeunmap;
15126         }
15127
15128         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15129         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15130         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15131         for (i = 0; i < tp->irq_max; i++) {
15132                 struct tg3_napi *tnapi = &tp->napi[i];
15133
15134                 tnapi->tp = tp;
15135                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15136
15137                 tnapi->int_mbox = intmbx;
15138                 if (i < 4)
15139                         intmbx += 0x8;
15140                 else
15141                         intmbx += 0x4;
15142
15143                 tnapi->consmbox = rcvmbx;
15144                 tnapi->prodmbox = sndmbx;
15145
15146                 if (i)
15147                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15148                 else
15149                         tnapi->coal_now = HOSTCC_MODE_NOW;
15150
15151                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
15152                         break;
15153
15154                 /*
15155                  * If we support MSIX, we'll be using RSS.  If we're using
15156                  * RSS, the first vector only handles link interrupts and the
15157                  * remaining vectors handle rx and tx interrupts.  Reuse the
15158                  * mailbox values for the next iteration.  The values we setup
15159                  * above are still useful for the single vectored mode.
15160                  */
15161                 if (!i)
15162                         continue;
15163
15164                 rcvmbx += 0x8;
15165
15166                 if (sndmbx & 0x4)
15167                         sndmbx -= 0x4;
15168                 else
15169                         sndmbx += 0xc;
15170         }
15171
15172         tg3_init_coal(tp);
15173
15174         pci_set_drvdata(pdev, dev);
15175
15176         err = register_netdev(dev);
15177         if (err) {
15178                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15179                 goto err_out_apeunmap;
15180         }
15181
15182         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15183                     tp->board_part_number,
15184                     tp->pci_chip_rev_id,
15185                     tg3_bus_string(tp, str),
15186                     dev->dev_addr);
15187
15188         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15189                 struct phy_device *phydev;
15190                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15191                 netdev_info(dev,
15192                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15193                             phydev->drv->name, dev_name(&phydev->dev));
15194         } else {
15195                 char *ethtype;
15196
15197                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15198                         ethtype = "10/100Base-TX";
15199                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15200                         ethtype = "1000Base-SX";
15201                 else
15202                         ethtype = "10/100/1000Base-T";
15203
15204                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15205                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
15206                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
15207         }
15208
15209         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15210                     (dev->features & NETIF_F_RXCSUM) != 0,
15211                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
15212                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15213                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
15214                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
15215         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15216                     tp->dma_rwctrl,
15217                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15218                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15219
15220         return 0;
15221
15222 err_out_apeunmap:
15223         if (tp->aperegs) {
15224                 iounmap(tp->aperegs);
15225                 tp->aperegs = NULL;
15226         }
15227
15228 err_out_iounmap:
15229         if (tp->regs) {
15230                 iounmap(tp->regs);
15231                 tp->regs = NULL;
15232         }
15233
15234 err_out_free_dev:
15235         free_netdev(dev);
15236
15237 err_out_free_res:
15238         pci_release_regions(pdev);
15239
15240 err_out_disable_pdev:
15241         pci_disable_device(pdev);
15242         pci_set_drvdata(pdev, NULL);
15243         return err;
15244 }
15245
15246 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15247 {
15248         struct net_device *dev = pci_get_drvdata(pdev);
15249
15250         if (dev) {
15251                 struct tg3 *tp = netdev_priv(dev);
15252
15253                 if (tp->fw)
15254                         release_firmware(tp->fw);
15255
15256                 cancel_work_sync(&tp->reset_task);
15257
15258                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
15259                         tg3_phy_fini(tp);
15260                         tg3_mdio_fini(tp);
15261                 }
15262
15263                 unregister_netdev(dev);
15264                 if (tp->aperegs) {
15265                         iounmap(tp->aperegs);
15266                         tp->aperegs = NULL;
15267                 }
15268                 if (tp->regs) {
15269                         iounmap(tp->regs);
15270                         tp->regs = NULL;
15271                 }
15272                 free_netdev(dev);
15273                 pci_release_regions(pdev);
15274                 pci_disable_device(pdev);
15275                 pci_set_drvdata(pdev, NULL);
15276         }
15277 }
15278
15279 #ifdef CONFIG_PM_SLEEP
15280 static int tg3_suspend(struct device *device)
15281 {
15282         struct pci_dev *pdev = to_pci_dev(device);
15283         struct net_device *dev = pci_get_drvdata(pdev);
15284         struct tg3 *tp = netdev_priv(dev);
15285         int err;
15286
15287         if (!netif_running(dev))
15288                 return 0;
15289
15290         flush_work_sync(&tp->reset_task);
15291         tg3_phy_stop(tp);
15292         tg3_netif_stop(tp);
15293
15294         del_timer_sync(&tp->timer);
15295
15296         tg3_full_lock(tp, 1);
15297         tg3_disable_ints(tp);
15298         tg3_full_unlock(tp);
15299
15300         netif_device_detach(dev);
15301
15302         tg3_full_lock(tp, 0);
15303         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15304         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15305         tg3_full_unlock(tp);
15306
15307         err = tg3_power_down_prepare(tp);
15308         if (err) {
15309                 int err2;
15310
15311                 tg3_full_lock(tp, 0);
15312
15313                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15314                 err2 = tg3_restart_hw(tp, 1);
15315                 if (err2)
15316                         goto out;
15317
15318                 tp->timer.expires = jiffies + tp->timer_offset;
15319                 add_timer(&tp->timer);
15320
15321                 netif_device_attach(dev);
15322                 tg3_netif_start(tp);
15323
15324 out:
15325                 tg3_full_unlock(tp);
15326
15327                 if (!err2)
15328                         tg3_phy_start(tp);
15329         }
15330
15331         return err;
15332 }
15333
15334 static int tg3_resume(struct device *device)
15335 {
15336         struct pci_dev *pdev = to_pci_dev(device);
15337         struct net_device *dev = pci_get_drvdata(pdev);
15338         struct tg3 *tp = netdev_priv(dev);
15339         int err;
15340
15341         if (!netif_running(dev))
15342                 return 0;
15343
15344         netif_device_attach(dev);
15345
15346         tg3_full_lock(tp, 0);
15347
15348         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15349         err = tg3_restart_hw(tp, 1);
15350         if (err)
15351                 goto out;
15352
15353         tp->timer.expires = jiffies + tp->timer_offset;
15354         add_timer(&tp->timer);
15355
15356         tg3_netif_start(tp);
15357
15358 out:
15359         tg3_full_unlock(tp);
15360
15361         if (!err)
15362                 tg3_phy_start(tp);
15363
15364         return err;
15365 }
15366
15367 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15368 #define TG3_PM_OPS (&tg3_pm_ops)
15369
15370 #else
15371
15372 #define TG3_PM_OPS NULL
15373
15374 #endif /* CONFIG_PM_SLEEP */
15375
15376 static struct pci_driver tg3_driver = {
15377         .name           = DRV_MODULE_NAME,
15378         .id_table       = tg3_pci_tbl,
15379         .probe          = tg3_init_one,
15380         .remove         = __devexit_p(tg3_remove_one),
15381         .driver.pm      = TG3_PM_OPS,
15382 };
15383
15384 static int __init tg3_init(void)
15385 {
15386         return pci_register_driver(&tg3_driver);
15387 }
15388
15389 static void __exit tg3_cleanup(void)
15390 {
15391         pci_unregister_driver(&tg3_driver);
15392 }
15393
15394 module_init(tg3_init);
15395 module_exit(tg3_cleanup);