2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.27"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
147 MODULE_DEVICE_TABLE(pci, sky2_id_table);
149 /* Avoid conditionals by using array */
150 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
152 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
154 static void sky2_set_multicast(struct net_device *dev);
156 /* Access to PHY via serial interconnect */
157 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
165 for (i = 0; i < PHY_RETRIES; i++) {
166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
170 if (!(ctrl & GM_SMI_CT_BUSY))
176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
184 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
191 for (i = 0; i < PHY_RETRIES; i++) {
192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
196 if (ctrl & GM_SMI_CT_RD_VAL) {
197 *val = gma_read16(hw, port, GM_SMI_DATA);
204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
211 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
214 __gm_phy_read(hw, port, reg, &v);
219 static void sky2_power_on(struct sky2_hw *hw)
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
254 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
256 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
257 reg = sky2_read32(hw, B2_GP_IO);
258 reg |= GLB_GPIO_STAT_RACE_DIS;
259 sky2_write32(hw, B2_GP_IO, reg);
261 sky2_read32(hw, B2_GP_IO);
264 /* Turn on "driver loaded" LED */
265 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
268 static void sky2_power_aux(struct sky2_hw *hw)
270 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
271 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
273 /* enable bits are inverted */
274 sky2_write8(hw, B2_Y2_CLK_GATE,
275 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
279 /* switch power to VAUX if supported and PME from D3cold */
280 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
281 pci_pme_capable(hw->pdev, PCI_D3cold))
282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
286 /* turn off "driver loaded LED" */
287 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
290 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
294 /* disable all GMAC IRQ's */
295 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
297 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
298 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
299 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
302 reg = gma_read16(hw, port, GM_RX_CTRL);
303 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
304 gma_write16(hw, port, GM_RX_CTRL, reg);
307 /* flow control to advertise bits */
308 static const u16 copper_fc_adv[] = {
310 [FC_TX] = PHY_M_AN_ASP,
311 [FC_RX] = PHY_M_AN_PC,
312 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
315 /* flow control to advertise bits when using 1000BaseX */
316 static const u16 fiber_fc_adv[] = {
317 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
318 [FC_TX] = PHY_M_P_ASYM_MD_X,
319 [FC_RX] = PHY_M_P_SYM_MD_X,
320 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
323 /* flow control to GMA disable bits */
324 static const u16 gm_fc_disable[] = {
325 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
326 [FC_TX] = GM_GPCR_FC_RX_DIS,
327 [FC_RX] = GM_GPCR_FC_TX_DIS,
332 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
334 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
335 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
337 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
338 !(hw->flags & SKY2_HW_NEWER_PHY)) {
339 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
341 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
343 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
345 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
346 if (hw->chip_id == CHIP_ID_YUKON_EC)
347 /* set downshift counter to 3x and enable downshift */
348 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
350 /* set master & slave downshift counter to 1x */
351 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
353 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
356 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
357 if (sky2_is_copper(hw)) {
358 if (!(hw->flags & SKY2_HW_GIGABIT)) {
359 /* enable automatic crossover */
360 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
362 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
363 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
366 /* Enable Class A driver for FE+ A0 */
367 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
368 spec |= PHY_M_FESC_SEL_CL_A;
369 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
372 /* disable energy detect */
373 ctrl &= ~PHY_M_PC_EN_DET_MSK;
375 /* enable automatic crossover */
376 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
378 /* downshift on PHY 88E1112 and 88E1149 is changed */
379 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
380 (hw->flags & SKY2_HW_NEWER_PHY)) {
381 /* set downshift counter to 3x and enable downshift */
382 ctrl &= ~PHY_M_PC_DSC_MSK;
383 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
387 /* workaround for deviation #4.88 (CRC errors) */
388 /* disable Automatic Crossover */
390 ctrl &= ~PHY_M_PC_MDIX_MSK;
393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
395 /* special setup for PHY 88E1112 Fiber */
396 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
397 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
399 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
400 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
401 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
402 ctrl &= ~PHY_M_MAC_MD_MSK;
403 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
404 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
406 if (hw->pmd_type == 'P') {
407 /* select page 1 to access Fiber registers */
408 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
410 /* for SFP-module set SIGDET polarity to low */
411 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
412 ctrl |= PHY_M_FIB_SIGD_POL;
413 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
416 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
424 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
425 if (sky2_is_copper(hw)) {
426 if (sky2->advertising & ADVERTISED_1000baseT_Full)
427 ct1000 |= PHY_M_1000C_AFD;
428 if (sky2->advertising & ADVERTISED_1000baseT_Half)
429 ct1000 |= PHY_M_1000C_AHD;
430 if (sky2->advertising & ADVERTISED_100baseT_Full)
431 adv |= PHY_M_AN_100_FD;
432 if (sky2->advertising & ADVERTISED_100baseT_Half)
433 adv |= PHY_M_AN_100_HD;
434 if (sky2->advertising & ADVERTISED_10baseT_Full)
435 adv |= PHY_M_AN_10_FD;
436 if (sky2->advertising & ADVERTISED_10baseT_Half)
437 adv |= PHY_M_AN_10_HD;
439 } else { /* special defines for FIBER (88E1040S only) */
440 if (sky2->advertising & ADVERTISED_1000baseT_Full)
441 adv |= PHY_M_AN_1000X_AFD;
442 if (sky2->advertising & ADVERTISED_1000baseT_Half)
443 adv |= PHY_M_AN_1000X_AHD;
446 /* Restart Auto-negotiation */
447 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
449 /* forced speed/duplex settings */
450 ct1000 = PHY_M_1000C_MSE;
452 /* Disable auto update for duplex flow control and duplex */
453 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
455 switch (sky2->speed) {
457 ctrl |= PHY_CT_SP1000;
458 reg |= GM_GPCR_SPEED_1000;
461 ctrl |= PHY_CT_SP100;
462 reg |= GM_GPCR_SPEED_100;
466 if (sky2->duplex == DUPLEX_FULL) {
467 reg |= GM_GPCR_DUP_FULL;
468 ctrl |= PHY_CT_DUP_MD;
469 } else if (sky2->speed < SPEED_1000)
470 sky2->flow_mode = FC_NONE;
473 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
474 if (sky2_is_copper(hw))
475 adv |= copper_fc_adv[sky2->flow_mode];
477 adv |= fiber_fc_adv[sky2->flow_mode];
479 reg |= GM_GPCR_AU_FCT_DIS;
480 reg |= gm_fc_disable[sky2->flow_mode];
482 /* Forward pause packets to GMAC? */
483 if (sky2->flow_mode & FC_RX)
484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
486 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
489 gma_write16(hw, port, GM_GP_CTRL, reg);
491 if (hw->flags & SKY2_HW_GIGABIT)
492 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
494 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
495 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
497 /* Setup Phy LED's */
498 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
501 switch (hw->chip_id) {
502 case CHIP_ID_YUKON_FE:
503 /* on 88E3082 these bits are at 11..9 (shifted left) */
504 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
506 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
508 /* delete ACT LED control bits */
509 ctrl &= ~PHY_M_FELP_LED1_MSK;
510 /* change ACT LED control to blink mode */
511 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
515 case CHIP_ID_YUKON_FE_P:
516 /* Enable Link Partner Next Page */
517 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
518 ctrl |= PHY_M_PC_ENA_LIP_NP;
520 /* disable Energy Detect and enable scrambler */
521 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
524 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
525 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
526 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
527 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
529 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
532 case CHIP_ID_YUKON_XL:
533 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
535 /* select page 3 to access LED control register */
536 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
538 /* set LED Function Control register */
539 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
540 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
541 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
542 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
543 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
545 /* set Polarity Control register */
546 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
547 (PHY_M_POLC_LS1_P_MIX(4) |
548 PHY_M_POLC_IS0_P_MIX(4) |
549 PHY_M_POLC_LOS_CTRL(2) |
550 PHY_M_POLC_INIT_CTRL(2) |
551 PHY_M_POLC_STA1_CTRL(2) |
552 PHY_M_POLC_STA0_CTRL(2)));
554 /* restore page register */
555 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
558 case CHIP_ID_YUKON_EC_U:
559 case CHIP_ID_YUKON_EX:
560 case CHIP_ID_YUKON_SUPR:
561 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
563 /* select page 3 to access LED control register */
564 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
566 /* set LED Function Control register */
567 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
568 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
569 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
570 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
571 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
573 /* set Blink Rate in LED Timer Control Register */
574 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
575 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
576 /* restore page register */
577 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
581 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
582 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
584 /* turn off the Rx LED (LED_RX) */
585 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
588 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
589 /* apply fixes in PHY AFE */
590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
592 /* increase differential signal amplitude in 10BASE-T */
593 gm_phy_write(hw, port, 0x18, 0xaa99);
594 gm_phy_write(hw, port, 0x17, 0x2011);
596 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
597 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
598 gm_phy_write(hw, port, 0x18, 0xa204);
599 gm_phy_write(hw, port, 0x17, 0x2002);
602 /* set page register to 0 */
603 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
604 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
605 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
606 /* apply workaround for integrated resistors calibration */
607 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
608 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
609 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
610 /* apply fixes in PHY AFE */
611 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
613 /* apply RDAC termination workaround */
614 gm_phy_write(hw, port, 24, 0x2800);
615 gm_phy_write(hw, port, 23, 0x2001);
617 /* set page register back to 0 */
618 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
619 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
620 hw->chip_id < CHIP_ID_YUKON_SUPR) {
621 /* no effect on Yukon-XL */
622 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
624 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
625 sky2->speed == SPEED_100) {
626 /* turn on 100 Mbps LED (LED_LINK100) */
627 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
631 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
635 /* Enable phy interrupt on auto-negotiation complete (or link up) */
636 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
639 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
642 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
643 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
645 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
649 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
650 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
651 reg1 &= ~phy_power[port];
653 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
654 reg1 |= coma_mode[port];
656 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
657 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
658 sky2_pci_read32(hw, PCI_DEV_REG1);
660 if (hw->chip_id == CHIP_ID_YUKON_FE)
661 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
662 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
663 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
666 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
671 /* release GPHY Control reset */
672 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
674 /* release GMAC reset */
675 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
677 if (hw->flags & SKY2_HW_NEWER_PHY) {
678 /* select page 2 to access MAC control register */
679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
681 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
682 /* allow GMII Power Down */
683 ctrl &= ~PHY_M_MAC_GMIF_PUP;
684 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
686 /* set page register back to 0 */
687 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
690 /* setup General Purpose Control Register */
691 gma_write16(hw, port, GM_GP_CTRL,
692 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
693 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
696 if (hw->chip_id != CHIP_ID_YUKON_EC) {
697 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
698 /* select page 2 to access MAC control register */
699 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
701 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
702 /* enable Power Down */
703 ctrl |= PHY_M_PC_POW_D_ENA;
704 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
706 /* set page register back to 0 */
707 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
710 /* set IEEE compatible Power Down Mode (dev. #4.99) */
711 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
714 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
715 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
716 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
717 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
718 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
721 /* Force a renegotiation */
722 static void sky2_phy_reinit(struct sky2_port *sky2)
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_init(sky2->hw, sky2->port);
726 spin_unlock_bh(&sky2->phy_lock);
729 /* Put device in state to listen for Wake On Lan */
730 static void sky2_wol_init(struct sky2_port *sky2)
732 struct sky2_hw *hw = sky2->hw;
733 unsigned port = sky2->port;
734 enum flow_control save_mode;
737 /* Bring hardware out of reset */
738 sky2_write16(hw, B0_CTST, CS_RST_CLR);
739 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
741 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
742 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
745 * sky2_reset will re-enable on resume
747 save_mode = sky2->flow_mode;
748 ctrl = sky2->advertising;
750 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
751 sky2->flow_mode = FC_NONE;
753 spin_lock_bh(&sky2->phy_lock);
754 sky2_phy_power_up(hw, port);
755 sky2_phy_init(hw, port);
756 spin_unlock_bh(&sky2->phy_lock);
758 sky2->flow_mode = save_mode;
759 sky2->advertising = ctrl;
761 /* Set GMAC to no flow control and auto update for speed/duplex */
762 gma_write16(hw, port, GM_GP_CTRL,
763 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
764 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
766 /* Set WOL address */
767 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
768 sky2->netdev->dev_addr, ETH_ALEN);
770 /* Turn on appropriate WOL control bits */
771 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
773 if (sky2->wol & WAKE_PHY)
774 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
776 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
778 if (sky2->wol & WAKE_MAGIC)
779 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
781 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
783 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
784 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
786 /* Disable PiG firmware */
787 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
790 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
793 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
795 struct net_device *dev = hw->dev[port];
797 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
798 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
799 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
800 /* Yukon-Extreme B0 and further Extreme devices */
801 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
802 } else if (dev->mtu > ETH_DATA_LEN) {
803 /* set Tx GMAC FIFO Almost Empty Threshold */
804 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
805 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
807 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
809 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
812 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
814 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
818 const u8 *addr = hw->dev[port]->dev_addr;
820 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
821 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
825 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
826 /* WA DEV_472 -- looks like crossed wires on port 2 */
827 /* clear GMAC 1 Control reset */
828 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
830 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
831 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
832 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
833 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
834 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
837 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
839 /* Enable Transmit FIFO Underrun */
840 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
842 spin_lock_bh(&sky2->phy_lock);
843 sky2_phy_power_up(hw, port);
844 sky2_phy_init(hw, port);
845 spin_unlock_bh(&sky2->phy_lock);
848 reg = gma_read16(hw, port, GM_PHY_ADDR);
849 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
851 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
852 gma_read16(hw, port, i);
853 gma_write16(hw, port, GM_PHY_ADDR, reg);
855 /* transmit control */
856 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
858 /* receive control reg: unicast + multicast + no FCS */
859 gma_write16(hw, port, GM_RX_CTRL,
860 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
862 /* transmit flow control */
863 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
865 /* transmit parameter */
866 gma_write16(hw, port, GM_TX_PARAM,
867 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
868 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
869 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
870 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
872 /* serial mode register */
873 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
874 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
876 if (hw->dev[port]->mtu > ETH_DATA_LEN)
877 reg |= GM_SMOD_JUMBO_ENA;
879 gma_write16(hw, port, GM_SERIAL_MODE, reg);
881 /* virtual address for data */
882 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
884 /* physical address: used for pause frames */
885 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
887 /* ignore counter overflows */
888 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
889 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
890 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
892 /* Configure Rx MAC FIFO */
893 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
894 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
895 if (hw->chip_id == CHIP_ID_YUKON_EX ||
896 hw->chip_id == CHIP_ID_YUKON_FE_P)
897 rx_reg |= GMF_RX_OVER_ON;
899 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
901 if (hw->chip_id == CHIP_ID_YUKON_XL) {
902 /* Hardware errata - clear flush mask */
903 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
905 /* Flush Rx MAC FIFO on any flow control or error */
906 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
909 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
910 reg = RX_GMF_FL_THR_DEF + 1;
911 /* Another magic mystery workaround from sk98lin */
912 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
913 hw->chip_rev == CHIP_REV_YU_FE2_A0)
915 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
917 /* Configure Tx MAC FIFO */
918 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
919 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
921 /* On chips without ram buffer, pause is controled by MAC level */
922 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
923 /* Pause threshold is scaled by 8 in bytes */
924 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
925 hw->chip_rev == CHIP_REV_YU_FE2_A0)
929 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
930 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
932 sky2_set_tx_stfwd(hw, port);
935 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
936 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
937 /* disable dynamic watermark */
938 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
939 reg &= ~TX_DYN_WM_ENA;
940 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
944 /* Assign Ram Buffer allocation to queue */
945 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
949 /* convert from K bytes to qwords used for hw register */
952 end = start + space - 1;
954 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
955 sky2_write32(hw, RB_ADDR(q, RB_START), start);
956 sky2_write32(hw, RB_ADDR(q, RB_END), end);
957 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
958 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
960 if (q == Q_R1 || q == Q_R2) {
961 u32 tp = space - space/4;
963 /* On receive queue's set the thresholds
964 * give receiver priority when > 3/4 full
965 * send pause when down to 2K
967 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
968 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
971 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
972 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
974 /* Enable store & forward on Tx queue's because
975 * Tx FIFO is only 1K on Yukon
977 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
980 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
981 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
984 /* Setup Bus Memory Interface */
985 static void sky2_qset(struct sky2_hw *hw, u16 q)
987 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
988 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
989 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
990 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
993 /* Setup prefetch unit registers. This is the interface between
994 * hardware and driver list elements
996 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
997 dma_addr_t addr, u32 last)
999 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1000 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1001 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1002 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1003 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1004 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1006 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1009 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1011 struct sky2_tx_le *le = sky2->tx_le + *slot;
1013 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1018 static void tx_init(struct sky2_port *sky2)
1020 struct sky2_tx_le *le;
1022 sky2->tx_prod = sky2->tx_cons = 0;
1023 sky2->tx_tcpsum = 0;
1024 sky2->tx_last_mss = 0;
1026 le = get_tx_le(sky2, &sky2->tx_prod);
1028 le->opcode = OP_ADDR64 | HW_OWNER;
1029 sky2->tx_last_upper = 0;
1032 /* Update chip's next pointer */
1033 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1035 /* Make sure write' to descriptors are complete before we tell hardware */
1037 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1039 /* Synchronize I/O on since next processor may write to tail */
1044 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1046 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1047 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1052 static unsigned sky2_get_rx_threshold(struct sky2_port* sky2)
1056 /* Space needed for frame data + headers rounded up */
1057 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1059 /* Stopping point for hardware truncation */
1060 return (size - 8) / sizeof(u32);
1063 static unsigned sky2_get_rx_data_size(struct sky2_port* sky2)
1065 struct rx_ring_info *re;
1068 /* Space needed for frame data + headers rounded up */
1069 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1071 sky2->rx_nfrags = size >> PAGE_SHIFT;
1072 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1074 /* Compute residue after pages */
1075 size -= sky2->rx_nfrags << PAGE_SHIFT;
1077 /* Optimize to handle small packets and headers */
1078 if (size < copybreak)
1080 if (size < ETH_HLEN)
1086 /* Build description to hardware for one receive segment */
1087 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1088 dma_addr_t map, unsigned len)
1090 struct sky2_rx_le *le;
1092 if (sizeof(dma_addr_t) > sizeof(u32)) {
1093 le = sky2_next_rx(sky2);
1094 le->addr = cpu_to_le32(upper_32_bits(map));
1095 le->opcode = OP_ADDR64 | HW_OWNER;
1098 le = sky2_next_rx(sky2);
1099 le->addr = cpu_to_le32(lower_32_bits(map));
1100 le->length = cpu_to_le16(len);
1101 le->opcode = op | HW_OWNER;
1104 /* Build description to hardware for one possibly fragmented skb */
1105 static void sky2_rx_submit(struct sky2_port *sky2,
1106 const struct rx_ring_info *re)
1110 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1112 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1113 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1117 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1120 struct sk_buff *skb = re->skb;
1123 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1124 if (pci_dma_mapping_error(pdev, re->data_addr))
1127 pci_unmap_len_set(re, data_size, size);
1129 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1130 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1132 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1135 PCI_DMA_FROMDEVICE);
1137 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1138 goto map_page_error;
1144 pci_unmap_page(pdev, re->frag_addr[i],
1145 skb_shinfo(skb)->frags[i].size,
1146 PCI_DMA_FROMDEVICE);
1149 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1150 PCI_DMA_FROMDEVICE);
1153 if (net_ratelimit())
1154 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1159 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1161 struct sk_buff *skb = re->skb;
1164 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1165 PCI_DMA_FROMDEVICE);
1167 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1168 pci_unmap_page(pdev, re->frag_addr[i],
1169 skb_shinfo(skb)->frags[i].size,
1170 PCI_DMA_FROMDEVICE);
1173 /* Tell chip where to start receive checksum.
1174 * Actually has two checksums, but set both same to avoid possible byte
1177 static void rx_set_checksum(struct sky2_port *sky2)
1179 struct sky2_rx_le *le = sky2_next_rx(sky2);
1181 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1183 le->opcode = OP_TCPSTART | HW_OWNER;
1185 sky2_write32(sky2->hw,
1186 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1187 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1188 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1192 * The RX Stop command will not work for Yukon-2 if the BMU does not
1193 * reach the end of packet and since we can't make sure that we have
1194 * incoming data, we must reset the BMU while it is not doing a DMA
1195 * transfer. Since it is possible that the RX path is still active,
1196 * the RX RAM buffer will be stopped first, so any possible incoming
1197 * data will not trigger a DMA. After the RAM buffer is stopped, the
1198 * BMU is polled until any DMA in progress is ended and only then it
1201 static void sky2_rx_stop(struct sky2_port *sky2)
1203 struct sky2_hw *hw = sky2->hw;
1204 unsigned rxq = rxqaddr[sky2->port];
1207 /* disable the RAM Buffer receive queue */
1208 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1210 for (i = 0; i < 0xffff; i++)
1211 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1212 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1215 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1216 sky2->netdev->name);
1218 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1220 /* reset the Rx prefetch unit */
1221 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1225 /* Clean out receive buffer area, assumes receiver hardware stopped */
1226 static void sky2_rx_clean(struct sky2_port *sky2)
1230 memset(sky2->rx_le, 0, RX_LE_BYTES);
1231 for (i = 0; i < sky2->rx_pending; i++) {
1232 struct rx_ring_info *re = sky2->rx_ring + i;
1235 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1242 /* Basic MII support */
1243 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1245 struct mii_ioctl_data *data = if_mii(ifr);
1246 struct sky2_port *sky2 = netdev_priv(dev);
1247 struct sky2_hw *hw = sky2->hw;
1248 int err = -EOPNOTSUPP;
1250 if (!netif_running(dev))
1251 return -ENODEV; /* Phy still in reset */
1255 data->phy_id = PHY_ADDR_MARV;
1261 spin_lock_bh(&sky2->phy_lock);
1262 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1263 spin_unlock_bh(&sky2->phy_lock);
1265 data->val_out = val;
1270 spin_lock_bh(&sky2->phy_lock);
1271 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1273 spin_unlock_bh(&sky2->phy_lock);
1279 #ifdef SKY2_VLAN_TAG_USED
1280 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1283 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1285 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1288 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1290 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1295 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1297 struct sky2_port *sky2 = netdev_priv(dev);
1298 struct sky2_hw *hw = sky2->hw;
1299 u16 port = sky2->port;
1301 netif_tx_lock_bh(dev);
1302 napi_disable(&hw->napi);
1305 sky2_set_vlan_mode(hw, port, grp != NULL);
1307 sky2_read32(hw, B0_Y2_SP_LISR);
1308 napi_enable(&hw->napi);
1309 netif_tx_unlock_bh(dev);
1313 /* Amount of required worst case padding in rx buffer */
1314 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1316 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1320 * Allocate an skb for receiving. If the MTU is large enough
1321 * make the skb non-linear with a fragment list of pages.
1323 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1325 struct sk_buff *skb;
1328 skb = netdev_alloc_skb(sky2->netdev,
1329 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1333 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1334 unsigned char *start;
1336 * Workaround for a bug in FIFO that cause hang
1337 * if the FIFO if the receive buffer is not 64 byte aligned.
1338 * The buffer returned from netdev_alloc_skb is
1339 * aligned except if slab debugging is enabled.
1341 start = PTR_ALIGN(skb->data, 8);
1342 skb_reserve(skb, start - skb->data);
1344 skb_reserve(skb, NET_IP_ALIGN);
1346 for (i = 0; i < sky2->rx_nfrags; i++) {
1347 struct page *page = alloc_page(GFP_ATOMIC);
1351 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1361 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1363 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1366 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1368 struct sky2_hw *hw = sky2->hw;
1371 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1374 for (i = 0; i < sky2->rx_pending; i++) {
1375 struct rx_ring_info *re = sky2->rx_ring + i;
1377 re->skb = sky2_rx_alloc(sky2);
1381 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1382 dev_kfree_skb(re->skb);
1391 * Setup receiver buffer pool.
1392 * Normal case this ends up creating one list element for skb
1393 * in the receive ring. Worst case if using large MTU and each
1394 * allocation falls on a different 64 bit region, that results
1395 * in 6 list elements per ring entry.
1396 * One element is used for checksum enable/disable, and one
1397 * extra to avoid wrap.
1399 static void sky2_rx_start(struct sky2_port *sky2)
1401 struct sky2_hw *hw = sky2->hw;
1402 struct rx_ring_info *re;
1403 unsigned rxq = rxqaddr[sky2->port];
1406 sky2->rx_put = sky2->rx_next = 0;
1409 /* On PCI express lowering the watermark gives better performance */
1410 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1411 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1413 /* These chips have no ram buffer?
1414 * MAC Rx RAM Read is controlled by hardware */
1415 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1416 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1417 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1418 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1420 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1422 if (!(hw->flags & SKY2_HW_NEW_LE))
1423 rx_set_checksum(sky2);
1425 /* submit Rx ring */
1426 for (i = 0; i < sky2->rx_pending; i++) {
1427 re = sky2->rx_ring + i;
1428 sky2_rx_submit(sky2, re);
1432 * The receiver hangs if it receives frames larger than the
1433 * packet buffer. As a workaround, truncate oversize frames, but
1434 * the register is limited to 9 bits, so if you do frames > 2052
1435 * you better get the MTU right!
1437 thresh = sky2_get_rx_threshold(sky2);
1439 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1441 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1442 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1445 /* Tell chip about available buffers */
1446 sky2_rx_update(sky2, rxq);
1448 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1449 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1451 * Disable flushing of non ASF packets;
1452 * must be done after initializing the BMUs;
1453 * drivers without ASF support should do this too, otherwise
1454 * it may happen that they cannot run on ASF devices;
1455 * remember that the MAC FIFO isn't reset during initialization.
1457 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1460 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1461 /* Enable RX Home Address & Routing Header checksum fix */
1462 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1463 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1465 /* Enable TX Home Address & Routing Header checksum fix */
1466 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1467 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1471 static int sky2_alloc_buffers(struct sky2_port *sky2)
1473 struct sky2_hw *hw = sky2->hw;
1475 /* must be power of 2 */
1476 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1477 sky2->tx_ring_size *
1478 sizeof(struct sky2_tx_le),
1483 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1488 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1492 memset(sky2->rx_le, 0, RX_LE_BYTES);
1494 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1499 return sky2_alloc_rx_skbs(sky2);
1504 static void sky2_free_buffers(struct sky2_port *sky2)
1506 struct sky2_hw *hw = sky2->hw;
1508 sky2_rx_clean(sky2);
1511 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1512 sky2->rx_le, sky2->rx_le_map);
1516 pci_free_consistent(hw->pdev,
1517 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1518 sky2->tx_le, sky2->tx_le_map);
1521 kfree(sky2->tx_ring);
1522 kfree(sky2->rx_ring);
1524 sky2->tx_ring = NULL;
1525 sky2->rx_ring = NULL;
1528 static void sky2_hw_up(struct sky2_port *sky2)
1530 struct sky2_hw *hw = sky2->hw;
1531 unsigned port = sky2->port;
1534 struct net_device *otherdev = hw->dev[sky2->port^1];
1539 * On dual port PCI-X card, there is an problem where status
1540 * can be received out of order due to split transactions
1542 if (otherdev && netif_running(otherdev) &&
1543 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1546 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1547 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1548 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1551 sky2_mac_init(hw, port);
1553 /* Register is number of 4K blocks on internal RAM buffer. */
1554 ramsize = sky2_read8(hw, B2_E_0) * 4;
1558 pr_debug(PFX "%s: ram buffer %dK\n", sky2->netdev->name, ramsize);
1560 rxspace = ramsize / 2;
1562 rxspace = 8 + (2*(ramsize - 16))/3;
1564 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1565 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1567 /* Make sure SyncQ is disabled */
1568 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1572 sky2_qset(hw, txqaddr[port]);
1574 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1575 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1576 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1578 /* Set almost empty threshold */
1579 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1580 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1581 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1583 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1584 sky2->tx_ring_size - 1);
1586 #ifdef SKY2_VLAN_TAG_USED
1587 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1590 sky2_rx_start(sky2);
1593 /* Bring up network interface. */
1594 static int sky2_up(struct net_device *dev)
1596 struct sky2_port *sky2 = netdev_priv(dev);
1597 struct sky2_hw *hw = sky2->hw;
1598 unsigned port = sky2->port;
1602 netif_carrier_off(dev);
1604 err = sky2_alloc_buffers(sky2);
1610 /* Enable interrupts from phy/mac for port */
1611 imask = sky2_read32(hw, B0_IMSK);
1612 imask |= portirq_msk[port];
1613 sky2_write32(hw, B0_IMSK, imask);
1614 sky2_read32(hw, B0_IMSK);
1616 if (netif_msg_ifup(sky2))
1617 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1622 sky2_free_buffers(sky2);
1626 /* Modular subtraction in ring */
1627 static inline int tx_inuse(const struct sky2_port *sky2)
1629 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1632 /* Number of list elements available for next tx */
1633 static inline int tx_avail(const struct sky2_port *sky2)
1635 return sky2->tx_pending - tx_inuse(sky2);
1638 /* Estimate of number of transmit list elements required */
1639 static unsigned tx_le_req(const struct sk_buff *skb)
1643 count = (skb_shinfo(skb)->nr_frags + 1)
1644 * (sizeof(dma_addr_t) / sizeof(u32));
1646 if (skb_is_gso(skb))
1648 else if (sizeof(dma_addr_t) == sizeof(u32))
1649 ++count; /* possible vlan */
1651 if (skb->ip_summed == CHECKSUM_PARTIAL)
1657 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1659 if (re->flags & TX_MAP_SINGLE)
1660 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1661 pci_unmap_len(re, maplen),
1663 else if (re->flags & TX_MAP_PAGE)
1664 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1665 pci_unmap_len(re, maplen),
1671 * Put one packet in ring for transmit.
1672 * A single packet can generate multiple list elements, and
1673 * the number of ring elements will probably be less than the number
1674 * of list elements used.
1676 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1677 struct net_device *dev)
1679 struct sky2_port *sky2 = netdev_priv(dev);
1680 struct sky2_hw *hw = sky2->hw;
1681 struct sky2_tx_le *le = NULL;
1682 struct tx_ring_info *re;
1690 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1691 return NETDEV_TX_BUSY;
1693 len = skb_headlen(skb);
1694 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1696 if (pci_dma_mapping_error(hw->pdev, mapping))
1699 slot = sky2->tx_prod;
1700 if (unlikely(netif_msg_tx_queued(sky2)))
1701 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1702 dev->name, slot, skb->len);
1704 /* Send high bits if needed */
1705 upper = upper_32_bits(mapping);
1706 if (upper != sky2->tx_last_upper) {
1707 le = get_tx_le(sky2, &slot);
1708 le->addr = cpu_to_le32(upper);
1709 sky2->tx_last_upper = upper;
1710 le->opcode = OP_ADDR64 | HW_OWNER;
1713 /* Check for TCP Segmentation Offload */
1714 mss = skb_shinfo(skb)->gso_size;
1717 if (!(hw->flags & SKY2_HW_NEW_LE))
1718 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1720 if (mss != sky2->tx_last_mss) {
1721 le = get_tx_le(sky2, &slot);
1722 le->addr = cpu_to_le32(mss);
1724 if (hw->flags & SKY2_HW_NEW_LE)
1725 le->opcode = OP_MSS | HW_OWNER;
1727 le->opcode = OP_LRGLEN | HW_OWNER;
1728 sky2->tx_last_mss = mss;
1733 #ifdef SKY2_VLAN_TAG_USED
1734 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1735 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1737 le = get_tx_le(sky2, &slot);
1739 le->opcode = OP_VLAN|HW_OWNER;
1741 le->opcode |= OP_VLAN;
1742 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1747 /* Handle TCP checksum offload */
1748 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1749 /* On Yukon EX (some versions) encoding change. */
1750 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1751 ctrl |= CALSUM; /* auto checksum */
1753 const unsigned offset = skb_transport_offset(skb);
1756 tcpsum = offset << 16; /* sum start */
1757 tcpsum |= offset + skb->csum_offset; /* sum write */
1759 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1760 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1763 if (tcpsum != sky2->tx_tcpsum) {
1764 sky2->tx_tcpsum = tcpsum;
1766 le = get_tx_le(sky2, &slot);
1767 le->addr = cpu_to_le32(tcpsum);
1768 le->length = 0; /* initial checksum value */
1769 le->ctrl = 1; /* one packet */
1770 le->opcode = OP_TCPLISW | HW_OWNER;
1775 re = sky2->tx_ring + slot;
1776 re->flags = TX_MAP_SINGLE;
1777 pci_unmap_addr_set(re, mapaddr, mapping);
1778 pci_unmap_len_set(re, maplen, len);
1780 le = get_tx_le(sky2, &slot);
1781 le->addr = cpu_to_le32(lower_32_bits(mapping));
1782 le->length = cpu_to_le16(len);
1784 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1787 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1788 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1790 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1791 frag->size, PCI_DMA_TODEVICE);
1793 if (pci_dma_mapping_error(hw->pdev, mapping))
1794 goto mapping_unwind;
1796 upper = upper_32_bits(mapping);
1797 if (upper != sky2->tx_last_upper) {
1798 le = get_tx_le(sky2, &slot);
1799 le->addr = cpu_to_le32(upper);
1800 sky2->tx_last_upper = upper;
1801 le->opcode = OP_ADDR64 | HW_OWNER;
1804 re = sky2->tx_ring + slot;
1805 re->flags = TX_MAP_PAGE;
1806 pci_unmap_addr_set(re, mapaddr, mapping);
1807 pci_unmap_len_set(re, maplen, frag->size);
1809 le = get_tx_le(sky2, &slot);
1810 le->addr = cpu_to_le32(lower_32_bits(mapping));
1811 le->length = cpu_to_le16(frag->size);
1813 le->opcode = OP_BUFFER | HW_OWNER;
1819 sky2->tx_prod = slot;
1821 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1822 netif_stop_queue(dev);
1824 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1826 return NETDEV_TX_OK;
1829 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1830 re = sky2->tx_ring + i;
1832 sky2_tx_unmap(hw->pdev, re);
1836 if (net_ratelimit())
1837 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1839 return NETDEV_TX_OK;
1843 * Free ring elements from starting at tx_cons until "done"
1846 * 1. The hardware will tell us about partial completion of multi-part
1847 * buffers so make sure not to free skb to early.
1848 * 2. This may run in parallel start_xmit because the it only
1849 * looks at the tail of the queue of FIFO (tx_cons), not
1850 * the head (tx_prod)
1852 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1854 struct net_device *dev = sky2->netdev;
1857 BUG_ON(done >= sky2->tx_ring_size);
1859 for (idx = sky2->tx_cons; idx != done;
1860 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1861 struct tx_ring_info *re = sky2->tx_ring + idx;
1862 struct sk_buff *skb = re->skb;
1864 sky2_tx_unmap(sky2->hw->pdev, re);
1867 if (unlikely(netif_msg_tx_done(sky2)))
1868 printk(KERN_DEBUG "%s: tx done %u\n",
1871 dev->stats.tx_packets++;
1872 dev->stats.tx_bytes += skb->len;
1875 dev_kfree_skb_any(skb);
1877 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1881 sky2->tx_cons = idx;
1885 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1887 /* Disable Force Sync bit and Enable Alloc bit */
1888 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1889 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1891 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1892 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1893 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1895 /* Reset the PCI FIFO of the async Tx queue */
1896 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1897 BMU_RST_SET | BMU_FIFO_RST);
1899 /* Reset the Tx prefetch units */
1900 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1903 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1904 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1907 static void sky2_hw_down(struct sky2_port *sky2)
1909 struct sky2_hw *hw = sky2->hw;
1910 unsigned port = sky2->port;
1913 /* Force flow control off */
1914 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1916 /* Stop transmitter */
1917 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1918 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1920 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1921 RB_RST_SET | RB_DIS_OP_MD);
1923 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1924 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1925 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1927 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1929 /* Workaround shared GMAC reset */
1930 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1931 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1932 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1934 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1936 /* Force any delayed status interrrupt and NAPI */
1937 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1938 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1939 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1940 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1944 spin_lock_bh(&sky2->phy_lock);
1945 sky2_phy_power_down(hw, port);
1946 spin_unlock_bh(&sky2->phy_lock);
1948 sky2_tx_reset(hw, port);
1950 /* Free any pending frames stuck in HW queue */
1951 sky2_tx_complete(sky2, sky2->tx_prod);
1954 /* Network shutdown */
1955 static int sky2_down(struct net_device *dev)
1957 struct sky2_port *sky2 = netdev_priv(dev);
1958 struct sky2_hw *hw = sky2->hw;
1960 /* Never really got started! */
1964 if (netif_msg_ifdown(sky2))
1965 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1967 /* Disable port IRQ */
1968 sky2_write32(hw, B0_IMSK,
1969 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
1970 sky2_read32(hw, B0_IMSK);
1972 synchronize_irq(hw->pdev->irq);
1973 napi_synchronize(&hw->napi);
1977 sky2_free_buffers(sky2);
1982 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1984 if (hw->flags & SKY2_HW_FIBRE_PHY)
1987 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1988 if (aux & PHY_M_PS_SPEED_100)
1994 switch (aux & PHY_M_PS_SPEED_MSK) {
1995 case PHY_M_PS_SPEED_1000:
1997 case PHY_M_PS_SPEED_100:
2004 static void sky2_link_up(struct sky2_port *sky2)
2006 struct sky2_hw *hw = sky2->hw;
2007 unsigned port = sky2->port;
2009 static const char *fc_name[] = {
2017 reg = gma_read16(hw, port, GM_GP_CTRL);
2018 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2019 gma_write16(hw, port, GM_GP_CTRL, reg);
2021 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2023 netif_carrier_on(sky2->netdev);
2025 mod_timer(&hw->watchdog_timer, jiffies + 1);
2027 /* Turn on link LED */
2028 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2029 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2031 if (netif_msg_link(sky2))
2032 printk(KERN_INFO PFX
2033 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
2034 sky2->netdev->name, sky2->speed,
2035 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2036 fc_name[sky2->flow_status]);
2039 static void sky2_link_down(struct sky2_port *sky2)
2041 struct sky2_hw *hw = sky2->hw;
2042 unsigned port = sky2->port;
2045 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2047 reg = gma_read16(hw, port, GM_GP_CTRL);
2048 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2049 gma_write16(hw, port, GM_GP_CTRL, reg);
2051 netif_carrier_off(sky2->netdev);
2053 /* Turn off link LED */
2054 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2056 if (netif_msg_link(sky2))
2057 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2059 sky2_phy_init(hw, port);
2062 static enum flow_control sky2_flow(int rx, int tx)
2065 return tx ? FC_BOTH : FC_RX;
2067 return tx ? FC_TX : FC_NONE;
2070 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2072 struct sky2_hw *hw = sky2->hw;
2073 unsigned port = sky2->port;
2076 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2077 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2078 if (lpa & PHY_M_AN_RF) {
2079 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2083 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2084 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2085 sky2->netdev->name);
2089 sky2->speed = sky2_phy_speed(hw, aux);
2090 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2092 /* Since the pause result bits seem to in different positions on
2093 * different chips. look at registers.
2095 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2096 /* Shift for bits in fiber PHY */
2097 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2098 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2100 if (advert & ADVERTISE_1000XPAUSE)
2101 advert |= ADVERTISE_PAUSE_CAP;
2102 if (advert & ADVERTISE_1000XPSE_ASYM)
2103 advert |= ADVERTISE_PAUSE_ASYM;
2104 if (lpa & LPA_1000XPAUSE)
2105 lpa |= LPA_PAUSE_CAP;
2106 if (lpa & LPA_1000XPAUSE_ASYM)
2107 lpa |= LPA_PAUSE_ASYM;
2110 sky2->flow_status = FC_NONE;
2111 if (advert & ADVERTISE_PAUSE_CAP) {
2112 if (lpa & LPA_PAUSE_CAP)
2113 sky2->flow_status = FC_BOTH;
2114 else if (advert & ADVERTISE_PAUSE_ASYM)
2115 sky2->flow_status = FC_RX;
2116 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2117 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2118 sky2->flow_status = FC_TX;
2121 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2122 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2123 sky2->flow_status = FC_NONE;
2125 if (sky2->flow_status & FC_TX)
2126 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2128 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2133 /* Interrupt from PHY */
2134 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2136 struct net_device *dev = hw->dev[port];
2137 struct sky2_port *sky2 = netdev_priv(dev);
2138 u16 istatus, phystat;
2140 if (!netif_running(dev))
2143 spin_lock(&sky2->phy_lock);
2144 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2145 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2147 if (netif_msg_intr(sky2))
2148 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2149 sky2->netdev->name, istatus, phystat);
2151 if (istatus & PHY_M_IS_AN_COMPL) {
2152 if (sky2_autoneg_done(sky2, phystat) == 0)
2157 if (istatus & PHY_M_IS_LSP_CHANGE)
2158 sky2->speed = sky2_phy_speed(hw, phystat);
2160 if (istatus & PHY_M_IS_DUP_CHANGE)
2162 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2164 if (istatus & PHY_M_IS_LST_CHANGE) {
2165 if (phystat & PHY_M_PS_LINK_UP)
2168 sky2_link_down(sky2);
2171 spin_unlock(&sky2->phy_lock);
2174 /* Special quick link interrupt (Yukon-2 Optima only) */
2175 static void sky2_qlink_intr(struct sky2_hw *hw)
2177 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2182 imask = sky2_read32(hw, B0_IMSK);
2183 imask &= ~Y2_IS_PHY_QLNK;
2184 sky2_write32(hw, B0_IMSK, imask);
2186 /* reset PHY Link Detect */
2187 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2188 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2189 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2190 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2195 /* Transmit timeout is only called if we are running, carrier is up
2196 * and tx queue is full (stopped).
2198 static void sky2_tx_timeout(struct net_device *dev)
2200 struct sky2_port *sky2 = netdev_priv(dev);
2201 struct sky2_hw *hw = sky2->hw;
2203 if (netif_msg_timer(sky2))
2204 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2206 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2207 dev->name, sky2->tx_cons, sky2->tx_prod,
2208 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2209 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2211 /* can't restart safely under softirq */
2212 schedule_work(&hw->restart_work);
2215 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2217 struct sky2_port *sky2 = netdev_priv(dev);
2218 struct sky2_hw *hw = sky2->hw;
2219 unsigned port = sky2->port;
2224 /* MTU size outside the spec */
2225 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2228 /* MTU > 1500 on yukon FE and FE+ not allowed */
2229 if (new_mtu > ETH_DATA_LEN &&
2230 (hw->chip_id == CHIP_ID_YUKON_FE ||
2231 hw->chip_id == CHIP_ID_YUKON_FE_P))
2234 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2235 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2236 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2238 if (!netif_running(dev)) {
2243 imask = sky2_read32(hw, B0_IMSK);
2244 sky2_write32(hw, B0_IMSK, 0);
2246 dev->trans_start = jiffies; /* prevent tx timeout */
2247 netif_stop_queue(dev);
2248 napi_disable(&hw->napi);
2250 synchronize_irq(hw->pdev->irq);
2252 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2253 sky2_set_tx_stfwd(hw, port);
2255 ctl = gma_read16(hw, port, GM_GP_CTRL);
2256 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2258 sky2_rx_clean(sky2);
2262 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2263 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2265 if (dev->mtu > ETH_DATA_LEN)
2266 mode |= GM_SMOD_JUMBO_ENA;
2268 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2270 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2272 err = sky2_alloc_rx_skbs(sky2);
2274 sky2_rx_start(sky2);
2276 sky2_rx_clean(sky2);
2277 sky2_write32(hw, B0_IMSK, imask);
2279 sky2_read32(hw, B0_Y2_SP_LISR);
2280 napi_enable(&hw->napi);
2285 gma_write16(hw, port, GM_GP_CTRL, ctl);
2287 netif_wake_queue(dev);
2293 /* For small just reuse existing skb for next receive */
2294 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2295 const struct rx_ring_info *re,
2298 struct sk_buff *skb;
2300 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2302 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2303 length, PCI_DMA_FROMDEVICE);
2304 skb_copy_from_linear_data(re->skb, skb->data, length);
2305 skb->ip_summed = re->skb->ip_summed;
2306 skb->csum = re->skb->csum;
2307 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2308 length, PCI_DMA_FROMDEVICE);
2309 re->skb->ip_summed = CHECKSUM_NONE;
2310 skb_put(skb, length);
2315 /* Adjust length of skb with fragments to match received data */
2316 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2317 unsigned int length)
2322 /* put header into skb */
2323 size = min(length, hdr_space);
2328 num_frags = skb_shinfo(skb)->nr_frags;
2329 for (i = 0; i < num_frags; i++) {
2330 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2333 /* don't need this page */
2334 __free_page(frag->page);
2335 --skb_shinfo(skb)->nr_frags;
2337 size = min(length, (unsigned) PAGE_SIZE);
2340 skb->data_len += size;
2341 skb->truesize += size;
2348 /* Normal packet - take skb from ring element and put in a new one */
2349 static struct sk_buff *receive_new(struct sky2_port *sky2,
2350 struct rx_ring_info *re,
2351 unsigned int length)
2353 struct sk_buff *skb;
2354 struct rx_ring_info nre;
2355 unsigned hdr_space = sky2->rx_data_size;
2357 nre.skb = sky2_rx_alloc(sky2);
2358 if (unlikely(!nre.skb))
2361 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2365 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2366 prefetch(skb->data);
2369 if (skb_shinfo(skb)->nr_frags)
2370 skb_put_frags(skb, hdr_space, length);
2372 skb_put(skb, length);
2376 dev_kfree_skb(nre.skb);
2382 * Receive one packet.
2383 * For larger packets, get new buffer.
2385 static struct sk_buff *sky2_receive(struct net_device *dev,
2386 u16 length, u32 status)
2388 struct sky2_port *sky2 = netdev_priv(dev);
2389 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2390 struct sk_buff *skb = NULL;
2391 u16 count = (status & GMR_FS_LEN) >> 16;
2393 #ifdef SKY2_VLAN_TAG_USED
2394 /* Account for vlan tag */
2395 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2399 if (unlikely(netif_msg_rx_status(sky2)))
2400 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2401 dev->name, sky2->rx_next, status, length);
2403 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2404 prefetch(sky2->rx_ring + sky2->rx_next);
2406 /* This chip has hardware problems that generates bogus status.
2407 * So do only marginal checking and expect higher level protocols
2408 * to handle crap frames.
2410 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2411 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2415 if (status & GMR_FS_ANY_ERR)
2418 if (!(status & GMR_FS_RX_OK))
2421 /* if length reported by DMA does not match PHY, packet was truncated */
2422 if (length != count)
2426 if (length < copybreak)
2427 skb = receive_copy(sky2, re, length);
2429 skb = receive_new(sky2, re, length);
2431 dev->stats.rx_dropped += (skb == NULL);
2434 sky2_rx_submit(sky2, re);
2439 /* Truncation of overlength packets
2440 causes PHY length to not match MAC length */
2441 ++dev->stats.rx_length_errors;
2442 if (netif_msg_rx_err(sky2) && net_ratelimit())
2443 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2444 dev->name, status, length);
2448 ++dev->stats.rx_errors;
2449 if (status & GMR_FS_RX_FF_OV) {
2450 dev->stats.rx_over_errors++;
2454 if (netif_msg_rx_err(sky2) && net_ratelimit())
2455 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2456 dev->name, status, length);
2458 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2459 dev->stats.rx_length_errors++;
2460 if (status & GMR_FS_FRAGMENT)
2461 dev->stats.rx_frame_errors++;
2462 if (status & GMR_FS_CRC_ERR)
2463 dev->stats.rx_crc_errors++;
2468 /* Transmit complete */
2469 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2471 struct sky2_port *sky2 = netdev_priv(dev);
2473 if (netif_running(dev)) {
2474 sky2_tx_complete(sky2, last);
2476 /* Wake unless it's detached, and called e.g. from sky2_down() */
2477 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2478 netif_wake_queue(dev);
2482 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2483 u32 status, struct sk_buff *skb)
2485 #ifdef SKY2_VLAN_TAG_USED
2486 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2487 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2488 if (skb->ip_summed == CHECKSUM_NONE)
2489 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2491 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2496 if (skb->ip_summed == CHECKSUM_NONE)
2497 netif_receive_skb(skb);
2499 napi_gro_receive(&sky2->hw->napi, skb);
2502 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2503 unsigned packets, unsigned bytes)
2506 struct net_device *dev = hw->dev[port];
2508 dev->stats.rx_packets += packets;
2509 dev->stats.rx_bytes += bytes;
2510 dev->last_rx = jiffies;
2511 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2515 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2517 /* If this happens then driver assuming wrong format for chip type */
2518 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2520 /* Both checksum counters are programmed to start at
2521 * the same offset, so unless there is a problem they
2522 * should match. This failure is an early indication that
2523 * hardware receive checksumming won't work.
2525 if (likely((u16)(status >> 16) == (u16)status)) {
2526 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2527 skb->ip_summed = CHECKSUM_COMPLETE;
2528 skb->csum = le16_to_cpu(status);
2530 dev_notice(&sky2->hw->pdev->dev,
2531 "%s: receive checksum problem (status = %#x)\n",
2532 sky2->netdev->name, status);
2534 /* Disable checksum offload */
2535 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2536 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2541 /* Process status response ring */
2542 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2545 unsigned int total_bytes[2] = { 0 };
2546 unsigned int total_packets[2] = { 0 };
2550 struct sky2_port *sky2;
2551 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2553 struct net_device *dev;
2554 struct sk_buff *skb;
2557 u8 opcode = le->opcode;
2559 if (!(opcode & HW_OWNER))
2562 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2564 port = le->css & CSS_LINK_BIT;
2565 dev = hw->dev[port];
2566 sky2 = netdev_priv(dev);
2567 length = le16_to_cpu(le->length);
2568 status = le32_to_cpu(le->status);
2571 switch (opcode & ~HW_OWNER) {
2573 total_packets[port]++;
2574 total_bytes[port] += length;
2576 skb = sky2_receive(dev, length, status);
2580 /* This chip reports checksum status differently */
2581 if (hw->flags & SKY2_HW_NEW_LE) {
2582 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
2583 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2584 (le->css & CSS_TCPUDPCSOK))
2585 skb->ip_summed = CHECKSUM_UNNECESSARY;
2587 skb->ip_summed = CHECKSUM_NONE;
2590 skb->protocol = eth_type_trans(skb, dev);
2592 sky2_skb_rx(sky2, status, skb);
2594 /* Stop after net poll weight */
2595 if (++work_done >= to_do)
2599 #ifdef SKY2_VLAN_TAG_USED
2601 sky2->rx_tag = length;
2605 sky2->rx_tag = length;
2609 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2610 sky2_rx_checksum(sky2, status);
2614 /* TX index reports status for both ports */
2615 sky2_tx_done(hw->dev[0], status & 0xfff);
2617 sky2_tx_done(hw->dev[1],
2618 ((status >> 24) & 0xff)
2619 | (u16)(length & 0xf) << 8);
2623 if (net_ratelimit())
2624 printk(KERN_WARNING PFX
2625 "unknown status opcode 0x%x\n", opcode);
2627 } while (hw->st_idx != idx);
2629 /* Fully processed status ring so clear irq */
2630 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2633 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2634 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2639 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2641 struct net_device *dev = hw->dev[port];
2643 if (net_ratelimit())
2644 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2647 if (status & Y2_IS_PAR_RD1) {
2648 if (net_ratelimit())
2649 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2652 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2655 if (status & Y2_IS_PAR_WR1) {
2656 if (net_ratelimit())
2657 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2660 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2663 if (status & Y2_IS_PAR_MAC1) {
2664 if (net_ratelimit())
2665 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2666 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2669 if (status & Y2_IS_PAR_RX1) {
2670 if (net_ratelimit())
2671 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2672 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2675 if (status & Y2_IS_TCP_TXA1) {
2676 if (net_ratelimit())
2677 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2679 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2683 static void sky2_hw_intr(struct sky2_hw *hw)
2685 struct pci_dev *pdev = hw->pdev;
2686 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2687 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2691 if (status & Y2_IS_TIST_OV)
2692 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2694 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2697 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2698 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2699 if (net_ratelimit())
2700 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2703 sky2_pci_write16(hw, PCI_STATUS,
2704 pci_err | PCI_STATUS_ERROR_BITS);
2705 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2708 if (status & Y2_IS_PCI_EXP) {
2709 /* PCI-Express uncorrectable Error occurred */
2712 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2713 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2714 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2716 if (net_ratelimit())
2717 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2719 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2720 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2723 if (status & Y2_HWE_L1_MASK)
2724 sky2_hw_error(hw, 0, status);
2726 if (status & Y2_HWE_L1_MASK)
2727 sky2_hw_error(hw, 1, status);
2730 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2732 struct net_device *dev = hw->dev[port];
2733 struct sky2_port *sky2 = netdev_priv(dev);
2734 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2736 if (netif_msg_intr(sky2))
2737 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2740 if (status & GM_IS_RX_CO_OV)
2741 gma_read16(hw, port, GM_RX_IRQ_SRC);
2743 if (status & GM_IS_TX_CO_OV)
2744 gma_read16(hw, port, GM_TX_IRQ_SRC);
2746 if (status & GM_IS_RX_FF_OR) {
2747 ++dev->stats.rx_fifo_errors;
2748 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2751 if (status & GM_IS_TX_FF_UR) {
2752 ++dev->stats.tx_fifo_errors;
2753 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2757 /* This should never happen it is a bug. */
2758 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2760 struct net_device *dev = hw->dev[port];
2761 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2763 dev_err(&hw->pdev->dev, PFX
2764 "%s: descriptor error q=%#x get=%u put=%u\n",
2765 dev->name, (unsigned) q, (unsigned) idx,
2766 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2768 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2771 static int sky2_rx_hung(struct net_device *dev)
2773 struct sky2_port *sky2 = netdev_priv(dev);
2774 struct sky2_hw *hw = sky2->hw;
2775 unsigned port = sky2->port;
2776 unsigned rxq = rxqaddr[port];
2777 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2778 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2779 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2780 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2782 /* If idle and MAC or PCI is stuck */
2783 if (sky2->check.last == dev->last_rx &&
2784 ((mac_rp == sky2->check.mac_rp &&
2785 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2786 /* Check if the PCI RX hang */
2787 (fifo_rp == sky2->check.fifo_rp &&
2788 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2789 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2790 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2791 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2794 sky2->check.last = dev->last_rx;
2795 sky2->check.mac_rp = mac_rp;
2796 sky2->check.mac_lev = mac_lev;
2797 sky2->check.fifo_rp = fifo_rp;
2798 sky2->check.fifo_lev = fifo_lev;
2803 static void sky2_watchdog(unsigned long arg)
2805 struct sky2_hw *hw = (struct sky2_hw *) arg;
2807 /* Check for lost IRQ once a second */
2808 if (sky2_read32(hw, B0_ISRC)) {
2809 napi_schedule(&hw->napi);
2813 for (i = 0; i < hw->ports; i++) {
2814 struct net_device *dev = hw->dev[i];
2815 if (!netif_running(dev))
2819 /* For chips with Rx FIFO, check if stuck */
2820 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2821 sky2_rx_hung(dev)) {
2822 pr_info(PFX "%s: receiver hang detected\n",
2824 schedule_work(&hw->restart_work);
2833 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2836 /* Hardware/software error handling */
2837 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2839 if (net_ratelimit())
2840 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2842 if (status & Y2_IS_HW_ERR)
2845 if (status & Y2_IS_IRQ_MAC1)
2846 sky2_mac_intr(hw, 0);
2848 if (status & Y2_IS_IRQ_MAC2)
2849 sky2_mac_intr(hw, 1);
2851 if (status & Y2_IS_CHK_RX1)
2852 sky2_le_error(hw, 0, Q_R1);
2854 if (status & Y2_IS_CHK_RX2)
2855 sky2_le_error(hw, 1, Q_R2);
2857 if (status & Y2_IS_CHK_TXA1)
2858 sky2_le_error(hw, 0, Q_XA1);
2860 if (status & Y2_IS_CHK_TXA2)
2861 sky2_le_error(hw, 1, Q_XA2);
2864 static int sky2_poll(struct napi_struct *napi, int work_limit)
2866 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2867 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2871 if (unlikely(status & Y2_IS_ERROR))
2872 sky2_err_intr(hw, status);
2874 if (status & Y2_IS_IRQ_PHY1)
2875 sky2_phy_intr(hw, 0);
2877 if (status & Y2_IS_IRQ_PHY2)
2878 sky2_phy_intr(hw, 1);
2880 if (status & Y2_IS_PHY_QLNK)
2881 sky2_qlink_intr(hw);
2883 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2884 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2886 if (work_done >= work_limit)
2890 napi_complete(napi);
2891 sky2_read32(hw, B0_Y2_SP_LISR);
2897 static irqreturn_t sky2_intr(int irq, void *dev_id)
2899 struct sky2_hw *hw = dev_id;
2902 /* Reading this mask interrupts as side effect */
2903 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2904 if (status == 0 || status == ~0)
2907 prefetch(&hw->st_le[hw->st_idx]);
2909 napi_schedule(&hw->napi);
2914 #ifdef CONFIG_NET_POLL_CONTROLLER
2915 static void sky2_netpoll(struct net_device *dev)
2917 struct sky2_port *sky2 = netdev_priv(dev);
2919 napi_schedule(&sky2->hw->napi);
2923 /* Chip internal frequency for clock calculations */
2924 static u32 sky2_mhz(const struct sky2_hw *hw)
2926 switch (hw->chip_id) {
2927 case CHIP_ID_YUKON_EC:
2928 case CHIP_ID_YUKON_EC_U:
2929 case CHIP_ID_YUKON_EX:
2930 case CHIP_ID_YUKON_SUPR:
2931 case CHIP_ID_YUKON_UL_2:
2932 case CHIP_ID_YUKON_OPT:
2935 case CHIP_ID_YUKON_FE:
2938 case CHIP_ID_YUKON_FE_P:
2941 case CHIP_ID_YUKON_XL:
2949 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2951 return sky2_mhz(hw) * us;
2954 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2956 return clk / sky2_mhz(hw);
2960 static int __devinit sky2_init(struct sky2_hw *hw)
2964 /* Enable all clocks and check for bad PCI access */
2965 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2967 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2969 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2970 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2972 switch(hw->chip_id) {
2973 case CHIP_ID_YUKON_XL:
2974 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2977 case CHIP_ID_YUKON_EC_U:
2978 hw->flags = SKY2_HW_GIGABIT
2980 | SKY2_HW_ADV_POWER_CTL;
2983 case CHIP_ID_YUKON_EX:
2984 hw->flags = SKY2_HW_GIGABIT
2987 | SKY2_HW_ADV_POWER_CTL;
2989 /* New transmit checksum */
2990 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2991 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2994 case CHIP_ID_YUKON_EC:
2995 /* This rev is really old, and requires untested workarounds */
2996 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2997 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3000 hw->flags = SKY2_HW_GIGABIT;
3003 case CHIP_ID_YUKON_FE:
3006 case CHIP_ID_YUKON_FE_P:
3007 hw->flags = SKY2_HW_NEWER_PHY
3009 | SKY2_HW_AUTO_TX_SUM
3010 | SKY2_HW_ADV_POWER_CTL;
3013 case CHIP_ID_YUKON_SUPR:
3014 hw->flags = SKY2_HW_GIGABIT
3017 | SKY2_HW_AUTO_TX_SUM
3018 | SKY2_HW_ADV_POWER_CTL;
3021 case CHIP_ID_YUKON_UL_2:
3022 hw->flags = SKY2_HW_GIGABIT
3023 | SKY2_HW_ADV_POWER_CTL;
3026 case CHIP_ID_YUKON_OPT:
3027 hw->flags = SKY2_HW_GIGABIT
3029 | SKY2_HW_ADV_POWER_CTL;
3033 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3038 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3039 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3040 hw->flags |= SKY2_HW_FIBRE_PHY;
3043 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3044 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3045 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3049 if (sky2_read8(hw, B2_E_0))
3050 hw->flags |= SKY2_HW_RAM_BUFFER;
3055 static void sky2_reset(struct sky2_hw *hw)
3057 struct pci_dev *pdev = hw->pdev;
3060 u32 hwe_mask = Y2_HWE_ALL_MASK;
3063 if (hw->chip_id == CHIP_ID_YUKON_EX
3064 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3065 sky2_write32(hw, CPU_WDOG, 0);
3066 status = sky2_read16(hw, HCU_CCSR);
3067 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3068 HCU_CCSR_UC_STATE_MSK);
3070 * CPU clock divider shouldn't be used because
3071 * - ASF firmware may malfunction
3072 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3074 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3075 sky2_write16(hw, HCU_CCSR, status);
3076 sky2_write32(hw, CPU_WDOG, 0);
3078 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3079 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3082 sky2_write8(hw, B0_CTST, CS_RST_SET);
3083 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3085 /* allow writes to PCI config */
3086 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3088 /* clear PCI errors, if any */
3089 status = sky2_pci_read16(hw, PCI_STATUS);
3090 status |= PCI_STATUS_ERROR_BITS;
3091 sky2_pci_write16(hw, PCI_STATUS, status);
3093 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3095 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3097 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3100 /* If error bit is stuck on ignore it */
3101 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3102 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3104 hwe_mask |= Y2_IS_PCI_EXP;
3108 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3110 for (i = 0; i < hw->ports; i++) {
3111 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3112 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3114 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3115 hw->chip_id == CHIP_ID_YUKON_SUPR)
3116 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3117 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3122 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3123 /* enable MACSec clock gating */
3124 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3127 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3131 if (hw->chip_rev == 0) {
3132 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3133 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3135 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3138 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3142 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3144 /* reset PHY Link Detect */
3145 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3146 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3147 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3148 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3151 /* enable PHY Quick Link */
3152 msk = sky2_read32(hw, B0_IMSK);
3153 msk |= Y2_IS_PHY_QLNK;
3154 sky2_write32(hw, B0_IMSK, msk);
3156 /* check if PSMv2 was running before */
3157 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3158 if (reg & PCI_EXP_LNKCTL_ASPMC) {
3159 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3160 /* restore the PCIe Link Control register */
3161 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3163 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3165 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3166 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3169 /* Clear I2C IRQ noise */
3170 sky2_write32(hw, B2_I2C_IRQ, 1);
3172 /* turn off hardware timer (unused) */
3173 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3174 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3176 /* Turn off descriptor polling */
3177 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3179 /* Turn off receive timestamp */
3180 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3181 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3183 /* enable the Tx Arbiters */
3184 for (i = 0; i < hw->ports; i++)
3185 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3187 /* Initialize ram interface */
3188 for (i = 0; i < hw->ports; i++) {
3189 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3191 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3192 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3193 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3194 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3195 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3196 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3197 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3198 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3199 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3200 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3201 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3202 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3205 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3207 for (i = 0; i < hw->ports; i++)
3208 sky2_gmac_reset(hw, i);
3210 memset(hw->st_le, 0, STATUS_LE_BYTES);
3213 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3214 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3216 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3217 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3219 /* Set the list last index */
3220 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3222 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3223 sky2_write8(hw, STAT_FIFO_WM, 16);
3225 /* set Status-FIFO ISR watermark */
3226 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3227 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3229 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3231 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3232 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3233 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3235 /* enable status unit */
3236 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3238 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3239 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3240 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3243 /* Take device down (offline).
3244 * Equivalent to doing dev_stop() but this does not
3245 * inform upper layers of the transistion.
3247 static void sky2_detach(struct net_device *dev)
3249 if (netif_running(dev)) {
3251 netif_device_detach(dev); /* stop txq */
3252 netif_tx_unlock(dev);
3257 /* Bring device back after doing sky2_detach */
3258 static int sky2_reattach(struct net_device *dev)
3262 if (netif_running(dev)) {
3265 printk(KERN_INFO PFX "%s: could not restart %d\n",
3269 netif_device_attach(dev);
3270 sky2_set_multicast(dev);
3277 static void sky2_restart(struct work_struct *work)
3279 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3285 napi_disable(&hw->napi);
3286 synchronize_irq(hw->pdev->irq);
3287 imask = sky2_read32(hw, B0_IMSK);
3288 sky2_write32(hw, B0_IMSK, 0);
3290 for (i = 0; i < hw->ports; i++) {
3291 struct net_device *dev = hw->dev[i];
3292 struct sky2_port *sky2 = netdev_priv(dev);
3294 if (!netif_running(dev))
3297 netif_carrier_off(dev);
3298 netif_tx_disable(dev);
3304 for (i = 0; i < hw->ports; i++) {
3305 struct net_device *dev = hw->dev[i];
3306 struct sky2_port *sky2 = netdev_priv(dev);
3308 if (!netif_running(dev))
3312 netif_wake_queue(dev);
3315 sky2_write32(hw, B0_IMSK, imask);
3316 sky2_read32(hw, B0_IMSK);
3318 sky2_read32(hw, B0_Y2_SP_LISR);
3319 napi_enable(&hw->napi);
3324 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3326 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3329 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3331 const struct sky2_port *sky2 = netdev_priv(dev);
3333 wol->supported = sky2_wol_supported(sky2->hw);
3334 wol->wolopts = sky2->wol;
3337 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3339 struct sky2_port *sky2 = netdev_priv(dev);
3340 struct sky2_hw *hw = sky2->hw;
3342 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3343 !device_can_wakeup(&hw->pdev->dev))
3346 sky2->wol = wol->wolopts;
3350 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3352 if (sky2_is_copper(hw)) {
3353 u32 modes = SUPPORTED_10baseT_Half
3354 | SUPPORTED_10baseT_Full
3355 | SUPPORTED_100baseT_Half
3356 | SUPPORTED_100baseT_Full
3357 | SUPPORTED_Autoneg | SUPPORTED_TP;
3359 if (hw->flags & SKY2_HW_GIGABIT)
3360 modes |= SUPPORTED_1000baseT_Half
3361 | SUPPORTED_1000baseT_Full;
3364 return SUPPORTED_1000baseT_Half
3365 | SUPPORTED_1000baseT_Full
3370 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3372 struct sky2_port *sky2 = netdev_priv(dev);
3373 struct sky2_hw *hw = sky2->hw;
3375 ecmd->transceiver = XCVR_INTERNAL;
3376 ecmd->supported = sky2_supported_modes(hw);
3377 ecmd->phy_address = PHY_ADDR_MARV;
3378 if (sky2_is_copper(hw)) {
3379 ecmd->port = PORT_TP;
3380 ecmd->speed = sky2->speed;
3382 ecmd->speed = SPEED_1000;
3383 ecmd->port = PORT_FIBRE;
3386 ecmd->advertising = sky2->advertising;
3387 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3388 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3389 ecmd->duplex = sky2->duplex;
3393 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3395 struct sky2_port *sky2 = netdev_priv(dev);
3396 const struct sky2_hw *hw = sky2->hw;
3397 u32 supported = sky2_supported_modes(hw);
3399 if (ecmd->autoneg == AUTONEG_ENABLE) {
3400 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3401 ecmd->advertising = supported;
3407 switch (ecmd->speed) {
3409 if (ecmd->duplex == DUPLEX_FULL)
3410 setting = SUPPORTED_1000baseT_Full;
3411 else if (ecmd->duplex == DUPLEX_HALF)
3412 setting = SUPPORTED_1000baseT_Half;
3417 if (ecmd->duplex == DUPLEX_FULL)
3418 setting = SUPPORTED_100baseT_Full;
3419 else if (ecmd->duplex == DUPLEX_HALF)
3420 setting = SUPPORTED_100baseT_Half;
3426 if (ecmd->duplex == DUPLEX_FULL)
3427 setting = SUPPORTED_10baseT_Full;
3428 else if (ecmd->duplex == DUPLEX_HALF)
3429 setting = SUPPORTED_10baseT_Half;
3437 if ((setting & supported) == 0)
3440 sky2->speed = ecmd->speed;
3441 sky2->duplex = ecmd->duplex;
3442 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3445 sky2->advertising = ecmd->advertising;
3447 if (netif_running(dev)) {
3448 sky2_phy_reinit(sky2);
3449 sky2_set_multicast(dev);
3455 static void sky2_get_drvinfo(struct net_device *dev,
3456 struct ethtool_drvinfo *info)
3458 struct sky2_port *sky2 = netdev_priv(dev);
3460 strcpy(info->driver, DRV_NAME);
3461 strcpy(info->version, DRV_VERSION);
3462 strcpy(info->fw_version, "N/A");
3463 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3466 static const struct sky2_stat {
3467 char name[ETH_GSTRING_LEN];
3470 { "tx_bytes", GM_TXO_OK_HI },
3471 { "rx_bytes", GM_RXO_OK_HI },
3472 { "tx_broadcast", GM_TXF_BC_OK },
3473 { "rx_broadcast", GM_RXF_BC_OK },
3474 { "tx_multicast", GM_TXF_MC_OK },
3475 { "rx_multicast", GM_RXF_MC_OK },
3476 { "tx_unicast", GM_TXF_UC_OK },
3477 { "rx_unicast", GM_RXF_UC_OK },
3478 { "tx_mac_pause", GM_TXF_MPAUSE },
3479 { "rx_mac_pause", GM_RXF_MPAUSE },
3480 { "collisions", GM_TXF_COL },
3481 { "late_collision",GM_TXF_LAT_COL },
3482 { "aborted", GM_TXF_ABO_COL },
3483 { "single_collisions", GM_TXF_SNG_COL },
3484 { "multi_collisions", GM_TXF_MUL_COL },
3486 { "rx_short", GM_RXF_SHT },
3487 { "rx_runt", GM_RXE_FRAG },
3488 { "rx_64_byte_packets", GM_RXF_64B },
3489 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3490 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3491 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3492 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3493 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3494 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3495 { "rx_too_long", GM_RXF_LNG_ERR },
3496 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3497 { "rx_jabber", GM_RXF_JAB_PKT },
3498 { "rx_fcs_error", GM_RXF_FCS_ERR },
3500 { "tx_64_byte_packets", GM_TXF_64B },
3501 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3502 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3503 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3504 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3505 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3506 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3507 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3510 static u32 sky2_get_rx_csum(struct net_device *dev)
3512 struct sky2_port *sky2 = netdev_priv(dev);
3514 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
3517 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3519 struct sky2_port *sky2 = netdev_priv(dev);
3522 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3524 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
3526 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3527 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3532 static u32 sky2_get_msglevel(struct net_device *netdev)
3534 struct sky2_port *sky2 = netdev_priv(netdev);
3535 return sky2->msg_enable;
3538 static int sky2_nway_reset(struct net_device *dev)
3540 struct sky2_port *sky2 = netdev_priv(dev);
3542 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3545 sky2_phy_reinit(sky2);
3546 sky2_set_multicast(dev);
3551 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3553 struct sky2_hw *hw = sky2->hw;
3554 unsigned port = sky2->port;
3557 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3558 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3559 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3560 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3562 for (i = 2; i < count; i++)
3563 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3566 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3568 struct sky2_port *sky2 = netdev_priv(netdev);
3569 sky2->msg_enable = value;
3572 static int sky2_get_sset_count(struct net_device *dev, int sset)
3576 return ARRAY_SIZE(sky2_stats);
3582 static void sky2_get_ethtool_stats(struct net_device *dev,
3583 struct ethtool_stats *stats, u64 * data)
3585 struct sky2_port *sky2 = netdev_priv(dev);
3587 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3590 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3594 switch (stringset) {
3596 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3597 memcpy(data + i * ETH_GSTRING_LEN,
3598 sky2_stats[i].name, ETH_GSTRING_LEN);
3603 static int sky2_set_mac_address(struct net_device *dev, void *p)
3605 struct sky2_port *sky2 = netdev_priv(dev);
3606 struct sky2_hw *hw = sky2->hw;
3607 unsigned port = sky2->port;
3608 const struct sockaddr *addr = p;
3610 if (!is_valid_ether_addr(addr->sa_data))
3611 return -EADDRNOTAVAIL;
3613 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3614 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3615 dev->dev_addr, ETH_ALEN);
3616 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3617 dev->dev_addr, ETH_ALEN);
3619 /* virtual address for data */
3620 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3622 /* physical address: used for pause frames */
3623 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3628 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3632 bit = ether_crc(ETH_ALEN, addr) & 63;
3633 filter[bit >> 3] |= 1 << (bit & 7);
3636 static void sky2_set_multicast(struct net_device *dev)
3638 struct sky2_port *sky2 = netdev_priv(dev);
3639 struct sky2_hw *hw = sky2->hw;
3640 unsigned port = sky2->port;
3641 struct dev_mc_list *list = dev->mc_list;
3645 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3647 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3648 memset(filter, 0, sizeof(filter));
3650 reg = gma_read16(hw, port, GM_RX_CTRL);
3651 reg |= GM_RXCR_UCF_ENA;
3653 if (dev->flags & IFF_PROMISC) /* promiscuous */
3654 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3655 else if (dev->flags & IFF_ALLMULTI)
3656 memset(filter, 0xff, sizeof(filter));
3657 else if (netdev_mc_empty(dev) && !rx_pause)
3658 reg &= ~GM_RXCR_MCF_ENA;
3661 reg |= GM_RXCR_MCF_ENA;
3664 sky2_add_filter(filter, pause_mc_addr);
3666 for (i = 0; list && i < netdev_mc_count(dev); i++, list = list->next)
3667 sky2_add_filter(filter, list->dmi_addr);
3670 gma_write16(hw, port, GM_MC_ADDR_H1,
3671 (u16) filter[0] | ((u16) filter[1] << 8));
3672 gma_write16(hw, port, GM_MC_ADDR_H2,
3673 (u16) filter[2] | ((u16) filter[3] << 8));
3674 gma_write16(hw, port, GM_MC_ADDR_H3,
3675 (u16) filter[4] | ((u16) filter[5] << 8));
3676 gma_write16(hw, port, GM_MC_ADDR_H4,
3677 (u16) filter[6] | ((u16) filter[7] << 8));
3679 gma_write16(hw, port, GM_RX_CTRL, reg);
3682 /* Can have one global because blinking is controlled by
3683 * ethtool and that is always under RTNL mutex
3685 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3687 struct sky2_hw *hw = sky2->hw;
3688 unsigned port = sky2->port;
3690 spin_lock_bh(&sky2->phy_lock);
3691 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3692 hw->chip_id == CHIP_ID_YUKON_EX ||
3693 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3695 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3696 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3700 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3701 PHY_M_LEDC_LOS_CTRL(8) |
3702 PHY_M_LEDC_INIT_CTRL(8) |
3703 PHY_M_LEDC_STA1_CTRL(8) |
3704 PHY_M_LEDC_STA0_CTRL(8));
3707 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3708 PHY_M_LEDC_LOS_CTRL(9) |
3709 PHY_M_LEDC_INIT_CTRL(9) |
3710 PHY_M_LEDC_STA1_CTRL(9) |
3711 PHY_M_LEDC_STA0_CTRL(9));
3714 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3715 PHY_M_LEDC_LOS_CTRL(0xa) |
3716 PHY_M_LEDC_INIT_CTRL(0xa) |
3717 PHY_M_LEDC_STA1_CTRL(0xa) |
3718 PHY_M_LEDC_STA0_CTRL(0xa));
3721 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3722 PHY_M_LEDC_LOS_CTRL(1) |
3723 PHY_M_LEDC_INIT_CTRL(8) |
3724 PHY_M_LEDC_STA1_CTRL(7) |
3725 PHY_M_LEDC_STA0_CTRL(7));
3728 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3730 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3731 PHY_M_LED_MO_DUP(mode) |
3732 PHY_M_LED_MO_10(mode) |
3733 PHY_M_LED_MO_100(mode) |
3734 PHY_M_LED_MO_1000(mode) |
3735 PHY_M_LED_MO_RX(mode) |
3736 PHY_M_LED_MO_TX(mode));
3738 spin_unlock_bh(&sky2->phy_lock);
3741 /* blink LED's for finding board */
3742 static int sky2_phys_id(struct net_device *dev, u32 data)
3744 struct sky2_port *sky2 = netdev_priv(dev);
3750 for (i = 0; i < data; i++) {
3751 sky2_led(sky2, MO_LED_ON);
3752 if (msleep_interruptible(500))
3754 sky2_led(sky2, MO_LED_OFF);
3755 if (msleep_interruptible(500))
3758 sky2_led(sky2, MO_LED_NORM);
3763 static void sky2_get_pauseparam(struct net_device *dev,
3764 struct ethtool_pauseparam *ecmd)
3766 struct sky2_port *sky2 = netdev_priv(dev);
3768 switch (sky2->flow_mode) {
3770 ecmd->tx_pause = ecmd->rx_pause = 0;
3773 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3776 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3779 ecmd->tx_pause = ecmd->rx_pause = 1;
3782 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3783 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3786 static int sky2_set_pauseparam(struct net_device *dev,
3787 struct ethtool_pauseparam *ecmd)
3789 struct sky2_port *sky2 = netdev_priv(dev);
3791 if (ecmd->autoneg == AUTONEG_ENABLE)
3792 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3794 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3796 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3798 if (netif_running(dev))
3799 sky2_phy_reinit(sky2);
3804 static int sky2_get_coalesce(struct net_device *dev,
3805 struct ethtool_coalesce *ecmd)
3807 struct sky2_port *sky2 = netdev_priv(dev);
3808 struct sky2_hw *hw = sky2->hw;
3810 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3811 ecmd->tx_coalesce_usecs = 0;
3813 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3814 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3816 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3818 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3819 ecmd->rx_coalesce_usecs = 0;
3821 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3822 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3824 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3826 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3827 ecmd->rx_coalesce_usecs_irq = 0;
3829 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3830 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3833 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3838 /* Note: this affect both ports */
3839 static int sky2_set_coalesce(struct net_device *dev,
3840 struct ethtool_coalesce *ecmd)
3842 struct sky2_port *sky2 = netdev_priv(dev);
3843 struct sky2_hw *hw = sky2->hw;
3844 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3846 if (ecmd->tx_coalesce_usecs > tmax ||
3847 ecmd->rx_coalesce_usecs > tmax ||
3848 ecmd->rx_coalesce_usecs_irq > tmax)
3851 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3853 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3855 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3858 if (ecmd->tx_coalesce_usecs == 0)
3859 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3861 sky2_write32(hw, STAT_TX_TIMER_INI,
3862 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3863 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3865 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3867 if (ecmd->rx_coalesce_usecs == 0)
3868 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3870 sky2_write32(hw, STAT_LEV_TIMER_INI,
3871 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3872 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3874 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3876 if (ecmd->rx_coalesce_usecs_irq == 0)
3877 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3879 sky2_write32(hw, STAT_ISR_TIMER_INI,
3880 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3881 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3883 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3887 static void sky2_get_ringparam(struct net_device *dev,
3888 struct ethtool_ringparam *ering)
3890 struct sky2_port *sky2 = netdev_priv(dev);
3892 ering->rx_max_pending = RX_MAX_PENDING;
3893 ering->rx_mini_max_pending = 0;
3894 ering->rx_jumbo_max_pending = 0;
3895 ering->tx_max_pending = TX_MAX_PENDING;
3897 ering->rx_pending = sky2->rx_pending;
3898 ering->rx_mini_pending = 0;
3899 ering->rx_jumbo_pending = 0;
3900 ering->tx_pending = sky2->tx_pending;
3903 static int sky2_set_ringparam(struct net_device *dev,
3904 struct ethtool_ringparam *ering)
3906 struct sky2_port *sky2 = netdev_priv(dev);
3908 if (ering->rx_pending > RX_MAX_PENDING ||
3909 ering->rx_pending < 8 ||
3910 ering->tx_pending < TX_MIN_PENDING ||
3911 ering->tx_pending > TX_MAX_PENDING)
3916 sky2->rx_pending = ering->rx_pending;
3917 sky2->tx_pending = ering->tx_pending;
3918 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3920 return sky2_reattach(dev);
3923 static int sky2_get_regs_len(struct net_device *dev)
3928 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3930 /* This complicated switch statement is to make sure and
3931 * only access regions that are unreserved.
3932 * Some blocks are only valid on dual port cards.
3936 case 5: /* Tx Arbiter 2 */
3938 case 14 ... 15: /* TX2 */
3939 case 17: case 19: /* Ram Buffer 2 */
3940 case 22 ... 23: /* Tx Ram Buffer 2 */
3941 case 25: /* Rx MAC Fifo 1 */
3942 case 27: /* Tx MAC Fifo 2 */
3943 case 31: /* GPHY 2 */
3944 case 40 ... 47: /* Pattern Ram 2 */
3945 case 52: case 54: /* TCP Segmentation 2 */
3946 case 112 ... 116: /* GMAC 2 */
3947 return hw->ports > 1;
3949 case 0: /* Control */
3950 case 2: /* Mac address */
3951 case 4: /* Tx Arbiter 1 */
3952 case 7: /* PCI express reg */
3954 case 12 ... 13: /* TX1 */
3955 case 16: case 18:/* Rx Ram Buffer 1 */
3956 case 20 ... 21: /* Tx Ram Buffer 1 */
3957 case 24: /* Rx MAC Fifo 1 */
3958 case 26: /* Tx MAC Fifo 1 */
3959 case 28 ... 29: /* Descriptor and status unit */
3960 case 30: /* GPHY 1*/
3961 case 32 ... 39: /* Pattern Ram 1 */
3962 case 48: case 50: /* TCP Segmentation 1 */
3963 case 56 ... 60: /* PCI space */
3964 case 80 ... 84: /* GMAC 1 */
3973 * Returns copy of control register region
3974 * Note: ethtool_get_regs always provides full size (16k) buffer
3976 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3979 const struct sky2_port *sky2 = netdev_priv(dev);
3980 const void __iomem *io = sky2->hw->regs;
3985 for (b = 0; b < 128; b++) {
3986 /* skip poisonous diagnostic ram region in block 3 */
3988 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3989 else if (sky2_reg_access_ok(sky2->hw, b))
3990 memcpy_fromio(p, io, 128);
3999 /* In order to do Jumbo packets on these chips, need to turn off the
4000 * transmit store/forward. Therefore checksum offload won't work.
4002 static int no_tx_offload(struct net_device *dev)
4004 const struct sky2_port *sky2 = netdev_priv(dev);
4005 const struct sky2_hw *hw = sky2->hw;
4007 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
4010 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
4012 if (data && no_tx_offload(dev))
4015 return ethtool_op_set_tx_csum(dev, data);
4019 static int sky2_set_tso(struct net_device *dev, u32 data)
4021 if (data && no_tx_offload(dev))
4024 return ethtool_op_set_tso(dev, data);
4027 static int sky2_get_eeprom_len(struct net_device *dev)
4029 struct sky2_port *sky2 = netdev_priv(dev);
4030 struct sky2_hw *hw = sky2->hw;
4033 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4034 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4037 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4039 unsigned long start = jiffies;
4041 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4042 /* Can take up to 10.6 ms for write */
4043 if (time_after(jiffies, start + HZ/4)) {
4044 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
4053 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4054 u16 offset, size_t length)
4058 while (length > 0) {
4061 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4062 rc = sky2_vpd_wait(hw, cap, 0);
4066 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4068 memcpy(data, &val, min(sizeof(val), length));
4069 offset += sizeof(u32);
4070 data += sizeof(u32);
4071 length -= sizeof(u32);
4077 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4078 u16 offset, unsigned int length)
4083 for (i = 0; i < length; i += sizeof(u32)) {
4084 u32 val = *(u32 *)(data + i);
4086 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4087 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4089 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4096 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4099 struct sky2_port *sky2 = netdev_priv(dev);
4100 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4105 eeprom->magic = SKY2_EEPROM_MAGIC;
4107 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4110 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4113 struct sky2_port *sky2 = netdev_priv(dev);
4114 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4119 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4122 /* Partial writes not supported */
4123 if ((eeprom->offset & 3) || (eeprom->len & 3))
4126 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4130 static const struct ethtool_ops sky2_ethtool_ops = {
4131 .get_settings = sky2_get_settings,
4132 .set_settings = sky2_set_settings,
4133 .get_drvinfo = sky2_get_drvinfo,
4134 .get_wol = sky2_get_wol,
4135 .set_wol = sky2_set_wol,
4136 .get_msglevel = sky2_get_msglevel,
4137 .set_msglevel = sky2_set_msglevel,
4138 .nway_reset = sky2_nway_reset,
4139 .get_regs_len = sky2_get_regs_len,
4140 .get_regs = sky2_get_regs,
4141 .get_link = ethtool_op_get_link,
4142 .get_eeprom_len = sky2_get_eeprom_len,
4143 .get_eeprom = sky2_get_eeprom,
4144 .set_eeprom = sky2_set_eeprom,
4145 .set_sg = ethtool_op_set_sg,
4146 .set_tx_csum = sky2_set_tx_csum,
4147 .set_tso = sky2_set_tso,
4148 .get_rx_csum = sky2_get_rx_csum,
4149 .set_rx_csum = sky2_set_rx_csum,
4150 .get_strings = sky2_get_strings,
4151 .get_coalesce = sky2_get_coalesce,
4152 .set_coalesce = sky2_set_coalesce,
4153 .get_ringparam = sky2_get_ringparam,
4154 .set_ringparam = sky2_set_ringparam,
4155 .get_pauseparam = sky2_get_pauseparam,
4156 .set_pauseparam = sky2_set_pauseparam,
4157 .phys_id = sky2_phys_id,
4158 .get_sset_count = sky2_get_sset_count,
4159 .get_ethtool_stats = sky2_get_ethtool_stats,
4162 #ifdef CONFIG_SKY2_DEBUG
4164 static struct dentry *sky2_debug;
4168 * Read and parse the first part of Vital Product Data
4170 #define VPD_SIZE 128
4171 #define VPD_MAGIC 0x82
4173 static const struct vpd_tag {
4177 { "PN", "Part Number" },
4178 { "EC", "Engineering Level" },
4179 { "MN", "Manufacturer" },
4180 { "SN", "Serial Number" },
4181 { "YA", "Asset Tag" },
4182 { "VL", "First Error Log Message" },
4183 { "VF", "Second Error Log Message" },
4184 { "VB", "Boot Agent ROM Configuration" },
4185 { "VE", "EFI UNDI Configuration" },
4188 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4196 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4197 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4199 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4200 buf = kmalloc(vpd_size, GFP_KERNEL);
4202 seq_puts(seq, "no memory!\n");
4206 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4207 seq_puts(seq, "VPD read failed\n");
4211 if (buf[0] != VPD_MAGIC) {
4212 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4216 if (len == 0 || len > vpd_size - 4) {
4217 seq_printf(seq, "Invalid id length: %d\n", len);
4221 seq_printf(seq, "%.*s\n", len, buf + 3);
4224 while (offs < vpd_size - 4) {
4227 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4229 len = buf[offs + 2];
4230 if (offs + len + 3 >= vpd_size)
4233 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4234 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4235 seq_printf(seq, " %s: %.*s\n",
4236 vpd_tags[i].label, len, buf + offs + 3);
4246 static int sky2_debug_show(struct seq_file *seq, void *v)
4248 struct net_device *dev = seq->private;
4249 const struct sky2_port *sky2 = netdev_priv(dev);
4250 struct sky2_hw *hw = sky2->hw;
4251 unsigned port = sky2->port;
4255 sky2_show_vpd(seq, hw);
4257 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4258 sky2_read32(hw, B0_ISRC),
4259 sky2_read32(hw, B0_IMSK),
4260 sky2_read32(hw, B0_Y2_SP_ICR));
4262 if (!netif_running(dev)) {
4263 seq_printf(seq, "network not running\n");
4267 napi_disable(&hw->napi);
4268 last = sky2_read16(hw, STAT_PUT_IDX);
4270 if (hw->st_idx == last)
4271 seq_puts(seq, "Status ring (empty)\n");
4273 seq_puts(seq, "Status ring\n");
4274 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4275 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4276 const struct sky2_status_le *le = hw->st_le + idx;
4277 seq_printf(seq, "[%d] %#x %d %#x\n",
4278 idx, le->opcode, le->length, le->status);
4280 seq_puts(seq, "\n");
4283 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4284 sky2->tx_cons, sky2->tx_prod,
4285 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4286 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4288 /* Dump contents of tx ring */
4290 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4291 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4292 const struct sky2_tx_le *le = sky2->tx_le + idx;
4293 u32 a = le32_to_cpu(le->addr);
4296 seq_printf(seq, "%u:", idx);
4299 switch(le->opcode & ~HW_OWNER) {
4301 seq_printf(seq, " %#x:", a);
4304 seq_printf(seq, " mtu=%d", a);
4307 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4310 seq_printf(seq, " csum=%#x", a);
4313 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4316 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4319 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4322 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4323 a, le16_to_cpu(le->length));
4326 if (le->ctrl & EOP) {
4327 seq_putc(seq, '\n');
4332 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4333 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4334 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4335 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4337 sky2_read32(hw, B0_Y2_SP_LISR);
4338 napi_enable(&hw->napi);
4342 static int sky2_debug_open(struct inode *inode, struct file *file)
4344 return single_open(file, sky2_debug_show, inode->i_private);
4347 static const struct file_operations sky2_debug_fops = {
4348 .owner = THIS_MODULE,
4349 .open = sky2_debug_open,
4351 .llseek = seq_lseek,
4352 .release = single_release,
4356 * Use network device events to create/remove/rename
4357 * debugfs file entries
4359 static int sky2_device_event(struct notifier_block *unused,
4360 unsigned long event, void *ptr)
4362 struct net_device *dev = ptr;
4363 struct sky2_port *sky2 = netdev_priv(dev);
4365 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4369 case NETDEV_CHANGENAME:
4370 if (sky2->debugfs) {
4371 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4372 sky2_debug, dev->name);
4376 case NETDEV_GOING_DOWN:
4377 if (sky2->debugfs) {
4378 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4380 debugfs_remove(sky2->debugfs);
4381 sky2->debugfs = NULL;
4386 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4389 if (IS_ERR(sky2->debugfs))
4390 sky2->debugfs = NULL;
4396 static struct notifier_block sky2_notifier = {
4397 .notifier_call = sky2_device_event,
4401 static __init void sky2_debug_init(void)
4405 ent = debugfs_create_dir("sky2", NULL);
4406 if (!ent || IS_ERR(ent))
4410 register_netdevice_notifier(&sky2_notifier);
4413 static __exit void sky2_debug_cleanup(void)
4416 unregister_netdevice_notifier(&sky2_notifier);
4417 debugfs_remove(sky2_debug);
4423 #define sky2_debug_init()
4424 #define sky2_debug_cleanup()
4427 /* Two copies of network device operations to handle special case of
4428 not allowing netpoll on second port */
4429 static const struct net_device_ops sky2_netdev_ops[2] = {
4431 .ndo_open = sky2_up,
4432 .ndo_stop = sky2_down,
4433 .ndo_start_xmit = sky2_xmit_frame,
4434 .ndo_do_ioctl = sky2_ioctl,
4435 .ndo_validate_addr = eth_validate_addr,
4436 .ndo_set_mac_address = sky2_set_mac_address,
4437 .ndo_set_multicast_list = sky2_set_multicast,
4438 .ndo_change_mtu = sky2_change_mtu,
4439 .ndo_tx_timeout = sky2_tx_timeout,
4440 #ifdef SKY2_VLAN_TAG_USED
4441 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4443 #ifdef CONFIG_NET_POLL_CONTROLLER
4444 .ndo_poll_controller = sky2_netpoll,
4448 .ndo_open = sky2_up,
4449 .ndo_stop = sky2_down,
4450 .ndo_start_xmit = sky2_xmit_frame,
4451 .ndo_do_ioctl = sky2_ioctl,
4452 .ndo_validate_addr = eth_validate_addr,
4453 .ndo_set_mac_address = sky2_set_mac_address,
4454 .ndo_set_multicast_list = sky2_set_multicast,
4455 .ndo_change_mtu = sky2_change_mtu,
4456 .ndo_tx_timeout = sky2_tx_timeout,
4457 #ifdef SKY2_VLAN_TAG_USED
4458 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4463 /* Initialize network device */
4464 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4466 int highmem, int wol)
4468 struct sky2_port *sky2;
4469 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4472 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4476 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4477 dev->irq = hw->pdev->irq;
4478 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4479 dev->watchdog_timeo = TX_WATCHDOG;
4480 dev->netdev_ops = &sky2_netdev_ops[port];
4482 sky2 = netdev_priv(dev);
4485 sky2->msg_enable = netif_msg_init(debug, default_msg);
4487 /* Auto speed and flow control */
4488 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4489 if (hw->chip_id != CHIP_ID_YUKON_XL)
4490 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4492 sky2->flow_mode = FC_BOTH;
4496 sky2->advertising = sky2_supported_modes(hw);
4499 spin_lock_init(&sky2->phy_lock);
4501 sky2->tx_pending = TX_DEF_PENDING;
4502 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4503 sky2->rx_pending = RX_DEF_PENDING;
4505 hw->dev[port] = dev;
4509 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4511 dev->features |= NETIF_F_HIGHDMA;
4513 #ifdef SKY2_VLAN_TAG_USED
4514 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4515 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4516 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4517 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4521 /* read the mac address */
4522 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4523 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4528 static void __devinit sky2_show_addr(struct net_device *dev)
4530 const struct sky2_port *sky2 = netdev_priv(dev);
4532 if (netif_msg_probe(sky2))
4533 printk(KERN_INFO PFX "%s: addr %pM\n",
4534 dev->name, dev->dev_addr);
4537 /* Handle software interrupt used during MSI test */
4538 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4540 struct sky2_hw *hw = dev_id;
4541 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4546 if (status & Y2_IS_IRQ_SW) {
4547 hw->flags |= SKY2_HW_USE_MSI;
4548 wake_up(&hw->msi_wait);
4549 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4551 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4556 /* Test interrupt path by forcing a a software IRQ */
4557 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4559 struct pci_dev *pdev = hw->pdev;
4562 init_waitqueue_head (&hw->msi_wait);
4564 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4566 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4568 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4572 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4573 sky2_read8(hw, B0_CTST);
4575 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4577 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4578 /* MSI test failed, go back to INTx mode */
4579 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4580 "switching to INTx mode.\n");
4583 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4586 sky2_write32(hw, B0_IMSK, 0);
4587 sky2_read32(hw, B0_IMSK);
4589 free_irq(pdev->irq, hw);
4594 /* This driver supports yukon2 chipset only */
4595 static const char *sky2_name(u8 chipid, char *buf, int sz)
4597 const char *name[] = {
4599 "EC Ultra", /* 0xb4 */
4600 "Extreme", /* 0xb5 */
4604 "Supreme", /* 0xb9 */
4606 "Unknown", /* 0xbb */
4607 "Optima", /* 0xbc */
4610 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
4611 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4613 snprintf(buf, sz, "(chip %#x)", chipid);
4617 static int __devinit sky2_probe(struct pci_dev *pdev,
4618 const struct pci_device_id *ent)
4620 struct net_device *dev;
4622 int err, using_dac = 0, wol_default;
4626 err = pci_enable_device(pdev);
4628 dev_err(&pdev->dev, "cannot enable PCI device\n");
4632 /* Get configuration information
4633 * Note: only regular PCI config access once to test for HW issues
4634 * other PCI access through shared memory for speed and to
4635 * avoid MMCONFIG problems.
4637 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4639 dev_err(&pdev->dev, "PCI read config failed\n");
4644 dev_err(&pdev->dev, "PCI configuration read error\n");
4648 err = pci_request_regions(pdev, DRV_NAME);
4650 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4651 goto err_out_disable;
4654 pci_set_master(pdev);
4656 if (sizeof(dma_addr_t) > sizeof(u32) &&
4657 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4659 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4661 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4662 "for consistent allocations\n");
4663 goto err_out_free_regions;
4666 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4668 dev_err(&pdev->dev, "no usable DMA configuration\n");
4669 goto err_out_free_regions;
4675 /* The sk98lin vendor driver uses hardware byte swapping but
4676 * this driver uses software swapping.
4678 reg &= ~PCI_REV_DESC;
4679 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4681 dev_err(&pdev->dev, "PCI write config failed\n");
4682 goto err_out_free_regions;
4686 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4690 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4691 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4693 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4694 goto err_out_free_regions;
4698 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4700 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4702 dev_err(&pdev->dev, "cannot map device registers\n");
4703 goto err_out_free_hw;
4706 /* ring for status responses */
4707 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4709 goto err_out_iounmap;
4711 err = sky2_init(hw);
4713 goto err_out_iounmap;
4715 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4716 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4720 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4723 goto err_out_free_pci;
4726 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4727 err = sky2_test_msi(hw);
4728 if (err == -EOPNOTSUPP)
4729 pci_disable_msi(pdev);
4731 goto err_out_free_netdev;
4734 err = register_netdev(dev);
4736 dev_err(&pdev->dev, "cannot register net device\n");
4737 goto err_out_free_netdev;
4740 netif_carrier_off(dev);
4742 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4744 err = request_irq(pdev->irq, sky2_intr,
4745 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4748 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4749 goto err_out_unregister;
4751 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4752 napi_enable(&hw->napi);
4754 sky2_show_addr(dev);
4756 if (hw->ports > 1) {
4757 struct net_device *dev1;
4760 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4761 if (dev1 && (err = register_netdev(dev1)) == 0)
4762 sky2_show_addr(dev1);
4764 dev_warn(&pdev->dev,
4765 "register of second port failed (%d)\n", err);
4773 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4774 INIT_WORK(&hw->restart_work, sky2_restart);
4776 pci_set_drvdata(pdev, hw);
4777 pdev->d3_delay = 150;
4782 if (hw->flags & SKY2_HW_USE_MSI)
4783 pci_disable_msi(pdev);
4784 unregister_netdev(dev);
4785 err_out_free_netdev:
4788 sky2_write8(hw, B0_CTST, CS_RST_SET);
4789 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4794 err_out_free_regions:
4795 pci_release_regions(pdev);
4797 pci_disable_device(pdev);
4799 pci_set_drvdata(pdev, NULL);
4803 static void __devexit sky2_remove(struct pci_dev *pdev)
4805 struct sky2_hw *hw = pci_get_drvdata(pdev);
4811 del_timer_sync(&hw->watchdog_timer);
4812 cancel_work_sync(&hw->restart_work);
4814 for (i = hw->ports-1; i >= 0; --i)
4815 unregister_netdev(hw->dev[i]);
4817 sky2_write32(hw, B0_IMSK, 0);
4821 sky2_write8(hw, B0_CTST, CS_RST_SET);
4822 sky2_read8(hw, B0_CTST);
4824 free_irq(pdev->irq, hw);
4825 if (hw->flags & SKY2_HW_USE_MSI)
4826 pci_disable_msi(pdev);
4827 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4828 pci_release_regions(pdev);
4829 pci_disable_device(pdev);
4831 for (i = hw->ports-1; i >= 0; --i)
4832 free_netdev(hw->dev[i]);
4837 pci_set_drvdata(pdev, NULL);
4840 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4842 struct sky2_hw *hw = pci_get_drvdata(pdev);
4848 del_timer_sync(&hw->watchdog_timer);
4849 cancel_work_sync(&hw->restart_work);
4852 for (i = 0; i < hw->ports; i++) {
4853 struct net_device *dev = hw->dev[i];
4854 struct sky2_port *sky2 = netdev_priv(dev);
4859 sky2_wol_init(sky2);
4864 device_set_wakeup_enable(&pdev->dev, wol != 0);
4866 sky2_write32(hw, B0_IMSK, 0);
4867 napi_disable(&hw->napi);
4871 pci_save_state(pdev);
4872 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4873 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4879 static int sky2_resume(struct pci_dev *pdev)
4881 struct sky2_hw *hw = pci_get_drvdata(pdev);
4887 err = pci_set_power_state(pdev, PCI_D0);
4891 err = pci_restore_state(pdev);
4895 pci_enable_wake(pdev, PCI_D0, 0);
4897 /* Re-enable all clocks */
4898 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4900 dev_err(&pdev->dev, "PCI write config failed\n");
4905 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4906 napi_enable(&hw->napi);
4909 for (i = 0; i < hw->ports; i++) {
4910 err = sky2_reattach(hw->dev[i]);
4920 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4921 pci_disable_device(pdev);
4926 static void sky2_shutdown(struct pci_dev *pdev)
4928 sky2_suspend(pdev, PMSG_SUSPEND);
4931 static struct pci_driver sky2_driver = {
4933 .id_table = sky2_id_table,
4934 .probe = sky2_probe,
4935 .remove = __devexit_p(sky2_remove),
4937 .suspend = sky2_suspend,
4938 .resume = sky2_resume,
4940 .shutdown = sky2_shutdown,
4943 static int __init sky2_init_module(void)
4945 pr_info(PFX "driver version " DRV_VERSION "\n");
4948 return pci_register_driver(&sky2_driver);
4951 static void __exit sky2_cleanup_module(void)
4953 pci_unregister_driver(&sky2_driver);
4954 sky2_debug_cleanup();
4957 module_init(sky2_init_module);
4958 module_exit(sky2_cleanup_module);
4960 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4961 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4962 MODULE_LICENSE("GPL");
4963 MODULE_VERSION(DRV_VERSION);