Pileus Git - ~andy/linux/blob - drivers/net/sfc/nic.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2009 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include "net_driver.h"
  17 #include "bitfield.h"
  18 #include "efx.h"
  19 #include "nic.h"
  20 #include "regs.h"
  21 #include "io.h"
  22 #include "workarounds.h"
  23
  24 /**************************************************************************
  25  *
  26  * Configurable values
  27  *
  28  **************************************************************************
  29  */
  30
  31 /* This is set to 16 for a good reason.  In summary, if larger than
  32  * 16, the descriptor cache holds more than a default socket
  33  * buffer's worth of packets (for UDP we can only have at most one
  34  * socket buffer's worth outstanding).  This combined with the fact
  35  * that we only get 1 TX event per descriptor cache means the NIC
  36  * goes idle.
  37  */
  38 #define TX_DC_ENTRIES 16
  39 #define TX_DC_ENTRIES_ORDER 1
  40
  41 #define RX_DC_ENTRIES 64
  42 #define RX_DC_ENTRIES_ORDER 3
  43
  44 /* RX FIFO XOFF watermark
  45  *
  46  * When the amount of the RX FIFO increases used increases past this
  47  * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
  48  * This also has an effect on RX/TX arbitration
  49  */
  50 int efx_nic_rx_xoff_thresh = -1;
  51 module_param_named(rx_xoff_thresh_bytes, efx_nic_rx_xoff_thresh, int, 0644);
  52 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
  53
  54 /* RX FIFO XON watermark
  55  *
  56  * When the amount of the RX FIFO used decreases below this
  57  * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
  58  * This also has an effect on RX/TX arbitration
  59  */
  60 int efx_nic_rx_xon_thresh = -1;
  61 module_param_named(rx_xon_thresh_bytes, efx_nic_rx_xon_thresh, int, 0644);
  62 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
  63
  64 /* If EFX_MAX_INT_ERRORS internal errors occur within
  65  * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
  66  * disable it.
  67  */
  68 #define EFX_INT_ERROR_EXPIRE 3600
  69 #define EFX_MAX_INT_ERRORS 5
  70
  71 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
  72  */
  73 #define EFX_FLUSH_INTERVAL 10
  74 #define EFX_FLUSH_POLL_COUNT 100
  75
  76 /* Size and alignment of special buffers (4KB) */
  77 #define EFX_BUF_SIZE 4096
  78
  79 /* Depth of RX flush request fifo */
  80 #define EFX_RX_FLUSH_COUNT 4
  81
  82 /* Generated event code for efx_generate_test_event() */
  83 #define EFX_CHANNEL_MAGIC_TEST(_channel)        \
  84         (0x00010100 + (_channel)->channel)
  85
  86 /* Generated event code for efx_generate_fill_event() */
  87 #define EFX_CHANNEL_MAGIC_FILL(_channel)        \
  88         (0x00010200 + (_channel)->channel)
  89
  90 /**************************************************************************
  91  *
  92  * Solarstorm hardware access
  93  *
  94  **************************************************************************/
  95
  96 static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
  97                                      unsigned int index)
  98 {
  99         efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
 100                         value, index);
 101 }
 102
 103 /* Read the current event from the event queue */
 104 static inline efx_qword_t *efx_event(struct efx_channel *channel,
 105                                      unsigned int index)
 106 {
 107         return (((efx_qword_t *) (channel->eventq.addr)) + index);
 108 }
 109
 110 /* See if an event is present
 111  *
 112  * We check both the high and low dword of the event for all ones.  We
 113  * wrote all ones when we cleared the event, and no valid event can
 114  * have all ones in either its high or low dwords.  This approach is
 115  * robust against reordering.
 116  *
 117  * Note that using a single 64-bit comparison is incorrect; even
 118  * though the CPU read will be atomic, the DMA write may not be.
 119  */
 120 static inline int efx_event_present(efx_qword_t *event)
 121 {
 122         return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
 123                   EFX_DWORD_IS_ALL_ONES(event->dword[1])));
 124 }
 125
 126 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
 127                                      const efx_oword_t *mask)
 128 {
 129         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
 130                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
 131 }
 132
 133 int efx_nic_test_registers(struct efx_nic *efx,
 134                            const struct efx_nic_register_test *regs,
 135                            size_t n_regs)
 136 {
 137         unsigned address = 0, i, j;
 138         efx_oword_t mask, imask, original, reg, buf;
 139
 140         /* Falcon should be in loopback to isolate the XMAC from the PHY */
 141         WARN_ON(!LOOPBACK_INTERNAL(efx));
 142
 143         for (i = 0; i < n_regs; ++i) {
 144                 address = regs[i].address;
 145                 mask = imask = regs[i].mask;
 146                 EFX_INVERT_OWORD(imask);
 147
 148                 efx_reado(efx, &original, address);
 149
 150                 /* bit sweep on and off */
 151                 for (j = 0; j < 128; j++) {
 152                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
 153                                 continue;
 154
 155                         /* Test this testable bit can be set in isolation */
 156                         EFX_AND_OWORD(reg, original, mask);
 157                         EFX_SET_OWORD32(reg, j, j, 1);
 158
 159                         efx_writeo(efx, &reg, address);
 160                         efx_reado(efx, &buf, address);
 161
 162                         if (efx_masked_compare_oword(&reg, &buf, &mask))
 163                                 goto fail;
 164
 165                         /* Test this testable bit can be cleared in isolation */
 166                         EFX_OR_OWORD(reg, original, mask);
 167                         EFX_SET_OWORD32(reg, j, j, 0);
 168
 169                         efx_writeo(efx, &reg, address);
 170                         efx_reado(efx, &buf, address);
 171
 172                         if (efx_masked_compare_oword(&reg, &buf, &mask))
 173                                 goto fail;
 174                 }
 175
 176                 efx_writeo(efx, &original, address);
 177         }
 178
 179         return 0;
 180
 181 fail:
 182         netif_err(efx, hw, efx->net_dev,
 183                   "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
 184                   " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
 185                   EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
 186         return -EIO;
 187 }
 188
 189 /**************************************************************************
 190  *
 191  * Special buffer handling
 192  * Special buffers are used for event queues and the TX and RX
 193  * descriptor rings.
 194  *
 195  *************************************************************************/
 196
 197 /*
 198  * Initialise a special buffer
 199  *
 200  * This will define a buffer (previously allocated via
 201  * efx_alloc_special_buffer()) in the buffer table, allowing
 202  * it to be used for event queues, descriptor rings etc.
 203  */
 204 static void
 205 efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 206 {
 207         efx_qword_t buf_desc;
 208         int index;
 209         dma_addr_t dma_addr;
 210         int i;
 211
 212         EFX_BUG_ON_PARANOID(!buffer->addr);
 213
 214         /* Write buffer descriptors to NIC */
 215         for (i = 0; i < buffer->entries; i++) {
 216                 index = buffer->index + i;
 217                 dma_addr = buffer->dma_addr + (i * 4096);
 218                 netif_dbg(efx, probe, efx->net_dev,
 219                           "mapping special buffer %d at %llx\n",
 220                           index, (unsigned long long)dma_addr);
 221                 EFX_POPULATE_QWORD_3(buf_desc,
 222                                      FRF_AZ_BUF_ADR_REGION, 0,
 223                                      FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
 224                                      FRF_AZ_BUF_OWNER_ID_FBUF, 0);
 225                 efx_write_buf_tbl(efx, &buf_desc, index);
 226         }
 227 }
 228
 229 /* Unmaps a buffer and clears the buffer table entries */
 230 static void
 231 efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 232 {
 233         efx_oword_t buf_tbl_upd;
 234         unsigned int start = buffer->index;
 235         unsigned int end = (buffer->index + buffer->entries - 1);
 236
 237         if (!buffer->entries)
 238                 return;
 239
 240         netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n",
 241                   buffer->index, buffer->index + buffer->entries - 1);
 242
 243         EFX_POPULATE_OWORD_4(buf_tbl_upd,
 244                              FRF_AZ_BUF_UPD_CMD, 0,
 245                              FRF_AZ_BUF_CLR_CMD, 1,
 246                              FRF_AZ_BUF_CLR_END_ID, end,
 247                              FRF_AZ_BUF_CLR_START_ID, start);
 248         efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
 249 }
 250
 251 /*
 252  * Allocate a new special buffer
 253  *
 254  * This allocates memory for a new buffer, clears it and allocates a
 255  * new buffer ID range.  It does not write into the buffer table.
 256  *
 257  * This call will allocate 4KB buffers, since 8KB buffers can't be
 258  * used for event queues and descriptor rings.
 259  */
 260 static int efx_alloc_special_buffer(struct efx_nic *efx,
 261                                     struct efx_special_buffer *buffer,
 262                                     unsigned int len)
 263 {
 264         len = ALIGN(len, EFX_BUF_SIZE);
 265
 266         buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len,
 267                                           &buffer->dma_addr, GFP_KERNEL);
 268         if (!buffer->addr)
 269                 return -ENOMEM;
 270         buffer->len = len;
 271         buffer->entries = len / EFX_BUF_SIZE;
 272         BUG_ON(buffer->dma_addr & (EFX_BUF_SIZE - 1));
 273
 274         /* All zeros is a potentially valid event so memset to 0xff */
 275         memset(buffer->addr, 0xff, len);
 276
 277         /* Select new buffer ID */
 278         buffer->index = efx->next_buffer_table;
 279         efx->next_buffer_table += buffer->entries;
 280
 281         netif_dbg(efx, probe, efx->net_dev,
 282                   "allocating special buffers %d-%d at %llx+%x "
 283                   "(virt %p phys %llx)\n", buffer->index,
 284                   buffer->index + buffer->entries - 1,
 285                   (u64)buffer->dma_addr, len,
 286                   buffer->addr, (u64)virt_to_phys(buffer->addr));
 287
 288         return 0;
 289 }
 290
 291 static void
 292 efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 293 {
 294         if (!buffer->addr)
 295                 return;
 296
 297         netif_dbg(efx, hw, efx->net_dev,
 298                   "deallocating special buffers %d-%d at %llx+%x "
 299                   "(virt %p phys %llx)\n", buffer->index,
 300                   buffer->index + buffer->entries - 1,
 301                   (u64)buffer->dma_addr, buffer->len,
 302                   buffer->addr, (u64)virt_to_phys(buffer->addr));
 303
 304         dma_free_coherent(&efx->pci_dev->dev, buffer->len, buffer->addr,
 305                           buffer->dma_addr);
 306         buffer->addr = NULL;
 307         buffer->entries = 0;
 308 }
 309
 310 /**************************************************************************
 311  *
 312  * Generic buffer handling
 313  * These buffers are used for interrupt status and MAC stats
 314  *
 315  **************************************************************************/
 316
 317 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
 318                          unsigned int len)
 319 {
 320         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 321                                             &buffer->dma_addr);
 322         if (!buffer->addr)
 323                 return -ENOMEM;
 324         buffer->len = len;
 325         memset(buffer->addr, 0, len);
 326         return 0;
 327 }
 328
 329 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
 330 {
 331         if (buffer->addr) {
 332                 pci_free_consistent(efx->pci_dev, buffer->len,
 333                                     buffer->addr, buffer->dma_addr);
 334                 buffer->addr = NULL;
 335         }
 336 }
 337
 338 /**************************************************************************
 339  *
 340  * TX path
 341  *
 342  **************************************************************************/
 343
 344 /* Returns a pointer to the specified transmit descriptor in the TX
 345  * descriptor queue belonging to the specified channel.
 346  */
 347 static inline efx_qword_t *
 348 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
 349 {
 350         return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
 351 }
 352
 353 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
 354 static inline void efx_notify_tx_desc(struct efx_tx_queue *tx_queue)
 355 {
 356         unsigned write_ptr;
 357         efx_dword_t reg;
 358
 359         write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
 360         EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
 361         efx_writed_page(tx_queue->efx, &reg,
 362                         FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
 363 }
 364
 365
 366 /* For each entry inserted into the software descriptor ring, create a
 367  * descriptor in the hardware TX descriptor ring (in host memory), and
 368  * write a doorbell.
 369  */
 370 void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
 371 {
 372
 373         struct efx_tx_buffer *buffer;
 374         efx_qword_t *txd;
 375         unsigned write_ptr;
 376
 377         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
 378
 379         do {
 380                 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
 381                 buffer = &tx_queue->buffer[write_ptr];
 382                 txd = efx_tx_desc(tx_queue, write_ptr);
 383                 ++tx_queue->write_count;
 384
 385                 /* Create TX descriptor ring entry */
 386                 EFX_POPULATE_QWORD_4(*txd,
 387                                      FSF_AZ_TX_KER_CONT, buffer->continuation,
 388                                      FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
 389                                      FSF_AZ_TX_KER_BUF_REGION, 0,
 390                                      FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
 391         } while (tx_queue->write_count != tx_queue->insert_count);
 392
 393         wmb(); /* Ensure descriptors are written before they are fetched */
 394         efx_notify_tx_desc(tx_queue);
 395 }
 396
 397 /* Allocate hardware resources for a TX queue */
 398 int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
 399 {
 400         struct efx_nic *efx = tx_queue->efx;
 401         BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
 402                      EFX_TXQ_SIZE & EFX_TXQ_MASK);
 403         return efx_alloc_special_buffer(efx, &tx_queue->txd,
 404                                         EFX_TXQ_SIZE * sizeof(efx_qword_t));
 405 }
 406
 407 void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
 408 {
 409         efx_oword_t tx_desc_ptr;
 410         struct efx_nic *efx = tx_queue->efx;
 411
 412         tx_queue->flushed = FLUSH_NONE;
 413
 414         /* Pin TX descriptor ring */
 415         efx_init_special_buffer(efx, &tx_queue->txd);
 416
 417         /* Push TX descriptor ring to card */
 418         EFX_POPULATE_OWORD_10(tx_desc_ptr,
 419                               FRF_AZ_TX_DESCQ_EN, 1,
 420                               FRF_AZ_TX_ISCSI_DDIG_EN, 0,
 421                               FRF_AZ_TX_ISCSI_HDIG_EN, 0,
 422                               FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
 423                               FRF_AZ_TX_DESCQ_EVQ_ID,
 424                               tx_queue->channel->channel,
 425                               FRF_AZ_TX_DESCQ_OWNER_ID, 0,
 426                               FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
 427                               FRF_AZ_TX_DESCQ_SIZE,
 428                               __ffs(tx_queue->txd.entries),
 429                               FRF_AZ_TX_DESCQ_TYPE, 0,
 430                               FRF_BZ_TX_NON_IP_DROP_DIS, 1);
 431
 432         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 433                 int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
 434                 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
 435                 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
 436                                     !csum);
 437         }
 438
 439         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 440                          tx_queue->queue);
 441
 442         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
 443                 efx_oword_t reg;
 444
 445                 /* Only 128 bits in this register */
 446                 BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128);
 447
 448                 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
 449                 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
 450                         clear_bit_le(tx_queue->queue, (void *)&reg);
 451                 else
 452                         set_bit_le(tx_queue->queue, (void *)&reg);
 453                 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
 454         }
 455 }
 456
 457 static void efx_flush_tx_queue(struct efx_tx_queue *tx_queue)
 458 {
 459         struct efx_nic *efx = tx_queue->efx;
 460         efx_oword_t tx_flush_descq;
 461
 462         tx_queue->flushed = FLUSH_PENDING;
 463
 464         /* Post a flush command */
 465         EFX_POPULATE_OWORD_2(tx_flush_descq,
 466                              FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
 467                              FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
 468         efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
 469 }
 470
 471 void efx_nic_fini_tx(struct efx_tx_queue *tx_queue)
 472 {
 473         struct efx_nic *efx = tx_queue->efx;
 474         efx_oword_t tx_desc_ptr;
 475
 476         /* The queue should have been flushed */
 477         WARN_ON(tx_queue->flushed != FLUSH_DONE);
 478
 479         /* Remove TX descriptor ring from card */
 480         EFX_ZERO_OWORD(tx_desc_ptr);
 481         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 482                          tx_queue->queue);
 483
 484         /* Unpin TX descriptor ring */
 485         efx_fini_special_buffer(efx, &tx_queue->txd);
 486 }
 487
 488 /* Free buffers backing TX queue */
 489 void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
 490 {
 491         efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
 492 }
 493
 494 /**************************************************************************
 495  *
 496  * RX path
 497  *
 498  **************************************************************************/
 499
 500 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
 501 static inline efx_qword_t *
 502 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
 503 {
 504         return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
 505 }
 506
 507 /* This creates an entry in the RX descriptor queue */
 508 static inline void
 509 efx_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
 510 {
 511         struct efx_rx_buffer *rx_buf;
 512         efx_qword_t *rxd;
 513
 514         rxd = efx_rx_desc(rx_queue, index);
 515         rx_buf = efx_rx_buffer(rx_queue, index);
 516         EFX_POPULATE_QWORD_3(*rxd,
 517                              FSF_AZ_RX_KER_BUF_SIZE,
 518                              rx_buf->len -
 519                              rx_queue->efx->type->rx_buffer_padding,
 520                              FSF_AZ_RX_KER_BUF_REGION, 0,
 521                              FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
 522 }
 523
 524 /* This writes to the RX_DESC_WPTR register for the specified receive
 525  * descriptor ring.
 526  */
 527 void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
 528 {
 529         efx_dword_t reg;
 530         unsigned write_ptr;
 531
 532         while (rx_queue->notified_count != rx_queue->added_count) {
 533                 efx_build_rx_desc(rx_queue,
 534                                   rx_queue->notified_count &
 535                                   EFX_RXQ_MASK);
 536                 ++rx_queue->notified_count;
 537         }
 538
 539         wmb();
 540         write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
 541         EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
 542         efx_writed_page(rx_queue->efx, &reg, FR_AZ_RX_DESC_UPD_DWORD_P0,
 543                         efx_rx_queue_index(rx_queue));
 544 }
 545
 546 int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
 547 {
 548         struct efx_nic *efx = rx_queue->efx;
 549         BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
 550                      EFX_RXQ_SIZE & EFX_RXQ_MASK);
 551         return efx_alloc_special_buffer(efx, &rx_queue->rxd,
 552                                         EFX_RXQ_SIZE * sizeof(efx_qword_t));
 553 }
 554
 555 void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
 556 {
 557         efx_oword_t rx_desc_ptr;
 558         struct efx_nic *efx = rx_queue->efx;
 559         bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
 560         bool iscsi_digest_en = is_b0;
 561
 562         netif_dbg(efx, hw, efx->net_dev,
 563                   "RX queue %d ring in special buffers %d-%d\n",
 564                   efx_rx_queue_index(rx_queue), rx_queue->rxd.index,
 565                   rx_queue->rxd.index + rx_queue->rxd.entries - 1);
 566
 567         rx_queue->flushed = FLUSH_NONE;
 568
 569         /* Pin RX descriptor ring */
 570         efx_init_special_buffer(efx, &rx_queue->rxd);
 571
 572         /* Push RX descriptor ring to card */
 573         EFX_POPULATE_OWORD_10(rx_desc_ptr,
 574                               FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
 575                               FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
 576                               FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
 577                               FRF_AZ_RX_DESCQ_EVQ_ID,
 578                               efx_rx_queue_channel(rx_queue)->channel,
 579                               FRF_AZ_RX_DESCQ_OWNER_ID, 0,
 580                               FRF_AZ_RX_DESCQ_LABEL,
 581                               efx_rx_queue_index(rx_queue),
 582                               FRF_AZ_RX_DESCQ_SIZE,
 583                               __ffs(rx_queue->rxd.entries),
 584                               FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
 585                               /* For >=B0 this is scatter so disable */
 586                               FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
 587                               FRF_AZ_RX_DESCQ_EN, 1);
 588         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 589                          efx_rx_queue_index(rx_queue));
 590 }
 591
 592 static void efx_flush_rx_queue(struct efx_rx_queue *rx_queue)
 593 {
 594         struct efx_nic *efx = rx_queue->efx;
 595         efx_oword_t rx_flush_descq;
 596
 597         rx_queue->flushed = FLUSH_PENDING;
 598
 599         /* Post a flush command */
 600         EFX_POPULATE_OWORD_2(rx_flush_descq,
 601                              FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
 602                              FRF_AZ_RX_FLUSH_DESCQ,
 603                              efx_rx_queue_index(rx_queue));
 604         efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
 605 }
 606
 607 void efx_nic_fini_rx(struct efx_rx_queue *rx_queue)
 608 {
 609         efx_oword_t rx_desc_ptr;
 610         struct efx_nic *efx = rx_queue->efx;
 611
 612         /* The queue should already have been flushed */
 613         WARN_ON(rx_queue->flushed != FLUSH_DONE);
 614
 615         /* Remove RX descriptor ring from card */
 616         EFX_ZERO_OWORD(rx_desc_ptr);
 617         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 618                          efx_rx_queue_index(rx_queue));
 619
 620         /* Unpin RX descriptor ring */
 621         efx_fini_special_buffer(efx, &rx_queue->rxd);
 622 }
 623
 624 /* Free buffers backing RX queue */
 625 void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
 626 {
 627         efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
 628 }
 629
 630 /**************************************************************************
 631  *
 632  * Event queue processing
 633  * Event queues are processed by per-channel tasklets.
 634  *
 635  **************************************************************************/
 636
 637 /* Update a channel's event queue's read pointer (RPTR) register
 638  *
 639  * This writes the EVQ_RPTR_REG register for the specified channel's
 640  * event queue.
 641  */
 642 void efx_nic_eventq_read_ack(struct efx_channel *channel)
 643 {
 644         efx_dword_t reg;
 645         struct efx_nic *efx = channel->efx;
 646
 647         EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
 648         efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
 649                          channel->channel);
 650 }
 651
 652 /* Use HW to insert a SW defined event */
 653 void efx_generate_event(struct efx_channel *channel, efx_qword_t *event)
 654 {
 655         efx_oword_t drv_ev_reg;
 656
 657         BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
 658                      FRF_AZ_DRV_EV_DATA_WIDTH != 64);
 659         drv_ev_reg.u32[0] = event->u32[0];
 660         drv_ev_reg.u32[1] = event->u32[1];
 661         drv_ev_reg.u32[2] = 0;
 662         drv_ev_reg.u32[3] = 0;
 663         EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
 664         efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
 665 }
 666
 667 /* Handle a transmit completion event
 668  *
 669  * The NIC batches TX completion events; the message we receive is of
 670  * the form "complete all TX events up to this index".
 671  */
 672 static int
 673 efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
 674 {
 675         unsigned int tx_ev_desc_ptr;
 676         unsigned int tx_ev_q_label;
 677         struct efx_tx_queue *tx_queue;
 678         struct efx_nic *efx = channel->efx;
 679         int tx_packets = 0;
 680
 681         if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
 682                 /* Transmit completion */
 683                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
 684                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 685                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 686                 tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) &
 687                               EFX_TXQ_MASK);
 688                 channel->irq_mod_score += tx_packets;
 689                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
 690         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
 691                 /* Rewrite the FIFO write pointer */
 692                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 693                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 694
 695                 if (efx_dev_registered(efx))
 696                         netif_tx_lock(efx->net_dev);
 697                 efx_notify_tx_desc(tx_queue);
 698                 if (efx_dev_registered(efx))
 699                         netif_tx_unlock(efx->net_dev);
 700         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
 701                    EFX_WORKAROUND_10727(efx)) {
 702                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 703         } else {
 704                 netif_err(efx, tx_err, efx->net_dev,
 705                           "channel %d unexpected TX event "
 706                           EFX_QWORD_FMT"\n", channel->channel,
 707                           EFX_QWORD_VAL(*event));
 708         }
 709
 710         return tx_packets;
 711 }
 712
 713 /* Detect errors included in the rx_evt_pkt_ok bit. */
 714 static void efx_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
 715                                  const efx_qword_t *event,
 716                                  bool *rx_ev_pkt_ok,
 717                                  bool *discard)
 718 {
 719         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
 720         struct efx_nic *efx = rx_queue->efx;
 721         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
 722         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
 723         bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
 724         bool rx_ev_other_err, rx_ev_pause_frm;
 725         bool rx_ev_hdr_type, rx_ev_mcast_pkt;
 726         unsigned rx_ev_pkt_type;
 727
 728         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
 729         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
 730         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
 731         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
 732         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
 733                                                  FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
 734         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
 735                                                   FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
 736         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
 737                                                    FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
 738         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
 739         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
 740         rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
 741                           0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
 742         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
 743
 744         /* Every error apart from tobe_disc and pause_frm */
 745         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
 746                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
 747                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
 748
 749         /* Count errors that are not in MAC stats.  Ignore expected
 750          * checksum errors during self-test. */
 751         if (rx_ev_frm_trunc)
 752                 ++channel->n_rx_frm_trunc;
 753         else if (rx_ev_tobe_disc)
 754                 ++channel->n_rx_tobe_disc;
 755         else if (!efx->loopback_selftest) {
 756                 if (rx_ev_ip_hdr_chksum_err)
 757                         ++channel->n_rx_ip_hdr_chksum_err;
 758                 else if (rx_ev_tcp_udp_chksum_err)
 759                         ++channel->n_rx_tcp_udp_chksum_err;
 760         }
 761
 762         /* The frame must be discarded if any of these are true. */
 763         *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
 764                     rx_ev_tobe_disc | rx_ev_pause_frm);
 765
 766         /* TOBE_DISC is expected on unicast mismatches; don't print out an
 767          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
 768          * to a FIFO overflow.
 769          */
 770 #ifdef EFX_ENABLE_DEBUG
 771         if (rx_ev_other_err && net_ratelimit()) {
 772                 netif_dbg(efx, rx_err, efx->net_dev,
 773                           " RX queue %d unexpected RX event "
 774                           EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
 775                           efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event),
 776                           rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
 777                           rx_ev_ip_hdr_chksum_err ?
 778                           " [IP_HDR_CHKSUM_ERR]" : "",
 779                           rx_ev_tcp_udp_chksum_err ?
 780                           " [TCP_UDP_CHKSUM_ERR]" : "",
 781                           rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
 782                           rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
 783                           rx_ev_drib_nib ? " [DRIB_NIB]" : "",
 784                           rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
 785                           rx_ev_pause_frm ? " [PAUSE]" : "");
 786         }
 787 #endif
 788 }
 789
 790 /* Handle receive events that are not in-order. */
 791 static void
 792 efx_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
 793 {
 794         struct efx_nic *efx = rx_queue->efx;
 795         unsigned expected, dropped;
 796
 797         expected = rx_queue->removed_count & EFX_RXQ_MASK;
 798         dropped = (index - expected) & EFX_RXQ_MASK;
 799         netif_info(efx, rx_err, efx->net_dev,
 800                    "dropped %d events (index=%d expected=%d)\n",
 801                    dropped, index, expected);
 802
 803         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
 804                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 805 }
 806
 807 /* Handle a packet received event
 808  *
 809  * The NIC gives a "discard" flag if it's a unicast packet with the
 810  * wrong destination address
 811  * Also "is multicast" and "matches multicast filter" flags can be used to
 812  * discard non-matching multicast packets.
 813  */
 814 static void
 815 efx_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
 816 {
 817         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
 818         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
 819         unsigned expected_ptr;
 820         bool rx_ev_pkt_ok, discard = false, checksummed;
 821         struct efx_rx_queue *rx_queue;
 822         struct efx_nic *efx = channel->efx;
 823
 824         /* Basic packet information */
 825         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
 826         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
 827         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
 828         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
 829         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
 830         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
 831                 channel->channel);
 832
 833         rx_queue = &efx->rx_queue[channel->channel];
 834
 835         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
 836         expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
 837         if (unlikely(rx_ev_desc_ptr != expected_ptr))
 838                 efx_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
 839
 840         if (likely(rx_ev_pkt_ok)) {
 841                 /* If packet is marked as OK and packet type is TCP/IP or
 842                  * UDP/IP, then we can rely on the hardware checksum.
 843                  */
 844                 checksummed =
 845                         likely(efx->rx_checksum_enabled) &&
 846                         (rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP ||
 847                          rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP);
 848         } else {
 849                 efx_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok, &discard);
 850                 checksummed = false;
 851         }
 852
 853         /* Detect multicast packets that didn't match the filter */
 854         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
 855         if (rx_ev_mcast_pkt) {
 856                 unsigned int rx_ev_mcast_hash_match =
 857                         EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
 858
 859                 if (unlikely(!rx_ev_mcast_hash_match)) {
 860                         ++channel->n_rx_mcast_mismatch;
 861                         discard = true;
 862                 }
 863         }
 864
 865         channel->irq_mod_score += 2;
 866
 867         /* Handle received packet */
 868         efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
 869                       checksummed, discard);
 870 }
 871
 872 static void
 873 efx_handle_generated_event(struct efx_channel *channel, efx_qword_t *event)
 874 {
 875         struct efx_nic *efx = channel->efx;
 876         unsigned code;
 877
 878         code = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC);
 879         if (code == EFX_CHANNEL_MAGIC_TEST(channel))
 880                 ++channel->magic_count;
 881         else if (code == EFX_CHANNEL_MAGIC_FILL(channel))
 882                 /* The queue must be empty, so we won't receive any rx
 883                  * events, so efx_process_channel() won't refill the
 884                  * queue. Refill it here */
 885                 efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]);
 886         else
 887                 netif_dbg(efx, hw, efx->net_dev, "channel %d received "
 888                           "generated event "EFX_QWORD_FMT"\n",
 889                           channel->channel, EFX_QWORD_VAL(*event));
 890 }
 891
 892 /* Global events are basically PHY events */
 893 static void
 894 efx_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
 895 {
 896         struct efx_nic *efx = channel->efx;
 897         bool handled = false;
 898
 899         if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
 900             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
 901             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
 902                 /* Ignored */
 903                 handled = true;
 904         }
 905
 906         if ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) &&
 907             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
 908                 efx->xmac_poll_required = true;
 909                 handled = true;
 910         }
 911
 912         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
 913             EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
 914             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
 915                 netif_err(efx, rx_err, efx->net_dev,
 916                           "channel %d seen global RX_RESET event. Resetting.\n",
 917                           channel->channel);
 918
 919                 atomic_inc(&efx->rx_reset);
 920                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
 921                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 922                 handled = true;
 923         }
 924
 925         if (!handled)
 926                 netif_err(efx, hw, efx->net_dev,
 927                           "channel %d unknown global event "
 928                           EFX_QWORD_FMT "\n", channel->channel,
 929                           EFX_QWORD_VAL(*event));
 930 }
 931
 932 static void
 933 efx_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
 934 {
 935         struct efx_nic *efx = channel->efx;
 936         unsigned int ev_sub_code;
 937         unsigned int ev_sub_data;
 938
 939         ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
 940         ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
 941
 942         switch (ev_sub_code) {
 943         case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
 944                 netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n",
 945                            channel->channel, ev_sub_data);
 946                 break;
 947         case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
 948                 netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n",
 949                            channel->channel, ev_sub_data);
 950                 break;
 951         case FSE_AZ_EVQ_INIT_DONE_EV:
 952                 netif_dbg(efx, hw, efx->net_dev,
 953                           "channel %d EVQ %d initialised\n",
 954                           channel->channel, ev_sub_data);
 955                 break;
 956         case FSE_AZ_SRM_UPD_DONE_EV:
 957                 netif_vdbg(efx, hw, efx->net_dev,
 958                            "channel %d SRAM update done\n", channel->channel);
 959                 break;
 960         case FSE_AZ_WAKE_UP_EV:
 961                 netif_vdbg(efx, hw, efx->net_dev,
 962                            "channel %d RXQ %d wakeup event\n",
 963                            channel->channel, ev_sub_data);
 964                 break;
 965         case FSE_AZ_TIMER_EV:
 966                 netif_vdbg(efx, hw, efx->net_dev,
 967                            "channel %d RX queue %d timer expired\n",
 968                            channel->channel, ev_sub_data);
 969                 break;
 970         case FSE_AA_RX_RECOVER_EV:
 971                 netif_err(efx, rx_err, efx->net_dev,
 972                           "channel %d seen DRIVER RX_RESET event. "
 973                         "Resetting.\n", channel->channel);
 974                 atomic_inc(&efx->rx_reset);
 975                 efx_schedule_reset(efx,
 976                                    EFX_WORKAROUND_6555(efx) ?
 977                                    RESET_TYPE_RX_RECOVERY :
 978                                    RESET_TYPE_DISABLE);
 979                 break;
 980         case FSE_BZ_RX_DSC_ERROR_EV:
 981                 netif_err(efx, rx_err, efx->net_dev,
 982                           "RX DMA Q %d reports descriptor fetch error."
 983                           " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 984                 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
 985                 break;
 986         case FSE_BZ_TX_DSC_ERROR_EV:
 987                 netif_err(efx, tx_err, efx->net_dev,
 988                           "TX DMA Q %d reports descriptor fetch error."
 989                           " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 990                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 991                 break;
 992         default:
 993                 netif_vdbg(efx, hw, efx->net_dev,
 994                            "channel %d unknown driver event code %d "
 995                            "data %04x\n", channel->channel, ev_sub_code,
 996                            ev_sub_data);
 997                 break;
 998         }
 999 }
1000
1001 int efx_nic_process_eventq(struct efx_channel *channel, int budget)
1002 {
1003         unsigned int read_ptr;
1004         efx_qword_t event, *p_event;
1005         int ev_code;
1006         int tx_packets = 0;
1007         int spent = 0;
1008
1009         read_ptr = channel->eventq_read_ptr;
1010
1011         for (;;) {
1012                 p_event = efx_event(channel, read_ptr);
1013                 event = *p_event;
1014
1015                 if (!efx_event_present(&event))
1016                         /* End of events */
1017                         break;
1018
1019                 netif_vdbg(channel->efx, intr, channel->efx->net_dev,
1020                            "channel %d event is "EFX_QWORD_FMT"\n",
1021                            channel->channel, EFX_QWORD_VAL(event));
1022
1023                 /* Clear this event by marking it all ones */
1024                 EFX_SET_QWORD(*p_event);
1025
1026                 /* Increment read pointer */
1027                 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1028
1029                 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1030
1031                 switch (ev_code) {
1032                 case FSE_AZ_EV_CODE_RX_EV:
1033                         efx_handle_rx_event(channel, &event);
1034                         if (++spent == budget)
1035                                 goto out;
1036                         break;
1037                 case FSE_AZ_EV_CODE_TX_EV:
1038                         tx_packets += efx_handle_tx_event(channel, &event);
1039                         if (tx_packets >= EFX_TXQ_SIZE) {
1040                                 spent = budget;
1041                                 goto out;
1042                         }
1043                         break;
1044                 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1045                         efx_handle_generated_event(channel, &event);
1046                         break;
1047                 case FSE_AZ_EV_CODE_GLOBAL_EV:
1048                         efx_handle_global_event(channel, &event);
1049                         break;
1050                 case FSE_AZ_EV_CODE_DRIVER_EV:
1051                         efx_handle_driver_event(channel, &event);
1052                         break;
1053                 case FSE_CZ_EV_CODE_MCDI_EV:
1054                         efx_mcdi_process_event(channel, &event);
1055                         break;
1056                 default:
1057                         netif_err(channel->efx, hw, channel->efx->net_dev,
1058                                   "channel %d unknown event type %d (data "
1059                                   EFX_QWORD_FMT ")\n", channel->channel,
1060                                   ev_code, EFX_QWORD_VAL(event));
1061                 }
1062         }
1063
1064 out:
1065         channel->eventq_read_ptr = read_ptr;
1066         return spent;
1067 }
1068
1069
1070 /* Allocate buffer table entries for event queue */
1071 int efx_nic_probe_eventq(struct efx_channel *channel)
1072 {
1073         struct efx_nic *efx = channel->efx;
1074         BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1075                      EFX_EVQ_SIZE & EFX_EVQ_MASK);
1076         return efx_alloc_special_buffer(efx, &channel->eventq,
1077                                         EFX_EVQ_SIZE * sizeof(efx_qword_t));
1078 }
1079
1080 void efx_nic_init_eventq(struct efx_channel *channel)
1081 {
1082         efx_oword_t reg;
1083         struct efx_nic *efx = channel->efx;
1084
1085         netif_dbg(efx, hw, efx->net_dev,
1086                   "channel %d event queue in special buffers %d-%d\n",
1087                   channel->channel, channel->eventq.index,
1088                   channel->eventq.index + channel->eventq.entries - 1);
1089
1090         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
1091                 EFX_POPULATE_OWORD_3(reg,
1092                                      FRF_CZ_TIMER_Q_EN, 1,
1093                                      FRF_CZ_HOST_NOTIFY_MODE, 0,
1094                                      FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1095                 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1096         }
1097
1098         /* Pin event queue buffer */
1099         efx_init_special_buffer(efx, &channel->eventq);
1100
1101         /* Fill event queue with all ones (i.e. empty events) */
1102         memset(channel->eventq.addr, 0xff, channel->eventq.len);
1103
1104         /* Push event queue to card */
1105         EFX_POPULATE_OWORD_3(reg,
1106                              FRF_AZ_EVQ_EN, 1,
1107                              FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1108                              FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1109         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1110                          channel->channel);
1111
1112         efx->type->push_irq_moderation(channel);
1113 }
1114
1115 void efx_nic_fini_eventq(struct efx_channel *channel)
1116 {
1117         efx_oword_t reg;
1118         struct efx_nic *efx = channel->efx;
1119
1120         /* Remove event queue from card */
1121         EFX_ZERO_OWORD(reg);
1122         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1123                          channel->channel);
1124         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1125                 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1126
1127         /* Unpin event queue */
1128         efx_fini_special_buffer(efx, &channel->eventq);
1129 }
1130
1131 /* Free buffers backing event queue */
1132 void efx_nic_remove_eventq(struct efx_channel *channel)
1133 {
1134         efx_free_special_buffer(channel->efx, &channel->eventq);
1135 }
1136
1137
1138 void efx_nic_generate_test_event(struct efx_channel *channel)
1139 {
1140         unsigned int magic = EFX_CHANNEL_MAGIC_TEST(channel);
1141         efx_qword_t test_event;
1142
1143         EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1144                              FSE_AZ_EV_CODE_DRV_GEN_EV,
1145                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1146         efx_generate_event(channel, &test_event);
1147 }
1148
1149 void efx_nic_generate_fill_event(struct efx_channel *channel)
1150 {
1151         unsigned int magic = EFX_CHANNEL_MAGIC_FILL(channel);
1152         efx_qword_t test_event;
1153
1154         EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1155                              FSE_AZ_EV_CODE_DRV_GEN_EV,
1156                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1157         efx_generate_event(channel, &test_event);
1158 }
1159
1160 /**************************************************************************
1161  *
1162  * Flush handling
1163  *
1164  **************************************************************************/
1165
1166
1167 static void efx_poll_flush_events(struct efx_nic *efx)
1168 {
1169         struct efx_channel *channel = &efx->channel[0];
1170         struct efx_tx_queue *tx_queue;
1171         struct efx_rx_queue *rx_queue;
1172         unsigned int read_ptr = channel->eventq_read_ptr;
1173         unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
1174
1175         do {
1176                 efx_qword_t *event = efx_event(channel, read_ptr);
1177                 int ev_code, ev_sub_code, ev_queue;
1178                 bool ev_failed;
1179
1180                 if (!efx_event_present(event))
1181                         break;
1182
1183                 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1184                 ev_sub_code = EFX_QWORD_FIELD(*event,
1185                                               FSF_AZ_DRIVER_EV_SUBCODE);
1186                 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1187                     ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1188                         ev_queue = EFX_QWORD_FIELD(*event,
1189                                                    FSF_AZ_DRIVER_EV_SUBDATA);
1190                         if (ev_queue < EFX_TXQ_TYPES * efx->n_tx_channels) {
1191                                 tx_queue = efx->tx_queue + ev_queue;
1192                                 tx_queue->flushed = FLUSH_DONE;
1193                         }
1194                 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1195                            ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1196                         ev_queue = EFX_QWORD_FIELD(
1197                                 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1198                         ev_failed = EFX_QWORD_FIELD(
1199                                 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1200                         if (ev_queue < efx->n_rx_channels) {
1201                                 rx_queue = efx->rx_queue + ev_queue;
1202                                 rx_queue->flushed =
1203                                         ev_failed ? FLUSH_FAILED : FLUSH_DONE;
1204                         }
1205                 }
1206
1207                 /* We're about to destroy the queue anyway, so
1208                  * it's ok to throw away every non-flush event */
1209                 EFX_SET_QWORD(*event);
1210
1211                 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1212         } while (read_ptr != end_ptr);
1213
1214         channel->eventq_read_ptr = read_ptr;
1215 }
1216
1217 /* Handle tx and rx flushes at the same time, since they run in
1218  * parallel in the hardware and there's no reason for us to
1219  * serialise them */
1220 int efx_nic_flush_queues(struct efx_nic *efx)
1221 {
1222         struct efx_rx_queue *rx_queue;
1223         struct efx_tx_queue *tx_queue;
1224         int i, tx_pending, rx_pending;
1225
1226         /* If necessary prepare the hardware for flushing */
1227         efx->type->prepare_flush(efx);
1228
1229         /* Flush all tx queues in parallel */
1230         efx_for_each_tx_queue(tx_queue, efx)
1231                 efx_flush_tx_queue(tx_queue);
1232
1233         /* The hardware supports four concurrent rx flushes, each of which may
1234          * need to be retried if there is an outstanding descriptor fetch */
1235         for (i = 0; i < EFX_FLUSH_POLL_COUNT; ++i) {
1236                 rx_pending = tx_pending = 0;
1237                 efx_for_each_rx_queue(rx_queue, efx) {
1238                         if (rx_queue->flushed == FLUSH_PENDING)
1239                                 ++rx_pending;
1240                 }
1241                 efx_for_each_rx_queue(rx_queue, efx) {
1242                         if (rx_pending == EFX_RX_FLUSH_COUNT)
1243                                 break;
1244                         if (rx_queue->flushed == FLUSH_FAILED ||
1245                             rx_queue->flushed == FLUSH_NONE) {
1246                                 efx_flush_rx_queue(rx_queue);
1247                                 ++rx_pending;
1248                         }
1249                 }
1250                 efx_for_each_tx_queue(tx_queue, efx) {
1251                         if (tx_queue->flushed != FLUSH_DONE)
1252                                 ++tx_pending;
1253                 }
1254
1255                 if (rx_pending == 0 && tx_pending == 0)
1256                         return 0;
1257
1258                 msleep(EFX_FLUSH_INTERVAL);
1259                 efx_poll_flush_events(efx);
1260         }
1261
1262         /* Mark the queues as all flushed. We're going to return failure
1263          * leading to a reset, or fake up success anyway */
1264         efx_for_each_tx_queue(tx_queue, efx) {
1265                 if (tx_queue->flushed != FLUSH_DONE)
1266                         netif_err(efx, hw, efx->net_dev,
1267                                   "tx queue %d flush command timed out\n",
1268                                   tx_queue->queue);
1269                 tx_queue->flushed = FLUSH_DONE;
1270         }
1271         efx_for_each_rx_queue(rx_queue, efx) {
1272                 if (rx_queue->flushed != FLUSH_DONE)
1273                         netif_err(efx, hw, efx->net_dev,
1274                                   "rx queue %d flush command timed out\n",
1275                                   efx_rx_queue_index(rx_queue));
1276                 rx_queue->flushed = FLUSH_DONE;
1277         }
1278
1279         return -ETIMEDOUT;
1280 }
1281
1282 /**************************************************************************
1283  *
1284  * Hardware interrupts
1285  * The hardware interrupt handler does very little work; all the event
1286  * queue processing is carried out by per-channel tasklets.
1287  *
1288  **************************************************************************/
1289
1290 /* Enable/disable/generate interrupts */
1291 static inline void efx_nic_interrupts(struct efx_nic *efx,
1292                                       bool enabled, bool force)
1293 {
1294         efx_oword_t int_en_reg_ker;
1295
1296         EFX_POPULATE_OWORD_3(int_en_reg_ker,
1297                              FRF_AZ_KER_INT_LEVE_SEL, efx->fatal_irq_level,
1298                              FRF_AZ_KER_INT_KER, force,
1299                              FRF_AZ_DRV_INT_EN_KER, enabled);
1300         efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1301 }
1302
1303 void efx_nic_enable_interrupts(struct efx_nic *efx)
1304 {
1305         struct efx_channel *channel;
1306
1307         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1308         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1309
1310         /* Enable interrupts */
1311         efx_nic_interrupts(efx, true, false);
1312
1313         /* Force processing of all the channels to get the EVQ RPTRs up to
1314            date */
1315         efx_for_each_channel(channel, efx)
1316                 efx_schedule_channel(channel);
1317 }
1318
1319 void efx_nic_disable_interrupts(struct efx_nic *efx)
1320 {
1321         /* Disable interrupts */
1322         efx_nic_interrupts(efx, false, false);
1323 }
1324
1325 /* Generate a test interrupt
1326  * Interrupt must already have been enabled, otherwise nasty things
1327  * may happen.
1328  */
1329 void efx_nic_generate_interrupt(struct efx_nic *efx)
1330 {
1331         efx_nic_interrupts(efx, true, true);
1332 }
1333
1334 /* Process a fatal interrupt
1335  * Disable bus mastering ASAP and schedule a reset
1336  */
1337 irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx)
1338 {
1339         struct falcon_nic_data *nic_data = efx->nic_data;
1340         efx_oword_t *int_ker = efx->irq_status.addr;
1341         efx_oword_t fatal_intr;
1342         int error, mem_perr;
1343
1344         efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1345         error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1346
1347         netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status "
1348                   EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1349                   EFX_OWORD_VAL(fatal_intr),
1350                   error ? "disabling bus mastering" : "no recognised error");
1351
1352         /* If this is a memory parity error dump which blocks are offending */
1353         mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) ||
1354                     EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER));
1355         if (mem_perr) {
1356                 efx_oword_t reg;
1357                 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1358                 netif_err(efx, hw, efx->net_dev,
1359                           "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n",
1360                           EFX_OWORD_VAL(reg));
1361         }
1362
1363         /* Disable both devices */
1364         pci_clear_master(efx->pci_dev);
1365         if (efx_nic_is_dual_func(efx))
1366                 pci_clear_master(nic_data->pci_dev2);
1367         efx_nic_disable_interrupts(efx);
1368
1369         /* Count errors and reset or disable the NIC accordingly */
1370         if (efx->int_error_count == 0 ||
1371             time_after(jiffies, efx->int_error_expire)) {
1372                 efx->int_error_count = 0;
1373                 efx->int_error_expire =
1374                         jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1375         }
1376         if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
1377                 netif_err(efx, hw, efx->net_dev,
1378                           "SYSTEM ERROR - reset scheduled\n");
1379                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1380         } else {
1381                 netif_err(efx, hw, efx->net_dev,
1382                           "SYSTEM ERROR - max number of errors seen."
1383                           "NIC will be disabled\n");
1384                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1385         }
1386
1387         return IRQ_HANDLED;
1388 }
1389
1390 /* Handle a legacy interrupt
1391  * Acknowledges the interrupt and schedule event queue processing.
1392  */
1393 static irqreturn_t efx_legacy_interrupt(int irq, void *dev_id)
1394 {
1395         struct efx_nic *efx = dev_id;
1396         efx_oword_t *int_ker = efx->irq_status.addr;
1397         irqreturn_t result = IRQ_NONE;
1398         struct efx_channel *channel;
1399         efx_dword_t reg;
1400         u32 queues;
1401         int syserr;
1402
1403         /* Read the ISR which also ACKs the interrupts */
1404         efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1405         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1406
1407         /* Check to see if we have a serious error condition */
1408         if (queues & (1U << efx->fatal_irq_level)) {
1409                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1410                 if (unlikely(syserr))
1411                         return efx_nic_fatal_interrupt(efx);
1412         }
1413
1414         if (queues != 0) {
1415                 if (EFX_WORKAROUND_15783(efx))
1416                         efx->irq_zero_count = 0;
1417
1418                 /* Schedule processing of any interrupting queues */
1419                 efx_for_each_channel(channel, efx) {
1420                         if (queues & 1)
1421                                 efx_schedule_channel(channel);
1422                         queues >>= 1;
1423                 }
1424                 result = IRQ_HANDLED;
1425
1426         } else if (EFX_WORKAROUND_15783(efx)) {
1427                 efx_qword_t *event;
1428
1429                 /* We can't return IRQ_HANDLED more than once on seeing ISR=0
1430                  * because this might be a shared interrupt. */
1431                 if (efx->irq_zero_count++ == 0)
1432                         result = IRQ_HANDLED;
1433
1434                 /* Ensure we schedule or rearm all event queues */
1435                 efx_for_each_channel(channel, efx) {
1436                         event = efx_event(channel, channel->eventq_read_ptr);
1437                         if (efx_event_present(event))
1438                                 efx_schedule_channel(channel);
1439                         else
1440                                 efx_nic_eventq_read_ack(channel);
1441                 }
1442         }
1443
1444         if (result == IRQ_HANDLED) {
1445                 efx->last_irq_cpu = raw_smp_processor_id();
1446                 netif_vdbg(efx, intr, efx->net_dev,
1447                            "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1448                            irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1449         }
1450
1451         return result;
1452 }
1453
1454 /* Handle an MSI interrupt
1455  *
1456  * Handle an MSI hardware interrupt.  This routine schedules event
1457  * queue processing.  No interrupt acknowledgement cycle is necessary.
1458  * Also, we never need to check that the interrupt is for us, since
1459  * MSI interrupts cannot be shared.
1460  */
1461 static irqreturn_t efx_msi_interrupt(int irq, void *dev_id)
1462 {
1463         struct efx_channel *channel = dev_id;
1464         struct efx_nic *efx = channel->efx;
1465         efx_oword_t *int_ker = efx->irq_status.addr;
1466         int syserr;
1467
1468         efx->last_irq_cpu = raw_smp_processor_id();
1469         netif_vdbg(efx, intr, efx->net_dev,
1470                    "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1471                    irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1472
1473         /* Check to see if we have a serious error condition */
1474         if (channel->channel == efx->fatal_irq_level) {
1475                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1476                 if (unlikely(syserr))
1477                         return efx_nic_fatal_interrupt(efx);
1478         }
1479
1480         /* Schedule processing of the channel */
1481         efx_schedule_channel(channel);
1482
1483         return IRQ_HANDLED;
1484 }
1485
1486
1487 /* Setup RSS indirection table.
1488  * This maps from the hash value of the packet to RXQ
1489  */
1490 void efx_nic_push_rx_indir_table(struct efx_nic *efx)
1491 {
1492         size_t i = 0;
1493         efx_dword_t dword;
1494
1495         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1496                 return;
1497
1498         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1499                      FR_BZ_RX_INDIRECTION_TBL_ROWS);
1500
1501         for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
1502                 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1503                                      efx->rx_indir_table[i]);
1504                 efx_writed_table(efx, &dword, FR_BZ_RX_INDIRECTION_TBL, i);
1505         }
1506 }
1507
1508 /* Hook interrupt handler(s)
1509  * Try MSI and then legacy interrupts.
1510  */
1511 int efx_nic_init_interrupt(struct efx_nic *efx)
1512 {
1513         struct efx_channel *channel;
1514         int rc;
1515
1516         if (!EFX_INT_MODE_USE_MSI(efx)) {
1517                 irq_handler_t handler;
1518                 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1519                         handler = efx_legacy_interrupt;
1520                 else
1521                         handler = falcon_legacy_interrupt_a1;
1522
1523                 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1524                                  efx->name, efx);
1525                 if (rc) {
1526                         netif_err(efx, drv, efx->net_dev,
1527                                   "failed to hook legacy IRQ %d\n",
1528                                   efx->pci_dev->irq);
1529                         goto fail1;
1530                 }
1531                 return 0;
1532         }
1533
1534         /* Hook MSI or MSI-X interrupt */
1535         efx_for_each_channel(channel, efx) {
1536                 rc = request_irq(channel->irq, efx_msi_interrupt,
1537                                  IRQF_PROBE_SHARED, /* Not shared */
1538                                  channel->name, channel);
1539                 if (rc) {
1540                         netif_err(efx, drv, efx->net_dev,
1541                                   "failed to hook IRQ %d\n", channel->irq);
1542                         goto fail2;
1543                 }
1544         }
1545
1546         return 0;
1547
1548  fail2:
1549         efx_for_each_channel(channel, efx)
1550                 free_irq(channel->irq, channel);
1551  fail1:
1552         return rc;
1553 }
1554
1555 void efx_nic_fini_interrupt(struct efx_nic *efx)
1556 {
1557         struct efx_channel *channel;
1558         efx_oword_t reg;
1559
1560         /* Disable MSI/MSI-X interrupts */
1561         efx_for_each_channel(channel, efx) {
1562                 if (channel->irq)
1563                         free_irq(channel->irq, channel);
1564         }
1565
1566         /* ACK legacy interrupt */
1567         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1568                 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1569         else
1570                 falcon_irq_ack_a1(efx);
1571
1572         /* Disable legacy interrupt */
1573         if (efx->legacy_irq)
1574                 free_irq(efx->legacy_irq, efx);
1575 }
1576
1577 u32 efx_nic_fpga_ver(struct efx_nic *efx)
1578 {
1579         efx_oword_t altera_build;
1580         efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
1581         return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
1582 }
1583
1584 void efx_nic_init_common(struct efx_nic *efx)
1585 {
1586         efx_oword_t temp;
1587
1588         /* Set positions of descriptor caches in SRAM. */
1589         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR,
1590                              efx->type->tx_dc_base / 8);
1591         efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
1592         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR,
1593                              efx->type->rx_dc_base / 8);
1594         efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
1595
1596         /* Set TX descriptor cache size. */
1597         BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
1598         EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
1599         efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
1600
1601         /* Set RX descriptor cache size.  Set low watermark to size-8, as
1602          * this allows most efficient prefetching.
1603          */
1604         BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
1605         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
1606         efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
1607         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
1608         efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
1609
1610         /* Program INT_KER address */
1611         EFX_POPULATE_OWORD_2(temp,
1612                              FRF_AZ_NORM_INT_VEC_DIS_KER,
1613                              EFX_INT_MODE_USE_MSI(efx),
1614                              FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1615         efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
1616
1617         if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx))
1618                 /* Use an interrupt level unused by event queues */
1619                 efx->fatal_irq_level = 0x1f;
1620         else
1621                 /* Use a valid MSI-X vector */
1622                 efx->fatal_irq_level = 0;
1623
1624         /* Enable all the genuinely fatal interrupts.  (They are still
1625          * masked by the overall interrupt mask, controlled by
1626          * falcon_interrupts()).
1627          *
1628          * Note: All other fatal interrupts are enabled
1629          */
1630         EFX_POPULATE_OWORD_3(temp,
1631                              FRF_AZ_ILL_ADR_INT_KER_EN, 1,
1632                              FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
1633                              FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
1634         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1635                 EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1);
1636         EFX_INVERT_OWORD(temp);
1637         efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
1638
1639         efx_nic_push_rx_indir_table(efx);
1640
1641         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1642          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1643          */
1644         efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
1645         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1646         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1647         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
1648         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
1649         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1650         /* Enable SW_EV to inherit in char driver - assume harmless here */
1651         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
1652         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1653         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
1654         /* Disable hardware watchdog which can misfire */
1655         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
1656         /* Squash TX of packets of 16 bytes or less */
1657         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1658                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
1659         efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
1660 }
1661
1662 /* Register dump */
1663
1664 #define REGISTER_REVISION_A     1
1665 #define REGISTER_REVISION_B     2
1666 #define REGISTER_REVISION_C     3
1667 #define REGISTER_REVISION_Z     3       /* latest revision */
1668
1669 struct efx_nic_reg {
1670         u32 offset:24;
1671         u32 min_revision:2, max_revision:2;
1672 };
1673
1674 #define REGISTER(name, min_rev, max_rev) {                              \
1675         FR_ ## min_rev ## max_rev ## _ ## name,                         \
1676         REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev    \
1677 }
1678 #define REGISTER_AA(name) REGISTER(name, A, A)
1679 #define REGISTER_AB(name) REGISTER(name, A, B)
1680 #define REGISTER_AZ(name) REGISTER(name, A, Z)
1681 #define REGISTER_BB(name) REGISTER(name, B, B)
1682 #define REGISTER_BZ(name) REGISTER(name, B, Z)
1683 #define REGISTER_CZ(name) REGISTER(name, C, Z)
1684
1685 static const struct efx_nic_reg efx_nic_regs[] = {
1686         REGISTER_AZ(ADR_REGION),
1687         REGISTER_AZ(INT_EN_KER),
1688         REGISTER_BZ(INT_EN_CHAR),
1689         REGISTER_AZ(INT_ADR_KER),
1690         REGISTER_BZ(INT_ADR_CHAR),
1691         /* INT_ACK_KER is WO */
1692         /* INT_ISR0 is RC */
1693         REGISTER_AZ(HW_INIT),
1694         REGISTER_CZ(USR_EV_CFG),
1695         REGISTER_AB(EE_SPI_HCMD),
1696         REGISTER_AB(EE_SPI_HADR),
1697         REGISTER_AB(EE_SPI_HDATA),
1698         REGISTER_AB(EE_BASE_PAGE),
1699         REGISTER_AB(EE_VPD_CFG0),
1700         /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
1701         /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
1702         /* PCIE_CORE_INDIRECT is indirect */
1703         REGISTER_AB(NIC_STAT),
1704         REGISTER_AB(GPIO_CTL),
1705         REGISTER_AB(GLB_CTL),
1706         /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
1707         REGISTER_BZ(DP_CTRL),
1708         REGISTER_AZ(MEM_STAT),
1709         REGISTER_AZ(CS_DEBUG),
1710         REGISTER_AZ(ALTERA_BUILD),
1711         REGISTER_AZ(CSR_SPARE),
1712         REGISTER_AB(PCIE_SD_CTL0123),
1713         REGISTER_AB(PCIE_SD_CTL45),
1714         REGISTER_AB(PCIE_PCS_CTL_STAT),
1715         /* DEBUG_DATA_OUT is not used */
1716         /* DRV_EV is WO */
1717         REGISTER_AZ(EVQ_CTL),
1718         REGISTER_AZ(EVQ_CNT1),
1719         REGISTER_AZ(EVQ_CNT2),
1720         REGISTER_AZ(BUF_TBL_CFG),
1721         REGISTER_AZ(SRM_RX_DC_CFG),
1722         REGISTER_AZ(SRM_TX_DC_CFG),
1723         REGISTER_AZ(SRM_CFG),
1724         /* BUF_TBL_UPD is WO */
1725         REGISTER_AZ(SRM_UPD_EVQ),
1726         REGISTER_AZ(SRAM_PARITY),
1727         REGISTER_AZ(RX_CFG),
1728         REGISTER_BZ(RX_FILTER_CTL),
1729         /* RX_FLUSH_DESCQ is WO */
1730         REGISTER_AZ(RX_DC_CFG),
1731         REGISTER_AZ(RX_DC_PF_WM),
1732         REGISTER_BZ(RX_RSS_TKEY),
1733         /* RX_NODESC_DROP is RC */
1734         REGISTER_AA(RX_SELF_RST),
1735         /* RX_DEBUG, RX_PUSH_DROP are not used */
1736         REGISTER_CZ(RX_RSS_IPV6_REG1),
1737         REGISTER_CZ(RX_RSS_IPV6_REG2),
1738         REGISTER_CZ(RX_RSS_IPV6_REG3),
1739         /* TX_FLUSH_DESCQ is WO */
1740         REGISTER_AZ(TX_DC_CFG),
1741         REGISTER_AA(TX_CHKSM_CFG),
1742         REGISTER_AZ(TX_CFG),
1743         /* TX_PUSH_DROP is not used */
1744         REGISTER_AZ(TX_RESERVED),
1745         REGISTER_BZ(TX_PACE),
1746         /* TX_PACE_DROP_QID is RC */
1747         REGISTER_BB(TX_VLAN),
1748         REGISTER_BZ(TX_IPFIL_PORTEN),
1749         REGISTER_AB(MD_TXD),
1750         REGISTER_AB(MD_RXD),
1751         REGISTER_AB(MD_CS),
1752         REGISTER_AB(MD_PHY_ADR),
1753         REGISTER_AB(MD_ID),
1754         /* MD_STAT is RC */
1755         REGISTER_AB(MAC_STAT_DMA),
1756         REGISTER_AB(MAC_CTRL),
1757         REGISTER_BB(GEN_MODE),
1758         REGISTER_AB(MAC_MC_HASH_REG0),
1759         REGISTER_AB(MAC_MC_HASH_REG1),
1760         REGISTER_AB(GM_CFG1),
1761         REGISTER_AB(GM_CFG2),
1762         /* GM_IPG and GM_HD are not used */
1763         REGISTER_AB(GM_MAX_FLEN),
1764         /* GM_TEST is not used */
1765         REGISTER_AB(GM_ADR1),
1766         REGISTER_AB(GM_ADR2),
1767         REGISTER_AB(GMF_CFG0),
1768         REGISTER_AB(GMF_CFG1),
1769         REGISTER_AB(GMF_CFG2),
1770         REGISTER_AB(GMF_CFG3),
1771         REGISTER_AB(GMF_CFG4),
1772         REGISTER_AB(GMF_CFG5),
1773         REGISTER_BB(TX_SRC_MAC_CTL),
1774         REGISTER_AB(XM_ADR_LO),
1775         REGISTER_AB(XM_ADR_HI),
1776         REGISTER_AB(XM_GLB_CFG),
1777         REGISTER_AB(XM_TX_CFG),
1778         REGISTER_AB(XM_RX_CFG),
1779         REGISTER_AB(XM_MGT_INT_MASK),
1780         REGISTER_AB(XM_FC),
1781         REGISTER_AB(XM_PAUSE_TIME),
1782         REGISTER_AB(XM_TX_PARAM),
1783         REGISTER_AB(XM_RX_PARAM),
1784         /* XM_MGT_INT_MSK (note no 'A') is RC */
1785         REGISTER_AB(XX_PWR_RST),
1786         REGISTER_AB(XX_SD_CTL),
1787         REGISTER_AB(XX_TXDRV_CTL),
1788         /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
1789         /* XX_CORE_STAT is partly RC */
1790 };
1791
1792 struct efx_nic_reg_table {
1793         u32 offset:24;
1794         u32 min_revision:2, max_revision:2;
1795         u32 step:6, rows:21;
1796 };
1797
1798 #define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \
1799         offset,                                                         \
1800         REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev,   \
1801         step, rows                                                      \
1802 }
1803 #define REGISTER_TABLE(name, min_rev, max_rev)                          \
1804         REGISTER_TABLE_DIMENSIONS(                                      \
1805                 name, FR_ ## min_rev ## max_rev ## _ ## name,           \
1806                 min_rev, max_rev,                                       \
1807                 FR_ ## min_rev ## max_rev ## _ ## name ## _STEP,        \
1808                 FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
1809 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A)
1810 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z)
1811 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B)
1812 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z)
1813 #define REGISTER_TABLE_BB_CZ(name)                                      \
1814         REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B,           \
1815                                   FR_BZ_ ## name ## _STEP,              \
1816                                   FR_BB_ ## name ## _ROWS),             \
1817         REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z,           \
1818                                   FR_BZ_ ## name ## _STEP,              \
1819                                   FR_CZ_ ## name ## _ROWS)
1820 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z)
1821
1822 static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
1823         /* DRIVER is not used */
1824         /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
1825         REGISTER_TABLE_BB(TX_IPFIL_TBL),
1826         REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
1827         REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
1828         REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
1829         REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
1830         REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
1831         REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
1832         REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
1833         /* The register buffer is allocated with slab, so we can't
1834          * reasonably read all of the buffer table (up to 8MB!).
1835          * However this driver will only use a few entries.  Reading
1836          * 1K entries allows for some expansion of queue count and
1837          * size before we need to change the version. */
1838         REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
1839                                   A, A, 8, 1024),
1840         REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
1841                                   B, Z, 8, 1024),
1842         /* RX_FILTER_TBL{0,1} is huge and not used by this driver */
1843         REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
1844         REGISTER_TABLE_BB_CZ(TIMER_TBL),
1845         REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
1846         REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
1847         /* TX_FILTER_TBL0 is huge and not used by this driver */
1848         REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
1849         REGISTER_TABLE_CZ(MC_TREG_SMEM),
1850         /* MSIX_PBA_TABLE is not mapped */
1851         /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
1852 };
1853
1854 size_t efx_nic_get_regs_len(struct efx_nic *efx)
1855 {
1856         const struct efx_nic_reg *reg;
1857         const struct efx_nic_reg_table *table;
1858         size_t len = 0;
1859
1860         for (reg = efx_nic_regs;
1861              reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
1862              reg++)
1863                 if (efx->type->revision >= reg->min_revision &&
1864                     efx->type->revision <= reg->max_revision)
1865                         len += sizeof(efx_oword_t);
1866
1867         for (table = efx_nic_reg_tables;
1868              table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
1869              table++)
1870                 if (efx->type->revision >= table->min_revision &&
1871                     efx->type->revision <= table->max_revision)
1872                         len += table->rows * min_t(size_t, table->step, 16);
1873
1874         return len;
1875 }
1876
1877 void efx_nic_get_regs(struct efx_nic *efx, void *buf)
1878 {
1879         const struct efx_nic_reg *reg;
1880         const struct efx_nic_reg_table *table;
1881
1882         for (reg = efx_nic_regs;
1883              reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
1884              reg++) {
1885                 if (efx->type->revision >= reg->min_revision &&
1886                     efx->type->revision <= reg->max_revision) {
1887                         efx_reado(efx, (efx_oword_t *)buf, reg->offset);
1888                         buf += sizeof(efx_oword_t);
1889                 }
1890         }
1891
1892         for (table = efx_nic_reg_tables;
1893              table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
1894              table++) {
1895                 size_t size, i;
1896
1897                 if (!(efx->type->revision >= table->min_revision &&
1898                       efx->type->revision <= table->max_revision))
1899                         continue;
1900
1901                 size = min_t(size_t, table->step, 16);
1902
1903                 for (i = 0; i < table->rows; i++) {
1904                         switch (table->step) {
1905                         case 4: /* 32-bit register or SRAM */
1906                                 efx_readd_table(efx, buf, table->offset, i);
1907                                 break;
1908                         case 8: /* 64-bit SRAM */
1909                                 efx_sram_readq(efx,
1910                                                efx->membase + table->offset,
1911                                                buf, i);
1912                                 break;
1913                         case 16: /* 128-bit register */
1914                                 efx_reado_table(efx, buf, table->offset, i);
1915                                 break;
1916                         case 32: /* 128-bit register, interleaved */
1917                                 efx_reado_table(efx, buf, table->offset, 2 * i);
1918                                 break;
1919                         default:
1920                                 WARN_ON(1);
1921                                 return;
1922                         }
1923                         buf += size;
1924                 }
1925         }
1926 }