Pileus Git - ~andy/linux/blob - drivers/net/qlcnic/qlcnic_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c)  2009-2010 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9
  10 #include <linux/slab.h>
  11 #include <net/ip.h>
  12
  13 #define MASK(n) ((1ULL<<(n))-1)
  14 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  15
  16 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  17
  18 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  19 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  20 #define CRB_WINDOW_2M   (0x130060)
  21 #define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  22 #define CRB_INDIRECT_2M (0x1e0000UL)
  23
  24
  25 #ifndef readq
  26 static inline u64 readq(void __iomem *addr)
  27 {
  28         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  29 }
  30 #endif
  31
  32 #ifndef writeq
  33 static inline void writeq(u64 val, void __iomem *addr)
  34 {
  35         writel(((u32) (val)), (addr));
  36         writel(((u32) (val >> 32)), (addr + 4));
  37 }
  38 #endif
  39
  40 static const struct crb_128M_2M_block_map
  41 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  42     {{{0, 0,         0,         0} } },         /* 0: PCI */
  43     {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
  44           {1, 0x0110000, 0x0120000, 0x130000},
  45           {1, 0x0120000, 0x0122000, 0x124000},
  46           {1, 0x0130000, 0x0132000, 0x126000},
  47           {1, 0x0140000, 0x0142000, 0x128000},
  48           {1, 0x0150000, 0x0152000, 0x12a000},
  49           {1, 0x0160000, 0x0170000, 0x110000},
  50           {1, 0x0170000, 0x0172000, 0x12e000},
  51           {0, 0x0000000, 0x0000000, 0x000000},
  52           {0, 0x0000000, 0x0000000, 0x000000},
  53           {0, 0x0000000, 0x0000000, 0x000000},
  54           {0, 0x0000000, 0x0000000, 0x000000},
  55           {0, 0x0000000, 0x0000000, 0x000000},
  56           {0, 0x0000000, 0x0000000, 0x000000},
  57           {1, 0x01e0000, 0x01e0800, 0x122000},
  58           {0, 0x0000000, 0x0000000, 0x000000} } },
  59         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  60     {{{0, 0,         0,         0} } },     /* 3: */
  61     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  62     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
  63     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
  64     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
  65     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
  66       {0, 0x0000000, 0x0000000, 0x000000},
  67       {0, 0x0000000, 0x0000000, 0x000000},
  68       {0, 0x0000000, 0x0000000, 0x000000},
  69       {0, 0x0000000, 0x0000000, 0x000000},
  70       {0, 0x0000000, 0x0000000, 0x000000},
  71       {0, 0x0000000, 0x0000000, 0x000000},
  72       {0, 0x0000000, 0x0000000, 0x000000},
  73       {0, 0x0000000, 0x0000000, 0x000000},
  74       {0, 0x0000000, 0x0000000, 0x000000},
  75       {0, 0x0000000, 0x0000000, 0x000000},
  76       {0, 0x0000000, 0x0000000, 0x000000},
  77       {0, 0x0000000, 0x0000000, 0x000000},
  78       {0, 0x0000000, 0x0000000, 0x000000},
  79       {0, 0x0000000, 0x0000000, 0x000000},
  80       {1, 0x08f0000, 0x08f2000, 0x172000} } },
  81     {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
  82       {0, 0x0000000, 0x0000000, 0x000000},
  83       {0, 0x0000000, 0x0000000, 0x000000},
  84       {0, 0x0000000, 0x0000000, 0x000000},
  85       {0, 0x0000000, 0x0000000, 0x000000},
  86       {0, 0x0000000, 0x0000000, 0x000000},
  87       {0, 0x0000000, 0x0000000, 0x000000},
  88       {0, 0x0000000, 0x0000000, 0x000000},
  89       {0, 0x0000000, 0x0000000, 0x000000},
  90       {0, 0x0000000, 0x0000000, 0x000000},
  91       {0, 0x0000000, 0x0000000, 0x000000},
  92       {0, 0x0000000, 0x0000000, 0x000000},
  93       {0, 0x0000000, 0x0000000, 0x000000},
  94       {0, 0x0000000, 0x0000000, 0x000000},
  95       {0, 0x0000000, 0x0000000, 0x000000},
  96       {1, 0x09f0000, 0x09f2000, 0x176000} } },
  97     {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
  98       {0, 0x0000000, 0x0000000, 0x000000},
  99       {0, 0x0000000, 0x0000000, 0x000000},
 100       {0, 0x0000000, 0x0000000, 0x000000},
 101       {0, 0x0000000, 0x0000000, 0x000000},
 102       {0, 0x0000000, 0x0000000, 0x000000},
 103       {0, 0x0000000, 0x0000000, 0x000000},
 104       {0, 0x0000000, 0x0000000, 0x000000},
 105       {0, 0x0000000, 0x0000000, 0x000000},
 106       {0, 0x0000000, 0x0000000, 0x000000},
 107       {0, 0x0000000, 0x0000000, 0x000000},
 108       {0, 0x0000000, 0x0000000, 0x000000},
 109       {0, 0x0000000, 0x0000000, 0x000000},
 110       {0, 0x0000000, 0x0000000, 0x000000},
 111       {0, 0x0000000, 0x0000000, 0x000000},
 112       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 113     {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
 114       {0, 0x0000000, 0x0000000, 0x000000},
 115       {0, 0x0000000, 0x0000000, 0x000000},
 116       {0, 0x0000000, 0x0000000, 0x000000},
 117       {0, 0x0000000, 0x0000000, 0x000000},
 118       {0, 0x0000000, 0x0000000, 0x000000},
 119       {0, 0x0000000, 0x0000000, 0x000000},
 120       {0, 0x0000000, 0x0000000, 0x000000},
 121       {0, 0x0000000, 0x0000000, 0x000000},
 122       {0, 0x0000000, 0x0000000, 0x000000},
 123       {0, 0x0000000, 0x0000000, 0x000000},
 124       {0, 0x0000000, 0x0000000, 0x000000},
 125       {0, 0x0000000, 0x0000000, 0x000000},
 126       {0, 0x0000000, 0x0000000, 0x000000},
 127       {0, 0x0000000, 0x0000000, 0x000000},
 128       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 129         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 130         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 131         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 132         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 133         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 134         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 135         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 136         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 137         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 138         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 139         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 140         {{{0, 0,         0,         0} } },     /* 23: */
 141         {{{0, 0,         0,         0} } },     /* 24: */
 142         {{{0, 0,         0,         0} } },     /* 25: */
 143         {{{0, 0,         0,         0} } },     /* 26: */
 144         {{{0, 0,         0,         0} } },     /* 27: */
 145         {{{0, 0,         0,         0} } },     /* 28: */
 146         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 147     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 148     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 149         {{{0} } },                              /* 32: PCI */
 150         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 151           {1, 0x2110000, 0x2120000, 0x130000},
 152           {1, 0x2120000, 0x2122000, 0x124000},
 153           {1, 0x2130000, 0x2132000, 0x126000},
 154           {1, 0x2140000, 0x2142000, 0x128000},
 155           {1, 0x2150000, 0x2152000, 0x12a000},
 156           {1, 0x2160000, 0x2170000, 0x110000},
 157           {1, 0x2170000, 0x2172000, 0x12e000},
 158           {0, 0x0000000, 0x0000000, 0x000000},
 159           {0, 0x0000000, 0x0000000, 0x000000},
 160           {0, 0x0000000, 0x0000000, 0x000000},
 161           {0, 0x0000000, 0x0000000, 0x000000},
 162           {0, 0x0000000, 0x0000000, 0x000000},
 163           {0, 0x0000000, 0x0000000, 0x000000},
 164           {0, 0x0000000, 0x0000000, 0x000000},
 165           {0, 0x0000000, 0x0000000, 0x000000} } },
 166         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 167         {{{0} } },                              /* 35: */
 168         {{{0} } },                              /* 36: */
 169         {{{0} } },                              /* 37: */
 170         {{{0} } },                              /* 38: */
 171         {{{0} } },                              /* 39: */
 172         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 173         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 174         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 175         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 176         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 177         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 178         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 179         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 180         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 181         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 182         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 183         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 184         {{{0} } },                              /* 52: */
 185         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 186         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 187         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 188         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 189         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 190         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 191         {{{0} } },                              /* 59: I2C0 */
 192         {{{0} } },                              /* 60: I2C1 */
 193         {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
 194         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 195         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 196 };
 197
 198 /*
 199  * top 12 bits of crb internal address (hub, agent)
 200  */
 201 static const unsigned crb_hub_agt[64] = {
 202         0,
 203         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 204         QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
 205         QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
 206         0,
 207         QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
 208         QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
 209         QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
 210         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
 211         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
 212         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
 213         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
 214         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 215         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 216         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 217         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
 218         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 219         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
 220         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
 221         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
 222         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
 223         QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
 224         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
 225         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
 226         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
 227         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
 228         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
 229         0,
 230         QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
 231         QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
 232         0,
 233         QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
 234         0,
 235         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 236         QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
 237         0,
 238         0,
 239         0,
 240         0,
 241         0,
 242         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 243         0,
 244         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
 245         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
 246         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
 247         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
 248         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
 249         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
 250         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
 251         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 252         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 253         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 254         0,
 255         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
 256         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
 257         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
 258         QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
 259         0,
 260         QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
 261         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
 262         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
 263         0,
 264         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
 265         0,
 266 };
 267
 268 /*  PCI Windowing for DDR regions.  */
 269
 270 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
 271
 272 int
 273 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
 274 {
 275         int done = 0, timeout = 0;
 276
 277         while (!done) {
 278                 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
 279                 if (done == 1)
 280                         break;
 281                 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
 282                         dev_err(&adapter->pdev->dev,
 283                                 "Failed to acquire sem=%d lock; holdby=%d\n",
 284                                 sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
 285                         return -EIO;
 286                 }
 287                 msleep(1);
 288         }
 289
 290         if (id_reg)
 291                 QLCWR32(adapter, id_reg, adapter->portnum);
 292
 293         return 0;
 294 }
 295
 296 void
 297 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
 298 {
 299         QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
 300 }
 301
 302 static int
 303 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
 304                 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
 305 {
 306         u32 i, producer, consumer;
 307         struct qlcnic_cmd_buffer *pbuf;
 308         struct cmd_desc_type0 *cmd_desc;
 309         struct qlcnic_host_tx_ring *tx_ring;
 310
 311         i = 0;
 312
 313         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 314                 return -EIO;
 315
 316         tx_ring = adapter->tx_ring;
 317         __netif_tx_lock_bh(tx_ring->txq);
 318
 319         producer = tx_ring->producer;
 320         consumer = tx_ring->sw_consumer;
 321
 322         if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
 323                 netif_tx_stop_queue(tx_ring->txq);
 324                 smp_mb();
 325                 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
 326                         if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
 327                                 netif_tx_wake_queue(tx_ring->txq);
 328                 } else {
 329                         adapter->stats.xmit_off++;
 330                         __netif_tx_unlock_bh(tx_ring->txq);
 331                         return -EBUSY;
 332                 }
 333         }
 334
 335         do {
 336                 cmd_desc = &cmd_desc_arr[i];
 337
 338                 pbuf = &tx_ring->cmd_buf_arr[producer];
 339                 pbuf->skb = NULL;
 340                 pbuf->frag_count = 0;
 341
 342                 memcpy(&tx_ring->desc_head[producer],
 343                         &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
 344
 345                 producer = get_next_index(producer, tx_ring->num_desc);
 346                 i++;
 347
 348         } while (i != nr_desc);
 349
 350         tx_ring->producer = producer;
 351
 352         qlcnic_update_cmd_producer(adapter, tx_ring);
 353
 354         __netif_tx_unlock_bh(tx_ring->txq);
 355
 356         return 0;
 357 }
 358
 359 static int
 360 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
 361                                 __le16 vlan_id, unsigned op)
 362 {
 363         struct qlcnic_nic_req req;
 364         struct qlcnic_mac_req *mac_req;
 365         struct qlcnic_vlan_req *vlan_req;
 366         u64 word;
 367
 368         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 369         req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
 370
 371         word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
 372         req.req_hdr = cpu_to_le64(word);
 373
 374         mac_req = (struct qlcnic_mac_req *)&req.words[0];
 375         mac_req->op = op;
 376         memcpy(mac_req->mac_addr, addr, 6);
 377
 378         vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
 379         vlan_req->vlan_id = vlan_id;
 380
 381         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 382 }
 383
 384 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr)
 385 {
 386         struct list_head *head;
 387         struct qlcnic_mac_list_s *cur;
 388
 389         /* look up if already exists */
 390         list_for_each(head, &adapter->mac_list) {
 391                 cur = list_entry(head, struct qlcnic_mac_list_s, list);
 392                 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
 393                         return 0;
 394         }
 395
 396         cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
 397         if (cur == NULL) {
 398                 dev_err(&adapter->netdev->dev,
 399                         "failed to add mac address filter\n");
 400                 return -ENOMEM;
 401         }
 402         memcpy(cur->mac_addr, addr, ETH_ALEN);
 403
 404         if (qlcnic_sre_macaddr_change(adapter,
 405                                 cur->mac_addr, 0, QLCNIC_MAC_ADD)) {
 406                 kfree(cur);
 407                 return -EIO;
 408         }
 409
 410         list_add_tail(&cur->list, &adapter->mac_list);
 411         return 0;
 412 }
 413
 414 void qlcnic_set_multi(struct net_device *netdev)
 415 {
 416         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 417         struct netdev_hw_addr *ha;
 418         u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 419         u32 mode = VPORT_MISS_MODE_DROP;
 420
 421         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 422                 return;
 423
 424         qlcnic_nic_add_mac(adapter, adapter->mac_addr);
 425         qlcnic_nic_add_mac(adapter, bcast_addr);
 426
 427         if (netdev->flags & IFF_PROMISC) {
 428                 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
 429                         mode = VPORT_MISS_MODE_ACCEPT_ALL;
 430                 goto send_fw_cmd;
 431         }
 432
 433         if ((netdev->flags & IFF_ALLMULTI) ||
 434             (netdev_mc_count(netdev) > adapter->max_mc_count)) {
 435                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 436                 goto send_fw_cmd;
 437         }
 438
 439         if (!netdev_mc_empty(netdev)) {
 440                 netdev_for_each_mc_addr(ha, netdev) {
 441                         qlcnic_nic_add_mac(adapter, ha->addr);
 442                 }
 443         }
 444
 445 send_fw_cmd:
 446         qlcnic_nic_set_promisc(adapter, mode);
 447 }
 448
 449 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
 450 {
 451         struct qlcnic_nic_req req;
 452         u64 word;
 453
 454         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 455
 456         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 457
 458         word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
 459                         ((u64)adapter->portnum << 16);
 460         req.req_hdr = cpu_to_le64(word);
 461
 462         req.words[0] = cpu_to_le64(mode);
 463
 464         return qlcnic_send_cmd_descs(adapter,
 465                                 (struct cmd_desc_type0 *)&req, 1);
 466 }
 467
 468 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
 469 {
 470         struct qlcnic_mac_list_s *cur;
 471         struct list_head *head = &adapter->mac_list;
 472
 473         while (!list_empty(head)) {
 474                 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
 475                 qlcnic_sre_macaddr_change(adapter,
 476                                 cur->mac_addr, 0, QLCNIC_MAC_DEL);
 477                 list_del(&cur->list);
 478                 kfree(cur);
 479         }
 480 }
 481
 482 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
 483 {
 484         struct qlcnic_filter *tmp_fil;
 485         struct hlist_node *tmp_hnode, *n;
 486         struct hlist_head *head;
 487         int i;
 488
 489         for (i = 0; i < adapter->fhash.fmax; i++) {
 490                 head = &(adapter->fhash.fhead[i]);
 491
 492                 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode)
 493                 {
 494                         if (jiffies >
 495                                 (QLCNIC_FILTER_AGE * HZ + tmp_fil->ftime)) {
 496                                 qlcnic_sre_macaddr_change(adapter,
 497                                         tmp_fil->faddr, tmp_fil->vlan_id,
 498                                         tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 499                                         QLCNIC_MAC_DEL);
 500                                 spin_lock_bh(&adapter->mac_learn_lock);
 501                                 adapter->fhash.fnum--;
 502                                 hlist_del(&tmp_fil->fnode);
 503                                 spin_unlock_bh(&adapter->mac_learn_lock);
 504                                 kfree(tmp_fil);
 505                         }
 506                 }
 507         }
 508 }
 509
 510 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
 511 {
 512         struct qlcnic_filter *tmp_fil;
 513         struct hlist_node *tmp_hnode, *n;
 514         struct hlist_head *head;
 515         int i;
 516
 517         for (i = 0; i < adapter->fhash.fmax; i++) {
 518                 head = &(adapter->fhash.fhead[i]);
 519
 520                 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
 521                         qlcnic_sre_macaddr_change(adapter, tmp_fil->faddr,
 522                                 tmp_fil->vlan_id, tmp_fil->vlan_id ?
 523                                 QLCNIC_MAC_VLAN_DEL :  QLCNIC_MAC_DEL);
 524                         spin_lock_bh(&adapter->mac_learn_lock);
 525                         adapter->fhash.fnum--;
 526                         hlist_del(&tmp_fil->fnode);
 527                         spin_unlock_bh(&adapter->mac_learn_lock);
 528                         kfree(tmp_fil);
 529                 }
 530         }
 531 }
 532
 533 #define QLCNIC_CONFIG_INTR_COALESCE     3
 534
 535 /*
 536  * Send the interrupt coalescing parameter set by ethtool to the card.
 537  */
 538 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
 539 {
 540         struct qlcnic_nic_req req;
 541         u64 word[6];
 542         int rv, i;
 543
 544         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 545
 546         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 547
 548         word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
 549         req.req_hdr = cpu_to_le64(word[0]);
 550
 551         memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
 552         for (i = 0; i < 6; i++)
 553                 req.words[i] = cpu_to_le64(word[i]);
 554
 555         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 556         if (rv != 0)
 557                 dev_err(&adapter->netdev->dev,
 558                         "Could not send interrupt coalescing parameters\n");
 559
 560         return rv;
 561 }
 562
 563 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
 564 {
 565         struct qlcnic_nic_req req;
 566         u64 word;
 567         int rv;
 568
 569         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 570
 571         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 572
 573         word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
 574         req.req_hdr = cpu_to_le64(word);
 575
 576         req.words[0] = cpu_to_le64(enable);
 577
 578         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 579         if (rv != 0)
 580                 dev_err(&adapter->netdev->dev,
 581                         "Could not send configure hw lro request\n");
 582
 583         return rv;
 584 }
 585
 586 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
 587 {
 588         struct qlcnic_nic_req req;
 589         u64 word;
 590         int rv;
 591
 592         if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
 593                 return 0;
 594
 595         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 596
 597         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 598
 599         word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
 600                 ((u64)adapter->portnum << 16);
 601         req.req_hdr = cpu_to_le64(word);
 602
 603         req.words[0] = cpu_to_le64(enable);
 604
 605         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 606         if (rv != 0)
 607                 dev_err(&adapter->netdev->dev,
 608                         "Could not send configure bridge mode request\n");
 609
 610         adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
 611
 612         return rv;
 613 }
 614
 615
 616 #define RSS_HASHTYPE_IP_TCP     0x3
 617
 618 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
 619 {
 620         struct qlcnic_nic_req req;
 621         u64 word;
 622         int i, rv;
 623
 624         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 625                         0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 626                         0x255b0ec26d5a56daULL };
 627
 628
 629         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 630         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 631
 632         word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
 633         req.req_hdr = cpu_to_le64(word);
 634
 635         /*
 636          * RSS request:
 637          * bits 3-0: hash_method
 638          *      5-4: hash_type_ipv4
 639          *      7-6: hash_type_ipv6
 640          *        8: enable
 641          *        9: use indirection table
 642          *    47-10: reserved
 643          *    63-48: indirection table mask
 644          */
 645         word =  ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
 646                 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
 647                 ((u64)(enable & 0x1) << 8) |
 648                 ((0x7ULL) << 48);
 649         req.words[0] = cpu_to_le64(word);
 650         for (i = 0; i < 5; i++)
 651                 req.words[i+1] = cpu_to_le64(key[i]);
 652
 653         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 654         if (rv != 0)
 655                 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
 656
 657         return rv;
 658 }
 659
 660 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd)
 661 {
 662         struct qlcnic_nic_req req;
 663         struct qlcnic_ipaddr *ipa;
 664         u64 word;
 665         int rv;
 666
 667         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 668         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 669
 670         word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
 671         req.req_hdr = cpu_to_le64(word);
 672
 673         req.words[0] = cpu_to_le64(cmd);
 674         ipa = (struct qlcnic_ipaddr *)&req.words[1];
 675         ipa->ipv4 = ip;
 676
 677         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 678         if (rv != 0)
 679                 dev_err(&adapter->netdev->dev,
 680                                 "could not notify %s IP 0x%x reuqest\n",
 681                                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
 682
 683         return rv;
 684 }
 685
 686 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
 687 {
 688         struct qlcnic_nic_req req;
 689         u64 word;
 690         int rv;
 691
 692         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 693         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 694
 695         word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
 696         req.req_hdr = cpu_to_le64(word);
 697         req.words[0] = cpu_to_le64(enable | (enable << 8));
 698
 699         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 700         if (rv != 0)
 701                 dev_err(&adapter->netdev->dev,
 702                                 "could not configure link notification\n");
 703
 704         return rv;
 705 }
 706
 707 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
 708 {
 709         struct qlcnic_nic_req req;
 710         u64 word;
 711         int rv;
 712
 713         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 714         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 715
 716         word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
 717                 ((u64)adapter->portnum << 16) |
 718                 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
 719
 720         req.req_hdr = cpu_to_le64(word);
 721
 722         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 723         if (rv != 0)
 724                 dev_err(&adapter->netdev->dev,
 725                                  "could not cleanup lro flows\n");
 726
 727         return rv;
 728 }
 729
 730 /*
 731  * qlcnic_change_mtu - Change the Maximum Transfer Unit
 732  * @returns 0 on success, negative on failure
 733  */
 734
 735 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
 736 {
 737         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 738         int rc = 0;
 739
 740         if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
 741                 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
 742                         " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
 743                 return -EINVAL;
 744         }
 745
 746         rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
 747
 748         if (!rc)
 749                 netdev->mtu = mtu;
 750
 751         return rc;
 752 }
 753
 754 /*
 755  * Changes the CRB window to the specified window.
 756  */
 757  /* Returns < 0 if off is not valid,
 758  *       1 if window access is needed. 'off' is set to offset from
 759  *         CRB space in 128M pci map
 760  *       0 if no window access is needed. 'off' is set to 2M addr
 761  * In: 'off' is offset from base in 128M pci map
 762  */
 763 static int
 764 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
 765                 ulong off, void __iomem **addr)
 766 {
 767         const struct crb_128M_2M_sub_block_map *m;
 768
 769         if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
 770                 return -EINVAL;
 771
 772         off -= QLCNIC_PCI_CRBSPACE;
 773
 774         /*
 775          * Try direct map
 776          */
 777         m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
 778
 779         if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
 780                 *addr = adapter->ahw.pci_base0 + m->start_2M +
 781                         (off - m->start_128M);
 782                 return 0;
 783         }
 784
 785         /*
 786          * Not in direct map, use crb window
 787          */
 788         *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
 789         return 1;
 790 }
 791
 792 /*
 793  * In: 'off' is offset from CRB space in 128M pci map
 794  * Out: 'off' is 2M pci map addr
 795  * side effect: lock crb window
 796  */
 797 static int
 798 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
 799 {
 800         u32 window;
 801         void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
 802
 803         off -= QLCNIC_PCI_CRBSPACE;
 804
 805         window = CRB_HI(off);
 806         if (window == 0) {
 807                 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
 808                 return -EIO;
 809         }
 810
 811         writel(window, addr);
 812         if (readl(addr) != window) {
 813                 if (printk_ratelimit())
 814                         dev_warn(&adapter->pdev->dev,
 815                                 "failed to set CRB window to %d off 0x%lx\n",
 816                                 window, off);
 817                 return -EIO;
 818         }
 819         return 0;
 820 }
 821
 822 int
 823 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
 824 {
 825         unsigned long flags;
 826         int rv;
 827         void __iomem *addr = NULL;
 828
 829         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 830
 831         if (rv == 0) {
 832                 writel(data, addr);
 833                 return 0;
 834         }
 835
 836         if (rv > 0) {
 837                 /* indirect access */
 838                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 839                 crb_win_lock(adapter);
 840                 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
 841                 if (!rv)
 842                         writel(data, addr);
 843                 crb_win_unlock(adapter);
 844                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 845                 return rv;
 846         }
 847
 848         dev_err(&adapter->pdev->dev,
 849                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 850         dump_stack();
 851         return -EIO;
 852 }
 853
 854 u32
 855 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
 856 {
 857         unsigned long flags;
 858         int rv;
 859         u32 data = -1;
 860         void __iomem *addr = NULL;
 861
 862         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 863
 864         if (rv == 0)
 865                 return readl(addr);
 866
 867         if (rv > 0) {
 868                 /* indirect access */
 869                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 870                 crb_win_lock(adapter);
 871                 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
 872                         data = readl(addr);
 873                 crb_win_unlock(adapter);
 874                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 875                 return data;
 876         }
 877
 878         dev_err(&adapter->pdev->dev,
 879                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 880         dump_stack();
 881         return -1;
 882 }
 883
 884
 885 void __iomem *
 886 qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
 887 {
 888         void __iomem *addr = NULL;
 889
 890         WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
 891
 892         return addr;
 893 }
 894
 895
 896 static int
 897 qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
 898                 u64 addr, u32 *start)
 899 {
 900         u32 window;
 901
 902         window = OCM_WIN_P3P(addr);
 903
 904         writel(window, adapter->ahw.ocm_win_crb);
 905         /* read back to flush */
 906         readl(adapter->ahw.ocm_win_crb);
 907
 908         *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
 909         return 0;
 910 }
 911
 912 static int
 913 qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
 914                 u64 *data, int op)
 915 {
 916         void __iomem *addr;
 917         int ret;
 918         u32 start;
 919
 920         mutex_lock(&adapter->ahw.mem_lock);
 921
 922         ret = qlcnic_pci_set_window_2M(adapter, off, &start);
 923         if (ret != 0)
 924                 goto unlock;
 925
 926         addr = adapter->ahw.pci_base0 + start;
 927
 928         if (op == 0)    /* read */
 929                 *data = readq(addr);
 930         else            /* write */
 931                 writeq(*data, addr);
 932
 933 unlock:
 934         mutex_unlock(&adapter->ahw.mem_lock);
 935
 936         return ret;
 937 }
 938
 939 void
 940 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
 941 {
 942         void __iomem *addr = adapter->ahw.pci_base0 +
 943                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
 944
 945         mutex_lock(&adapter->ahw.mem_lock);
 946         *data = readq(addr);
 947         mutex_unlock(&adapter->ahw.mem_lock);
 948 }
 949
 950 void
 951 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
 952 {
 953         void __iomem *addr = adapter->ahw.pci_base0 +
 954                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
 955
 956         mutex_lock(&adapter->ahw.mem_lock);
 957         writeq(data, addr);
 958         mutex_unlock(&adapter->ahw.mem_lock);
 959 }
 960
 961 #define MAX_CTL_CHECK   1000
 962
 963 int
 964 qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
 965                 u64 off, u64 data)
 966 {
 967         int i, j, ret;
 968         u32 temp, off8;
 969         void __iomem *mem_crb;
 970
 971         /* Only 64-bit aligned access */
 972         if (off & 7)
 973                 return -EIO;
 974
 975         /* P3 onward, test agent base for MIU and SIU is same */
 976         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
 977                                 QLCNIC_ADDR_QDR_NET_MAX)) {
 978                 mem_crb = qlcnic_get_ioaddr(adapter,
 979                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
 980                 goto correct;
 981         }
 982
 983         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
 984                 mem_crb = qlcnic_get_ioaddr(adapter,
 985                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
 986                 goto correct;
 987         }
 988
 989         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
 990                 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
 991
 992         return -EIO;
 993
 994 correct:
 995         off8 = off & ~0xf;
 996
 997         mutex_lock(&adapter->ahw.mem_lock);
 998
 999         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1000         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1001
1002         i = 0;
1003         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1004         writel((TA_CTL_START | TA_CTL_ENABLE),
1005                         (mem_crb + TEST_AGT_CTRL));
1006
1007         for (j = 0; j < MAX_CTL_CHECK; j++) {
1008                 temp = readl(mem_crb + TEST_AGT_CTRL);
1009                 if ((temp & TA_CTL_BUSY) == 0)
1010                         break;
1011         }
1012
1013         if (j >= MAX_CTL_CHECK) {
1014                 ret = -EIO;
1015                 goto done;
1016         }
1017
1018         i = (off & 0xf) ? 0 : 2;
1019         writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1020                         mem_crb + MIU_TEST_AGT_WRDATA(i));
1021         writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1022                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1023         i = (off & 0xf) ? 2 : 0;
1024
1025         writel(data & 0xffffffff,
1026                         mem_crb + MIU_TEST_AGT_WRDATA(i));
1027         writel((data >> 32) & 0xffffffff,
1028                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1029
1030         writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1031         writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1032                         (mem_crb + TEST_AGT_CTRL));
1033
1034         for (j = 0; j < MAX_CTL_CHECK; j++) {
1035                 temp = readl(mem_crb + TEST_AGT_CTRL);
1036                 if ((temp & TA_CTL_BUSY) == 0)
1037                         break;
1038         }
1039
1040         if (j >= MAX_CTL_CHECK) {
1041                 if (printk_ratelimit())
1042                         dev_err(&adapter->pdev->dev,
1043                                         "failed to write through agent\n");
1044                 ret = -EIO;
1045         } else
1046                 ret = 0;
1047
1048 done:
1049         mutex_unlock(&adapter->ahw.mem_lock);
1050
1051         return ret;
1052 }
1053
1054 int
1055 qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1056                 u64 off, u64 *data)
1057 {
1058         int j, ret;
1059         u32 temp, off8;
1060         u64 val;
1061         void __iomem *mem_crb;
1062
1063         /* Only 64-bit aligned access */
1064         if (off & 7)
1065                 return -EIO;
1066
1067         /* P3 onward, test agent base for MIU and SIU is same */
1068         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1069                                 QLCNIC_ADDR_QDR_NET_MAX)) {
1070                 mem_crb = qlcnic_get_ioaddr(adapter,
1071                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1072                 goto correct;
1073         }
1074
1075         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1076                 mem_crb = qlcnic_get_ioaddr(adapter,
1077                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1078                 goto correct;
1079         }
1080
1081         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1082                 return qlcnic_pci_mem_access_direct(adapter,
1083                                 off, data, 0);
1084         }
1085
1086         return -EIO;
1087
1088 correct:
1089         off8 = off & ~0xf;
1090
1091         mutex_lock(&adapter->ahw.mem_lock);
1092
1093         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1094         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1095         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1096         writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1097
1098         for (j = 0; j < MAX_CTL_CHECK; j++) {
1099                 temp = readl(mem_crb + TEST_AGT_CTRL);
1100                 if ((temp & TA_CTL_BUSY) == 0)
1101                         break;
1102         }
1103
1104         if (j >= MAX_CTL_CHECK) {
1105                 if (printk_ratelimit())
1106                         dev_err(&adapter->pdev->dev,
1107                                         "failed to read through agent\n");
1108                 ret = -EIO;
1109         } else {
1110                 off8 = MIU_TEST_AGT_RDDATA_LO;
1111                 if (off & 0xf)
1112                         off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1113
1114                 temp = readl(mem_crb + off8 + 4);
1115                 val = (u64)temp << 32;
1116                 val |= readl(mem_crb + off8);
1117                 *data = val;
1118                 ret = 0;
1119         }
1120
1121         mutex_unlock(&adapter->ahw.mem_lock);
1122
1123         return ret;
1124 }
1125
1126 int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1127 {
1128         int offset, board_type, magic;
1129         struct pci_dev *pdev = adapter->pdev;
1130
1131         offset = QLCNIC_FW_MAGIC_OFFSET;
1132         if (qlcnic_rom_fast_read(adapter, offset, &magic))
1133                 return -EIO;
1134
1135         if (magic != QLCNIC_BDINFO_MAGIC) {
1136                 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1137                         magic);
1138                 return -EIO;
1139         }
1140
1141         offset = QLCNIC_BRDTYPE_OFFSET;
1142         if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1143                 return -EIO;
1144
1145         adapter->ahw.board_type = board_type;
1146
1147         if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
1148                 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1149                 if ((gpio & 0x8000) == 0)
1150                         board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
1151         }
1152
1153         switch (board_type) {
1154         case QLCNIC_BRDTYPE_P3P_HMEZ:
1155         case QLCNIC_BRDTYPE_P3P_XG_LOM:
1156         case QLCNIC_BRDTYPE_P3P_10G_CX4:
1157         case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1158         case QLCNIC_BRDTYPE_P3P_IMEZ:
1159         case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1160         case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1161         case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1162         case QLCNIC_BRDTYPE_P3P_10G_XFP:
1163         case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
1164                 adapter->ahw.port_type = QLCNIC_XGBE;
1165                 break;
1166         case QLCNIC_BRDTYPE_P3P_REF_QG:
1167         case QLCNIC_BRDTYPE_P3P_4_GB:
1168         case QLCNIC_BRDTYPE_P3P_4_GB_MM:
1169                 adapter->ahw.port_type = QLCNIC_GBE;
1170                 break;
1171         case QLCNIC_BRDTYPE_P3P_10G_TP:
1172                 adapter->ahw.port_type = (adapter->portnum < 2) ?
1173                         QLCNIC_XGBE : QLCNIC_GBE;
1174                 break;
1175         default:
1176                 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1177                 adapter->ahw.port_type = QLCNIC_XGBE;
1178                 break;
1179         }
1180
1181         return 0;
1182 }
1183
1184 int
1185 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1186 {
1187         u32 wol_cfg;
1188
1189         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1190         if (wol_cfg & (1UL << adapter->portnum)) {
1191                 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1192                 if (wol_cfg & (1 << adapter->portnum))
1193                         return 1;
1194         }
1195
1196         return 0;
1197 }
1198
1199 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1200 {
1201         struct qlcnic_nic_req   req;
1202         int rv;
1203         u64 word;
1204
1205         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1206         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1207
1208         word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1209         req.req_hdr = cpu_to_le64(word);
1210
1211         req.words[0] = cpu_to_le64((u64)rate << 32);
1212         req.words[1] = cpu_to_le64(state);
1213
1214         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1215         if (rv)
1216                 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1217
1218         return rv;
1219 }