Pileus Git - ~andy/linux/blob - drivers/net/phy/vitesse.c

   1 /*
   2  * Driver for Vitesse PHYs
   3  *
   4  * Author: Kriston Carson
   5  *
   6  * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/mii.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20
  21 /* Vitesse Extended Control Register 1 */
  22 #define MII_VSC8244_EXT_CON1           0x17
  23 #define MII_VSC8244_EXTCON1_INIT       0x0000
  24 #define MII_VSC8244_EXTCON1_TX_SKEW_MASK        0x0c00
  25 #define MII_VSC8244_EXTCON1_RX_SKEW_MASK        0x0300
  26 #define MII_VSC8244_EXTCON1_TX_SKEW     0x0800
  27 #define MII_VSC8244_EXTCON1_RX_SKEW     0x0200
  28
  29 /* Vitesse Interrupt Mask Register */
  30 #define MII_VSC8244_IMASK               0x19
  31 #define MII_VSC8244_IMASK_IEN           0x8000
  32 #define MII_VSC8244_IMASK_SPEED         0x4000
  33 #define MII_VSC8244_IMASK_LINK          0x2000
  34 #define MII_VSC8244_IMASK_DUPLEX        0x1000
  35 #define MII_VSC8244_IMASK_MASK          0xf000
  36
  37 #define MII_VSC8221_IMASK_MASK          0xa000
  38
  39 /* Vitesse Interrupt Status Register */
  40 #define MII_VSC8244_ISTAT               0x1a
  41 #define MII_VSC8244_ISTAT_STATUS        0x8000
  42 #define MII_VSC8244_ISTAT_SPEED         0x4000
  43 #define MII_VSC8244_ISTAT_LINK          0x2000
  44 #define MII_VSC8244_ISTAT_DUPLEX        0x1000
  45
  46 /* Vitesse Auxiliary Control/Status Register */
  47 #define MII_VSC8244_AUX_CONSTAT         0x1c
  48 #define MII_VSC8244_AUXCONSTAT_INIT     0x0000
  49 #define MII_VSC8244_AUXCONSTAT_DUPLEX   0x0020
  50 #define MII_VSC8244_AUXCONSTAT_SPEED    0x0018
  51 #define MII_VSC8244_AUXCONSTAT_GBIT     0x0010
  52 #define MII_VSC8244_AUXCONSTAT_100      0x0008
  53
  54 #define MII_VSC8221_AUXCONSTAT_INIT     0x0004 /* need to set this bit? */
  55 #define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
  56
  57 #define PHY_ID_VSC8234                  0x000fc620
  58 #define PHY_ID_VSC8244                  0x000fc6c0
  59 #define PHY_ID_VSC8574                  0x000704a0
  60 #define PHY_ID_VSC8662                  0x00070660
  61 #define PHY_ID_VSC8221                  0x000fc550
  62 #define PHY_ID_VSC8211                  0x000fc4b0
  63
  64 MODULE_DESCRIPTION("Vitesse PHY driver");
  65 MODULE_AUTHOR("Kriston Carson");
  66 MODULE_LICENSE("GPL");
  67
  68 static int vsc824x_add_skew(struct phy_device *phydev)
  69 {
  70         int err;
  71         int extcon;
  72
  73         extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
  74
  75         if (extcon < 0)
  76                 return extcon;
  77
  78         extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
  79                         MII_VSC8244_EXTCON1_RX_SKEW_MASK);
  80
  81         extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
  82                         MII_VSC8244_EXTCON1_RX_SKEW);
  83
  84         err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
  85
  86         return err;
  87 }
  88
  89 static int vsc824x_config_init(struct phy_device *phydev)
  90 {
  91         int err;
  92
  93         err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
  94                         MII_VSC8244_AUXCONSTAT_INIT);
  95         if (err < 0)
  96                 return err;
  97
  98         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
  99                 err = vsc824x_add_skew(phydev);
 100
 101         return err;
 102 }
 103
 104 static int vsc824x_ack_interrupt(struct phy_device *phydev)
 105 {
 106         int err = 0;
 107
 108         /* Don't bother to ACK the interrupts if interrupts
 109          * are disabled.  The 824x cannot clear the interrupts
 110          * if they are disabled.
 111          */
 112         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 113                 err = phy_read(phydev, MII_VSC8244_ISTAT);
 114
 115         return (err < 0) ? err : 0;
 116 }
 117
 118 static int vsc82xx_config_intr(struct phy_device *phydev)
 119 {
 120         int err;
 121
 122         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 123                 err = phy_write(phydev, MII_VSC8244_IMASK,
 124                         (phydev->drv->phy_id == PHY_ID_VSC8234 ||
 125                          phydev->drv->phy_id == PHY_ID_VSC8244 ||
 126                          phydev->drv->phy_id == PHY_ID_VSC8574) ?
 127                                 MII_VSC8244_IMASK_MASK :
 128                                 MII_VSC8221_IMASK_MASK);
 129         else {
 130                 /* The Vitesse PHY cannot clear the interrupt
 131                  * once it has disabled them, so we clear them first
 132                  */
 133                 err = phy_read(phydev, MII_VSC8244_ISTAT);
 134
 135                 if (err < 0)
 136                         return err;
 137
 138                 err = phy_write(phydev, MII_VSC8244_IMASK, 0);
 139         }
 140
 141         return err;
 142 }
 143
 144 static int vsc8221_config_init(struct phy_device *phydev)
 145 {
 146         int err;
 147
 148         err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
 149                         MII_VSC8221_AUXCONSTAT_INIT);
 150         return err;
 151
 152         /* Perhaps we should set EXT_CON1 based on the interface?
 153          * Options are 802.3Z SerDes or SGMII
 154          */
 155 }
 156
 157 /* Vitesse 82xx */
 158 static struct phy_driver vsc82xx_driver[] = {
 159 {
 160         .phy_id         = PHY_ID_VSC8234,
 161         .name           = "Vitesse VSC8234",
 162         .phy_id_mask    = 0x000ffff0,
 163         .features       = PHY_GBIT_FEATURES,
 164         .flags          = PHY_HAS_INTERRUPT,
 165         .config_init    = &vsc824x_config_init,
 166         .config_aneg    = &genphy_config_aneg,
 167         .read_status    = &genphy_read_status,
 168         .ack_interrupt  = &vsc824x_ack_interrupt,
 169         .config_intr    = &vsc82xx_config_intr,
 170         .driver         = { .owner = THIS_MODULE,},
 171 }, {
 172         .phy_id         = PHY_ID_VSC8244,
 173         .name           = "Vitesse VSC8244",
 174         .phy_id_mask    = 0x000fffc0,
 175         .features       = PHY_GBIT_FEATURES,
 176         .flags          = PHY_HAS_INTERRUPT,
 177         .config_init    = &vsc824x_config_init,
 178         .config_aneg    = &genphy_config_aneg,
 179         .read_status    = &genphy_read_status,
 180         .ack_interrupt  = &vsc824x_ack_interrupt,
 181         .config_intr    = &vsc82xx_config_intr,
 182         .driver         = { .owner = THIS_MODULE,},
 183 }, {
 184         .phy_id         = PHY_ID_VSC8574,
 185         .name           = "Vitesse VSC8574",
 186         .phy_id_mask    = 0x000ffff0,
 187         .features       = PHY_GBIT_FEATURES,
 188         .flags          = PHY_HAS_INTERRUPT,
 189         .config_init    = &vsc824x_config_init,
 190         .config_aneg    = &genphy_config_aneg,
 191         .read_status    = &genphy_read_status,
 192         .ack_interrupt  = &vsc824x_ack_interrupt,
 193         .config_intr    = &vsc82xx_config_intr,
 194         .driver         = { .owner = THIS_MODULE,},
 195 }, {
 196         .phy_id         = PHY_ID_VSC8662,
 197         .name           = "Vitesse VSC8662",
 198         .phy_id_mask    = 0x000ffff0,
 199         .features       = PHY_GBIT_FEATURES,
 200         .flags          = PHY_HAS_INTERRUPT,
 201         .config_init    = &vsc824x_config_init,
 202         .config_aneg    = &genphy_config_aneg,
 203         .read_status    = &genphy_read_status,
 204         .ack_interrupt  = &vsc824x_ack_interrupt,
 205         .config_intr    = &vsc82xx_config_intr,
 206         .driver         = { .owner = THIS_MODULE,},
 207 }, {
 208         /* Vitesse 8221 */
 209         .phy_id         = PHY_ID_VSC8221,
 210         .phy_id_mask    = 0x000ffff0,
 211         .name           = "Vitesse VSC8221",
 212         .features       = PHY_GBIT_FEATURES,
 213         .flags          = PHY_HAS_INTERRUPT,
 214         .config_init    = &vsc8221_config_init,
 215         .config_aneg    = &genphy_config_aneg,
 216         .read_status    = &genphy_read_status,
 217         .ack_interrupt  = &vsc824x_ack_interrupt,
 218         .config_intr    = &vsc82xx_config_intr,
 219         .driver         = { .owner = THIS_MODULE,},
 220 }, {
 221         /* Vitesse 8211 */
 222         .phy_id         = PHY_ID_VSC8211,
 223         .phy_id_mask    = 0x000ffff0,
 224         .name           = "Vitesse VSC8211",
 225         .features       = PHY_GBIT_FEATURES,
 226         .flags          = PHY_HAS_INTERRUPT,
 227         .config_init    = &vsc8221_config_init,
 228         .config_aneg    = &genphy_config_aneg,
 229         .read_status    = &genphy_read_status,
 230         .ack_interrupt  = &vsc824x_ack_interrupt,
 231         .config_intr    = &vsc82xx_config_intr,
 232         .driver         = { .owner = THIS_MODULE,},
 233 } };
 234
 235 static int __init vsc82xx_init(void)
 236 {
 237         return phy_drivers_register(vsc82xx_driver,
 238                 ARRAY_SIZE(vsc82xx_driver));
 239 }
 240
 241 static void __exit vsc82xx_exit(void)
 242 {
 243         return phy_drivers_unregister(vsc82xx_driver,
 244                 ARRAY_SIZE(vsc82xx_driver));
 245 }
 246
 247 module_init(vsc82xx_init);
 248 module_exit(vsc82xx_exit);
 249
 250 static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
 251         { PHY_ID_VSC8234, 0x000ffff0 },
 252         { PHY_ID_VSC8244, 0x000fffc0 },
 253         { PHY_ID_VSC8574, 0x000ffff0 },
 254         { PHY_ID_VSC8662, 0x000ffff0 },
 255         { PHY_ID_VSC8221, 0x000ffff0 },
 256         { PHY_ID_VSC8211, 0x000ffff0 },
 257         { }
 258 };
 259
 260 MODULE_DEVICE_TABLE(mdio, vitesse_tbl);