Pileus Git - ~andy/linux/blob - drivers/net/niu.c

   1 /* niu.c: Neptune ethernet driver.
   2  *
   3  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/init.h>
   8 #include <linux/pci.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/netdevice.h>
  11 #include <linux/ethtool.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/delay.h>
  15 #include <linux/bitops.h>
  16 #include <linux/mii.h>
  17 #include <linux/if_ether.h>
  18 #include <linux/if_vlan.h>
  19 #include <linux/ip.h>
  20 #include <linux/in.h>
  21 #include <linux/ipv6.h>
  22 #include <linux/log2.h>
  23 #include <linux/jiffies.h>
  24 #include <linux/crc32.h>
  25
  26 #include <linux/io.h>
  27
  28 #ifdef CONFIG_SPARC64
  29 #include <linux/of_device.h>
  30 #endif
  31
  32 #include "niu.h"
  33
  34 #define DRV_MODULE_NAME         "niu"
  35 #define PFX DRV_MODULE_NAME     ": "
  36 #define DRV_MODULE_VERSION      "1.0"
  37 #define DRV_MODULE_RELDATE      "Nov 14, 2008"
  38
  39 static char version[] __devinitdata =
  40         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  41
  42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  43 MODULE_DESCRIPTION("NIU ethernet driver");
  44 MODULE_LICENSE("GPL");
  45 MODULE_VERSION(DRV_MODULE_VERSION);
  46
  47 #ifndef DMA_44BIT_MASK
  48 #define DMA_44BIT_MASK  0x00000fffffffffffULL
  49 #endif
  50
  51 #ifndef readq
  52 static u64 readq(void __iomem *reg)
  53 {
  54         return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
  55 }
  56
  57 static void writeq(u64 val, void __iomem *reg)
  58 {
  59         writel(val & 0xffffffff, reg);
  60         writel(val >> 32, reg + 0x4UL);
  61 }
  62 #endif
  63
  64 static struct pci_device_id niu_pci_tbl[] = {
  65         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  66         {}
  67 };
  68
  69 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  70
  71 #define NIU_TX_TIMEOUT                  (5 * HZ)
  72
  73 #define nr64(reg)               readq(np->regs + (reg))
  74 #define nw64(reg, val)          writeq((val), np->regs + (reg))
  75
  76 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
  77 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
  78
  79 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
  80 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
  81
  82 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
  83 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
  84
  85 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
  86 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
  87
  88 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  89
  90 static int niu_debug;
  91 static int debug = -1;
  92 module_param(debug, int, 0);
  93 MODULE_PARM_DESC(debug, "NIU debug level");
  94
  95 #define niudbg(TYPE, f, a...) \
  96 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
  97                 printk(KERN_DEBUG PFX f, ## a); \
  98 } while (0)
  99
 100 #define niuinfo(TYPE, f, a...) \
 101 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 102                 printk(KERN_INFO PFX f, ## a); \
 103 } while (0)
 104
 105 #define niuwarn(TYPE, f, a...) \
 106 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 107                 printk(KERN_WARNING PFX f, ## a); \
 108 } while (0)
 109
 110 #define niu_lock_parent(np, flags) \
 111         spin_lock_irqsave(&np->parent->lock, flags)
 112 #define niu_unlock_parent(np, flags) \
 113         spin_unlock_irqrestore(&np->parent->lock, flags)
 114
 115 static int serdes_init_10g_serdes(struct niu *np);
 116
 117 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
 118                                      u64 bits, int limit, int delay)
 119 {
 120         while (--limit >= 0) {
 121                 u64 val = nr64_mac(reg);
 122
 123                 if (!(val & bits))
 124                         break;
 125                 udelay(delay);
 126         }
 127         if (limit < 0)
 128                 return -ENODEV;
 129         return 0;
 130 }
 131
 132 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
 133                                         u64 bits, int limit, int delay,
 134                                         const char *reg_name)
 135 {
 136         int err;
 137
 138         nw64_mac(reg, bits);
 139         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
 140         if (err)
 141                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 142                         "would not clear, val[%llx]\n",
 143                         np->dev->name, (unsigned long long) bits, reg_name,
 144                         (unsigned long long) nr64_mac(reg));
 145         return err;
 146 }
 147
 148 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 149 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 150         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 151 })
 152
 153 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
 154                                      u64 bits, int limit, int delay)
 155 {
 156         while (--limit >= 0) {
 157                 u64 val = nr64_ipp(reg);
 158
 159                 if (!(val & bits))
 160                         break;
 161                 udelay(delay);
 162         }
 163         if (limit < 0)
 164                 return -ENODEV;
 165         return 0;
 166 }
 167
 168 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
 169                                         u64 bits, int limit, int delay,
 170                                         const char *reg_name)
 171 {
 172         int err;
 173         u64 val;
 174
 175         val = nr64_ipp(reg);
 176         val |= bits;
 177         nw64_ipp(reg, val);
 178
 179         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
 180         if (err)
 181                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 182                         "would not clear, val[%llx]\n",
 183                         np->dev->name, (unsigned long long) bits, reg_name,
 184                         (unsigned long long) nr64_ipp(reg));
 185         return err;
 186 }
 187
 188 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 189 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 190         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 191 })
 192
 193 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
 194                                  u64 bits, int limit, int delay)
 195 {
 196         while (--limit >= 0) {
 197                 u64 val = nr64(reg);
 198
 199                 if (!(val & bits))
 200                         break;
 201                 udelay(delay);
 202         }
 203         if (limit < 0)
 204                 return -ENODEV;
 205         return 0;
 206 }
 207
 208 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
 209 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 210         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
 211 })
 212
 213 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
 214                                     u64 bits, int limit, int delay,
 215                                     const char *reg_name)
 216 {
 217         int err;
 218
 219         nw64(reg, bits);
 220         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
 221         if (err)
 222                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 223                         "would not clear, val[%llx]\n",
 224                         np->dev->name, (unsigned long long) bits, reg_name,
 225                         (unsigned long long) nr64(reg));
 226         return err;
 227 }
 228
 229 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 230 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 231         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 232 })
 233
 234 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
 235 {
 236         u64 val = (u64) lp->timer;
 237
 238         if (on)
 239                 val |= LDG_IMGMT_ARM;
 240
 241         nw64(LDG_IMGMT(lp->ldg_num), val);
 242 }
 243
 244 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
 245 {
 246         unsigned long mask_reg, bits;
 247         u64 val;
 248
 249         if (ldn < 0 || ldn > LDN_MAX)
 250                 return -EINVAL;
 251
 252         if (ldn < 64) {
 253                 mask_reg = LD_IM0(ldn);
 254                 bits = LD_IM0_MASK;
 255         } else {
 256                 mask_reg = LD_IM1(ldn - 64);
 257                 bits = LD_IM1_MASK;
 258         }
 259
 260         val = nr64(mask_reg);
 261         if (on)
 262                 val &= ~bits;
 263         else
 264                 val |= bits;
 265         nw64(mask_reg, val);
 266
 267         return 0;
 268 }
 269
 270 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
 271 {
 272         struct niu_parent *parent = np->parent;
 273         int i;
 274
 275         for (i = 0; i <= LDN_MAX; i++) {
 276                 int err;
 277
 278                 if (parent->ldg_map[i] != lp->ldg_num)
 279                         continue;
 280
 281                 err = niu_ldn_irq_enable(np, i, on);
 282                 if (err)
 283                         return err;
 284         }
 285         return 0;
 286 }
 287
 288 static int niu_enable_interrupts(struct niu *np, int on)
 289 {
 290         int i;
 291
 292         for (i = 0; i < np->num_ldg; i++) {
 293                 struct niu_ldg *lp = &np->ldg[i];
 294                 int err;
 295
 296                 err = niu_enable_ldn_in_ldg(np, lp, on);
 297                 if (err)
 298                         return err;
 299         }
 300         for (i = 0; i < np->num_ldg; i++)
 301                 niu_ldg_rearm(np, &np->ldg[i], on);
 302
 303         return 0;
 304 }
 305
 306 static u32 phy_encode(u32 type, int port)
 307 {
 308         return (type << (port * 2));
 309 }
 310
 311 static u32 phy_decode(u32 val, int port)
 312 {
 313         return (val >> (port * 2)) & PORT_TYPE_MASK;
 314 }
 315
 316 static int mdio_wait(struct niu *np)
 317 {
 318         int limit = 1000;
 319         u64 val;
 320
 321         while (--limit > 0) {
 322                 val = nr64(MIF_FRAME_OUTPUT);
 323                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
 324                         return val & MIF_FRAME_OUTPUT_DATA;
 325
 326                 udelay(10);
 327         }
 328
 329         return -ENODEV;
 330 }
 331
 332 static int mdio_read(struct niu *np, int port, int dev, int reg)
 333 {
 334         int err;
 335
 336         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 337         err = mdio_wait(np);
 338         if (err < 0)
 339                 return err;
 340
 341         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
 342         return mdio_wait(np);
 343 }
 344
 345 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
 346 {
 347         int err;
 348
 349         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 350         err = mdio_wait(np);
 351         if (err < 0)
 352                 return err;
 353
 354         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
 355         err = mdio_wait(np);
 356         if (err < 0)
 357                 return err;
 358
 359         return 0;
 360 }
 361
 362 static int mii_read(struct niu *np, int port, int reg)
 363 {
 364         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
 365         return mdio_wait(np);
 366 }
 367
 368 static int mii_write(struct niu *np, int port, int reg, int data)
 369 {
 370         int err;
 371
 372         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
 373         err = mdio_wait(np);
 374         if (err < 0)
 375                 return err;
 376
 377         return 0;
 378 }
 379
 380 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
 381 {
 382         int err;
 383
 384         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 385                          ESR2_TI_PLL_TX_CFG_L(channel),
 386                          val & 0xffff);
 387         if (!err)
 388                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 389                                  ESR2_TI_PLL_TX_CFG_H(channel),
 390                                  val >> 16);
 391         return err;
 392 }
 393
 394 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
 395 {
 396         int err;
 397
 398         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 399                          ESR2_TI_PLL_RX_CFG_L(channel),
 400                          val & 0xffff);
 401         if (!err)
 402                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 403                                  ESR2_TI_PLL_RX_CFG_H(channel),
 404                                  val >> 16);
 405         return err;
 406 }
 407
 408 /* Mode is always 10G fiber.  */
 409 static int serdes_init_niu_10g_fiber(struct niu *np)
 410 {
 411         struct niu_link_config *lp = &np->link_config;
 412         u32 tx_cfg, rx_cfg;
 413         unsigned long i;
 414
 415         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 416         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 417                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 418                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 419
 420         if (lp->loopback_mode == LOOPBACK_PHY) {
 421                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 422
 423                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 424                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 425
 426                 tx_cfg |= PLL_TX_CFG_ENTEST;
 427                 rx_cfg |= PLL_RX_CFG_ENTEST;
 428         }
 429
 430         /* Initialize all 4 lanes of the SERDES.  */
 431         for (i = 0; i < 4; i++) {
 432                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
 433                 if (err)
 434                         return err;
 435         }
 436
 437         for (i = 0; i < 4; i++) {
 438                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
 439                 if (err)
 440                         return err;
 441         }
 442
 443         return 0;
 444 }
 445
 446 static int serdes_init_niu_1g_serdes(struct niu *np)
 447 {
 448         struct niu_link_config *lp = &np->link_config;
 449         u16 pll_cfg, pll_sts;
 450         int max_retry = 100;
 451         u64 uninitialized_var(sig), mask, val;
 452         u32 tx_cfg, rx_cfg;
 453         unsigned long i;
 454         int err;
 455
 456         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
 457                   PLL_TX_CFG_RATE_HALF);
 458         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 459                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 460                   PLL_RX_CFG_RATE_HALF);
 461
 462         if (np->port == 0)
 463                 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
 464
 465         if (lp->loopback_mode == LOOPBACK_PHY) {
 466                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 467
 468                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 469                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 470
 471                 tx_cfg |= PLL_TX_CFG_ENTEST;
 472                 rx_cfg |= PLL_RX_CFG_ENTEST;
 473         }
 474
 475         /* Initialize PLL for 1G */
 476         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
 477
 478         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 479                          ESR2_TI_PLL_CFG_L, pll_cfg);
 480         if (err) {
 481                 dev_err(np->device, PFX "NIU Port %d "
 482                         "serdes_init_niu_1g_serdes: "
 483                         "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
 484                 return err;
 485         }
 486
 487         pll_sts = PLL_CFG_ENPLL;
 488
 489         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 490                          ESR2_TI_PLL_STS_L, pll_sts);
 491         if (err) {
 492                 dev_err(np->device, PFX "NIU Port %d "
 493                         "serdes_init_niu_1g_serdes: "
 494                         "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
 495                 return err;
 496         }
 497
 498         udelay(200);
 499
 500         /* Initialize all 4 lanes of the SERDES.  */
 501         for (i = 0; i < 4; i++) {
 502                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 503                 if (err)
 504                         return err;
 505         }
 506
 507         for (i = 0; i < 4; i++) {
 508                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 509                 if (err)
 510                         return err;
 511         }
 512
 513         switch (np->port) {
 514         case 0:
 515                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
 516                 mask = val;
 517                 break;
 518
 519         case 1:
 520                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
 521                 mask = val;
 522                 break;
 523
 524         default:
 525                 return -EINVAL;
 526         }
 527
 528         while (max_retry--) {
 529                 sig = nr64(ESR_INT_SIGNALS);
 530                 if ((sig & mask) == val)
 531                         break;
 532
 533                 mdelay(500);
 534         }
 535
 536         if ((sig & mask) != val) {
 537                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
 538                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
 539                 return -ENODEV;
 540         }
 541
 542         return 0;
 543 }
 544
 545 static int serdes_init_niu_10g_serdes(struct niu *np)
 546 {
 547         struct niu_link_config *lp = &np->link_config;
 548         u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
 549         int max_retry = 100;
 550         u64 uninitialized_var(sig), mask, val;
 551         unsigned long i;
 552         int err;
 553
 554         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 555         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 556                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 557                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 558
 559         if (lp->loopback_mode == LOOPBACK_PHY) {
 560                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 561
 562                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 563                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 564
 565                 tx_cfg |= PLL_TX_CFG_ENTEST;
 566                 rx_cfg |= PLL_RX_CFG_ENTEST;
 567         }
 568
 569         /* Initialize PLL for 10G */
 570         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
 571
 572         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 573                          ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
 574         if (err) {
 575                 dev_err(np->device, PFX "NIU Port %d "
 576                         "serdes_init_niu_10g_serdes: "
 577                         "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
 578                 return err;
 579         }
 580
 581         pll_sts = PLL_CFG_ENPLL;
 582
 583         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 584                          ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
 585         if (err) {
 586                 dev_err(np->device, PFX "NIU Port %d "
 587                         "serdes_init_niu_10g_serdes: "
 588                         "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
 589                 return err;
 590         }
 591
 592         udelay(200);
 593
 594         /* Initialize all 4 lanes of the SERDES.  */
 595         for (i = 0; i < 4; i++) {
 596                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 597                 if (err)
 598                         return err;
 599         }
 600
 601         for (i = 0; i < 4; i++) {
 602                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 603                 if (err)
 604                         return err;
 605         }
 606
 607         /* check if serdes is ready */
 608
 609         switch (np->port) {
 610         case 0:
 611                 mask = ESR_INT_SIGNALS_P0_BITS;
 612                 val = (ESR_INT_SRDY0_P0 |
 613                        ESR_INT_DET0_P0 |
 614                        ESR_INT_XSRDY_P0 |
 615                        ESR_INT_XDP_P0_CH3 |
 616                        ESR_INT_XDP_P0_CH2 |
 617                        ESR_INT_XDP_P0_CH1 |
 618                        ESR_INT_XDP_P0_CH0);
 619                 break;
 620
 621         case 1:
 622                 mask = ESR_INT_SIGNALS_P1_BITS;
 623                 val = (ESR_INT_SRDY0_P1 |
 624                        ESR_INT_DET0_P1 |
 625                        ESR_INT_XSRDY_P1 |
 626                        ESR_INT_XDP_P1_CH3 |
 627                        ESR_INT_XDP_P1_CH2 |
 628                        ESR_INT_XDP_P1_CH1 |
 629                        ESR_INT_XDP_P1_CH0);
 630                 break;
 631
 632         default:
 633                 return -EINVAL;
 634         }
 635
 636         while (max_retry--) {
 637                 sig = nr64(ESR_INT_SIGNALS);
 638                 if ((sig & mask) == val)
 639                         break;
 640
 641                 mdelay(500);
 642         }
 643
 644         if ((sig & mask) != val) {
 645                 pr_info(PFX "NIU Port %u signal bits [%08x] are not "
 646                         "[%08x] for 10G...trying 1G\n",
 647                         np->port, (int) (sig & mask), (int) val);
 648
 649                 /* 10G failed, try initializing at 1G */
 650                 err = serdes_init_niu_1g_serdes(np);
 651                 if (!err) {
 652                         np->flags &= ~NIU_FLAGS_10G;
 653                         np->mac_xcvr = MAC_XCVR_PCS;
 654                 }  else {
 655                         dev_err(np->device, PFX "Port %u 10G/1G SERDES "
 656                                 "Link Failed \n", np->port);
 657                         return -ENODEV;
 658                 }
 659         }
 660         return 0;
 661 }
 662
 663 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
 664 {
 665         int err;
 666
 667         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
 668         if (err >= 0) {
 669                 *val = (err & 0xffff);
 670                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 671                                 ESR_RXTX_CTRL_H(chan));
 672                 if (err >= 0)
 673                         *val |= ((err & 0xffff) << 16);
 674                 err = 0;
 675         }
 676         return err;
 677 }
 678
 679 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
 680 {
 681         int err;
 682
 683         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 684                         ESR_GLUE_CTRL0_L(chan));
 685         if (err >= 0) {
 686                 *val = (err & 0xffff);
 687                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 688                                 ESR_GLUE_CTRL0_H(chan));
 689                 if (err >= 0) {
 690                         *val |= ((err & 0xffff) << 16);
 691                         err = 0;
 692                 }
 693         }
 694         return err;
 695 }
 696
 697 static int esr_read_reset(struct niu *np, u32 *val)
 698 {
 699         int err;
 700
 701         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 702                         ESR_RXTX_RESET_CTRL_L);
 703         if (err >= 0) {
 704                 *val = (err & 0xffff);
 705                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 706                                 ESR_RXTX_RESET_CTRL_H);
 707                 if (err >= 0) {
 708                         *val |= ((err & 0xffff) << 16);
 709                         err = 0;
 710                 }
 711         }
 712         return err;
 713 }
 714
 715 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
 716 {
 717         int err;
 718
 719         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 720                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
 721         if (!err)
 722                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 723                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
 724         return err;
 725 }
 726
 727 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
 728 {
 729         int err;
 730
 731         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 732                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
 733         if (!err)
 734                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 735                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
 736         return err;
 737 }
 738
 739 static int esr_reset(struct niu *np)
 740 {
 741         u32 uninitialized_var(reset);
 742         int err;
 743
 744         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 745                          ESR_RXTX_RESET_CTRL_L, 0x0000);
 746         if (err)
 747                 return err;
 748         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 749                          ESR_RXTX_RESET_CTRL_H, 0xffff);
 750         if (err)
 751                 return err;
 752         udelay(200);
 753
 754         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 755                          ESR_RXTX_RESET_CTRL_L, 0xffff);
 756         if (err)
 757                 return err;
 758         udelay(200);
 759
 760         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 761                          ESR_RXTX_RESET_CTRL_H, 0x0000);
 762         if (err)
 763                 return err;
 764         udelay(200);
 765
 766         err = esr_read_reset(np, &reset);
 767         if (err)
 768                 return err;
 769         if (reset != 0) {
 770                 dev_err(np->device, PFX "Port %u ESR_RESET "
 771                         "did not clear [%08x]\n",
 772                         np->port, reset);
 773                 return -ENODEV;
 774         }
 775
 776         return 0;
 777 }
 778
 779 static int serdes_init_10g(struct niu *np)
 780 {
 781         struct niu_link_config *lp = &np->link_config;
 782         unsigned long ctrl_reg, test_cfg_reg, i;
 783         u64 ctrl_val, test_cfg_val, sig, mask, val;
 784         int err;
 785
 786         switch (np->port) {
 787         case 0:
 788                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 789                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 790                 break;
 791         case 1:
 792                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 793                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 794                 break;
 795
 796         default:
 797                 return -EINVAL;
 798         }
 799         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 800                     ENET_SERDES_CTRL_SDET_1 |
 801                     ENET_SERDES_CTRL_SDET_2 |
 802                     ENET_SERDES_CTRL_SDET_3 |
 803                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 804                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 805                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 806                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 807                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 808                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 809                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 810                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 811         test_cfg_val = 0;
 812
 813         if (lp->loopback_mode == LOOPBACK_PHY) {
 814                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 815                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 816                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 817                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 818                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 819                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 820                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 821                                   ENET_SERDES_TEST_MD_3_SHIFT));
 822         }
 823
 824         nw64(ctrl_reg, ctrl_val);
 825         nw64(test_cfg_reg, test_cfg_val);
 826
 827         /* Initialize all 4 lanes of the SERDES.  */
 828         for (i = 0; i < 4; i++) {
 829                 u32 rxtx_ctrl, glue0;
 830
 831                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 832                 if (err)
 833                         return err;
 834                 err = esr_read_glue0(np, i, &glue0);
 835                 if (err)
 836                         return err;
 837
 838                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 839                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 840                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 841
 842                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 843                            ESR_GLUE_CTRL0_THCNT |
 844                            ESR_GLUE_CTRL0_BLTIME);
 845                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 846                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 847                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 848                           (BLTIME_300_CYCLES <<
 849                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 850
 851                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 852                 if (err)
 853                         return err;
 854                 err = esr_write_glue0(np, i, glue0);
 855                 if (err)
 856                         return err;
 857         }
 858
 859         err = esr_reset(np);
 860         if (err)
 861                 return err;
 862
 863         sig = nr64(ESR_INT_SIGNALS);
 864         switch (np->port) {
 865         case 0:
 866                 mask = ESR_INT_SIGNALS_P0_BITS;
 867                 val = (ESR_INT_SRDY0_P0 |
 868                        ESR_INT_DET0_P0 |
 869                        ESR_INT_XSRDY_P0 |
 870                        ESR_INT_XDP_P0_CH3 |
 871                        ESR_INT_XDP_P0_CH2 |
 872                        ESR_INT_XDP_P0_CH1 |
 873                        ESR_INT_XDP_P0_CH0);
 874                 break;
 875
 876         case 1:
 877                 mask = ESR_INT_SIGNALS_P1_BITS;
 878                 val = (ESR_INT_SRDY0_P1 |
 879                        ESR_INT_DET0_P1 |
 880                        ESR_INT_XSRDY_P1 |
 881                        ESR_INT_XDP_P1_CH3 |
 882                        ESR_INT_XDP_P1_CH2 |
 883                        ESR_INT_XDP_P1_CH1 |
 884                        ESR_INT_XDP_P1_CH0);
 885                 break;
 886
 887         default:
 888                 return -EINVAL;
 889         }
 890
 891         if ((sig & mask) != val) {
 892                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
 893                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 894                         return 0;
 895                 }
 896                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
 897                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
 898                 return -ENODEV;
 899         }
 900         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
 901                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 902         return 0;
 903 }
 904
 905 static int serdes_init_1g(struct niu *np)
 906 {
 907         u64 val;
 908
 909         val = nr64(ENET_SERDES_1_PLL_CFG);
 910         val &= ~ENET_SERDES_PLL_FBDIV2;
 911         switch (np->port) {
 912         case 0:
 913                 val |= ENET_SERDES_PLL_HRATE0;
 914                 break;
 915         case 1:
 916                 val |= ENET_SERDES_PLL_HRATE1;
 917                 break;
 918         case 2:
 919                 val |= ENET_SERDES_PLL_HRATE2;
 920                 break;
 921         case 3:
 922                 val |= ENET_SERDES_PLL_HRATE3;
 923                 break;
 924         default:
 925                 return -EINVAL;
 926         }
 927         nw64(ENET_SERDES_1_PLL_CFG, val);
 928
 929         return 0;
 930 }
 931
 932 static int serdes_init_1g_serdes(struct niu *np)
 933 {
 934         struct niu_link_config *lp = &np->link_config;
 935         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
 936         u64 ctrl_val, test_cfg_val, sig, mask, val;
 937         int err;
 938         u64 reset_val, val_rd;
 939
 940         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
 941                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
 942                 ENET_SERDES_PLL_FBDIV0;
 943         switch (np->port) {
 944         case 0:
 945                 reset_val =  ENET_SERDES_RESET_0;
 946                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 947                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 948                 pll_cfg = ENET_SERDES_0_PLL_CFG;
 949                 break;
 950         case 1:
 951                 reset_val =  ENET_SERDES_RESET_1;
 952                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 953                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 954                 pll_cfg = ENET_SERDES_1_PLL_CFG;
 955                 break;
 956
 957         default:
 958                 return -EINVAL;
 959         }
 960         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 961                     ENET_SERDES_CTRL_SDET_1 |
 962                     ENET_SERDES_CTRL_SDET_2 |
 963                     ENET_SERDES_CTRL_SDET_3 |
 964                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 965                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 966                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 967                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 968                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 969                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 970                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 971                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 972         test_cfg_val = 0;
 973
 974         if (lp->loopback_mode == LOOPBACK_PHY) {
 975                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 976                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 977                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 978                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 979                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 980                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 981                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 982                                   ENET_SERDES_TEST_MD_3_SHIFT));
 983         }
 984
 985         nw64(ENET_SERDES_RESET, reset_val);
 986         mdelay(20);
 987         val_rd = nr64(ENET_SERDES_RESET);
 988         val_rd &= ~reset_val;
 989         nw64(pll_cfg, val);
 990         nw64(ctrl_reg, ctrl_val);
 991         nw64(test_cfg_reg, test_cfg_val);
 992         nw64(ENET_SERDES_RESET, val_rd);
 993         mdelay(2000);
 994
 995         /* Initialize all 4 lanes of the SERDES.  */
 996         for (i = 0; i < 4; i++) {
 997                 u32 rxtx_ctrl, glue0;
 998
 999                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
1000                 if (err)
1001                         return err;
1002                 err = esr_read_glue0(np, i, &glue0);
1003                 if (err)
1004                         return err;
1005
1006                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
1007                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
1008                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
1009
1010                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
1011                            ESR_GLUE_CTRL0_THCNT |
1012                            ESR_GLUE_CTRL0_BLTIME);
1013                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
1014                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
1015                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
1016                           (BLTIME_300_CYCLES <<
1017                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
1018
1019                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
1020                 if (err)
1021                         return err;
1022                 err = esr_write_glue0(np, i, glue0);
1023                 if (err)
1024                         return err;
1025         }
1026
1027
1028         sig = nr64(ESR_INT_SIGNALS);
1029         switch (np->port) {
1030         case 0:
1031                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1032                 mask = val;
1033                 break;
1034
1035         case 1:
1036                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1037                 mask = val;
1038                 break;
1039
1040         default:
1041                 return -EINVAL;
1042         }
1043
1044         if ((sig & mask) != val) {
1045                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
1046                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
1047                 return -ENODEV;
1048         }
1049
1050         return 0;
1051 }
1052
1053 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1054 {
1055         struct niu_link_config *lp = &np->link_config;
1056         int link_up;
1057         u64 val;
1058         u16 current_speed;
1059         unsigned long flags;
1060         u8 current_duplex;
1061
1062         link_up = 0;
1063         current_speed = SPEED_INVALID;
1064         current_duplex = DUPLEX_INVALID;
1065
1066         spin_lock_irqsave(&np->lock, flags);
1067
1068         val = nr64_pcs(PCS_MII_STAT);
1069
1070         if (val & PCS_MII_STAT_LINK_STATUS) {
1071                 link_up = 1;
1072                 current_speed = SPEED_1000;
1073                 current_duplex = DUPLEX_FULL;
1074         }
1075
1076         lp->active_speed = current_speed;
1077         lp->active_duplex = current_duplex;
1078         spin_unlock_irqrestore(&np->lock, flags);
1079
1080         *link_up_p = link_up;
1081         return 0;
1082 }
1083
1084 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1085 {
1086         unsigned long flags;
1087         struct niu_link_config *lp = &np->link_config;
1088         int link_up = 0;
1089         int link_ok = 1;
1090         u64 val, val2;
1091         u16 current_speed;
1092         u8 current_duplex;
1093
1094         if (!(np->flags & NIU_FLAGS_10G))
1095                 return link_status_1g_serdes(np, link_up_p);
1096
1097         current_speed = SPEED_INVALID;
1098         current_duplex = DUPLEX_INVALID;
1099         spin_lock_irqsave(&np->lock, flags);
1100
1101         val = nr64_xpcs(XPCS_STATUS(0));
1102         val2 = nr64_mac(XMAC_INTER2);
1103         if (val2 & 0x01000000)
1104                 link_ok = 0;
1105
1106         if ((val & 0x1000ULL) && link_ok) {
1107                 link_up = 1;
1108                 current_speed = SPEED_10000;
1109                 current_duplex = DUPLEX_FULL;
1110         }
1111         lp->active_speed = current_speed;
1112         lp->active_duplex = current_duplex;
1113         spin_unlock_irqrestore(&np->lock, flags);
1114         *link_up_p = link_up;
1115         return 0;
1116 }
1117
1118 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1119 {
1120         struct niu_link_config *lp = &np->link_config;
1121         u16 current_speed, bmsr;
1122         unsigned long flags;
1123         u8 current_duplex;
1124         int err, link_up;
1125
1126         link_up = 0;
1127         current_speed = SPEED_INVALID;
1128         current_duplex = DUPLEX_INVALID;
1129
1130         spin_lock_irqsave(&np->lock, flags);
1131
1132         err = -EINVAL;
1133
1134         err = mii_read(np, np->phy_addr, MII_BMSR);
1135         if (err < 0)
1136                 goto out;
1137
1138         bmsr = err;
1139         if (bmsr & BMSR_LSTATUS) {
1140                 u16 adv, lpa, common, estat;
1141
1142                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1143                 if (err < 0)
1144                         goto out;
1145                 adv = err;
1146
1147                 err = mii_read(np, np->phy_addr, MII_LPA);
1148                 if (err < 0)
1149                         goto out;
1150                 lpa = err;
1151
1152                 common = adv & lpa;
1153
1154                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1155                 if (err < 0)
1156                         goto out;
1157                 estat = err;
1158                 link_up = 1;
1159                 current_speed = SPEED_1000;
1160                 current_duplex = DUPLEX_FULL;
1161
1162         }
1163         lp->active_speed = current_speed;
1164         lp->active_duplex = current_duplex;
1165         err = 0;
1166
1167 out:
1168         spin_unlock_irqrestore(&np->lock, flags);
1169
1170         *link_up_p = link_up;
1171         return err;
1172 }
1173
1174 static int bcm8704_reset(struct niu *np)
1175 {
1176         int err, limit;
1177
1178         err = mdio_read(np, np->phy_addr,
1179                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1180         if (err < 0)
1181                 return err;
1182         err |= BMCR_RESET;
1183         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1184                          MII_BMCR, err);
1185         if (err)
1186                 return err;
1187
1188         limit = 1000;
1189         while (--limit >= 0) {
1190                 err = mdio_read(np, np->phy_addr,
1191                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1192                 if (err < 0)
1193                         return err;
1194                 if (!(err & BMCR_RESET))
1195                         break;
1196         }
1197         if (limit < 0) {
1198                 dev_err(np->device, PFX "Port %u PHY will not reset "
1199                         "(bmcr=%04x)\n", np->port, (err & 0xffff));
1200                 return -ENODEV;
1201         }
1202         return 0;
1203 }
1204
1205 /* When written, certain PHY registers need to be read back twice
1206  * in order for the bits to settle properly.
1207  */
1208 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1209 {
1210         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1211         if (err < 0)
1212                 return err;
1213         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1214         if (err < 0)
1215                 return err;
1216         return 0;
1217 }
1218
1219 static int bcm8706_init_user_dev3(struct niu *np)
1220 {
1221         int err;
1222
1223
1224         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1225                         BCM8704_USER_OPT_DIGITAL_CTRL);
1226         if (err < 0)
1227                 return err;
1228         err &= ~USER_ODIG_CTRL_GPIOS;
1229         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1230         err |=  USER_ODIG_CTRL_RESV2;
1231         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1232                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1233         if (err)
1234                 return err;
1235
1236         mdelay(1000);
1237
1238         return 0;
1239 }
1240
1241 static int bcm8704_init_user_dev3(struct niu *np)
1242 {
1243         int err;
1244
1245         err = mdio_write(np, np->phy_addr,
1246                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1247                          (USER_CONTROL_OPTXRST_LVL |
1248                           USER_CONTROL_OPBIASFLT_LVL |
1249                           USER_CONTROL_OBTMPFLT_LVL |
1250                           USER_CONTROL_OPPRFLT_LVL |
1251                           USER_CONTROL_OPTXFLT_LVL |
1252                           USER_CONTROL_OPRXLOS_LVL |
1253                           USER_CONTROL_OPRXFLT_LVL |
1254                           USER_CONTROL_OPTXON_LVL |
1255                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1256         if (err)
1257                 return err;
1258
1259         err = mdio_write(np, np->phy_addr,
1260                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1261                          (USER_PMD_TX_CTL_XFP_CLKEN |
1262                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1263                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1264                           USER_PMD_TX_CTL_TSCK_LPWREN));
1265         if (err)
1266                 return err;
1267
1268         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1269         if (err)
1270                 return err;
1271         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1272         if (err)
1273                 return err;
1274
1275         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1276                         BCM8704_USER_OPT_DIGITAL_CTRL);
1277         if (err < 0)
1278                 return err;
1279         err &= ~USER_ODIG_CTRL_GPIOS;
1280         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1281         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1282                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1283         if (err)
1284                 return err;
1285
1286         mdelay(1000);
1287
1288         return 0;
1289 }
1290
1291 static int mrvl88x2011_act_led(struct niu *np, int val)
1292 {
1293         int     err;
1294
1295         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1296                 MRVL88X2011_LED_8_TO_11_CTL);
1297         if (err < 0)
1298                 return err;
1299
1300         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1301         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1302
1303         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1304                           MRVL88X2011_LED_8_TO_11_CTL, err);
1305 }
1306
1307 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1308 {
1309         int     err;
1310
1311         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1312                         MRVL88X2011_LED_BLINK_CTL);
1313         if (err >= 0) {
1314                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1315                 err |= (rate << 4);
1316
1317                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1318                                  MRVL88X2011_LED_BLINK_CTL, err);
1319         }
1320
1321         return err;
1322 }
1323
1324 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1325 {
1326         int     err;
1327
1328         /* Set LED functions */
1329         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1330         if (err)
1331                 return err;
1332
1333         /* led activity */
1334         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1335         if (err)
1336                 return err;
1337
1338         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1339                         MRVL88X2011_GENERAL_CTL);
1340         if (err < 0)
1341                 return err;
1342
1343         err |= MRVL88X2011_ENA_XFPREFCLK;
1344
1345         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1346                          MRVL88X2011_GENERAL_CTL, err);
1347         if (err < 0)
1348                 return err;
1349
1350         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1351                         MRVL88X2011_PMA_PMD_CTL_1);
1352         if (err < 0)
1353                 return err;
1354
1355         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1356                 err |= MRVL88X2011_LOOPBACK;
1357         else
1358                 err &= ~MRVL88X2011_LOOPBACK;
1359
1360         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1361                          MRVL88X2011_PMA_PMD_CTL_1, err);
1362         if (err < 0)
1363                 return err;
1364
1365         /* Enable PMD  */
1366         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1367                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1368 }
1369
1370
1371 static int xcvr_diag_bcm870x(struct niu *np)
1372 {
1373         u16 analog_stat0, tx_alarm_status;
1374         int err = 0;
1375
1376 #if 1
1377         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1378                         MII_STAT1000);
1379         if (err < 0)
1380                 return err;
1381         pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1382                 np->port, err);
1383
1384         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1385         if (err < 0)
1386                 return err;
1387         pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1388                 np->port, err);
1389
1390         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1391                         MII_NWAYTEST);
1392         if (err < 0)
1393                 return err;
1394         pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1395                 np->port, err);
1396 #endif
1397
1398         /* XXX dig this out it might not be so useful XXX */
1399         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1400                         BCM8704_USER_ANALOG_STATUS0);
1401         if (err < 0)
1402                 return err;
1403         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1404                         BCM8704_USER_ANALOG_STATUS0);
1405         if (err < 0)
1406                 return err;
1407         analog_stat0 = err;
1408
1409         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1410                         BCM8704_USER_TX_ALARM_STATUS);
1411         if (err < 0)
1412                 return err;
1413         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1414                         BCM8704_USER_TX_ALARM_STATUS);
1415         if (err < 0)
1416                 return err;
1417         tx_alarm_status = err;
1418
1419         if (analog_stat0 != 0x03fc) {
1420                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1421                         pr_info(PFX "Port %u cable not connected "
1422                                 "or bad cable.\n", np->port);
1423                 } else if (analog_stat0 == 0x639c) {
1424                         pr_info(PFX "Port %u optical module is bad "
1425                                 "or missing.\n", np->port);
1426                 }
1427         }
1428
1429         return 0;
1430 }
1431
1432 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1433 {
1434         struct niu_link_config *lp = &np->link_config;
1435         int err;
1436
1437         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1438                         MII_BMCR);
1439         if (err < 0)
1440                 return err;
1441
1442         err &= ~BMCR_LOOPBACK;
1443
1444         if (lp->loopback_mode == LOOPBACK_MAC)
1445                 err |= BMCR_LOOPBACK;
1446
1447         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1448                          MII_BMCR, err);
1449         if (err)
1450                 return err;
1451
1452         return 0;
1453 }
1454
1455 static int xcvr_init_10g_bcm8706(struct niu *np)
1456 {
1457         int err = 0;
1458         u64 val;
1459
1460         if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1461             (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1462                         return err;
1463
1464         val = nr64_mac(XMAC_CONFIG);
1465         val &= ~XMAC_CONFIG_LED_POLARITY;
1466         val |= XMAC_CONFIG_FORCE_LED_ON;
1467         nw64_mac(XMAC_CONFIG, val);
1468
1469         val = nr64(MIF_CONFIG);
1470         val |= MIF_CONFIG_INDIRECT_MODE;
1471         nw64(MIF_CONFIG, val);
1472
1473         err = bcm8704_reset(np);
1474         if (err)
1475                 return err;
1476
1477         err = xcvr_10g_set_lb_bcm870x(np);
1478         if (err)
1479                 return err;
1480
1481         err = bcm8706_init_user_dev3(np);
1482         if (err)
1483                 return err;
1484
1485         err = xcvr_diag_bcm870x(np);
1486         if (err)
1487                 return err;
1488
1489         return 0;
1490 }
1491
1492 static int xcvr_init_10g_bcm8704(struct niu *np)
1493 {
1494         int err;
1495
1496         err = bcm8704_reset(np);
1497         if (err)
1498                 return err;
1499
1500         err = bcm8704_init_user_dev3(np);
1501         if (err)
1502                 return err;
1503
1504         err = xcvr_10g_set_lb_bcm870x(np);
1505         if (err)
1506                 return err;
1507
1508         err =  xcvr_diag_bcm870x(np);
1509         if (err)
1510                 return err;
1511
1512         return 0;
1513 }
1514
1515 static int xcvr_init_10g(struct niu *np)
1516 {
1517         int phy_id, err;
1518         u64 val;
1519
1520         val = nr64_mac(XMAC_CONFIG);
1521         val &= ~XMAC_CONFIG_LED_POLARITY;
1522         val |= XMAC_CONFIG_FORCE_LED_ON;
1523         nw64_mac(XMAC_CONFIG, val);
1524
1525         /* XXX shared resource, lock parent XXX */
1526         val = nr64(MIF_CONFIG);
1527         val |= MIF_CONFIG_INDIRECT_MODE;
1528         nw64(MIF_CONFIG, val);
1529
1530         phy_id = phy_decode(np->parent->port_phy, np->port);
1531         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1532
1533         /* handle different phy types */
1534         switch (phy_id & NIU_PHY_ID_MASK) {
1535         case NIU_PHY_ID_MRVL88X2011:
1536                 err = xcvr_init_10g_mrvl88x2011(np);
1537                 break;
1538
1539         default: /* bcom 8704 */
1540                 err = xcvr_init_10g_bcm8704(np);
1541                 break;
1542         }
1543
1544         return 0;
1545 }
1546
1547 static int mii_reset(struct niu *np)
1548 {
1549         int limit, err;
1550
1551         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1552         if (err)
1553                 return err;
1554
1555         limit = 1000;
1556         while (--limit >= 0) {
1557                 udelay(500);
1558                 err = mii_read(np, np->phy_addr, MII_BMCR);
1559                 if (err < 0)
1560                         return err;
1561                 if (!(err & BMCR_RESET))
1562                         break;
1563         }
1564         if (limit < 0) {
1565                 dev_err(np->device, PFX "Port %u MII would not reset, "
1566                         "bmcr[%04x]\n", np->port, err);
1567                 return -ENODEV;
1568         }
1569
1570         return 0;
1571 }
1572
1573 static int xcvr_init_1g_rgmii(struct niu *np)
1574 {
1575         int err;
1576         u64 val;
1577         u16 bmcr, bmsr, estat;
1578
1579         val = nr64(MIF_CONFIG);
1580         val &= ~MIF_CONFIG_INDIRECT_MODE;
1581         nw64(MIF_CONFIG, val);
1582
1583         err = mii_reset(np);
1584         if (err)
1585                 return err;
1586
1587         err = mii_read(np, np->phy_addr, MII_BMSR);
1588         if (err < 0)
1589                 return err;
1590         bmsr = err;
1591
1592         estat = 0;
1593         if (bmsr & BMSR_ESTATEN) {
1594                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1595                 if (err < 0)
1596                         return err;
1597                 estat = err;
1598         }
1599
1600         bmcr = 0;
1601         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1602         if (err)
1603                 return err;
1604
1605         if (bmsr & BMSR_ESTATEN) {
1606                 u16 ctrl1000 = 0;
1607
1608                 if (estat & ESTATUS_1000_TFULL)
1609                         ctrl1000 |= ADVERTISE_1000FULL;
1610                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1611                 if (err)
1612                         return err;
1613         }
1614
1615         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1616
1617         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1618         if (err)
1619                 return err;
1620
1621         err = mii_read(np, np->phy_addr, MII_BMCR);
1622         if (err < 0)
1623                 return err;
1624         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1625
1626         err = mii_read(np, np->phy_addr, MII_BMSR);
1627         if (err < 0)
1628                 return err;
1629
1630         return 0;
1631 }
1632
1633 static int mii_init_common(struct niu *np)
1634 {
1635         struct niu_link_config *lp = &np->link_config;
1636         u16 bmcr, bmsr, adv, estat;
1637         int err;
1638
1639         err = mii_reset(np);
1640         if (err)
1641                 return err;
1642
1643         err = mii_read(np, np->phy_addr, MII_BMSR);
1644         if (err < 0)
1645                 return err;
1646         bmsr = err;
1647
1648         estat = 0;
1649         if (bmsr & BMSR_ESTATEN) {
1650                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1651                 if (err < 0)
1652                         return err;
1653                 estat = err;
1654         }
1655
1656         bmcr = 0;
1657         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1658         if (err)
1659                 return err;
1660
1661         if (lp->loopback_mode == LOOPBACK_MAC) {
1662                 bmcr |= BMCR_LOOPBACK;
1663                 if (lp->active_speed == SPEED_1000)
1664                         bmcr |= BMCR_SPEED1000;
1665                 if (lp->active_duplex == DUPLEX_FULL)
1666                         bmcr |= BMCR_FULLDPLX;
1667         }
1668
1669         if (lp->loopback_mode == LOOPBACK_PHY) {
1670                 u16 aux;
1671
1672                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1673                        BCM5464R_AUX_CTL_WRITE_1);
1674                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1675                 if (err)
1676                         return err;
1677         }
1678
1679         /* XXX configurable XXX */
1680         /* XXX for now don't advertise half-duplex or asym pause... XXX */
1681         adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1682         if (bmsr & BMSR_10FULL)
1683                 adv |= ADVERTISE_10FULL;
1684         if (bmsr & BMSR_100FULL)
1685                 adv |= ADVERTISE_100FULL;
1686         err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1687         if (err)
1688                 return err;
1689
1690         if (bmsr & BMSR_ESTATEN) {
1691                 u16 ctrl1000 = 0;
1692
1693                 if (estat & ESTATUS_1000_TFULL)
1694                         ctrl1000 |= ADVERTISE_1000FULL;
1695                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1696                 if (err)
1697                         return err;
1698         }
1699         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1700
1701         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1702         if (err)
1703                 return err;
1704
1705         err = mii_read(np, np->phy_addr, MII_BMCR);
1706         if (err < 0)
1707                 return err;
1708         err = mii_read(np, np->phy_addr, MII_BMSR);
1709         if (err < 0)
1710                 return err;
1711 #if 0
1712         pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1713                 np->port, bmcr, bmsr);
1714 #endif
1715
1716         return 0;
1717 }
1718
1719 static int xcvr_init_1g(struct niu *np)
1720 {
1721         u64 val;
1722
1723         /* XXX shared resource, lock parent XXX */
1724         val = nr64(MIF_CONFIG);
1725         val &= ~MIF_CONFIG_INDIRECT_MODE;
1726         nw64(MIF_CONFIG, val);
1727
1728         return mii_init_common(np);
1729 }
1730
1731 static int niu_xcvr_init(struct niu *np)
1732 {
1733         const struct niu_phy_ops *ops = np->phy_ops;
1734         int err;
1735
1736         err = 0;
1737         if (ops->xcvr_init)
1738                 err = ops->xcvr_init(np);
1739
1740         return err;
1741 }
1742
1743 static int niu_serdes_init(struct niu *np)
1744 {
1745         const struct niu_phy_ops *ops = np->phy_ops;
1746         int err;
1747
1748         err = 0;
1749         if (ops->serdes_init)
1750                 err = ops->serdes_init(np);
1751
1752         return err;
1753 }
1754
1755 static void niu_init_xif(struct niu *);
1756 static void niu_handle_led(struct niu *, int status);
1757
1758 static int niu_link_status_common(struct niu *np, int link_up)
1759 {
1760         struct niu_link_config *lp = &np->link_config;
1761         struct net_device *dev = np->dev;
1762         unsigned long flags;
1763
1764         if (!netif_carrier_ok(dev) && link_up) {
1765                 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1766                        dev->name,
1767                        (lp->active_speed == SPEED_10000 ?
1768                         "10Gb/sec" :
1769                         (lp->active_speed == SPEED_1000 ?
1770                          "1Gb/sec" :
1771                          (lp->active_speed == SPEED_100 ?
1772                           "100Mbit/sec" : "10Mbit/sec"))),
1773                        (lp->active_duplex == DUPLEX_FULL ?
1774                         "full" : "half"));
1775
1776                 spin_lock_irqsave(&np->lock, flags);
1777                 niu_init_xif(np);
1778                 niu_handle_led(np, 1);
1779                 spin_unlock_irqrestore(&np->lock, flags);
1780
1781                 netif_carrier_on(dev);
1782         } else if (netif_carrier_ok(dev) && !link_up) {
1783                 niuwarn(LINK, "%s: Link is down\n", dev->name);
1784                 spin_lock_irqsave(&np->lock, flags);
1785                 niu_handle_led(np, 0);
1786                 spin_unlock_irqrestore(&np->lock, flags);
1787                 netif_carrier_off(dev);
1788         }
1789
1790         return 0;
1791 }
1792
1793 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1794 {
1795         int err, link_up, pma_status, pcs_status;
1796
1797         link_up = 0;
1798
1799         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1800                         MRVL88X2011_10G_PMD_STATUS_2);
1801         if (err < 0)
1802                 goto out;
1803
1804         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1805         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1806                         MRVL88X2011_PMA_PMD_STATUS_1);
1807         if (err < 0)
1808                 goto out;
1809
1810         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1811
1812         /* Check PMC Register : 3.0001.2 == 1: read twice */
1813         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1814                         MRVL88X2011_PMA_PMD_STATUS_1);
1815         if (err < 0)
1816                 goto out;
1817
1818         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1819                         MRVL88X2011_PMA_PMD_STATUS_1);
1820         if (err < 0)
1821                 goto out;
1822
1823         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1824
1825         /* Check XGXS Register : 4.0018.[0-3,12] */
1826         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1827                         MRVL88X2011_10G_XGXS_LANE_STAT);
1828         if (err < 0)
1829                 goto out;
1830
1831         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1832                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1833                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1834                     0x800))
1835                 link_up = (pma_status && pcs_status) ? 1 : 0;
1836
1837         np->link_config.active_speed = SPEED_10000;
1838         np->link_config.active_duplex = DUPLEX_FULL;
1839         err = 0;
1840 out:
1841         mrvl88x2011_act_led(np, (link_up ?
1842                                  MRVL88X2011_LED_CTL_PCS_ACT :
1843                                  MRVL88X2011_LED_CTL_OFF));
1844
1845         *link_up_p = link_up;
1846         return err;
1847 }
1848
1849 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
1850 {
1851         int err, link_up;
1852         link_up = 0;
1853
1854         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1855                         BCM8704_PMD_RCV_SIGDET);
1856         if (err < 0)
1857                 goto out;
1858         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1859                 err = 0;
1860                 goto out;
1861         }
1862
1863         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1864                         BCM8704_PCS_10G_R_STATUS);
1865         if (err < 0)
1866                 goto out;
1867
1868         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1869                 err = 0;
1870                 goto out;
1871         }
1872
1873         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1874                         BCM8704_PHYXS_XGXS_LANE_STAT);
1875         if (err < 0)
1876                 goto out;
1877         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1878                     PHYXS_XGXS_LANE_STAT_MAGIC |
1879                     PHYXS_XGXS_LANE_STAT_PATTEST |
1880                     PHYXS_XGXS_LANE_STAT_LANE3 |
1881                     PHYXS_XGXS_LANE_STAT_LANE2 |
1882                     PHYXS_XGXS_LANE_STAT_LANE1 |
1883                     PHYXS_XGXS_LANE_STAT_LANE0)) {
1884                 err = 0;
1885                 np->link_config.active_speed = SPEED_INVALID;
1886                 np->link_config.active_duplex = DUPLEX_INVALID;
1887                 goto out;
1888         }
1889
1890         link_up = 1;
1891         np->link_config.active_speed = SPEED_10000;
1892         np->link_config.active_duplex = DUPLEX_FULL;
1893         err = 0;
1894
1895 out:
1896         *link_up_p = link_up;
1897         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
1898                 err = 0;
1899         return err;
1900 }
1901
1902 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
1903 {
1904         int err, link_up;
1905
1906         link_up = 0;
1907
1908         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1909                         BCM8704_PMD_RCV_SIGDET);
1910         if (err < 0)
1911                 goto out;
1912         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1913                 err = 0;
1914                 goto out;
1915         }
1916
1917         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1918                         BCM8704_PCS_10G_R_STATUS);
1919         if (err < 0)
1920                 goto out;
1921         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1922                 err = 0;
1923                 goto out;
1924         }
1925
1926         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1927                         BCM8704_PHYXS_XGXS_LANE_STAT);
1928         if (err < 0)
1929                 goto out;
1930
1931         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1932                     PHYXS_XGXS_LANE_STAT_MAGIC |
1933                     PHYXS_XGXS_LANE_STAT_LANE3 |
1934                     PHYXS_XGXS_LANE_STAT_LANE2 |
1935                     PHYXS_XGXS_LANE_STAT_LANE1 |
1936                     PHYXS_XGXS_LANE_STAT_LANE0)) {
1937                 err = 0;
1938                 goto out;
1939         }
1940
1941         link_up = 1;
1942         np->link_config.active_speed = SPEED_10000;
1943         np->link_config.active_duplex = DUPLEX_FULL;
1944         err = 0;
1945
1946 out:
1947         *link_up_p = link_up;
1948         return err;
1949 }
1950
1951 static int link_status_10g(struct niu *np, int *link_up_p)
1952 {
1953         unsigned long flags;
1954         int err = -EINVAL;
1955
1956         spin_lock_irqsave(&np->lock, flags);
1957
1958         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
1959                 int phy_id;
1960
1961                 phy_id = phy_decode(np->parent->port_phy, np->port);
1962                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1963
1964                 /* handle different phy types */
1965                 switch (phy_id & NIU_PHY_ID_MASK) {
1966                 case NIU_PHY_ID_MRVL88X2011:
1967                         err = link_status_10g_mrvl(np, link_up_p);
1968                         break;
1969
1970                 default: /* bcom 8704 */
1971                         err = link_status_10g_bcom(np, link_up_p);
1972                         break;
1973                 }
1974         }
1975
1976         spin_unlock_irqrestore(&np->lock, flags);
1977
1978         return err;
1979 }
1980
1981 static int niu_10g_phy_present(struct niu *np)
1982 {
1983         u64 sig, mask, val;
1984
1985         sig = nr64(ESR_INT_SIGNALS);
1986         switch (np->port) {
1987         case 0:
1988                 mask = ESR_INT_SIGNALS_P0_BITS;
1989                 val = (ESR_INT_SRDY0_P0 |
1990                        ESR_INT_DET0_P0 |
1991                        ESR_INT_XSRDY_P0 |
1992                        ESR_INT_XDP_P0_CH3 |
1993                        ESR_INT_XDP_P0_CH2 |
1994                        ESR_INT_XDP_P0_CH1 |
1995                        ESR_INT_XDP_P0_CH0);
1996                 break;
1997
1998         case 1:
1999                 mask = ESR_INT_SIGNALS_P1_BITS;
2000                 val = (ESR_INT_SRDY0_P1 |
2001                        ESR_INT_DET0_P1 |
2002                        ESR_INT_XSRDY_P1 |
2003                        ESR_INT_XDP_P1_CH3 |
2004                        ESR_INT_XDP_P1_CH2 |
2005                        ESR_INT_XDP_P1_CH1 |
2006                        ESR_INT_XDP_P1_CH0);
2007                 break;
2008
2009         default:
2010                 return 0;
2011         }
2012
2013         if ((sig & mask) != val)
2014                 return 0;
2015         return 1;
2016 }
2017
2018 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2019 {
2020         unsigned long flags;
2021         int err = 0;
2022         int phy_present;
2023         int phy_present_prev;
2024
2025         spin_lock_irqsave(&np->lock, flags);
2026
2027         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2028                 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2029                         1 : 0;
2030                 phy_present = niu_10g_phy_present(np);
2031                 if (phy_present != phy_present_prev) {
2032                         /* state change */
2033                         if (phy_present) {
2034                                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2035                                 if (np->phy_ops->xcvr_init)
2036                                         err = np->phy_ops->xcvr_init(np);
2037                                 if (err) {
2038                                         /* debounce */
2039                                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2040                                 }
2041                         } else {
2042                                 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2043                                 *link_up_p = 0;
2044                                 niuwarn(LINK, "%s: Hotplug PHY Removed\n",
2045                                         np->dev->name);
2046                         }
2047                 }
2048                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT)
2049                         err = link_status_10g_bcm8706(np, link_up_p);
2050         }
2051
2052         spin_unlock_irqrestore(&np->lock, flags);
2053
2054         return err;
2055 }
2056
2057 static int link_status_1g(struct niu *np, int *link_up_p)
2058 {
2059         struct niu_link_config *lp = &np->link_config;
2060         u16 current_speed, bmsr;
2061         unsigned long flags;
2062         u8 current_duplex;
2063         int err, link_up;
2064
2065         link_up = 0;
2066         current_speed = SPEED_INVALID;
2067         current_duplex = DUPLEX_INVALID;
2068
2069         spin_lock_irqsave(&np->lock, flags);
2070
2071         err = -EINVAL;
2072         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
2073                 goto out;
2074
2075         err = mii_read(np, np->phy_addr, MII_BMSR);
2076         if (err < 0)
2077                 goto out;
2078
2079         bmsr = err;
2080         if (bmsr & BMSR_LSTATUS) {
2081                 u16 adv, lpa, common, estat;
2082
2083                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
2084                 if (err < 0)
2085                         goto out;
2086                 adv = err;
2087
2088                 err = mii_read(np, np->phy_addr, MII_LPA);
2089                 if (err < 0)
2090                         goto out;
2091                 lpa = err;
2092
2093                 common = adv & lpa;
2094
2095                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
2096                 if (err < 0)
2097                         goto out;
2098                 estat = err;
2099
2100                 link_up = 1;
2101                 if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
2102                         current_speed = SPEED_1000;
2103                         if (estat & ESTATUS_1000_TFULL)
2104                                 current_duplex = DUPLEX_FULL;
2105                         else
2106                                 current_duplex = DUPLEX_HALF;
2107                 } else {
2108                         if (common & ADVERTISE_100BASE4) {
2109                                 current_speed = SPEED_100;
2110                                 current_duplex = DUPLEX_HALF;
2111                         } else if (common & ADVERTISE_100FULL) {
2112                                 current_speed = SPEED_100;
2113                                 current_duplex = DUPLEX_FULL;
2114                         } else if (common & ADVERTISE_100HALF) {
2115                                 current_speed = SPEED_100;
2116                                 current_duplex = DUPLEX_HALF;
2117                         } else if (common & ADVERTISE_10FULL) {
2118                                 current_speed = SPEED_10;
2119                                 current_duplex = DUPLEX_FULL;
2120                         } else if (common & ADVERTISE_10HALF) {
2121                                 current_speed = SPEED_10;
2122                                 current_duplex = DUPLEX_HALF;
2123                         } else
2124                                 link_up = 0;
2125                 }
2126         }
2127         lp->active_speed = current_speed;
2128         lp->active_duplex = current_duplex;
2129         err = 0;
2130
2131 out:
2132         spin_unlock_irqrestore(&np->lock, flags);
2133
2134         *link_up_p = link_up;
2135         return err;
2136 }
2137
2138 static int niu_link_status(struct niu *np, int *link_up_p)
2139 {
2140         const struct niu_phy_ops *ops = np->phy_ops;
2141         int err;
2142
2143         err = 0;
2144         if (ops->link_status)
2145                 err = ops->link_status(np, link_up_p);
2146
2147         return err;
2148 }
2149
2150 static void niu_timer(unsigned long __opaque)
2151 {
2152         struct niu *np = (struct niu *) __opaque;
2153         unsigned long off;
2154         int err, link_up;
2155
2156         err = niu_link_status(np, &link_up);
2157         if (!err)
2158                 niu_link_status_common(np, link_up);
2159
2160         if (netif_carrier_ok(np->dev))
2161                 off = 5 * HZ;
2162         else
2163                 off = 1 * HZ;
2164         np->timer.expires = jiffies + off;
2165
2166         add_timer(&np->timer);
2167 }
2168
2169 static const struct niu_phy_ops phy_ops_10g_serdes = {
2170         .serdes_init            = serdes_init_10g_serdes,
2171         .link_status            = link_status_10g_serdes,
2172 };
2173
2174 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2175         .serdes_init            = serdes_init_niu_10g_serdes,
2176         .link_status            = link_status_10g_serdes,
2177 };
2178
2179 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2180         .serdes_init            = serdes_init_niu_1g_serdes,
2181         .link_status            = link_status_1g_serdes,
2182 };
2183
2184 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2185         .xcvr_init              = xcvr_init_1g_rgmii,
2186         .link_status            = link_status_1g_rgmii,
2187 };
2188
2189 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2190         .serdes_init            = serdes_init_niu_10g_fiber,
2191         .xcvr_init              = xcvr_init_10g,
2192         .link_status            = link_status_10g,
2193 };
2194
2195 static const struct niu_phy_ops phy_ops_10g_fiber = {
2196         .serdes_init            = serdes_init_10g,
2197         .xcvr_init              = xcvr_init_10g,
2198         .link_status            = link_status_10g,
2199 };
2200
2201 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2202         .serdes_init            = serdes_init_10g,
2203         .xcvr_init              = xcvr_init_10g_bcm8706,
2204         .link_status            = link_status_10g_hotplug,
2205 };
2206
2207 static const struct niu_phy_ops phy_ops_10g_copper = {
2208         .serdes_init            = serdes_init_10g,
2209         .link_status            = link_status_10g, /* XXX */
2210 };
2211
2212 static const struct niu_phy_ops phy_ops_1g_fiber = {
2213         .serdes_init            = serdes_init_1g,
2214         .xcvr_init              = xcvr_init_1g,
2215         .link_status            = link_status_1g,
2216 };
2217
2218 static const struct niu_phy_ops phy_ops_1g_copper = {
2219         .xcvr_init              = xcvr_init_1g,
2220         .link_status            = link_status_1g,
2221 };
2222
2223 struct niu_phy_template {
2224         const struct niu_phy_ops        *ops;
2225         u32                             phy_addr_base;
2226 };
2227
2228 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2229         .ops            = &phy_ops_10g_fiber_niu,
2230         .phy_addr_base  = 16,
2231 };
2232
2233 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2234         .ops            = &phy_ops_10g_serdes_niu,
2235         .phy_addr_base  = 0,
2236 };
2237
2238 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2239         .ops            = &phy_ops_1g_serdes_niu,
2240         .phy_addr_base  = 0,
2241 };
2242
2243 static const struct niu_phy_template phy_template_10g_fiber = {
2244         .ops            = &phy_ops_10g_fiber,
2245         .phy_addr_base  = 8,
2246 };
2247
2248 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2249         .ops            = &phy_ops_10g_fiber_hotplug,
2250         .phy_addr_base  = 8,
2251 };
2252
2253 static const struct niu_phy_template phy_template_10g_copper = {
2254         .ops            = &phy_ops_10g_copper,
2255         .phy_addr_base  = 10,
2256 };
2257
2258 static const struct niu_phy_template phy_template_1g_fiber = {
2259         .ops            = &phy_ops_1g_fiber,
2260         .phy_addr_base  = 0,
2261 };
2262
2263 static const struct niu_phy_template phy_template_1g_copper = {
2264         .ops            = &phy_ops_1g_copper,
2265         .phy_addr_base  = 0,
2266 };
2267
2268 static const struct niu_phy_template phy_template_1g_rgmii = {
2269         .ops            = &phy_ops_1g_rgmii,
2270         .phy_addr_base  = 0,
2271 };
2272
2273 static const struct niu_phy_template phy_template_10g_serdes = {
2274         .ops            = &phy_ops_10g_serdes,
2275         .phy_addr_base  = 0,
2276 };
2277
2278 static int niu_atca_port_num[4] = {
2279         0, 0,  11, 10
2280 };
2281
2282 static int serdes_init_10g_serdes(struct niu *np)
2283 {
2284         struct niu_link_config *lp = &np->link_config;
2285         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2286         u64 ctrl_val, test_cfg_val, sig, mask, val;
2287         int err;
2288         u64 reset_val;
2289
2290         switch (np->port) {
2291         case 0:
2292                 reset_val =  ENET_SERDES_RESET_0;
2293                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2294                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2295                 pll_cfg = ENET_SERDES_0_PLL_CFG;
2296                 break;
2297         case 1:
2298                 reset_val =  ENET_SERDES_RESET_1;
2299                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2300                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2301                 pll_cfg = ENET_SERDES_1_PLL_CFG;
2302                 break;
2303
2304         default:
2305                 return -EINVAL;
2306         }
2307         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2308                     ENET_SERDES_CTRL_SDET_1 |
2309                     ENET_SERDES_CTRL_SDET_2 |
2310                     ENET_SERDES_CTRL_SDET_3 |
2311                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2312                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2313                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2314                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2315                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2316                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2317                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2318                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2319         test_cfg_val = 0;
2320
2321         if (lp->loopback_mode == LOOPBACK_PHY) {
2322                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2323                                   ENET_SERDES_TEST_MD_0_SHIFT) |
2324                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2325                                   ENET_SERDES_TEST_MD_1_SHIFT) |
2326                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2327                                   ENET_SERDES_TEST_MD_2_SHIFT) |
2328                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2329                                   ENET_SERDES_TEST_MD_3_SHIFT));
2330         }
2331
2332         esr_reset(np);
2333         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2334         nw64(ctrl_reg, ctrl_val);
2335         nw64(test_cfg_reg, test_cfg_val);
2336
2337         /* Initialize all 4 lanes of the SERDES.  */
2338         for (i = 0; i < 4; i++) {
2339                 u32 rxtx_ctrl, glue0;
2340
2341                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2342                 if (err)
2343                         return err;
2344                 err = esr_read_glue0(np, i, &glue0);
2345                 if (err)
2346                         return err;
2347
2348                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2349                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2350                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2351
2352                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2353                            ESR_GLUE_CTRL0_THCNT |
2354                            ESR_GLUE_CTRL0_BLTIME);
2355                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2356                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2357                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2358                           (BLTIME_300_CYCLES <<
2359                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
2360
2361                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2362                 if (err)
2363                         return err;
2364                 err = esr_write_glue0(np, i, glue0);
2365                 if (err)
2366                         return err;
2367         }
2368
2369
2370         sig = nr64(ESR_INT_SIGNALS);
2371         switch (np->port) {
2372         case 0:
2373                 mask = ESR_INT_SIGNALS_P0_BITS;
2374                 val = (ESR_INT_SRDY0_P0 |
2375                        ESR_INT_DET0_P0 |
2376                        ESR_INT_XSRDY_P0 |
2377                        ESR_INT_XDP_P0_CH3 |
2378                        ESR_INT_XDP_P0_CH2 |
2379                        ESR_INT_XDP_P0_CH1 |
2380                        ESR_INT_XDP_P0_CH0);
2381                 break;
2382
2383         case 1:
2384                 mask = ESR_INT_SIGNALS_P1_BITS;
2385                 val = (ESR_INT_SRDY0_P1 |
2386                        ESR_INT_DET0_P1 |
2387                        ESR_INT_XSRDY_P1 |
2388                        ESR_INT_XDP_P1_CH3 |
2389                        ESR_INT_XDP_P1_CH2 |
2390                        ESR_INT_XDP_P1_CH1 |
2391                        ESR_INT_XDP_P1_CH0);
2392                 break;
2393
2394         default:
2395                 return -EINVAL;
2396         }
2397
2398         if ((sig & mask) != val) {
2399                 int err;
2400                 err = serdes_init_1g_serdes(np);
2401                 if (!err) {
2402                         np->flags &= ~NIU_FLAGS_10G;
2403                         np->mac_xcvr = MAC_XCVR_PCS;
2404                 }  else {
2405                         dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
2406                          np->port);
2407                         return -ENODEV;
2408                 }
2409         }
2410
2411         return 0;
2412 }
2413
2414 static int niu_determine_phy_disposition(struct niu *np)
2415 {
2416         struct niu_parent *parent = np->parent;
2417         u8 plat_type = parent->plat_type;
2418         const struct niu_phy_template *tp;
2419         u32 phy_addr_off = 0;
2420
2421         if (plat_type == PLAT_TYPE_NIU) {
2422                 switch (np->flags &
2423                         (NIU_FLAGS_10G |
2424                          NIU_FLAGS_FIBER |
2425                          NIU_FLAGS_XCVR_SERDES)) {
2426                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2427                         /* 10G Serdes */
2428                         tp = &phy_template_niu_10g_serdes;
2429                         break;
2430                 case NIU_FLAGS_XCVR_SERDES:
2431                         /* 1G Serdes */
2432                         tp = &phy_template_niu_1g_serdes;
2433                         break;
2434                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2435                         /* 10G Fiber */
2436                 default:
2437                         tp = &phy_template_niu_10g_fiber;
2438                         phy_addr_off += np->port;
2439                         break;
2440                 }
2441         } else {
2442                 switch (np->flags &
2443                         (NIU_FLAGS_10G |
2444                          NIU_FLAGS_FIBER |
2445                          NIU_FLAGS_XCVR_SERDES)) {
2446                 case 0:
2447                         /* 1G copper */
2448                         tp = &phy_template_1g_copper;
2449                         if (plat_type == PLAT_TYPE_VF_P0)
2450                                 phy_addr_off = 10;
2451                         else if (plat_type == PLAT_TYPE_VF_P1)
2452                                 phy_addr_off = 26;
2453
2454                         phy_addr_off += (np->port ^ 0x3);
2455                         break;
2456
2457                 case NIU_FLAGS_10G:
2458                         /* 10G copper */
2459                         tp = &phy_template_1g_copper;
2460                         break;
2461
2462                 case NIU_FLAGS_FIBER:
2463                         /* 1G fiber */
2464                         tp = &phy_template_1g_fiber;
2465                         break;
2466
2467                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2468                         /* 10G fiber */
2469                         tp = &phy_template_10g_fiber;
2470                         if (plat_type == PLAT_TYPE_VF_P0 ||
2471                             plat_type == PLAT_TYPE_VF_P1)
2472                                 phy_addr_off = 8;
2473                         phy_addr_off += np->port;
2474                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2475                                 tp = &phy_template_10g_fiber_hotplug;
2476                                 if (np->port == 0)
2477                                         phy_addr_off = 8;
2478                                 if (np->port == 1)
2479                                         phy_addr_off = 12;
2480                         }
2481                         break;
2482
2483                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2484                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2485                 case NIU_FLAGS_XCVR_SERDES:
2486                         switch(np->port) {
2487                         case 0:
2488                         case 1:
2489                                 tp = &phy_template_10g_serdes;
2490                                 break;
2491                         case 2:
2492                         case 3:
2493                                 tp = &phy_template_1g_rgmii;
2494                                 break;
2495                         default:
2496                                 return -EINVAL;
2497                                 break;
2498                         }
2499                         phy_addr_off = niu_atca_port_num[np->port];
2500                         break;
2501
2502                 default:
2503                         return -EINVAL;
2504                 }
2505         }
2506
2507         np->phy_ops = tp->ops;
2508         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2509
2510         return 0;
2511 }
2512
2513 static int niu_init_link(struct niu *np)
2514 {
2515         struct niu_parent *parent = np->parent;
2516         int err, ignore;
2517
2518         if (parent->plat_type == PLAT_TYPE_NIU) {
2519                 err = niu_xcvr_init(np);
2520                 if (err)
2521                         return err;
2522                 msleep(200);
2523         }
2524         err = niu_serdes_init(np);
2525         if (err)
2526                 return err;
2527         msleep(200);
2528         err = niu_xcvr_init(np);
2529         if (!err)
2530                 niu_link_status(np, &ignore);
2531         return 0;
2532 }
2533
2534 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2535 {
2536         u16 reg0 = addr[4] << 8 | addr[5];
2537         u16 reg1 = addr[2] << 8 | addr[3];
2538         u16 reg2 = addr[0] << 8 | addr[1];
2539
2540         if (np->flags & NIU_FLAGS_XMAC) {
2541                 nw64_mac(XMAC_ADDR0, reg0);
2542                 nw64_mac(XMAC_ADDR1, reg1);
2543                 nw64_mac(XMAC_ADDR2, reg2);
2544         } else {
2545                 nw64_mac(BMAC_ADDR0, reg0);
2546                 nw64_mac(BMAC_ADDR1, reg1);
2547                 nw64_mac(BMAC_ADDR2, reg2);
2548         }
2549 }
2550
2551 static int niu_num_alt_addr(struct niu *np)
2552 {
2553         if (np->flags & NIU_FLAGS_XMAC)
2554                 return XMAC_NUM_ALT_ADDR;
2555         else
2556                 return BMAC_NUM_ALT_ADDR;
2557 }
2558
2559 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2560 {
2561         u16 reg0 = addr[4] << 8 | addr[5];
2562         u16 reg1 = addr[2] << 8 | addr[3];
2563         u16 reg2 = addr[0] << 8 | addr[1];
2564
2565         if (index >= niu_num_alt_addr(np))
2566                 return -EINVAL;
2567
2568         if (np->flags & NIU_FLAGS_XMAC) {
2569                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2570                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2571                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2572         } else {
2573                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2574                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2575                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2576         }
2577
2578         return 0;
2579 }
2580
2581 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2582 {
2583         unsigned long reg;
2584         u64 val, mask;
2585
2586         if (index >= niu_num_alt_addr(np))
2587                 return -EINVAL;
2588
2589         if (np->flags & NIU_FLAGS_XMAC) {
2590                 reg = XMAC_ADDR_CMPEN;
2591                 mask = 1 << index;
2592         } else {
2593                 reg = BMAC_ADDR_CMPEN;
2594                 mask = 1 << (index + 1);
2595         }
2596
2597         val = nr64_mac(reg);
2598         if (on)
2599                 val |= mask;
2600         else
2601                 val &= ~mask;
2602         nw64_mac(reg, val);
2603
2604         return 0;
2605 }
2606
2607 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2608                                    int num, int mac_pref)
2609 {
2610         u64 val = nr64_mac(reg);
2611         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2612         val |= num;
2613         if (mac_pref)
2614                 val |= HOST_INFO_MPR;
2615         nw64_mac(reg, val);
2616 }
2617
2618 static int __set_rdc_table_num(struct niu *np,
2619                                int xmac_index, int bmac_index,
2620                                int rdc_table_num, int mac_pref)
2621 {
2622         unsigned long reg;
2623
2624         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2625                 return -EINVAL;
2626         if (np->flags & NIU_FLAGS_XMAC)
2627                 reg = XMAC_HOST_INFO(xmac_index);
2628         else
2629                 reg = BMAC_HOST_INFO(bmac_index);
2630         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2631         return 0;
2632 }
2633
2634 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2635                                          int mac_pref)
2636 {
2637         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2638 }
2639
2640 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2641                                            int mac_pref)
2642 {
2643         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2644 }
2645
2646 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2647                                      int table_num, int mac_pref)
2648 {
2649         if (idx >= niu_num_alt_addr(np))
2650                 return -EINVAL;
2651         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2652 }
2653
2654 static u64 vlan_entry_set_parity(u64 reg_val)
2655 {
2656         u64 port01_mask;
2657         u64 port23_mask;
2658
2659         port01_mask = 0x00ff;
2660         port23_mask = 0xff00;
2661
2662         if (hweight64(reg_val & port01_mask) & 1)
2663                 reg_val |= ENET_VLAN_TBL_PARITY0;
2664         else
2665                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2666
2667         if (hweight64(reg_val & port23_mask) & 1)
2668                 reg_val |= ENET_VLAN_TBL_PARITY1;
2669         else
2670                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2671
2672         return reg_val;
2673 }
2674
2675 static void vlan_tbl_write(struct niu *np, unsigned long index,
2676                            int port, int vpr, int rdc_table)
2677 {
2678         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2679
2680         reg_val &= ~((ENET_VLAN_TBL_VPR |
2681                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2682                      ENET_VLAN_TBL_SHIFT(port));
2683         if (vpr)
2684                 reg_val |= (ENET_VLAN_TBL_VPR <<
2685                             ENET_VLAN_TBL_SHIFT(port));
2686         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2687
2688         reg_val = vlan_entry_set_parity(reg_val);
2689
2690         nw64(ENET_VLAN_TBL(index), reg_val);
2691 }
2692
2693 static void vlan_tbl_clear(struct niu *np)
2694 {
2695         int i;
2696
2697         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2698                 nw64(ENET_VLAN_TBL(i), 0);
2699 }
2700
2701 static int tcam_wait_bit(struct niu *np, u64 bit)
2702 {
2703         int limit = 1000;
2704
2705         while (--limit > 0) {
2706                 if (nr64(TCAM_CTL) & bit)
2707                         break;
2708                 udelay(1);
2709         }
2710         if (limit < 0)
2711                 return -ENODEV;
2712
2713         return 0;
2714 }
2715
2716 static int tcam_flush(struct niu *np, int index)
2717 {
2718         nw64(TCAM_KEY_0, 0x00);
2719         nw64(TCAM_KEY_MASK_0, 0xff);
2720         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2721
2722         return tcam_wait_bit(np, TCAM_CTL_STAT);
2723 }
2724
2725 #if 0
2726 static int tcam_read(struct niu *np, int index,
2727                      u64 *key, u64 *mask)
2728 {
2729         int err;
2730
2731         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2732         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2733         if (!err) {
2734                 key[0] = nr64(TCAM_KEY_0);
2735                 key[1] = nr64(TCAM_KEY_1);
2736                 key[2] = nr64(TCAM_KEY_2);
2737                 key[3] = nr64(TCAM_KEY_3);
2738                 mask[0] = nr64(TCAM_KEY_MASK_0);
2739                 mask[1] = nr64(TCAM_KEY_MASK_1);
2740                 mask[2] = nr64(TCAM_KEY_MASK_2);
2741                 mask[3] = nr64(TCAM_KEY_MASK_3);
2742         }
2743         return err;
2744 }
2745 #endif
2746
2747 static int tcam_write(struct niu *np, int index,
2748                       u64 *key, u64 *mask)
2749 {
2750         nw64(TCAM_KEY_0, key[0]);
2751         nw64(TCAM_KEY_1, key[1]);
2752         nw64(TCAM_KEY_2, key[2]);
2753         nw64(TCAM_KEY_3, key[3]);
2754         nw64(TCAM_KEY_MASK_0, mask[0]);
2755         nw64(TCAM_KEY_MASK_1, mask[1]);
2756         nw64(TCAM_KEY_MASK_2, mask[2]);
2757         nw64(TCAM_KEY_MASK_3, mask[3]);
2758         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2759
2760         return tcam_wait_bit(np, TCAM_CTL_STAT);
2761 }
2762
2763 #if 0
2764 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2765 {
2766         int err;
2767
2768         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2769         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2770         if (!err)
2771                 *data = nr64(TCAM_KEY_1);
2772
2773         return err;
2774 }
2775 #endif
2776
2777 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2778 {
2779         nw64(TCAM_KEY_1, assoc_data);
2780         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2781
2782         return tcam_wait_bit(np, TCAM_CTL_STAT);
2783 }
2784
2785 static void tcam_enable(struct niu *np, int on)
2786 {
2787         u64 val = nr64(FFLP_CFG_1);
2788
2789         if (on)
2790                 val &= ~FFLP_CFG_1_TCAM_DIS;
2791         else
2792                 val |= FFLP_CFG_1_TCAM_DIS;
2793         nw64(FFLP_CFG_1, val);
2794 }
2795
2796 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2797 {
2798         u64 val = nr64(FFLP_CFG_1);
2799
2800         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2801                  FFLP_CFG_1_CAMLAT |
2802                  FFLP_CFG_1_CAMRATIO);
2803         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2804         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2805         nw64(FFLP_CFG_1, val);
2806
2807         val = nr64(FFLP_CFG_1);
2808         val |= FFLP_CFG_1_FFLPINITDONE;
2809         nw64(FFLP_CFG_1, val);
2810 }
2811
2812 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2813                                       int on)
2814 {
2815         unsigned long reg;
2816         u64 val;
2817
2818         if (class < CLASS_CODE_ETHERTYPE1 ||
2819             class > CLASS_CODE_ETHERTYPE2)
2820                 return -EINVAL;
2821
2822         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2823         val = nr64(reg);
2824         if (on)
2825                 val |= L2_CLS_VLD;
2826         else
2827                 val &= ~L2_CLS_VLD;
2828         nw64(reg, val);
2829
2830         return 0;
2831 }
2832
2833 #if 0
2834 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2835                                    u64 ether_type)
2836 {
2837         unsigned long reg;
2838         u64 val;
2839
2840         if (class < CLASS_CODE_ETHERTYPE1 ||
2841             class > CLASS_CODE_ETHERTYPE2 ||
2842             (ether_type & ~(u64)0xffff) != 0)
2843                 return -EINVAL;
2844
2845         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2846         val = nr64(reg);
2847         val &= ~L2_CLS_ETYPE;
2848         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2849         nw64(reg, val);
2850
2851         return 0;
2852 }
2853 #endif
2854
2855 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2856                                      int on)
2857 {
2858         unsigned long reg;
2859         u64 val;
2860
2861         if (class < CLASS_CODE_USER_PROG1 ||
2862             class > CLASS_CODE_USER_PROG4)
2863                 return -EINVAL;
2864
2865         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2866         val = nr64(reg);
2867         if (on)
2868                 val |= L3_CLS_VALID;
2869         else
2870                 val &= ~L3_CLS_VALID;
2871         nw64(reg, val);
2872
2873         return 0;
2874 }
2875
2876 #if 0
2877 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2878                                   int ipv6, u64 protocol_id,
2879                                   u64 tos_mask, u64 tos_val)
2880 {
2881         unsigned long reg;
2882         u64 val;
2883
2884         if (class < CLASS_CODE_USER_PROG1 ||
2885             class > CLASS_CODE_USER_PROG4 ||
2886             (protocol_id & ~(u64)0xff) != 0 ||
2887             (tos_mask & ~(u64)0xff) != 0 ||
2888             (tos_val & ~(u64)0xff) != 0)
2889                 return -EINVAL;
2890
2891         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2892         val = nr64(reg);
2893         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2894                  L3_CLS_TOSMASK | L3_CLS_TOS);
2895         if (ipv6)
2896                 val |= L3_CLS_IPVER;
2897         val |= (protocol_id << L3_CLS_PID_SHIFT);
2898         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2899         val |= (tos_val << L3_CLS_TOS_SHIFT);
2900         nw64(reg, val);
2901
2902         return 0;
2903 }
2904 #endif
2905
2906 static int tcam_early_init(struct niu *np)
2907 {
2908         unsigned long i;
2909         int err;
2910
2911         tcam_enable(np, 0);
2912         tcam_set_lat_and_ratio(np,
2913                                DEFAULT_TCAM_LATENCY,
2914                                DEFAULT_TCAM_ACCESS_RATIO);
2915         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
2916                 err = tcam_user_eth_class_enable(np, i, 0);
2917                 if (err)
2918                         return err;
2919         }
2920         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
2921                 err = tcam_user_ip_class_enable(np, i, 0);
2922                 if (err)
2923                         return err;
2924         }
2925
2926         return 0;
2927 }
2928
2929 static int tcam_flush_all(struct niu *np)
2930 {
2931         unsigned long i;
2932
2933         for (i = 0; i < np->parent->tcam_num_entries; i++) {
2934                 int err = tcam_flush(np, i);
2935                 if (err)
2936                         return err;
2937         }
2938         return 0;
2939 }
2940
2941 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
2942 {
2943         return ((u64)index | (num_entries == 1 ?
2944                               HASH_TBL_ADDR_AUTOINC : 0));
2945 }
2946
2947 #if 0
2948 static int hash_read(struct niu *np, unsigned long partition,
2949                      unsigned long index, unsigned long num_entries,
2950                      u64 *data)
2951 {
2952         u64 val = hash_addr_regval(index, num_entries);
2953         unsigned long i;
2954
2955         if (partition >= FCRAM_NUM_PARTITIONS ||
2956             index + num_entries > FCRAM_SIZE)
2957                 return -EINVAL;
2958
2959         nw64(HASH_TBL_ADDR(partition), val);
2960         for (i = 0; i < num_entries; i++)
2961                 data[i] = nr64(HASH_TBL_DATA(partition));
2962
2963         return 0;
2964 }
2965 #endif
2966
2967 static int hash_write(struct niu *np, unsigned long partition,
2968                       unsigned long index, unsigned long num_entries,
2969                       u64 *data)
2970 {
2971         u64 val = hash_addr_regval(index, num_entries);
2972         unsigned long i;
2973
2974         if (partition >= FCRAM_NUM_PARTITIONS ||
2975             index + (num_entries * 8) > FCRAM_SIZE)
2976                 return -EINVAL;
2977
2978         nw64(HASH_TBL_ADDR(partition), val);
2979         for (i = 0; i < num_entries; i++)
2980                 nw64(HASH_TBL_DATA(partition), data[i]);
2981
2982         return 0;
2983 }
2984
2985 static void fflp_reset(struct niu *np)
2986 {
2987         u64 val;
2988
2989         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
2990         udelay(10);
2991         nw64(FFLP_CFG_1, 0);
2992
2993         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
2994         nw64(FFLP_CFG_1, val);
2995 }
2996
2997 static void fflp_set_timings(struct niu *np)
2998 {
2999         u64 val = nr64(FFLP_CFG_1);
3000
3001         val &= ~FFLP_CFG_1_FFLPINITDONE;
3002         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3003         nw64(FFLP_CFG_1, val);
3004
3005         val = nr64(FFLP_CFG_1);
3006         val |= FFLP_CFG_1_FFLPINITDONE;
3007         nw64(FFLP_CFG_1, val);
3008
3009         val = nr64(FCRAM_REF_TMR);
3010         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3011         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3012         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3013         nw64(FCRAM_REF_TMR, val);
3014 }
3015
3016 static int fflp_set_partition(struct niu *np, u64 partition,
3017                               u64 mask, u64 base, int enable)
3018 {
3019         unsigned long reg;
3020         u64 val;
3021
3022         if (partition >= FCRAM_NUM_PARTITIONS ||
3023             (mask & ~(u64)0x1f) != 0 ||
3024             (base & ~(u64)0x1f) != 0)
3025                 return -EINVAL;
3026
3027         reg = FLW_PRT_SEL(partition);
3028
3029         val = nr64(reg);
3030         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3031         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3032         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3033         if (enable)
3034                 val |= FLW_PRT_SEL_EXT;
3035         nw64(reg, val);
3036
3037         return 0;
3038 }
3039
3040 static int fflp_disable_all_partitions(struct niu *np)
3041 {
3042         unsigned long i;
3043
3044         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3045                 int err = fflp_set_partition(np, 0, 0, 0, 0);
3046                 if (err)
3047                         return err;
3048         }
3049         return 0;
3050 }
3051
3052 static void fflp_llcsnap_enable(struct niu *np, int on)
3053 {
3054         u64 val = nr64(FFLP_CFG_1);
3055
3056         if (on)
3057                 val |= FFLP_CFG_1_LLCSNAP;
3058         else
3059                 val &= ~FFLP_CFG_1_LLCSNAP;
3060         nw64(FFLP_CFG_1, val);
3061 }
3062
3063 static void fflp_errors_enable(struct niu *np, int on)
3064 {
3065         u64 val = nr64(FFLP_CFG_1);
3066
3067         if (on)
3068                 val &= ~FFLP_CFG_1_ERRORDIS;
3069         else
3070                 val |= FFLP_CFG_1_ERRORDIS;
3071         nw64(FFLP_CFG_1, val);
3072 }
3073
3074 static int fflp_hash_clear(struct niu *np)
3075 {
3076         struct fcram_hash_ipv4 ent;
3077         unsigned long i;
3078
3079         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
3080         memset(&ent, 0, sizeof(ent));
3081         ent.header = HASH_HEADER_EXT;
3082
3083         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3084                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3085                 if (err)
3086                         return err;
3087         }
3088         return 0;
3089 }
3090
3091 static int fflp_early_init(struct niu *np)
3092 {
3093         struct niu_parent *parent;
3094         unsigned long flags;
3095         int err;
3096
3097         niu_lock_parent(np, flags);
3098
3099         parent = np->parent;
3100         err = 0;
3101         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3102                 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
3103                        np->port);
3104                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3105                         fflp_reset(np);
3106                         fflp_set_timings(np);
3107                         err = fflp_disable_all_partitions(np);
3108                         if (err) {
3109                                 niudbg(PROBE, "fflp_disable_all_partitions "
3110                                        "failed, err=%d\n", err);
3111                                 goto out;
3112                         }
3113                 }
3114
3115                 err = tcam_early_init(np);
3116                 if (err) {
3117                         niudbg(PROBE, "tcam_early_init failed, err=%d\n",
3118                                err);
3119                         goto out;
3120                 }
3121                 fflp_llcsnap_enable(np, 1);
3122                 fflp_errors_enable(np, 0);
3123                 nw64(H1POLY, 0);
3124                 nw64(H2POLY, 0);
3125
3126                 err = tcam_flush_all(np);
3127                 if (err) {
3128                         niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
3129                                err);
3130                         goto out;
3131                 }
3132                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3133                         err = fflp_hash_clear(np);
3134                         if (err) {
3135                                 niudbg(PROBE, "fflp_hash_clear failed, "
3136                                        "err=%d\n", err);
3137                                 goto out;
3138                         }
3139                 }
3140
3141                 vlan_tbl_clear(np);
3142
3143                 niudbg(PROBE, "fflp_early_init: Success\n");
3144                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3145         }
3146 out:
3147         niu_unlock_parent(np, flags);
3148         return err;
3149 }
3150
3151 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3152 {
3153         if (class_code < CLASS_CODE_USER_PROG1 ||
3154             class_code > CLASS_CODE_SCTP_IPV6)
3155                 return -EINVAL;
3156
3157         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3158         return 0;
3159 }
3160
3161 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3162 {
3163         if (class_code < CLASS_CODE_USER_PROG1 ||
3164             class_code > CLASS_CODE_SCTP_IPV6)
3165                 return -EINVAL;
3166
3167         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3168         return 0;
3169 }
3170
3171 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3172                               u32 offset, u32 size)
3173 {
3174         int i = skb_shinfo(skb)->nr_frags;
3175         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3176
3177         frag->page = page;
3178         frag->page_offset = offset;
3179         frag->size = size;
3180
3181         skb->len += size;
3182         skb->data_len += size;
3183         skb->truesize += size;
3184
3185         skb_shinfo(skb)->nr_frags = i + 1;
3186 }
3187
3188 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3189 {
3190         a >>= PAGE_SHIFT;
3191         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3192
3193         return (a & (MAX_RBR_RING_SIZE - 1));
3194 }
3195
3196 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3197                                     struct page ***link)
3198 {
3199         unsigned int h = niu_hash_rxaddr(rp, addr);
3200         struct page *p, **pp;
3201
3202         addr &= PAGE_MASK;
3203         pp = &rp->rxhash[h];
3204         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3205                 if (p->index == addr) {
3206                         *link = pp;
3207                         break;
3208                 }
3209         }
3210
3211         return p;
3212 }
3213
3214 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3215 {
3216         unsigned int h = niu_hash_rxaddr(rp, base);
3217
3218         page->index = base;
3219         page->mapping = (struct address_space *) rp->rxhash[h];
3220         rp->rxhash[h] = page;
3221 }
3222
3223 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3224                             gfp_t mask, int start_index)
3225 {
3226         struct page *page;
3227         u64 addr;
3228         int i;
3229
3230         page = alloc_page(mask);
3231         if (!page)
3232                 return -ENOMEM;
3233
3234         addr = np->ops->map_page(np->device, page, 0,
3235                                  PAGE_SIZE, DMA_FROM_DEVICE);
3236
3237         niu_hash_page(rp, page, addr);
3238         if (rp->rbr_blocks_per_page > 1)
3239                 atomic_add(rp->rbr_blocks_per_page - 1,
3240                            &compound_head(page)->_count);
3241
3242         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3243                 __le32 *rbr = &rp->rbr[start_index + i];
3244
3245                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3246                 addr += rp->rbr_block_size;
3247         }
3248
3249         return 0;
3250 }
3251
3252 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3253 {
3254         int index = rp->rbr_index;
3255
3256         rp->rbr_pending++;
3257         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3258                 int err = niu_rbr_add_page(np, rp, mask, index);
3259
3260                 if (unlikely(err)) {
3261                         rp->rbr_pending--;
3262                         return;
3263                 }
3264
3265                 rp->rbr_index += rp->rbr_blocks_per_page;
3266                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3267                 if (rp->rbr_index == rp->rbr_table_size)
3268                         rp->rbr_index = 0;
3269
3270                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3271                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3272                         rp->rbr_pending = 0;
3273                 }
3274         }
3275 }
3276
3277 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3278 {
3279         unsigned int index = rp->rcr_index;
3280         int num_rcr = 0;
3281
3282         rp->rx_dropped++;
3283         while (1) {
3284                 struct page *page, **link;
3285                 u64 addr, val;
3286                 u32 rcr_size;
3287
3288                 num_rcr++;
3289
3290                 val = le64_to_cpup(&rp->rcr[index]);
3291                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3292                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3293                 page = niu_find_rxpage(rp, addr, &link);
3294
3295                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3296                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3297                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3298                         *link = (struct page *) page->mapping;
3299                         np->ops->unmap_page(np->device, page->index,
3300                                             PAGE_SIZE, DMA_FROM_DEVICE);
3301                         page->index = 0;
3302                         page->mapping = NULL;
3303                         __free_page(page);
3304                         rp->rbr_refill_pending++;
3305                 }
3306
3307                 index = NEXT_RCR(rp, index);
3308                 if (!(val & RCR_ENTRY_MULTI))
3309                         break;
3310
3311         }
3312         rp->rcr_index = index;
3313
3314         return num_rcr;
3315 }
3316
3317 static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
3318 {
3319         unsigned int index = rp->rcr_index;
3320         struct sk_buff *skb;
3321         int len, num_rcr;
3322
3323         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3324         if (unlikely(!skb))
3325                 return niu_rx_pkt_ignore(np, rp);
3326
3327         num_rcr = 0;
3328         while (1) {
3329                 struct page *page, **link;
3330                 u32 rcr_size, append_size;
3331                 u64 addr, val, off;
3332
3333                 num_rcr++;
3334
3335                 val = le64_to_cpup(&rp->rcr[index]);
3336
3337                 len = (val & RCR_ENTRY_L2_LEN) >>
3338                         RCR_ENTRY_L2_LEN_SHIFT;
3339                 len -= ETH_FCS_LEN;
3340
3341                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3342                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3343                 page = niu_find_rxpage(rp, addr, &link);
3344
3345                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3346                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3347
3348                 off = addr & ~PAGE_MASK;
3349                 append_size = rcr_size;
3350                 if (num_rcr == 1) {
3351                         int ptype;
3352
3353                         off += 2;
3354                         append_size -= 2;
3355
3356                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3357                         if ((ptype == RCR_PKT_TYPE_TCP ||
3358                              ptype == RCR_PKT_TYPE_UDP) &&
3359                             !(val & (RCR_ENTRY_NOPORT |
3360                                      RCR_ENTRY_ERROR)))
3361                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3362                         else
3363                                 skb->ip_summed = CHECKSUM_NONE;
3364                 }
3365                 if (!(val & RCR_ENTRY_MULTI))
3366                         append_size = len - skb->len;
3367
3368                 niu_rx_skb_append(skb, page, off, append_size);
3369                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3370                         *link = (struct page *) page->mapping;
3371                         np->ops->unmap_page(np->device, page->index,
3372                                             PAGE_SIZE, DMA_FROM_DEVICE);
3373                         page->index = 0;
3374                         page->mapping = NULL;
3375                         rp->rbr_refill_pending++;
3376                 } else
3377                         get_page(page);
3378
3379                 index = NEXT_RCR(rp, index);
3380                 if (!(val & RCR_ENTRY_MULTI))
3381                         break;
3382
3383         }
3384         rp->rcr_index = index;
3385
3386         skb_reserve(skb, NET_IP_ALIGN);
3387         __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
3388
3389         rp->rx_packets++;
3390         rp->rx_bytes += skb->len;
3391
3392         skb->protocol = eth_type_trans(skb, np->dev);
3393         netif_receive_skb(skb);
3394
3395         return num_rcr;
3396 }
3397
3398 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3399 {
3400         int blocks_per_page = rp->rbr_blocks_per_page;
3401         int err, index = rp->rbr_index;
3402
3403         err = 0;
3404         while (index < (rp->rbr_table_size - blocks_per_page)) {
3405                 err = niu_rbr_add_page(np, rp, mask, index);
3406                 if (err)
3407                         break;
3408
3409                 index += blocks_per_page;
3410         }
3411
3412         rp->rbr_index = index;
3413         return err;
3414 }
3415
3416 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3417 {
3418         int i;
3419
3420         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3421                 struct page *page;
3422
3423                 page = rp->rxhash[i];
3424                 while (page) {
3425                         struct page *next = (struct page *) page->mapping;
3426                         u64 base = page->index;
3427
3428                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
3429                                             DMA_FROM_DEVICE);
3430                         page->index = 0;
3431                         page->mapping = NULL;
3432
3433                         __free_page(page);
3434
3435                         page = next;
3436                 }
3437         }
3438
3439         for (i = 0; i < rp->rbr_table_size; i++)
3440                 rp->rbr[i] = cpu_to_le32(0);
3441         rp->rbr_index = 0;
3442 }
3443
3444 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3445 {
3446         struct tx_buff_info *tb = &rp->tx_buffs[idx];
3447         struct sk_buff *skb = tb->skb;
3448         struct tx_pkt_hdr *tp;
3449         u64 tx_flags;
3450         int i, len;
3451
3452         tp = (struct tx_pkt_hdr *) skb->data;
3453         tx_flags = le64_to_cpup(&tp->flags);
3454
3455         rp->tx_packets++;
3456         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3457                          ((tx_flags & TXHDR_PAD) / 2));
3458
3459         len = skb_headlen(skb);
3460         np->ops->unmap_single(np->device, tb->mapping,
3461                               len, DMA_TO_DEVICE);
3462
3463         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3464                 rp->mark_pending--;
3465
3466         tb->skb = NULL;
3467         do {
3468                 idx = NEXT_TX(rp, idx);
3469                 len -= MAX_TX_DESC_LEN;
3470         } while (len > 0);
3471
3472         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3473                 tb = &rp->tx_buffs[idx];
3474                 BUG_ON(tb->skb != NULL);
3475                 np->ops->unmap_page(np->device, tb->mapping,
3476                                     skb_shinfo(skb)->frags[i].size,
3477                                     DMA_TO_DEVICE);
3478                 idx = NEXT_TX(rp, idx);
3479         }
3480
3481         dev_kfree_skb(skb);
3482
3483         return idx;
3484 }
3485
3486 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3487
3488 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3489 {
3490         struct netdev_queue *txq;
3491         u16 pkt_cnt, tmp;
3492         int cons, index;
3493         u64 cs;
3494
3495         index = (rp - np->tx_rings);
3496         txq = netdev_get_tx_queue(np->dev, index);
3497
3498         cs = rp->tx_cs;
3499         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3500                 goto out;
3501
3502         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3503         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3504                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3505
3506         rp->last_pkt_cnt = tmp;
3507
3508         cons = rp->cons;
3509
3510         niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3511                np->dev->name, pkt_cnt, cons);
3512
3513         while (pkt_cnt--)
3514                 cons = release_tx_packet(np, rp, cons);
3515
3516         rp->cons = cons;
3517         smp_mb();
3518
3519 out:
3520         if (unlikely(netif_tx_queue_stopped(txq) &&
3521                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3522                 __netif_tx_lock(txq, smp_processor_id());
3523                 if (netif_tx_queue_stopped(txq) &&
3524                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3525                         netif_tx_wake_queue(txq);
3526                 __netif_tx_unlock(txq);
3527         }
3528 }
3529
3530 static inline void niu_sync_rx_discard_stats(struct niu *np,
3531                                              struct rx_ring_info *rp,
3532                                              const int limit)
3533 {
3534         /* This elaborate scheme is needed for reading the RX discard
3535          * counters, as they are only 16-bit and can overflow quickly,
3536          * and because the overflow indication bit is not usable as
3537          * the counter value does not wrap, but remains at max value
3538          * 0xFFFF.
3539          *
3540          * In theory and in practice counters can be lost in between
3541          * reading nr64() and clearing the counter nw64().  For this
3542          * reason, the number of counter clearings nw64() is
3543          * limited/reduced though the limit parameter.
3544          */
3545         int rx_channel = rp->rx_channel;
3546         u32 misc, wred;
3547
3548         /* RXMISC (Receive Miscellaneous Discard Count), covers the
3549          * following discard events: IPP (Input Port Process),
3550          * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3551          * Block Ring) prefetch buffer is empty.
3552          */
3553         misc = nr64(RXMISC(rx_channel));
3554         if (unlikely((misc & RXMISC_COUNT) > limit)) {
3555                 nw64(RXMISC(rx_channel), 0);
3556                 rp->rx_errors += misc & RXMISC_COUNT;
3557
3558                 if (unlikely(misc & RXMISC_OFLOW))
3559                         dev_err(np->device, "rx-%d: Counter overflow "
3560                                 "RXMISC discard\n", rx_channel);
3561         }
3562
3563         /* WRED (Weighted Random Early Discard) by hardware */
3564         wred = nr64(RED_DIS_CNT(rx_channel));
3565         if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3566                 nw64(RED_DIS_CNT(rx_channel), 0);
3567                 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3568
3569                 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3570                         dev_err(np->device, "rx-%d: Counter overflow "
3571                                 "WRED discard\n", rx_channel);
3572         }
3573 }
3574
3575 static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
3576 {
3577         int qlen, rcr_done = 0, work_done = 0;
3578         struct rxdma_mailbox *mbox = rp->mbox;
3579         u64 stat;
3580
3581 #if 1
3582         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3583         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3584 #else
3585         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3586         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3587 #endif
3588         mbox->rx_dma_ctl_stat = 0;
3589         mbox->rcrstat_a = 0;
3590
3591         niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3592                np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3593
3594         rcr_done = work_done = 0;
3595         qlen = min(qlen, budget);
3596         while (work_done < qlen) {
3597                 rcr_done += niu_process_rx_pkt(np, rp);
3598                 work_done++;
3599         }
3600
3601         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3602                 unsigned int i;
3603
3604                 for (i = 0; i < rp->rbr_refill_pending; i++)
3605                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3606                 rp->rbr_refill_pending = 0;
3607         }
3608
3609         stat = (RX_DMA_CTL_STAT_MEX |
3610                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3611                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3612
3613         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3614
3615         niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3616
3617         return work_done;
3618 }
3619
3620 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3621 {
3622         u64 v0 = lp->v0;
3623         u32 tx_vec = (v0 >> 32);
3624         u32 rx_vec = (v0 & 0xffffffff);
3625         int i, work_done = 0;
3626
3627         niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3628                np->dev->name, (unsigned long long) v0);
3629
3630         for (i = 0; i < np->num_tx_rings; i++) {
3631                 struct tx_ring_info *rp = &np->tx_rings[i];
3632                 if (tx_vec & (1 << rp->tx_channel))
3633                         niu_tx_work(np, rp);
3634                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3635         }
3636
3637         for (i = 0; i < np->num_rx_rings; i++) {
3638                 struct rx_ring_info *rp = &np->rx_rings[i];
3639
3640                 if (rx_vec & (1 << rp->rx_channel)) {
3641                         int this_work_done;
3642
3643                         this_work_done = niu_rx_work(np, rp,
3644                                                      budget);
3645
3646                         budget -= this_work_done;
3647                         work_done += this_work_done;
3648                 }
3649                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3650         }
3651
3652         return work_done;
3653 }
3654
3655 static int niu_poll(struct napi_struct *napi, int budget)
3656 {
3657         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3658         struct niu *np = lp->np;
3659         int work_done;
3660
3661         work_done = niu_poll_core(np, lp, budget);
3662
3663         if (work_done < budget) {
3664                 netif_rx_complete(np->dev, napi);
3665                 niu_ldg_rearm(np, lp, 1);
3666         }
3667         return work_done;
3668 }
3669
3670 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3671                                   u64 stat)
3672 {
3673         dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3674                 np->dev->name, rp->rx_channel);
3675
3676         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3677                 printk("RBR_TMOUT ");
3678         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3679                 printk("RSP_CNT ");
3680         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3681                 printk("BYTE_EN_BUS ");
3682         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3683                 printk("RSP_DAT ");
3684         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3685                 printk("RCR_ACK ");
3686         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3687                 printk("RCR_SHA_PAR ");
3688         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3689                 printk("RBR_PRE_PAR ");
3690         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3691                 printk("CONFIG ");
3692         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3693                 printk("RCRINCON ");
3694         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3695                 printk("RCRFULL ");
3696         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3697                 printk("RBRFULL ");
3698         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3699                 printk("RBRLOGPAGE ");
3700         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3701                 printk("CFIGLOGPAGE ");
3702         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3703                 printk("DC_FIDO ");
3704
3705         printk(")\n");
3706 }
3707
3708 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3709 {
3710         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3711         int err = 0;
3712
3713
3714         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3715                     RX_DMA_CTL_STAT_PORT_FATAL))
3716                 err = -EINVAL;
3717
3718         if (err) {
3719                 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3720                         np->dev->name, rp->rx_channel,
3721                         (unsigned long long) stat);
3722
3723                 niu_log_rxchan_errors(np, rp, stat);
3724         }
3725
3726         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3727              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3728
3729         return err;
3730 }
3731
3732 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3733                                   u64 cs)
3734 {
3735         dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3736                 np->dev->name, rp->tx_channel);
3737
3738         if (cs & TX_CS_MBOX_ERR)
3739                 printk("MBOX ");
3740         if (cs & TX_CS_PKT_SIZE_ERR)
3741                 printk("PKT_SIZE ");
3742         if (cs & TX_CS_TX_RING_OFLOW)
3743                 printk("TX_RING_OFLOW ");
3744         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3745                 printk("PREF_BUF_PAR ");
3746         if (cs & TX_CS_NACK_PREF)
3747                 printk("NACK_PREF ");
3748         if (cs & TX_CS_NACK_PKT_RD)
3749                 printk("NACK_PKT_RD ");
3750         if (cs & TX_CS_CONF_PART_ERR)
3751                 printk("CONF_PART ");
3752         if (cs & TX_CS_PKT_PRT_ERR)
3753                 printk("PKT_PTR ");
3754
3755         printk(")\n");
3756 }
3757
3758 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3759 {
3760         u64 cs, logh, logl;
3761
3762         cs = nr64(TX_CS(rp->tx_channel));
3763         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3764         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3765
3766         dev_err(np->device, PFX "%s: TX channel %u error, "
3767                 "cs[%llx] logh[%llx] logl[%llx]\n",
3768                 np->dev->name, rp->tx_channel,
3769                 (unsigned long long) cs,
3770                 (unsigned long long) logh,
3771                 (unsigned long long) logl);
3772
3773         niu_log_txchan_errors(np, rp, cs);
3774
3775         return -ENODEV;
3776 }
3777
3778 static int niu_mif_interrupt(struct niu *np)
3779 {
3780         u64 mif_status = nr64(MIF_STATUS);
3781         int phy_mdint = 0;
3782
3783         if (np->flags & NIU_FLAGS_XMAC) {
3784                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3785
3786                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3787                         phy_mdint = 1;
3788         }
3789
3790         dev_err(np->device, PFX "%s: MIF interrupt, "
3791                 "stat[%llx] phy_mdint(%d)\n",
3792                 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3793
3794         return -ENODEV;
3795 }
3796
3797 static void niu_xmac_interrupt(struct niu *np)
3798 {
3799         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3800         u64 val;
3801
3802         val = nr64_mac(XTXMAC_STATUS);
3803         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3804                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3805         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3806                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3807         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3808                 mp->tx_fifo_errors++;
3809         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3810                 mp->tx_overflow_errors++;
3811         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3812                 mp->tx_max_pkt_size_errors++;
3813         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3814                 mp->tx_underflow_errors++;
3815
3816         val = nr64_mac(XRXMAC_STATUS);
3817         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3818                 mp->rx_local_faults++;
3819         if (val & XRXMAC_STATUS_RFLT_DET)
3820                 mp->rx_remote_faults++;
3821         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3822                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3823         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3824                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3825         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3826                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3827         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3828                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3829         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3830                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3831         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3832                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3833         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3834                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3835         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3836                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3837         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3838                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3839         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3840                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3841         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3842                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3843         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3844                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3845         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3846                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3847         if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
3848                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3849         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3850                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3851         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3852                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3853         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3854                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3855         if (val & XRXMAC_STATUS_RXUFLOW)
3856                 mp->rx_underflows++;
3857         if (val & XRXMAC_STATUS_RXOFLOW)
3858                 mp->rx_overflows++;
3859
3860         val = nr64_mac(XMAC_FC_STAT);
3861         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3862                 mp->pause_off_state++;
3863         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3864                 mp->pause_on_state++;
3865         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3866                 mp->pause_received++;
3867 }
3868
3869 static void niu_bmac_interrupt(struct niu *np)
3870 {
3871         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3872         u64 val;
3873
3874         val = nr64_mac(BTXMAC_STATUS);
3875         if (val & BTXMAC_STATUS_UNDERRUN)
3876                 mp->tx_underflow_errors++;
3877         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3878                 mp->tx_max_pkt_size_errors++;
3879         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3880                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3881         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
3882                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
3883
3884         val = nr64_mac(BRXMAC_STATUS);
3885         if (val & BRXMAC_STATUS_OVERFLOW)
3886                 mp->rx_overflows++;
3887         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
3888                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
3889         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
3890                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3891         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
3892                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3893         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
3894                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
3895
3896         val = nr64_mac(BMAC_CTRL_STATUS);
3897         if (val & BMAC_CTRL_STATUS_NOPAUSE)
3898                 mp->pause_off_state++;
3899         if (val & BMAC_CTRL_STATUS_PAUSE)
3900                 mp->pause_on_state++;
3901         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
3902                 mp->pause_received++;
3903 }
3904
3905 static int niu_mac_interrupt(struct niu *np)
3906 {
3907         if (np->flags & NIU_FLAGS_XMAC)
3908                 niu_xmac_interrupt(np);
3909         else
3910                 niu_bmac_interrupt(np);
3911
3912         return 0;
3913 }
3914
3915 static void niu_log_device_error(struct niu *np, u64 stat)
3916 {
3917         dev_err(np->device, PFX "%s: Core device errors ( ",
3918                 np->dev->name);
3919
3920         if (stat & SYS_ERR_MASK_META2)
3921                 printk("META2 ");
3922         if (stat & SYS_ERR_MASK_META1)
3923                 printk("META1 ");
3924         if (stat & SYS_ERR_MASK_PEU)
3925                 printk("PEU ");
3926         if (stat & SYS_ERR_MASK_TXC)
3927                 printk("TXC ");
3928         if (stat & SYS_ERR_MASK_RDMC)
3929                 printk("RDMC ");
3930         if (stat & SYS_ERR_MASK_TDMC)
3931                 printk("TDMC ");
3932         if (stat & SYS_ERR_MASK_ZCP)
3933                 printk("ZCP ");
3934         if (stat & SYS_ERR_MASK_FFLP)
3935                 printk("FFLP ");
3936         if (stat & SYS_ERR_MASK_IPP)
3937                 printk("IPP ");
3938         if (stat & SYS_ERR_MASK_MAC)
3939                 printk("MAC ");
3940         if (stat & SYS_ERR_MASK_SMX)
3941                 printk("SMX ");
3942
3943         printk(")\n");
3944 }
3945
3946 static int niu_device_error(struct niu *np)
3947 {
3948         u64 stat = nr64(SYS_ERR_STAT);
3949
3950         dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
3951                 np->dev->name, (unsigned long long) stat);
3952
3953         niu_log_device_error(np, stat);
3954
3955         return -ENODEV;
3956 }
3957
3958 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
3959                               u64 v0, u64 v1, u64 v2)
3960 {
3961
3962         int i, err = 0;
3963
3964         lp->v0 = v0;
3965         lp->v1 = v1;
3966         lp->v2 = v2;
3967
3968         if (v1 & 0x00000000ffffffffULL) {
3969                 u32 rx_vec = (v1 & 0xffffffff);
3970
3971                 for (i = 0; i < np->num_rx_rings; i++) {
3972                         struct rx_ring_info *rp = &np->rx_rings[i];
3973
3974                         if (rx_vec & (1 << rp->rx_channel)) {
3975                                 int r = niu_rx_error(np, rp);
3976                                 if (r) {
3977                                         err = r;
3978                                 } else {
3979                                         if (!v0)
3980                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3981                                                      RX_DMA_CTL_STAT_MEX);
3982                                 }
3983                         }
3984                 }
3985         }
3986         if (v1 & 0x7fffffff00000000ULL) {
3987                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
3988
3989                 for (i = 0; i < np->num_tx_rings; i++) {
3990                         struct tx_ring_info *rp = &np->tx_rings[i];
3991
3992                         if (tx_vec & (1 << rp->tx_channel)) {
3993                                 int r = niu_tx_error(np, rp);
3994                                 if (r)
3995                                         err = r;
3996                         }
3997                 }
3998         }
3999         if ((v0 | v1) & 0x8000000000000000ULL) {
4000                 int r = niu_mif_interrupt(np);
4001                 if (r)
4002                         err = r;
4003         }
4004         if (v2) {
4005                 if (v2 & 0x01ef) {
4006                         int r = niu_mac_interrupt(np);
4007                         if (r)
4008                                 err = r;
4009                 }
4010                 if (v2 & 0x0210) {
4011                         int r = niu_device_error(np);
4012                         if (r)
4013                                 err = r;
4014                 }
4015         }
4016
4017         if (err)
4018                 niu_enable_interrupts(np, 0);
4019
4020         return err;
4021 }
4022
4023 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4024                             int ldn)
4025 {
4026         struct rxdma_mailbox *mbox = rp->mbox;
4027         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4028
4029         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4030                       RX_DMA_CTL_STAT_RCRTO);
4031         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4032
4033         niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
4034                np->dev->name, (unsigned long long) stat);
4035 }
4036
4037 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4038                             int ldn)
4039 {
4040         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4041
4042         niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
4043                np->dev->name, (unsigned long long) rp->tx_cs);
4044 }
4045
4046 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4047 {
4048         struct niu_parent *parent = np->parent;
4049         u32 rx_vec, tx_vec;
4050         int i;
4051
4052         tx_vec = (v0 >> 32);
4053         rx_vec = (v0 & 0xffffffff);
4054
4055         for (i = 0; i < np->num_rx_rings; i++) {
4056                 struct rx_ring_info *rp = &np->rx_rings[i];
4057                 int ldn = LDN_RXDMA(rp->rx_channel);
4058
4059                 if (parent->ldg_map[ldn] != ldg)
4060                         continue;
4061
4062                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4063                 if (rx_vec & (1 << rp->rx_channel))
4064                         niu_rxchan_intr(np, rp, ldn);
4065         }
4066
4067         for (i = 0; i < np->num_tx_rings; i++) {
4068                 struct tx_ring_info *rp = &np->tx_rings[i];
4069                 int ldn = LDN_TXDMA(rp->tx_channel);
4070
4071                 if (parent->ldg_map[ldn] != ldg)
4072                         continue;
4073
4074                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4075                 if (tx_vec & (1 << rp->tx_channel))
4076                         niu_txchan_intr(np, rp, ldn);
4077         }
4078 }
4079
4080 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4081                               u64 v0, u64 v1, u64 v2)
4082 {
4083         if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) {
4084                 lp->v0 = v0;
4085                 lp->v1 = v1;
4086                 lp->v2 = v2;
4087                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4088                 __netif_rx_schedule(np->dev, &lp->napi);
4089         }
4090 }
4091
4092 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4093 {
4094         struct niu_ldg *lp = dev_id;
4095         struct niu *np = lp->np;
4096         int ldg = lp->ldg_num;
4097         unsigned long flags;
4098         u64 v0, v1, v2;
4099
4100         if (netif_msg_intr(np))
4101                 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
4102                        lp, ldg);
4103
4104         spin_lock_irqsave(&np->lock, flags);
4105
4106         v0 = nr64(LDSV0(ldg));
4107         v1 = nr64(LDSV1(ldg));
4108         v2 = nr64(LDSV2(ldg));
4109
4110         if (netif_msg_intr(np))
4111                 printk("v0[%llx] v1[%llx] v2[%llx]\n",
4112                        (unsigned long long) v0,
4113                        (unsigned long long) v1,
4114                        (unsigned long long) v2);
4115
4116         if (unlikely(!v0 && !v1 && !v2)) {
4117                 spin_unlock_irqrestore(&np->lock, flags);
4118                 return IRQ_NONE;
4119         }
4120
4121         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4122                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4123                 if (err)
4124                         goto out;
4125         }
4126         if (likely(v0 & ~((u64)1 << LDN_MIF)))
4127                 niu_schedule_napi(np, lp, v0, v1, v2);
4128         else
4129                 niu_ldg_rearm(np, lp, 1);
4130 out:
4131         spin_unlock_irqrestore(&np->lock, flags);
4132
4133         return IRQ_HANDLED;
4134 }
4135
4136 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4137 {
4138         if (rp->mbox) {
4139                 np->ops->free_coherent(np->device,
4140                                        sizeof(struct rxdma_mailbox),
4141                                        rp->mbox, rp->mbox_dma);
4142                 rp->mbox = NULL;
4143         }
4144         if (rp->rcr) {
4145                 np->ops->free_coherent(np->device,
4146                                        MAX_RCR_RING_SIZE * sizeof(__le64),
4147                                        rp->rcr, rp->rcr_dma);
4148                 rp->rcr = NULL;
4149                 rp->rcr_table_size = 0;
4150                 rp->rcr_index = 0;
4151         }
4152         if (rp->rbr) {
4153                 niu_rbr_free(np, rp);
4154
4155                 np->ops->free_coherent(np->device,
4156                                        MAX_RBR_RING_SIZE * sizeof(__le32),
4157                                        rp->rbr, rp->rbr_dma);
4158                 rp->rbr = NULL;
4159                 rp->rbr_table_size = 0;
4160                 rp->rbr_index = 0;
4161         }
4162         kfree(rp->rxhash);
4163         rp->rxhash = NULL;
4164 }
4165
4166 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4167 {
4168         if (rp->mbox) {
4169                 np->ops->free_coherent(np->device,
4170                                        sizeof(struct txdma_mailbox),
4171                                        rp->mbox, rp->mbox_dma);
4172                 rp->mbox = NULL;
4173         }
4174         if (rp->descr) {
4175                 int i;
4176
4177                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4178                         if (rp->tx_buffs[i].skb)
4179                                 (void) release_tx_packet(np, rp, i);
4180                 }
4181
4182                 np->ops->free_coherent(np->device,
4183                                        MAX_TX_RING_SIZE * sizeof(__le64),
4184                                        rp->descr, rp->descr_dma);
4185                 rp->descr = NULL;
4186                 rp->pending = 0;
4187                 rp->prod = 0;
4188                 rp->cons = 0;
4189                 rp->wrap_bit = 0;
4190         }
4191 }
4192
4193 static void niu_free_channels(struct niu *np)
4194 {
4195         int i;
4196
4197         if (np->rx_rings) {
4198                 for (i = 0; i < np->num_rx_rings; i++) {
4199                         struct rx_ring_info *rp = &np->rx_rings[i];
4200
4201                         niu_free_rx_ring_info(np, rp);
4202                 }
4203                 kfree(np->rx_rings);
4204                 np->rx_rings = NULL;
4205                 np->num_rx_rings = 0;
4206         }
4207
4208         if (np->tx_rings) {
4209                 for (i = 0; i < np->num_tx_rings; i++) {
4210                         struct tx_ring_info *rp = &np->tx_rings[i];
4211
4212                         niu_free_tx_ring_info(np, rp);
4213                 }
4214                 kfree(np->tx_rings);
4215                 np->tx_rings = NULL;
4216                 np->num_tx_rings = 0;
4217         }
4218 }
4219
4220 static int niu_alloc_rx_ring_info(struct niu *np,
4221                                   struct rx_ring_info *rp)
4222 {
4223         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4224
4225         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4226                              GFP_KERNEL);
4227         if (!rp->rxhash)
4228                 return -ENOMEM;
4229
4230         rp->mbox = np->ops->alloc_coherent(np->device,
4231                                            sizeof(struct rxdma_mailbox),
4232                                            &rp->mbox_dma, GFP_KERNEL);
4233         if (!rp->mbox)
4234                 return -ENOMEM;
4235         if ((unsigned long)rp->mbox & (64UL - 1)) {
4236                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4237                         "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
4238                 return -EINVAL;
4239         }
4240
4241         rp->rcr = np->ops->alloc_coherent(np->device,
4242                                           MAX_RCR_RING_SIZE * sizeof(__le64),
4243                                           &rp->rcr_dma, GFP_KERNEL);
4244         if (!rp->rcr)
4245                 return -ENOMEM;
4246         if ((unsigned long)rp->rcr & (64UL - 1)) {
4247                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4248                         "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
4249                 return -EINVAL;
4250         }
4251         rp->rcr_table_size = MAX_RCR_RING_SIZE;
4252         rp->rcr_index = 0;
4253
4254         rp->rbr = np->ops->alloc_coherent(np->device,
4255                                           MAX_RBR_RING_SIZE * sizeof(__le32),
4256                                           &rp->rbr_dma, GFP_KERNEL);
4257         if (!rp->rbr)
4258                 return -ENOMEM;
4259         if ((unsigned long)rp->rbr & (64UL - 1)) {
4260                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4261                         "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
4262                 return -EINVAL;
4263         }
4264         rp->rbr_table_size = MAX_RBR_RING_SIZE;
4265         rp->rbr_index = 0;
4266         rp->rbr_pending = 0;
4267
4268         return 0;
4269 }
4270
4271 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4272 {
4273         int mtu = np->dev->mtu;
4274
4275         /* These values are recommended by the HW designers for fair
4276          * utilization of DRR amongst the rings.
4277          */
4278         rp->max_burst = mtu + 32;
4279         if (rp->max_burst > 4096)
4280                 rp->max_burst = 4096;
4281 }
4282
4283 static int niu_alloc_tx_ring_info(struct niu *np,
4284                                   struct tx_ring_info *rp)
4285 {
4286         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4287
4288         rp->mbox = np->ops->alloc_coherent(np->device,
4289                                            sizeof(struct txdma_mailbox),
4290                                            &rp->mbox_dma, GFP_KERNEL);
4291         if (!rp->mbox)
4292                 return -ENOMEM;
4293         if ((unsigned long)rp->mbox & (64UL - 1)) {
4294                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4295                         "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
4296                 return -EINVAL;
4297         }
4298
4299         rp->descr = np->ops->alloc_coherent(np->device,
4300                                             MAX_TX_RING_SIZE * sizeof(__le64),
4301                                             &rp->descr_dma, GFP_KERNEL);
4302         if (!rp->descr)
4303                 return -ENOMEM;
4304         if ((unsigned long)rp->descr & (64UL - 1)) {
4305                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4306                         "TXDMA descr table %p\n", np->dev->name, rp->descr);
4307                 return -EINVAL;
4308         }
4309
4310         rp->pending = MAX_TX_RING_SIZE;
4311         rp->prod = 0;
4312         rp->cons = 0;
4313         rp->wrap_bit = 0;
4314
4315         /* XXX make these configurable... XXX */
4316         rp->mark_freq = rp->pending / 4;
4317
4318         niu_set_max_burst(np, rp);
4319
4320         return 0;
4321 }
4322
4323 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4324 {
4325         u16 bss;
4326
4327         bss = min(PAGE_SHIFT, 15);
4328
4329         rp->rbr_block_size = 1 << bss;
4330         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4331
4332         rp->rbr_sizes[0] = 256;
4333         rp->rbr_sizes[1] = 1024;
4334         if (np->dev->mtu > ETH_DATA_LEN) {
4335                 switch (PAGE_SIZE) {
4336                 case 4 * 1024:
4337                         rp->rbr_sizes[2] = 4096;
4338                         break;
4339
4340                 default:
4341                         rp->rbr_sizes[2] = 8192;
4342                         break;
4343                 }
4344         } else {
4345                 rp->rbr_sizes[2] = 2048;
4346         }
4347         rp->rbr_sizes[3] = rp->rbr_block_size;
4348 }
4349
4350 static int niu_alloc_channels(struct niu *np)
4351 {
4352         struct niu_parent *parent = np->parent;
4353         int first_rx_channel, first_tx_channel;
4354         int i, port, err;
4355
4356         port = np->port;
4357         first_rx_channel = first_tx_channel = 0;
4358         for (i = 0; i < port; i++) {
4359                 first_rx_channel += parent->rxchan_per_port[i];
4360                 first_tx_channel += parent->txchan_per_port[i];
4361         }
4362
4363         np->num_rx_rings = parent->rxchan_per_port[port];
4364         np->num_tx_rings = parent->txchan_per_port[port];
4365
4366         np->dev->real_num_tx_queues = np->num_tx_rings;
4367
4368         np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4369                                GFP_KERNEL);
4370         err = -ENOMEM;
4371         if (!np->rx_rings)
4372                 goto out_err;
4373
4374         for (i = 0; i < np->num_rx_rings; i++) {
4375                 struct rx_ring_info *rp = &np->rx_rings[i];
4376
4377                 rp->np = np;
4378                 rp->rx_channel = first_rx_channel + i;
4379
4380                 err = niu_alloc_rx_ring_info(np, rp);
4381                 if (err)
4382                         goto out_err;
4383
4384                 niu_size_rbr(np, rp);
4385
4386                 /* XXX better defaults, configurable, etc... XXX */
4387                 rp->nonsyn_window = 64;
4388                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4389                 rp->syn_window = 64;
4390                 rp->syn_threshold = rp->rcr_table_size - 64;
4391                 rp->rcr_pkt_threshold = 16;
4392                 rp->rcr_timeout = 8;
4393                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4394                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4395                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4396
4397                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4398                 if (err)
4399                         return err;
4400         }
4401
4402         np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4403                                GFP_KERNEL);
4404         err = -ENOMEM;
4405         if (!np->tx_rings)
4406                 goto out_err;
4407
4408         for (i = 0; i < np->num_tx_rings; i++) {
4409                 struct tx_ring_info *rp = &np->tx_rings[i];
4410
4411                 rp->np = np;
4412                 rp->tx_channel = first_tx_channel + i;
4413
4414                 err = niu_alloc_tx_ring_info(np, rp);
4415                 if (err)
4416                         goto out_err;
4417         }
4418
4419         return 0;
4420
4421 out_err:
4422         niu_free_channels(np);
4423         return err;
4424 }
4425
4426 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4427 {
4428         int limit = 1000;
4429
4430         while (--limit > 0) {
4431                 u64 val = nr64(TX_CS(channel));
4432                 if (val & TX_CS_SNG_STATE)
4433                         return 0;
4434         }
4435         return -ENODEV;
4436 }
4437
4438 static int niu_tx_channel_stop(struct niu *np, int channel)
4439 {
4440         u64 val = nr64(TX_CS(channel));
4441
4442         val |= TX_CS_STOP_N_GO;
4443         nw64(TX_CS(channel), val);
4444
4445         return niu_tx_cs_sng_poll(np, channel);
4446 }
4447
4448 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4449 {
4450         int limit = 1000;
4451
4452         while (--limit > 0) {
4453                 u64 val = nr64(TX_CS(channel));
4454                 if (!(val & TX_CS_RST))
4455                         return 0;
4456         }
4457         return -ENODEV;
4458 }
4459
4460 static int niu_tx_channel_reset(struct niu *np, int channel)
4461 {
4462         u64 val = nr64(TX_CS(channel));
4463         int err;
4464
4465         val |= TX_CS_RST;
4466         nw64(TX_CS(channel), val);
4467
4468         err = niu_tx_cs_reset_poll(np, channel);
4469         if (!err)
4470                 nw64(TX_RING_KICK(channel), 0);
4471
4472         return err;
4473 }
4474
4475 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4476 {
4477         u64 val;
4478
4479         nw64(TX_LOG_MASK1(channel), 0);
4480         nw64(TX_LOG_VAL1(channel), 0);
4481         nw64(TX_LOG_MASK2(channel), 0);
4482         nw64(TX_LOG_VAL2(channel), 0);
4483         nw64(TX_LOG_PAGE_RELO1(channel), 0);
4484         nw64(TX_LOG_PAGE_RELO2(channel), 0);
4485         nw64(TX_LOG_PAGE_HDL(channel), 0);
4486
4487         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4488         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4489         nw64(TX_LOG_PAGE_VLD(channel), val);
4490
4491         /* XXX TXDMA 32bit mode? XXX */
4492
4493         return 0;
4494 }
4495
4496 static void niu_txc_enable_port(struct niu *np, int on)
4497 {
4498         unsigned long flags;
4499         u64 val, mask;
4500
4501         niu_lock_parent(np, flags);
4502         val = nr64(TXC_CONTROL);
4503         mask = (u64)1 << np->port;
4504         if (on) {
4505                 val |= TXC_CONTROL_ENABLE | mask;
4506         } else {
4507                 val &= ~mask;
4508                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4509                         val &= ~TXC_CONTROL_ENABLE;
4510         }
4511         nw64(TXC_CONTROL, val);
4512         niu_unlock_parent(np, flags);
4513 }
4514
4515 static void niu_txc_set_imask(struct niu *np, u64 imask)
4516 {
4517         unsigned long flags;
4518         u64 val;
4519
4520         niu_lock_parent(np, flags);
4521         val = nr64(TXC_INT_MASK);
4522         val &= ~TXC_INT_MASK_VAL(np->port);
4523         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4524         niu_unlock_parent(np, flags);
4525 }
4526
4527 static void niu_txc_port_dma_enable(struct niu *np, int on)
4528 {
4529         u64 val = 0;
4530
4531         if (on) {
4532                 int i;
4533
4534                 for (i = 0; i < np->num_tx_rings; i++)
4535                         val |= (1 << np->tx_rings[i].tx_channel);
4536         }
4537         nw64(TXC_PORT_DMA(np->port), val);
4538 }
4539
4540 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4541 {
4542         int err, channel = rp->tx_channel;
4543         u64 val, ring_len;
4544
4545         err = niu_tx_channel_stop(np, channel);
4546         if (err)
4547                 return err;
4548
4549         err = niu_tx_channel_reset(np, channel);
4550         if (err)
4551                 return err;
4552
4553         err = niu_tx_channel_lpage_init(np, channel);
4554         if (err)
4555                 return err;
4556
4557         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4558         nw64(TX_ENT_MSK(channel), 0);
4559
4560         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4561                               TX_RNG_CFIG_STADDR)) {
4562                 dev_err(np->device, PFX "%s: TX ring channel %d "
4563                         "DMA addr (%llx) is not aligned.\n",
4564                         np->dev->name, channel,
4565                         (unsigned long long) rp->descr_dma);
4566                 return -EINVAL;
4567         }
4568
4569         /* The length field in TX_RNG_CFIG is measured in 64-byte
4570          * blocks.  rp->pending is the number of TX descriptors in
4571          * our ring, 8 bytes each, thus we divide by 8 bytes more
4572          * to get the proper value the chip wants.
4573          */
4574         ring_len = (rp->pending / 8);
4575
4576         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4577                rp->descr_dma);
4578         nw64(TX_RNG_CFIG(channel), val);
4579
4580         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4581             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4582                 dev_err(np->device, PFX "%s: TX ring channel %d "
4583                         "MBOX addr (%llx) is has illegal bits.\n",
4584                         np->dev->name, channel,
4585                         (unsigned long long) rp->mbox_dma);
4586                 return -EINVAL;
4587         }
4588         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4589         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4590
4591         nw64(TX_CS(channel), 0);
4592
4593         rp->last_pkt_cnt = 0;
4594
4595         return 0;
4596 }
4597
4598 static void niu_init_rdc_groups(struct niu *np)
4599 {
4600         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4601         int i, first_table_num = tp->first_table_num;
4602
4603         for (i = 0; i < tp->num_tables; i++) {
4604                 struct rdc_table *tbl = &tp->tables[i];
4605                 int this_table = first_table_num + i;
4606                 int slot;
4607
4608                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4609                         nw64(RDC_TBL(this_table, slot),
4610                              tbl->rxdma_channel[slot]);
4611         }
4612
4613         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4614 }
4615
4616 static void niu_init_drr_weight(struct niu *np)
4617 {
4618         int type = phy_decode(np->parent->port_phy, np->port);
4619         u64 val;
4620
4621         switch (type) {
4622         case PORT_TYPE_10G:
4623                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4624                 break;
4625
4626         case PORT_TYPE_1G:
4627         default:
4628                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4629                 break;
4630         }
4631         nw64(PT_DRR_WT(np->port), val);
4632 }
4633
4634 static int niu_init_hostinfo(struct niu *np)
4635 {
4636         struct niu_parent *parent = np->parent;
4637         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4638         int i, err, num_alt = niu_num_alt_addr(np);
4639         int first_rdc_table = tp->first_table_num;
4640
4641         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4642         if (err)
4643                 return err;
4644
4645         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4646         if (err)
4647                 return err;
4648
4649         for (i = 0; i < num_alt; i++) {
4650                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4651                 if (err)
4652                         return err;
4653         }
4654
4655         return 0;
4656 }
4657
4658 static int niu_rx_channel_reset(struct niu *np, int channel)
4659 {
4660         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4661                                       RXDMA_CFIG1_RST, 1000, 10,
4662                                       "RXDMA_CFIG1");
4663 }
4664
4665 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4666 {
4667         u64 val;
4668
4669         nw64(RX_LOG_MASK1(channel), 0);
4670         nw64(RX_LOG_VAL1(channel), 0);
4671         nw64(RX_LOG_MASK2(channel), 0);
4672         nw64(RX_LOG_VAL2(channel), 0);
4673         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4674         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4675         nw64(RX_LOG_PAGE_HDL(channel), 0);
4676
4677         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4678         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4679         nw64(RX_LOG_PAGE_VLD(channel), val);
4680
4681         return 0;
4682 }
4683
4684 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4685 {
4686         u64 val;
4687
4688         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4689                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4690                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4691                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4692         nw64(RDC_RED_PARA(rp->rx_channel), val);
4693 }
4694
4695 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4696 {
4697         u64 val = 0;
4698
4699         switch (rp->rbr_block_size) {
4700         case 4 * 1024:
4701                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4702                 break;
4703         case 8 * 1024:
4704                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4705                 break;
4706         case 16 * 1024:
4707                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4708                 break;
4709         case 32 * 1024:
4710                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4711                 break;
4712         default:
4713                 return -EINVAL;
4714         }
4715         val |= RBR_CFIG_B_VLD2;
4716         switch (rp->rbr_sizes[2]) {
4717         case 2 * 1024:
4718                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4719                 break;
4720         case 4 * 1024:
4721                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4722                 break;
4723         case 8 * 1024:
4724                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4725                 break;
4726         case 16 * 1024:
4727                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4728                 break;
4729
4730         default:
4731                 return -EINVAL;
4732         }
4733         val |= RBR_CFIG_B_VLD1;
4734         switch (rp->rbr_sizes[1]) {
4735         case 1 * 1024:
4736                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4737                 break;
4738         case 2 * 1024:
4739                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4740                 break;
4741         case 4 * 1024:
4742                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4743                 break;
4744         case 8 * 1024:
4745                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4746                 break;
4747
4748         default:
4749                 return -EINVAL;
4750         }
4751         val |= RBR_CFIG_B_VLD0;
4752         switch (rp->rbr_sizes[0]) {
4753         case 256:
4754                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4755                 break;
4756         case 512:
4757                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4758                 break;
4759         case 1 * 1024:
4760                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4761                 break;
4762         case 2 * 1024:
4763                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4764                 break;
4765
4766         default:
4767                 return -EINVAL;
4768         }
4769
4770         *ret = val;
4771         return 0;
4772 }
4773
4774 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4775 {
4776         u64 val = nr64(RXDMA_CFIG1(channel));
4777         int limit;
4778
4779         if (on)
4780                 val |= RXDMA_CFIG1_EN;
4781         else
4782                 val &= ~RXDMA_CFIG1_EN;
4783         nw64(RXDMA_CFIG1(channel), val);
4784
4785         limit = 1000;
4786         while (--limit > 0) {
4787                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4788                         break;
4789                 udelay(10);
4790         }
4791         if (limit <= 0)
4792                 return -ENODEV;
4793         return 0;
4794 }
4795
4796 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4797 {
4798         int err, channel = rp->rx_channel;
4799         u64 val;
4800
4801         err = niu_rx_channel_reset(np, channel);
4802         if (err)
4803                 return err;
4804
4805         err = niu_rx_channel_lpage_init(np, channel);
4806         if (err)
4807                 return err;
4808
4809         niu_rx_channel_wred_init(np, rp);
4810
4811         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4812         nw64(RX_DMA_CTL_STAT(channel),
4813              (RX_DMA_CTL_STAT_MEX |
4814               RX_DMA_CTL_STAT_RCRTHRES |
4815               RX_DMA_CTL_STAT_RCRTO |
4816               RX_DMA_CTL_STAT_RBR_EMPTY));
4817         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4818         nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4819         nw64(RBR_CFIG_A(channel),
4820              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4821              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4822         err = niu_compute_rbr_cfig_b(rp, &val);
4823         if (err)
4824                 return err;
4825         nw64(RBR_CFIG_B(channel), val);
4826         nw64(RCRCFIG_A(channel),
4827              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4828              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4829         nw64(RCRCFIG_B(channel),
4830              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4831              RCRCFIG_B_ENTOUT |
4832              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4833
4834         err = niu_enable_rx_channel(np, channel, 1);
4835         if (err)
4836                 return err;
4837
4838         nw64(RBR_KICK(channel), rp->rbr_index);
4839
4840         val = nr64(RX_DMA_CTL_STAT(channel));
4841         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4842         nw64(RX_DMA_CTL_STAT(channel), val);
4843
4844         return 0;
4845 }
4846
4847 static int niu_init_rx_channels(struct niu *np)
4848 {
4849         unsigned long flags;
4850         u64 seed = jiffies_64;
4851         int err, i;
4852
4853         niu_lock_parent(np, flags);
4854         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4855         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4856         niu_unlock_parent(np, flags);
4857
4858         /* XXX RXDMA 32bit mode? XXX */
4859
4860         niu_init_rdc_groups(np);
4861         niu_init_drr_weight(np);
4862
4863         err = niu_init_hostinfo(np);
4864         if (err)
4865                 return err;
4866
4867         for (i = 0; i < np->num_rx_rings; i++) {
4868                 struct rx_ring_info *rp = &np->rx_rings[i];
4869
4870                 err = niu_init_one_rx_channel(np, rp);
4871                 if (err)
4872                         return err;
4873         }
4874
4875         return 0;
4876 }
4877
4878 static int niu_set_ip_frag_rule(struct niu *np)
4879 {
4880         struct niu_parent *parent = np->parent;
4881         struct niu_classifier *cp = &np->clas;
4882         struct niu_tcam_entry *tp;
4883         int index, err;
4884
4885         /* XXX fix this allocation scheme XXX */
4886         index = cp->tcam_index;
4887         tp = &parent->tcam[index];
4888
4889         /* Note that the noport bit is the same in both ipv4 and
4890          * ipv6 format TCAM entries.
4891          */
4892         memset(tp, 0, sizeof(*tp));
4893         tp->key[1] = TCAM_V4KEY1_NOPORT;
4894         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
4895         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
4896                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
4897         err = tcam_write(np, index, tp->key, tp->key_mask);
4898         if (err)
4899                 return err;
4900         err = tcam_assoc_write(np, index, tp->assoc_data);
4901         if (err)
4902                 return err;
4903
4904         return 0;
4905 }
4906
4907 static int niu_init_classifier_hw(struct niu *np)
4908 {
4909         struct niu_parent *parent = np->parent;
4910         struct niu_classifier *cp = &np->clas;
4911         int i, err;
4912
4913         nw64(H1POLY, cp->h1_init);
4914         nw64(H2POLY, cp->h2_init);
4915
4916         err = niu_init_hostinfo(np);
4917         if (err)
4918                 return err;
4919
4920         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
4921                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
4922
4923                 vlan_tbl_write(np, i, np->port,
4924                                vp->vlan_pref, vp->rdc_num);
4925         }
4926
4927         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
4928                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
4929
4930                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
4931                                                 ap->rdc_num, ap->mac_pref);
4932                 if (err)
4933                         return err;
4934         }
4935
4936         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
4937                 int index = i - CLASS_CODE_USER_PROG1;
4938
4939                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
4940                 if (err)
4941                         return err;
4942                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
4943                 if (err)
4944                         return err;
4945         }
4946
4947         err = niu_set_ip_frag_rule(np);
4948         if (err)
4949                 return err;
4950
4951         tcam_enable(np, 1);
4952
4953         return 0;
4954 }
4955
4956 static int niu_zcp_write(struct niu *np, int index, u64 *data)
4957 {
4958         nw64(ZCP_RAM_DATA0, data[0]);
4959         nw64(ZCP_RAM_DATA1, data[1]);
4960         nw64(ZCP_RAM_DATA2, data[2]);
4961         nw64(ZCP_RAM_DATA3, data[3]);
4962         nw64(ZCP_RAM_DATA4, data[4]);
4963         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
4964         nw64(ZCP_RAM_ACC,
4965              (ZCP_RAM_ACC_WRITE |
4966               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4967               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4968
4969         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4970                                    1000, 100);
4971 }
4972
4973 static int niu_zcp_read(struct niu *np, int index, u64 *data)
4974 {
4975         int err;
4976
4977         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4978                                   1000, 100);
4979         if (err) {
4980                 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
4981                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
4982                         (unsigned long long) nr64(ZCP_RAM_ACC));
4983                 return err;
4984         }
4985
4986         nw64(ZCP_RAM_ACC,
4987              (ZCP_RAM_ACC_READ |
4988               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4989               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4990
4991         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4992                                   1000, 100);
4993         if (err) {
4994                 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
4995                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
4996                         (unsigned long long) nr64(ZCP_RAM_ACC));
4997                 return err;
4998         }
4999
5000         data[0] = nr64(ZCP_RAM_DATA0);
5001         data[1] = nr64(ZCP_RAM_DATA1);
5002         data[2] = nr64(ZCP_RAM_DATA2);
5003         data[3] = nr64(ZCP_RAM_DATA3);
5004         data[4] = nr64(ZCP_RAM_DATA4);
5005
5006         return 0;
5007 }
5008
5009 static void niu_zcp_cfifo_reset(struct niu *np)
5010 {
5011         u64 val = nr64(RESET_CFIFO);
5012
5013         val |= RESET_CFIFO_RST(np->port);
5014         nw64(RESET_CFIFO, val);
5015         udelay(10);
5016
5017         val &= ~RESET_CFIFO_RST(np->port);
5018         nw64(RESET_CFIFO, val);
5019 }
5020
5021 static int niu_init_zcp(struct niu *np)
5022 {
5023         u64 data[5], rbuf[5];
5024         int i, max, err;
5025
5026         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5027                 if (np->port == 0 || np->port == 1)
5028                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
5029                 else
5030                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
5031         } else
5032                 max = NIU_CFIFO_ENTRIES;
5033
5034         data[0] = 0;
5035         data[1] = 0;
5036         data[2] = 0;
5037         data[3] = 0;
5038         data[4] = 0;
5039
5040         for (i = 0; i < max; i++) {
5041                 err = niu_zcp_write(np, i, data);
5042                 if (err)
5043                         return err;
5044                 err = niu_zcp_read(np, i, rbuf);
5045                 if (err)
5046                         return err;
5047         }
5048
5049         niu_zcp_cfifo_reset(np);
5050         nw64(CFIFO_ECC(np->port), 0);
5051         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5052         (void) nr64(ZCP_INT_STAT);
5053         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5054
5055         return 0;
5056 }
5057
5058 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5059 {
5060         u64 val = nr64_ipp(IPP_CFIG);
5061
5062         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5063         nw64_ipp(IPP_DFIFO_WR_PTR, index);
5064         nw64_ipp(IPP_DFIFO_WR0, data[0]);
5065         nw64_ipp(IPP_DFIFO_WR1, data[1]);
5066         nw64_ipp(IPP_DFIFO_WR2, data[2]);
5067         nw64_ipp(IPP_DFIFO_WR3, data[3]);
5068         nw64_ipp(IPP_DFIFO_WR4, data[4]);
5069         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5070 }
5071
5072 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5073 {
5074         nw64_ipp(IPP_DFIFO_RD_PTR, index);
5075         data[0] = nr64_ipp(IPP_DFIFO_RD0);
5076         data[1] = nr64_ipp(IPP_DFIFO_RD1);
5077         data[2] = nr64_ipp(IPP_DFIFO_RD2);
5078         data[3] = nr64_ipp(IPP_DFIFO_RD3);
5079         data[4] = nr64_ipp(IPP_DFIFO_RD4);
5080 }
5081
5082 static int niu_ipp_reset(struct niu *np)
5083 {
5084         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5085                                           1000, 100, "IPP_CFIG");
5086 }
5087
5088 static int niu_init_ipp(struct niu *np)
5089 {
5090         u64 data[5], rbuf[5], val;
5091         int i, max, err;
5092
5093         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5094                 if (np->port == 0 || np->port == 1)
5095                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
5096                 else
5097                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
5098         } else
5099                 max = NIU_DFIFO_ENTRIES;
5100
5101         data[0] = 0;
5102         data[1] = 0;
5103         data[2] = 0;
5104         data[3] = 0;
5105         data[4] = 0;
5106
5107         for (i = 0; i < max; i++) {
5108                 niu_ipp_write(np, i, data);
5109                 niu_ipp_read(np, i, rbuf);
5110         }
5111
5112         (void) nr64_ipp(IPP_INT_STAT);
5113         (void) nr64_ipp(IPP_INT_STAT);
5114
5115         err = niu_ipp_reset(np);
5116         if (err)
5117                 return err;
5118
5119         (void) nr64_ipp(IPP_PKT_DIS);
5120         (void) nr64_ipp(IPP_BAD_CS_CNT);
5121         (void) nr64_ipp(IPP_ECC);
5122
5123         (void) nr64_ipp(IPP_INT_STAT);
5124
5125         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5126
5127         val = nr64_ipp(IPP_CFIG);
5128         val &= ~IPP_CFIG_IP_MAX_PKT;
5129         val |= (IPP_CFIG_IPP_ENABLE |
5130                 IPP_CFIG_DFIFO_ECC_EN |
5131                 IPP_CFIG_DROP_BAD_CRC |
5132                 IPP_CFIG_CKSUM_EN |
5133                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5134         nw64_ipp(IPP_CFIG, val);
5135
5136         return 0;
5137 }
5138
5139 static void niu_handle_led(struct niu *np, int status)
5140 {
5141         u64 val;
5142         val = nr64_mac(XMAC_CONFIG);
5143
5144         if ((np->flags & NIU_FLAGS_10G) != 0 &&
5145             (np->flags & NIU_FLAGS_FIBER) != 0) {
5146                 if (status) {
5147                         val |= XMAC_CONFIG_LED_POLARITY;
5148                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
5149                 } else {
5150                         val |= XMAC_CONFIG_FORCE_LED_ON;
5151                         val &= ~XMAC_CONFIG_LED_POLARITY;
5152                 }
5153         }
5154
5155         nw64_mac(XMAC_CONFIG, val);
5156 }
5157
5158 static void niu_init_xif_xmac(struct niu *np)
5159 {
5160         struct niu_link_config *lp = &np->link_config;
5161         u64 val;
5162
5163         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5164                 val = nr64(MIF_CONFIG);
5165                 val |= MIF_CONFIG_ATCA_GE;
5166                 nw64(MIF_CONFIG, val);
5167         }
5168
5169         val = nr64_mac(XMAC_CONFIG);
5170         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5171
5172         val |= XMAC_CONFIG_TX_OUTPUT_EN;
5173
5174         if (lp->loopback_mode == LOOPBACK_MAC) {
5175                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5176                 val |= XMAC_CONFIG_LOOPBACK;
5177         } else {
5178                 val &= ~XMAC_CONFIG_LOOPBACK;
5179         }
5180
5181         if (np->flags & NIU_FLAGS_10G) {
5182                 val &= ~XMAC_CONFIG_LFS_DISABLE;
5183         } else {
5184                 val |= XMAC_CONFIG_LFS_DISABLE;
5185                 if (!(np->flags & NIU_FLAGS_FIBER) &&
5186                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
5187                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
5188                 else
5189                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5190         }
5191
5192         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5193
5194         if (lp->active_speed == SPEED_100)
5195                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5196         else
5197                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5198
5199         nw64_mac(XMAC_CONFIG, val);
5200
5201         val = nr64_mac(XMAC_CONFIG);
5202         val &= ~XMAC_CONFIG_MODE_MASK;
5203         if (np->flags & NIU_FLAGS_10G) {
5204                 val |= XMAC_CONFIG_MODE_XGMII;
5205         } else {
5206                 if (lp->active_speed == SPEED_100)
5207                         val |= XMAC_CONFIG_MODE_MII;
5208                 else
5209                         val |= XMAC_CONFIG_MODE_GMII;
5210         }
5211
5212         nw64_mac(XMAC_CONFIG, val);
5213 }
5214
5215 static void niu_init_xif_bmac(struct niu *np)
5216 {
5217         struct niu_link_config *lp = &np->link_config;
5218         u64 val;
5219
5220         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5221
5222         if (lp->loopback_mode == LOOPBACK_MAC)
5223                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5224         else
5225                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5226
5227         if (lp->active_speed == SPEED_1000)
5228                 val |= BMAC_XIF_CONFIG_GMII_MODE;
5229         else
5230                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5231
5232         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5233                  BMAC_XIF_CONFIG_LED_POLARITY);
5234
5235         if (!(np->flags & NIU_FLAGS_10G) &&
5236             !(np->flags & NIU_FLAGS_FIBER) &&
5237             lp->active_speed == SPEED_100)
5238                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5239         else
5240                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5241
5242         nw64_mac(BMAC_XIF_CONFIG, val);
5243 }
5244
5245 static void niu_init_xif(struct niu *np)
5246 {
5247         if (np->flags & NIU_FLAGS_XMAC)
5248                 niu_init_xif_xmac(np);
5249         else
5250                 niu_init_xif_bmac(np);
5251 }
5252
5253 static void niu_pcs_mii_reset(struct niu *np)
5254 {
5255         int limit = 1000;
5256         u64 val = nr64_pcs(PCS_MII_CTL);
5257         val |= PCS_MII_CTL_RST;
5258         nw64_pcs(PCS_MII_CTL, val);
5259         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5260                 udelay(100);
5261                 val = nr64_pcs(PCS_MII_CTL);
5262         }
5263 }
5264
5265 static void niu_xpcs_reset(struct niu *np)
5266 {
5267         int limit = 1000;
5268         u64 val = nr64_xpcs(XPCS_CONTROL1);
5269         val |= XPCS_CONTROL1_RESET;
5270         nw64_xpcs(XPCS_CONTROL1, val);
5271         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5272                 udelay(100);
5273                 val = nr64_xpcs(XPCS_CONTROL1);
5274         }
5275 }
5276
5277 static int niu_init_pcs(struct niu *np)
5278 {
5279         struct niu_link_config *lp = &np->link_config;
5280         u64 val;
5281
5282         switch (np->flags & (NIU_FLAGS_10G |
5283                              NIU_FLAGS_FIBER |
5284                              NIU_FLAGS_XCVR_SERDES)) {
5285         case NIU_FLAGS_FIBER:
5286                 /* 1G fiber */
5287                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5288                 nw64_pcs(PCS_DPATH_MODE, 0);
5289                 niu_pcs_mii_reset(np);
5290                 break;
5291
5292         case NIU_FLAGS_10G:
5293         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5294         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5295                 /* 10G SERDES */
5296                 if (!(np->flags & NIU_FLAGS_XMAC))
5297                         return -EINVAL;
5298
5299                 /* 10G copper or fiber */
5300                 val = nr64_mac(XMAC_CONFIG);
5301                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5302                 nw64_mac(XMAC_CONFIG, val);
5303
5304                 niu_xpcs_reset(np);
5305
5306                 val = nr64_xpcs(XPCS_CONTROL1);
5307                 if (lp->loopback_mode == LOOPBACK_PHY)
5308                         val |= XPCS_CONTROL1_LOOPBACK;
5309                 else
5310                         val &= ~XPCS_CONTROL1_LOOPBACK;
5311                 nw64_xpcs(XPCS_CONTROL1, val);
5312
5313                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5314                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5315                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5316                 break;
5317
5318
5319         case NIU_FLAGS_XCVR_SERDES:
5320                 /* 1G SERDES */
5321                 niu_pcs_mii_reset(np);
5322                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5323                 nw64_pcs(PCS_DPATH_MODE, 0);
5324                 break;
5325
5326         case 0:
5327                 /* 1G copper */
5328         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5329                 /* 1G RGMII FIBER */
5330                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5331                 niu_pcs_mii_reset(np);
5332                 break;
5333
5334         default:
5335                 return -EINVAL;
5336         }
5337
5338         return 0;
5339 }
5340
5341 static int niu_reset_tx_xmac(struct niu *np)
5342 {
5343         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5344                                           (XTXMAC_SW_RST_REG_RS |
5345                                            XTXMAC_SW_RST_SOFT_RST),
5346                                           1000, 100, "XTXMAC_SW_RST");
5347 }
5348
5349 static int niu_reset_tx_bmac(struct niu *np)
5350 {
5351         int limit;
5352
5353         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5354         limit = 1000;
5355         while (--limit >= 0) {
5356                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5357                         break;
5358                 udelay(100);
5359         }
5360         if (limit < 0) {
5361                 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
5362                         "BTXMAC_SW_RST[%llx]\n",
5363                         np->port,
5364                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5365                 return -ENODEV;
5366         }
5367
5368         return 0;
5369 }
5370
5371 static int niu_reset_tx_mac(struct niu *np)
5372 {
5373         if (np->flags & NIU_FLAGS_XMAC)
5374                 return niu_reset_tx_xmac(np);
5375         else
5376                 return niu_reset_tx_bmac(np);
5377 }
5378
5379 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5380 {
5381         u64 val;
5382
5383         val = nr64_mac(XMAC_MIN);
5384         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5385                  XMAC_MIN_RX_MIN_PKT_SIZE);
5386         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5387         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5388         nw64_mac(XMAC_MIN, val);
5389
5390         nw64_mac(XMAC_MAX, max);
5391
5392         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5393
5394         val = nr64_mac(XMAC_IPG);
5395         if (np->flags & NIU_FLAGS_10G) {
5396                 val &= ~XMAC_IPG_IPG_XGMII;
5397                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5398         } else {
5399                 val &= ~XMAC_IPG_IPG_MII_GMII;
5400                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5401         }
5402         nw64_mac(XMAC_IPG, val);
5403
5404         val = nr64_mac(XMAC_CONFIG);
5405         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5406                  XMAC_CONFIG_STRETCH_MODE |
5407                  XMAC_CONFIG_VAR_MIN_IPG_EN |
5408                  XMAC_CONFIG_TX_ENABLE);
5409         nw64_mac(XMAC_CONFIG, val);
5410
5411         nw64_mac(TXMAC_FRM_CNT, 0);
5412         nw64_mac(TXMAC_BYTE_CNT, 0);
5413 }
5414
5415 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5416 {
5417         u64 val;
5418
5419         nw64_mac(BMAC_MIN_FRAME, min);
5420         nw64_mac(BMAC_MAX_FRAME, max);
5421
5422         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5423         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5424         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5425
5426         val = nr64_mac(BTXMAC_CONFIG);
5427         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5428                  BTXMAC_CONFIG_ENABLE);
5429         nw64_mac(BTXMAC_CONFIG, val);
5430 }
5431
5432 static void niu_init_tx_mac(struct niu *np)
5433 {
5434         u64 min, max;
5435
5436         min = 64;
5437         if (np->dev->mtu > ETH_DATA_LEN)
5438                 max = 9216;
5439         else
5440                 max = 1522;
5441
5442         /* The XMAC_MIN register only accepts values for TX min which
5443          * have the low 3 bits cleared.
5444          */
5445         BUILD_BUG_ON(min & 0x7);
5446
5447         if (np->flags & NIU_FLAGS_XMAC)
5448                 niu_init_tx_xmac(np, min, max);
5449         else
5450                 niu_init_tx_bmac(np, min, max);
5451 }
5452
5453 static int niu_reset_rx_xmac(struct niu *np)
5454 {
5455         int limit;
5456
5457         nw64_mac(XRXMAC_SW_RST,
5458                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5459         limit = 1000;
5460         while (--limit >= 0) {
5461                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5462                                                  XRXMAC_SW_RST_SOFT_RST)))
5463                     break;
5464                 udelay(100);
5465         }
5466         if (limit < 0) {
5467                 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
5468                         "XRXMAC_SW_RST[%llx]\n",
5469                         np->port,
5470                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5471                 return -ENODEV;
5472         }
5473
5474         return 0;
5475 }
5476
5477 static int niu_reset_rx_bmac(struct niu *np)
5478 {
5479         int limit;
5480
5481         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5482         limit = 1000;
5483         while (--limit >= 0) {
5484                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5485                         break;
5486                 udelay(100);
5487         }
5488         if (limit < 0) {
5489                 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
5490                         "BRXMAC_SW_RST[%llx]\n",
5491                         np->port,
5492                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5493                 return -ENODEV;
5494         }
5495
5496         return 0;
5497 }
5498
5499 static int niu_reset_rx_mac(struct niu *np)
5500 {
5501         if (np->flags & NIU_FLAGS_XMAC)
5502                 return niu_reset_rx_xmac(np);
5503         else
5504                 return niu_reset_rx_bmac(np);
5505 }
5506
5507 static void niu_init_rx_xmac(struct niu *np)
5508 {
5509         struct niu_parent *parent = np->parent;
5510         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5511         int first_rdc_table = tp->first_table_num;
5512         unsigned long i;
5513         u64 val;
5514
5515         nw64_mac(XMAC_ADD_FILT0, 0);
5516         nw64_mac(XMAC_ADD_FILT1, 0);
5517         nw64_mac(XMAC_ADD_FILT2, 0);
5518         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5519         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5520         for (i = 0; i < MAC_NUM_HASH; i++)
5521                 nw64_mac(XMAC_HASH_TBL(i), 0);
5522         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5523         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5524         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5525
5526         val = nr64_mac(XMAC_CONFIG);
5527         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5528                  XMAC_CONFIG_PROMISCUOUS |
5529                  XMAC_CONFIG_PROMISC_GROUP |
5530                  XMAC_CONFIG_ERR_CHK_DIS |
5531                  XMAC_CONFIG_RX_CRC_CHK_DIS |
5532                  XMAC_CONFIG_RESERVED_MULTICAST |
5533                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5534                  XMAC_CONFIG_ADDR_FILTER_EN |
5535                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5536                  XMAC_CONFIG_STRIP_CRC |
5537                  XMAC_CONFIG_PASS_FLOW_CTRL |
5538                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5539         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5540         nw64_mac(XMAC_CONFIG, val);
5541
5542         nw64_mac(RXMAC_BT_CNT, 0);
5543         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5544         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5545         nw64_mac(RXMAC_FRAG_CNT, 0);
5546         nw64_mac(RXMAC_HIST_CNT1, 0);
5547         nw64_mac(RXMAC_HIST_CNT2, 0);
5548         nw64_mac(RXMAC_HIST_CNT3, 0);
5549         nw64_mac(RXMAC_HIST_CNT4, 0);
5550         nw64_mac(RXMAC_HIST_CNT5, 0);
5551         nw64_mac(RXMAC_HIST_CNT6, 0);
5552         nw64_mac(RXMAC_HIST_CNT7, 0);
5553         nw64_mac(RXMAC_MPSZER_CNT, 0);
5554         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5555         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5556         nw64_mac(LINK_FAULT_CNT, 0);
5557 }
5558
5559 static void niu_init_rx_bmac(struct niu *np)
5560 {
5561         struct niu_parent *parent = np->parent;
5562         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5563         int first_rdc_table = tp->first_table_num;
5564         unsigned long i;
5565         u64 val;
5566
5567         nw64_mac(BMAC_ADD_FILT0, 0);
5568         nw64_mac(BMAC_ADD_FILT1, 0);
5569         nw64_mac(BMAC_ADD_FILT2, 0);
5570         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5571         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5572         for (i = 0; i < MAC_NUM_HASH; i++)
5573                 nw64_mac(BMAC_HASH_TBL(i), 0);
5574         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5575         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5576         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5577
5578         val = nr64_mac(BRXMAC_CONFIG);
5579         val &= ~(BRXMAC_CONFIG_ENABLE |
5580                  BRXMAC_CONFIG_STRIP_PAD |
5581                  BRXMAC_CONFIG_STRIP_FCS |
5582                  BRXMAC_CONFIG_PROMISC |
5583                  BRXMAC_CONFIG_PROMISC_GRP |
5584                  BRXMAC_CONFIG_ADDR_FILT_EN |
5585                  BRXMAC_CONFIG_DISCARD_DIS);
5586         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5587         nw64_mac(BRXMAC_CONFIG, val);
5588
5589         val = nr64_mac(BMAC_ADDR_CMPEN);
5590         val |= BMAC_ADDR_CMPEN_EN0;
5591         nw64_mac(BMAC_ADDR_CMPEN, val);
5592 }
5593
5594 static void niu_init_rx_mac(struct niu *np)
5595 {
5596         niu_set_primary_mac(np, np->dev->dev_addr);
5597
5598         if (np->flags & NIU_FLAGS_XMAC)
5599                 niu_init_rx_xmac(np);
5600         else
5601                 niu_init_rx_bmac(np);
5602 }
5603
5604 static void niu_enable_tx_xmac(struct niu *np, int on)
5605 {
5606         u64 val = nr64_mac(XMAC_CONFIG);
5607
5608         if (on)
5609                 val |= XMAC_CONFIG_TX_ENABLE;
5610         else
5611                 val &= ~XMAC_CONFIG_TX_ENABLE;
5612         nw64_mac(XMAC_CONFIG, val);
5613 }
5614
5615 static void niu_enable_tx_bmac(struct niu *np, int on)
5616 {
5617         u64 val = nr64_mac(BTXMAC_CONFIG);
5618
5619         if (on)
5620                 val |= BTXMAC_CONFIG_ENABLE;
5621         else
5622                 val &= ~BTXMAC_CONFIG_ENABLE;
5623         nw64_mac(BTXMAC_CONFIG, val);
5624 }
5625
5626 static void niu_enable_tx_mac(struct niu *np, int on)
5627 {
5628         if (np->flags & NIU_FLAGS_XMAC)
5629                 niu_enable_tx_xmac(np, on);
5630         else
5631                 niu_enable_tx_bmac(np, on);
5632 }
5633
5634 static void niu_enable_rx_xmac(struct niu *np, int on)
5635 {
5636         u64 val = nr64_mac(XMAC_CONFIG);
5637
5638         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5639                  XMAC_CONFIG_PROMISCUOUS);
5640
5641         if (np->flags & NIU_FLAGS_MCAST)
5642                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5643         if (np->flags & NIU_FLAGS_PROMISC)
5644                 val |= XMAC_CONFIG_PROMISCUOUS;
5645
5646         if (on)
5647                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5648         else
5649                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5650         nw64_mac(XMAC_CONFIG, val);
5651 }
5652
5653 static void niu_enable_rx_bmac(struct niu *np, int on)
5654 {
5655         u64 val = nr64_mac(BRXMAC_CONFIG);
5656
5657         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5658                  BRXMAC_CONFIG_PROMISC);
5659
5660         if (np->flags & NIU_FLAGS_MCAST)
5661                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5662         if (np->flags & NIU_FLAGS_PROMISC)
5663                 val |= BRXMAC_CONFIG_PROMISC;
5664
5665         if (on)
5666                 val |= BRXMAC_CONFIG_ENABLE;
5667         else
5668                 val &= ~BRXMAC_CONFIG_ENABLE;
5669         nw64_mac(BRXMAC_CONFIG, val);
5670 }
5671
5672 static void niu_enable_rx_mac(struct niu *np, int on)
5673 {
5674         if (np->flags & NIU_FLAGS_XMAC)
5675                 niu_enable_rx_xmac(np, on);
5676         else
5677                 niu_enable_rx_bmac(np, on);
5678 }
5679
5680 static int niu_init_mac(struct niu *np)
5681 {
5682         int err;
5683
5684         niu_init_xif(np);
5685         err = niu_init_pcs(np);
5686         if (err)
5687                 return err;
5688
5689         err = niu_reset_tx_mac(np);
5690         if (err)
5691                 return err;
5692         niu_init_tx_mac(np);
5693         err = niu_reset_rx_mac(np);
5694         if (err)
5695                 return err;
5696         niu_init_rx_mac(np);
5697
5698         /* This looks hookey but the RX MAC reset we just did will
5699          * undo some of the state we setup in niu_init_tx_mac() so we
5700          * have to call it again.  In particular, the RX MAC reset will
5701          * set the XMAC_MAX register back to it's default value.
5702          */
5703         niu_init_tx_mac(np);
5704         niu_enable_tx_mac(np, 1);
5705
5706         niu_enable_rx_mac(np, 1);
5707
5708         return 0;
5709 }
5710
5711 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5712 {
5713         (void) niu_tx_channel_stop(np, rp->tx_channel);
5714 }
5715
5716 static void niu_stop_tx_channels(struct niu *np)
5717 {
5718         int i;
5719
5720         for (i = 0; i < np->num_tx_rings; i++) {
5721                 struct tx_ring_info *rp = &np->tx_rings[i];
5722
5723                 niu_stop_one_tx_channel(np, rp);
5724         }
5725 }
5726
5727 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5728 {
5729         (void) niu_tx_channel_reset(np, rp->tx_channel);
5730 }
5731
5732 static void niu_reset_tx_channels(struct niu *np)
5733 {
5734         int i;
5735
5736         for (i = 0; i < np->num_tx_rings; i++) {
5737                 struct tx_ring_info *rp = &np->tx_rings[i];
5738
5739                 niu_reset_one_tx_channel(np, rp);
5740         }
5741 }
5742
5743 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5744 {
5745         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5746 }
5747
5748 static void niu_stop_rx_channels(struct niu *np)
5749 {
5750         int i;
5751
5752         for (i = 0; i < np->num_rx_rings; i++) {
5753                 struct rx_ring_info *rp = &np->rx_rings[i];
5754
5755                 niu_stop_one_rx_channel(np, rp);
5756         }
5757 }
5758
5759 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5760 {
5761         int channel = rp->rx_channel;
5762
5763         (void) niu_rx_channel_reset(np, channel);
5764         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5765         nw64(RX_DMA_CTL_STAT(channel), 0);
5766         (void) niu_enable_rx_channel(np, channel, 0);
5767 }
5768
5769 static void niu_reset_rx_channels(struct niu *np)
5770 {
5771         int i;
5772
5773         for (i = 0; i < np->num_rx_rings; i++) {
5774                 struct rx_ring_info *rp = &np->rx_rings[i];
5775
5776                 niu_reset_one_rx_channel(np, rp);
5777         }
5778 }
5779
5780 static void niu_disable_ipp(struct niu *np)
5781 {
5782         u64 rd, wr, val;
5783         int limit;
5784
5785         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5786         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5787         limit = 100;
5788         while (--limit >= 0 && (rd != wr)) {
5789                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5790                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5791         }
5792         if (limit < 0 &&
5793             (rd != 0 && wr != 1)) {
5794                 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5795                         "rd_ptr[%llx] wr_ptr[%llx]\n",
5796                         np->dev->name,
5797                         (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5798                         (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5799         }
5800
5801         val = nr64_ipp(IPP_CFIG);
5802         val &= ~(IPP_CFIG_IPP_ENABLE |
5803                  IPP_CFIG_DFIFO_ECC_EN |
5804                  IPP_CFIG_DROP_BAD_CRC |
5805                  IPP_CFIG_CKSUM_EN);
5806         nw64_ipp(IPP_CFIG, val);
5807
5808         (void) niu_ipp_reset(np);
5809 }
5810
5811 static int niu_init_hw(struct niu *np)
5812 {
5813         int i, err;
5814
5815         niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5816         niu_txc_enable_port(np, 1);
5817         niu_txc_port_dma_enable(np, 1);
5818         niu_txc_set_imask(np, 0);
5819
5820         niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5821         for (i = 0; i < np->num_tx_rings; i++) {
5822                 struct tx_ring_info *rp = &np->tx_rings[i];
5823
5824                 err = niu_init_one_tx_channel(np, rp);
5825                 if (err)
5826                         return err;
5827         }
5828
5829         niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
5830         err = niu_init_rx_channels(np);
5831         if (err)
5832                 goto out_uninit_tx_channels;
5833
5834         niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
5835         err = niu_init_classifier_hw(np);
5836         if (err)
5837                 goto out_uninit_rx_channels;
5838
5839         niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
5840         err = niu_init_zcp(np);
5841         if (err)
5842                 goto out_uninit_rx_channels;
5843
5844         niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
5845         err = niu_init_ipp(np);
5846         if (err)
5847                 goto out_uninit_rx_channels;
5848
5849         niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
5850         err = niu_init_mac(np);
5851         if (err)
5852                 goto out_uninit_ipp;
5853
5854         return 0;
5855
5856 out_uninit_ipp:
5857         niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
5858         niu_disable_ipp(np);
5859
5860 out_uninit_rx_channels:
5861         niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
5862         niu_stop_rx_channels(np);
5863         niu_reset_rx_channels(np);
5864
5865 out_uninit_tx_channels:
5866         niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
5867         niu_stop_tx_channels(np);
5868         niu_reset_tx_channels(np);
5869
5870         return err;
5871 }
5872
5873 static void niu_stop_hw(struct niu *np)
5874 {
5875         niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
5876         niu_enable_interrupts(np, 0);
5877
5878         niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
5879         niu_enable_rx_mac(np, 0);
5880
5881         niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
5882         niu_disable_ipp(np);
5883
5884         niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
5885         niu_stop_tx_channels(np);
5886
5887         niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
5888         niu_stop_rx_channels(np);
5889
5890         niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
5891         niu_reset_tx_channels(np);
5892
5893         niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
5894         niu_reset_rx_channels(np);
5895 }
5896
5897 static void niu_set_irq_name(struct niu *np)
5898 {
5899         int port = np->port;
5900         int i, j = 1;
5901
5902         sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
5903
5904         if (port == 0) {
5905                 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
5906                 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
5907                 j = 3;
5908         }
5909
5910         for (i = 0; i < np->num_ldg - j; i++) {
5911                 if (i < np->num_rx_rings)
5912                         sprintf(np->irq_name[i+j], "%s-rx-%d",
5913                                 np->dev->name, i);
5914                 else if (i < np->num_tx_rings + np->num_rx_rings)
5915                         sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
5916                                 i - np->num_rx_rings);
5917         }
5918 }
5919
5920 static int niu_request_irq(struct niu *np)
5921 {
5922         int i, j, err;
5923
5924         niu_set_irq_name(np);
5925
5926         err = 0;
5927         for (i = 0; i < np->num_ldg; i++) {
5928                 struct niu_ldg *lp = &np->ldg[i];
5929
5930                 err = request_irq(lp->irq, niu_interrupt,
5931                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
5932                                   np->irq_name[i], lp);
5933                 if (err)
5934                         goto out_free_irqs;
5935
5936         }
5937
5938         return 0;
5939
5940 out_free_irqs:
5941         for (j = 0; j < i; j++) {
5942                 struct niu_ldg *lp = &np->ldg[j];
5943
5944                 free_irq(lp->irq, lp);
5945         }
5946         return err;
5947 }
5948
5949 static void niu_free_irq(struct niu *np)
5950 {
5951         int i;
5952
5953         for (i = 0; i < np->num_ldg; i++) {
5954                 struct niu_ldg *lp = &np->ldg[i];
5955
5956                 free_irq(lp->irq, lp);
5957         }
5958 }
5959
5960 static void niu_enable_napi(struct niu *np)
5961 {
5962         int i;
5963
5964         for (i = 0; i < np->num_ldg; i++)
5965                 napi_enable(&np->ldg[i].napi);
5966 }
5967
5968 static void niu_disable_napi(struct niu *np)
5969 {
5970         int i;
5971
5972         for (i = 0; i < np->num_ldg; i++)
5973                 napi_disable(&np->ldg[i].napi);
5974 }
5975
5976 static int niu_open(struct net_device *dev)
5977 {
5978         struct niu *np = netdev_priv(dev);
5979         int err;
5980
5981         netif_carrier_off(dev);
5982
5983         err = niu_alloc_channels(np);
5984         if (err)
5985                 goto out_err;
5986
5987         err = niu_enable_interrupts(np, 0);
5988         if (err)
5989                 goto out_free_channels;
5990
5991         err = niu_request_irq(np);
5992         if (err)
5993                 goto out_free_channels;
5994
5995         niu_enable_napi(np);
5996
5997         spin_lock_irq(&np->lock);
5998
5999         err = niu_init_hw(np);
6000         if (!err) {
6001                 init_timer(&np->timer);
6002                 np->timer.expires = jiffies + HZ;
6003                 np->timer.data = (unsigned long) np;
6004                 np->timer.function = niu_timer;
6005
6006                 err = niu_enable_interrupts(np, 1);
6007                 if (err)
6008                         niu_stop_hw(np);
6009         }
6010
6011         spin_unlock_irq(&np->lock);
6012
6013         if (err) {
6014                 niu_disable_napi(np);
6015                 goto out_free_irq;
6016         }
6017
6018         netif_tx_start_all_queues(dev);
6019
6020         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6021                 netif_carrier_on(dev);
6022
6023         add_timer(&np->timer);
6024
6025         return 0;
6026
6027 out_free_irq:
6028         niu_free_irq(np);
6029
6030 out_free_channels:
6031         niu_free_channels(np);
6032
6033 out_err:
6034         return err;
6035 }
6036
6037 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6038 {
6039         cancel_work_sync(&np->reset_task);
6040
6041         niu_disable_napi(np);
6042         netif_tx_stop_all_queues(dev);
6043
6044         del_timer_sync(&np->timer);
6045
6046         spin_lock_irq(&np->lock);
6047
6048         niu_stop_hw(np);
6049
6050         spin_unlock_irq(&np->lock);
6051 }
6052
6053 static int niu_close(struct net_device *dev)
6054 {
6055         struct niu *np = netdev_priv(dev);
6056
6057         niu_full_shutdown(np, dev);
6058
6059         niu_free_irq(np);
6060
6061         niu_free_channels(np);
6062
6063         niu_handle_led(np, 0);
6064
6065         return 0;
6066 }
6067
6068 static void niu_sync_xmac_stats(struct niu *np)
6069 {
6070         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6071
6072         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6073         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6074
6075         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6076         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6077         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6078         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6079         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6080         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6081         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6082         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6083         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6084         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6085         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6086         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6087         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6088         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6089         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6090         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6091 }
6092
6093 static void niu_sync_bmac_stats(struct niu *np)
6094 {
6095         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6096
6097         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6098         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6099
6100         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6101         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6102         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6103         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6104 }
6105
6106 static void niu_sync_mac_stats(struct niu *np)
6107 {
6108         if (np->flags & NIU_FLAGS_XMAC)
6109                 niu_sync_xmac_stats(np);
6110         else
6111                 niu_sync_bmac_stats(np);
6112 }
6113
6114 static void niu_get_rx_stats(struct niu *np)
6115 {
6116         unsigned long pkts, dropped, errors, bytes;
6117         int i;
6118
6119         pkts = dropped = errors = bytes = 0;
6120         for (i = 0; i < np->num_rx_rings; i++) {
6121                 struct rx_ring_info *rp = &np->rx_rings[i];
6122
6123                 niu_sync_rx_discard_stats(np, rp, 0);
6124
6125                 pkts += rp->rx_packets;
6126                 bytes += rp->rx_bytes;
6127                 dropped += rp->rx_dropped;
6128                 errors += rp->rx_errors;
6129         }
6130         np->dev->stats.rx_packets = pkts;
6131         np->dev->stats.rx_bytes = bytes;
6132         np->dev->stats.rx_dropped = dropped;
6133         np->dev->stats.rx_errors = errors;
6134 }
6135
6136 static void niu_get_tx_stats(struct niu *np)
6137 {
6138         unsigned long pkts, errors, bytes;
6139         int i;
6140
6141         pkts = errors = bytes = 0;
6142         for (i = 0; i < np->num_tx_rings; i++) {
6143                 struct tx_ring_info *rp = &np->tx_rings[i];
6144
6145                 pkts += rp->tx_packets;
6146                 bytes += rp->tx_bytes;
6147                 errors += rp->tx_errors;
6148         }
6149         np->dev->stats.tx_packets = pkts;
6150         np->dev->stats.tx_bytes = bytes;
6151         np->dev->stats.tx_errors = errors;
6152 }
6153
6154 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6155 {
6156         struct niu *np = netdev_priv(dev);
6157
6158         niu_get_rx_stats(np);
6159         niu_get_tx_stats(np);
6160
6161         return &dev->stats;
6162 }
6163
6164 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6165 {
6166         int i;
6167
6168         for (i = 0; i < 16; i++)
6169                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6170 }
6171
6172 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6173 {
6174         int i;
6175
6176         for (i = 0; i < 16; i++)
6177                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6178 }
6179
6180 static void niu_load_hash(struct niu *np, u16 *hash)
6181 {
6182         if (np->flags & NIU_FLAGS_XMAC)
6183                 niu_load_hash_xmac(np, hash);
6184         else
6185                 niu_load_hash_bmac(np, hash);
6186 }
6187
6188 static void niu_set_rx_mode(struct net_device *dev)
6189 {
6190         struct niu *np = netdev_priv(dev);
6191         int i, alt_cnt, err;
6192         struct dev_addr_list *addr;
6193         unsigned long flags;
6194         u16 hash[16] = { 0, };
6195
6196         spin_lock_irqsave(&np->lock, flags);
6197         niu_enable_rx_mac(np, 0);
6198
6199         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6200         if (dev->flags & IFF_PROMISC)
6201                 np->flags |= NIU_FLAGS_PROMISC;
6202         if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
6203                 np->flags |= NIU_FLAGS_MCAST;
6204
6205         alt_cnt = dev->uc_count;
6206         if (alt_cnt > niu_num_alt_addr(np)) {
6207                 alt_cnt = 0;
6208                 np->flags |= NIU_FLAGS_PROMISC;
6209         }
6210
6211         if (alt_cnt) {
6212                 int index = 0;
6213
6214                 for (addr = dev->uc_list; addr; addr = addr->next) {
6215                         err = niu_set_alt_mac(np, index,
6216                                               addr->da_addr);
6217                         if (err)
6218                                 printk(KERN_WARNING PFX "%s: Error %d "
6219                                        "adding alt mac %d\n",
6220                                        dev->name, err, index);
6221                         err = niu_enable_alt_mac(np, index, 1);
6222                         if (err)
6223                                 printk(KERN_WARNING PFX "%s: Error %d "
6224                                        "enabling alt mac %d\n",
6225                                        dev->name, err, index);
6226
6227                         index++;
6228                 }
6229         } else {
6230                 int alt_start;
6231                 if (np->flags & NIU_FLAGS_XMAC)
6232                         alt_start = 0;
6233                 else
6234                         alt_start = 1;
6235                 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6236                         err = niu_enable_alt_mac(np, i, 0);
6237                         if (err)
6238                                 printk(KERN_WARNING PFX "%s: Error %d "
6239                                        "disabling alt mac %d\n",
6240                                        dev->name, err, i);
6241                 }
6242         }
6243         if (dev->flags & IFF_ALLMULTI) {
6244                 for (i = 0; i < 16; i++)
6245                         hash[i] = 0xffff;
6246         } else if (dev->mc_count > 0) {
6247                 for (addr = dev->mc_list; addr; addr = addr->next) {
6248                         u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
6249
6250                         crc >>= 24;
6251                         hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6252                 }
6253         }
6254
6255         if (np->flags & NIU_FLAGS_MCAST)
6256                 niu_load_hash(np, hash);
6257
6258         niu_enable_rx_mac(np, 1);
6259         spin_unlock_irqrestore(&np->lock, flags);
6260 }
6261
6262 static int niu_set_mac_addr(struct net_device *dev, void *p)
6263 {
6264         struct niu *np = netdev_priv(dev);
6265         struct sockaddr *addr = p;
6266         unsigned long flags;
6267
6268         if (!is_valid_ether_addr(addr->sa_data))
6269                 return -EINVAL;
6270
6271         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6272
6273         if (!netif_running(dev))
6274                 return 0;
6275
6276         spin_lock_irqsave(&np->lock, flags);
6277         niu_enable_rx_mac(np, 0);
6278         niu_set_primary_mac(np, dev->dev_addr);
6279         niu_enable_rx_mac(np, 1);
6280         spin_unlock_irqrestore(&np->lock, flags);
6281
6282         return 0;
6283 }
6284
6285 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6286 {
6287         return -EOPNOTSUPP;
6288 }
6289
6290 static void niu_netif_stop(struct niu *np)
6291 {
6292         np->dev->trans_start = jiffies; /* prevent tx timeout */
6293
6294         niu_disable_napi(np);
6295
6296         netif_tx_disable(np->dev);
6297 }
6298
6299 static void niu_netif_start(struct niu *np)
6300 {
6301         /* NOTE: unconditional netif_wake_queue is only appropriate
6302          * so long as all callers are assured to have free tx slots
6303          * (such as after niu_init_hw).
6304          */
6305         netif_tx_wake_all_queues(np->dev);
6306
6307         niu_enable_napi(np);
6308
6309         niu_enable_interrupts(np, 1);
6310 }
6311
6312 static void niu_reset_buffers(struct niu *np)
6313 {
6314         int i, j, k, err;
6315
6316         if (np->rx_rings) {
6317                 for (i = 0; i < np->num_rx_rings; i++) {
6318                         struct rx_ring_info *rp = &np->rx_rings[i];
6319
6320                         for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6321                                 struct page *page;
6322
6323                                 page = rp->rxhash[j];
6324                                 while (page) {
6325                                         struct page *next =
6326                                                 (struct page *) page->mapping;
6327                                         u64 base = page->index;
6328                                         base = base >> RBR_DESCR_ADDR_SHIFT;
6329                                         rp->rbr[k++] = cpu_to_le32(base);
6330                                         page = next;
6331                                 }
6332                         }
6333                         for (; k < MAX_RBR_RING_SIZE; k++) {
6334                                 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6335                                 if (unlikely(err))
6336                                         break;
6337                         }
6338
6339                         rp->rbr_index = rp->rbr_table_size - 1;
6340                         rp->rcr_index = 0;
6341                         rp->rbr_pending = 0;
6342                         rp->rbr_refill_pending = 0;
6343                 }
6344         }
6345         if (np->tx_rings) {
6346                 for (i = 0; i < np->num_tx_rings; i++) {
6347                         struct tx_ring_info *rp = &np->tx_rings[i];
6348
6349                         for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6350                                 if (rp->tx_buffs[j].skb)
6351                                         (void) release_tx_packet(np, rp, j);
6352                         }
6353
6354                         rp->pending = MAX_TX_RING_SIZE;
6355                         rp->prod = 0;
6356                         rp->cons = 0;
6357                         rp->wrap_bit = 0;
6358                 }
6359         }
6360 }
6361
6362 static void niu_reset_task(struct work_struct *work)
6363 {
6364         struct niu *np = container_of(work, struct niu, reset_task);
6365         unsigned long flags;
6366         int err;
6367
6368         spin_lock_irqsave(&np->lock, flags);
6369         if (!netif_running(np->dev)) {
6370                 spin_unlock_irqrestore(&np->lock, flags);
6371                 return;
6372         }
6373
6374         spin_unlock_irqrestore(&np->lock, flags);
6375
6376         del_timer_sync(&np->timer);
6377
6378         niu_netif_stop(np);
6379
6380         spin_lock_irqsave(&np->lock, flags);
6381
6382         niu_stop_hw(np);
6383
6384         spin_unlock_irqrestore(&np->lock, flags);
6385
6386         niu_reset_buffers(np);
6387
6388         spin_lock_irqsave(&np->lock, flags);
6389
6390         err = niu_init_hw(np);
6391         if (!err) {
6392                 np->timer.expires = jiffies + HZ;
6393                 add_timer(&np->timer);
6394                 niu_netif_start(np);
6395         }
6396
6397         spin_unlock_irqrestore(&np->lock, flags);
6398 }
6399
6400 static void niu_tx_timeout(struct net_device *dev)
6401 {
6402         struct niu *np = netdev_priv(dev);
6403
6404         dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
6405                 dev->name);
6406
6407         schedule_work(&np->reset_task);
6408 }
6409
6410 static void niu_set_txd(struct tx_ring_info *rp, int index,
6411                         u64 mapping, u64 len, u64 mark,
6412                         u64 n_frags)
6413 {
6414         __le64 *desc = &rp->descr[index];
6415
6416         *desc = cpu_to_le64(mark |
6417                             (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6418                             (len << TX_DESC_TR_LEN_SHIFT) |
6419                             (mapping & TX_DESC_SAD));
6420 }
6421
6422 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6423                                 u64 pad_bytes, u64 len)
6424 {
6425         u16 eth_proto, eth_proto_inner;
6426         u64 csum_bits, l3off, ihl, ret;
6427         u8 ip_proto;
6428         int ipv6;
6429
6430         eth_proto = be16_to_cpu(ehdr->h_proto);
6431         eth_proto_inner = eth_proto;
6432         if (eth_proto == ETH_P_8021Q) {
6433                 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6434                 __be16 val = vp->h_vlan_encapsulated_proto;
6435
6436                 eth_proto_inner = be16_to_cpu(val);
6437         }
6438
6439         ipv6 = ihl = 0;
6440         switch (skb->protocol) {
6441         case __constant_htons(ETH_P_IP):
6442                 ip_proto = ip_hdr(skb)->protocol;
6443                 ihl = ip_hdr(skb)->ihl;
6444                 break;
6445         case __constant_htons(ETH_P_IPV6):
6446                 ip_proto = ipv6_hdr(skb)->nexthdr;
6447                 ihl = (40 >> 2);
6448                 ipv6 = 1;
6449                 break;
6450         default:
6451                 ip_proto = ihl = 0;
6452                 break;
6453         }
6454
6455         csum_bits = TXHDR_CSUM_NONE;
6456         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6457                 u64 start, stuff;
6458
6459                 csum_bits = (ip_proto == IPPROTO_TCP ?
6460                              TXHDR_CSUM_TCP :
6461                              (ip_proto == IPPROTO_UDP ?
6462                               TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6463
6464                 start = skb_transport_offset(skb) -
6465                         (pad_bytes + sizeof(struct tx_pkt_hdr));
6466                 stuff = start + skb->csum_offset;
6467
6468                 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6469                 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6470         }
6471
6472         l3off = skb_network_offset(skb) -
6473                 (pad_bytes + sizeof(struct tx_pkt_hdr));
6474
6475         ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6476                (len << TXHDR_LEN_SHIFT) |
6477                ((l3off / 2) << TXHDR_L3START_SHIFT) |
6478                (ihl << TXHDR_IHL_SHIFT) |
6479                ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6480                ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6481                (ipv6 ? TXHDR_IP_VER : 0) |
6482                csum_bits);
6483
6484         return ret;
6485 }
6486
6487 static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6488 {
6489         struct niu *np = netdev_priv(dev);
6490         unsigned long align, headroom;
6491         struct netdev_queue *txq;
6492         struct tx_ring_info *rp;
6493         struct tx_pkt_hdr *tp;
6494         unsigned int len, nfg;
6495         struct ethhdr *ehdr;
6496         int prod, i, tlen;
6497         u64 mapping, mrk;
6498
6499         i = skb_get_queue_mapping(skb);
6500         rp = &np->tx_rings[i];
6501         txq = netdev_get_tx_queue(dev, i);
6502
6503         if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6504                 netif_tx_stop_queue(txq);
6505                 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
6506                         "queue awake!\n", dev->name);
6507                 rp->tx_errors++;
6508                 return NETDEV_TX_BUSY;
6509         }
6510
6511         if (skb->len < ETH_ZLEN) {
6512                 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6513
6514                 if (skb_pad(skb, pad_bytes))
6515                         goto out;
6516                 skb_put(skb, pad_bytes);
6517         }
6518
6519         len = sizeof(struct tx_pkt_hdr) + 15;
6520         if (skb_headroom(skb) < len) {
6521                 struct sk_buff *skb_new;
6522
6523                 skb_new = skb_realloc_headroom(skb, len);
6524                 if (!skb_new) {
6525                         rp->tx_errors++;
6526                         goto out_drop;
6527                 }
6528                 kfree_skb(skb);
6529                 skb = skb_new;
6530         } else
6531                 skb_orphan(skb);
6532
6533         align = ((unsigned long) skb->data & (16 - 1));
6534         headroom = align + sizeof(struct tx_pkt_hdr);
6535
6536         ehdr = (struct ethhdr *) skb->data;
6537         tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6538
6539         len = skb->len - sizeof(struct tx_pkt_hdr);
6540         tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6541         tp->resv = 0;
6542
6543         len = skb_headlen(skb);
6544         mapping = np->ops->map_single(np->device, skb->data,
6545                                       len, DMA_TO_DEVICE);
6546
6547         prod = rp->prod;
6548
6549         rp->tx_buffs[prod].skb = skb;
6550         rp->tx_buffs[prod].mapping = mapping;
6551
6552         mrk = TX_DESC_SOP;
6553         if (++rp->mark_counter == rp->mark_freq) {
6554                 rp->mark_counter = 0;
6555                 mrk |= TX_DESC_MARK;
6556                 rp->mark_pending++;
6557         }
6558
6559         tlen = len;
6560         nfg = skb_shinfo(skb)->nr_frags;
6561         while (tlen > 0) {
6562                 tlen -= MAX_TX_DESC_LEN;
6563                 nfg++;
6564         }
6565
6566         while (len > 0) {
6567                 unsigned int this_len = len;
6568
6569                 if (this_len > MAX_TX_DESC_LEN)
6570                         this_len = MAX_TX_DESC_LEN;
6571
6572                 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6573                 mrk = nfg = 0;
6574
6575                 prod = NEXT_TX(rp, prod);
6576                 mapping += this_len;
6577                 len -= this_len;
6578         }
6579
6580         for (i = 0; i <  skb_shinfo(skb)->nr_frags; i++) {
6581                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6582
6583                 len = frag->size;
6584                 mapping = np->ops->map_page(np->device, frag->page,
6585                                             frag->page_offset, len,
6586                                             DMA_TO_DEVICE);
6587
6588                 rp->tx_buffs[prod].skb = NULL;
6589                 rp->tx_buffs[prod].mapping = mapping;
6590
6591                 niu_set_txd(rp, prod, mapping, len, 0, 0);
6592
6593                 prod = NEXT_TX(rp, prod);
6594         }
6595
6596         if (prod < rp->prod)
6597                 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6598         rp->prod = prod;
6599
6600         nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6601
6602         if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6603                 netif_tx_stop_queue(txq);
6604                 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6605                         netif_tx_wake_queue(txq);
6606         }
6607
6608         dev->trans_start = jiffies;
6609
6610 out:
6611         return NETDEV_TX_OK;
6612
6613 out_drop:
6614         rp->tx_errors++;
6615         kfree_skb(skb);
6616         goto out;
6617 }
6618
6619 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6620 {
6621         struct niu *np = netdev_priv(dev);
6622         int err, orig_jumbo, new_jumbo;
6623
6624         if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6625                 return -EINVAL;
6626
6627         orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6628         new_jumbo = (new_mtu > ETH_DATA_LEN);
6629
6630         dev->mtu = new_mtu;
6631
6632         if (!netif_running(dev) ||
6633             (orig_jumbo == new_jumbo))
6634                 return 0;
6635
6636         niu_full_shutdown(np, dev);
6637
6638         niu_free_channels(np);
6639
6640         niu_enable_napi(np);
6641
6642         err = niu_alloc_channels(np);
6643         if (err)
6644                 return err;
6645
6646         spin_lock_irq(&np->lock);
6647
6648         err = niu_init_hw(np);
6649         if (!err) {
6650                 init_timer(&np->timer);
6651                 np->timer.expires = jiffies + HZ;
6652                 np->timer.data = (unsigned long) np;
6653                 np->timer.function = niu_timer;
6654
6655                 err = niu_enable_interrupts(np, 1);
6656                 if (err)
6657                         niu_stop_hw(np);
6658         }
6659
6660         spin_unlock_irq(&np->lock);
6661
6662         if (!err) {
6663                 netif_tx_start_all_queues(dev);
6664                 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6665                         netif_carrier_on(dev);
6666
6667                 add_timer(&np->timer);
6668         }
6669
6670         return err;
6671 }
6672
6673 static void niu_get_drvinfo(struct net_device *dev,
6674                             struct ethtool_drvinfo *info)
6675 {
6676         struct niu *np = netdev_priv(dev);
6677         struct niu_vpd *vpd = &np->vpd;
6678
6679         strcpy(info->driver, DRV_MODULE_NAME);
6680         strcpy(info->version, DRV_MODULE_VERSION);
6681         sprintf(info->fw_version, "%d.%d",
6682                 vpd->fcode_major, vpd->fcode_minor);
6683         if (np->parent->plat_type != PLAT_TYPE_NIU)
6684                 strcpy(info->bus_info, pci_name(np->pdev));
6685 }
6686
6687 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6688 {
6689         struct niu *np = netdev_priv(dev);
6690         struct niu_link_config *lp;
6691
6692         lp = &np->link_config;
6693
6694         memset(cmd, 0, sizeof(*cmd));
6695         cmd->phy_address = np->phy_addr;
6696         cmd->supported = lp->supported;
6697         cmd->advertising = lp->advertising;
6698         cmd->autoneg = lp->autoneg;
6699         cmd->speed = lp->active_speed;
6700         cmd->duplex = lp->active_duplex;
6701
6702         return 0;
6703 }
6704
6705 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6706 {
6707         return -EINVAL;
6708 }
6709
6710 static u32 niu_get_msglevel(struct net_device *dev)
6711 {
6712         struct niu *np = netdev_priv(dev);
6713         return np->msg_enable;
6714 }
6715
6716 static void niu_set_msglevel(struct net_device *dev, u32 value)
6717 {
6718         struct niu *np = netdev_priv(dev);
6719         np->msg_enable = value;
6720 }
6721
6722 static int niu_get_eeprom_len(struct net_device *dev)
6723 {
6724         struct niu *np = netdev_priv(dev);
6725
6726         return np->eeprom_len;
6727 }
6728
6729 static int niu_get_eeprom(struct net_device *dev,
6730                           struct ethtool_eeprom *eeprom, u8 *data)
6731 {
6732         struct niu *np = netdev_priv(dev);
6733         u32 offset, len, val;
6734
6735         offset = eeprom->offset;
6736         len = eeprom->len;
6737
6738         if (offset + len < offset)
6739                 return -EINVAL;
6740         if (offset >= np->eeprom_len)
6741                 return -EINVAL;
6742         if (offset + len > np->eeprom_len)
6743                 len = eeprom->len = np->eeprom_len - offset;
6744
6745         if (offset & 3) {
6746                 u32 b_offset, b_count;
6747
6748                 b_offset = offset & 3;
6749                 b_count = 4 - b_offset;
6750                 if (b_count > len)
6751                         b_count = len;
6752
6753                 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6754                 memcpy(data, ((char *)&val) + b_offset, b_count);
6755                 data += b_count;
6756                 len -= b_count;
6757                 offset += b_count;
6758         }
6759         while (len >= 4) {
6760                 val = nr64(ESPC_NCR(offset / 4));
6761                 memcpy(data, &val, 4);
6762                 data += 4;
6763                 len -= 4;
6764                 offset += 4;
6765         }
6766         if (len) {
6767                 val = nr64(ESPC_NCR(offset / 4));
6768                 memcpy(data, &val, len);
6769         }
6770         return 0;
6771 }
6772
6773 static int niu_ethflow_to_class(int flow_type, u64 *class)
6774 {
6775         switch (flow_type) {
6776         case TCP_V4_FLOW:
6777                 *class = CLASS_CODE_TCP_IPV4;
6778                 break;
6779         case UDP_V4_FLOW:
6780                 *class = CLASS_CODE_UDP_IPV4;
6781                 break;
6782         case AH_ESP_V4_FLOW:
6783                 *class = CLASS_CODE_AH_ESP_IPV4;
6784                 break;
6785         case SCTP_V4_FLOW:
6786                 *class = CLASS_CODE_SCTP_IPV4;
6787                 break;
6788         case TCP_V6_FLOW:
6789                 *class = CLASS_CODE_TCP_IPV6;
6790                 break;
6791         case UDP_V6_FLOW:
6792                 *class = CLASS_CODE_UDP_IPV6;
6793                 break;
6794         case AH_ESP_V6_FLOW:
6795                 *class = CLASS_CODE_AH_ESP_IPV6;
6796                 break;
6797         case SCTP_V6_FLOW:
6798                 *class = CLASS_CODE_SCTP_IPV6;
6799                 break;
6800         default:
6801                 return 0;
6802         }
6803
6804         return 1;
6805 }
6806
6807 static u64 niu_flowkey_to_ethflow(u64 flow_key)
6808 {
6809         u64 ethflow = 0;
6810
6811         if (flow_key & FLOW_KEY_PORT)
6812                 ethflow |= RXH_DEV_PORT;
6813         if (flow_key & FLOW_KEY_L2DA)
6814                 ethflow |= RXH_L2DA;
6815         if (flow_key & FLOW_KEY_VLAN)
6816                 ethflow |= RXH_VLAN;
6817         if (flow_key & FLOW_KEY_IPSA)
6818                 ethflow |= RXH_IP_SRC;
6819         if (flow_key & FLOW_KEY_IPDA)
6820                 ethflow |= RXH_IP_DST;
6821         if (flow_key & FLOW_KEY_PROTO)
6822                 ethflow |= RXH_L3_PROTO;
6823         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
6824                 ethflow |= RXH_L4_B_0_1;
6825         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
6826                 ethflow |= RXH_L4_B_2_3;
6827
6828         return ethflow;
6829
6830 }
6831
6832 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
6833 {
6834         u64 key = 0;
6835
6836         if (ethflow & RXH_DEV_PORT)
6837                 key |= FLOW_KEY_PORT;
6838         if (ethflow & RXH_L2DA)
6839                 key |= FLOW_KEY_L2DA;
6840         if (ethflow & RXH_VLAN)
6841                 key |= FLOW_KEY_VLAN;
6842         if (ethflow & RXH_IP_SRC)
6843                 key |= FLOW_KEY_IPSA;
6844         if (ethflow & RXH_IP_DST)
6845                 key |= FLOW_KEY_IPDA;
6846         if (ethflow & RXH_L3_PROTO)
6847                 key |= FLOW_KEY_PROTO;
6848         if (ethflow & RXH_L4_B_0_1)
6849                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
6850         if (ethflow & RXH_L4_B_2_3)
6851                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
6852
6853         *flow_key = key;
6854
6855         return 1;
6856
6857 }
6858
6859 static int niu_get_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
6860 {
6861         struct niu *np = netdev_priv(dev);
6862         u64 class;
6863
6864         cmd->data = 0;
6865
6866         if (!niu_ethflow_to_class(cmd->flow_type, &class))
6867                 return -EINVAL;
6868
6869         if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
6870             TCAM_KEY_DISC)
6871                 cmd->data = RXH_DISCARD;
6872         else
6873
6874                 cmd->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
6875                                                       CLASS_CODE_USER_PROG1]);
6876         return 0;
6877 }
6878
6879 static int niu_set_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
6880 {
6881         struct niu *np = netdev_priv(dev);
6882         u64 class;
6883         u64 flow_key = 0;
6884         unsigned long flags;
6885
6886         if (!niu_ethflow_to_class(cmd->flow_type, &class))
6887                 return -EINVAL;
6888
6889         if (class < CLASS_CODE_USER_PROG1 ||
6890             class > CLASS_CODE_SCTP_IPV6)
6891                 return -EINVAL;
6892
6893         if (cmd->data & RXH_DISCARD) {
6894                 niu_lock_parent(np, flags);
6895                 flow_key = np->parent->tcam_key[class -
6896                                                CLASS_CODE_USER_PROG1];
6897                 flow_key |= TCAM_KEY_DISC;
6898                 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
6899                 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
6900                 niu_unlock_parent(np, flags);
6901                 return 0;
6902         } else {
6903                 /* Discard was set before, but is not set now */
6904                 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
6905                     TCAM_KEY_DISC) {
6906                         niu_lock_parent(np, flags);
6907                         flow_key = np->parent->tcam_key[class -
6908                                                CLASS_CODE_USER_PROG1];
6909                         flow_key &= ~TCAM_KEY_DISC;
6910                         nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
6911                              flow_key);
6912                         np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
6913                                 flow_key;
6914                         niu_unlock_parent(np, flags);
6915                 }
6916         }
6917
6918         if (!niu_ethflow_to_flowkey(cmd->data, &flow_key))
6919                 return -EINVAL;
6920
6921         niu_lock_parent(np, flags);
6922         nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
6923         np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
6924         niu_unlock_parent(np, flags);
6925
6926         return 0;
6927 }
6928
6929 static const struct {
6930         const char string[ETH_GSTRING_LEN];
6931 } niu_xmac_stat_keys[] = {
6932         { "tx_frames" },
6933         { "tx_bytes" },
6934         { "tx_fifo_errors" },
6935         { "tx_overflow_errors" },
6936         { "tx_max_pkt_size_errors" },
6937         { "tx_underflow_errors" },
6938         { "rx_local_faults" },
6939         { "rx_remote_faults" },
6940         { "rx_link_faults" },
6941         { "rx_align_errors" },
6942         { "rx_frags" },
6943         { "rx_mcasts" },
6944         { "rx_bcasts" },
6945         { "rx_hist_cnt1" },
6946         { "rx_hist_cnt2" },
6947         { "rx_hist_cnt3" },
6948         { "rx_hist_cnt4" },
6949         { "rx_hist_cnt5" },
6950         { "rx_hist_cnt6" },
6951         { "rx_hist_cnt7" },
6952         { "rx_octets" },
6953         { "rx_code_violations" },
6954         { "rx_len_errors" },
6955         { "rx_crc_errors" },
6956         { "rx_underflows" },
6957         { "rx_overflows" },
6958         { "pause_off_state" },
6959         { "pause_on_state" },
6960         { "pause_received" },
6961 };
6962
6963 #define NUM_XMAC_STAT_KEYS      ARRAY_SIZE(niu_xmac_stat_keys)
6964
6965 static const struct {
6966         const char string[ETH_GSTRING_LEN];
6967 } niu_bmac_stat_keys[] = {
6968         { "tx_underflow_errors" },
6969         { "tx_max_pkt_size_errors" },
6970         { "tx_bytes" },
6971         { "tx_frames" },
6972         { "rx_overflows" },
6973         { "rx_frames" },
6974         { "rx_align_errors" },
6975         { "rx_crc_errors" },
6976         { "rx_len_errors" },
6977         { "pause_off_state" },
6978         { "pause_on_state" },
6979         { "pause_received" },
6980 };
6981
6982 #define NUM_BMAC_STAT_KEYS      ARRAY_SIZE(niu_bmac_stat_keys)
6983
6984 static const struct {
6985         const char string[ETH_GSTRING_LEN];
6986 } niu_rxchan_stat_keys[] = {
6987         { "rx_channel" },
6988         { "rx_packets" },
6989         { "rx_bytes" },
6990         { "rx_dropped" },
6991         { "rx_errors" },
6992 };
6993
6994 #define NUM_RXCHAN_STAT_KEYS    ARRAY_SIZE(niu_rxchan_stat_keys)
6995
6996 static const struct {
6997         const char string[ETH_GSTRING_LEN];
6998 } niu_txchan_stat_keys[] = {
6999         { "tx_channel" },
7000         { "tx_packets" },
7001         { "tx_bytes" },
7002         { "tx_errors" },
7003 };
7004
7005 #define NUM_TXCHAN_STAT_KEYS    ARRAY_SIZE(niu_txchan_stat_keys)
7006
7007 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7008 {
7009         struct niu *np = netdev_priv(dev);
7010         int i;
7011
7012         if (stringset != ETH_SS_STATS)
7013                 return;
7014
7015         if (np->flags & NIU_FLAGS_XMAC) {
7016                 memcpy(data, niu_xmac_stat_keys,
7017                        sizeof(niu_xmac_stat_keys));
7018                 data += sizeof(niu_xmac_stat_keys);
7019         } else {
7020                 memcpy(data, niu_bmac_stat_keys,
7021                        sizeof(niu_bmac_stat_keys));
7022                 data += sizeof(niu_bmac_stat_keys);
7023         }
7024         for (i = 0; i < np->num_rx_rings; i++) {
7025                 memcpy(data, niu_rxchan_stat_keys,
7026                        sizeof(niu_rxchan_stat_keys));
7027                 data += sizeof(niu_rxchan_stat_keys);
7028         }
7029         for (i = 0; i < np->num_tx_rings; i++) {
7030                 memcpy(data, niu_txchan_stat_keys,
7031                        sizeof(niu_txchan_stat_keys));
7032                 data += sizeof(niu_txchan_stat_keys);
7033         }
7034 }
7035
7036 static int niu_get_stats_count(struct net_device *dev)
7037 {
7038         struct niu *np = netdev_priv(dev);
7039
7040         return ((np->flags & NIU_FLAGS_XMAC ?
7041                  NUM_XMAC_STAT_KEYS :
7042                  NUM_BMAC_STAT_KEYS) +
7043                 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7044                 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7045 }
7046
7047 static void niu_get_ethtool_stats(struct net_device *dev,
7048                                   struct ethtool_stats *stats, u64 *data)
7049 {
7050         struct niu *np = netdev_priv(dev);
7051         int i;
7052
7053         niu_sync_mac_stats(np);
7054         if (np->flags & NIU_FLAGS_XMAC) {
7055                 memcpy(data, &np->mac_stats.xmac,
7056                        sizeof(struct niu_xmac_stats));
7057                 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7058         } else {
7059                 memcpy(data, &np->mac_stats.bmac,
7060                        sizeof(struct niu_bmac_stats));
7061                 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7062         }
7063         for (i = 0; i < np->num_rx_rings; i++) {
7064                 struct rx_ring_info *rp = &np->rx_rings[i];
7065
7066                 niu_sync_rx_discard_stats(np, rp, 0);
7067
7068                 data[0] = rp->rx_channel;
7069                 data[1] = rp->rx_packets;
7070                 data[2] = rp->rx_bytes;
7071                 data[3] = rp->rx_dropped;
7072                 data[4] = rp->rx_errors;
7073                 data += 5;
7074         }
7075         for (i = 0; i < np->num_tx_rings; i++) {
7076                 struct tx_ring_info *rp = &np->tx_rings[i];
7077
7078                 data[0] = rp->tx_channel;
7079                 data[1] = rp->tx_packets;
7080                 data[2] = rp->tx_bytes;
7081                 data[3] = rp->tx_errors;
7082                 data += 4;
7083         }
7084 }
7085
7086 static u64 niu_led_state_save(struct niu *np)
7087 {
7088         if (np->flags & NIU_FLAGS_XMAC)
7089                 return nr64_mac(XMAC_CONFIG);
7090         else
7091                 return nr64_mac(BMAC_XIF_CONFIG);
7092 }
7093
7094 static void niu_led_state_restore(struct niu *np, u64 val)
7095 {
7096         if (np->flags & NIU_FLAGS_XMAC)
7097                 nw64_mac(XMAC_CONFIG, val);
7098         else
7099                 nw64_mac(BMAC_XIF_CONFIG, val);
7100 }
7101
7102 static void niu_force_led(struct niu *np, int on)
7103 {
7104         u64 val, reg, bit;
7105
7106         if (np->flags & NIU_FLAGS_XMAC) {
7107                 reg = XMAC_CONFIG;
7108                 bit = XMAC_CONFIG_FORCE_LED_ON;
7109         } else {
7110                 reg = BMAC_XIF_CONFIG;
7111                 bit = BMAC_XIF_CONFIG_LINK_LED;
7112         }
7113
7114         val = nr64_mac(reg);
7115         if (on)
7116                 val |= bit;
7117         else
7118                 val &= ~bit;
7119         nw64_mac(reg, val);
7120 }
7121
7122 static int niu_phys_id(struct net_device *dev, u32 data)
7123 {
7124         struct niu *np = netdev_priv(dev);
7125         u64 orig_led_state;
7126         int i;
7127
7128         if (!netif_running(dev))
7129                 return -EAGAIN;
7130
7131         if (data == 0)
7132                 data = 2;
7133
7134         orig_led_state = niu_led_state_save(np);
7135         for (i = 0; i < (data * 2); i++) {
7136                 int on = ((i % 2) == 0);
7137
7138                 niu_force_led(np, on);
7139
7140                 if (msleep_interruptible(500))
7141                         break;
7142         }
7143         niu_led_state_restore(np, orig_led_state);
7144
7145         return 0;
7146 }
7147
7148 static const struct ethtool_ops niu_ethtool_ops = {
7149         .get_drvinfo            = niu_get_drvinfo,
7150         .get_link               = ethtool_op_get_link,
7151         .get_msglevel           = niu_get_msglevel,
7152         .set_msglevel           = niu_set_msglevel,
7153         .get_eeprom_len         = niu_get_eeprom_len,
7154         .get_eeprom             = niu_get_eeprom,
7155         .get_settings           = niu_get_settings,
7156         .set_settings           = niu_set_settings,
7157         .get_strings            = niu_get_strings,
7158         .get_stats_count        = niu_get_stats_count,
7159         .get_ethtool_stats      = niu_get_ethtool_stats,
7160         .phys_id                = niu_phys_id,
7161         .get_rxhash             = niu_get_hash_opts,
7162         .set_rxhash             = niu_set_hash_opts,
7163 };
7164
7165 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7166                               int ldg, int ldn)
7167 {
7168         if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7169                 return -EINVAL;
7170         if (ldn < 0 || ldn > LDN_MAX)
7171                 return -EINVAL;
7172
7173         parent->ldg_map[ldn] = ldg;
7174
7175         if (np->parent->plat_type == PLAT_TYPE_NIU) {
7176                 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7177                  * the firmware, and we're not supposed to change them.
7178                  * Validate the mapping, because if it's wrong we probably
7179                  * won't get any interrupts and that's painful to debug.
7180                  */
7181                 if (nr64(LDG_NUM(ldn)) != ldg) {
7182                         dev_err(np->device, PFX "Port %u, mis-matched "
7183                                 "LDG assignment "
7184                                 "for ldn %d, should be %d is %llu\n",
7185                                 np->port, ldn, ldg,
7186                                 (unsigned long long) nr64(LDG_NUM(ldn)));
7187                         return -EINVAL;
7188                 }
7189         } else
7190                 nw64(LDG_NUM(ldn), ldg);
7191
7192         return 0;
7193 }
7194
7195 static int niu_set_ldg_timer_res(struct niu *np, int res)
7196 {
7197         if (res < 0 || res > LDG_TIMER_RES_VAL)
7198                 return -EINVAL;
7199
7200
7201         nw64(LDG_TIMER_RES, res);
7202
7203         return 0;
7204 }
7205
7206 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7207 {
7208         if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7209             (func < 0 || func > 3) ||
7210             (vector < 0 || vector > 0x1f))
7211                 return -EINVAL;
7212
7213         nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7214
7215         return 0;
7216 }
7217
7218 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7219 {
7220         u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7221                                  (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7222         int limit;
7223
7224         if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7225                 return -EINVAL;
7226
7227         frame = frame_base;
7228         nw64(ESPC_PIO_STAT, frame);
7229         limit = 64;
7230         do {
7231                 udelay(5);
7232                 frame = nr64(ESPC_PIO_STAT);
7233                 if (frame & ESPC_PIO_STAT_READ_END)
7234                         break;
7235         } while (limit--);
7236         if (!(frame & ESPC_PIO_STAT_READ_END)) {
7237                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
7238                         (unsigned long long) frame);
7239                 return -ENODEV;
7240         }
7241
7242         frame = frame_base;
7243         nw64(ESPC_PIO_STAT, frame);
7244         limit = 64;
7245         do {
7246                 udelay(5);
7247                 frame = nr64(ESPC_PIO_STAT);
7248                 if (frame & ESPC_PIO_STAT_READ_END)
7249                         break;
7250         } while (limit--);
7251         if (!(frame & ESPC_PIO_STAT_READ_END)) {
7252                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
7253                         (unsigned long long) frame);
7254                 return -ENODEV;
7255         }
7256
7257         frame = nr64(ESPC_PIO_STAT);
7258         return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
7259 }
7260
7261 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
7262 {
7263         int err = niu_pci_eeprom_read(np, off);
7264         u16 val;
7265
7266         if (err < 0)
7267                 return err;
7268         val = (err << 8);
7269         err = niu_pci_eeprom_read(np, off + 1);
7270         if (err < 0)
7271                 return err;
7272         val |= (err & 0xff);
7273
7274         return val;
7275 }
7276
7277 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
7278 {
7279         int err = niu_pci_eeprom_read(np, off);
7280         u16 val;
7281
7282         if (err < 0)
7283                 return err;
7284
7285         val = (err & 0xff);
7286         err = niu_pci_eeprom_read(np, off + 1);
7287         if (err < 0)
7288                 return err;
7289
7290         val |= (err & 0xff) << 8;
7291
7292         return val;
7293 }
7294
7295 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
7296                                               u32 off,
7297                                               char *namebuf,
7298                                               int namebuf_len)
7299 {
7300         int i;
7301
7302         for (i = 0; i < namebuf_len; i++) {
7303                 int err = niu_pci_eeprom_read(np, off + i);
7304                 if (err < 0)
7305                         return err;
7306                 *namebuf++ = err;
7307                 if (!err)
7308                         break;
7309         }
7310         if (i >= namebuf_len)
7311                 return -EINVAL;
7312
7313         return i + 1;
7314 }
7315
7316 static void __devinit niu_vpd_parse_version(struct niu *np)
7317 {
7318         struct niu_vpd *vpd = &np->vpd;
7319         int len = strlen(vpd->version) + 1;
7320         const char *s = vpd->version;
7321         int i;
7322
7323         for (i = 0; i < len - 5; i++) {
7324                 if (!strncmp(s + i, "FCode ", 5))
7325                         break;
7326         }
7327         if (i >= len - 5)
7328                 return;
7329
7330         s += i + 5;
7331         sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
7332
7333         niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
7334                vpd->fcode_major, vpd->fcode_minor);
7335         if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
7336             (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
7337              vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
7338                 np->flags |= NIU_FLAGS_VPD_VALID;
7339 }
7340
7341 /* ESPC_PIO_EN_ENABLE must be set */
7342 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
7343                                             u32 start, u32 end)
7344 {
7345         unsigned int found_mask = 0;
7346 #define FOUND_MASK_MODEL        0x00000001
7347 #define FOUND_MASK_BMODEL       0x00000002
7348 #define FOUND_MASK_VERS         0x00000004
7349 #define FOUND_MASK_MAC          0x00000008
7350 #define FOUND_MASK_NMAC         0x00000010
7351 #define FOUND_MASK_PHY          0x00000020
7352 #define FOUND_MASK_ALL          0x0000003f
7353
7354         niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
7355                start, end);
7356         while (start < end) {
7357                 int len, err, instance, type, prop_len;
7358                 char namebuf[64];
7359                 u8 *prop_buf;
7360                 int max_len;
7361
7362                 if (found_mask == FOUND_MASK_ALL) {
7363                         niu_vpd_parse_version(np);
7364                         return 1;
7365                 }
7366
7367                 err = niu_pci_eeprom_read(np, start + 2);
7368                 if (err < 0)
7369                         return err;
7370                 len = err;
7371                 start += 3;
7372
7373                 instance = niu_pci_eeprom_read(np, start);
7374                 type = niu_pci_eeprom_read(np, start + 3);
7375                 prop_len = niu_pci_eeprom_read(np, start + 4);
7376                 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
7377                 if (err < 0)
7378                         return err;
7379
7380                 prop_buf = NULL;
7381                 max_len = 0;
7382                 if (!strcmp(namebuf, "model")) {
7383                         prop_buf = np->vpd.model;
7384                         max_len = NIU_VPD_MODEL_MAX;
7385                         found_mask |= FOUND_MASK_MODEL;
7386                 } else if (!strcmp(namebuf, "board-model")) {
7387                         prop_buf = np->vpd.board_model;
7388                         max_len = NIU_VPD_BD_MODEL_MAX;
7389                         found_mask |= FOUND_MASK_BMODEL;
7390                 } else if (!strcmp(namebuf, "version")) {
7391                         prop_buf = np->vpd.version;
7392                         max_len = NIU_VPD_VERSION_MAX;
7393                         found_mask |= FOUND_MASK_VERS;
7394                 } else if (!strcmp(namebuf, "local-mac-address")) {
7395                         prop_buf = np->vpd.local_mac;
7396                         max_len = ETH_ALEN;
7397                         found_mask |= FOUND_MASK_MAC;
7398                 } else if (!strcmp(namebuf, "num-mac-addresses")) {
7399                         prop_buf = &np->vpd.mac_num;
7400                         max_len = 1;
7401                         found_mask |= FOUND_MASK_NMAC;
7402                 } else if (!strcmp(namebuf, "phy-type")) {
7403                         prop_buf = np->vpd.phy_type;
7404                         max_len = NIU_VPD_PHY_TYPE_MAX;
7405                         found_mask |= FOUND_MASK_PHY;
7406                 }
7407
7408                 if (max_len && prop_len > max_len) {
7409                         dev_err(np->device, PFX "Property '%s' length (%d) is "
7410                                 "too long.\n", namebuf, prop_len);
7411                         return -EINVAL;
7412                 }
7413
7414                 if (prop_buf) {
7415                         u32 off = start + 5 + err;
7416                         int i;
7417
7418                         niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
7419                                "len[%d]\n", namebuf, prop_len);
7420                         for (i = 0; i < prop_len; i++)
7421                                 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
7422                 }
7423
7424                 start += len;
7425         }
7426
7427         return 0;
7428 }
7429
7430 /* ESPC_PIO_EN_ENABLE must be set */
7431 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
7432 {
7433         u32 offset;
7434         int err;
7435
7436         err = niu_pci_eeprom_read16_swp(np, start + 1);
7437         if (err < 0)
7438                 return;
7439
7440         offset = err + 3;
7441
7442         while (start + offset < ESPC_EEPROM_SIZE) {
7443                 u32 here = start + offset;
7444                 u32 end;
7445
7446                 err = niu_pci_eeprom_read(np, here);
7447                 if (err != 0x90)
7448                         return;
7449
7450                 err = niu_pci_eeprom_read16_swp(np, here + 1);
7451                 if (err < 0)
7452                         return;
7453
7454                 here = start + offset + 3;
7455                 end = start + offset + err;
7456
7457                 offset += err;
7458
7459                 err = niu_pci_vpd_scan_props(np, here, end);
7460                 if (err < 0 || err == 1)
7461                         return;
7462         }
7463 }
7464
7465 /* ESPC_PIO_EN_ENABLE must be set */
7466 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
7467 {
7468         u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
7469         int err;
7470
7471         while (start < end) {
7472                 ret = start;
7473
7474                 /* ROM header signature?  */
7475                 err = niu_pci_eeprom_read16(np, start +  0);
7476                 if (err != 0x55aa)
7477                         return 0;
7478
7479                 /* Apply offset to PCI data structure.  */
7480                 err = niu_pci_eeprom_read16(np, start + 23);
7481                 if (err < 0)
7482                         return 0;
7483                 start += err;
7484
7485                 /* Check for "PCIR" signature.  */
7486                 err = niu_pci_eeprom_read16(np, start +  0);
7487                 if (err != 0x5043)
7488                         return 0;
7489                 err = niu_pci_eeprom_read16(np, start +  2);
7490                 if (err != 0x4952)
7491                         return 0;
7492
7493                 /* Check for OBP image type.  */
7494                 err = niu_pci_eeprom_read(np, start + 20);
7495                 if (err < 0)
7496                         return 0;
7497                 if (err != 0x01) {
7498                         err = niu_pci_eeprom_read(np, ret + 2);
7499                         if (err < 0)
7500                                 return 0;
7501
7502                         start = ret + (err * 512);
7503                         continue;
7504                 }
7505
7506                 err = niu_pci_eeprom_read16_swp(np, start + 8);
7507                 if (err < 0)
7508                         return err;
7509                 ret += err;
7510
7511                 err = niu_pci_eeprom_read(np, ret + 0);
7512                 if (err != 0x82)
7513                         return 0;
7514
7515                 return ret;
7516         }
7517
7518         return 0;
7519 }
7520
7521 static int __devinit niu_phy_type_prop_decode(struct niu *np,
7522                                               const char *phy_prop)
7523 {
7524         if (!strcmp(phy_prop, "mif")) {
7525                 /* 1G copper, MII */
7526                 np->flags &= ~(NIU_FLAGS_FIBER |
7527                                NIU_FLAGS_10G);
7528                 np->mac_xcvr = MAC_XCVR_MII;
7529         } else if (!strcmp(phy_prop, "xgf")) {
7530                 /* 10G fiber, XPCS */
7531                 np->flags |= (NIU_FLAGS_10G |
7532                               NIU_FLAGS_FIBER);
7533                 np->mac_xcvr = MAC_XCVR_XPCS;
7534         } else if (!strcmp(phy_prop, "pcs")) {
7535                 /* 1G fiber, PCS */
7536                 np->flags &= ~NIU_FLAGS_10G;
7537                 np->flags |= NIU_FLAGS_FIBER;
7538                 np->mac_xcvr = MAC_XCVR_PCS;
7539         } else if (!strcmp(phy_prop, "xgc")) {
7540                 /* 10G copper, XPCS */
7541                 np->flags |= NIU_FLAGS_10G;
7542                 np->flags &= ~NIU_FLAGS_FIBER;
7543                 np->mac_xcvr = MAC_XCVR_XPCS;
7544         } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
7545                 /* 10G Serdes or 1G Serdes, default to 10G */
7546                 np->flags |= NIU_FLAGS_10G;
7547                 np->flags &= ~NIU_FLAGS_FIBER;
7548                 np->flags |= NIU_FLAGS_XCVR_SERDES;
7549                 np->mac_xcvr = MAC_XCVR_XPCS;
7550         } else {
7551                 return -EINVAL;
7552         }
7553         return 0;
7554 }
7555
7556 static int niu_pci_vpd_get_nports(struct niu *np)
7557 {
7558         int ports = 0;
7559
7560         if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
7561             (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
7562             (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
7563             (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
7564             (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7565                 ports = 4;
7566         } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
7567                    (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
7568                    (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
7569                    (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7570                 ports = 2;
7571         }
7572
7573         return ports;
7574 }
7575
7576 static void __devinit niu_pci_vpd_validate(struct niu *np)
7577 {
7578         struct net_device *dev = np->dev;
7579         struct niu_vpd *vpd = &np->vpd;
7580         u8 val8;
7581
7582         if (!is_valid_ether_addr(&vpd->local_mac[0])) {
7583                 dev_err(np->device, PFX "VPD MAC invalid, "
7584                         "falling back to SPROM.\n");
7585
7586                 np->flags &= ~NIU_FLAGS_VPD_VALID;
7587                 return;
7588         }
7589
7590         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
7591             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
7592                 np->flags |= NIU_FLAGS_10G;
7593                 np->flags &= ~NIU_FLAGS_FIBER;
7594                 np->flags |= NIU_FLAGS_XCVR_SERDES;
7595                 np->mac_xcvr = MAC_XCVR_PCS;
7596                 if (np->port > 1) {
7597                         np->flags |= NIU_FLAGS_FIBER;
7598                         np->flags &= ~NIU_FLAGS_10G;
7599                 }
7600                 if (np->flags & NIU_FLAGS_10G)
7601                          np->mac_xcvr = MAC_XCVR_XPCS;
7602         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
7603                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
7604                               NIU_FLAGS_HOTPLUG_PHY);
7605         } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
7606                 dev_err(np->device, PFX "Illegal phy string [%s].\n",
7607                         np->vpd.phy_type);
7608                 dev_err(np->device, PFX "Falling back to SPROM.\n");
7609                 np->flags &= ~NIU_FLAGS_VPD_VALID;
7610                 return;
7611         }
7612
7613         memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
7614
7615         val8 = dev->perm_addr[5];
7616         dev->perm_addr[5] += np->port;
7617         if (dev->perm_addr[5] < val8)
7618                 dev->perm_addr[4]++;
7619
7620         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7621 }
7622
7623 static int __devinit niu_pci_probe_sprom(struct niu *np)
7624 {
7625         struct net_device *dev = np->dev;
7626         int len, i;
7627         u64 val, sum;
7628         u8 val8;
7629
7630         val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
7631         val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
7632         len = val / 4;
7633
7634         np->eeprom_len = len;
7635
7636         niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
7637
7638         sum = 0;
7639         for (i = 0; i < len; i++) {
7640                 val = nr64(ESPC_NCR(i));
7641                 sum += (val >>  0) & 0xff;
7642                 sum += (val >>  8) & 0xff;
7643                 sum += (val >> 16) & 0xff;
7644                 sum += (val >> 24) & 0xff;
7645         }
7646         niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
7647         if ((sum & 0xff) != 0xab) {
7648                 dev_err(np->device, PFX "Bad SPROM checksum "
7649                         "(%x, should be 0xab)\n", (int) (sum & 0xff));
7650                 return -EINVAL;
7651         }
7652
7653         val = nr64(ESPC_PHY_TYPE);
7654         switch (np->port) {
7655         case 0:
7656                 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
7657                         ESPC_PHY_TYPE_PORT0_SHIFT;
7658                 break;
7659         case 1:
7660                 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
7661                         ESPC_PHY_TYPE_PORT1_SHIFT;
7662                 break;
7663         case 2:
7664                 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
7665                         ESPC_PHY_TYPE_PORT2_SHIFT;
7666                 break;
7667         case 3:
7668                 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
7669                         ESPC_PHY_TYPE_PORT3_SHIFT;
7670                 break;
7671         default:
7672                 dev_err(np->device, PFX "Bogus port number %u\n",
7673                         np->port);
7674                 return -EINVAL;
7675         }
7676         niudbg(PROBE, "SPROM: PHY type %x\n", val8);
7677
7678         switch (val8) {
7679         case ESPC_PHY_TYPE_1G_COPPER:
7680                 /* 1G copper, MII */
7681                 np->flags &= ~(NIU_FLAGS_FIBER |
7682                                NIU_FLAGS_10G);
7683                 np->mac_xcvr = MAC_XCVR_MII;
7684                 break;
7685
7686         case ESPC_PHY_TYPE_1G_FIBER:
7687                 /* 1G fiber, PCS */
7688                 np->flags &= ~NIU_FLAGS_10G;
7689                 np->flags |= NIU_FLAGS_FIBER;
7690                 np->mac_xcvr = MAC_XCVR_PCS;
7691                 break;
7692
7693         case ESPC_PHY_TYPE_10G_COPPER:
7694                 /* 10G copper, XPCS */
7695                 np->flags |= NIU_FLAGS_10G;
7696                 np->flags &= ~NIU_FLAGS_FIBER;
7697                 np->mac_xcvr = MAC_XCVR_XPCS;
7698                 break;
7699
7700         case ESPC_PHY_TYPE_10G_FIBER:
7701                 /* 10G fiber, XPCS */
7702                 np->flags |= (NIU_FLAGS_10G |
7703                               NIU_FLAGS_FIBER);
7704                 np->mac_xcvr = MAC_XCVR_XPCS;
7705                 break;
7706
7707         default:
7708                 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
7709                 return -EINVAL;
7710         }
7711
7712         val = nr64(ESPC_MAC_ADDR0);
7713         niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
7714                (unsigned long long) val);
7715         dev->perm_addr[0] = (val >>  0) & 0xff;
7716         dev->perm_addr[1] = (val >>  8) & 0xff;
7717         dev->perm_addr[2] = (val >> 16) & 0xff;
7718         dev->perm_addr[3] = (val >> 24) & 0xff;
7719
7720         val = nr64(ESPC_MAC_ADDR1);
7721         niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
7722                (unsigned long long) val);
7723         dev->perm_addr[4] = (val >>  0) & 0xff;
7724         dev->perm_addr[5] = (val >>  8) & 0xff;
7725
7726         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
7727                 dev_err(np->device, PFX "SPROM MAC address invalid\n");
7728                 dev_err(np->device, PFX "[ \n");
7729                 for (i = 0; i < 6; i++)
7730                         printk("%02x ", dev->perm_addr[i]);
7731                 printk("]\n");
7732                 return -EINVAL;
7733         }
7734
7735         val8 = dev->perm_addr[5];
7736         dev->perm_addr[5] += np->port;
7737         if (dev->perm_addr[5] < val8)
7738                 dev->perm_addr[4]++;
7739
7740         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7741
7742         val = nr64(ESPC_MOD_STR_LEN);
7743         niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
7744                (unsigned long long) val);
7745         if (val >= 8 * 4)
7746                 return -EINVAL;
7747
7748         for (i = 0; i < val; i += 4) {
7749                 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
7750
7751                 np->vpd.model[i + 3] = (tmp >>  0) & 0xff;
7752                 np->vpd.model[i + 2] = (tmp >>  8) & 0xff;
7753                 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
7754                 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
7755         }
7756         np->vpd.model[val] = '\0';
7757
7758         val = nr64(ESPC_BD_MOD_STR_LEN);
7759         niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
7760                (unsigned long long) val);
7761         if (val >= 4 * 4)
7762                 return -EINVAL;
7763
7764         for (i = 0; i < val; i += 4) {
7765                 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
7766
7767                 np->vpd.board_model[i + 3] = (tmp >>  0) & 0xff;
7768                 np->vpd.board_model[i + 2] = (tmp >>  8) & 0xff;
7769                 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
7770                 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
7771         }
7772         np->vpd.board_model[val] = '\0';
7773
7774         np->vpd.mac_num =
7775                 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
7776         niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
7777                np->vpd.mac_num);
7778
7779         return 0;
7780 }
7781
7782 static int __devinit niu_get_and_validate_port(struct niu *np)
7783 {
7784         struct niu_parent *parent = np->parent;
7785
7786         if (np->port <= 1)
7787                 np->flags |= NIU_FLAGS_XMAC;
7788
7789         if (!parent->num_ports) {
7790                 if (parent->plat_type == PLAT_TYPE_NIU) {
7791                         parent->num_ports = 2;
7792                 } else {
7793                         parent->num_ports = niu_pci_vpd_get_nports(np);
7794                         if (!parent->num_ports) {
7795                                 /* Fall back to SPROM as last resort.
7796                                  * This will fail on most cards.
7797                                  */
7798                                 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
7799                                         ESPC_NUM_PORTS_MACS_VAL;
7800
7801                                 /* All of the current probing methods fail on
7802                                  * Maramba on-board parts.
7803                                  */
7804                                 if (!parent->num_ports)
7805                                         parent->num_ports = 4;
7806                         }
7807                 }
7808         }
7809
7810         niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
7811                np->port, parent->num_ports);
7812         if (np->port >= parent->num_ports)
7813                 return -ENODEV;
7814
7815         return 0;
7816 }
7817
7818 static int __devinit phy_record(struct niu_parent *parent,
7819                                 struct phy_probe_info *p,
7820                                 int dev_id_1, int dev_id_2, u8 phy_port,
7821                                 int type)
7822 {
7823         u32 id = (dev_id_1 << 16) | dev_id_2;
7824         u8 idx;
7825
7826         if (dev_id_1 < 0 || dev_id_2 < 0)
7827                 return 0;
7828         if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
7829                 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
7830                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
7831                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
7832                         return 0;
7833         } else {
7834                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
7835                         return 0;
7836         }
7837
7838         pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
7839                 parent->index, id,
7840                 (type == PHY_TYPE_PMA_PMD ?
7841                  "PMA/PMD" :
7842                  (type == PHY_TYPE_PCS ?
7843                   "PCS" : "MII")),
7844                 phy_port);
7845
7846         if (p->cur[type] >= NIU_MAX_PORTS) {
7847                 printk(KERN_ERR PFX "Too many PHY ports.\n");
7848                 return -EINVAL;
7849         }
7850         idx = p->cur[type];
7851         p->phy_id[type][idx] = id;
7852         p->phy_port[type][idx] = phy_port;
7853         p->cur[type] = idx + 1;
7854         return 0;
7855 }
7856
7857 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
7858 {
7859         int i;
7860
7861         for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
7862                 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
7863                         return 1;
7864         }
7865         for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
7866                 if (p->phy_port[PHY_TYPE_PCS][i] == port)
7867                         return 1;
7868         }
7869
7870         return 0;
7871 }
7872
7873 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
7874 {
7875         int port, cnt;
7876
7877         cnt = 0;
7878         *lowest = 32;
7879         for (port = 8; port < 32; port++) {
7880                 if (port_has_10g(p, port)) {
7881                         if (!cnt)
7882                                 *lowest = port;
7883                         cnt++;
7884                 }
7885         }
7886
7887         return cnt;
7888 }
7889
7890 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
7891 {
7892         *lowest = 32;
7893         if (p->cur[PHY_TYPE_MII])
7894                 *lowest = p->phy_port[PHY_TYPE_MII][0];
7895
7896         return p->cur[PHY_TYPE_MII];
7897 }
7898
7899 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
7900 {
7901         int num_ports = parent->num_ports;
7902         int i;
7903
7904         for (i = 0; i < num_ports; i++) {
7905                 parent->rxchan_per_port[i] = (16 / num_ports);
7906                 parent->txchan_per_port[i] = (16 / num_ports);
7907
7908                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7909                         "[%u TX chans]\n",
7910                         parent->index, i,
7911                         parent->rxchan_per_port[i],
7912                         parent->txchan_per_port[i]);
7913         }
7914 }
7915
7916 static void __devinit niu_divide_channels(struct niu_parent *parent,
7917                                           int num_10g, int num_1g)
7918 {
7919         int num_ports = parent->num_ports;
7920         int rx_chans_per_10g, rx_chans_per_1g;
7921         int tx_chans_per_10g, tx_chans_per_1g;
7922         int i, tot_rx, tot_tx;
7923
7924         if (!num_10g || !num_1g) {
7925                 rx_chans_per_10g = rx_chans_per_1g =
7926                         (NIU_NUM_RXCHAN / num_ports);
7927                 tx_chans_per_10g = tx_chans_per_1g =
7928                         (NIU_NUM_TXCHAN / num_ports);
7929         } else {
7930                 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
7931                 rx_chans_per_10g = (NIU_NUM_RXCHAN -
7932                                     (rx_chans_per_1g * num_1g)) /
7933                         num_10g;
7934
7935                 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
7936                 tx_chans_per_10g = (NIU_NUM_TXCHAN -
7937                                     (tx_chans_per_1g * num_1g)) /
7938                         num_10g;
7939         }
7940
7941         tot_rx = tot_tx = 0;
7942         for (i = 0; i < num_ports; i++) {
7943                 int type = phy_decode(parent->port_phy, i);
7944
7945                 if (type == PORT_TYPE_10G) {
7946                         parent->rxchan_per_port[i] = rx_chans_per_10g;
7947                         parent->txchan_per_port[i] = tx_chans_per_10g;
7948                 } else {
7949                         parent->rxchan_per_port[i] = rx_chans_per_1g;
7950                         parent->txchan_per_port[i] = tx_chans_per_1g;
7951                 }
7952                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7953                         "[%u TX chans]\n",
7954                         parent->index, i,
7955                         parent->rxchan_per_port[i],
7956                         parent->txchan_per_port[i]);
7957                 tot_rx += parent->rxchan_per_port[i];
7958                 tot_tx += parent->txchan_per_port[i];
7959         }
7960
7961         if (tot_rx > NIU_NUM_RXCHAN) {
7962                 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
7963                        "resetting to one per port.\n",
7964                        parent->index, tot_rx);
7965                 for (i = 0; i < num_ports; i++)
7966                         parent->rxchan_per_port[i] = 1;
7967         }
7968         if (tot_tx > NIU_NUM_TXCHAN) {
7969                 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
7970                        "resetting to one per port.\n",
7971                        parent->index, tot_tx);
7972                 for (i = 0; i < num_ports; i++)
7973                         parent->txchan_per_port[i] = 1;
7974         }
7975         if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
7976                 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
7977                        "RX[%d] TX[%d]\n",
7978                        parent->index, tot_rx, tot_tx);
7979         }
7980 }
7981
7982 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
7983                                             int num_10g, int num_1g)
7984 {
7985         int i, num_ports = parent->num_ports;
7986         int rdc_group, rdc_groups_per_port;
7987         int rdc_channel_base;
7988
7989         rdc_group = 0;
7990         rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
7991
7992         rdc_channel_base = 0;
7993
7994         for (i = 0; i < num_ports; i++) {
7995                 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
7996                 int grp, num_channels = parent->rxchan_per_port[i];
7997                 int this_channel_offset;
7998
7999                 tp->first_table_num = rdc_group;
8000                 tp->num_tables = rdc_groups_per_port;
8001                 this_channel_offset = 0;
8002                 for (grp = 0; grp < tp->num_tables; grp++) {
8003                         struct rdc_table *rt = &tp->tables[grp];
8004                         int slot;
8005
8006                         pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
8007                                 parent->index, i, tp->first_table_num + grp);
8008                         for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8009                                 rt->rxdma_channel[slot] =
8010                                         rdc_channel_base + this_channel_offset;
8011
8012                                 printk("%d ", rt->rxdma_channel[slot]);
8013
8014                                 if (++this_channel_offset == num_channels)
8015                                         this_channel_offset = 0;
8016                         }
8017                         printk("]\n");
8018                 }
8019
8020                 parent->rdc_default[i] = rdc_channel_base;
8021
8022                 rdc_channel_base += num_channels;
8023                 rdc_group += rdc_groups_per_port;
8024         }
8025 }
8026
8027 static int __devinit fill_phy_probe_info(struct niu *np,
8028                                          struct niu_parent *parent,
8029                                          struct phy_probe_info *info)
8030 {
8031         unsigned long flags;
8032         int port, err;
8033
8034         memset(info, 0, sizeof(*info));
8035
8036         /* Port 0 to 7 are reserved for onboard Serdes, probe the rest.  */
8037         niu_lock_parent(np, flags);
8038         err = 0;
8039         for (port = 8; port < 32; port++) {
8040                 int dev_id_1, dev_id_2;
8041
8042                 dev_id_1 = mdio_read(np, port,
8043                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8044                 dev_id_2 = mdio_read(np, port,
8045                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8046                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8047                                  PHY_TYPE_PMA_PMD);
8048                 if (err)
8049                         break;
8050                 dev_id_1 = mdio_read(np, port,
8051                                      NIU_PCS_DEV_ADDR, MII_PHYSID1);
8052                 dev_id_2 = mdio_read(np, port,
8053                                      NIU_PCS_DEV_ADDR, MII_PHYSID2);
8054                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8055                                  PHY_TYPE_PCS);
8056                 if (err)
8057                         break;
8058                 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8059                 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8060                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8061                                  PHY_TYPE_MII);
8062                 if (err)
8063                         break;
8064         }
8065         niu_unlock_parent(np, flags);
8066
8067         return err;
8068 }
8069
8070 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8071 {
8072         struct phy_probe_info *info = &parent->phy_probe_info;
8073         int lowest_10g, lowest_1g;
8074         int num_10g, num_1g;
8075         u32 val;
8076         int err;
8077
8078         num_10g = num_1g = 0;
8079
8080         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8081             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8082                 num_10g = 0;
8083                 num_1g = 2;
8084                 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8085                 parent->num_ports = 4;
8086                 val = (phy_encode(PORT_TYPE_1G, 0) |
8087                        phy_encode(PORT_TYPE_1G, 1) |
8088                        phy_encode(PORT_TYPE_1G, 2) |
8089                        phy_encode(PORT_TYPE_1G, 3));
8090         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8091                 num_10g = 2;
8092                 num_1g = 0;
8093                 parent->num_ports = 2;
8094                 val = (phy_encode(PORT_TYPE_10G, 0) |
8095                        phy_encode(PORT_TYPE_10G, 1));
8096         } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8097                    (parent->plat_type == PLAT_TYPE_NIU)) {
8098                 /* this is the Monza case */
8099                 if (np->flags & NIU_FLAGS_10G) {
8100                         val = (phy_encode(PORT_TYPE_10G, 0) |
8101                                phy_encode(PORT_TYPE_10G, 1));
8102                 } else {
8103                         val = (phy_encode(PORT_TYPE_1G, 0) |
8104                                phy_encode(PORT_TYPE_1G, 1));
8105                 }
8106         } else {
8107                 err = fill_phy_probe_info(np, parent, info);
8108                 if (err)
8109                         return err;
8110
8111                 num_10g = count_10g_ports(info, &lowest_10g);
8112                 num_1g = count_1g_ports(info, &lowest_1g);
8113
8114                 switch ((num_10g << 4) | num_1g) {
8115                 case 0x24:
8116                         if (lowest_1g == 10)
8117                                 parent->plat_type = PLAT_TYPE_VF_P0;
8118                         else if (lowest_1g == 26)
8119                                 parent->plat_type = PLAT_TYPE_VF_P1;
8120                         else
8121                                 goto unknown_vg_1g_port;
8122
8123                         /* fallthru */
8124                 case 0x22:
8125                         val = (phy_encode(PORT_TYPE_10G, 0) |
8126                                phy_encode(PORT_TYPE_10G, 1) |
8127                                phy_encode(PORT_TYPE_1G, 2) |
8128                                phy_encode(PORT_TYPE_1G, 3));
8129                         break;
8130
8131                 case 0x20:
8132                         val = (phy_encode(PORT_TYPE_10G, 0) |
8133                                phy_encode(PORT_TYPE_10G, 1));
8134                         break;
8135
8136                 case 0x10:
8137                         val = phy_encode(PORT_TYPE_10G, np->port);
8138                         break;
8139
8140                 case 0x14:
8141                         if (lowest_1g == 10)
8142                                 parent->plat_type = PLAT_TYPE_VF_P0;
8143                         else if (lowest_1g == 26)
8144                                 parent->plat_type = PLAT_TYPE_VF_P1;
8145                         else
8146                                 goto unknown_vg_1g_port;
8147
8148                         /* fallthru */
8149                 case 0x13:
8150                         if ((lowest_10g & 0x7) == 0)
8151                                 val = (phy_encode(PORT_TYPE_10G, 0) |
8152                                        phy_encode(PORT_TYPE_1G, 1) |
8153                                        phy_encode(PORT_TYPE_1G, 2) |
8154                                        phy_encode(PORT_TYPE_1G, 3));
8155                         else
8156                                 val = (phy_encode(PORT_TYPE_1G, 0) |
8157                                        phy_encode(PORT_TYPE_10G, 1) |
8158                                        phy_encode(PORT_TYPE_1G, 2) |
8159                                        phy_encode(PORT_TYPE_1G, 3));
8160                         break;
8161
8162                 case 0x04:
8163                         if (lowest_1g == 10)
8164                                 parent->plat_type = PLAT_TYPE_VF_P0;
8165                         else if (lowest_1g == 26)
8166                                 parent->plat_type = PLAT_TYPE_VF_P1;
8167                         else
8168                                 goto unknown_vg_1g_port;
8169
8170                         val = (phy_encode(PORT_TYPE_1G, 0) |
8171                                phy_encode(PORT_TYPE_1G, 1) |
8172                                phy_encode(PORT_TYPE_1G, 2) |
8173                                phy_encode(PORT_TYPE_1G, 3));
8174                         break;
8175
8176                 default:
8177                         printk(KERN_ERR PFX "Unsupported port config "
8178                                "10G[%d] 1G[%d]\n",
8179                                num_10g, num_1g);
8180                         return -EINVAL;
8181                 }
8182         }
8183
8184         parent->port_phy = val;
8185
8186         if (parent->plat_type == PLAT_TYPE_NIU)
8187                 niu_n2_divide_channels(parent);
8188         else
8189                 niu_divide_channels(parent, num_10g, num_1g);
8190
8191         niu_divide_rdc_groups(parent, num_10g, num_1g);
8192
8193         return 0;
8194
8195 unknown_vg_1g_port:
8196         printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
8197                lowest_1g);
8198         return -EINVAL;
8199 }
8200
8201 static int __devinit niu_probe_ports(struct niu *np)
8202 {
8203         struct niu_parent *parent = np->parent;
8204         int err, i;
8205
8206         niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
8207                parent->port_phy);
8208
8209         if (parent->port_phy == PORT_PHY_UNKNOWN) {
8210                 err = walk_phys(np, parent);
8211                 if (err)
8212                         return err;
8213
8214                 niu_set_ldg_timer_res(np, 2);
8215                 for (i = 0; i <= LDN_MAX; i++)
8216                         niu_ldn_irq_enable(np, i, 0);
8217         }
8218
8219         if (parent->port_phy == PORT_PHY_INVALID)
8220                 return -EINVAL;
8221
8222         return 0;
8223 }
8224
8225 static int __devinit niu_classifier_swstate_init(struct niu *np)
8226 {
8227         struct niu_classifier *cp = &np->clas;
8228
8229         niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
8230                np->parent->tcam_num_entries);
8231
8232         cp->tcam_index = (u16) np->port;
8233         cp->h1_init = 0xffffffff;
8234         cp->h2_init = 0xffff;
8235
8236         return fflp_early_init(np);
8237 }
8238
8239 static void __devinit niu_link_config_init(struct niu *np)
8240 {
8241         struct niu_link_config *lp = &np->link_config;
8242
8243         lp->advertising = (ADVERTISED_10baseT_Half |
8244                            ADVERTISED_10baseT_Full |
8245                            ADVERTISED_100baseT_Half |
8246                            ADVERTISED_100baseT_Full |
8247                            ADVERTISED_1000baseT_Half |
8248                            ADVERTISED_1000baseT_Full |
8249                            ADVERTISED_10000baseT_Full |
8250                            ADVERTISED_Autoneg);
8251         lp->speed = lp->active_speed = SPEED_INVALID;
8252         lp->duplex = lp->active_duplex = DUPLEX_INVALID;
8253 #if 0
8254         lp->loopback_mode = LOOPBACK_MAC;
8255         lp->active_speed = SPEED_10000;
8256         lp->active_duplex = DUPLEX_FULL;
8257 #else
8258         lp->loopback_mode = LOOPBACK_DISABLED;
8259 #endif
8260 }
8261
8262 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
8263 {
8264         switch (np->port) {
8265         case 0:
8266                 np->mac_regs = np->regs + XMAC_PORT0_OFF;
8267                 np->ipp_off  = 0x00000;
8268                 np->pcs_off  = 0x04000;
8269                 np->xpcs_off = 0x02000;
8270                 break;
8271
8272         case 1:
8273                 np->mac_regs = np->regs + XMAC_PORT1_OFF;
8274                 np->ipp_off  = 0x08000;
8275                 np->pcs_off  = 0x0a000;
8276                 np->xpcs_off = 0x08000;
8277                 break;
8278
8279         case 2:
8280                 np->mac_regs = np->regs + BMAC_PORT2_OFF;
8281                 np->ipp_off  = 0x04000;
8282                 np->pcs_off  = 0x0e000;
8283                 np->xpcs_off = ~0UL;
8284                 break;
8285
8286         case 3:
8287                 np->mac_regs = np->regs + BMAC_PORT3_OFF;
8288                 np->ipp_off  = 0x0c000;
8289                 np->pcs_off  = 0x12000;
8290                 np->xpcs_off = ~0UL;
8291                 break;
8292
8293         default:
8294                 dev_err(np->device, PFX "Port %u is invalid, cannot "
8295                         "compute MAC block offset.\n", np->port);
8296                 return -EINVAL;
8297         }
8298
8299         return 0;
8300 }
8301
8302 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
8303 {
8304         struct msix_entry msi_vec[NIU_NUM_LDG];
8305         struct niu_parent *parent = np->parent;
8306         struct pci_dev *pdev = np->pdev;
8307         int i, num_irqs, err;
8308         u8 first_ldg;
8309
8310         first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
8311         for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
8312                 ldg_num_map[i] = first_ldg + i;
8313
8314         num_irqs = (parent->rxchan_per_port[np->port] +
8315                     parent->txchan_per_port[np->port] +
8316                     (np->port == 0 ? 3 : 1));
8317         BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
8318
8319 retry:
8320         for (i = 0; i < num_irqs; i++) {
8321                 msi_vec[i].vector = 0;
8322                 msi_vec[i].entry = i;
8323         }
8324
8325         err = pci_enable_msix(pdev, msi_vec, num_irqs);
8326         if (err < 0) {
8327                 np->flags &= ~NIU_FLAGS_MSIX;
8328                 return;
8329         }
8330         if (err > 0) {
8331                 num_irqs = err;
8332                 goto retry;
8333         }
8334
8335         np->flags |= NIU_FLAGS_MSIX;
8336         for (i = 0; i < num_irqs; i++)
8337                 np->ldg[i].irq = msi_vec[i].vector;
8338         np->num_ldg = num_irqs;
8339 }
8340
8341 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
8342 {
8343 #ifdef CONFIG_SPARC64
8344         struct of_device *op = np->op;
8345         const u32 *int_prop;
8346         int i;
8347
8348         int_prop = of_get_property(op->node, "interrupts", NULL);
8349         if (!int_prop)
8350                 return -ENODEV;
8351
8352         for (i = 0; i < op->num_irqs; i++) {
8353                 ldg_num_map[i] = int_prop[i];
8354                 np->ldg[i].irq = op->irqs[i];
8355         }
8356
8357         np->num_ldg = op->num_irqs;
8358
8359         return 0;
8360 #else
8361         return -EINVAL;
8362 #endif
8363 }
8364
8365 static int __devinit niu_ldg_init(struct niu *np)
8366 {
8367         struct niu_parent *parent = np->parent;
8368         u8 ldg_num_map[NIU_NUM_LDG];
8369         int first_chan, num_chan;
8370         int i, err, ldg_rotor;
8371         u8 port;
8372
8373         np->num_ldg = 1;
8374         np->ldg[0].irq = np->dev->irq;
8375         if (parent->plat_type == PLAT_TYPE_NIU) {
8376                 err = niu_n2_irq_init(np, ldg_num_map);
8377                 if (err)
8378                         return err;
8379         } else
8380                 niu_try_msix(np, ldg_num_map);
8381
8382         port = np->port;
8383         for (i = 0; i < np->num_ldg; i++) {
8384                 struct niu_ldg *lp = &np->ldg[i];
8385
8386                 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
8387
8388                 lp->np = np;
8389                 lp->ldg_num = ldg_num_map[i];
8390                 lp->timer = 2; /* XXX */
8391
8392                 /* On N2 NIU the firmware has setup the SID mappings so they go
8393                  * to the correct values that will route the LDG to the proper
8394                  * interrupt in the NCU interrupt table.
8395                  */
8396                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
8397                         err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
8398                         if (err)
8399                                 return err;
8400                 }
8401         }
8402
8403         /* We adopt the LDG assignment ordering used by the N2 NIU
8404          * 'interrupt' properties because that simplifies a lot of
8405          * things.  This ordering is:
8406          *
8407          *      MAC
8408          *      MIF     (if port zero)
8409          *      SYSERR  (if port zero)
8410          *      RX channels
8411          *      TX channels
8412          */
8413
8414         ldg_rotor = 0;
8415
8416         err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
8417                                   LDN_MAC(port));
8418         if (err)
8419                 return err;
8420
8421         ldg_rotor++;
8422         if (ldg_rotor == np->num_ldg)
8423                 ldg_rotor = 0;
8424
8425         if (port == 0) {
8426                 err = niu_ldg_assign_ldn(np, parent,
8427                                          ldg_num_map[ldg_rotor],
8428                                          LDN_MIF);
8429                 if (err)
8430                         return err;
8431
8432                 ldg_rotor++;
8433                 if (ldg_rotor == np->num_ldg)
8434                         ldg_rotor = 0;
8435
8436                 err = niu_ldg_assign_ldn(np, parent,
8437                                          ldg_num_map[ldg_rotor],
8438                                          LDN_DEVICE_ERROR);
8439                 if (err)
8440                         return err;
8441
8442                 ldg_rotor++;
8443                 if (ldg_rotor == np->num_ldg)
8444                         ldg_rotor = 0;
8445
8446         }
8447
8448         first_chan = 0;
8449         for (i = 0; i < port; i++)
8450                 first_chan += parent->rxchan_per_port[port];
8451         num_chan = parent->rxchan_per_port[port];
8452
8453         for (i = first_chan; i < (first_chan + num_chan); i++) {
8454                 err = niu_ldg_assign_ldn(np, parent,
8455                                          ldg_num_map[ldg_rotor],
8456                                          LDN_RXDMA(i));
8457                 if (err)
8458                         return err;
8459                 ldg_rotor++;
8460                 if (ldg_rotor == np->num_ldg)
8461                         ldg_rotor = 0;
8462         }
8463
8464         first_chan = 0;
8465         for (i = 0; i < port; i++)
8466                 first_chan += parent->txchan_per_port[port];
8467         num_chan = parent->txchan_per_port[port];
8468         for (i = first_chan; i < (first_chan + num_chan); i++) {
8469                 err = niu_ldg_assign_ldn(np, parent,
8470                                          ldg_num_map[ldg_rotor],
8471                                          LDN_TXDMA(i));
8472                 if (err)
8473                         return err;
8474                 ldg_rotor++;
8475                 if (ldg_rotor == np->num_ldg)
8476                         ldg_rotor = 0;
8477         }
8478
8479         return 0;
8480 }
8481
8482 static void __devexit niu_ldg_free(struct niu *np)
8483 {
8484         if (np->flags & NIU_FLAGS_MSIX)
8485                 pci_disable_msix(np->pdev);
8486 }
8487
8488 static int __devinit niu_get_of_props(struct niu *np)
8489 {
8490 #ifdef CONFIG_SPARC64
8491         struct net_device *dev = np->dev;
8492         struct device_node *dp;
8493         const char *phy_type;
8494         const u8 *mac_addr;
8495         const char *model;
8496         int prop_len;
8497
8498         if (np->parent->plat_type == PLAT_TYPE_NIU)
8499                 dp = np->op->node;
8500         else
8501                 dp = pci_device_to_OF_node(np->pdev);
8502
8503         phy_type = of_get_property(dp, "phy-type", &prop_len);
8504         if (!phy_type) {
8505                 dev_err(np->device, PFX "%s: OF node lacks "
8506                         "phy-type property\n",
8507                         dp->full_name);
8508                 return -EINVAL;
8509         }
8510
8511         if (!strcmp(phy_type, "none"))
8512                 return -ENODEV;
8513
8514         strcpy(np->vpd.phy_type, phy_type);
8515
8516         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8517                 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
8518                         dp->full_name, np->vpd.phy_type);
8519                 return -EINVAL;
8520         }
8521
8522         mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
8523         if (!mac_addr) {
8524                 dev_err(np->device, PFX "%s: OF node lacks "
8525                         "local-mac-address property\n",
8526                         dp->full_name);
8527                 return -EINVAL;
8528         }
8529         if (prop_len != dev->addr_len) {
8530                 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
8531                         "is wrong.\n",
8532                         dp->full_name, prop_len);
8533         }
8534         memcpy(dev->perm_addr, mac_addr, dev->addr_len);
8535         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8536                 int i;
8537
8538                 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
8539                         dp->full_name);
8540                 dev_err(np->device, PFX "%s: [ \n",
8541                         dp->full_name);
8542                 for (i = 0; i < 6; i++)
8543                         printk("%02x ", dev->perm_addr[i]);
8544                 printk("]\n");
8545                 return -EINVAL;
8546         }
8547
8548         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8549
8550         model = of_get_property(dp, "model", &prop_len);
8551
8552         if (model)
8553                 strcpy(np->vpd.model, model);
8554
8555         return 0;
8556 #else
8557         return -EINVAL;
8558 #endif
8559 }
8560
8561 static int __devinit niu_get_invariants(struct niu *np)
8562 {
8563         int err, have_props;
8564         u32 offset;
8565
8566         err = niu_get_of_props(np);
8567         if (err == -ENODEV)
8568                 return err;
8569
8570         have_props = !err;
8571
8572         err = niu_init_mac_ipp_pcs_base(np);
8573         if (err)
8574                 return err;
8575
8576         if (have_props) {
8577                 err = niu_get_and_validate_port(np);
8578                 if (err)
8579                         return err;
8580
8581         } else  {
8582                 if (np->parent->plat_type == PLAT_TYPE_NIU)
8583                         return -EINVAL;
8584
8585                 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
8586                 offset = niu_pci_vpd_offset(np);
8587                 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
8588                        offset);
8589                 if (offset)
8590                         niu_pci_vpd_fetch(np, offset);
8591                 nw64(ESPC_PIO_EN, 0);
8592
8593                 if (np->flags & NIU_FLAGS_VPD_VALID) {
8594                         niu_pci_vpd_validate(np);
8595                         err = niu_get_and_validate_port(np);
8596                         if (err)
8597                                 return err;
8598                 }
8599
8600                 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
8601                         err = niu_get_and_validate_port(np);
8602                         if (err)
8603                                 return err;
8604                         err = niu_pci_probe_sprom(np);
8605                         if (err)
8606                                 return err;
8607                 }
8608         }
8609
8610         err = niu_probe_ports(np);
8611         if (err)
8612                 return err;
8613
8614         niu_ldg_init(np);
8615
8616         niu_classifier_swstate_init(np);
8617         niu_link_config_init(np);
8618
8619         err = niu_determine_phy_disposition(np);
8620         if (!err)
8621                 err = niu_init_link(np);
8622
8623         return err;
8624 }
8625
8626 static LIST_HEAD(niu_parent_list);
8627 static DEFINE_MUTEX(niu_parent_lock);
8628 static int niu_parent_index;
8629
8630 static ssize_t show_port_phy(struct device *dev,
8631                              struct device_attribute *attr, char *buf)
8632 {
8633         struct platform_device *plat_dev = to_platform_device(dev);
8634         struct niu_parent *p = plat_dev->dev.platform_data;
8635         u32 port_phy = p->port_phy;
8636         char *orig_buf = buf;
8637         int i;
8638
8639         if (port_phy == PORT_PHY_UNKNOWN ||
8640             port_phy == PORT_PHY_INVALID)
8641                 return 0;
8642
8643         for (i = 0; i < p->num_ports; i++) {
8644                 const char *type_str;
8645                 int type;
8646
8647                 type = phy_decode(port_phy, i);
8648                 if (type == PORT_TYPE_10G)
8649                         type_str = "10G";
8650                 else
8651                         type_str = "1G";
8652                 buf += sprintf(buf,
8653                                (i == 0) ? "%s" : " %s",
8654                                type_str);
8655         }
8656         buf += sprintf(buf, "\n");
8657         return buf - orig_buf;
8658 }
8659
8660 static ssize_t show_plat_type(struct device *dev,
8661                               struct device_attribute *attr, char *buf)
8662 {
8663         struct platform_device *plat_dev = to_platform_device(dev);
8664         struct niu_parent *p = plat_dev->dev.platform_data;
8665         const char *type_str;
8666
8667         switch (p->plat_type) {
8668         case PLAT_TYPE_ATLAS:
8669                 type_str = "atlas";
8670                 break;
8671         case PLAT_TYPE_NIU:
8672                 type_str = "niu";
8673                 break;
8674         case PLAT_TYPE_VF_P0:
8675                 type_str = "vf_p0";
8676                 break;
8677         case PLAT_TYPE_VF_P1:
8678                 type_str = "vf_p1";
8679                 break;
8680         default:
8681                 type_str = "unknown";
8682                 break;
8683         }
8684
8685         return sprintf(buf, "%s\n", type_str);
8686 }
8687
8688 static ssize_t __show_chan_per_port(struct device *dev,
8689                                     struct device_attribute *attr, char *buf,
8690                                     int rx)
8691 {
8692         struct platform_device *plat_dev = to_platform_device(dev);
8693         struct niu_parent *p = plat_dev->dev.platform_data;
8694         char *orig_buf = buf;
8695         u8 *arr;
8696         int i;
8697
8698         arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
8699
8700         for (i = 0; i < p->num_ports; i++) {
8701                 buf += sprintf(buf,
8702                                (i == 0) ? "%d" : " %d",
8703                                arr[i]);
8704         }
8705         buf += sprintf(buf, "\n");
8706
8707         return buf - orig_buf;
8708 }
8709
8710 static ssize_t show_rxchan_per_port(struct device *dev,
8711                                     struct device_attribute *attr, char *buf)
8712 {
8713         return __show_chan_per_port(dev, attr, buf, 1);
8714 }
8715
8716 static ssize_t show_txchan_per_port(struct device *dev,
8717                                     struct device_attribute *attr, char *buf)
8718 {
8719         return __show_chan_per_port(dev, attr, buf, 1);
8720 }
8721
8722 static ssize_t show_num_ports(struct device *dev,
8723                               struct device_attribute *attr, char *buf)
8724 {
8725         struct platform_device *plat_dev = to_platform_device(dev);
8726         struct niu_parent *p = plat_dev->dev.platform_data;
8727
8728         return sprintf(buf, "%d\n", p->num_ports);
8729 }
8730
8731 static struct device_attribute niu_parent_attributes[] = {
8732         __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
8733         __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
8734         __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
8735         __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
8736         __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
8737         {}
8738 };
8739
8740 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
8741                                                     union niu_parent_id *id,
8742                                                     u8 ptype)
8743 {
8744         struct platform_device *plat_dev;
8745         struct niu_parent *p;
8746         int i;
8747
8748         niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
8749
8750         plat_dev = platform_device_register_simple("niu", niu_parent_index,
8751                                                    NULL, 0);
8752         if (!plat_dev)
8753                 return NULL;
8754
8755         for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
8756                 int err = device_create_file(&plat_dev->dev,
8757                                              &niu_parent_attributes[i]);
8758                 if (err)
8759                         goto fail_unregister;
8760         }
8761
8762         p = kzalloc(sizeof(*p), GFP_KERNEL);
8763         if (!p)
8764                 goto fail_unregister;
8765
8766         p->index = niu_parent_index++;
8767
8768         plat_dev->dev.platform_data = p;
8769         p->plat_dev = plat_dev;
8770
8771         memcpy(&p->id, id, sizeof(*id));
8772         p->plat_type = ptype;
8773         INIT_LIST_HEAD(&p->list);
8774         atomic_set(&p->refcnt, 0);
8775         list_add(&p->list, &niu_parent_list);
8776         spin_lock_init(&p->lock);
8777
8778         p->rxdma_clock_divider = 7500;
8779
8780         p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
8781         if (p->plat_type == PLAT_TYPE_NIU)
8782                 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
8783
8784         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
8785                 int index = i - CLASS_CODE_USER_PROG1;
8786
8787                 p->tcam_key[index] = TCAM_KEY_TSEL;
8788                 p->flow_key[index] = (FLOW_KEY_IPSA |
8789                                       FLOW_KEY_IPDA |
8790                                       FLOW_KEY_PROTO |
8791                                       (FLOW_KEY_L4_BYTE12 <<
8792                                        FLOW_KEY_L4_0_SHIFT) |
8793                                       (FLOW_KEY_L4_BYTE12 <<
8794                                        FLOW_KEY_L4_1_SHIFT));
8795         }
8796
8797         for (i = 0; i < LDN_MAX + 1; i++)
8798                 p->ldg_map[i] = LDG_INVALID;
8799
8800         return p;
8801
8802 fail_unregister:
8803         platform_device_unregister(plat_dev);
8804         return NULL;
8805 }
8806
8807 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
8808                                                     union niu_parent_id *id,
8809                                                     u8 ptype)
8810 {
8811         struct niu_parent *p, *tmp;
8812         int port = np->port;
8813
8814         niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
8815                ptype, port);
8816
8817         mutex_lock(&niu_parent_lock);
8818         p = NULL;
8819         list_for_each_entry(tmp, &niu_parent_list, list) {
8820                 if (!memcmp(id, &tmp->id, sizeof(*id))) {
8821                         p = tmp;
8822                         break;
8823                 }
8824         }
8825         if (!p)
8826                 p = niu_new_parent(np, id, ptype);
8827
8828         if (p) {
8829                 char port_name[6];
8830                 int err;
8831
8832                 sprintf(port_name, "port%d", port);
8833                 err = sysfs_create_link(&p->plat_dev->dev.kobj,
8834                                         &np->device->kobj,
8835                                         port_name);
8836                 if (!err) {
8837                         p->ports[port] = np;
8838                         atomic_inc(&p->refcnt);
8839                 }
8840         }
8841         mutex_unlock(&niu_parent_lock);
8842
8843         return p;
8844 }
8845
8846 static void niu_put_parent(struct niu *np)
8847 {
8848         struct niu_parent *p = np->parent;
8849         u8 port = np->port;
8850         char port_name[6];
8851
8852         BUG_ON(!p || p->ports[port] != np);
8853
8854         niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
8855
8856         sprintf(port_name, "port%d", port);
8857
8858         mutex_lock(&niu_parent_lock);
8859
8860         sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
8861
8862         p->ports[port] = NULL;
8863         np->parent = NULL;
8864
8865         if (atomic_dec_and_test(&p->refcnt)) {
8866                 list_del(&p->list);
8867                 platform_device_unregister(p->plat_dev);
8868         }
8869
8870         mutex_unlock(&niu_parent_lock);
8871 }
8872
8873 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
8874                                     u64 *handle, gfp_t flag)
8875 {
8876         dma_addr_t dh;
8877         void *ret;
8878
8879         ret = dma_alloc_coherent(dev, size, &dh, flag);
8880         if (ret)
8881                 *handle = dh;
8882         return ret;
8883 }
8884
8885 static void niu_pci_free_coherent(struct device *dev, size_t size,
8886                                   void *cpu_addr, u64 handle)
8887 {
8888         dma_free_coherent(dev, size, cpu_addr, handle);
8889 }
8890
8891 static u64 niu_pci_map_page(struct device *dev, struct page *page,
8892                             unsigned long offset, size_t size,
8893                             enum dma_data_direction direction)
8894 {
8895         return dma_map_page(dev, page, offset, size, direction);
8896 }
8897
8898 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
8899                                size_t size, enum dma_data_direction direction)
8900 {
8901         return dma_unmap_page(dev, dma_address, size, direction);
8902 }
8903
8904 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
8905                               size_t size,
8906                               enum dma_data_direction direction)
8907 {
8908         return dma_map_single(dev, cpu_addr, size, direction);
8909 }
8910
8911 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
8912                                  size_t size,
8913                                  enum dma_data_direction direction)
8914 {
8915         dma_unmap_single(dev, dma_address, size, direction);
8916 }
8917
8918 static const struct niu_ops niu_pci_ops = {
8919         .alloc_coherent = niu_pci_alloc_coherent,
8920         .free_coherent  = niu_pci_free_coherent,
8921         .map_page       = niu_pci_map_page,
8922         .unmap_page     = niu_pci_unmap_page,
8923         .map_single     = niu_pci_map_single,
8924         .unmap_single   = niu_pci_unmap_single,
8925 };
8926
8927 static void __devinit niu_driver_version(void)
8928 {
8929         static int niu_version_printed;
8930
8931         if (niu_version_printed++ == 0)
8932                 pr_info("%s", version);
8933 }
8934
8935 static struct net_device * __devinit niu_alloc_and_init(
8936         struct device *gen_dev, struct pci_dev *pdev,
8937         struct of_device *op, const struct niu_ops *ops,
8938         u8 port)
8939 {
8940         struct net_device *dev;
8941         struct niu *np;
8942
8943         dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
8944         if (!dev) {
8945                 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
8946                 return NULL;
8947         }
8948
8949         SET_NETDEV_DEV(dev, gen_dev);
8950
8951         np = netdev_priv(dev);
8952         np->dev = dev;
8953         np->pdev = pdev;
8954         np->op = op;
8955         np->device = gen_dev;
8956         np->ops = ops;
8957
8958         np->msg_enable = niu_debug;
8959
8960         spin_lock_init(&np->lock);
8961         INIT_WORK(&np->reset_task, niu_reset_task);
8962
8963         np->port = port;
8964
8965         return dev;
8966 }
8967
8968 static const struct net_device_ops niu_netdev_ops = {
8969         .ndo_open               = niu_open,
8970         .ndo_stop               = niu_close,
8971         .ndo_start_xmit         = niu_start_xmit,
8972         .ndo_get_stats          = niu_get_stats,
8973         .ndo_set_multicast_list = niu_set_rx_mode,
8974         .ndo_validate_addr      = eth_validate_addr,
8975         .ndo_set_mac_address    = niu_set_mac_addr,
8976         .ndo_do_ioctl           = niu_ioctl,
8977         .ndo_tx_timeout         = niu_tx_timeout,
8978         .ndo_change_mtu         = niu_change_mtu,
8979 };
8980
8981 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
8982 {
8983         dev->netdev_ops = &niu_netdev_ops;
8984         dev->ethtool_ops = &niu_ethtool_ops;
8985         dev->watchdog_timeo = NIU_TX_TIMEOUT;
8986 }
8987
8988 static void __devinit niu_device_announce(struct niu *np)
8989 {
8990         struct net_device *dev = np->dev;
8991
8992         pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
8993
8994         if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
8995                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8996                                 dev->name,
8997                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
8998                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
8999                                 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9000                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9001                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9002                                 np->vpd.phy_type);
9003         } else {
9004                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9005                                 dev->name,
9006                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9007                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9008                                 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9009                                  (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9010                                   "COPPER")),
9011                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9012                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9013                                 np->vpd.phy_type);
9014         }
9015 }
9016
9017 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9018                                       const struct pci_device_id *ent)
9019 {
9020         union niu_parent_id parent_id;
9021         struct net_device *dev;
9022         struct niu *np;
9023         int err, pos;
9024         u64 dma_mask;
9025         u16 val16;
9026
9027         niu_driver_version();
9028
9029         err = pci_enable_device(pdev);
9030         if (err) {
9031                 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
9032                         "aborting.\n");
9033                 return err;
9034         }
9035
9036         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9037             !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9038                 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
9039                         "base addresses, aborting.\n");
9040                 err = -ENODEV;
9041                 goto err_out_disable_pdev;
9042         }
9043
9044         err = pci_request_regions(pdev, DRV_MODULE_NAME);
9045         if (err) {
9046                 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
9047                         "aborting.\n");
9048                 goto err_out_disable_pdev;
9049         }
9050
9051         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9052         if (pos <= 0) {
9053                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
9054                         "aborting.\n");
9055                 goto err_out_free_res;
9056         }
9057
9058         dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9059                                  &niu_pci_ops, PCI_FUNC(pdev->devfn));
9060         if (!dev) {
9061                 err = -ENOMEM;
9062                 goto err_out_free_res;
9063         }
9064         np = netdev_priv(dev);
9065
9066         memset(&parent_id, 0, sizeof(parent_id));
9067         parent_id.pci.domain = pci_domain_nr(pdev->bus);
9068         parent_id.pci.bus = pdev->bus->number;
9069         parent_id.pci.device = PCI_SLOT(pdev->devfn);
9070
9071         np->parent = niu_get_parent(np, &parent_id,
9072                                     PLAT_TYPE_ATLAS);
9073         if (!np->parent) {
9074                 err = -ENOMEM;
9075                 goto err_out_free_dev;
9076         }
9077
9078         pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9079         val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9080         val16 |= (PCI_EXP_DEVCTL_CERE |
9081                   PCI_EXP_DEVCTL_NFERE |
9082                   PCI_EXP_DEVCTL_FERE |
9083                   PCI_EXP_DEVCTL_URRE |
9084                   PCI_EXP_DEVCTL_RELAX_EN);
9085         pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9086
9087         dma_mask = DMA_44BIT_MASK;
9088         err = pci_set_dma_mask(pdev, dma_mask);
9089         if (!err) {
9090                 dev->features |= NETIF_F_HIGHDMA;
9091                 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9092                 if (err) {
9093                         dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
9094                                 "DMA for consistent allocations, "
9095                                 "aborting.\n");
9096                         goto err_out_release_parent;
9097                 }
9098         }
9099         if (err || dma_mask == DMA_32BIT_MASK) {
9100                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
9101                 if (err) {
9102                         dev_err(&pdev->dev, PFX "No usable DMA configuration, "
9103                                 "aborting.\n");
9104                         goto err_out_release_parent;
9105                 }
9106         }
9107
9108         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9109
9110         np->regs = pci_ioremap_bar(pdev, 0);
9111         if (!np->regs) {
9112                 dev_err(&pdev->dev, PFX "Cannot map device registers, "
9113                         "aborting.\n");
9114                 err = -ENOMEM;
9115                 goto err_out_release_parent;
9116         }
9117
9118         pci_set_master(pdev);
9119         pci_save_state(pdev);
9120
9121         dev->irq = pdev->irq;
9122
9123         niu_assign_netdev_ops(dev);
9124
9125         err = niu_get_invariants(np);
9126         if (err) {
9127                 if (err != -ENODEV)
9128                         dev_err(&pdev->dev, PFX "Problem fetching invariants "
9129                                 "of chip, aborting.\n");
9130                 goto err_out_iounmap;
9131         }
9132
9133         err = register_netdev(dev);
9134         if (err) {
9135                 dev_err(&pdev->dev, PFX "Cannot register net device, "
9136                         "aborting.\n");
9137                 goto err_out_iounmap;
9138         }
9139
9140         pci_set_drvdata(pdev, dev);
9141
9142         niu_device_announce(np);
9143
9144         return 0;
9145
9146 err_out_iounmap:
9147         if (np->regs) {
9148                 iounmap(np->regs);
9149                 np->regs = NULL;
9150         }
9151
9152 err_out_release_parent:
9153         niu_put_parent(np);
9154
9155 err_out_free_dev:
9156         free_netdev(dev);
9157
9158 err_out_free_res:
9159         pci_release_regions(pdev);
9160
9161 err_out_disable_pdev:
9162         pci_disable_device(pdev);
9163         pci_set_drvdata(pdev, NULL);
9164
9165         return err;
9166 }
9167
9168 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9169 {
9170         struct net_device *dev = pci_get_drvdata(pdev);
9171
9172         if (dev) {
9173                 struct niu *np = netdev_priv(dev);
9174
9175                 unregister_netdev(dev);
9176                 if (np->regs) {
9177                         iounmap(np->regs);
9178                         np->regs = NULL;
9179                 }
9180
9181                 niu_ldg_free(np);
9182
9183                 niu_put_parent(np);
9184
9185                 free_netdev(dev);
9186                 pci_release_regions(pdev);
9187                 pci_disable_device(pdev);
9188                 pci_set_drvdata(pdev, NULL);
9189         }
9190 }
9191
9192 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9193 {
9194         struct net_device *dev = pci_get_drvdata(pdev);
9195         struct niu *np = netdev_priv(dev);
9196         unsigned long flags;
9197
9198         if (!netif_running(dev))
9199                 return 0;
9200
9201         flush_scheduled_work();
9202         niu_netif_stop(np);
9203
9204         del_timer_sync(&np->timer);
9205
9206         spin_lock_irqsave(&np->lock, flags);
9207         niu_enable_interrupts(np, 0);
9208         spin_unlock_irqrestore(&np->lock, flags);
9209
9210         netif_device_detach(dev);
9211
9212         spin_lock_irqsave(&np->lock, flags);
9213         niu_stop_hw(np);
9214         spin_unlock_irqrestore(&np->lock, flags);
9215
9216         pci_save_state(pdev);
9217
9218         return 0;
9219 }
9220
9221 static int niu_resume(struct pci_dev *pdev)
9222 {
9223         struct net_device *dev = pci_get_drvdata(pdev);
9224         struct niu *np = netdev_priv(dev);
9225         unsigned long flags;
9226         int err;
9227
9228         if (!netif_running(dev))
9229                 return 0;
9230
9231         pci_restore_state(pdev);
9232
9233         netif_device_attach(dev);
9234
9235         spin_lock_irqsave(&np->lock, flags);
9236
9237         err = niu_init_hw(np);
9238         if (!err) {
9239                 np->timer.expires = jiffies + HZ;
9240                 add_timer(&np->timer);
9241                 niu_netif_start(np);
9242         }
9243
9244         spin_unlock_irqrestore(&np->lock, flags);
9245
9246         return err;
9247 }
9248
9249 static struct pci_driver niu_pci_driver = {
9250         .name           = DRV_MODULE_NAME,
9251         .id_table       = niu_pci_tbl,
9252         .probe          = niu_pci_init_one,
9253         .remove         = __devexit_p(niu_pci_remove_one),
9254         .suspend        = niu_suspend,
9255         .resume         = niu_resume,
9256 };
9257
9258 #ifdef CONFIG_SPARC64
9259 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9260                                      u64 *dma_addr, gfp_t flag)
9261 {
9262         unsigned long order = get_order(size);
9263         unsigned long page = __get_free_pages(flag, order);
9264
9265         if (page == 0UL)
9266                 return NULL;
9267         memset((char *)page, 0, PAGE_SIZE << order);
9268         *dma_addr = __pa(page);
9269
9270         return (void *) page;
9271 }
9272
9273 static void niu_phys_free_coherent(struct device *dev, size_t size,
9274                                    void *cpu_addr, u64 handle)
9275 {
9276         unsigned long order = get_order(size);
9277
9278         free_pages((unsigned long) cpu_addr, order);
9279 }
9280
9281 static u64 niu_phys_map_page(struct device *dev, struct page *page,
9282                              unsigned long offset, size_t size,
9283                              enum dma_data_direction direction)
9284 {
9285         return page_to_phys(page) + offset;
9286 }
9287
9288 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
9289                                 size_t size, enum dma_data_direction direction)
9290 {
9291         /* Nothing to do.  */
9292 }
9293
9294 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
9295                                size_t size,
9296                                enum dma_data_direction direction)
9297 {
9298         return __pa(cpu_addr);
9299 }
9300
9301 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
9302                                   size_t size,
9303                                   enum dma_data_direction direction)
9304 {
9305         /* Nothing to do.  */
9306 }
9307
9308 static const struct niu_ops niu_phys_ops = {
9309         .alloc_coherent = niu_phys_alloc_coherent,
9310         .free_coherent  = niu_phys_free_coherent,
9311         .map_page       = niu_phys_map_page,
9312         .unmap_page     = niu_phys_unmap_page,
9313         .map_single     = niu_phys_map_single,
9314         .unmap_single   = niu_phys_unmap_single,
9315 };
9316
9317 static unsigned long res_size(struct resource *r)
9318 {
9319         return r->end - r->start + 1UL;
9320 }
9321
9322 static int __devinit niu_of_probe(struct of_device *op,
9323                                   const struct of_device_id *match)
9324 {
9325         union niu_parent_id parent_id;
9326         struct net_device *dev;
9327         struct niu *np;
9328         const u32 *reg;
9329         int err;
9330
9331         niu_driver_version();
9332
9333         reg = of_get_property(op->node, "reg", NULL);
9334         if (!reg) {
9335                 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
9336                         op->node->full_name);
9337                 return -ENODEV;
9338         }
9339
9340         dev = niu_alloc_and_init(&op->dev, NULL, op,
9341                                  &niu_phys_ops, reg[0] & 0x1);
9342         if (!dev) {
9343                 err = -ENOMEM;
9344                 goto err_out;
9345         }
9346         np = netdev_priv(dev);
9347
9348         memset(&parent_id, 0, sizeof(parent_id));
9349         parent_id.of = of_get_parent(op->node);
9350
9351         np->parent = niu_get_parent(np, &parent_id,
9352                                     PLAT_TYPE_NIU);
9353         if (!np->parent) {
9354                 err = -ENOMEM;
9355                 goto err_out_free_dev;
9356         }
9357
9358         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9359
9360         np->regs = of_ioremap(&op->resource[1], 0,
9361                               res_size(&op->resource[1]),
9362                               "niu regs");
9363         if (!np->regs) {
9364                 dev_err(&op->dev, PFX "Cannot map device registers, "
9365                         "aborting.\n");
9366                 err = -ENOMEM;
9367                 goto err_out_release_parent;
9368         }
9369
9370         np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
9371                                     res_size(&op->resource[2]),
9372                                     "niu vregs-1");
9373         if (!np->vir_regs_1) {
9374                 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
9375                         "aborting.\n");
9376                 err = -ENOMEM;
9377                 goto err_out_iounmap;
9378         }
9379
9380         np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
9381                                     res_size(&op->resource[3]),
9382                                     "niu vregs-2");
9383         if (!np->vir_regs_2) {
9384                 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
9385                         "aborting.\n");
9386                 err = -ENOMEM;
9387                 goto err_out_iounmap;
9388         }
9389
9390         niu_assign_netdev_ops(dev);
9391
9392         err = niu_get_invariants(np);
9393         if (err) {
9394                 if (err != -ENODEV)
9395                         dev_err(&op->dev, PFX "Problem fetching invariants "
9396                                 "of chip, aborting.\n");
9397                 goto err_out_iounmap;
9398         }
9399
9400         err = register_netdev(dev);
9401         if (err) {
9402                 dev_err(&op->dev, PFX "Cannot register net device, "
9403                         "aborting.\n");
9404                 goto err_out_iounmap;
9405         }
9406
9407         dev_set_drvdata(&op->dev, dev);
9408
9409         niu_device_announce(np);
9410
9411         return 0;
9412
9413 err_out_iounmap:
9414         if (np->vir_regs_1) {
9415                 of_iounmap(&op->resource[2], np->vir_regs_1,
9416                            res_size(&op->resource[2]));
9417                 np->vir_regs_1 = NULL;
9418         }
9419
9420         if (np->vir_regs_2) {
9421                 of_iounmap(&op->resource[3], np->vir_regs_2,
9422                            res_size(&op->resource[3]));
9423                 np->vir_regs_2 = NULL;
9424         }
9425
9426         if (np->regs) {
9427                 of_iounmap(&op->resource[1], np->regs,
9428                            res_size(&op->resource[1]));
9429                 np->regs = NULL;
9430         }
9431
9432 err_out_release_parent:
9433         niu_put_parent(np);
9434
9435 err_out_free_dev:
9436         free_netdev(dev);
9437
9438 err_out:
9439         return err;
9440 }
9441
9442 static int __devexit niu_of_remove(struct of_device *op)
9443 {
9444         struct net_device *dev = dev_get_drvdata(&op->dev);
9445
9446         if (dev) {
9447                 struct niu *np = netdev_priv(dev);
9448
9449                 unregister_netdev(dev);
9450
9451                 if (np->vir_regs_1) {
9452                         of_iounmap(&op->resource[2], np->vir_regs_1,
9453                                    res_size(&op->resource[2]));
9454                         np->vir_regs_1 = NULL;
9455                 }
9456
9457                 if (np->vir_regs_2) {
9458                         of_iounmap(&op->resource[3], np->vir_regs_2,
9459                                    res_size(&op->resource[3]));
9460                         np->vir_regs_2 = NULL;
9461                 }
9462
9463                 if (np->regs) {
9464                         of_iounmap(&op->resource[1], np->regs,
9465                                    res_size(&op->resource[1]));
9466                         np->regs = NULL;
9467                 }
9468
9469                 niu_ldg_free(np);
9470
9471                 niu_put_parent(np);
9472
9473                 free_netdev(dev);
9474                 dev_set_drvdata(&op->dev, NULL);
9475         }
9476         return 0;
9477 }
9478
9479 static const struct of_device_id niu_match[] = {
9480         {
9481                 .name = "network",
9482                 .compatible = "SUNW,niusl",
9483         },
9484         {},
9485 };
9486 MODULE_DEVICE_TABLE(of, niu_match);
9487
9488 static struct of_platform_driver niu_of_driver = {
9489         .name           = "niu",
9490         .match_table    = niu_match,
9491         .probe          = niu_of_probe,
9492         .remove         = __devexit_p(niu_of_remove),
9493 };
9494
9495 #endif /* CONFIG_SPARC64 */
9496
9497 static int __init niu_init(void)
9498 {
9499         int err = 0;
9500
9501         BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
9502
9503         niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
9504
9505 #ifdef CONFIG_SPARC64
9506         err = of_register_driver(&niu_of_driver, &of_bus_type);
9507 #endif
9508
9509         if (!err) {
9510                 err = pci_register_driver(&niu_pci_driver);
9511 #ifdef CONFIG_SPARC64
9512                 if (err)
9513                         of_unregister_driver(&niu_of_driver);
9514 #endif
9515         }
9516
9517         return err;
9518 }
9519
9520 static void __exit niu_exit(void)
9521 {
9522         pci_unregister_driver(&niu_pci_driver);
9523 #ifdef CONFIG_SPARC64
9524         of_unregister_driver(&niu_of_driver);
9525 #endif
9526 }
9527
9528 module_init(niu_init);
9529 module_exit(niu_exit);