2 * Copyright (C) 2003 - 2009 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
27 * Cupertino, CA 95014-0701
31 #ifndef _NETXEN_NIC_H_
32 #define _NETXEN_NIC_H_
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/ioport.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
43 #include <linux/tcp.h>
44 #include <linux/skbuff.h>
45 #include <linux/firmware.h>
47 #include <linux/ethtool.h>
48 #include <linux/mii.h>
49 #include <linux/timer.h>
51 #include <linux/vmalloc.h>
54 #include <asm/byteorder.h>
56 #include "netxen_nic_hw.h"
58 #define _NETXEN_NIC_LINUX_MAJOR 4
59 #define _NETXEN_NIC_LINUX_MINOR 0
60 #define _NETXEN_NIC_LINUX_SUBVERSION 41
61 #define NETXEN_NIC_LINUX_VERSIONID "4.0.41"
63 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
64 #define _major(v) (((v) >> 24) & 0xff)
65 #define _minor(v) (((v) >> 16) & 0xff)
66 #define _build(v) ((v) & 0xffff)
68 /* version in image has weird encoding:
71 * 31:16 - build (little endian)
73 #define NETXEN_DECODE_VERSION(v) \
74 NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
76 #define NETXEN_NUM_FLASH_SECTORS (64)
77 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
78 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
79 * NETXEN_FLASH_SECTOR_SIZE)
81 #define PHAN_VENDOR_ID 0x4040
83 #define RCV_DESC_RINGSIZE(rds_ring) \
84 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
85 #define RCV_BUFF_RINGSIZE(rds_ring) \
86 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
87 #define STATUS_DESC_RINGSIZE(sds_ring) \
88 (sizeof(struct status_desc) * (sds_ring)->num_desc)
89 #define TX_BUFF_RINGSIZE(tx_ring) \
90 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
91 #define TX_DESC_RINGSIZE(tx_ring) \
92 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
94 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
96 #define NETXEN_RCV_PRODUCER_OFFSET 0
97 #define NETXEN_RCV_PEG_DB_ID 2
98 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
99 #define FLASH_SUCCESS 0
101 #define ADDR_IN_WINDOW1(off) \
102 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
105 * normalize a 64MB crb address to 32MB PCI window
106 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
108 #define NETXEN_CRB_NORMAL(reg) \
109 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
111 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
112 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
114 #define DB_NORMALIZE(adapter, off) \
115 (adapter->ahw.db_base + (off))
117 #define NX_P2_C0 0x24
118 #define NX_P2_C1 0x25
119 #define NX_P3_A0 0x30
120 #define NX_P3_A2 0x30
121 #define NX_P3_B0 0x40
122 #define NX_P3_B1 0x41
123 #define NX_P3_B2 0x42
125 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
126 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
128 #define FIRST_PAGE_GROUP_START 0
129 #define FIRST_PAGE_GROUP_END 0x100000
131 #define SECOND_PAGE_GROUP_START 0x6000000
132 #define SECOND_PAGE_GROUP_END 0x68BC000
134 #define THIRD_PAGE_GROUP_START 0x70E4000
135 #define THIRD_PAGE_GROUP_END 0x8000000
137 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
138 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
139 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
141 #define P2_MAX_MTU (8000)
142 #define P3_MAX_MTU (9600)
143 #define NX_ETHERMTU 1500
144 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
146 #define NX_P2_RX_BUF_MAX_LEN 1760
147 #define NX_P3_RX_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
148 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
149 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
150 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
152 #define NX_RX_LRO_BUFFER_LENGTH (8060)
155 * Maximum number of ring contexts
157 #define MAX_RING_CTX 1
159 /* Opcodes to be used with the commands */
160 #define TX_ETHER_PKT 0x01
161 #define TX_TCP_PKT 0x02
162 #define TX_UDP_PKT 0x03
163 #define TX_IP_PKT 0x04
164 #define TX_TCP_LSO 0x05
165 #define TX_TCP_LSO6 0x06
166 #define TX_IPSEC 0x07
167 #define TX_IPSEC_CMD 0x0a
168 #define TX_TCPV6_PKT 0x0b
169 #define TX_UDPV6_PKT 0x0c
171 /* The following opcodes are for internal consumption. */
172 #define NETXEN_CONTROL_OP 0x10
173 #define PEGNET_REQUEST 0x11
175 #define MAX_NUM_CARDS 4
177 #define MAX_BUFFERS_PER_CMD 32
178 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4)
181 * Following are the states of the Phantom. Phantom will set them and
182 * Host will read to check if the fields are correct.
184 #define PHAN_INITIALIZE_START 0xff00
185 #define PHAN_INITIALIZE_FAILED 0xffff
186 #define PHAN_INITIALIZE_COMPLETE 0xff01
188 /* Host writes the following to notify that it has done the init-handshake */
189 #define PHAN_INITIALIZE_ACK 0xf00f
191 #define NUM_RCV_DESC_RINGS 3
192 #define NUM_STS_DESC_RINGS 4
194 #define RCV_RING_NORMAL 0
195 #define RCV_RING_JUMBO 1
196 #define RCV_RING_LRO 2
198 #define MIN_CMD_DESCRIPTORS 64
199 #define MIN_RCV_DESCRIPTORS 64
200 #define MIN_JUMBO_DESCRIPTORS 32
202 #define MAX_CMD_DESCRIPTORS 1024
203 #define MAX_RCV_DESCRIPTORS_1G 4096
204 #define MAX_RCV_DESCRIPTORS_10G 8192
205 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
206 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
207 #define MAX_LRO_RCV_DESCRIPTORS 8
209 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
210 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
212 #define NETXEN_CTX_SIGNATURE 0xdee0
213 #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
214 #define NETXEN_CTX_RESET 0xbad0
215 #define NETXEN_CTX_D3_RESET 0xacc0
216 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
218 #define PHAN_PEG_RCV_INITIALIZED 0xff01
219 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
221 #define get_next_index(index, length) \
222 (((index) + 1) & ((length) - 1))
224 #define get_index_range(index,length,count) \
225 (((index) + (count)) & ((length) - 1))
227 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
228 #define MPORT_MULTI_FUNCTION_MODE 0x2222
230 #include "netxen_nic_phan_reg.h"
233 * NetXen host-peg signal message structure
235 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
236 * Bit 2 : priv_id => must be 1
237 * Bit 3-17 : count => for doorbell
238 * Bit 18-27 : ctx_id => Context id
242 typedef u32 netxen_ctx_msg;
244 #define netxen_set_msg_peg_id(config_word, val) \
245 ((config_word) &= ~3, (config_word) |= val & 3)
246 #define netxen_set_msg_privid(config_word) \
247 ((config_word) |= 1 << 2)
248 #define netxen_set_msg_count(config_word, val) \
249 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
250 #define netxen_set_msg_ctxid(config_word, val) \
251 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
252 #define netxen_set_msg_opcode(config_word, val) \
253 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
255 struct netxen_rcv_ring {
261 struct netxen_sts_ring {
268 struct netxen_ring_ctx {
270 /* one command ring */
271 __le64 cmd_consumer_offset;
272 __le64 cmd_ring_addr;
273 __le32 cmd_ring_size;
276 /* three receive rings */
277 struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
279 __le64 sts_ring_addr;
280 __le32 sts_ring_size;
285 __le32 sts_ring_count;
287 struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
289 } __attribute__ ((aligned(64)));
292 * Following data structures describe the descriptors that will be used.
293 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
294 * we are doing LSO (above the 1500 size packet) only.
298 * The size of reference handle been changed to 16 bits to pass the MSS fields
302 #define FLAGS_CHECKSUM_ENABLED 0x01
303 #define FLAGS_LSO_ENABLED 0x02
304 #define FLAGS_IPSEC_SA_ADD 0x04
305 #define FLAGS_IPSEC_SA_DELETE 0x08
306 #define FLAGS_VLAN_TAGGED 0x10
307 #define FLAGS_VLAN_OOB 0x40
309 #define netxen_set_tx_vlan_tci(cmd_desc, v) \
310 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
312 #define netxen_set_cmd_desc_port(cmd_desc, var) \
313 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
314 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
315 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
317 #define netxen_set_tx_port(_desc, _port) \
318 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
320 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
321 (_desc)->flags_opcode = \
322 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
324 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
325 (_desc)->nfrags__length = \
326 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
328 struct cmd_desc_type0 {
329 u8 tcp_hdr_offset; /* For LSO only */
330 u8 ip_hdr_offset; /* For LSO only */
331 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
332 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
336 __le16 reference_handle;
338 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
339 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
340 __le16 conn_id; /* IPSec offoad only */
345 __le16 buffer_length[4];
353 } __attribute__ ((aligned(64)));
355 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
357 __le16 reference_handle;
359 __le32 buffer_length; /* allocated buffer length (usually 2K) */
363 /* opcode field in status_desc */
364 #define NETXEN_NIC_SYN_OFFLOAD 0x03
365 #define NETXEN_NIC_RXPKT_DESC 0x04
366 #define NETXEN_OLD_RXPKT_DESC 0x3f
367 #define NETXEN_NIC_RESPONSE_DESC 0x05
369 /* for status field in status_desc */
370 #define STATUS_NEED_CKSUM (1)
371 #define STATUS_CKSUM_OK (2)
373 /* owner bits of status_desc */
374 #define STATUS_OWNER_HOST (0x1ULL << 56)
375 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
377 /* Status descriptor:
378 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
379 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
380 53-55 desc_cnt, 56-57 owner, 58-63 opcode
382 #define netxen_get_sts_port(sts_data) \
384 #define netxen_get_sts_status(sts_data) \
385 (((sts_data) >> 4) & 0x0F)
386 #define netxen_get_sts_type(sts_data) \
387 (((sts_data) >> 8) & 0x0F)
388 #define netxen_get_sts_totallength(sts_data) \
389 (((sts_data) >> 12) & 0xFFFF)
390 #define netxen_get_sts_refhandle(sts_data) \
391 (((sts_data) >> 28) & 0xFFFF)
392 #define netxen_get_sts_prot(sts_data) \
393 (((sts_data) >> 44) & 0x0F)
394 #define netxen_get_sts_pkt_offset(sts_data) \
395 (((sts_data) >> 48) & 0x1F)
396 #define netxen_get_sts_desc_cnt(sts_data) \
397 (((sts_data) >> 53) & 0x7)
398 #define netxen_get_sts_opcode(sts_data) \
399 (((sts_data) >> 58) & 0x03F)
402 __le64 status_desc_data[2];
403 } __attribute__ ((aligned(16)));
405 /* The version of the main data structure */
406 #define NETXEN_BDINFO_VERSION 1
408 /* Magic number to let user know flash is programmed */
409 #define NETXEN_BDINFO_MAGIC 0x12345678
411 /* Max number of Gig ports on a Phantom board */
412 #define NETXEN_MAX_PORTS 4
414 #define NETXEN_BRDTYPE_P1_BD 0x0000
415 #define NETXEN_BRDTYPE_P1_SB 0x0001
416 #define NETXEN_BRDTYPE_P1_SMAX 0x0002
417 #define NETXEN_BRDTYPE_P1_SOCK 0x0003
419 #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
420 #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
421 #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
422 #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
423 #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
425 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
426 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
427 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
429 #define NETXEN_BRDTYPE_P3_REF_QG 0x0021
430 #define NETXEN_BRDTYPE_P3_HMEZ 0x0022
431 #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
432 #define NETXEN_BRDTYPE_P3_4_GB 0x0024
433 #define NETXEN_BRDTYPE_P3_IMEZ 0x0025
434 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
435 #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
436 #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
437 #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
438 #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
439 #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
440 #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
441 #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
442 #define NETXEN_BRDTYPE_P3_10G_TP 0x0080
444 struct netxen_board_info {
456 u32 port_mask; /* available niu ports */
457 u32 peg_mask; /* available pegs */
458 u32 icache_ok; /* can we run with icache? */
459 u32 dcache_ok; /* can we run with dcache? */
467 /* MN-related config */
468 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
469 u32 mn_sync_shift_cclk;
470 u32 mn_sync_shift_mclk;
472 u32 mn_crystal_freq; /* in MHz */
473 u32 mn_speed; /* in MHz */
476 u32 mn_ranks_0; /* ranks per slot */
477 u32 mn_ranks_1; /* ranks per slot */
488 u32 mn_mode_reg; /* MIU DDR Mode Register */
489 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
490 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
491 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
492 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
494 /* SN-related config */
495 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
496 u32 sn_pt_mode; /* pass through mode */
511 u32 magic; /* indicates flash has been initialized */
518 #define FLASH_NUM_PORTS (4)
520 struct netxen_flash_mac_addr {
524 struct netxen_user_old_info {
536 /* primary image status */
538 u32 secondary_present;
540 /* MAC address , 4 ports */
541 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
543 #define FLASH_NUM_MAC_PER_PORT 32
544 struct netxen_user_info {
545 u8 flash_md5[16 * 64];
552 /* primary image status */
554 u32 secondary_present;
556 /* MAC address , 4 ports, 32 address per port */
557 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
561 /* Any user defined data */
565 * Flash Layout - new format.
567 struct netxen_new_user_info {
568 u8 flash_md5[16 * 64];
575 /* primary image status */
577 u32 secondary_present;
579 /* MAC address , 4 ports, 32 address per port */
580 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
584 /* Any user defined data */
587 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
588 #define SECONDARY_IMAGE_ABSENT 0xffffffff
589 #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
590 #define PRIMARY_IMAGE_BAD 0xffffffff
592 /* Flash memory map */
593 #define NETXEN_CRBINIT_START 0 /* crbinit section */
594 #define NETXEN_BRDCFG_START 0x4000 /* board config */
595 #define NETXEN_INITCODE_START 0x6000 /* pegtune code */
596 #define NETXEN_BOOTLD_START 0x10000 /* bootld */
597 #define NETXEN_IMAGE_START 0x43000 /* compressed image */
598 #define NETXEN_SECONDARY_START 0x200000 /* backup images */
599 #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
600 #define NETXEN_USER_START 0x3E8000 /* Firmare info */
601 #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
603 #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
604 #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
605 #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
606 #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
607 #define NX_FW_MIN_SIZE (0x3fffff)
608 #define NX_P2_MN_ROMIMAGE 0
609 #define NX_P3_CT_ROMIMAGE 1
610 #define NX_P3_MN_ROMIMAGE 2
611 #define NX_FLASH_ROMIMAGE 3
613 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
615 #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
616 #define NETXEN_INIT_SECTOR (0)
617 #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
618 #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
619 #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
620 #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
621 #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
622 #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
623 #define NETXEN_NUM_CONFIG_SECTORS (1)
624 extern char netxen_nic_driver_name[];
626 /* Number of status descriptors to handle per interrupt */
627 #define MAX_STATUS_HANDLE (64)
630 * netxen_skb_frag{} is to contain mapping info for each SG list. This
631 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
633 struct netxen_skb_frag {
638 #define _netxen_set_bits(config_word, start, bits, val) {\
639 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
640 unsigned long long __tvalue = (val); \
641 (config_word) &= ~__tmask; \
642 (config_word) |= (((__tvalue) << (start)) & __tmask); \
645 #define _netxen_clear_bits(config_word, start, bits) {\
646 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
647 (config_word) &= ~__tmask; \
650 /* Following defines are for the state of the buffers */
651 #define NETXEN_BUFFER_FREE 0
652 #define NETXEN_BUFFER_BUSY 1
655 * There will be one netxen_buffer per skb packet. These will be
656 * used to save the dma info for pci_unmap_page()
658 struct netxen_cmd_buffer {
660 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
664 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
665 struct netxen_rx_buffer {
666 struct list_head list;
674 #define NETXEN_NIC_GBE 0x01
675 #define NETXEN_NIC_XGBE 0x02
678 * One hardware_context{} per adapter
679 * contains interrupt info as well shared hardware info.
681 struct netxen_hardware_context {
682 void __iomem *pci_base0;
683 void __iomem *pci_base1;
684 void __iomem *pci_base2;
685 void __iomem *db_base;
686 unsigned long db_len;
687 unsigned long pci_len0;
691 unsigned long mn_win_crb;
692 unsigned long ms_win_crb;
702 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
703 #define ETHERNET_FCS_SIZE 4
705 struct netxen_adapter_stats {
717 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
718 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
720 struct nx_host_rds_ring {
722 u32 crb_rcv_producer;
727 struct rcv_desc *desc_head;
728 struct netxen_rx_buffer *rx_buf_arr;
729 struct list_head free_list;
731 dma_addr_t phys_addr;
734 struct nx_host_sds_ring {
736 u32 crb_sts_consumer;
740 struct status_desc *desc_head;
741 struct netxen_adapter *adapter;
742 struct napi_struct napi;
743 struct list_head free_list[NUM_RCV_DESC_RINGS];
747 dma_addr_t phys_addr;
748 char name[IFNAMSIZ+4];
751 struct nx_host_tx_ring {
755 u32 crb_cmd_producer;
756 u32 crb_cmd_consumer;
759 struct netdev_queue *txq;
761 struct netxen_cmd_buffer *cmd_buf_arr;
762 struct cmd_desc_type0 *desc_head;
763 dma_addr_t phys_addr;
767 * Receive context. There is one such structure per instance of the
768 * receive processing. Any state information that is relevant to
769 * the receive, and is must be in this structure. The global data may be
772 struct netxen_recv_context {
777 struct nx_host_rds_ring *rds_rings;
778 struct nx_host_sds_ring *sds_rings;
780 struct netxen_ring_ctx *hwctx;
781 dma_addr_t phys_addr;
784 /* New HW context creation */
786 #define NX_OS_CRB_RETRY_COUNT 4000
787 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
788 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
790 #define NX_CDRP_CLEAR 0x00000000
791 #define NX_CDRP_CMD_BIT 0x80000000
794 * All responses must have the NX_CDRP_CMD_BIT cleared
795 * in the crb NX_CDRP_CRB_OFFSET.
797 #define NX_CDRP_FORM_RSP(rsp) (rsp)
798 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
800 #define NX_CDRP_RSP_OK 0x00000001
801 #define NX_CDRP_RSP_FAIL 0x00000002
802 #define NX_CDRP_RSP_TIMEOUT 0x00000003
805 * All commands must have the NX_CDRP_CMD_BIT set in
806 * the crb NX_CDRP_CRB_OFFSET.
808 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
809 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
811 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
812 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
813 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
814 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
815 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
816 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
817 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
818 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
819 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
820 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
821 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
822 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
823 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
824 #define NX_CDRP_CMD_SET_MTU 0x00000012
825 #define NX_CDRP_CMD_MAX 0x00000013
827 #define NX_RCODE_SUCCESS 0
828 #define NX_RCODE_NO_HOST_MEM 1
829 #define NX_RCODE_NO_HOST_RESOURCE 2
830 #define NX_RCODE_NO_CARD_CRB 3
831 #define NX_RCODE_NO_CARD_MEM 4
832 #define NX_RCODE_NO_CARD_RESOURCE 5
833 #define NX_RCODE_INVALID_ARGS 6
834 #define NX_RCODE_INVALID_ACTION 7
835 #define NX_RCODE_INVALID_STATE 8
836 #define NX_RCODE_NOT_SUPPORTED 9
837 #define NX_RCODE_NOT_PERMITTED 10
838 #define NX_RCODE_NOT_READY 11
839 #define NX_RCODE_DOES_NOT_EXIST 12
840 #define NX_RCODE_ALREADY_EXISTS 13
841 #define NX_RCODE_BAD_SIGNATURE 14
842 #define NX_RCODE_CMD_NOT_IMPL 15
843 #define NX_RCODE_CMD_INVALID 16
844 #define NX_RCODE_TIMEOUT 17
845 #define NX_RCODE_CMD_FAILED 18
846 #define NX_RCODE_MAX_EXCEEDED 19
847 #define NX_RCODE_MAX 20
849 #define NX_DESTROY_CTX_RESET 0
850 #define NX_DESTROY_CTX_D3_RESET 1
851 #define NX_DESTROY_CTX_MAX 2
856 #define NX_CAP_BIT(class, bit) (1 << bit)
857 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
858 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
859 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
860 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
861 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
862 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
863 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
864 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
865 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
870 #define NX_HOST_CTX_STATE_FREED 0
871 #define NX_HOST_CTX_STATE_ALLOCATED 1
872 #define NX_HOST_CTX_STATE_ACTIVE 2
873 #define NX_HOST_CTX_STATE_DISABLED 3
874 #define NX_HOST_CTX_STATE_QUIESCED 4
875 #define NX_HOST_CTX_STATE_MAX 5
882 __le64 host_phys_addr; /* Ring base addr */
883 __le32 ring_size; /* Ring entries */
885 __le16 rsvd; /* Padding */
886 } nx_hostrq_sds_ring_t;
889 __le64 host_phys_addr; /* Ring base addr */
890 __le64 buff_size; /* Packet buffer size */
891 __le32 ring_size; /* Ring entries */
892 __le32 ring_kind; /* Class of ring */
893 } nx_hostrq_rds_ring_t;
896 __le64 host_rsp_dma_addr; /* Response dma'd here */
897 __le32 capabilities[4]; /* Flag bit vector */
898 __le32 host_int_crb_mode; /* Interrupt crb usage */
899 __le32 host_rds_crb_mode; /* RDS crb usage */
900 /* These ring offsets are relative to data[0] below */
901 __le32 rds_ring_offset; /* Offset to RDS config */
902 __le32 sds_ring_offset; /* Offset to SDS config */
903 __le16 num_rds_rings; /* Count of RDS rings */
904 __le16 num_sds_rings; /* Count of SDS rings */
905 __le16 rsvd1; /* Padding */
906 __le16 rsvd2; /* Padding */
907 u8 reserved[128]; /* reserve space for future expansion*/
908 /* MUST BE 64-bit aligned.
909 The following is packed:
911 - N hostrq_sds_rings */
913 } nx_hostrq_rx_ctx_t;
916 __le32 host_producer_crb; /* Crb to use */
917 __le32 rsvd1; /* Padding */
918 } nx_cardrsp_rds_ring_t;
921 __le32 host_consumer_crb; /* Crb to use */
922 __le32 interrupt_crb; /* Crb to use */
923 } nx_cardrsp_sds_ring_t;
926 /* These ring offsets are relative to data[0] below */
927 __le32 rds_ring_offset; /* Offset to RDS config */
928 __le32 sds_ring_offset; /* Offset to SDS config */
929 __le32 host_ctx_state; /* Starting State */
930 __le32 num_fn_per_port; /* How many PCI fn share the port */
931 __le16 num_rds_rings; /* Count of RDS rings */
932 __le16 num_sds_rings; /* Count of SDS rings */
933 __le16 context_id; /* Handle for context */
934 u8 phys_port; /* Physical id of port */
935 u8 virt_port; /* Virtual/Logical id of port */
936 u8 reserved[128]; /* save space for future expansion */
937 /* MUST BE 64-bit aligned.
938 The following is packed:
939 - N cardrsp_rds_rings
940 - N cardrs_sds_rings */
942 } nx_cardrsp_rx_ctx_t;
944 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
945 (sizeof(HOSTRQ_RX) + \
946 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
947 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
949 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
950 (sizeof(CARDRSP_RX) + \
951 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
952 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
959 __le64 host_phys_addr; /* Ring base addr */
960 __le32 ring_size; /* Ring entries */
961 __le32 rsvd; /* Padding */
962 } nx_hostrq_cds_ring_t;
965 __le64 host_rsp_dma_addr; /* Response dma'd here */
966 __le64 cmd_cons_dma_addr; /* */
967 __le64 dummy_dma_addr; /* */
968 __le32 capabilities[4]; /* Flag bit vector */
969 __le32 host_int_crb_mode; /* Interrupt crb usage */
970 __le32 rsvd1; /* Padding */
971 __le16 rsvd2; /* Padding */
972 __le16 interrupt_ctl;
974 __le16 rsvd3; /* Padding */
975 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
976 u8 reserved[128]; /* future expansion */
977 } nx_hostrq_tx_ctx_t;
980 __le32 host_producer_crb; /* Crb to use */
981 __le32 interrupt_crb; /* Crb to use */
982 } nx_cardrsp_cds_ring_t;
985 __le32 host_ctx_state; /* Starting state */
986 __le16 context_id; /* Handle for context */
987 u8 phys_port; /* Physical id of port */
988 u8 virt_port; /* Virtual/Logical id of port */
989 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
990 u8 reserved[128]; /* future expansion */
991 } nx_cardrsp_tx_ctx_t;
993 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
994 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
998 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
999 #define NX_HOST_RDS_CRB_MODE_SHARED 1
1000 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
1001 #define NX_HOST_RDS_CRB_MODE_MAX 3
1003 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
1004 #define NX_HOST_INT_CRB_MODE_SHARED 1
1005 #define NX_HOST_INT_CRB_MODE_NORX 2
1006 #define NX_HOST_INT_CRB_MODE_NOTX 3
1007 #define NX_HOST_INT_CRB_MODE_NORXTX 4
1012 #define MC_COUNT_P2 16
1013 #define MC_COUNT_P3 38
1015 #define NETXEN_MAC_NOOP 0
1016 #define NETXEN_MAC_ADD 1
1017 #define NETXEN_MAC_DEL 2
1019 typedef struct nx_mac_list_s {
1020 struct list_head list;
1021 uint8_t mac_addr[ETH_ALEN+2];
1025 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1026 * adjusted based on configured MTU.
1028 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1029 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1030 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1031 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1033 #define NETXEN_NIC_INTR_DEFAULT 0x04
1037 uint16_t rx_packets;
1038 uint16_t rx_time_us;
1039 uint16_t tx_packets;
1040 uint16_t tx_time_us;
1043 } nx_nic_intr_coalesce_data_t;
1046 uint16_t stats_time_us;
1047 uint16_t rate_sample_time;
1050 uint32_t low_threshold;
1051 uint32_t high_threshold;
1052 nx_nic_intr_coalesce_data_t normal;
1053 nx_nic_intr_coalesce_data_t low;
1054 nx_nic_intr_coalesce_data_t high;
1055 nx_nic_intr_coalesce_data_t irq;
1056 } nx_nic_intr_coalesce_t;
1058 #define NX_HOST_REQUEST 0x13
1059 #define NX_NIC_REQUEST 0x14
1061 #define NX_MAC_EVENT 0x1
1064 #define NX_IP_DOWN 3
1067 * Driver --> Firmware
1069 #define NX_NIC_H2C_OPCODE_START 0
1070 #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
1071 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
1072 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
1073 #define NX_NIC_H2C_OPCODE_CONFIG_LED 4
1074 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
1075 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
1076 #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
1077 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
1078 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
1079 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
1080 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
1081 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
1082 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
1083 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
1084 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
1085 #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
1086 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
1087 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
1088 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
1089 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
1090 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
1091 #define NX_NIC_C2C_OPCODE 22
1092 #define NX_NIC_H2C_OPCODE_LAST 23
1095 * Firmware --> Driver
1098 #define NX_NIC_C2H_OPCODE_START 128
1099 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
1100 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
1101 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
1102 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
1103 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
1104 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
1105 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
1106 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
1107 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
1108 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
1109 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1110 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
1111 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
1112 #define NX_NIC_C2H_OPCODE_LAST 142
1114 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1115 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1116 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1118 #define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5)
1119 #define NX_FW_CAPABILITY_SWITCHING (1 << 6)
1120 #define NX_FW_CAPABILITY_PEXQ (1 << 7)
1121 #define NX_FW_CAPABILITY_BDG (1 << 8)
1122 #define NX_FW_CAPABILITY_FVLANTX (1 << 9)
1125 #define LINKEVENT_MODULE_NOT_PRESENT 1
1126 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
1127 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
1128 #define LINKEVENT_MODULE_OPTICAL_LRM 4
1129 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
1130 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
1131 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
1132 #define LINKEVENT_MODULE_TWINAX 8
1134 #define LINKSPEED_10GBPS 10000
1135 #define LINKSPEED_1GBPS 1000
1136 #define LINKSPEED_100MBPS 100
1137 #define LINKSPEED_10MBPS 10
1139 #define LINKSPEED_ENCODED_10MBPS 0
1140 #define LINKSPEED_ENCODED_100MBPS 1
1141 #define LINKSPEED_ENCODED_1GBPS 2
1143 #define LINKEVENT_AUTONEG_DISABLED 0
1144 #define LINKEVENT_AUTONEG_ENABLED 1
1146 #define LINKEVENT_HALF_DUPLEX 0
1147 #define LINKEVENT_FULL_DUPLEX 1
1149 #define LINKEVENT_LINKSPEED_MBPS 0
1150 #define LINKEVENT_LINKSPEED_ENCODED 1
1152 /* firmware response header:
1153 * 63:58 - message type
1155 * 55:53 - desc count
1157 * 47:40 - completion id
1159 * 31:16 - error code
1162 #define netxen_get_nic_msgtype(msg_hdr) \
1163 ((msg_hdr >> 58) & 0x3F)
1164 #define netxen_get_nic_msg_compid(msg_hdr) \
1165 ((msg_hdr >> 40) & 0xFF)
1166 #define netxen_get_nic_msg_opcode(msg_hdr) \
1167 ((msg_hdr >> 32) & 0xFF)
1168 #define netxen_get_nic_msg_errcode(msg_hdr) \
1169 ((msg_hdr >> 16) & 0xFFFF)
1193 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1195 #define NETXEN_NIC_MSI_ENABLED 0x02
1196 #define NETXEN_NIC_MSIX_ENABLED 0x04
1197 #define NETXEN_IS_MSI_FAMILY(adapter) \
1198 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1200 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
1201 #define NETXEN_MSIX_TBL_SPACE 8192
1202 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1204 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1206 #define NETXEN_NETDEV_WEIGHT 128
1207 #define NETXEN_ADAPTER_UP_MAGIC 777
1208 #define NETXEN_NIC_PEG_TUNE 0
1210 struct netxen_dummy_dma {
1212 dma_addr_t phys_addr;
1215 struct netxen_adapter {
1216 struct netxen_hardware_context ahw;
1218 struct net_device *netdev;
1219 struct pci_dev *pdev;
1220 struct list_head mac_list;
1224 rwlock_t adapter_lock;
1226 spinlock_t tx_clean_lock;
1267 struct netxen_adapter_stats stats;
1269 struct netxen_recv_context recv_ctx;
1270 struct nx_host_tx_ring *tx_ring;
1272 int (*enable_phy_interrupts) (struct netxen_adapter *);
1273 int (*disable_phy_interrupts) (struct netxen_adapter *);
1274 int (*macaddr_set) (struct netxen_adapter *, u8 *);
1275 int (*set_mtu) (struct netxen_adapter *, int);
1276 int (*set_promisc) (struct netxen_adapter *, u32);
1277 void (*set_multi) (struct net_device *);
1278 int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1279 int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1280 int (*init_port) (struct netxen_adapter *, int);
1281 int (*stop_port) (struct netxen_adapter *);
1283 u32 (*hw_read_wx)(struct netxen_adapter *, ulong);
1284 int (*hw_write_wx)(struct netxen_adapter *, ulong, u32);
1285 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1286 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1287 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1288 u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1289 unsigned long (*pci_set_window)(struct netxen_adapter *,
1290 unsigned long long);
1292 struct netxen_legacy_intr_set legacy_intr;
1294 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1296 struct netxen_dummy_dma dummy_dma;
1298 struct work_struct watchdog_task;
1299 struct timer_list watchdog_timer;
1300 struct work_struct tx_timeout_task;
1302 struct net_device_stats net_stats;
1304 nx_nic_intr_coalesce_t coal;
1308 const struct firmware *fw;
1311 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1312 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1313 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1314 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1315 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1317 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1318 long reg, __u32 val);
1320 /* Functions available from netxen_nic_hw.c */
1321 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1322 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1324 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1325 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1327 #define NXRD32(adapter, off) \
1328 (adapter->hw_read_wx(adapter, off))
1329 #define NXWR32(adapter, off, val) \
1330 (adapter->hw_write_wx(adapter, off, val))
1332 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1333 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
1334 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1336 u32 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off);
1337 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1338 ulong off, u32 data);
1339 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1340 u64 off, void *data, int size);
1341 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1342 u64 off, void *data, int size);
1343 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1345 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1346 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1348 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1349 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1350 unsigned long long addr);
1351 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1354 u32 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off);
1355 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1356 ulong off, u32 data);
1357 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1358 u64 off, void *data, int size);
1359 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1360 u64 off, void *data, int size);
1361 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1363 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1364 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1366 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1367 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1368 unsigned long long addr);
1370 /* Functions from netxen_nic_init.c */
1371 int netxen_init_dummy_dma(struct netxen_adapter *adapter);
1372 void netxen_free_dummy_dma(struct netxen_adapter *adapter);
1374 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1375 int netxen_load_firmware(struct netxen_adapter *adapter);
1376 int netxen_need_fw_reset(struct netxen_adapter *adapter);
1377 void netxen_request_firmware(struct netxen_adapter *adapter);
1378 void netxen_release_firmware(struct netxen_adapter *adapter);
1379 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1381 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1382 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1383 u8 *bytes, size_t size);
1384 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1385 u8 *bytes, size_t size);
1386 int netxen_flash_unlock(struct netxen_adapter *adapter);
1387 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1388 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1389 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1390 void netxen_halt_pegs(struct netxen_adapter *adapter);
1392 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1394 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1395 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1397 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1398 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1400 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1401 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1403 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1404 int netxen_init_firmware(struct netxen_adapter *adapter);
1405 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1406 void netxen_watchdog_task(struct work_struct *work);
1407 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1408 struct nx_host_rds_ring *rds_ring);
1409 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1410 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1411 void netxen_p2_nic_set_multi(struct net_device *netdev);
1412 void netxen_p3_nic_set_multi(struct net_device *netdev);
1413 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1414 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1415 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1416 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1417 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd);
1418 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1419 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1421 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1422 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1424 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1425 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1427 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1428 struct nx_host_tx_ring *tx_ring);
1430 /* Functions from netxen_nic_main.c */
1431 int netxen_nic_reset_context(struct netxen_adapter *);
1434 * NetXen Board information
1437 #define NETXEN_MAX_SHORT_NAME 32
1438 struct netxen_brdinfo {
1439 int brdtype; /* type of board */
1440 long ports; /* max no of physical ports */
1441 char short_name[NETXEN_MAX_SHORT_NAME];
1444 static const struct netxen_brdinfo netxen_boards[] = {
1445 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1446 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1447 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1448 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1449 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1450 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1451 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1452 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1453 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1454 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1455 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1456 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1457 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1458 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1459 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1460 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1461 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1462 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1463 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1466 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1468 static inline void get_brd_name_by_type(u32 type, char *name)
1471 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1472 if (netxen_boards[i].brdtype == type) {
1473 strcpy(name, netxen_boards[i].short_name);
1483 static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1486 return find_diff_among(tx_ring->producer,
1487 tx_ring->sw_consumer, tx_ring->num_desc);
1491 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1492 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1493 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1494 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1497 extern struct ethtool_ops netxen_nic_ethtool_ops;
1499 #endif /* __NETXEN_NIC_H_ */