2 * Copyright (C) 2003 - 2009 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
27 * Cupertino, CA 95014-0701
31 #ifndef _NETXEN_NIC_H_
32 #define _NETXEN_NIC_H_
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/ioport.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
43 #include <linux/tcp.h>
44 #include <linux/skbuff.h>
45 #include <linux/firmware.h>
47 #include <linux/ethtool.h>
48 #include <linux/mii.h>
49 #include <linux/timer.h>
51 #include <linux/vmalloc.h>
54 #include <asm/byteorder.h>
56 #include "netxen_nic_hw.h"
58 #define _NETXEN_NIC_LINUX_MAJOR 4
59 #define _NETXEN_NIC_LINUX_MINOR 0
60 #define _NETXEN_NIC_LINUX_SUBVERSION 30
61 #define NETXEN_NIC_LINUX_VERSIONID "4.0.30"
63 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
64 #define _major(v) (((v) >> 24) & 0xff)
65 #define _minor(v) (((v) >> 16) & 0xff)
66 #define _build(v) ((v) & 0xffff)
68 /* version in image has weird encoding:
71 * 31:16 - build (little endian)
73 #define NETXEN_DECODE_VERSION(v) \
74 NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
76 #define NETXEN_NUM_FLASH_SECTORS (64)
77 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
78 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
79 * NETXEN_FLASH_SECTOR_SIZE)
81 #define PHAN_VENDOR_ID 0x4040
83 #define RCV_DESC_RINGSIZE(rds_ring) \
84 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
85 #define RCV_BUFF_RINGSIZE(rds_ring) \
86 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
87 #define STATUS_DESC_RINGSIZE(sds_ring) \
88 (sizeof(struct status_desc) * (sds_ring)->num_desc)
89 #define TX_BUFF_RINGSIZE(tx_ring) \
90 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
91 #define TX_DESC_RINGSIZE(tx_ring) \
92 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
94 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
96 #define NETXEN_RCV_PRODUCER_OFFSET 0
97 #define NETXEN_RCV_PEG_DB_ID 2
98 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
99 #define FLASH_SUCCESS 0
101 #define ADDR_IN_WINDOW1(off) \
102 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
105 * normalize a 64MB crb address to 32MB PCI window
106 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
108 #define NETXEN_CRB_NORMAL(reg) \
109 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
111 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
112 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
114 #define DB_NORMALIZE(adapter, off) \
115 (adapter->ahw.db_base + (off))
117 #define NX_P2_C0 0x24
118 #define NX_P2_C1 0x25
119 #define NX_P3_A0 0x30
120 #define NX_P3_A2 0x30
121 #define NX_P3_B0 0x40
122 #define NX_P3_B1 0x41
123 #define NX_P3_B2 0x42
125 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
126 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
128 #define FIRST_PAGE_GROUP_START 0
129 #define FIRST_PAGE_GROUP_END 0x100000
131 #define SECOND_PAGE_GROUP_START 0x6000000
132 #define SECOND_PAGE_GROUP_END 0x68BC000
134 #define THIRD_PAGE_GROUP_START 0x70E4000
135 #define THIRD_PAGE_GROUP_END 0x8000000
137 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
138 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
139 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
141 #define P2_MAX_MTU (8000)
142 #define P3_MAX_MTU (9600)
143 #define NX_ETHERMTU 1500
144 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
146 #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
147 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
148 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
149 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
151 #define MAX_RX_BUFFER_LENGTH 1760
152 #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
153 #define MAX_RX_LRO_BUFFER_LENGTH (8062)
154 #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
155 #define RX_JUMBO_DMA_MAP_LEN \
156 (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
157 #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
160 * Maximum number of ring contexts
162 #define MAX_RING_CTX 1
164 /* Opcodes to be used with the commands */
165 #define TX_ETHER_PKT 0x01
166 #define TX_TCP_PKT 0x02
167 #define TX_UDP_PKT 0x03
168 #define TX_IP_PKT 0x04
169 #define TX_TCP_LSO 0x05
170 #define TX_TCP_LSO6 0x06
171 #define TX_IPSEC 0x07
172 #define TX_IPSEC_CMD 0x0a
173 #define TX_TCPV6_PKT 0x0b
174 #define TX_UDPV6_PKT 0x0c
176 /* The following opcodes are for internal consumption. */
177 #define NETXEN_CONTROL_OP 0x10
178 #define PEGNET_REQUEST 0x11
180 #define MAX_NUM_CARDS 4
182 #define MAX_BUFFERS_PER_CMD 32
183 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4)
186 * Following are the states of the Phantom. Phantom will set them and
187 * Host will read to check if the fields are correct.
189 #define PHAN_INITIALIZE_START 0xff00
190 #define PHAN_INITIALIZE_FAILED 0xffff
191 #define PHAN_INITIALIZE_COMPLETE 0xff01
193 /* Host writes the following to notify that it has done the init-handshake */
194 #define PHAN_INITIALIZE_ACK 0xf00f
196 #define NUM_RCV_DESC_RINGS 3
197 #define NUM_STS_DESC_RINGS 4
199 #define RCV_RING_NORMAL 0
200 #define RCV_RING_JUMBO 1
201 #define RCV_RING_LRO 2
203 #define MAX_CMD_DESCRIPTORS 4096
204 #define MAX_RCV_DESCRIPTORS 16384
205 #define MAX_CMD_DESCRIPTORS_HOST 1024
206 #define MAX_RCV_DESCRIPTORS_1G 2048
207 #define MAX_RCV_DESCRIPTORS_10G 4096
208 #define MAX_JUMBO_RCV_DESCRIPTORS 1024
209 #define MAX_LRO_RCV_DESCRIPTORS 8
210 #define NETXEN_CTX_SIGNATURE 0xdee0
211 #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
212 #define NETXEN_CTX_RESET 0xbad0
213 #define NETXEN_CTX_D3_RESET 0xacc0
214 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
216 #define PHAN_PEG_RCV_INITIALIZED 0xff01
217 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
219 #define get_next_index(index, length) \
220 (((index) + 1) & ((length) - 1))
222 #define get_index_range(index,length,count) \
223 (((index) + (count)) & ((length) - 1))
225 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
226 #define MPORT_MULTI_FUNCTION_MODE 0x2222
228 #include "netxen_nic_phan_reg.h"
231 * NetXen host-peg signal message structure
233 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
234 * Bit 2 : priv_id => must be 1
235 * Bit 3-17 : count => for doorbell
236 * Bit 18-27 : ctx_id => Context id
240 typedef u32 netxen_ctx_msg;
242 #define netxen_set_msg_peg_id(config_word, val) \
243 ((config_word) &= ~3, (config_word) |= val & 3)
244 #define netxen_set_msg_privid(config_word) \
245 ((config_word) |= 1 << 2)
246 #define netxen_set_msg_count(config_word, val) \
247 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
248 #define netxen_set_msg_ctxid(config_word, val) \
249 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
250 #define netxen_set_msg_opcode(config_word, val) \
251 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
253 struct netxen_rcv_ring {
259 struct netxen_sts_ring {
266 struct netxen_ring_ctx {
268 /* one command ring */
269 __le64 cmd_consumer_offset;
270 __le64 cmd_ring_addr;
271 __le32 cmd_ring_size;
274 /* three receive rings */
275 struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
277 __le64 sts_ring_addr;
278 __le32 sts_ring_size;
283 __le32 sts_ring_count;
285 struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
287 } __attribute__ ((aligned(64)));
290 * Following data structures describe the descriptors that will be used.
291 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
292 * we are doing LSO (above the 1500 size packet) only.
296 * The size of reference handle been changed to 16 bits to pass the MSS fields
300 #define FLAGS_CHECKSUM_ENABLED 0x01
301 #define FLAGS_LSO_ENABLED 0x02
302 #define FLAGS_IPSEC_SA_ADD 0x04
303 #define FLAGS_IPSEC_SA_DELETE 0x08
304 #define FLAGS_VLAN_TAGGED 0x10
306 #define netxen_set_cmd_desc_port(cmd_desc, var) \
307 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
308 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
309 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
311 #define netxen_set_tx_port(_desc, _port) \
312 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
314 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
315 (_desc)->flags_opcode = \
316 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
318 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
319 (_desc)->nfrags__length = \
320 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
322 struct cmd_desc_type0 {
323 u8 tcp_hdr_offset; /* For LSO only */
324 u8 ip_hdr_offset; /* For LSO only */
325 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
326 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
330 __le16 reference_handle;
332 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
333 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
334 __le16 conn_id; /* IPSec offoad only */
339 __le16 buffer_length[4];
345 } __attribute__ ((aligned(64)));
347 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
349 __le16 reference_handle;
351 __le32 buffer_length; /* allocated buffer length (usually 2K) */
355 /* opcode field in status_desc */
356 #define NETXEN_NIC_SYN_OFFLOAD 0x03
357 #define NETXEN_NIC_RXPKT_DESC 0x04
358 #define NETXEN_OLD_RXPKT_DESC 0x3f
359 #define NETXEN_NIC_RESPONSE_DESC 0x05
361 /* for status field in status_desc */
362 #define STATUS_NEED_CKSUM (1)
363 #define STATUS_CKSUM_OK (2)
365 /* owner bits of status_desc */
366 #define STATUS_OWNER_HOST (0x1ULL << 56)
367 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
369 /* Status descriptor:
370 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
371 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
372 53-55 desc_cnt, 56-57 owner, 58-63 opcode
374 #define netxen_get_sts_port(sts_data) \
376 #define netxen_get_sts_status(sts_data) \
377 (((sts_data) >> 4) & 0x0F)
378 #define netxen_get_sts_type(sts_data) \
379 (((sts_data) >> 8) & 0x0F)
380 #define netxen_get_sts_totallength(sts_data) \
381 (((sts_data) >> 12) & 0xFFFF)
382 #define netxen_get_sts_refhandle(sts_data) \
383 (((sts_data) >> 28) & 0xFFFF)
384 #define netxen_get_sts_prot(sts_data) \
385 (((sts_data) >> 44) & 0x0F)
386 #define netxen_get_sts_pkt_offset(sts_data) \
387 (((sts_data) >> 48) & 0x1F)
388 #define netxen_get_sts_desc_cnt(sts_data) \
389 (((sts_data) >> 53) & 0x7)
390 #define netxen_get_sts_opcode(sts_data) \
391 (((sts_data) >> 58) & 0x03F)
394 __le64 status_desc_data[2];
395 } __attribute__ ((aligned(16)));
397 /* The version of the main data structure */
398 #define NETXEN_BDINFO_VERSION 1
400 /* Magic number to let user know flash is programmed */
401 #define NETXEN_BDINFO_MAGIC 0x12345678
403 /* Max number of Gig ports on a Phantom board */
404 #define NETXEN_MAX_PORTS 4
406 #define NETXEN_BRDTYPE_P1_BD 0x0000
407 #define NETXEN_BRDTYPE_P1_SB 0x0001
408 #define NETXEN_BRDTYPE_P1_SMAX 0x0002
409 #define NETXEN_BRDTYPE_P1_SOCK 0x0003
411 #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
412 #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
413 #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
414 #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
415 #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
417 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
418 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
419 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
421 #define NETXEN_BRDTYPE_P3_REF_QG 0x0021
422 #define NETXEN_BRDTYPE_P3_HMEZ 0x0022
423 #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
424 #define NETXEN_BRDTYPE_P3_4_GB 0x0024
425 #define NETXEN_BRDTYPE_P3_IMEZ 0x0025
426 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
427 #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
428 #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
429 #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
430 #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
431 #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
432 #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
433 #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
434 #define NETXEN_BRDTYPE_P3_10G_TP 0x0080
436 struct netxen_board_info {
448 u32 port_mask; /* available niu ports */
449 u32 peg_mask; /* available pegs */
450 u32 icache_ok; /* can we run with icache? */
451 u32 dcache_ok; /* can we run with dcache? */
459 /* MN-related config */
460 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
461 u32 mn_sync_shift_cclk;
462 u32 mn_sync_shift_mclk;
464 u32 mn_crystal_freq; /* in MHz */
465 u32 mn_speed; /* in MHz */
468 u32 mn_ranks_0; /* ranks per slot */
469 u32 mn_ranks_1; /* ranks per slot */
480 u32 mn_mode_reg; /* MIU DDR Mode Register */
481 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
482 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
483 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
484 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
486 /* SN-related config */
487 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
488 u32 sn_pt_mode; /* pass through mode */
503 u32 magic; /* indicates flash has been initialized */
510 #define FLASH_NUM_PORTS (4)
512 struct netxen_flash_mac_addr {
516 struct netxen_user_old_info {
528 /* primary image status */
530 u32 secondary_present;
532 /* MAC address , 4 ports */
533 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
535 #define FLASH_NUM_MAC_PER_PORT 32
536 struct netxen_user_info {
537 u8 flash_md5[16 * 64];
544 /* primary image status */
546 u32 secondary_present;
548 /* MAC address , 4 ports, 32 address per port */
549 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
553 /* Any user defined data */
557 * Flash Layout - new format.
559 struct netxen_new_user_info {
560 u8 flash_md5[16 * 64];
567 /* primary image status */
569 u32 secondary_present;
571 /* MAC address , 4 ports, 32 address per port */
572 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
576 /* Any user defined data */
579 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
580 #define SECONDARY_IMAGE_ABSENT 0xffffffff
581 #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
582 #define PRIMARY_IMAGE_BAD 0xffffffff
584 /* Flash memory map */
585 #define NETXEN_CRBINIT_START 0 /* crbinit section */
586 #define NETXEN_BRDCFG_START 0x4000 /* board config */
587 #define NETXEN_INITCODE_START 0x6000 /* pegtune code */
588 #define NETXEN_BOOTLD_START 0x10000 /* bootld */
589 #define NETXEN_IMAGE_START 0x43000 /* compressed image */
590 #define NETXEN_SECONDARY_START 0x200000 /* backup images */
591 #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
592 #define NETXEN_USER_START 0x3E8000 /* Firmare info */
593 #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
595 #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
596 #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
597 #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
598 #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
599 #define NX_FW_MIN_SIZE (0x3fffff)
600 #define NX_P2_MN_ROMIMAGE 0
601 #define NX_P3_CT_ROMIMAGE 1
602 #define NX_P3_MN_ROMIMAGE 2
603 #define NX_FLASH_ROMIMAGE 3
605 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
607 #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
608 #define NETXEN_INIT_SECTOR (0)
609 #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
610 #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
611 #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
612 #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
613 #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
614 #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
615 #define NETXEN_NUM_CONFIG_SECTORS (1)
616 extern char netxen_nic_driver_name[];
618 /* Number of status descriptors to handle per interrupt */
619 #define MAX_STATUS_HANDLE (64)
622 * netxen_skb_frag{} is to contain mapping info for each SG list. This
623 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
625 struct netxen_skb_frag {
630 #define _netxen_set_bits(config_word, start, bits, val) {\
631 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
632 unsigned long long __tvalue = (val); \
633 (config_word) &= ~__tmask; \
634 (config_word) |= (((__tvalue) << (start)) & __tmask); \
637 #define _netxen_clear_bits(config_word, start, bits) {\
638 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
639 (config_word) &= ~__tmask; \
642 /* Following defines are for the state of the buffers */
643 #define NETXEN_BUFFER_FREE 0
644 #define NETXEN_BUFFER_BUSY 1
647 * There will be one netxen_buffer per skb packet. These will be
648 * used to save the dma info for pci_unmap_page()
650 struct netxen_cmd_buffer {
652 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
656 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
657 struct netxen_rx_buffer {
658 struct list_head list;
666 #define NETXEN_NIC_GBE 0x01
667 #define NETXEN_NIC_XGBE 0x02
670 * One hardware_context{} per adapter
671 * contains interrupt info as well shared hardware info.
673 struct netxen_hardware_context {
674 void __iomem *pci_base0;
675 void __iomem *pci_base1;
676 void __iomem *pci_base2;
677 void __iomem *db_base;
678 unsigned long db_len;
679 unsigned long pci_len0;
683 unsigned long mn_win_crb;
684 unsigned long ms_win_crb;
694 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
695 #define ETHERNET_FCS_SIZE 4
697 struct netxen_adapter_stats {
709 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
710 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
712 struct nx_host_rds_ring {
714 u32 crb_rcv_producer;
719 struct rcv_desc *desc_head;
720 struct netxen_rx_buffer *rx_buf_arr;
721 struct list_head free_list;
723 dma_addr_t phys_addr;
726 struct nx_host_sds_ring {
728 u32 crb_sts_consumer;
732 struct status_desc *desc_head;
733 struct netxen_adapter *adapter;
734 struct napi_struct napi;
735 struct list_head free_list[NUM_RCV_DESC_RINGS];
739 dma_addr_t phys_addr;
740 char name[IFNAMSIZ+4];
743 struct nx_host_tx_ring {
747 u32 crb_cmd_producer;
748 u32 crb_cmd_consumer;
751 struct netdev_queue *txq;
753 struct netxen_cmd_buffer *cmd_buf_arr;
754 struct cmd_desc_type0 *desc_head;
755 dma_addr_t phys_addr;
759 * Receive context. There is one such structure per instance of the
760 * receive processing. Any state information that is relevant to
761 * the receive, and is must be in this structure. The global data may be
764 struct netxen_recv_context {
769 struct nx_host_rds_ring *rds_rings;
770 struct nx_host_sds_ring *sds_rings;
772 struct netxen_ring_ctx *hwctx;
773 dma_addr_t phys_addr;
776 /* New HW context creation */
778 #define NX_OS_CRB_RETRY_COUNT 4000
779 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
780 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
782 #define NX_CDRP_CLEAR 0x00000000
783 #define NX_CDRP_CMD_BIT 0x80000000
786 * All responses must have the NX_CDRP_CMD_BIT cleared
787 * in the crb NX_CDRP_CRB_OFFSET.
789 #define NX_CDRP_FORM_RSP(rsp) (rsp)
790 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
792 #define NX_CDRP_RSP_OK 0x00000001
793 #define NX_CDRP_RSP_FAIL 0x00000002
794 #define NX_CDRP_RSP_TIMEOUT 0x00000003
797 * All commands must have the NX_CDRP_CMD_BIT set in
798 * the crb NX_CDRP_CRB_OFFSET.
800 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
801 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
803 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
804 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
805 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
806 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
807 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
808 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
809 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
810 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
811 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
812 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
813 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
814 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
815 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
816 #define NX_CDRP_CMD_SET_MTU 0x00000012
817 #define NX_CDRP_CMD_MAX 0x00000013
819 #define NX_RCODE_SUCCESS 0
820 #define NX_RCODE_NO_HOST_MEM 1
821 #define NX_RCODE_NO_HOST_RESOURCE 2
822 #define NX_RCODE_NO_CARD_CRB 3
823 #define NX_RCODE_NO_CARD_MEM 4
824 #define NX_RCODE_NO_CARD_RESOURCE 5
825 #define NX_RCODE_INVALID_ARGS 6
826 #define NX_RCODE_INVALID_ACTION 7
827 #define NX_RCODE_INVALID_STATE 8
828 #define NX_RCODE_NOT_SUPPORTED 9
829 #define NX_RCODE_NOT_PERMITTED 10
830 #define NX_RCODE_NOT_READY 11
831 #define NX_RCODE_DOES_NOT_EXIST 12
832 #define NX_RCODE_ALREADY_EXISTS 13
833 #define NX_RCODE_BAD_SIGNATURE 14
834 #define NX_RCODE_CMD_NOT_IMPL 15
835 #define NX_RCODE_CMD_INVALID 16
836 #define NX_RCODE_TIMEOUT 17
837 #define NX_RCODE_CMD_FAILED 18
838 #define NX_RCODE_MAX_EXCEEDED 19
839 #define NX_RCODE_MAX 20
841 #define NX_DESTROY_CTX_RESET 0
842 #define NX_DESTROY_CTX_D3_RESET 1
843 #define NX_DESTROY_CTX_MAX 2
848 #define NX_CAP_BIT(class, bit) (1 << bit)
849 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
850 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
851 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
852 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
853 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
854 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
855 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
856 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
857 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
862 #define NX_HOST_CTX_STATE_FREED 0
863 #define NX_HOST_CTX_STATE_ALLOCATED 1
864 #define NX_HOST_CTX_STATE_ACTIVE 2
865 #define NX_HOST_CTX_STATE_DISABLED 3
866 #define NX_HOST_CTX_STATE_QUIESCED 4
867 #define NX_HOST_CTX_STATE_MAX 5
874 __le64 host_phys_addr; /* Ring base addr */
875 __le32 ring_size; /* Ring entries */
877 __le16 rsvd; /* Padding */
878 } nx_hostrq_sds_ring_t;
881 __le64 host_phys_addr; /* Ring base addr */
882 __le64 buff_size; /* Packet buffer size */
883 __le32 ring_size; /* Ring entries */
884 __le32 ring_kind; /* Class of ring */
885 } nx_hostrq_rds_ring_t;
888 __le64 host_rsp_dma_addr; /* Response dma'd here */
889 __le32 capabilities[4]; /* Flag bit vector */
890 __le32 host_int_crb_mode; /* Interrupt crb usage */
891 __le32 host_rds_crb_mode; /* RDS crb usage */
892 /* These ring offsets are relative to data[0] below */
893 __le32 rds_ring_offset; /* Offset to RDS config */
894 __le32 sds_ring_offset; /* Offset to SDS config */
895 __le16 num_rds_rings; /* Count of RDS rings */
896 __le16 num_sds_rings; /* Count of SDS rings */
897 __le16 rsvd1; /* Padding */
898 __le16 rsvd2; /* Padding */
899 u8 reserved[128]; /* reserve space for future expansion*/
900 /* MUST BE 64-bit aligned.
901 The following is packed:
903 - N hostrq_sds_rings */
905 } nx_hostrq_rx_ctx_t;
908 __le32 host_producer_crb; /* Crb to use */
909 __le32 rsvd1; /* Padding */
910 } nx_cardrsp_rds_ring_t;
913 __le32 host_consumer_crb; /* Crb to use */
914 __le32 interrupt_crb; /* Crb to use */
915 } nx_cardrsp_sds_ring_t;
918 /* These ring offsets are relative to data[0] below */
919 __le32 rds_ring_offset; /* Offset to RDS config */
920 __le32 sds_ring_offset; /* Offset to SDS config */
921 __le32 host_ctx_state; /* Starting State */
922 __le32 num_fn_per_port; /* How many PCI fn share the port */
923 __le16 num_rds_rings; /* Count of RDS rings */
924 __le16 num_sds_rings; /* Count of SDS rings */
925 __le16 context_id; /* Handle for context */
926 u8 phys_port; /* Physical id of port */
927 u8 virt_port; /* Virtual/Logical id of port */
928 u8 reserved[128]; /* save space for future expansion */
929 /* MUST BE 64-bit aligned.
930 The following is packed:
931 - N cardrsp_rds_rings
932 - N cardrs_sds_rings */
934 } nx_cardrsp_rx_ctx_t;
936 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
937 (sizeof(HOSTRQ_RX) + \
938 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
939 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
941 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
942 (sizeof(CARDRSP_RX) + \
943 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
944 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
951 __le64 host_phys_addr; /* Ring base addr */
952 __le32 ring_size; /* Ring entries */
953 __le32 rsvd; /* Padding */
954 } nx_hostrq_cds_ring_t;
957 __le64 host_rsp_dma_addr; /* Response dma'd here */
958 __le64 cmd_cons_dma_addr; /* */
959 __le64 dummy_dma_addr; /* */
960 __le32 capabilities[4]; /* Flag bit vector */
961 __le32 host_int_crb_mode; /* Interrupt crb usage */
962 __le32 rsvd1; /* Padding */
963 __le16 rsvd2; /* Padding */
964 __le16 interrupt_ctl;
966 __le16 rsvd3; /* Padding */
967 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
968 u8 reserved[128]; /* future expansion */
969 } nx_hostrq_tx_ctx_t;
972 __le32 host_producer_crb; /* Crb to use */
973 __le32 interrupt_crb; /* Crb to use */
974 } nx_cardrsp_cds_ring_t;
977 __le32 host_ctx_state; /* Starting state */
978 __le16 context_id; /* Handle for context */
979 u8 phys_port; /* Physical id of port */
980 u8 virt_port; /* Virtual/Logical id of port */
981 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
982 u8 reserved[128]; /* future expansion */
983 } nx_cardrsp_tx_ctx_t;
985 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
986 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
990 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
991 #define NX_HOST_RDS_CRB_MODE_SHARED 1
992 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
993 #define NX_HOST_RDS_CRB_MODE_MAX 3
995 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
996 #define NX_HOST_INT_CRB_MODE_SHARED 1
997 #define NX_HOST_INT_CRB_MODE_NORX 2
998 #define NX_HOST_INT_CRB_MODE_NOTX 3
999 #define NX_HOST_INT_CRB_MODE_NORXTX 4
1004 #define MC_COUNT_P2 16
1005 #define MC_COUNT_P3 38
1007 #define NETXEN_MAC_NOOP 0
1008 #define NETXEN_MAC_ADD 1
1009 #define NETXEN_MAC_DEL 2
1011 typedef struct nx_mac_list_s {
1012 struct list_head list;
1013 uint8_t mac_addr[ETH_ALEN+2];
1017 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1018 * adjusted based on configured MTU.
1020 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1021 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1022 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1023 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1025 #define NETXEN_NIC_INTR_DEFAULT 0x04
1029 uint16_t rx_packets;
1030 uint16_t rx_time_us;
1031 uint16_t tx_packets;
1032 uint16_t tx_time_us;
1035 } nx_nic_intr_coalesce_data_t;
1038 uint16_t stats_time_us;
1039 uint16_t rate_sample_time;
1042 uint32_t low_threshold;
1043 uint32_t high_threshold;
1044 nx_nic_intr_coalesce_data_t normal;
1045 nx_nic_intr_coalesce_data_t low;
1046 nx_nic_intr_coalesce_data_t high;
1047 nx_nic_intr_coalesce_data_t irq;
1048 } nx_nic_intr_coalesce_t;
1050 #define NX_HOST_REQUEST 0x13
1051 #define NX_NIC_REQUEST 0x14
1053 #define NX_MAC_EVENT 0x1
1056 #define NX_IP_DOWN 3
1059 * Driver --> Firmware
1061 #define NX_NIC_H2C_OPCODE_START 0
1062 #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
1063 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
1064 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
1065 #define NX_NIC_H2C_OPCODE_CONFIG_LED 4
1066 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
1067 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
1068 #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
1069 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
1070 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
1071 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
1072 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
1073 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
1074 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
1075 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
1076 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
1077 #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
1078 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
1079 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
1080 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
1081 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
1082 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
1083 #define NX_NIC_C2C_OPCODE 22
1084 #define NX_NIC_H2C_OPCODE_LAST 23
1087 * Firmware --> Driver
1090 #define NX_NIC_C2H_OPCODE_START 128
1091 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
1092 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
1093 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
1094 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
1095 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
1096 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
1097 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
1098 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
1099 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
1100 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
1101 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1102 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
1103 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
1104 #define NX_NIC_C2H_OPCODE_LAST 142
1106 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1107 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1108 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1110 #define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5)
1111 #define NX_FW_CAPABILITY_SWITCHING (1 << 6)
1114 #define LINKEVENT_MODULE_NOT_PRESENT 1
1115 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
1116 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
1117 #define LINKEVENT_MODULE_OPTICAL_LRM 4
1118 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
1119 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
1120 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
1121 #define LINKEVENT_MODULE_TWINAX 8
1123 #define LINKSPEED_10GBPS 10000
1124 #define LINKSPEED_1GBPS 1000
1125 #define LINKSPEED_100MBPS 100
1126 #define LINKSPEED_10MBPS 10
1128 #define LINKSPEED_ENCODED_10MBPS 0
1129 #define LINKSPEED_ENCODED_100MBPS 1
1130 #define LINKSPEED_ENCODED_1GBPS 2
1132 #define LINKEVENT_AUTONEG_DISABLED 0
1133 #define LINKEVENT_AUTONEG_ENABLED 1
1135 #define LINKEVENT_HALF_DUPLEX 0
1136 #define LINKEVENT_FULL_DUPLEX 1
1138 #define LINKEVENT_LINKSPEED_MBPS 0
1139 #define LINKEVENT_LINKSPEED_ENCODED 1
1141 /* firmware response header:
1142 * 63:58 - message type
1144 * 55:53 - desc count
1146 * 47:40 - completion id
1148 * 31:16 - error code
1151 #define netxen_get_nic_msgtype(msg_hdr) \
1152 ((msg_hdr >> 58) & 0x3F)
1153 #define netxen_get_nic_msg_compid(msg_hdr) \
1154 ((msg_hdr >> 40) & 0xFF)
1155 #define netxen_get_nic_msg_opcode(msg_hdr) \
1156 ((msg_hdr >> 32) & 0xFF)
1157 #define netxen_get_nic_msg_errcode(msg_hdr) \
1158 ((msg_hdr >> 16) & 0xFFFF)
1182 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1184 #define NETXEN_NIC_MSI_ENABLED 0x02
1185 #define NETXEN_NIC_MSIX_ENABLED 0x04
1186 #define NETXEN_IS_MSI_FAMILY(adapter) \
1187 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1189 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
1190 #define NETXEN_MSIX_TBL_SPACE 8192
1191 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1193 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1195 #define NETXEN_NETDEV_WEIGHT 128
1196 #define NETXEN_ADAPTER_UP_MAGIC 777
1197 #define NETXEN_NIC_PEG_TUNE 0
1199 struct netxen_dummy_dma {
1201 dma_addr_t phys_addr;
1204 struct netxen_adapter {
1205 struct netxen_hardware_context ahw;
1207 struct net_device *netdev;
1208 struct pci_dev *pdev;
1209 struct list_head mac_list;
1213 rwlock_t adapter_lock;
1215 spinlock_t tx_clean_lock;
1256 struct netxen_adapter_stats stats;
1258 struct netxen_recv_context recv_ctx;
1259 struct nx_host_tx_ring *tx_ring;
1261 int (*enable_phy_interrupts) (struct netxen_adapter *);
1262 int (*disable_phy_interrupts) (struct netxen_adapter *);
1263 int (*macaddr_set) (struct netxen_adapter *, u8 *);
1264 int (*set_mtu) (struct netxen_adapter *, int);
1265 int (*set_promisc) (struct netxen_adapter *, u32);
1266 void (*set_multi) (struct net_device *);
1267 int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1268 int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1269 int (*init_port) (struct netxen_adapter *, int);
1270 int (*stop_port) (struct netxen_adapter *);
1272 u32 (*hw_read_wx)(struct netxen_adapter *, ulong);
1273 int (*hw_write_wx)(struct netxen_adapter *, ulong, u32);
1274 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1275 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1276 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1277 u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1278 unsigned long (*pci_set_window)(struct netxen_adapter *,
1279 unsigned long long);
1281 struct netxen_legacy_intr_set legacy_intr;
1283 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1285 struct netxen_dummy_dma dummy_dma;
1287 struct work_struct watchdog_task;
1288 struct timer_list watchdog_timer;
1289 struct work_struct tx_timeout_task;
1291 struct net_device_stats net_stats;
1293 nx_nic_intr_coalesce_t coal;
1297 const struct firmware *fw;
1300 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1301 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1302 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1303 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1304 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1306 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1307 long reg, __u32 val);
1309 /* Functions available from netxen_nic_hw.c */
1310 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1311 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1313 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1314 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1316 #define NXRD32(adapter, off) \
1317 (adapter->hw_read_wx(adapter, off))
1318 #define NXWR32(adapter, off, val) \
1319 (adapter->hw_write_wx(adapter, off, val))
1321 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1322 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
1323 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1325 u32 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off);
1326 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1327 ulong off, u32 data);
1328 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1329 u64 off, void *data, int size);
1330 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1331 u64 off, void *data, int size);
1332 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1334 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1335 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1337 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1338 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1339 unsigned long long addr);
1340 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1343 u32 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off);
1344 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1345 ulong off, u32 data);
1346 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1347 u64 off, void *data, int size);
1348 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1349 u64 off, void *data, int size);
1350 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1352 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1353 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1355 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1356 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1357 unsigned long long addr);
1359 /* Functions from netxen_nic_init.c */
1360 int netxen_init_dummy_dma(struct netxen_adapter *adapter);
1361 void netxen_free_dummy_dma(struct netxen_adapter *adapter);
1363 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1364 int netxen_load_firmware(struct netxen_adapter *adapter);
1365 int netxen_need_fw_reset(struct netxen_adapter *adapter);
1366 void netxen_request_firmware(struct netxen_adapter *adapter);
1367 void netxen_release_firmware(struct netxen_adapter *adapter);
1368 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1370 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1371 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1372 u8 *bytes, size_t size);
1373 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1374 u8 *bytes, size_t size);
1375 int netxen_flash_unlock(struct netxen_adapter *adapter);
1376 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1377 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1378 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1379 void netxen_halt_pegs(struct netxen_adapter *adapter);
1381 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1383 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1384 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1386 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1387 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1389 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1390 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1392 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1393 int netxen_init_firmware(struct netxen_adapter *adapter);
1394 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1395 void netxen_watchdog_task(struct work_struct *work);
1396 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1397 struct nx_host_rds_ring *rds_ring);
1398 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1399 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1400 void netxen_p2_nic_set_multi(struct net_device *netdev);
1401 void netxen_p3_nic_set_multi(struct net_device *netdev);
1402 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1403 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1404 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1405 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1406 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd);
1407 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1408 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1410 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1411 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1413 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1414 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1416 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1417 struct nx_host_tx_ring *tx_ring);
1420 * NetXen Board information
1423 #define NETXEN_MAX_SHORT_NAME 32
1424 struct netxen_brdinfo {
1425 int brdtype; /* type of board */
1426 long ports; /* max no of physical ports */
1427 char short_name[NETXEN_MAX_SHORT_NAME];
1430 static const struct netxen_brdinfo netxen_boards[] = {
1431 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1432 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1433 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1434 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1435 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1436 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1437 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1438 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1439 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1440 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1441 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1442 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1443 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1444 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1445 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1446 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1447 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1448 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1449 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1452 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1454 static inline void get_brd_name_by_type(u32 type, char *name)
1457 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1458 if (netxen_boards[i].brdtype == type) {
1459 strcpy(name, netxen_boards[i].short_name);
1469 static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1472 return find_diff_among(tx_ring->producer,
1473 tx_ring->sw_consumer, tx_ring->num_desc);
1477 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1478 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1479 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1480 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1483 extern struct ethtool_ops netxen_nic_ethtool_ops;
1485 #endif /* __NETXEN_NIC_H_ */