Pileus Git - ~andy/linux/blob - drivers/net/mlx4/main.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/init.h>
  38 #include <linux/errno.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/io-mapping.h>
  43
  44 #include <linux/mlx4/device.h>
  45 #include <linux/mlx4/doorbell.h>
  46
  47 #include "mlx4.h"
  48 #include "fw.h"
  49 #include "icm.h"
  50
  51 MODULE_AUTHOR("Roland Dreier");
  52 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  53 MODULE_LICENSE("Dual BSD/GPL");
  54 MODULE_VERSION(DRV_VERSION);
  55
  56 struct workqueue_struct *mlx4_wq;
  57
  58 #ifdef CONFIG_MLX4_DEBUG
  59
  60 int mlx4_debug_level = 0;
  61 module_param_named(debug_level, mlx4_debug_level, int, 0644);
  62 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  63
  64 #endif /* CONFIG_MLX4_DEBUG */
  65
  66 #ifdef CONFIG_PCI_MSI
  67
  68 static int msi_x = 1;
  69 module_param(msi_x, int, 0444);
  70 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  71
  72 #else /* CONFIG_PCI_MSI */
  73
  74 #define msi_x (0)
  75
  76 #endif /* CONFIG_PCI_MSI */
  77
  78 static char mlx4_version[] __devinitdata =
  79         DRV_NAME ": Mellanox ConnectX core driver v"
  80         DRV_VERSION " (" DRV_RELDATE ")\n";
  81
  82 static struct mlx4_profile default_profile = {
  83         .num_qp         = 1 << 17,
  84         .num_srq        = 1 << 16,
  85         .rdmarc_per_qp  = 1 << 4,
  86         .num_cq         = 1 << 16,
  87         .num_mcg        = 1 << 13,
  88         .num_mpt        = 1 << 17,
  89         .num_mtt        = 1 << 20,
  90 };
  91
  92 static int log_num_mac = 2;
  93 module_param_named(log_num_mac, log_num_mac, int, 0444);
  94 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
  95
  96 static int log_num_vlan;
  97 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
  98 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
  99 /* Log2 max number of VLANs per ETH port (0-7) */
 100 #define MLX4_LOG_NUM_VLANS 7
 101
 102 static int use_prio;
 103 module_param_named(use_prio, use_prio, bool, 0444);
 104 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
 105                   "(0/1, default 0)");
 106
 107 static int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
 108 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
 109 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
 110
 111 int mlx4_check_port_params(struct mlx4_dev *dev,
 112                            enum mlx4_port_type *port_type)
 113 {
 114         int i;
 115
 116         for (i = 0; i < dev->caps.num_ports - 1; i++) {
 117                 if (port_type[i] != port_type[i + 1]) {
 118                         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 119                                 mlx4_err(dev, "Only same port types supported "
 120                                          "on this HCA, aborting.\n");
 121                                 return -EINVAL;
 122                         }
 123                         if (port_type[i] == MLX4_PORT_TYPE_ETH &&
 124                             port_type[i + 1] == MLX4_PORT_TYPE_IB)
 125                                 return -EINVAL;
 126                 }
 127         }
 128
 129         for (i = 0; i < dev->caps.num_ports; i++) {
 130                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
 131                         mlx4_err(dev, "Requested port type for port %d is not "
 132                                       "supported on this HCA\n", i + 1);
 133                         return -EINVAL;
 134                 }
 135         }
 136         return 0;
 137 }
 138
 139 static void mlx4_set_port_mask(struct mlx4_dev *dev)
 140 {
 141         int i;
 142
 143         dev->caps.port_mask = 0;
 144         for (i = 1; i <= dev->caps.num_ports; ++i)
 145                 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB)
 146                         dev->caps.port_mask |= 1 << (i - 1);
 147 }
 148
 149 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 150 {
 151         int err;
 152         int i;
 153
 154         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
 155         if (err) {
 156                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 157                 return err;
 158         }
 159
 160         if (dev_cap->min_page_sz > PAGE_SIZE) {
 161                 mlx4_err(dev, "HCA minimum page size of %d bigger than "
 162                          "kernel PAGE_SIZE of %ld, aborting.\n",
 163                          dev_cap->min_page_sz, PAGE_SIZE);
 164                 return -ENODEV;
 165         }
 166         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
 167                 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
 168                          "aborting.\n",
 169                          dev_cap->num_ports, MLX4_MAX_PORTS);
 170                 return -ENODEV;
 171         }
 172
 173         if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
 174                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
 175                          "PCI resource 2 size of 0x%llx, aborting.\n",
 176                          dev_cap->uar_size,
 177                          (unsigned long long) pci_resource_len(dev->pdev, 2));
 178                 return -ENODEV;
 179         }
 180
 181         dev->caps.num_ports          = dev_cap->num_ports;
 182         for (i = 1; i <= dev->caps.num_ports; ++i) {
 183                 dev->caps.vl_cap[i]         = dev_cap->max_vl[i];
 184                 dev->caps.ib_mtu_cap[i]     = dev_cap->ib_mtu[i];
 185                 dev->caps.gid_table_len[i]  = dev_cap->max_gids[i];
 186                 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
 187                 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
 188                 dev->caps.eth_mtu_cap[i]    = dev_cap->eth_mtu[i];
 189                 dev->caps.def_mac[i]        = dev_cap->def_mac[i];
 190                 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
 191                 dev->caps.trans_type[i]     = dev_cap->trans_type[i];
 192                 dev->caps.vendor_oui[i]     = dev_cap->vendor_oui[i];
 193                 dev->caps.wavelength[i]     = dev_cap->wavelength[i];
 194                 dev->caps.trans_code[i]     = dev_cap->trans_code[i];
 195         }
 196
 197         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
 198         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
 199         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
 200         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
 201         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
 202         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
 203         dev->caps.max_wqes           = dev_cap->max_qp_sz;
 204         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
 205         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
 206         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
 207         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
 208         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
 209         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
 210         dev->caps.num_qp_per_mgm     = MLX4_QP_PER_MGM;
 211         /*
 212          * Subtract 1 from the limit because we need to allocate a
 213          * spare CQE so the HCA HW can tell the difference between an
 214          * empty CQ and a full CQ.
 215          */
 216         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
 217         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
 218         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
 219         dev->caps.mtts_per_seg       = 1 << log_mtts_per_seg;
 220         dev->caps.reserved_mtts      = DIV_ROUND_UP(dev_cap->reserved_mtts,
 221                                                     dev->caps.mtts_per_seg);
 222         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
 223         dev->caps.reserved_uars      = dev_cap->reserved_uars;
 224         dev->caps.reserved_pds       = dev_cap->reserved_pds;
 225         dev->caps.mtt_entry_sz       = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz;
 226         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
 227         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
 228         dev->caps.flags              = dev_cap->flags;
 229         dev->caps.bmme_flags         = dev_cap->bmme_flags;
 230         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
 231         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
 232         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
 233
 234         dev->caps.log_num_macs  = log_num_mac;
 235         dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
 236         dev->caps.log_num_prios = use_prio ? 3 : 0;
 237
 238         for (i = 1; i <= dev->caps.num_ports; ++i) {
 239                 if (dev->caps.supported_type[i] != MLX4_PORT_TYPE_ETH)
 240                         dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
 241                 else
 242                         dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
 243                 dev->caps.possible_type[i] = dev->caps.port_type[i];
 244                 mlx4_priv(dev)->sense.sense_allowed[i] =
 245                         dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO;
 246
 247                 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
 248                         dev->caps.log_num_macs = dev_cap->log_max_macs[i];
 249                         mlx4_warn(dev, "Requested number of MACs is too much "
 250                                   "for port %d, reducing to %d.\n",
 251                                   i, 1 << dev->caps.log_num_macs);
 252                 }
 253                 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
 254                         dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
 255                         mlx4_warn(dev, "Requested number of VLANs is too much "
 256                                   "for port %d, reducing to %d.\n",
 257                                   i, 1 << dev->caps.log_num_vlans);
 258                 }
 259         }
 260
 261         mlx4_set_port_mask(dev);
 262
 263         dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
 264
 265         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
 266         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
 267                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
 268                 (1 << dev->caps.log_num_macs) *
 269                 (1 << dev->caps.log_num_vlans) *
 270                 (1 << dev->caps.log_num_prios) *
 271                 dev->caps.num_ports;
 272         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
 273
 274         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
 275                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
 276                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
 277                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
 278
 279         return 0;
 280 }
 281
 282 /*
 283  * Change the port configuration of the device.
 284  * Every user of this function must hold the port mutex.
 285  */
 286 int mlx4_change_port_types(struct mlx4_dev *dev,
 287                            enum mlx4_port_type *port_types)
 288 {
 289         int err = 0;
 290         int change = 0;
 291         int port;
 292
 293         for (port = 0; port <  dev->caps.num_ports; port++) {
 294                 /* Change the port type only if the new type is different
 295                  * from the current, and not set to Auto */
 296                 if (port_types[port] != dev->caps.port_type[port + 1]) {
 297                         change = 1;
 298                         dev->caps.port_type[port + 1] = port_types[port];
 299                 }
 300         }
 301         if (change) {
 302                 mlx4_unregister_device(dev);
 303                 for (port = 1; port <= dev->caps.num_ports; port++) {
 304                         mlx4_CLOSE_PORT(dev, port);
 305                         err = mlx4_SET_PORT(dev, port);
 306                         if (err) {
 307                                 mlx4_err(dev, "Failed to set port %d, "
 308                                               "aborting\n", port);
 309                                 goto out;
 310                         }
 311                 }
 312                 mlx4_set_port_mask(dev);
 313                 err = mlx4_register_device(dev);
 314         }
 315
 316 out:
 317         return err;
 318 }
 319
 320 static ssize_t show_port_type(struct device *dev,
 321                               struct device_attribute *attr,
 322                               char *buf)
 323 {
 324         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 325                                                    port_attr);
 326         struct mlx4_dev *mdev = info->dev;
 327         char type[8];
 328
 329         sprintf(type, "%s",
 330                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
 331                 "ib" : "eth");
 332         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
 333                 sprintf(buf, "auto (%s)\n", type);
 334         else
 335                 sprintf(buf, "%s\n", type);
 336
 337         return strlen(buf);
 338 }
 339
 340 static ssize_t set_port_type(struct device *dev,
 341                              struct device_attribute *attr,
 342                              const char *buf, size_t count)
 343 {
 344         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 345                                                    port_attr);
 346         struct mlx4_dev *mdev = info->dev;
 347         struct mlx4_priv *priv = mlx4_priv(mdev);
 348         enum mlx4_port_type types[MLX4_MAX_PORTS];
 349         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
 350         int i;
 351         int err = 0;
 352
 353         if (!strcmp(buf, "ib\n"))
 354                 info->tmp_type = MLX4_PORT_TYPE_IB;
 355         else if (!strcmp(buf, "eth\n"))
 356                 info->tmp_type = MLX4_PORT_TYPE_ETH;
 357         else if (!strcmp(buf, "auto\n"))
 358                 info->tmp_type = MLX4_PORT_TYPE_AUTO;
 359         else {
 360                 mlx4_err(mdev, "%s is not supported port type\n", buf);
 361                 return -EINVAL;
 362         }
 363
 364         mlx4_stop_sense(mdev);
 365         mutex_lock(&priv->port_mutex);
 366         /* Possible type is always the one that was delivered */
 367         mdev->caps.possible_type[info->port] = info->tmp_type;
 368
 369         for (i = 0; i < mdev->caps.num_ports; i++) {
 370                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
 371                                         mdev->caps.possible_type[i+1];
 372                 if (types[i] == MLX4_PORT_TYPE_AUTO)
 373                         types[i] = mdev->caps.port_type[i+1];
 374         }
 375
 376         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 377                 for (i = 1; i <= mdev->caps.num_ports; i++) {
 378                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
 379                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
 380                                 err = -EINVAL;
 381                         }
 382                 }
 383         }
 384         if (err) {
 385                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
 386                                "Set only 'eth' or 'ib' for both ports "
 387                                "(should be the same)\n");
 388                 goto out;
 389         }
 390
 391         mlx4_do_sense_ports(mdev, new_types, types);
 392
 393         err = mlx4_check_port_params(mdev, new_types);
 394         if (err)
 395                 goto out;
 396
 397         /* We are about to apply the changes after the configuration
 398          * was verified, no need to remember the temporary types
 399          * any more */
 400         for (i = 0; i < mdev->caps.num_ports; i++)
 401                 priv->port[i + 1].tmp_type = 0;
 402
 403         err = mlx4_change_port_types(mdev, new_types);
 404
 405 out:
 406         mlx4_start_sense(mdev);
 407         mutex_unlock(&priv->port_mutex);
 408         return err ? err : count;
 409 }
 410
 411 static int mlx4_load_fw(struct mlx4_dev *dev)
 412 {
 413         struct mlx4_priv *priv = mlx4_priv(dev);
 414         int err;
 415
 416         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
 417                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
 418         if (!priv->fw.fw_icm) {
 419                 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
 420                 return -ENOMEM;
 421         }
 422
 423         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
 424         if (err) {
 425                 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
 426                 goto err_free;
 427         }
 428
 429         err = mlx4_RUN_FW(dev);
 430         if (err) {
 431                 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
 432                 goto err_unmap_fa;
 433         }
 434
 435         return 0;
 436
 437 err_unmap_fa:
 438         mlx4_UNMAP_FA(dev);
 439
 440 err_free:
 441         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
 442         return err;
 443 }
 444
 445 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
 446                                 int cmpt_entry_sz)
 447 {
 448         struct mlx4_priv *priv = mlx4_priv(dev);
 449         int err;
 450
 451         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
 452                                   cmpt_base +
 453                                   ((u64) (MLX4_CMPT_TYPE_QP *
 454                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 455                                   cmpt_entry_sz, dev->caps.num_qps,
 456                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 457                                   0, 0);
 458         if (err)
 459                 goto err;
 460
 461         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
 462                                   cmpt_base +
 463                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
 464                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 465                                   cmpt_entry_sz, dev->caps.num_srqs,
 466                                   dev->caps.reserved_srqs, 0, 0);
 467         if (err)
 468                 goto err_qp;
 469
 470         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
 471                                   cmpt_base +
 472                                   ((u64) (MLX4_CMPT_TYPE_CQ *
 473                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 474                                   cmpt_entry_sz, dev->caps.num_cqs,
 475                                   dev->caps.reserved_cqs, 0, 0);
 476         if (err)
 477                 goto err_srq;
 478
 479         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
 480                                   cmpt_base +
 481                                   ((u64) (MLX4_CMPT_TYPE_EQ *
 482                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 483                                   cmpt_entry_sz,
 484                                   dev->caps.num_eqs, dev->caps.num_eqs, 0, 0);
 485         if (err)
 486                 goto err_cq;
 487
 488         return 0;
 489
 490 err_cq:
 491         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
 492
 493 err_srq:
 494         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
 495
 496 err_qp:
 497         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
 498
 499 err:
 500         return err;
 501 }
 502
 503 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
 504                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
 505 {
 506         struct mlx4_priv *priv = mlx4_priv(dev);
 507         u64 aux_pages;
 508         int err;
 509
 510         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
 511         if (err) {
 512                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
 513                 return err;
 514         }
 515
 516         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
 517                  (unsigned long long) icm_size >> 10,
 518                  (unsigned long long) aux_pages << 2);
 519
 520         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
 521                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
 522         if (!priv->fw.aux_icm) {
 523                 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
 524                 return -ENOMEM;
 525         }
 526
 527         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
 528         if (err) {
 529                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
 530                 goto err_free_aux;
 531         }
 532
 533         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
 534         if (err) {
 535                 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
 536                 goto err_unmap_aux;
 537         }
 538
 539         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
 540                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
 541                                   dev->caps.num_eqs, dev->caps.num_eqs,
 542                                   0, 0);
 543         if (err) {
 544                 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
 545                 goto err_unmap_cmpt;
 546         }
 547
 548         /*
 549          * Reserved MTT entries must be aligned up to a cacheline
 550          * boundary, since the FW will write to them, while the driver
 551          * writes to all other MTT entries. (The variable
 552          * dev->caps.mtt_entry_sz below is really the MTT segment
 553          * size, not the raw entry size)
 554          */
 555         dev->caps.reserved_mtts =
 556                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
 557                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
 558
 559         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
 560                                   init_hca->mtt_base,
 561                                   dev->caps.mtt_entry_sz,
 562                                   dev->caps.num_mtt_segs,
 563                                   dev->caps.reserved_mtts, 1, 0);
 564         if (err) {
 565                 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
 566                 goto err_unmap_eq;
 567         }
 568
 569         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
 570                                   init_hca->dmpt_base,
 571                                   dev_cap->dmpt_entry_sz,
 572                                   dev->caps.num_mpts,
 573                                   dev->caps.reserved_mrws, 1, 1);
 574         if (err) {
 575                 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
 576                 goto err_unmap_mtt;
 577         }
 578
 579         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
 580                                   init_hca->qpc_base,
 581                                   dev_cap->qpc_entry_sz,
 582                                   dev->caps.num_qps,
 583                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 584                                   0, 0);
 585         if (err) {
 586                 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
 587                 goto err_unmap_dmpt;
 588         }
 589
 590         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
 591                                   init_hca->auxc_base,
 592                                   dev_cap->aux_entry_sz,
 593                                   dev->caps.num_qps,
 594                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 595                                   0, 0);
 596         if (err) {
 597                 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
 598                 goto err_unmap_qp;
 599         }
 600
 601         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
 602                                   init_hca->altc_base,
 603                                   dev_cap->altc_entry_sz,
 604                                   dev->caps.num_qps,
 605                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 606                                   0, 0);
 607         if (err) {
 608                 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
 609                 goto err_unmap_auxc;
 610         }
 611
 612         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
 613                                   init_hca->rdmarc_base,
 614                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
 615                                   dev->caps.num_qps,
 616                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 617                                   0, 0);
 618         if (err) {
 619                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
 620                 goto err_unmap_altc;
 621         }
 622
 623         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
 624                                   init_hca->cqc_base,
 625                                   dev_cap->cqc_entry_sz,
 626                                   dev->caps.num_cqs,
 627                                   dev->caps.reserved_cqs, 0, 0);
 628         if (err) {
 629                 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
 630                 goto err_unmap_rdmarc;
 631         }
 632
 633         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
 634                                   init_hca->srqc_base,
 635                                   dev_cap->srq_entry_sz,
 636                                   dev->caps.num_srqs,
 637                                   dev->caps.reserved_srqs, 0, 0);
 638         if (err) {
 639                 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
 640                 goto err_unmap_cq;
 641         }
 642
 643         /*
 644          * It's not strictly required, but for simplicity just map the
 645          * whole multicast group table now.  The table isn't very big
 646          * and it's a lot easier than trying to track ref counts.
 647          */
 648         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
 649                                   init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
 650                                   dev->caps.num_mgms + dev->caps.num_amgms,
 651                                   dev->caps.num_mgms + dev->caps.num_amgms,
 652                                   0, 0);
 653         if (err) {
 654                 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
 655                 goto err_unmap_srq;
 656         }
 657
 658         return 0;
 659
 660 err_unmap_srq:
 661         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
 662
 663 err_unmap_cq:
 664         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
 665
 666 err_unmap_rdmarc:
 667         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
 668
 669 err_unmap_altc:
 670         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
 671
 672 err_unmap_auxc:
 673         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
 674
 675 err_unmap_qp:
 676         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
 677
 678 err_unmap_dmpt:
 679         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
 680
 681 err_unmap_mtt:
 682         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
 683
 684 err_unmap_eq:
 685         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
 686
 687 err_unmap_cmpt:
 688         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
 689         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
 690         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
 691         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
 692
 693 err_unmap_aux:
 694         mlx4_UNMAP_ICM_AUX(dev);
 695
 696 err_free_aux:
 697         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
 698
 699         return err;
 700 }
 701
 702 static void mlx4_free_icms(struct mlx4_dev *dev)
 703 {
 704         struct mlx4_priv *priv = mlx4_priv(dev);
 705
 706         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
 707         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
 708         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
 709         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
 710         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
 711         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
 712         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
 713         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
 714         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
 715         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
 716         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
 717         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
 718         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
 719         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
 720
 721         mlx4_UNMAP_ICM_AUX(dev);
 722         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
 723 }
 724
 725 static int map_bf_area(struct mlx4_dev *dev)
 726 {
 727         struct mlx4_priv *priv = mlx4_priv(dev);
 728         resource_size_t bf_start;
 729         resource_size_t bf_len;
 730         int err = 0;
 731
 732         bf_start = pci_resource_start(dev->pdev, 2) + (dev->caps.num_uars << PAGE_SHIFT);
 733         bf_len = pci_resource_len(dev->pdev, 2) - (dev->caps.num_uars << PAGE_SHIFT);
 734         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
 735         if (!priv->bf_mapping)
 736                 err = -ENOMEM;
 737
 738         return err;
 739 }
 740
 741 static void unmap_bf_area(struct mlx4_dev *dev)
 742 {
 743         if (mlx4_priv(dev)->bf_mapping)
 744                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
 745 }
 746
 747 static void mlx4_close_hca(struct mlx4_dev *dev)
 748 {
 749         unmap_bf_area(dev);
 750         mlx4_CLOSE_HCA(dev, 0);
 751         mlx4_free_icms(dev);
 752         mlx4_UNMAP_FA(dev);
 753         mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
 754 }
 755
 756 static int mlx4_init_hca(struct mlx4_dev *dev)
 757 {
 758         struct mlx4_priv          *priv = mlx4_priv(dev);
 759         struct mlx4_adapter        adapter;
 760         struct mlx4_dev_cap        dev_cap;
 761         struct mlx4_mod_stat_cfg   mlx4_cfg;
 762         struct mlx4_profile        profile;
 763         struct mlx4_init_hca_param init_hca;
 764         u64 icm_size;
 765         int err;
 766
 767         err = mlx4_QUERY_FW(dev);
 768         if (err) {
 769                 if (err == -EACCES)
 770                         mlx4_info(dev, "non-primary physical function, skipping.\n");
 771                 else
 772                         mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
 773                 return err;
 774         }
 775
 776         err = mlx4_load_fw(dev);
 777         if (err) {
 778                 mlx4_err(dev, "Failed to start FW, aborting.\n");
 779                 return err;
 780         }
 781
 782         mlx4_cfg.log_pg_sz_m = 1;
 783         mlx4_cfg.log_pg_sz = 0;
 784         err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
 785         if (err)
 786                 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
 787
 788         err = mlx4_dev_cap(dev, &dev_cap);
 789         if (err) {
 790                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 791                 goto err_stop_fw;
 792         }
 793
 794         profile = default_profile;
 795
 796         icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
 797         if ((long long) icm_size < 0) {
 798                 err = icm_size;
 799                 goto err_stop_fw;
 800         }
 801
 802         if (map_bf_area(dev))
 803                 mlx4_dbg(dev, "Failed to map blue flame area\n");
 804
 805         init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
 806
 807         err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
 808         if (err)
 809                 goto err_stop_fw;
 810
 811         err = mlx4_INIT_HCA(dev, &init_hca);
 812         if (err) {
 813                 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
 814                 goto err_free_icm;
 815         }
 816
 817         err = mlx4_QUERY_ADAPTER(dev, &adapter);
 818         if (err) {
 819                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
 820                 goto err_close;
 821         }
 822
 823         priv->eq_table.inta_pin = adapter.inta_pin;
 824         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
 825
 826         return 0;
 827
 828 err_close:
 829         mlx4_CLOSE_HCA(dev, 0);
 830
 831 err_free_icm:
 832         mlx4_free_icms(dev);
 833
 834 err_stop_fw:
 835         unmap_bf_area(dev);
 836         mlx4_UNMAP_FA(dev);
 837         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
 838
 839         return err;
 840 }
 841
 842 static int mlx4_init_counters_table(struct mlx4_dev *dev)
 843 {
 844         struct mlx4_priv *priv = mlx4_priv(dev);
 845         int nent;
 846
 847         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
 848                 return -ENOENT;
 849
 850         nent = dev->caps.max_counters;
 851         return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
 852 }
 853
 854 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
 855 {
 856         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
 857 }
 858
 859 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
 860 {
 861         struct mlx4_priv *priv = mlx4_priv(dev);
 862
 863         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
 864                 return -ENOENT;
 865
 866         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
 867         if (*idx == -1)
 868                 return -ENOMEM;
 869
 870         return 0;
 871 }
 872 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
 873
 874 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
 875 {
 876         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
 877         return;
 878 }
 879 EXPORT_SYMBOL_GPL(mlx4_counter_free);
 880
 881 static int mlx4_setup_hca(struct mlx4_dev *dev)
 882 {
 883         struct mlx4_priv *priv = mlx4_priv(dev);
 884         int err;
 885         int port;
 886         __be32 ib_port_default_caps;
 887
 888         err = mlx4_init_uar_table(dev);
 889         if (err) {
 890                 mlx4_err(dev, "Failed to initialize "
 891                          "user access region table, aborting.\n");
 892                 return err;
 893         }
 894
 895         err = mlx4_uar_alloc(dev, &priv->driver_uar);
 896         if (err) {
 897                 mlx4_err(dev, "Failed to allocate driver access region, "
 898                          "aborting.\n");
 899                 goto err_uar_table_free;
 900         }
 901
 902         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
 903         if (!priv->kar) {
 904                 mlx4_err(dev, "Couldn't map kernel access region, "
 905                          "aborting.\n");
 906                 err = -ENOMEM;
 907                 goto err_uar_free;
 908         }
 909
 910         err = mlx4_init_pd_table(dev);
 911         if (err) {
 912                 mlx4_err(dev, "Failed to initialize "
 913                          "protection domain table, aborting.\n");
 914                 goto err_kar_unmap;
 915         }
 916
 917         err = mlx4_init_mr_table(dev);
 918         if (err) {
 919                 mlx4_err(dev, "Failed to initialize "
 920                          "memory region table, aborting.\n");
 921                 goto err_pd_table_free;
 922         }
 923
 924         err = mlx4_init_eq_table(dev);
 925         if (err) {
 926                 mlx4_err(dev, "Failed to initialize "
 927                          "event queue table, aborting.\n");
 928                 goto err_mr_table_free;
 929         }
 930
 931         err = mlx4_cmd_use_events(dev);
 932         if (err) {
 933                 mlx4_err(dev, "Failed to switch to event-driven "
 934                          "firmware commands, aborting.\n");
 935                 goto err_eq_table_free;
 936         }
 937
 938         err = mlx4_NOP(dev);
 939         if (err) {
 940                 if (dev->flags & MLX4_FLAG_MSI_X) {
 941                         mlx4_warn(dev, "NOP command failed to generate MSI-X "
 942                                   "interrupt IRQ %d).\n",
 943                                   priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
 944                         mlx4_warn(dev, "Trying again without MSI-X.\n");
 945                 } else {
 946                         mlx4_err(dev, "NOP command failed to generate interrupt "
 947                                  "(IRQ %d), aborting.\n",
 948                                  priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
 949                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
 950                 }
 951
 952                 goto err_cmd_poll;
 953         }
 954
 955         mlx4_dbg(dev, "NOP command IRQ test passed\n");
 956
 957         err = mlx4_init_cq_table(dev);
 958         if (err) {
 959                 mlx4_err(dev, "Failed to initialize "
 960                          "completion queue table, aborting.\n");
 961                 goto err_cmd_poll;
 962         }
 963
 964         err = mlx4_init_srq_table(dev);
 965         if (err) {
 966                 mlx4_err(dev, "Failed to initialize "
 967                          "shared receive queue table, aborting.\n");
 968                 goto err_cq_table_free;
 969         }
 970
 971         err = mlx4_init_qp_table(dev);
 972         if (err) {
 973                 mlx4_err(dev, "Failed to initialize "
 974                          "queue pair table, aborting.\n");
 975                 goto err_srq_table_free;
 976         }
 977
 978         err = mlx4_init_mcg_table(dev);
 979         if (err) {
 980                 mlx4_err(dev, "Failed to initialize "
 981                          "multicast group table, aborting.\n");
 982                 goto err_qp_table_free;
 983         }
 984
 985         err = mlx4_init_counters_table(dev);
 986         if (err && err != -ENOENT) {
 987                 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
 988                 goto err_counters_table_free;
 989         }
 990
 991         for (port = 1; port <= dev->caps.num_ports; port++) {
 992                 enum mlx4_port_type port_type = 0;
 993                 mlx4_SENSE_PORT(dev, port, &port_type);
 994                 if (port_type)
 995                         dev->caps.port_type[port] = port_type;
 996                 ib_port_default_caps = 0;
 997                 err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps);
 998                 if (err)
 999                         mlx4_warn(dev, "failed to get port %d default "
1000                                   "ib capabilities (%d). Continuing with "
1001                                   "caps = 0\n", port, err);
1002                 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1003                 err = mlx4_SET_PORT(dev, port);
1004                 if (err) {
1005                         mlx4_err(dev, "Failed to set port %d, aborting\n",
1006                                 port);
1007                         goto err_mcg_table_free;
1008                 }
1009         }
1010         mlx4_set_port_mask(dev);
1011
1012         return 0;
1013
1014 err_mcg_table_free:
1015         mlx4_cleanup_mcg_table(dev);
1016
1017 err_counters_table_free:
1018         mlx4_cleanup_counters_table(dev);
1019
1020 err_qp_table_free:
1021         mlx4_cleanup_qp_table(dev);
1022
1023 err_srq_table_free:
1024         mlx4_cleanup_srq_table(dev);
1025
1026 err_cq_table_free:
1027         mlx4_cleanup_cq_table(dev);
1028
1029 err_cmd_poll:
1030         mlx4_cmd_use_polling(dev);
1031
1032 err_eq_table_free:
1033         mlx4_cleanup_eq_table(dev);
1034
1035 err_mr_table_free:
1036         mlx4_cleanup_mr_table(dev);
1037
1038 err_pd_table_free:
1039         mlx4_cleanup_pd_table(dev);
1040
1041 err_kar_unmap:
1042         iounmap(priv->kar);
1043
1044 err_uar_free:
1045         mlx4_uar_free(dev, &priv->driver_uar);
1046
1047 err_uar_table_free:
1048         mlx4_cleanup_uar_table(dev);
1049         return err;
1050 }
1051
1052 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1053 {
1054         struct mlx4_priv *priv = mlx4_priv(dev);
1055         struct msix_entry *entries;
1056         int nreq = min_t(int, dev->caps.num_ports *
1057                          min_t(int, num_online_cpus() + 1, MAX_MSIX_P_PORT)
1058                                 + MSIX_LEGACY_SZ, MAX_MSIX);
1059         int err;
1060         int i;
1061
1062         if (msi_x) {
1063                 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1064                              nreq);
1065                 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1066                 if (!entries)
1067                         goto no_msi;
1068
1069                 for (i = 0; i < nreq; ++i)
1070                         entries[i].entry = i;
1071
1072         retry:
1073                 err = pci_enable_msix(dev->pdev, entries, nreq);
1074                 if (err) {
1075                         /* Try again if at least 2 vectors are available */
1076                         if (err > 1) {
1077                                 mlx4_info(dev, "Requested %d vectors, "
1078                                           "but only %d MSI-X vectors available, "
1079                                           "trying again\n", nreq, err);
1080                                 nreq = err;
1081                                 goto retry;
1082                         }
1083                         kfree(entries);
1084                         goto no_msi;
1085                 }
1086
1087                 if (nreq <
1088                     MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1089                         /*Working in legacy mode , all EQ's shared*/
1090                         dev->caps.comp_pool           = 0;
1091                         dev->caps.num_comp_vectors = nreq - 1;
1092                 } else {
1093                         dev->caps.comp_pool           = nreq - MSIX_LEGACY_SZ;
1094                         dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1095                 }
1096                 for (i = 0; i < nreq; ++i)
1097                         priv->eq_table.eq[i].irq = entries[i].vector;
1098
1099                 dev->flags |= MLX4_FLAG_MSI_X;
1100
1101                 kfree(entries);
1102                 return;
1103         }
1104
1105 no_msi:
1106         dev->caps.num_comp_vectors = 1;
1107         dev->caps.comp_pool        = 0;
1108
1109         for (i = 0; i < 2; ++i)
1110                 priv->eq_table.eq[i].irq = dev->pdev->irq;
1111 }
1112
1113 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1114 {
1115         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1116         int err = 0;
1117
1118         info->dev = dev;
1119         info->port = port;
1120         mlx4_init_mac_table(dev, &info->mac_table);
1121         mlx4_init_vlan_table(dev, &info->vlan_table);
1122         info->base_qpn = dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
1123                         (port - 1) * (1 << log_num_mac);
1124
1125         sprintf(info->dev_name, "mlx4_port%d", port);
1126         info->port_attr.attr.name = info->dev_name;
1127         info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1128         info->port_attr.show      = show_port_type;
1129         info->port_attr.store     = set_port_type;
1130         sysfs_attr_init(&info->port_attr.attr);
1131
1132         err = device_create_file(&dev->pdev->dev, &info->port_attr);
1133         if (err) {
1134                 mlx4_err(dev, "Failed to create file for port %d\n", port);
1135                 info->port = -1;
1136         }
1137
1138         return err;
1139 }
1140
1141 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1142 {
1143         if (info->port < 0)
1144                 return;
1145
1146         device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1147 }
1148
1149 static int mlx4_init_steering(struct mlx4_dev *dev)
1150 {
1151         struct mlx4_priv *priv = mlx4_priv(dev);
1152         int num_entries = dev->caps.num_ports;
1153         int i, j;
1154
1155         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1156         if (!priv->steer)
1157                 return -ENOMEM;
1158
1159         for (i = 0; i < num_entries; i++) {
1160                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1161                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1162                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1163                 }
1164                 INIT_LIST_HEAD(&priv->steer[i].high_prios);
1165         }
1166         return 0;
1167 }
1168
1169 static void mlx4_clear_steering(struct mlx4_dev *dev)
1170 {
1171         struct mlx4_priv *priv = mlx4_priv(dev);
1172         struct mlx4_steer_index *entry, *tmp_entry;
1173         struct mlx4_promisc_qp *pqp, *tmp_pqp;
1174         int num_entries = dev->caps.num_ports;
1175         int i, j;
1176
1177         for (i = 0; i < num_entries; i++) {
1178                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1179                         list_for_each_entry_safe(pqp, tmp_pqp,
1180                                                  &priv->steer[i].promisc_qps[j],
1181                                                  list) {
1182                                 list_del(&pqp->list);
1183                                 kfree(pqp);
1184                         }
1185                         list_for_each_entry_safe(entry, tmp_entry,
1186                                                  &priv->steer[i].steer_entries[j],
1187                                                  list) {
1188                                 list_del(&entry->list);
1189                                 list_for_each_entry_safe(pqp, tmp_pqp,
1190                                                          &entry->duplicates,
1191                                                          list) {
1192                                         list_del(&pqp->list);
1193                                         kfree(pqp);
1194                                 }
1195                                 kfree(entry);
1196                         }
1197                 }
1198         }
1199         kfree(priv->steer);
1200 }
1201
1202 static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1203 {
1204         struct mlx4_priv *priv;
1205         struct mlx4_dev *dev;
1206         int err;
1207         int port;
1208
1209         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
1210
1211         err = pci_enable_device(pdev);
1212         if (err) {
1213                 dev_err(&pdev->dev, "Cannot enable PCI device, "
1214                         "aborting.\n");
1215                 return err;
1216         }
1217
1218         /*
1219          * Check for BARs.  We expect 0: 1MB
1220          */
1221         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
1222             pci_resource_len(pdev, 0) != 1 << 20) {
1223                 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
1224                 err = -ENODEV;
1225                 goto err_disable_pdev;
1226         }
1227         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1228                 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1229                 err = -ENODEV;
1230                 goto err_disable_pdev;
1231         }
1232
1233         err = pci_request_regions(pdev, DRV_NAME);
1234         if (err) {
1235                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
1236                 goto err_disable_pdev;
1237         }
1238
1239         pci_set_master(pdev);
1240
1241         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1242         if (err) {
1243                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
1244                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1245                 if (err) {
1246                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1247                         goto err_release_regions;
1248                 }
1249         }
1250         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1251         if (err) {
1252                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1253                          "consistent PCI DMA mask.\n");
1254                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1255                 if (err) {
1256                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1257                                 "aborting.\n");
1258                         goto err_release_regions;
1259                 }
1260         }
1261
1262         /* Allow large DMA segments, up to the firmware limit of 1 GB */
1263         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
1264
1265         priv = kzalloc(sizeof *priv, GFP_KERNEL);
1266         if (!priv) {
1267                 dev_err(&pdev->dev, "Device struct alloc failed, "
1268                         "aborting.\n");
1269                 err = -ENOMEM;
1270                 goto err_release_regions;
1271         }
1272
1273         dev       = &priv->dev;
1274         dev->pdev = pdev;
1275         INIT_LIST_HEAD(&priv->ctx_list);
1276         spin_lock_init(&priv->ctx_lock);
1277
1278         mutex_init(&priv->port_mutex);
1279
1280         INIT_LIST_HEAD(&priv->pgdir_list);
1281         mutex_init(&priv->pgdir_mutex);
1282
1283         INIT_LIST_HEAD(&priv->bf_list);
1284         mutex_init(&priv->bf_mutex);
1285
1286         dev->rev_id = pdev->revision;
1287
1288         /*
1289          * Now reset the HCA before we touch the PCI capabilities or
1290          * attempt a firmware command, since a boot ROM may have left
1291          * the HCA in an undefined state.
1292          */
1293         err = mlx4_reset(dev);
1294         if (err) {
1295                 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1296                 goto err_free_dev;
1297         }
1298
1299         if (mlx4_cmd_init(dev)) {
1300                 mlx4_err(dev, "Failed to init command interface, aborting.\n");
1301                 goto err_free_dev;
1302         }
1303
1304         err = mlx4_init_hca(dev);
1305         if (err)
1306                 goto err_cmd;
1307
1308         err = mlx4_alloc_eq_table(dev);
1309         if (err)
1310                 goto err_close;
1311
1312         priv->msix_ctl.pool_bm = 0;
1313         spin_lock_init(&priv->msix_ctl.pool_lock);
1314
1315         mlx4_enable_msi_x(dev);
1316
1317         err = mlx4_init_steering(dev);
1318         if (err)
1319                 goto err_free_eq;
1320
1321         err = mlx4_setup_hca(dev);
1322         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
1323                 dev->flags &= ~MLX4_FLAG_MSI_X;
1324                 pci_disable_msix(pdev);
1325                 err = mlx4_setup_hca(dev);
1326         }
1327
1328         if (err)
1329                 goto err_steer;
1330
1331         for (port = 1; port <= dev->caps.num_ports; port++) {
1332                 err = mlx4_init_port_info(dev, port);
1333                 if (err)
1334                         goto err_port;
1335         }
1336
1337         err = mlx4_register_device(dev);
1338         if (err)
1339                 goto err_port;
1340
1341         mlx4_sense_init(dev);
1342         mlx4_start_sense(dev);
1343
1344         pci_set_drvdata(pdev, dev);
1345
1346         return 0;
1347
1348 err_port:
1349         for (--port; port >= 1; --port)
1350                 mlx4_cleanup_port_info(&priv->port[port]);
1351
1352         mlx4_cleanup_counters_table(dev);
1353         mlx4_cleanup_mcg_table(dev);
1354         mlx4_cleanup_qp_table(dev);
1355         mlx4_cleanup_srq_table(dev);
1356         mlx4_cleanup_cq_table(dev);
1357         mlx4_cmd_use_polling(dev);
1358         mlx4_cleanup_eq_table(dev);
1359         mlx4_cleanup_mr_table(dev);
1360         mlx4_cleanup_pd_table(dev);
1361         mlx4_cleanup_uar_table(dev);
1362
1363 err_steer:
1364         mlx4_clear_steering(dev);
1365
1366 err_free_eq:
1367         mlx4_free_eq_table(dev);
1368
1369 err_close:
1370         if (dev->flags & MLX4_FLAG_MSI_X)
1371                 pci_disable_msix(pdev);
1372
1373         mlx4_close_hca(dev);
1374
1375 err_cmd:
1376         mlx4_cmd_cleanup(dev);
1377
1378 err_free_dev:
1379         kfree(priv);
1380
1381 err_release_regions:
1382         pci_release_regions(pdev);
1383
1384 err_disable_pdev:
1385         pci_disable_device(pdev);
1386         pci_set_drvdata(pdev, NULL);
1387         return err;
1388 }
1389
1390 static int __devinit mlx4_init_one(struct pci_dev *pdev,
1391                                    const struct pci_device_id *id)
1392 {
1393         printk_once(KERN_INFO "%s", mlx4_version);
1394
1395         return __mlx4_init_one(pdev, id);
1396 }
1397
1398 static void mlx4_remove_one(struct pci_dev *pdev)
1399 {
1400         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
1401         struct mlx4_priv *priv = mlx4_priv(dev);
1402         int p;
1403
1404         if (dev) {
1405                 mlx4_stop_sense(dev);
1406                 mlx4_unregister_device(dev);
1407
1408                 for (p = 1; p <= dev->caps.num_ports; p++) {
1409                         mlx4_cleanup_port_info(&priv->port[p]);
1410                         mlx4_CLOSE_PORT(dev, p);
1411                 }
1412
1413                 mlx4_cleanup_counters_table(dev);
1414                 mlx4_cleanup_mcg_table(dev);
1415                 mlx4_cleanup_qp_table(dev);
1416                 mlx4_cleanup_srq_table(dev);
1417                 mlx4_cleanup_cq_table(dev);
1418                 mlx4_cmd_use_polling(dev);
1419                 mlx4_cleanup_eq_table(dev);
1420                 mlx4_cleanup_mr_table(dev);
1421                 mlx4_cleanup_pd_table(dev);
1422
1423                 iounmap(priv->kar);
1424                 mlx4_uar_free(dev, &priv->driver_uar);
1425                 mlx4_cleanup_uar_table(dev);
1426                 mlx4_clear_steering(dev);
1427                 mlx4_free_eq_table(dev);
1428                 mlx4_close_hca(dev);
1429                 mlx4_cmd_cleanup(dev);
1430
1431                 if (dev->flags & MLX4_FLAG_MSI_X)
1432                         pci_disable_msix(pdev);
1433
1434                 kfree(priv);
1435                 pci_release_regions(pdev);
1436                 pci_disable_device(pdev);
1437                 pci_set_drvdata(pdev, NULL);
1438         }
1439 }
1440
1441 int mlx4_restart_one(struct pci_dev *pdev)
1442 {
1443         mlx4_remove_one(pdev);
1444         return __mlx4_init_one(pdev, NULL);
1445 }
1446
1447 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
1448         { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
1449         { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
1450         { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
1451         { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
1452         { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
1453         { PCI_VDEVICE(MELLANOX, 0x6368) }, /* MT25408 "Hermon" EN 10GigE */
1454         { PCI_VDEVICE(MELLANOX, 0x6750) }, /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
1455         { PCI_VDEVICE(MELLANOX, 0x6372) }, /* MT25458 ConnectX EN 10GBASE-T 10GigE */
1456         { PCI_VDEVICE(MELLANOX, 0x675a) }, /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
1457         { PCI_VDEVICE(MELLANOX, 0x6764) }, /* MT26468 ConnectX EN 10GigE PCIe gen2*/
1458         { PCI_VDEVICE(MELLANOX, 0x6746) }, /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
1459         { PCI_VDEVICE(MELLANOX, 0x676e) }, /* MT26478 ConnectX2 40GigE PCIe gen2 */
1460         { PCI_VDEVICE(MELLANOX, 0x1002) }, /* MT25400 Family [ConnectX-2 Virtual Function] */
1461         { PCI_VDEVICE(MELLANOX, 0x1003) }, /* MT27500 Family [ConnectX-3] */
1462         { PCI_VDEVICE(MELLANOX, 0x1004) }, /* MT27500 Family [ConnectX-3 Virtual Function] */
1463         { PCI_VDEVICE(MELLANOX, 0x1005) }, /* MT27510 Family */
1464         { PCI_VDEVICE(MELLANOX, 0x1006) }, /* MT27511 Family */
1465         { PCI_VDEVICE(MELLANOX, 0x1007) }, /* MT27520 Family */
1466         { PCI_VDEVICE(MELLANOX, 0x1008) }, /* MT27521 Family */
1467         { PCI_VDEVICE(MELLANOX, 0x1009) }, /* MT27530 Family */
1468         { PCI_VDEVICE(MELLANOX, 0x100a) }, /* MT27531 Family */
1469         { PCI_VDEVICE(MELLANOX, 0x100b) }, /* MT27540 Family */
1470         { PCI_VDEVICE(MELLANOX, 0x100c) }, /* MT27541 Family */
1471         { PCI_VDEVICE(MELLANOX, 0x100d) }, /* MT27550 Family */
1472         { PCI_VDEVICE(MELLANOX, 0x100e) }, /* MT27551 Family */
1473         { PCI_VDEVICE(MELLANOX, 0x100f) }, /* MT27560 Family */
1474         { PCI_VDEVICE(MELLANOX, 0x1010) }, /* MT27561 Family */
1475         { 0, }
1476 };
1477
1478 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
1479
1480 static struct pci_driver mlx4_driver = {
1481         .name           = DRV_NAME,
1482         .id_table       = mlx4_pci_table,
1483         .probe          = mlx4_init_one,
1484         .remove         = __devexit_p(mlx4_remove_one)
1485 };
1486
1487 static int __init mlx4_verify_params(void)
1488 {
1489         if ((log_num_mac < 0) || (log_num_mac > 7)) {
1490                 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
1491                 return -1;
1492         }
1493
1494         if (log_num_vlan != 0)
1495                 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
1496                            MLX4_LOG_NUM_VLANS);
1497
1498         if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
1499                 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
1500                 return -1;
1501         }
1502
1503         return 0;
1504 }
1505
1506 static int __init mlx4_init(void)
1507 {
1508         int ret;
1509
1510         if (mlx4_verify_params())
1511                 return -EINVAL;
1512
1513         mlx4_catas_init();
1514
1515         mlx4_wq = create_singlethread_workqueue("mlx4");
1516         if (!mlx4_wq)
1517                 return -ENOMEM;
1518
1519         ret = pci_register_driver(&mlx4_driver);
1520         return ret < 0 ? ret : 0;
1521 }
1522
1523 static void __exit mlx4_cleanup(void)
1524 {
1525         pci_unregister_driver(&mlx4_driver);
1526         destroy_workqueue(mlx4_wq);
1527 }
1528
1529 module_init(mlx4_init);
1530 module_exit(mlx4_cleanup);