Pileus Git - ~andy/linux/blob - drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47 #include "ixgbe_dcb_82599.h"
  48
  49 char ixgbe_driver_name[] = "ixgbe";
  50 static const char ixgbe_driver_string[] =
  51                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  52
  53 #define DRV_VERSION "2.0.44-k2"
  54 const char ixgbe_driver_version[] = DRV_VERSION;
  55 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  56
  57 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  58         [board_82598] = &ixgbe_82598_info,
  59         [board_82599] = &ixgbe_82599_info,
  60 };
  61
  62 /* ixgbe_pci_tbl - PCI Device ID Table
  63  *
  64  * Wildcard entries (PCI_ANY_ID) should come last
  65  * Last entry must be all 0s
  66  *
  67  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  68  *   Class, Class Mask, private data (not used) }
  69  */
  70 static struct pci_device_id ixgbe_pci_tbl[] = {
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  96          board_82599 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 108          board_82599 },
 109
 110         /* required last entry */
 111         {0, }
 112 };
 113 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 114
 115 #ifdef CONFIG_IXGBE_DCA
 116 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 117                             void *p);
 118 static struct notifier_block dca_notifier = {
 119         .notifier_call = ixgbe_notify_dca,
 120         .next          = NULL,
 121         .priority      = 0
 122 };
 123 #endif
 124
 125 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 126 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 127 MODULE_LICENSE("GPL");
 128 MODULE_VERSION(DRV_VERSION);
 129
 130 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 131
 132 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 133 {
 134         u32 ctrl_ext;
 135
 136         /* Let firmware take over control of h/w */
 137         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 138         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 139                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 140 }
 141
 142 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 143 {
 144         u32 ctrl_ext;
 145
 146         /* Let firmware know the driver has taken over */
 147         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 148         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 149                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 150 }
 151
 152 /*
 153  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 154  * @adapter: pointer to adapter struct
 155  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 156  * @queue: queue to map the corresponding interrupt to
 157  * @msix_vector: the vector to map to the corresponding queue
 158  *
 159  */
 160 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 161                            u8 queue, u8 msix_vector)
 162 {
 163         u32 ivar, index;
 164         struct ixgbe_hw *hw = &adapter->hw;
 165         switch (hw->mac.type) {
 166         case ixgbe_mac_82598EB:
 167                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 168                 if (direction == -1)
 169                         direction = 0;
 170                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 171                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 172                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 173                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 174                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 175                 break;
 176         case ixgbe_mac_82599EB:
 177                 if (direction == -1) {
 178                         /* other causes */
 179                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 180                         index = ((queue & 1) * 8);
 181                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 182                         ivar &= ~(0xFF << index);
 183                         ivar |= (msix_vector << index);
 184                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 185                         break;
 186                 } else {
 187                         /* tx or rx causes */
 188                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 189                         index = ((16 * (queue & 1)) + (8 * direction));
 190                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 191                         ivar &= ~(0xFF << index);
 192                         ivar |= (msix_vector << index);
 193                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 194                         break;
 195                 }
 196         default:
 197                 break;
 198         }
 199 }
 200
 201 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 202                                           u64 qmask)
 203 {
 204         u32 mask;
 205
 206         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 207                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 208                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 209         } else {
 210                 mask = (qmask & 0xFFFFFFFF);
 211                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 212                 mask = (qmask >> 32);
 213                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 214         }
 215 }
 216
 217 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 218                                              struct ixgbe_tx_buffer
 219                                              *tx_buffer_info)
 220 {
 221         tx_buffer_info->dma = 0;
 222         if (tx_buffer_info->skb) {
 223                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 224                               DMA_TO_DEVICE);
 225                 dev_kfree_skb_any(tx_buffer_info->skb);
 226                 tx_buffer_info->skb = NULL;
 227         }
 228         tx_buffer_info->time_stamp = 0;
 229         /* tx_buffer_info must be completely set up in the transmit path */
 230 }
 231
 232 /**
 233  * ixgbe_tx_is_paused - check if the tx ring is paused
 234  * @adapter: the ixgbe adapter
 235  * @tx_ring: the corresponding tx_ring
 236  *
 237  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 238  * corresponding TC of this tx_ring when checking TFCS.
 239  *
 240  * Returns : true if paused
 241  */
 242 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
 243                                       struct ixgbe_ring *tx_ring)
 244 {
 245         int tc;
 246         u32 txoff = IXGBE_TFCS_TXOFF;
 247
 248 #ifdef CONFIG_IXGBE_DCB
 249         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 250                 int reg_idx = tx_ring->reg_idx;
 251                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 252
 253                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 254                         tc = reg_idx >> 2;
 255                         txoff = IXGBE_TFCS_TXOFF0;
 256                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 257                         tc = 0;
 258                         txoff = IXGBE_TFCS_TXOFF;
 259                         if (dcb_i == 8) {
 260                                 /* TC0, TC1 */
 261                                 tc = reg_idx >> 5;
 262                                 if (tc == 2) /* TC2, TC3 */
 263                                         tc += (reg_idx - 64) >> 4;
 264                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 265                                         tc += 1 + ((reg_idx - 96) >> 3);
 266                         } else if (dcb_i == 4) {
 267                                 /* TC0, TC1 */
 268                                 tc = reg_idx >> 6;
 269                                 if (tc == 1) {
 270                                         tc += (reg_idx - 64) >> 5;
 271                                         if (tc == 2) /* TC2, TC3 */
 272                                                 tc += (reg_idx - 96) >> 4;
 273                                 }
 274                         }
 275                 }
 276                 txoff <<= tc;
 277         }
 278 #endif
 279         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 280 }
 281
 282 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 283                                        struct ixgbe_ring *tx_ring,
 284                                        unsigned int eop)
 285 {
 286         struct ixgbe_hw *hw = &adapter->hw;
 287
 288         /* Detect a transmit hang in hardware, this serializes the
 289          * check with the clearing of time_stamp and movement of eop */
 290         adapter->detect_tx_hung = false;
 291         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 292             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 293             !ixgbe_tx_is_paused(adapter, tx_ring)) {
 294                 /* detected Tx unit hang */
 295                 union ixgbe_adv_tx_desc *tx_desc;
 296                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 297                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 298                         "  Tx Queue             <%d>\n"
 299                         "  TDH, TDT             <%x>, <%x>\n"
 300                         "  next_to_use          <%x>\n"
 301                         "  next_to_clean        <%x>\n"
 302                         "tx_buffer_info[next_to_clean]\n"
 303                         "  time_stamp           <%lx>\n"
 304                         "  jiffies              <%lx>\n",
 305                         tx_ring->queue_index,
 306                         IXGBE_READ_REG(hw, tx_ring->head),
 307                         IXGBE_READ_REG(hw, tx_ring->tail),
 308                         tx_ring->next_to_use, eop,
 309                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 310                 return true;
 311         }
 312
 313         return false;
 314 }
 315
 316 #define IXGBE_MAX_TXD_PWR       14
 317 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 318
 319 /* Tx Descriptors needed, worst case */
 320 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 321                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 322 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 323         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 324
 325 static void ixgbe_tx_timeout(struct net_device *netdev);
 326
 327 /**
 328  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 329  * @q_vector: structure containing interrupt and ring information
 330  * @tx_ring: tx ring to clean
 331  **/
 332 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 333                                struct ixgbe_ring *tx_ring)
 334 {
 335         struct ixgbe_adapter *adapter = q_vector->adapter;
 336         struct net_device *netdev = adapter->netdev;
 337         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 338         struct ixgbe_tx_buffer *tx_buffer_info;
 339         unsigned int i, eop, count = 0;
 340         unsigned int total_bytes = 0, total_packets = 0;
 341
 342         i = tx_ring->next_to_clean;
 343         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 344         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 345
 346         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 347                (count < tx_ring->work_limit)) {
 348                 bool cleaned = false;
 349                 for ( ; !cleaned; count++) {
 350                         struct sk_buff *skb;
 351                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 352                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 353                         cleaned = (i == eop);
 354                         skb = tx_buffer_info->skb;
 355
 356                         if (cleaned && skb) {
 357                                 unsigned int segs, bytecount;
 358                                 unsigned int hlen = skb_headlen(skb);
 359
 360                                 /* gso_segs is currently only valid for tcp */
 361                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 362 #ifdef IXGBE_FCOE
 363                                 /* adjust for FCoE Sequence Offload */
 364                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 365                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 366                                     skb_is_gso(skb)) {
 367                                         hlen = skb_transport_offset(skb) +
 368                                                 sizeof(struct fc_frame_header) +
 369                                                 sizeof(struct fcoe_crc_eof);
 370                                         segs = DIV_ROUND_UP(skb->len - hlen,
 371                                                 skb_shinfo(skb)->gso_size);
 372                                 }
 373 #endif /* IXGBE_FCOE */
 374                                 /* multiply data chunks by size of headers */
 375                                 bytecount = ((segs - 1) * hlen) + skb->len;
 376                                 total_packets += segs;
 377                                 total_bytes += bytecount;
 378                         }
 379
 380                         ixgbe_unmap_and_free_tx_resource(adapter,
 381                                                          tx_buffer_info);
 382
 383                         tx_desc->wb.status = 0;
 384
 385                         i++;
 386                         if (i == tx_ring->count)
 387                                 i = 0;
 388                 }
 389
 390                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 391                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 392         }
 393
 394         tx_ring->next_to_clean = i;
 395
 396 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 397         if (unlikely(count && netif_carrier_ok(netdev) &&
 398                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 399                 /* Make sure that anybody stopping the queue after this
 400                  * sees the new next_to_clean.
 401                  */
 402                 smp_mb();
 403                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 404                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 405                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 406                         ++adapter->restart_queue;
 407                 }
 408         }
 409
 410         if (adapter->detect_tx_hung) {
 411                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 412                         /* schedule immediate reset if we believe we hung */
 413                         DPRINTK(PROBE, INFO,
 414                                 "tx hang %d detected, resetting adapter\n",
 415                                 adapter->tx_timeout_count + 1);
 416                         ixgbe_tx_timeout(adapter->netdev);
 417                 }
 418         }
 419
 420         /* re-arm the interrupt */
 421         if (count >= tx_ring->work_limit)
 422                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 423
 424         tx_ring->total_bytes += total_bytes;
 425         tx_ring->total_packets += total_packets;
 426         tx_ring->stats.packets += total_packets;
 427         tx_ring->stats.bytes += total_bytes;
 428         netdev->stats.tx_bytes += total_bytes;
 429         netdev->stats.tx_packets += total_packets;
 430         return (count < tx_ring->work_limit);
 431 }
 432
 433 #ifdef CONFIG_IXGBE_DCA
 434 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 435                                 struct ixgbe_ring *rx_ring)
 436 {
 437         u32 rxctrl;
 438         int cpu = get_cpu();
 439         int q = rx_ring - adapter->rx_ring;
 440
 441         if (rx_ring->cpu != cpu) {
 442                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 443                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 444                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 445                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 446                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 447                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 448                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 449                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 450                 }
 451                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 452                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 453                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 454                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 455                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 456                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 457                 rx_ring->cpu = cpu;
 458         }
 459         put_cpu();
 460 }
 461
 462 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 463                                 struct ixgbe_ring *tx_ring)
 464 {
 465         u32 txctrl;
 466         int cpu = get_cpu();
 467         int q = tx_ring - adapter->tx_ring;
 468         struct ixgbe_hw *hw = &adapter->hw;
 469
 470         if (tx_ring->cpu != cpu) {
 471                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 472                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 473                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 474                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 475                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 476                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 477                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 478                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 479                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 480                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 481                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 482                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 483                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 484                 }
 485                 tx_ring->cpu = cpu;
 486         }
 487         put_cpu();
 488 }
 489
 490 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 491 {
 492         int i;
 493
 494         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 495                 return;
 496
 497         /* always use CB2 mode, difference is masked in the CB driver */
 498         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 499
 500         for (i = 0; i < adapter->num_tx_queues; i++) {
 501                 adapter->tx_ring[i].cpu = -1;
 502                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 503         }
 504         for (i = 0; i < adapter->num_rx_queues; i++) {
 505                 adapter->rx_ring[i].cpu = -1;
 506                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 507         }
 508 }
 509
 510 static int __ixgbe_notify_dca(struct device *dev, void *data)
 511 {
 512         struct net_device *netdev = dev_get_drvdata(dev);
 513         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 514         unsigned long event = *(unsigned long *)data;
 515
 516         switch (event) {
 517         case DCA_PROVIDER_ADD:
 518                 /* if we're already enabled, don't do it again */
 519                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 520                         break;
 521                 if (dca_add_requester(dev) == 0) {
 522                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 523                         ixgbe_setup_dca(adapter);
 524                         break;
 525                 }
 526                 /* Fall Through since DCA is disabled. */
 527         case DCA_PROVIDER_REMOVE:
 528                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 529                         dca_remove_requester(dev);
 530                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 531                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 532                 }
 533                 break;
 534         }
 535
 536         return 0;
 537 }
 538
 539 #endif /* CONFIG_IXGBE_DCA */
 540 /**
 541  * ixgbe_receive_skb - Send a completed packet up the stack
 542  * @adapter: board private structure
 543  * @skb: packet to send up
 544  * @status: hardware indication of status of receive
 545  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 546  * @rx_desc: rx descriptor
 547  **/
 548 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 549                               struct sk_buff *skb, u8 status,
 550                               struct ixgbe_ring *ring,
 551                               union ixgbe_adv_rx_desc *rx_desc)
 552 {
 553         struct ixgbe_adapter *adapter = q_vector->adapter;
 554         struct napi_struct *napi = &q_vector->napi;
 555         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 556         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 557
 558         skb_record_rx_queue(skb, ring->queue_index);
 559         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 560                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 561                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 562                 else
 563                         napi_gro_receive(napi, skb);
 564         } else {
 565                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 566                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 567                 else
 568                         netif_rx(skb);
 569         }
 570 }
 571
 572 /**
 573  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 574  * @adapter: address of board private structure
 575  * @status_err: hardware indication of status of receive
 576  * @skb: skb currently being received and modified
 577  **/
 578 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 579                                      union ixgbe_adv_rx_desc *rx_desc,
 580                                      struct sk_buff *skb)
 581 {
 582         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 583
 584         skb->ip_summed = CHECKSUM_NONE;
 585
 586         /* Rx csum disabled */
 587         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 588                 return;
 589
 590         /* if IP and error */
 591         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 592             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 593                 adapter->hw_csum_rx_error++;
 594                 return;
 595         }
 596
 597         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 598                 return;
 599
 600         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 601                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 602
 603                 /*
 604                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 605                  * checksum errors.
 606                  */
 607                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 608                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 609                         return;
 610
 611                 adapter->hw_csum_rx_error++;
 612                 return;
 613         }
 614
 615         /* It must be a TCP or UDP packet with a valid checksum */
 616         skb->ip_summed = CHECKSUM_UNNECESSARY;
 617         adapter->hw_csum_rx_good++;
 618 }
 619
 620 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 621                                          struct ixgbe_ring *rx_ring, u32 val)
 622 {
 623         /*
 624          * Force memory writes to complete before letting h/w
 625          * know there are new descriptors to fetch.  (Only
 626          * applicable for weak-ordered memory model archs,
 627          * such as IA-64).
 628          */
 629         wmb();
 630         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 631 }
 632
 633 /**
 634  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 635  * @adapter: address of board private structure
 636  **/
 637 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 638                                    struct ixgbe_ring *rx_ring,
 639                                    int cleaned_count)
 640 {
 641         struct pci_dev *pdev = adapter->pdev;
 642         union ixgbe_adv_rx_desc *rx_desc;
 643         struct ixgbe_rx_buffer *bi;
 644         unsigned int i;
 645
 646         i = rx_ring->next_to_use;
 647         bi = &rx_ring->rx_buffer_info[i];
 648
 649         while (cleaned_count--) {
 650                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 651
 652                 if (!bi->page_dma &&
 653                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 654                         if (!bi->page) {
 655                                 bi->page = alloc_page(GFP_ATOMIC);
 656                                 if (!bi->page) {
 657                                         adapter->alloc_rx_page_failed++;
 658                                         goto no_buffers;
 659                                 }
 660                                 bi->page_offset = 0;
 661                         } else {
 662                                 /* use a half page if we're re-using */
 663                                 bi->page_offset ^= (PAGE_SIZE / 2);
 664                         }
 665
 666                         bi->page_dma = pci_map_page(pdev, bi->page,
 667                                                     bi->page_offset,
 668                                                     (PAGE_SIZE / 2),
 669                                                     PCI_DMA_FROMDEVICE);
 670                 }
 671
 672                 if (!bi->skb) {
 673                         struct sk_buff *skb;
 674                         skb = netdev_alloc_skb_ip_align(adapter->netdev,
 675                                                         rx_ring->rx_buf_len);
 676
 677                         if (!skb) {
 678                                 adapter->alloc_rx_buff_failed++;
 679                                 goto no_buffers;
 680                         }
 681
 682                         bi->skb = skb;
 683                         bi->dma = pci_map_single(pdev, skb->data,
 684                                                  rx_ring->rx_buf_len,
 685                                                  PCI_DMA_FROMDEVICE);
 686                 }
 687                 /* Refresh the desc even if buffer_addrs didn't change because
 688                  * each write-back erases this info. */
 689                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 690                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 691                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 692                 } else {
 693                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 694                 }
 695
 696                 i++;
 697                 if (i == rx_ring->count)
 698                         i = 0;
 699                 bi = &rx_ring->rx_buffer_info[i];
 700         }
 701
 702 no_buffers:
 703         if (rx_ring->next_to_use != i) {
 704                 rx_ring->next_to_use = i;
 705                 if (i-- == 0)
 706                         i = (rx_ring->count - 1);
 707
 708                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 709         }
 710 }
 711
 712 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 713 {
 714         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 715 }
 716
 717 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 718 {
 719         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 720 }
 721
 722 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 723 {
 724         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 725                 IXGBE_RXDADV_RSCCNT_MASK) >>
 726                 IXGBE_RXDADV_RSCCNT_SHIFT;
 727 }
 728
 729 /**
 730  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 731  * @skb: pointer to the last skb in the rsc queue
 732  *
 733  * This function changes a queue full of hw rsc buffers into a completed
 734  * packet.  It uses the ->prev pointers to find the first packet and then
 735  * turns it into the frag list owner.
 736  **/
 737 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 738 {
 739         unsigned int frag_list_size = 0;
 740
 741         while (skb->prev) {
 742                 struct sk_buff *prev = skb->prev;
 743                 frag_list_size += skb->len;
 744                 skb->prev = NULL;
 745                 skb = prev;
 746         }
 747
 748         skb_shinfo(skb)->frag_list = skb->next;
 749         skb->next = NULL;
 750         skb->len += frag_list_size;
 751         skb->data_len += frag_list_size;
 752         skb->truesize += frag_list_size;
 753         return skb;
 754 }
 755
 756 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 757                                struct ixgbe_ring *rx_ring,
 758                                int *work_done, int work_to_do)
 759 {
 760         struct ixgbe_adapter *adapter = q_vector->adapter;
 761         struct net_device *netdev = adapter->netdev;
 762         struct pci_dev *pdev = adapter->pdev;
 763         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 764         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 765         struct sk_buff *skb;
 766         unsigned int i, rsc_count = 0;
 767         u32 len, staterr;
 768         u16 hdr_info;
 769         bool cleaned = false;
 770         int cleaned_count = 0;
 771         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 772 #ifdef IXGBE_FCOE
 773         int ddp_bytes = 0;
 774 #endif /* IXGBE_FCOE */
 775
 776         i = rx_ring->next_to_clean;
 777         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 778         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 779         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 780
 781         while (staterr & IXGBE_RXD_STAT_DD) {
 782                 u32 upper_len = 0;
 783                 if (*work_done >= work_to_do)
 784                         break;
 785                 (*work_done)++;
 786
 787                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 788                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 789                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 790                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 791                         if (hdr_info & IXGBE_RXDADV_SPH)
 792                                 adapter->rx_hdr_split++;
 793                         if (len > IXGBE_RX_HDR_SIZE)
 794                                 len = IXGBE_RX_HDR_SIZE;
 795                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 796                 } else {
 797                         len = le16_to_cpu(rx_desc->wb.upper.length);
 798                 }
 799
 800                 cleaned = true;
 801                 skb = rx_buffer_info->skb;
 802                 prefetch(skb->data - NET_IP_ALIGN);
 803                 rx_buffer_info->skb = NULL;
 804
 805                 if (rx_buffer_info->dma) {
 806                         pci_unmap_single(pdev, rx_buffer_info->dma,
 807                                          rx_ring->rx_buf_len,
 808                                          PCI_DMA_FROMDEVICE);
 809                         rx_buffer_info->dma = 0;
 810                         skb_put(skb, len);
 811                 }
 812
 813                 if (upper_len) {
 814                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 815                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 816                         rx_buffer_info->page_dma = 0;
 817                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 818                                            rx_buffer_info->page,
 819                                            rx_buffer_info->page_offset,
 820                                            upper_len);
 821
 822                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 823                             (page_count(rx_buffer_info->page) != 1))
 824                                 rx_buffer_info->page = NULL;
 825                         else
 826                                 get_page(rx_buffer_info->page);
 827
 828                         skb->len += upper_len;
 829                         skb->data_len += upper_len;
 830                         skb->truesize += upper_len;
 831                 }
 832
 833                 i++;
 834                 if (i == rx_ring->count)
 835                         i = 0;
 836
 837                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 838                 prefetch(next_rxd);
 839                 cleaned_count++;
 840
 841                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 842                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 843
 844                 if (rsc_count) {
 845                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 846                                      IXGBE_RXDADV_NEXTP_SHIFT;
 847                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 848                         rx_ring->rsc_count += (rsc_count - 1);
 849                 } else {
 850                         next_buffer = &rx_ring->rx_buffer_info[i];
 851                 }
 852
 853                 if (staterr & IXGBE_RXD_STAT_EOP) {
 854                         if (skb->prev)
 855                                 skb = ixgbe_transform_rsc_queue(skb);
 856                         rx_ring->stats.packets++;
 857                         rx_ring->stats.bytes += skb->len;
 858                 } else {
 859                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 860                                 rx_buffer_info->skb = next_buffer->skb;
 861                                 rx_buffer_info->dma = next_buffer->dma;
 862                                 next_buffer->skb = skb;
 863                                 next_buffer->dma = 0;
 864                         } else {
 865                                 skb->next = next_buffer->skb;
 866                                 skb->next->prev = skb;
 867                         }
 868                         adapter->non_eop_descs++;
 869                         goto next_desc;
 870                 }
 871
 872                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 873                         dev_kfree_skb_irq(skb);
 874                         goto next_desc;
 875                 }
 876
 877                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 878
 879                 /* probably a little skewed due to removing CRC */
 880                 total_rx_bytes += skb->len;
 881                 total_rx_packets++;
 882
 883                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 884 #ifdef IXGBE_FCOE
 885                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 886                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 887                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 888                         if (!ddp_bytes)
 889                                 goto next_desc;
 890                 }
 891 #endif /* IXGBE_FCOE */
 892                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 893
 894 next_desc:
 895                 rx_desc->wb.upper.status_error = 0;
 896
 897                 /* return some buffers to hardware, one at a time is too slow */
 898                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 899                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 900                         cleaned_count = 0;
 901                 }
 902
 903                 /* use prefetched values */
 904                 rx_desc = next_rxd;
 905                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 906
 907                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 908         }
 909
 910         rx_ring->next_to_clean = i;
 911         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 912
 913         if (cleaned_count)
 914                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 915
 916 #ifdef IXGBE_FCOE
 917         /* include DDPed FCoE data */
 918         if (ddp_bytes > 0) {
 919                 unsigned int mss;
 920
 921                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 922                         sizeof(struct fc_frame_header) -
 923                         sizeof(struct fcoe_crc_eof);
 924                 if (mss > 512)
 925                         mss &= ~511;
 926                 total_rx_bytes += ddp_bytes;
 927                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 928         }
 929 #endif /* IXGBE_FCOE */
 930
 931         rx_ring->total_packets += total_rx_packets;
 932         rx_ring->total_bytes += total_rx_bytes;
 933         netdev->stats.rx_bytes += total_rx_bytes;
 934         netdev->stats.rx_packets += total_rx_packets;
 935
 936         return cleaned;
 937 }
 938
 939 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 940 /**
 941  * ixgbe_configure_msix - Configure MSI-X hardware
 942  * @adapter: board private structure
 943  *
 944  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 945  * interrupts.
 946  **/
 947 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 948 {
 949         struct ixgbe_q_vector *q_vector;
 950         int i, j, q_vectors, v_idx, r_idx;
 951         u32 mask;
 952
 953         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 954
 955         /*
 956          * Populate the IVAR table and set the ITR values to the
 957          * corresponding register.
 958          */
 959         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 960                 q_vector = adapter->q_vector[v_idx];
 961                 /* XXX for_each_bit(...) */
 962                 r_idx = find_first_bit(q_vector->rxr_idx,
 963                                        adapter->num_rx_queues);
 964
 965                 for (i = 0; i < q_vector->rxr_count; i++) {
 966                         j = adapter->rx_ring[r_idx].reg_idx;
 967                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 968                         r_idx = find_next_bit(q_vector->rxr_idx,
 969                                               adapter->num_rx_queues,
 970                                               r_idx + 1);
 971                 }
 972                 r_idx = find_first_bit(q_vector->txr_idx,
 973                                        adapter->num_tx_queues);
 974
 975                 for (i = 0; i < q_vector->txr_count; i++) {
 976                         j = adapter->tx_ring[r_idx].reg_idx;
 977                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 978                         r_idx = find_next_bit(q_vector->txr_idx,
 979                                               adapter->num_tx_queues,
 980                                               r_idx + 1);
 981                 }
 982
 983                 if (q_vector->txr_count && !q_vector->rxr_count)
 984                         /* tx only */
 985                         q_vector->eitr = adapter->tx_eitr_param;
 986                 else if (q_vector->rxr_count)
 987                         /* rx or mixed */
 988                         q_vector->eitr = adapter->rx_eitr_param;
 989
 990                 ixgbe_write_eitr(q_vector);
 991         }
 992
 993         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 994                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 995                                v_idx);
 996         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 997                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 998         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 999
1000         /* set up to autoclear timer, and the vectors */
1001         mask = IXGBE_EIMS_ENABLE_MASK;
1002         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1003         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1004 }
1005
1006 enum latency_range {
1007         lowest_latency = 0,
1008         low_latency = 1,
1009         bulk_latency = 2,
1010         latency_invalid = 255
1011 };
1012
1013 /**
1014  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1015  * @adapter: pointer to adapter
1016  * @eitr: eitr setting (ints per sec) to give last timeslice
1017  * @itr_setting: current throttle rate in ints/second
1018  * @packets: the number of packets during this measurement interval
1019  * @bytes: the number of bytes during this measurement interval
1020  *
1021  *      Stores a new ITR value based on packets and byte
1022  *      counts during the last interrupt.  The advantage of per interrupt
1023  *      computation is faster updates and more accurate ITR for the current
1024  *      traffic pattern.  Constants in this function were computed
1025  *      based on theoretical maximum wire speed and thresholds were set based
1026  *      on testing data as well as attempting to minimize response time
1027  *      while increasing bulk throughput.
1028  *      this functionality is controlled by the InterruptThrottleRate module
1029  *      parameter (see ixgbe_param.c)
1030  **/
1031 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1032                            u32 eitr, u8 itr_setting,
1033                            int packets, int bytes)
1034 {
1035         unsigned int retval = itr_setting;
1036         u32 timepassed_us;
1037         u64 bytes_perint;
1038
1039         if (packets == 0)
1040                 goto update_itr_done;
1041
1042
1043         /* simple throttlerate management
1044          *    0-20MB/s lowest (100000 ints/s)
1045          *   20-100MB/s low   (20000 ints/s)
1046          *  100-1249MB/s bulk (8000 ints/s)
1047          */
1048         /* what was last interrupt timeslice? */
1049         timepassed_us = 1000000/eitr;
1050         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1051
1052         switch (itr_setting) {
1053         case lowest_latency:
1054                 if (bytes_perint > adapter->eitr_low)
1055                         retval = low_latency;
1056                 break;
1057         case low_latency:
1058                 if (bytes_perint > adapter->eitr_high)
1059                         retval = bulk_latency;
1060                 else if (bytes_perint <= adapter->eitr_low)
1061                         retval = lowest_latency;
1062                 break;
1063         case bulk_latency:
1064                 if (bytes_perint <= adapter->eitr_high)
1065                         retval = low_latency;
1066                 break;
1067         }
1068
1069 update_itr_done:
1070         return retval;
1071 }
1072
1073 /**
1074  * ixgbe_write_eitr - write EITR register in hardware specific way
1075  * @q_vector: structure containing interrupt and ring information
1076  *
1077  * This function is made to be called by ethtool and by the driver
1078  * when it needs to update EITR registers at runtime.  Hardware
1079  * specific quirks/differences are taken care of here.
1080  */
1081 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1082 {
1083         struct ixgbe_adapter *adapter = q_vector->adapter;
1084         struct ixgbe_hw *hw = &adapter->hw;
1085         int v_idx = q_vector->v_idx;
1086         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1087
1088         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1089                 /* must write high and low 16 bits to reset counter */
1090                 itr_reg |= (itr_reg << 16);
1091         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1092                 /*
1093                  * set the WDIS bit to not clear the timer bits and cause an
1094                  * immediate assertion of the interrupt
1095                  */
1096                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1097         }
1098         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1099 }
1100
1101 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1102 {
1103         struct ixgbe_adapter *adapter = q_vector->adapter;
1104         u32 new_itr;
1105         u8 current_itr, ret_itr;
1106         int i, r_idx;
1107         struct ixgbe_ring *rx_ring, *tx_ring;
1108
1109         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1110         for (i = 0; i < q_vector->txr_count; i++) {
1111                 tx_ring = &(adapter->tx_ring[r_idx]);
1112                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1113                                            q_vector->tx_itr,
1114                                            tx_ring->total_packets,
1115                                            tx_ring->total_bytes);
1116                 /* if the result for this queue would decrease interrupt
1117                  * rate for this vector then use that result */
1118                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1119                                     q_vector->tx_itr - 1 : ret_itr);
1120                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1121                                       r_idx + 1);
1122         }
1123
1124         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1125         for (i = 0; i < q_vector->rxr_count; i++) {
1126                 rx_ring = &(adapter->rx_ring[r_idx]);
1127                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1128                                            q_vector->rx_itr,
1129                                            rx_ring->total_packets,
1130                                            rx_ring->total_bytes);
1131                 /* if the result for this queue would decrease interrupt
1132                  * rate for this vector then use that result */
1133                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1134                                     q_vector->rx_itr - 1 : ret_itr);
1135                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1136                                       r_idx + 1);
1137         }
1138
1139         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1140
1141         switch (current_itr) {
1142         /* counts and packets in update_itr are dependent on these numbers */
1143         case lowest_latency:
1144                 new_itr = 100000;
1145                 break;
1146         case low_latency:
1147                 new_itr = 20000; /* aka hwitr = ~200 */
1148                 break;
1149         case bulk_latency:
1150         default:
1151                 new_itr = 8000;
1152                 break;
1153         }
1154
1155         if (new_itr != q_vector->eitr) {
1156                 /* do an exponential smoothing */
1157                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1158
1159                 /* save the algorithm value here, not the smoothed one */
1160                 q_vector->eitr = new_itr;
1161
1162                 ixgbe_write_eitr(q_vector);
1163         }
1164
1165         return;
1166 }
1167
1168 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1169 {
1170         struct ixgbe_hw *hw = &adapter->hw;
1171
1172         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1173             (eicr & IXGBE_EICR_GPI_SDP1)) {
1174                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1175                 /* write to clear the interrupt */
1176                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1177         }
1178 }
1179
1180 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1181 {
1182         struct ixgbe_hw *hw = &adapter->hw;
1183
1184         if (eicr & IXGBE_EICR_GPI_SDP1) {
1185                 /* Clear the interrupt */
1186                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1187                 schedule_work(&adapter->multispeed_fiber_task);
1188         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1189                 /* Clear the interrupt */
1190                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1191                 schedule_work(&adapter->sfp_config_module_task);
1192         } else {
1193                 /* Interrupt isn't for us... */
1194                 return;
1195         }
1196 }
1197
1198 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1199 {
1200         struct ixgbe_hw *hw = &adapter->hw;
1201
1202         adapter->lsc_int++;
1203         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1204         adapter->link_check_timeout = jiffies;
1205         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1206                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1207                 schedule_work(&adapter->watchdog_task);
1208         }
1209 }
1210
1211 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1212 {
1213         struct net_device *netdev = data;
1214         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1215         struct ixgbe_hw *hw = &adapter->hw;
1216         u32 eicr;
1217
1218         /*
1219          * Workaround for Silicon errata.  Use clear-by-write instead
1220          * of clear-by-read.  Reading with EICS will return the
1221          * interrupt causes without clearing, which later be done
1222          * with the write to EICR.
1223          */
1224         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1225         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1226
1227         if (eicr & IXGBE_EICR_LSC)
1228                 ixgbe_check_lsc(adapter);
1229
1230         if (hw->mac.type == ixgbe_mac_82598EB)
1231                 ixgbe_check_fan_failure(adapter, eicr);
1232
1233         if (hw->mac.type == ixgbe_mac_82599EB) {
1234                 ixgbe_check_sfp_event(adapter, eicr);
1235
1236                 /* Handle Flow Director Full threshold interrupt */
1237                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1238                         int i;
1239                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1240                         /* Disable transmits before FDIR Re-initialization */
1241                         netif_tx_stop_all_queues(netdev);
1242                         for (i = 0; i < adapter->num_tx_queues; i++) {
1243                                 struct ixgbe_ring *tx_ring =
1244                                                            &adapter->tx_ring[i];
1245                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1246                                                        &tx_ring->reinit_state))
1247                                         schedule_work(&adapter->fdir_reinit_task);
1248                         }
1249                 }
1250         }
1251         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1252                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1253
1254         return IRQ_HANDLED;
1255 }
1256
1257 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1258                                            u64 qmask)
1259 {
1260         u32 mask;
1261
1262         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1263                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1264                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1265         } else {
1266                 mask = (qmask & 0xFFFFFFFF);
1267                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1268                 mask = (qmask >> 32);
1269                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1270         }
1271         /* skip the flush */
1272 }
1273
1274 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1275                                             u64 qmask)
1276 {
1277         u32 mask;
1278
1279         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1280                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1281                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1282         } else {
1283                 mask = (qmask & 0xFFFFFFFF);
1284                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1285                 mask = (qmask >> 32);
1286                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1287         }
1288         /* skip the flush */
1289 }
1290
1291 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1292 {
1293         struct ixgbe_q_vector *q_vector = data;
1294         struct ixgbe_adapter  *adapter = q_vector->adapter;
1295         struct ixgbe_ring     *tx_ring;
1296         int i, r_idx;
1297
1298         if (!q_vector->txr_count)
1299                 return IRQ_HANDLED;
1300
1301         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1302         for (i = 0; i < q_vector->txr_count; i++) {
1303                 tx_ring = &(adapter->tx_ring[r_idx]);
1304                 tx_ring->total_bytes = 0;
1305                 tx_ring->total_packets = 0;
1306                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1307                                       r_idx + 1);
1308         }
1309
1310         /* disable interrupts on this vector only */
1311         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1312         napi_schedule(&q_vector->napi);
1313
1314         return IRQ_HANDLED;
1315 }
1316
1317 /**
1318  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1319  * @irq: unused
1320  * @data: pointer to our q_vector struct for this interrupt vector
1321  **/
1322 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1323 {
1324         struct ixgbe_q_vector *q_vector = data;
1325         struct ixgbe_adapter  *adapter = q_vector->adapter;
1326         struct ixgbe_ring  *rx_ring;
1327         int r_idx;
1328         int i;
1329
1330         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1331         for (i = 0;  i < q_vector->rxr_count; i++) {
1332                 rx_ring = &(adapter->rx_ring[r_idx]);
1333                 rx_ring->total_bytes = 0;
1334                 rx_ring->total_packets = 0;
1335                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1336                                       r_idx + 1);
1337         }
1338
1339         if (!q_vector->rxr_count)
1340                 return IRQ_HANDLED;
1341
1342         /* disable interrupts on this vector only */
1343         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1344         napi_schedule(&q_vector->napi);
1345
1346         return IRQ_HANDLED;
1347 }
1348
1349 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1350 {
1351         struct ixgbe_q_vector *q_vector = data;
1352         struct ixgbe_adapter  *adapter = q_vector->adapter;
1353         struct ixgbe_ring  *ring;
1354         int r_idx;
1355         int i;
1356
1357         if (!q_vector->txr_count && !q_vector->rxr_count)
1358                 return IRQ_HANDLED;
1359
1360         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1361         for (i = 0; i < q_vector->txr_count; i++) {
1362                 ring = &(adapter->tx_ring[r_idx]);
1363                 ring->total_bytes = 0;
1364                 ring->total_packets = 0;
1365                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1366                                       r_idx + 1);
1367         }
1368
1369         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1370         for (i = 0; i < q_vector->rxr_count; i++) {
1371                 ring = &(adapter->rx_ring[r_idx]);
1372                 ring->total_bytes = 0;
1373                 ring->total_packets = 0;
1374                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1375                                       r_idx + 1);
1376         }
1377
1378         /* disable interrupts on this vector only */
1379         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1380         napi_schedule(&q_vector->napi);
1381
1382         return IRQ_HANDLED;
1383 }
1384
1385 /**
1386  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1387  * @napi: napi struct with our devices info in it
1388  * @budget: amount of work driver is allowed to do this pass, in packets
1389  *
1390  * This function is optimized for cleaning one queue only on a single
1391  * q_vector!!!
1392  **/
1393 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1394 {
1395         struct ixgbe_q_vector *q_vector =
1396                                container_of(napi, struct ixgbe_q_vector, napi);
1397         struct ixgbe_adapter *adapter = q_vector->adapter;
1398         struct ixgbe_ring *rx_ring = NULL;
1399         int work_done = 0;
1400         long r_idx;
1401
1402         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1403         rx_ring = &(adapter->rx_ring[r_idx]);
1404 #ifdef CONFIG_IXGBE_DCA
1405         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1406                 ixgbe_update_rx_dca(adapter, rx_ring);
1407 #endif
1408
1409         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1410
1411         /* If all Rx work done, exit the polling mode */
1412         if (work_done < budget) {
1413                 napi_complete(napi);
1414                 if (adapter->rx_itr_setting & 1)
1415                         ixgbe_set_itr_msix(q_vector);
1416                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1417                         ixgbe_irq_enable_queues(adapter,
1418                                                 ((u64)1 << q_vector->v_idx));
1419         }
1420
1421         return work_done;
1422 }
1423
1424 /**
1425  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1426  * @napi: napi struct with our devices info in it
1427  * @budget: amount of work driver is allowed to do this pass, in packets
1428  *
1429  * This function will clean more than one rx queue associated with a
1430  * q_vector.
1431  **/
1432 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1433 {
1434         struct ixgbe_q_vector *q_vector =
1435                                container_of(napi, struct ixgbe_q_vector, napi);
1436         struct ixgbe_adapter *adapter = q_vector->adapter;
1437         struct ixgbe_ring *ring = NULL;
1438         int work_done = 0, i;
1439         long r_idx;
1440         bool tx_clean_complete = true;
1441
1442         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1443         for (i = 0; i < q_vector->txr_count; i++) {
1444                 ring = &(adapter->tx_ring[r_idx]);
1445 #ifdef CONFIG_IXGBE_DCA
1446                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1447                         ixgbe_update_tx_dca(adapter, ring);
1448 #endif
1449                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1450                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1451                                       r_idx + 1);
1452         }
1453
1454         /* attempt to distribute budget to each queue fairly, but don't allow
1455          * the budget to go below 1 because we'll exit polling */
1456         budget /= (q_vector->rxr_count ?: 1);
1457         budget = max(budget, 1);
1458         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1459         for (i = 0; i < q_vector->rxr_count; i++) {
1460                 ring = &(adapter->rx_ring[r_idx]);
1461 #ifdef CONFIG_IXGBE_DCA
1462                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1463                         ixgbe_update_rx_dca(adapter, ring);
1464 #endif
1465                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1466                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1467                                       r_idx + 1);
1468         }
1469
1470         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1471         ring = &(adapter->rx_ring[r_idx]);
1472         /* If all Rx work done, exit the polling mode */
1473         if (work_done < budget) {
1474                 napi_complete(napi);
1475                 if (adapter->rx_itr_setting & 1)
1476                         ixgbe_set_itr_msix(q_vector);
1477                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1478                         ixgbe_irq_enable_queues(adapter,
1479                                                 ((u64)1 << q_vector->v_idx));
1480                 return 0;
1481         }
1482
1483         return work_done;
1484 }
1485
1486 /**
1487  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1488  * @napi: napi struct with our devices info in it
1489  * @budget: amount of work driver is allowed to do this pass, in packets
1490  *
1491  * This function is optimized for cleaning one queue only on a single
1492  * q_vector!!!
1493  **/
1494 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1495 {
1496         struct ixgbe_q_vector *q_vector =
1497                                container_of(napi, struct ixgbe_q_vector, napi);
1498         struct ixgbe_adapter *adapter = q_vector->adapter;
1499         struct ixgbe_ring *tx_ring = NULL;
1500         int work_done = 0;
1501         long r_idx;
1502
1503         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1504         tx_ring = &(adapter->tx_ring[r_idx]);
1505 #ifdef CONFIG_IXGBE_DCA
1506         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1507                 ixgbe_update_tx_dca(adapter, tx_ring);
1508 #endif
1509
1510         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1511                 work_done = budget;
1512
1513         /* If all Tx work done, exit the polling mode */
1514         if (work_done < budget) {
1515                 napi_complete(napi);
1516                 if (adapter->tx_itr_setting & 1)
1517                         ixgbe_set_itr_msix(q_vector);
1518                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1519                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1520         }
1521
1522         return work_done;
1523 }
1524
1525 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1526                                      int r_idx)
1527 {
1528         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1529
1530         set_bit(r_idx, q_vector->rxr_idx);
1531         q_vector->rxr_count++;
1532 }
1533
1534 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1535                                      int t_idx)
1536 {
1537         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1538
1539         set_bit(t_idx, q_vector->txr_idx);
1540         q_vector->txr_count++;
1541 }
1542
1543 /**
1544  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1545  * @adapter: board private structure to initialize
1546  * @vectors: allotted vector count for descriptor rings
1547  *
1548  * This function maps descriptor rings to the queue-specific vectors
1549  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1550  * one vector per ring/queue, but on a constrained vector budget, we
1551  * group the rings as "efficiently" as possible.  You would add new
1552  * mapping configurations in here.
1553  **/
1554 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1555                                       int vectors)
1556 {
1557         int v_start = 0;
1558         int rxr_idx = 0, txr_idx = 0;
1559         int rxr_remaining = adapter->num_rx_queues;
1560         int txr_remaining = adapter->num_tx_queues;
1561         int i, j;
1562         int rqpv, tqpv;
1563         int err = 0;
1564
1565         /* No mapping required if MSI-X is disabled. */
1566         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1567                 goto out;
1568
1569         /*
1570          * The ideal configuration...
1571          * We have enough vectors to map one per queue.
1572          */
1573         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1574                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1575                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1576
1577                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1578                         map_vector_to_txq(adapter, v_start, txr_idx);
1579
1580                 goto out;
1581         }
1582
1583         /*
1584          * If we don't have enough vectors for a 1-to-1
1585          * mapping, we'll have to group them so there are
1586          * multiple queues per vector.
1587          */
1588         /* Re-adjusting *qpv takes care of the remainder. */
1589         for (i = v_start; i < vectors; i++) {
1590                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1591                 for (j = 0; j < rqpv; j++) {
1592                         map_vector_to_rxq(adapter, i, rxr_idx);
1593                         rxr_idx++;
1594                         rxr_remaining--;
1595                 }
1596         }
1597         for (i = v_start; i < vectors; i++) {
1598                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1599                 for (j = 0; j < tqpv; j++) {
1600                         map_vector_to_txq(adapter, i, txr_idx);
1601                         txr_idx++;
1602                         txr_remaining--;
1603                 }
1604         }
1605
1606 out:
1607         return err;
1608 }
1609
1610 /**
1611  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1612  * @adapter: board private structure
1613  *
1614  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1615  * interrupts from the kernel.
1616  **/
1617 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1618 {
1619         struct net_device *netdev = adapter->netdev;
1620         irqreturn_t (*handler)(int, void *);
1621         int i, vector, q_vectors, err;
1622         int ri=0, ti=0;
1623
1624         /* Decrement for Other and TCP Timer vectors */
1625         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1626
1627         /* Map the Tx/Rx rings to the vectors we were allotted. */
1628         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1629         if (err)
1630                 goto out;
1631
1632 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1633                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1634                          &ixgbe_msix_clean_many)
1635         for (vector = 0; vector < q_vectors; vector++) {
1636                 handler = SET_HANDLER(adapter->q_vector[vector]);
1637
1638                 if(handler == &ixgbe_msix_clean_rx) {
1639                         sprintf(adapter->name[vector], "%s-%s-%d",
1640                                 netdev->name, "rx", ri++);
1641                 }
1642                 else if(handler == &ixgbe_msix_clean_tx) {
1643                         sprintf(adapter->name[vector], "%s-%s-%d",
1644                                 netdev->name, "tx", ti++);
1645                 }
1646                 else
1647                         sprintf(adapter->name[vector], "%s-%s-%d",
1648                                 netdev->name, "TxRx", vector);
1649
1650                 err = request_irq(adapter->msix_entries[vector].vector,
1651                                   handler, 0, adapter->name[vector],
1652                                   adapter->q_vector[vector]);
1653                 if (err) {
1654                         DPRINTK(PROBE, ERR,
1655                                 "request_irq failed for MSIX interrupt "
1656                                 "Error: %d\n", err);
1657                         goto free_queue_irqs;
1658                 }
1659         }
1660
1661         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1662         err = request_irq(adapter->msix_entries[vector].vector,
1663                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1664         if (err) {
1665                 DPRINTK(PROBE, ERR,
1666                         "request_irq for msix_lsc failed: %d\n", err);
1667                 goto free_queue_irqs;
1668         }
1669
1670         return 0;
1671
1672 free_queue_irqs:
1673         for (i = vector - 1; i >= 0; i--)
1674                 free_irq(adapter->msix_entries[--vector].vector,
1675                          adapter->q_vector[i]);
1676         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1677         pci_disable_msix(adapter->pdev);
1678         kfree(adapter->msix_entries);
1679         adapter->msix_entries = NULL;
1680 out:
1681         return err;
1682 }
1683
1684 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1685 {
1686         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1687         u8 current_itr;
1688         u32 new_itr = q_vector->eitr;
1689         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1690         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1691
1692         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1693                                             q_vector->tx_itr,
1694                                             tx_ring->total_packets,
1695                                             tx_ring->total_bytes);
1696         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1697                                             q_vector->rx_itr,
1698                                             rx_ring->total_packets,
1699                                             rx_ring->total_bytes);
1700
1701         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1702
1703         switch (current_itr) {
1704         /* counts and packets in update_itr are dependent on these numbers */
1705         case lowest_latency:
1706                 new_itr = 100000;
1707                 break;
1708         case low_latency:
1709                 new_itr = 20000; /* aka hwitr = ~200 */
1710                 break;
1711         case bulk_latency:
1712                 new_itr = 8000;
1713                 break;
1714         default:
1715                 break;
1716         }
1717
1718         if (new_itr != q_vector->eitr) {
1719                 /* do an exponential smoothing */
1720                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1721
1722                 /* save the algorithm value here, not the smoothed one */
1723                 q_vector->eitr = new_itr;
1724
1725                 ixgbe_write_eitr(q_vector);
1726         }
1727
1728         return;
1729 }
1730
1731 /**
1732  * ixgbe_irq_enable - Enable default interrupt generation settings
1733  * @adapter: board private structure
1734  **/
1735 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1736 {
1737         u32 mask;
1738
1739         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1740         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1741                 mask |= IXGBE_EIMS_GPI_SDP1;
1742         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1743                 mask |= IXGBE_EIMS_ECC;
1744                 mask |= IXGBE_EIMS_GPI_SDP1;
1745                 mask |= IXGBE_EIMS_GPI_SDP2;
1746         }
1747         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1748             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1749                 mask |= IXGBE_EIMS_FLOW_DIR;
1750
1751         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1752         ixgbe_irq_enable_queues(adapter, ~0);
1753         IXGBE_WRITE_FLUSH(&adapter->hw);
1754 }
1755
1756 /**
1757  * ixgbe_intr - legacy mode Interrupt Handler
1758  * @irq: interrupt number
1759  * @data: pointer to a network interface device structure
1760  **/
1761 static irqreturn_t ixgbe_intr(int irq, void *data)
1762 {
1763         struct net_device *netdev = data;
1764         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1765         struct ixgbe_hw *hw = &adapter->hw;
1766         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1767         u32 eicr;
1768
1769         /*
1770          * Workaround for silicon errata.  Mask the interrupts
1771          * before the read of EICR.
1772          */
1773         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1774
1775         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1776          * therefore no explict interrupt disable is necessary */
1777         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1778         if (!eicr) {
1779                 /* shared interrupt alert!
1780                  * make sure interrupts are enabled because the read will
1781                  * have disabled interrupts due to EIAM */
1782                 ixgbe_irq_enable(adapter);
1783                 return IRQ_NONE;        /* Not our interrupt */
1784         }
1785
1786         if (eicr & IXGBE_EICR_LSC)
1787                 ixgbe_check_lsc(adapter);
1788
1789         if (hw->mac.type == ixgbe_mac_82599EB)
1790                 ixgbe_check_sfp_event(adapter, eicr);
1791
1792         ixgbe_check_fan_failure(adapter, eicr);
1793
1794         if (napi_schedule_prep(&(q_vector->napi))) {
1795                 adapter->tx_ring[0].total_packets = 0;
1796                 adapter->tx_ring[0].total_bytes = 0;
1797                 adapter->rx_ring[0].total_packets = 0;
1798                 adapter->rx_ring[0].total_bytes = 0;
1799                 /* would disable interrupts here but EIAM disabled it */
1800                 __napi_schedule(&(q_vector->napi));
1801         }
1802
1803         return IRQ_HANDLED;
1804 }
1805
1806 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1807 {
1808         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1809
1810         for (i = 0; i < q_vectors; i++) {
1811                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1812                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1813                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1814                 q_vector->rxr_count = 0;
1815                 q_vector->txr_count = 0;
1816         }
1817 }
1818
1819 /**
1820  * ixgbe_request_irq - initialize interrupts
1821  * @adapter: board private structure
1822  *
1823  * Attempts to configure interrupts using the best available
1824  * capabilities of the hardware and kernel.
1825  **/
1826 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1827 {
1828         struct net_device *netdev = adapter->netdev;
1829         int err;
1830
1831         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1832                 err = ixgbe_request_msix_irqs(adapter);
1833         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1834                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1835                                   netdev->name, netdev);
1836         } else {
1837                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1838                                   netdev->name, netdev);
1839         }
1840
1841         if (err)
1842                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1843
1844         return err;
1845 }
1846
1847 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1848 {
1849         struct net_device *netdev = adapter->netdev;
1850
1851         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1852                 int i, q_vectors;
1853
1854                 q_vectors = adapter->num_msix_vectors;
1855
1856                 i = q_vectors - 1;
1857                 free_irq(adapter->msix_entries[i].vector, netdev);
1858
1859                 i--;
1860                 for (; i >= 0; i--) {
1861                         free_irq(adapter->msix_entries[i].vector,
1862                                  adapter->q_vector[i]);
1863                 }
1864
1865                 ixgbe_reset_q_vectors(adapter);
1866         } else {
1867                 free_irq(adapter->pdev->irq, netdev);
1868         }
1869 }
1870
1871 /**
1872  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1873  * @adapter: board private structure
1874  **/
1875 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1876 {
1877         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1878                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1879         } else {
1880                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1881                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1882                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1883         }
1884         IXGBE_WRITE_FLUSH(&adapter->hw);
1885         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1886                 int i;
1887                 for (i = 0; i < adapter->num_msix_vectors; i++)
1888                         synchronize_irq(adapter->msix_entries[i].vector);
1889         } else {
1890                 synchronize_irq(adapter->pdev->irq);
1891         }
1892 }
1893
1894 /**
1895  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1896  *
1897  **/
1898 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1899 {
1900         struct ixgbe_hw *hw = &adapter->hw;
1901
1902         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1903                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1904
1905         ixgbe_set_ivar(adapter, 0, 0, 0);
1906         ixgbe_set_ivar(adapter, 1, 0, 0);
1907
1908         map_vector_to_rxq(adapter, 0, 0);
1909         map_vector_to_txq(adapter, 0, 0);
1910
1911         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1912 }
1913
1914 /**
1915  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1916  * @adapter: board private structure
1917  *
1918  * Configure the Tx unit of the MAC after a reset.
1919  **/
1920 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1921 {
1922         u64 tdba;
1923         struct ixgbe_hw *hw = &adapter->hw;
1924         u32 i, j, tdlen, txctrl;
1925
1926         /* Setup the HW Tx Head and Tail descriptor pointers */
1927         for (i = 0; i < adapter->num_tx_queues; i++) {
1928                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1929                 j = ring->reg_idx;
1930                 tdba = ring->dma;
1931                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1932                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1933                                 (tdba & DMA_BIT_MASK(32)));
1934                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1935                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1936                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1937                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1938                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1939                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1940                 /*
1941                  * Disable Tx Head Writeback RO bit, since this hoses
1942                  * bookkeeping if things aren't delivered in order.
1943                  */
1944                 switch (hw->mac.type) {
1945                 case ixgbe_mac_82598EB:
1946                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1947                         break;
1948                 case ixgbe_mac_82599EB:
1949                 default:
1950                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1951                         break;
1952                 }
1953                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1954                 switch (hw->mac.type) {
1955                 case ixgbe_mac_82598EB:
1956                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1957                         break;
1958                 case ixgbe_mac_82599EB:
1959                 default:
1960                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1961                         break;
1962                 }
1963         }
1964
1965         if (hw->mac.type == ixgbe_mac_82599EB) {
1966                 u32 rttdcs;
1967
1968                 /* disable the arbiter while setting MTQC */
1969                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
1970                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
1971                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1972
1973                 /* We enable 8 traffic classes, DCB only */
1974                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1975                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1976                                         IXGBE_MTQC_8TC_8TQ));
1977                 else
1978                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1979
1980                 /* re-eable the arbiter */
1981                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
1982                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1983         }
1984 }
1985
1986 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1987
1988 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1989                                    struct ixgbe_ring *rx_ring)
1990 {
1991         u32 srrctl;
1992         int index;
1993         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1994
1995         index = rx_ring->reg_idx;
1996         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1997                 unsigned long mask;
1998                 mask = (unsigned long) feature[RING_F_RSS].mask;
1999                 index = index & mask;
2000         }
2001         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2002
2003         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2004         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2005
2006         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2007                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2008
2009         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2010 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2011                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2012 #else
2013                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2014 #endif
2015                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2016         } else {
2017                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2018                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2019                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2020         }
2021
2022         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2023 }
2024
2025 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2026 {
2027         u32 mrqc = 0;
2028         int mask;
2029
2030         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2031                 return mrqc;
2032
2033         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2034 #ifdef CONFIG_IXGBE_DCB
2035                                  | IXGBE_FLAG_DCB_ENABLED
2036 #endif
2037                                 );
2038
2039         switch (mask) {
2040         case (IXGBE_FLAG_RSS_ENABLED):
2041                 mrqc = IXGBE_MRQC_RSSEN;
2042                 break;
2043 #ifdef CONFIG_IXGBE_DCB
2044         case (IXGBE_FLAG_DCB_ENABLED):
2045                 mrqc = IXGBE_MRQC_RT8TCEN;
2046                 break;
2047 #endif /* CONFIG_IXGBE_DCB */
2048         default:
2049                 break;
2050         }
2051
2052         return mrqc;
2053 }
2054
2055 /**
2056  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2057  * @adapter:    address of board private structure
2058  * @index:      index of ring to set
2059  * @rx_buf_len: rx buffer length
2060  **/
2061 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index,
2062                                    int rx_buf_len)
2063 {
2064         struct ixgbe_ring *rx_ring;
2065         struct ixgbe_hw *hw = &adapter->hw;
2066         int j;
2067         u32 rscctrl;
2068
2069         rx_ring = &adapter->rx_ring[index];
2070         j = rx_ring->reg_idx;
2071         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2072         rscctrl |= IXGBE_RSCCTL_RSCEN;
2073         /*
2074          * we must limit the number of descriptors so that the
2075          * total size of max desc * buf_len is not greater
2076          * than 65535
2077          */
2078         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2079 #if (MAX_SKB_FRAGS > 16)
2080                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2081 #elif (MAX_SKB_FRAGS > 8)
2082                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2083 #elif (MAX_SKB_FRAGS > 4)
2084                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2085 #else
2086                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2087 #endif
2088         } else {
2089                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2090                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2091                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2092                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2093                 else
2094                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2095         }
2096         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2097 }
2098
2099 /**
2100  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2101  * @adapter: board private structure
2102  *
2103  * Configure the Rx unit of the MAC after a reset.
2104  **/
2105 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2106 {
2107         u64 rdba;
2108         struct ixgbe_hw *hw = &adapter->hw;
2109         struct ixgbe_ring *rx_ring;
2110         struct net_device *netdev = adapter->netdev;
2111         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2112         int i, j;
2113         u32 rdlen, rxctrl, rxcsum;
2114         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2115                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2116                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2117         u32 fctrl, hlreg0;
2118         u32 reta = 0, mrqc = 0;
2119         u32 rdrxctl;
2120         int rx_buf_len;
2121
2122         /* Decide whether to use packet split mode or not */
2123         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2124
2125         /* Set the RX buffer length according to the mode */
2126         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2127                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2128                 if (hw->mac.type == ixgbe_mac_82599EB) {
2129                         /* PSRTYPE must be initialized in 82599 */
2130                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2131                                       IXGBE_PSRTYPE_UDPHDR |
2132                                       IXGBE_PSRTYPE_IPV4HDR |
2133                                       IXGBE_PSRTYPE_IPV6HDR |
2134                                       IXGBE_PSRTYPE_L2HDR;
2135                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2136                 }
2137         } else {
2138                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2139                     (netdev->mtu <= ETH_DATA_LEN))
2140                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2141                 else
2142                         rx_buf_len = ALIGN(max_frame, 1024);
2143         }
2144
2145         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2146         fctrl |= IXGBE_FCTRL_BAM;
2147         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2148         fctrl |= IXGBE_FCTRL_PMCF;
2149         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2150
2151         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2152         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2153                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2154         else
2155                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2156 #ifdef IXGBE_FCOE
2157         if (netdev->features & NETIF_F_FCOE_MTU)
2158                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2159 #endif
2160         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2161
2162         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2163         /* disable receives while setting up the descriptors */
2164         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2165         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2166
2167         /*
2168          * Setup the HW Rx Head and Tail Descriptor Pointers and
2169          * the Base and Length of the Rx Descriptor Ring
2170          */
2171         for (i = 0; i < adapter->num_rx_queues; i++) {
2172                 rx_ring = &adapter->rx_ring[i];
2173                 rdba = rx_ring->dma;
2174                 j = rx_ring->reg_idx;
2175                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2176                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2177                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2178                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2179                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2180                 rx_ring->head = IXGBE_RDH(j);
2181                 rx_ring->tail = IXGBE_RDT(j);
2182                 rx_ring->rx_buf_len = rx_buf_len;
2183
2184                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2185                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2186                 else
2187                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2188
2189 #ifdef IXGBE_FCOE
2190                 if (netdev->features & NETIF_F_FCOE_MTU) {
2191                         struct ixgbe_ring_feature *f;
2192                         f = &adapter->ring_feature[RING_F_FCOE];
2193                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2194                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2195                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2196                                         rx_ring->rx_buf_len =
2197                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2198                         }
2199                 }
2200
2201 #endif /* IXGBE_FCOE */
2202                 ixgbe_configure_srrctl(adapter, rx_ring);
2203         }
2204
2205         if (hw->mac.type == ixgbe_mac_82598EB) {
2206                 /*
2207                  * For VMDq support of different descriptor types or
2208                  * buffer sizes through the use of multiple SRRCTL
2209                  * registers, RDRXCTL.MVMEN must be set to 1
2210                  *
2211                  * also, the manual doesn't mention it clearly but DCA hints
2212                  * will only use queue 0's tags unless this bit is set.  Side
2213                  * effects of setting this bit are only that SRRCTL must be
2214                  * fully programmed [0..15]
2215                  */
2216                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2217                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2218                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2219         }
2220
2221         /* Program MRQC for the distribution of queues */
2222         mrqc = ixgbe_setup_mrqc(adapter);
2223
2224         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2225                 /* Fill out redirection table */
2226                 for (i = 0, j = 0; i < 128; i++, j++) {
2227                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2228                                 j = 0;
2229                         /* reta = 4-byte sliding window of
2230                          * 0x00..(indices-1)(indices-1)00..etc. */
2231                         reta = (reta << 8) | (j * 0x11);
2232                         if ((i & 3) == 3)
2233                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2234                 }
2235
2236                 /* Fill out hash function seeds */
2237                 for (i = 0; i < 10; i++)
2238                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2239
2240                 if (hw->mac.type == ixgbe_mac_82598EB)
2241                         mrqc |= IXGBE_MRQC_RSSEN;
2242                     /* Perform hash on these packet types */
2243                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2244                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2245                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2246                       | IXGBE_MRQC_RSS_FIELD_IPV6
2247                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2248                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2249         }
2250         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2251
2252         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2253
2254         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2255             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2256                 /* Disable indicating checksum in descriptor, enables
2257                  * RSS hash */
2258                 rxcsum |= IXGBE_RXCSUM_PCSD;
2259         }
2260         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2261                 /* Enable IPv4 payload checksum for UDP fragments
2262                  * if PCSD is not set */
2263                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2264         }
2265
2266         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2267
2268         if (hw->mac.type == ixgbe_mac_82599EB) {
2269                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2270                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2271                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2272                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2273         }
2274
2275         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2276                 /* Enable 82599 HW-RSC */
2277                 for (i = 0; i < adapter->num_rx_queues; i++)
2278                         ixgbe_configure_rscctl(adapter, i, rx_buf_len);
2279
2280                 /* Disable RSC for ACK packets */
2281                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2282                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2283         }
2284 }
2285
2286 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2287 {
2288         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2289         struct ixgbe_hw *hw = &adapter->hw;
2290
2291         /* add VID to filter table */
2292         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2293 }
2294
2295 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2296 {
2297         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2298         struct ixgbe_hw *hw = &adapter->hw;
2299
2300         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2301                 ixgbe_irq_disable(adapter);
2302
2303         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2304
2305         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2306                 ixgbe_irq_enable(adapter);
2307
2308         /* remove VID from filter table */
2309         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2310 }
2311
2312 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2313                                    struct vlan_group *grp)
2314 {
2315         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2316         u32 ctrl;
2317         int i, j;
2318
2319         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2320                 ixgbe_irq_disable(adapter);
2321         adapter->vlgrp = grp;
2322
2323         /*
2324          * For a DCB driver, always enable VLAN tag stripping so we can
2325          * still receive traffic from a DCB-enabled host even if we're
2326          * not in DCB mode.
2327          */
2328         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2329         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2330                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2331                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2332                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2333         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2334                 ctrl |= IXGBE_VLNCTRL_VFE;
2335                 /* enable VLAN tag insert/strip */
2336                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2337                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2338                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2339                 for (i = 0; i < adapter->num_rx_queues; i++) {
2340                         j = adapter->rx_ring[i].reg_idx;
2341                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2342                         ctrl |= IXGBE_RXDCTL_VME;
2343                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2344                 }
2345         }
2346         ixgbe_vlan_rx_add_vid(netdev, 0);
2347
2348         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2349                 ixgbe_irq_enable(adapter);
2350 }
2351
2352 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2353 {
2354         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2355
2356         if (adapter->vlgrp) {
2357                 u16 vid;
2358                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2359                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2360                                 continue;
2361                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2362                 }
2363         }
2364 }
2365
2366 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2367 {
2368         struct dev_mc_list *mc_ptr;
2369         u8 *addr = *mc_addr_ptr;
2370         *vmdq = 0;
2371
2372         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2373         if (mc_ptr->next)
2374                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2375         else
2376                 *mc_addr_ptr = NULL;
2377
2378         return addr;
2379 }
2380
2381 /**
2382  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2383  * @netdev: network interface device structure
2384  *
2385  * The set_rx_method entry point is called whenever the unicast/multicast
2386  * address list or the network interface flags are updated.  This routine is
2387  * responsible for configuring the hardware for proper unicast, multicast and
2388  * promiscuous mode.
2389  **/
2390 static void ixgbe_set_rx_mode(struct net_device *netdev)
2391 {
2392         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2393         struct ixgbe_hw *hw = &adapter->hw;
2394         u32 fctrl, vlnctrl;
2395         u8 *addr_list = NULL;
2396         int addr_count = 0;
2397
2398         /* Check for Promiscuous and All Multicast modes */
2399
2400         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2401         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2402
2403         if (netdev->flags & IFF_PROMISC) {
2404                 hw->addr_ctrl.user_set_promisc = 1;
2405                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2406                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2407         } else {
2408                 if (netdev->flags & IFF_ALLMULTI) {
2409                         fctrl |= IXGBE_FCTRL_MPE;
2410                         fctrl &= ~IXGBE_FCTRL_UPE;
2411                 } else {
2412                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2413                 }
2414                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2415                 hw->addr_ctrl.user_set_promisc = 0;
2416         }
2417
2418         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2419         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2420
2421         /* reprogram secondary unicast list */
2422         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2423
2424         /* reprogram multicast list */
2425         addr_count = netdev->mc_count;
2426         if (addr_count)
2427                 addr_list = netdev->mc_list->dmi_addr;
2428         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2429                                         ixgbe_addr_list_itr);
2430 }
2431
2432 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2433 {
2434         int q_idx;
2435         struct ixgbe_q_vector *q_vector;
2436         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2437
2438         /* legacy and MSI only use one vector */
2439         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2440                 q_vectors = 1;
2441
2442         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2443                 struct napi_struct *napi;
2444                 q_vector = adapter->q_vector[q_idx];
2445                 napi = &q_vector->napi;
2446                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2447                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2448                                 if (q_vector->txr_count == 1)
2449                                         napi->poll = &ixgbe_clean_txonly;
2450                                 else if (q_vector->rxr_count == 1)
2451                                         napi->poll = &ixgbe_clean_rxonly;
2452                         }
2453                 }
2454
2455                 napi_enable(napi);
2456         }
2457 }
2458
2459 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2460 {
2461         int q_idx;
2462         struct ixgbe_q_vector *q_vector;
2463         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2464
2465         /* legacy and MSI only use one vector */
2466         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2467                 q_vectors = 1;
2468
2469         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2470                 q_vector = adapter->q_vector[q_idx];
2471                 napi_disable(&q_vector->napi);
2472         }
2473 }
2474
2475 #ifdef CONFIG_IXGBE_DCB
2476 /*
2477  * ixgbe_configure_dcb - Configure DCB hardware
2478  * @adapter: ixgbe adapter struct
2479  *
2480  * This is called by the driver on open to configure the DCB hardware.
2481  * This is also called by the gennetlink interface when reconfiguring
2482  * the DCB state.
2483  */
2484 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2485 {
2486         struct ixgbe_hw *hw = &adapter->hw;
2487         u32 txdctl, vlnctrl;
2488         int i, j;
2489
2490         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2491         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2492         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2493
2494         /* reconfigure the hardware */
2495         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2496
2497         for (i = 0; i < adapter->num_tx_queues; i++) {
2498                 j = adapter->tx_ring[i].reg_idx;
2499                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2500                 /* PThresh workaround for Tx hang with DFP enabled. */
2501                 txdctl |= 32;
2502                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2503         }
2504         /* Enable VLAN tag insert/strip */
2505         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2506         if (hw->mac.type == ixgbe_mac_82598EB) {
2507                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2508                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2509                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2510         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2511                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2512                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2513                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2514                 for (i = 0; i < adapter->num_rx_queues; i++) {
2515                         j = adapter->rx_ring[i].reg_idx;
2516                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2517                         vlnctrl |= IXGBE_RXDCTL_VME;
2518                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2519                 }
2520         }
2521         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2522 }
2523
2524 #endif
2525 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2526 {
2527         struct net_device *netdev = adapter->netdev;
2528         struct ixgbe_hw *hw = &adapter->hw;
2529         int i;
2530
2531         ixgbe_set_rx_mode(netdev);
2532
2533         ixgbe_restore_vlan(adapter);
2534 #ifdef CONFIG_IXGBE_DCB
2535         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2536                 if (hw->mac.type == ixgbe_mac_82598EB)
2537                         netif_set_gso_max_size(netdev, 32768);
2538                 else
2539                         netif_set_gso_max_size(netdev, 65536);
2540                 ixgbe_configure_dcb(adapter);
2541         } else {
2542                 netif_set_gso_max_size(netdev, 65536);
2543         }
2544 #else
2545         netif_set_gso_max_size(netdev, 65536);
2546 #endif
2547
2548 #ifdef IXGBE_FCOE
2549         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2550                 ixgbe_configure_fcoe(adapter);
2551
2552 #endif /* IXGBE_FCOE */
2553         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2554                 for (i = 0; i < adapter->num_tx_queues; i++)
2555                         adapter->tx_ring[i].atr_sample_rate =
2556                                                        adapter->atr_sample_rate;
2557                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2558         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2559                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2560         }
2561
2562         ixgbe_configure_tx(adapter);
2563         ixgbe_configure_rx(adapter);
2564         for (i = 0; i < adapter->num_rx_queues; i++)
2565                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2566                                        (adapter->rx_ring[i].count - 1));
2567 }
2568
2569 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2570 {
2571         switch (hw->phy.type) {
2572         case ixgbe_phy_sfp_avago:
2573         case ixgbe_phy_sfp_ftl:
2574         case ixgbe_phy_sfp_intel:
2575         case ixgbe_phy_sfp_unknown:
2576         case ixgbe_phy_tw_tyco:
2577         case ixgbe_phy_tw_unknown:
2578                 return true;
2579         default:
2580                 return false;
2581         }
2582 }
2583
2584 /**
2585  * ixgbe_sfp_link_config - set up SFP+ link
2586  * @adapter: pointer to private adapter struct
2587  **/
2588 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2589 {
2590         struct ixgbe_hw *hw = &adapter->hw;
2591
2592                 if (hw->phy.multispeed_fiber) {
2593                         /*
2594                          * In multispeed fiber setups, the device may not have
2595                          * had a physical connection when the driver loaded.
2596                          * If that's the case, the initial link configuration
2597                          * couldn't get the MAC into 10G or 1G mode, so we'll
2598                          * never have a link status change interrupt fire.
2599                          * We need to try and force an autonegotiation
2600                          * session, then bring up link.
2601                          */
2602                         hw->mac.ops.setup_sfp(hw);
2603                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2604                                 schedule_work(&adapter->multispeed_fiber_task);
2605                 } else {
2606                         /*
2607                          * Direct Attach Cu and non-multispeed fiber modules
2608                          * still need to be configured properly prior to
2609                          * attempting link.
2610                          */
2611                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2612                                 schedule_work(&adapter->sfp_config_module_task);
2613                 }
2614 }
2615
2616 /**
2617  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2618  * @hw: pointer to private hardware struct
2619  *
2620  * Returns 0 on success, negative on failure
2621  **/
2622 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2623 {
2624         u32 autoneg;
2625         bool negotiation, link_up = false;
2626         u32 ret = IXGBE_ERR_LINK_SETUP;
2627
2628         if (hw->mac.ops.check_link)
2629                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2630
2631         if (ret)
2632                 goto link_cfg_out;
2633
2634         if (hw->mac.ops.get_link_capabilities)
2635                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2636         if (ret)
2637                 goto link_cfg_out;
2638
2639         if (hw->mac.ops.setup_link)
2640                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2641 link_cfg_out:
2642         return ret;
2643 }
2644
2645 #define IXGBE_MAX_RX_DESC_POLL 10
2646 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2647                                               int rxr)
2648 {
2649         int j = adapter->rx_ring[rxr].reg_idx;
2650         int k;
2651
2652         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2653                 if (IXGBE_READ_REG(&adapter->hw,
2654                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2655                         break;
2656                 else
2657                         msleep(1);
2658         }
2659         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2660                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2661                         "not set within the polling period\n", rxr);
2662         }
2663         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2664                               (adapter->rx_ring[rxr].count - 1));
2665 }
2666
2667 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2668 {
2669         struct net_device *netdev = adapter->netdev;
2670         struct ixgbe_hw *hw = &adapter->hw;
2671         int i, j = 0;
2672         int num_rx_rings = adapter->num_rx_queues;
2673         int err;
2674         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2675         u32 txdctl, rxdctl, mhadd;
2676         u32 dmatxctl;
2677         u32 gpie;
2678
2679         ixgbe_get_hw_control(adapter);
2680
2681         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2682             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2683                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2684                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2685                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2686                 } else {
2687                         /* MSI only */
2688                         gpie = 0;
2689                 }
2690                 /* XXX: to interrupt immediately for EICS writes, enable this */
2691                 /* gpie |= IXGBE_GPIE_EIMEN; */
2692                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2693         }
2694
2695         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2696                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2697                  * specifically only auto mask tx and rx interrupts */
2698                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2699         }
2700
2701         /* Enable fan failure interrupt if media type is copper */
2702         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2703                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2704                 gpie |= IXGBE_SDP1_GPIEN;
2705                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2706         }
2707
2708         if (hw->mac.type == ixgbe_mac_82599EB) {
2709                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2710                 gpie |= IXGBE_SDP1_GPIEN;
2711                 gpie |= IXGBE_SDP2_GPIEN;
2712                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2713         }
2714
2715 #ifdef IXGBE_FCOE
2716         /* adjust max frame to be able to do baby jumbo for FCoE */
2717         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2718             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2719                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2720
2721 #endif /* IXGBE_FCOE */
2722         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2723         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2724                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2725                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2726
2727                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2728         }
2729
2730         for (i = 0; i < adapter->num_tx_queues; i++) {
2731                 j = adapter->tx_ring[i].reg_idx;
2732                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2733                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2734                 txdctl |= (8 << 16);
2735                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2736         }
2737
2738         if (hw->mac.type == ixgbe_mac_82599EB) {
2739                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2740                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2741                 dmatxctl |= IXGBE_DMATXCTL_TE;
2742                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2743         }
2744         for (i = 0; i < adapter->num_tx_queues; i++) {
2745                 j = adapter->tx_ring[i].reg_idx;
2746                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2747                 txdctl |= IXGBE_TXDCTL_ENABLE;
2748                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2749         }
2750
2751         for (i = 0; i < num_rx_rings; i++) {
2752                 j = adapter->rx_ring[i].reg_idx;
2753                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2754                 /* enable PTHRESH=32 descriptors (half the internal cache)
2755                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2756                  * this also removes a pesky rx_no_buffer_count increment */
2757                 rxdctl |= 0x0020;
2758                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2759                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2760                 if (hw->mac.type == ixgbe_mac_82599EB)
2761                         ixgbe_rx_desc_queue_enable(adapter, i);
2762         }
2763         /* enable all receives */
2764         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2765         if (hw->mac.type == ixgbe_mac_82598EB)
2766                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2767         else
2768                 rxdctl |= IXGBE_RXCTRL_RXEN;
2769         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2770
2771         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2772                 ixgbe_configure_msix(adapter);
2773         else
2774                 ixgbe_configure_msi_and_legacy(adapter);
2775
2776         clear_bit(__IXGBE_DOWN, &adapter->state);
2777         ixgbe_napi_enable_all(adapter);
2778
2779         /* clear any pending interrupts, may auto mask */
2780         IXGBE_READ_REG(hw, IXGBE_EICR);
2781
2782         ixgbe_irq_enable(adapter);
2783
2784         /*
2785          * If this adapter has a fan, check to see if we had a failure
2786          * before we enabled the interrupt.
2787          */
2788         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2789                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2790                 if (esdp & IXGBE_ESDP_SDP1)
2791                         DPRINTK(DRV, CRIT,
2792                                 "Fan has stopped, replace the adapter\n");
2793         }
2794
2795         /*
2796          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2797          * arrived before interrupts were enabled but after probe.  Such
2798          * devices wouldn't have their type identified yet. We need to
2799          * kick off the SFP+ module setup first, then try to bring up link.
2800          * If we're not hot-pluggable SFP+, we just need to configure link
2801          * and bring it up.
2802          */
2803         if (hw->phy.type == ixgbe_phy_unknown) {
2804                 err = hw->phy.ops.identify(hw);
2805                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2806                         /*
2807                          * Take the device down and schedule the sfp tasklet
2808                          * which will unregister_netdev and log it.
2809                          */
2810                         ixgbe_down(adapter);
2811                         schedule_work(&adapter->sfp_config_module_task);
2812                         return err;
2813                 }
2814         }
2815
2816         if (ixgbe_is_sfp(hw)) {
2817                 ixgbe_sfp_link_config(adapter);
2818         } else {
2819                 err = ixgbe_non_sfp_link_config(hw);
2820                 if (err)
2821                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2822         }
2823
2824         for (i = 0; i < adapter->num_tx_queues; i++)
2825                 set_bit(__IXGBE_FDIR_INIT_DONE,
2826                         &(adapter->tx_ring[i].reinit_state));
2827
2828         /* enable transmits */
2829         netif_tx_start_all_queues(netdev);
2830
2831         /* bring the link up in the watchdog, this could race with our first
2832          * link up interrupt but shouldn't be a problem */
2833         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2834         adapter->link_check_timeout = jiffies;
2835         mod_timer(&adapter->watchdog_timer, jiffies);
2836         return 0;
2837 }
2838
2839 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2840 {
2841         WARN_ON(in_interrupt());
2842         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2843                 msleep(1);
2844         ixgbe_down(adapter);
2845         ixgbe_up(adapter);
2846         clear_bit(__IXGBE_RESETTING, &adapter->state);
2847 }
2848
2849 int ixgbe_up(struct ixgbe_adapter *adapter)
2850 {
2851         /* hardware has been reset, we need to reload some things */
2852         ixgbe_configure(adapter);
2853
2854         return ixgbe_up_complete(adapter);
2855 }
2856
2857 void ixgbe_reset(struct ixgbe_adapter *adapter)
2858 {
2859         struct ixgbe_hw *hw = &adapter->hw;
2860         int err;
2861
2862         err = hw->mac.ops.init_hw(hw);
2863         switch (err) {
2864         case 0:
2865         case IXGBE_ERR_SFP_NOT_PRESENT:
2866                 break;
2867         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2868                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2869                 break;
2870         case IXGBE_ERR_EEPROM_VERSION:
2871                 /* We are running on a pre-production device, log a warning */
2872                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2873                          "adapter/LOM.  Please be aware there may be issues "
2874                          "associated with your hardware.  If you are "
2875                          "experiencing problems please contact your Intel or "
2876                          "hardware representative who provided you with this "
2877                          "hardware.\n");
2878                 break;
2879         default:
2880                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2881         }
2882
2883         /* reprogram the RAR[0] in case user changed it. */
2884         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2885 }
2886
2887 /**
2888  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2889  * @adapter: board private structure
2890  * @rx_ring: ring to free buffers from
2891  **/
2892 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2893                                 struct ixgbe_ring *rx_ring)
2894 {
2895         struct pci_dev *pdev = adapter->pdev;
2896         unsigned long size;
2897         unsigned int i;
2898
2899         /* Free all the Rx ring sk_buffs */
2900
2901         for (i = 0; i < rx_ring->count; i++) {
2902                 struct ixgbe_rx_buffer *rx_buffer_info;
2903
2904                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2905                 if (rx_buffer_info->dma) {
2906                         pci_unmap_single(pdev, rx_buffer_info->dma,
2907                                          rx_ring->rx_buf_len,
2908                                          PCI_DMA_FROMDEVICE);
2909                         rx_buffer_info->dma = 0;
2910                 }
2911                 if (rx_buffer_info->skb) {
2912                         struct sk_buff *skb = rx_buffer_info->skb;
2913                         rx_buffer_info->skb = NULL;
2914                         do {
2915                                 struct sk_buff *this = skb;
2916                                 skb = skb->prev;
2917                                 dev_kfree_skb(this);
2918                         } while (skb);
2919                 }
2920                 if (!rx_buffer_info->page)
2921                         continue;
2922                 if (rx_buffer_info->page_dma) {
2923                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2924                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2925                         rx_buffer_info->page_dma = 0;
2926                 }
2927                 put_page(rx_buffer_info->page);
2928                 rx_buffer_info->page = NULL;
2929                 rx_buffer_info->page_offset = 0;
2930         }
2931
2932         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2933         memset(rx_ring->rx_buffer_info, 0, size);
2934
2935         /* Zero out the descriptor ring */
2936         memset(rx_ring->desc, 0, rx_ring->size);
2937
2938         rx_ring->next_to_clean = 0;
2939         rx_ring->next_to_use = 0;
2940
2941         if (rx_ring->head)
2942                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2943         if (rx_ring->tail)
2944                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2945 }
2946
2947 /**
2948  * ixgbe_clean_tx_ring - Free Tx Buffers
2949  * @adapter: board private structure
2950  * @tx_ring: ring to be cleaned
2951  **/
2952 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2953                                 struct ixgbe_ring *tx_ring)
2954 {
2955         struct ixgbe_tx_buffer *tx_buffer_info;
2956         unsigned long size;
2957         unsigned int i;
2958
2959         /* Free all the Tx ring sk_buffs */
2960
2961         for (i = 0; i < tx_ring->count; i++) {
2962                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2963                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2964         }
2965
2966         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2967         memset(tx_ring->tx_buffer_info, 0, size);
2968
2969         /* Zero out the descriptor ring */
2970         memset(tx_ring->desc, 0, tx_ring->size);
2971
2972         tx_ring->next_to_use = 0;
2973         tx_ring->next_to_clean = 0;
2974
2975         if (tx_ring->head)
2976                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2977         if (tx_ring->tail)
2978                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2979 }
2980
2981 /**
2982  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2983  * @adapter: board private structure
2984  **/
2985 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2986 {
2987         int i;
2988
2989         for (i = 0; i < adapter->num_rx_queues; i++)
2990                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2991 }
2992
2993 /**
2994  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2995  * @adapter: board private structure
2996  **/
2997 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2998 {
2999         int i;
3000
3001         for (i = 0; i < adapter->num_tx_queues; i++)
3002                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
3003 }
3004
3005 void ixgbe_down(struct ixgbe_adapter *adapter)
3006 {
3007         struct net_device *netdev = adapter->netdev;
3008         struct ixgbe_hw *hw = &adapter->hw;
3009         u32 rxctrl;
3010         u32 txdctl;
3011         int i, j;
3012
3013         /* signal that we are down to the interrupt handler */
3014         set_bit(__IXGBE_DOWN, &adapter->state);
3015
3016         /* disable receives */
3017         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3018         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3019
3020         netif_tx_disable(netdev);
3021
3022         IXGBE_WRITE_FLUSH(hw);
3023         msleep(10);
3024
3025         netif_tx_stop_all_queues(netdev);
3026
3027         ixgbe_irq_disable(adapter);
3028
3029         ixgbe_napi_disable_all(adapter);
3030
3031         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3032         del_timer_sync(&adapter->sfp_timer);
3033         del_timer_sync(&adapter->watchdog_timer);
3034         cancel_work_sync(&adapter->watchdog_task);
3035
3036         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3037             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3038                 cancel_work_sync(&adapter->fdir_reinit_task);
3039
3040         /* disable transmits in the hardware now that interrupts are off */
3041         for (i = 0; i < adapter->num_tx_queues; i++) {
3042                 j = adapter->tx_ring[i].reg_idx;
3043                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3044                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3045                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3046         }
3047         /* Disable the Tx DMA engine on 82599 */
3048         if (hw->mac.type == ixgbe_mac_82599EB)
3049                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3050                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3051                                  ~IXGBE_DMATXCTL_TE));
3052
3053         netif_carrier_off(netdev);
3054
3055         if (!pci_channel_offline(adapter->pdev))
3056                 ixgbe_reset(adapter);
3057         ixgbe_clean_all_tx_rings(adapter);
3058         ixgbe_clean_all_rx_rings(adapter);
3059
3060 #ifdef CONFIG_IXGBE_DCA
3061         /* since we reset the hardware DCA settings were cleared */
3062         ixgbe_setup_dca(adapter);
3063 #endif
3064 }
3065
3066 /**
3067  * ixgbe_poll - NAPI Rx polling callback
3068  * @napi: structure for representing this polling device
3069  * @budget: how many packets driver is allowed to clean
3070  *
3071  * This function is used for legacy and MSI, NAPI mode
3072  **/
3073 static int ixgbe_poll(struct napi_struct *napi, int budget)
3074 {
3075         struct ixgbe_q_vector *q_vector =
3076                                 container_of(napi, struct ixgbe_q_vector, napi);
3077         struct ixgbe_adapter *adapter = q_vector->adapter;
3078         int tx_clean_complete, work_done = 0;
3079
3080 #ifdef CONFIG_IXGBE_DCA
3081         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3082                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3083                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3084         }
3085 #endif
3086
3087         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3088         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3089
3090         if (!tx_clean_complete)
3091                 work_done = budget;
3092
3093         /* If budget not fully consumed, exit the polling mode */
3094         if (work_done < budget) {
3095                 napi_complete(napi);
3096                 if (adapter->rx_itr_setting & 1)
3097                         ixgbe_set_itr(adapter);
3098                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3099                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3100         }
3101         return work_done;
3102 }
3103
3104 /**
3105  * ixgbe_tx_timeout - Respond to a Tx Hang
3106  * @netdev: network interface device structure
3107  **/
3108 static void ixgbe_tx_timeout(struct net_device *netdev)
3109 {
3110         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3111
3112         /* Do the reset outside of interrupt context */
3113         schedule_work(&adapter->reset_task);
3114 }
3115
3116 static void ixgbe_reset_task(struct work_struct *work)
3117 {
3118         struct ixgbe_adapter *adapter;
3119         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3120
3121         /* If we're already down or resetting, just bail */
3122         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3123             test_bit(__IXGBE_RESETTING, &adapter->state))
3124                 return;
3125
3126         adapter->tx_timeout_count++;
3127
3128         ixgbe_reinit_locked(adapter);
3129 }
3130
3131 #ifdef CONFIG_IXGBE_DCB
3132 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3133 {
3134         bool ret = false;
3135         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3136
3137         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3138                 return ret;
3139
3140         f->mask = 0x7 << 3;
3141         adapter->num_rx_queues = f->indices;
3142         adapter->num_tx_queues = f->indices;
3143         ret = true;
3144
3145         return ret;
3146 }
3147 #endif
3148
3149 /**
3150  * ixgbe_set_rss_queues: Allocate queues for RSS
3151  * @adapter: board private structure to initialize
3152  *
3153  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3154  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3155  *
3156  **/
3157 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3158 {
3159         bool ret = false;
3160         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3161
3162         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3163                 f->mask = 0xF;
3164                 adapter->num_rx_queues = f->indices;
3165                 adapter->num_tx_queues = f->indices;
3166                 ret = true;
3167         } else {
3168                 ret = false;
3169         }
3170
3171         return ret;
3172 }
3173
3174 /**
3175  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3176  * @adapter: board private structure to initialize
3177  *
3178  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3179  * to the original CPU that initiated the Tx session.  This runs in addition
3180  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3181  * Rx load across CPUs using RSS.
3182  *
3183  **/
3184 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3185 {
3186         bool ret = false;
3187         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3188
3189         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3190         f_fdir->mask = 0;
3191
3192         /* Flow Director must have RSS enabled */
3193         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3194             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3195              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3196                 adapter->num_tx_queues = f_fdir->indices;
3197                 adapter->num_rx_queues = f_fdir->indices;
3198                 ret = true;
3199         } else {
3200                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3201                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3202         }
3203         return ret;
3204 }
3205
3206 #ifdef IXGBE_FCOE
3207 /**
3208  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3209  * @adapter: board private structure to initialize
3210  *
3211  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3212  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3213  * rx queues out of the max number of rx queues, instead, it is used as the
3214  * index of the first rx queue used by FCoE.
3215  *
3216  **/
3217 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3218 {
3219         bool ret = false;
3220         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3221
3222         f->indices = min((int)num_online_cpus(), f->indices);
3223         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3224                 adapter->num_rx_queues = 1;
3225                 adapter->num_tx_queues = 1;
3226 #ifdef CONFIG_IXGBE_DCB
3227                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3228                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3229                         ixgbe_set_dcb_queues(adapter);
3230                 }
3231 #endif
3232                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3233                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3234                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3235                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3236                                 ixgbe_set_fdir_queues(adapter);
3237                         else
3238                                 ixgbe_set_rss_queues(adapter);
3239                 }
3240                 /* adding FCoE rx rings to the end */
3241                 f->mask = adapter->num_rx_queues;
3242                 adapter->num_rx_queues += f->indices;
3243                 adapter->num_tx_queues += f->indices;
3244
3245                 ret = true;
3246         }
3247
3248         return ret;
3249 }
3250
3251 #endif /* IXGBE_FCOE */
3252 /*
3253  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3254  * @adapter: board private structure to initialize
3255  *
3256  * This is the top level queue allocation routine.  The order here is very
3257  * important, starting with the "most" number of features turned on at once,
3258  * and ending with the smallest set of features.  This way large combinations
3259  * can be allocated if they're turned on, and smaller combinations are the
3260  * fallthrough conditions.
3261  *
3262  **/
3263 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3264 {
3265 #ifdef IXGBE_FCOE
3266         if (ixgbe_set_fcoe_queues(adapter))
3267                 goto done;
3268
3269 #endif /* IXGBE_FCOE */
3270 #ifdef CONFIG_IXGBE_DCB
3271         if (ixgbe_set_dcb_queues(adapter))
3272                 goto done;
3273
3274 #endif
3275         if (ixgbe_set_fdir_queues(adapter))
3276                 goto done;
3277
3278         if (ixgbe_set_rss_queues(adapter))
3279                 goto done;
3280
3281         /* fallback to base case */
3282         adapter->num_rx_queues = 1;
3283         adapter->num_tx_queues = 1;
3284
3285 done:
3286         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3287         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3288 }
3289
3290 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3291                                        int vectors)
3292 {
3293         int err, vector_threshold;
3294
3295         /* We'll want at least 3 (vector_threshold):
3296          * 1) TxQ[0] Cleanup
3297          * 2) RxQ[0] Cleanup
3298          * 3) Other (Link Status Change, etc.)
3299          * 4) TCP Timer (optional)
3300          */
3301         vector_threshold = MIN_MSIX_COUNT;
3302
3303         /* The more we get, the more we will assign to Tx/Rx Cleanup
3304          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3305          * Right now, we simply care about how many we'll get; we'll
3306          * set them up later while requesting irq's.
3307          */
3308         while (vectors >= vector_threshold) {
3309                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3310                                       vectors);
3311                 if (!err) /* Success in acquiring all requested vectors. */
3312                         break;
3313                 else if (err < 0)
3314                         vectors = 0; /* Nasty failure, quit now */
3315                 else /* err == number of vectors we should try again with */
3316                         vectors = err;
3317         }
3318
3319         if (vectors < vector_threshold) {
3320                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3321                  * This just means we'll go with either a single MSI
3322                  * vector or fall back to legacy interrupts.
3323                  */
3324                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3325                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3326                 kfree(adapter->msix_entries);
3327                 adapter->msix_entries = NULL;
3328         } else {
3329                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3330                 /*
3331                  * Adjust for only the vectors we'll use, which is minimum
3332                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3333                  * vectors we were allocated.
3334                  */
3335                 adapter->num_msix_vectors = min(vectors,
3336                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3337         }
3338 }
3339
3340 /**
3341  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3342  * @adapter: board private structure to initialize
3343  *
3344  * Cache the descriptor ring offsets for RSS to the assigned rings.
3345  *
3346  **/
3347 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3348 {
3349         int i;
3350         bool ret = false;
3351
3352         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3353                 for (i = 0; i < adapter->num_rx_queues; i++)
3354                         adapter->rx_ring[i].reg_idx = i;
3355                 for (i = 0; i < adapter->num_tx_queues; i++)
3356                         adapter->tx_ring[i].reg_idx = i;
3357                 ret = true;
3358         } else {
3359                 ret = false;
3360         }
3361
3362         return ret;
3363 }
3364
3365 #ifdef CONFIG_IXGBE_DCB
3366 /**
3367  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3368  * @adapter: board private structure to initialize
3369  *
3370  * Cache the descriptor ring offsets for DCB to the assigned rings.
3371  *
3372  **/
3373 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3374 {
3375         int i;
3376         bool ret = false;
3377         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3378
3379         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3380                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3381                         /* the number of queues is assumed to be symmetric */
3382                         for (i = 0; i < dcb_i; i++) {
3383                                 adapter->rx_ring[i].reg_idx = i << 3;
3384                                 adapter->tx_ring[i].reg_idx = i << 2;
3385                         }
3386                         ret = true;
3387                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3388                         if (dcb_i == 8) {
3389                                 /*
3390                                  * Tx TC0 starts at: descriptor queue 0
3391                                  * Tx TC1 starts at: descriptor queue 32
3392                                  * Tx TC2 starts at: descriptor queue 64
3393                                  * Tx TC3 starts at: descriptor queue 80
3394                                  * Tx TC4 starts at: descriptor queue 96
3395                                  * Tx TC5 starts at: descriptor queue 104
3396                                  * Tx TC6 starts at: descriptor queue 112
3397                                  * Tx TC7 starts at: descriptor queue 120
3398                                  *
3399                                  * Rx TC0-TC7 are offset by 16 queues each
3400                                  */
3401                                 for (i = 0; i < 3; i++) {
3402                                         adapter->tx_ring[i].reg_idx = i << 5;
3403                                         adapter->rx_ring[i].reg_idx = i << 4;
3404                                 }
3405                                 for ( ; i < 5; i++) {
3406                                         adapter->tx_ring[i].reg_idx =
3407                                                                  ((i + 2) << 4);
3408                                         adapter->rx_ring[i].reg_idx = i << 4;
3409                                 }
3410                                 for ( ; i < dcb_i; i++) {
3411                                         adapter->tx_ring[i].reg_idx =
3412                                                                  ((i + 8) << 3);
3413                                         adapter->rx_ring[i].reg_idx = i << 4;
3414                                 }
3415
3416                                 ret = true;
3417                         } else if (dcb_i == 4) {
3418                                 /*
3419                                  * Tx TC0 starts at: descriptor queue 0
3420                                  * Tx TC1 starts at: descriptor queue 64
3421                                  * Tx TC2 starts at: descriptor queue 96
3422                                  * Tx TC3 starts at: descriptor queue 112
3423                                  *
3424                                  * Rx TC0-TC3 are offset by 32 queues each
3425                                  */
3426                                 adapter->tx_ring[0].reg_idx = 0;
3427                                 adapter->tx_ring[1].reg_idx = 64;
3428                                 adapter->tx_ring[2].reg_idx = 96;
3429                                 adapter->tx_ring[3].reg_idx = 112;
3430                                 for (i = 0 ; i < dcb_i; i++)
3431                                         adapter->rx_ring[i].reg_idx = i << 5;
3432
3433                                 ret = true;
3434                         } else {
3435                                 ret = false;
3436                         }
3437                 } else {
3438                         ret = false;
3439                 }
3440         } else {
3441                 ret = false;
3442         }
3443
3444         return ret;
3445 }
3446 #endif
3447
3448 /**
3449  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3450  * @adapter: board private structure to initialize
3451  *
3452  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3453  *
3454  **/
3455 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3456 {
3457         int i;
3458         bool ret = false;
3459
3460         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3461             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3462              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3463                 for (i = 0; i < adapter->num_rx_queues; i++)
3464                         adapter->rx_ring[i].reg_idx = i;
3465                 for (i = 0; i < adapter->num_tx_queues; i++)
3466                         adapter->tx_ring[i].reg_idx = i;
3467                 ret = true;
3468         }
3469
3470         return ret;
3471 }
3472
3473 #ifdef IXGBE_FCOE
3474 /**
3475  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3476  * @adapter: board private structure to initialize
3477  *
3478  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3479  *
3480  */
3481 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3482 {
3483         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3484         bool ret = false;
3485         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3486
3487         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3488 #ifdef CONFIG_IXGBE_DCB
3489                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3490                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3491
3492                         ixgbe_cache_ring_dcb(adapter);
3493                         /* find out queues in TC for FCoE */
3494                         fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3495                         fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3496                         /*
3497                          * In 82599, the number of Tx queues for each traffic
3498                          * class for both 8-TC and 4-TC modes are:
3499                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3500                          * 8 TCs:  32  32  16  16   8   8   8   8
3501                          * 4 TCs:  64  64  32  32
3502                          * We have max 8 queues for FCoE, where 8 the is
3503                          * FCoE redirection table size. If TC for FCoE is
3504                          * less than or equal to TC3, we have enough queues
3505                          * to add max of 8 queues for FCoE, so we start FCoE
3506                          * tx descriptor from the next one, i.e., reg_idx + 1.
3507                          * If TC for FCoE is above TC3, implying 8 TC mode,
3508                          * and we need 8 for FCoE, we have to take all queues
3509                          * in that traffic class for FCoE.
3510                          */
3511                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3512                                 fcoe_tx_i--;
3513                 }
3514 #endif /* CONFIG_IXGBE_DCB */
3515                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3516                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3517                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3518                                 ixgbe_cache_ring_fdir(adapter);
3519                         else
3520                                 ixgbe_cache_ring_rss(adapter);
3521
3522                         fcoe_rx_i = f->mask;
3523                         fcoe_tx_i = f->mask;
3524                 }
3525                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3526                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3527                         adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3528                 }
3529                 ret = true;
3530         }
3531         return ret;
3532 }
3533
3534 #endif /* IXGBE_FCOE */
3535 /**
3536  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3537  * @adapter: board private structure to initialize
3538  *
3539  * Once we know the feature-set enabled for the device, we'll cache
3540  * the register offset the descriptor ring is assigned to.
3541  *
3542  * Note, the order the various feature calls is important.  It must start with
3543  * the "most" features enabled at the same time, then trickle down to the
3544  * least amount of features turned on at once.
3545  **/
3546 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3547 {
3548         /* start with default case */
3549         adapter->rx_ring[0].reg_idx = 0;
3550         adapter->tx_ring[0].reg_idx = 0;
3551
3552 #ifdef IXGBE_FCOE
3553         if (ixgbe_cache_ring_fcoe(adapter))
3554                 return;
3555
3556 #endif /* IXGBE_FCOE */
3557 #ifdef CONFIG_IXGBE_DCB
3558         if (ixgbe_cache_ring_dcb(adapter))
3559                 return;
3560
3561 #endif
3562         if (ixgbe_cache_ring_fdir(adapter))
3563                 return;
3564
3565         if (ixgbe_cache_ring_rss(adapter))
3566                 return;
3567 }
3568
3569 /**
3570  * ixgbe_alloc_queues - Allocate memory for all rings
3571  * @adapter: board private structure to initialize
3572  *
3573  * We allocate one ring per queue at run-time since we don't know the
3574  * number of queues at compile-time.  The polling_netdev array is
3575  * intended for Multiqueue, but should work fine with a single queue.
3576  **/
3577 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3578 {
3579         int i;
3580
3581         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3582                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3583         if (!adapter->tx_ring)
3584                 goto err_tx_ring_allocation;
3585
3586         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3587                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3588         if (!adapter->rx_ring)
3589                 goto err_rx_ring_allocation;
3590
3591         for (i = 0; i < adapter->num_tx_queues; i++) {
3592                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3593                 adapter->tx_ring[i].queue_index = i;
3594         }
3595
3596         for (i = 0; i < adapter->num_rx_queues; i++) {
3597                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3598                 adapter->rx_ring[i].queue_index = i;
3599         }
3600
3601         ixgbe_cache_ring_register(adapter);
3602
3603         return 0;
3604
3605 err_rx_ring_allocation:
3606         kfree(adapter->tx_ring);
3607 err_tx_ring_allocation:
3608         return -ENOMEM;
3609 }
3610
3611 /**
3612  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3613  * @adapter: board private structure to initialize
3614  *
3615  * Attempt to configure the interrupts using the best available
3616  * capabilities of the hardware and the kernel.
3617  **/
3618 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3619 {
3620         struct ixgbe_hw *hw = &adapter->hw;
3621         int err = 0;
3622         int vector, v_budget;
3623
3624         /*
3625          * It's easy to be greedy for MSI-X vectors, but it really
3626          * doesn't do us much good if we have a lot more vectors
3627          * than CPU's.  So let's be conservative and only ask for
3628          * (roughly) twice the number of vectors as there are CPU's.
3629          */
3630         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3631                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3632
3633         /*
3634          * At the same time, hardware can only support a maximum of
3635          * hw.mac->max_msix_vectors vectors.  With features
3636          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3637          * descriptor queues supported by our device.  Thus, we cap it off in
3638          * those rare cases where the cpu count also exceeds our vector limit.
3639          */
3640         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3641
3642         /* A failure in MSI-X entry allocation isn't fatal, but it does
3643          * mean we disable MSI-X capabilities of the adapter. */
3644         adapter->msix_entries = kcalloc(v_budget,
3645                                         sizeof(struct msix_entry), GFP_KERNEL);
3646         if (adapter->msix_entries) {
3647                 for (vector = 0; vector < v_budget; vector++)
3648                         adapter->msix_entries[vector].entry = vector;
3649
3650                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3651
3652                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3653                         goto out;
3654         }
3655
3656         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3657         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3658         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3659         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3660         adapter->atr_sample_rate = 0;
3661         ixgbe_set_num_queues(adapter);
3662
3663         err = pci_enable_msi(adapter->pdev);
3664         if (!err) {
3665                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3666         } else {
3667                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3668                         "falling back to legacy.  Error: %d\n", err);
3669                 /* reset err */
3670                 err = 0;
3671         }
3672
3673 out:
3674         return err;
3675 }
3676
3677 /**
3678  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3679  * @adapter: board private structure to initialize
3680  *
3681  * We allocate one q_vector per queue interrupt.  If allocation fails we
3682  * return -ENOMEM.
3683  **/
3684 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3685 {
3686         int q_idx, num_q_vectors;
3687         struct ixgbe_q_vector *q_vector;
3688         int napi_vectors;
3689         int (*poll)(struct napi_struct *, int);
3690
3691         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3692                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3693                 napi_vectors = adapter->num_rx_queues;
3694                 poll = &ixgbe_clean_rxtx_many;
3695         } else {
3696                 num_q_vectors = 1;
3697                 napi_vectors = 1;
3698                 poll = &ixgbe_poll;
3699         }
3700
3701         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3702                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3703                 if (!q_vector)
3704                         goto err_out;
3705                 q_vector->adapter = adapter;
3706                 if (q_vector->txr_count && !q_vector->rxr_count)
3707                         q_vector->eitr = adapter->tx_eitr_param;
3708                 else
3709                         q_vector->eitr = adapter->rx_eitr_param;
3710                 q_vector->v_idx = q_idx;
3711                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3712                 adapter->q_vector[q_idx] = q_vector;
3713         }
3714
3715         return 0;
3716
3717 err_out:
3718         while (q_idx) {
3719                 q_idx--;
3720                 q_vector = adapter->q_vector[q_idx];
3721                 netif_napi_del(&q_vector->napi);
3722                 kfree(q_vector);
3723                 adapter->q_vector[q_idx] = NULL;
3724         }
3725         return -ENOMEM;
3726 }
3727
3728 /**
3729  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3730  * @adapter: board private structure to initialize
3731  *
3732  * This function frees the memory allocated to the q_vectors.  In addition if
3733  * NAPI is enabled it will delete any references to the NAPI struct prior
3734  * to freeing the q_vector.
3735  **/
3736 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3737 {
3738         int q_idx, num_q_vectors;
3739
3740         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3741                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3742         else
3743                 num_q_vectors = 1;
3744
3745         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3746                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3747                 adapter->q_vector[q_idx] = NULL;
3748                 netif_napi_del(&q_vector->napi);
3749                 kfree(q_vector);
3750         }
3751 }
3752
3753 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3754 {
3755         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3756                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3757                 pci_disable_msix(adapter->pdev);
3758                 kfree(adapter->msix_entries);
3759                 adapter->msix_entries = NULL;
3760         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3761                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3762                 pci_disable_msi(adapter->pdev);
3763         }
3764         return;
3765 }
3766
3767 /**
3768  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3769  * @adapter: board private structure to initialize
3770  *
3771  * We determine which interrupt scheme to use based on...
3772  * - Kernel support (MSI, MSI-X)
3773  *   - which can be user-defined (via MODULE_PARAM)
3774  * - Hardware queue count (num_*_queues)
3775  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3776  **/
3777 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3778 {
3779         int err;
3780
3781         /* Number of supported queues */
3782         ixgbe_set_num_queues(adapter);
3783
3784         err = ixgbe_set_interrupt_capability(adapter);
3785         if (err) {
3786                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3787                 goto err_set_interrupt;
3788         }
3789
3790         err = ixgbe_alloc_q_vectors(adapter);
3791         if (err) {
3792                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3793                         "vectors\n");
3794                 goto err_alloc_q_vectors;
3795         }
3796
3797         err = ixgbe_alloc_queues(adapter);
3798         if (err) {
3799                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3800                 goto err_alloc_queues;
3801         }
3802
3803         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3804                 "Tx Queue count = %u\n",
3805                 (adapter->num_rx_queues > 1) ? "Enabled" :
3806                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3807
3808         set_bit(__IXGBE_DOWN, &adapter->state);
3809
3810         return 0;
3811
3812 err_alloc_queues:
3813         ixgbe_free_q_vectors(adapter);
3814 err_alloc_q_vectors:
3815         ixgbe_reset_interrupt_capability(adapter);
3816 err_set_interrupt:
3817         return err;
3818 }
3819
3820 /**
3821  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3822  * @adapter: board private structure to clear interrupt scheme on
3823  *
3824  * We go through and clear interrupt specific resources and reset the structure
3825  * to pre-load conditions
3826  **/
3827 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3828 {
3829         kfree(adapter->tx_ring);
3830         kfree(adapter->rx_ring);
3831         adapter->tx_ring = NULL;
3832         adapter->rx_ring = NULL;
3833
3834         ixgbe_free_q_vectors(adapter);
3835         ixgbe_reset_interrupt_capability(adapter);
3836 }
3837
3838 /**
3839  * ixgbe_sfp_timer - worker thread to find a missing module
3840  * @data: pointer to our adapter struct
3841  **/
3842 static void ixgbe_sfp_timer(unsigned long data)
3843 {
3844         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3845
3846         /*
3847          * Do the sfp_timer outside of interrupt context due to the
3848          * delays that sfp+ detection requires
3849          */
3850         schedule_work(&adapter->sfp_task);
3851 }
3852
3853 /**
3854  * ixgbe_sfp_task - worker thread to find a missing module
3855  * @work: pointer to work_struct containing our data
3856  **/
3857 static void ixgbe_sfp_task(struct work_struct *work)
3858 {
3859         struct ixgbe_adapter *adapter = container_of(work,
3860                                                      struct ixgbe_adapter,
3861                                                      sfp_task);
3862         struct ixgbe_hw *hw = &adapter->hw;
3863
3864         if ((hw->phy.type == ixgbe_phy_nl) &&
3865             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3866                 s32 ret = hw->phy.ops.identify_sfp(hw);
3867                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3868                         goto reschedule;
3869                 ret = hw->phy.ops.reset(hw);
3870                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3871                         dev_err(&adapter->pdev->dev, "failed to initialize "
3872                                 "because an unsupported SFP+ module type "
3873                                 "was detected.\n"
3874                                 "Reload the driver after installing a "
3875                                 "supported module.\n");
3876                         unregister_netdev(adapter->netdev);
3877                 } else {
3878                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3879                                 hw->phy.sfp_type);
3880                 }
3881                 /* don't need this routine any more */
3882                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3883         }
3884         return;
3885 reschedule:
3886         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3887                 mod_timer(&adapter->sfp_timer,
3888                           round_jiffies(jiffies + (2 * HZ)));
3889 }
3890
3891 /**
3892  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3893  * @adapter: board private structure to initialize
3894  *
3895  * ixgbe_sw_init initializes the Adapter private data structure.
3896  * Fields are initialized based on PCI device information and
3897  * OS network device settings (MTU size).
3898  **/
3899 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3900 {
3901         struct ixgbe_hw *hw = &adapter->hw;
3902         struct pci_dev *pdev = adapter->pdev;
3903         unsigned int rss;
3904 #ifdef CONFIG_IXGBE_DCB
3905         int j;
3906         struct tc_configuration *tc;
3907 #endif
3908
3909         /* PCI config space info */
3910
3911         hw->vendor_id = pdev->vendor;
3912         hw->device_id = pdev->device;
3913         hw->revision_id = pdev->revision;
3914         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3915         hw->subsystem_device_id = pdev->subsystem_device;
3916
3917         /* Set capability flags */
3918         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3919         adapter->ring_feature[RING_F_RSS].indices = rss;
3920         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3921         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3922         if (hw->mac.type == ixgbe_mac_82598EB) {
3923                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3924                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3925                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3926         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3927                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3928                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3929                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3930                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3931                 adapter->ring_feature[RING_F_FDIR].indices =
3932                                                          IXGBE_MAX_FDIR_INDICES;
3933                 adapter->atr_sample_rate = 20;
3934                 adapter->fdir_pballoc = 0;
3935 #ifdef IXGBE_FCOE
3936                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3937                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3938                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3939                 /* Default traffic class to use for FCoE */
3940                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3941 #endif /* IXGBE_FCOE */
3942         }
3943
3944 #ifdef CONFIG_IXGBE_DCB
3945         /* Configure DCB traffic classes */
3946         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3947                 tc = &adapter->dcb_cfg.tc_config[j];
3948                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3949                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3950                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3951                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3952                 tc->dcb_pfc = pfc_disabled;
3953         }
3954         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3955         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3956         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3957         adapter->dcb_cfg.pfc_mode_enable = false;
3958         adapter->dcb_cfg.round_robin_enable = false;
3959         adapter->dcb_set_bitmap = 0x00;
3960         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3961                            adapter->ring_feature[RING_F_DCB].indices);
3962
3963 #endif
3964
3965         /* default flow control settings */
3966         hw->fc.requested_mode = ixgbe_fc_full;
3967         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3968 #ifdef CONFIG_DCB
3969         adapter->last_lfc_mode = hw->fc.current_mode;
3970 #endif
3971         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3972         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3973         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3974         hw->fc.send_xon = true;
3975         hw->fc.disable_fc_autoneg = false;
3976
3977         /* enable itr by default in dynamic mode */
3978         adapter->rx_itr_setting = 1;
3979         adapter->rx_eitr_param = 20000;
3980         adapter->tx_itr_setting = 1;
3981         adapter->tx_eitr_param = 10000;
3982
3983         /* set defaults for eitr in MegaBytes */
3984         adapter->eitr_low = 10;
3985         adapter->eitr_high = 20;
3986
3987         /* set default ring sizes */
3988         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3989         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3990
3991         /* initialize eeprom parameters */
3992         if (ixgbe_init_eeprom_params_generic(hw)) {
3993                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3994                 return -EIO;
3995         }
3996
3997         /* enable rx csum by default */
3998         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3999
4000         set_bit(__IXGBE_DOWN, &adapter->state);
4001
4002         return 0;
4003 }
4004
4005 /**
4006  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4007  * @adapter: board private structure
4008  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4009  *
4010  * Return 0 on success, negative on failure
4011  **/
4012 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4013                              struct ixgbe_ring *tx_ring)
4014 {
4015         struct pci_dev *pdev = adapter->pdev;
4016         int size;
4017
4018         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4019         tx_ring->tx_buffer_info = vmalloc(size);
4020         if (!tx_ring->tx_buffer_info)
4021                 goto err;
4022         memset(tx_ring->tx_buffer_info, 0, size);
4023
4024         /* round up to nearest 4K */
4025         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4026         tx_ring->size = ALIGN(tx_ring->size, 4096);
4027
4028         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4029                                              &tx_ring->dma);
4030         if (!tx_ring->desc)
4031                 goto err;
4032
4033         tx_ring->next_to_use = 0;
4034         tx_ring->next_to_clean = 0;
4035         tx_ring->work_limit = tx_ring->count;
4036         return 0;
4037
4038 err:
4039         vfree(tx_ring->tx_buffer_info);
4040         tx_ring->tx_buffer_info = NULL;
4041         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4042                             "descriptor ring\n");
4043         return -ENOMEM;
4044 }
4045
4046 /**
4047  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4048  * @adapter: board private structure
4049  *
4050  * If this function returns with an error, then it's possible one or
4051  * more of the rings is populated (while the rest are not).  It is the
4052  * callers duty to clean those orphaned rings.
4053  *
4054  * Return 0 on success, negative on failure
4055  **/
4056 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4057 {
4058         int i, err = 0;
4059
4060         for (i = 0; i < adapter->num_tx_queues; i++) {
4061                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4062                 if (!err)
4063                         continue;
4064                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4065                 break;
4066         }
4067
4068         return err;
4069 }
4070
4071 /**
4072  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4073  * @adapter: board private structure
4074  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4075  *
4076  * Returns 0 on success, negative on failure
4077  **/
4078 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4079                              struct ixgbe_ring *rx_ring)
4080 {
4081         struct pci_dev *pdev = adapter->pdev;
4082         int size;
4083
4084         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4085         rx_ring->rx_buffer_info = vmalloc(size);
4086         if (!rx_ring->rx_buffer_info) {
4087                 DPRINTK(PROBE, ERR,
4088                         "vmalloc allocation failed for the rx desc ring\n");
4089                 goto alloc_failed;
4090         }
4091         memset(rx_ring->rx_buffer_info, 0, size);
4092
4093         /* Round up to nearest 4K */
4094         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4095         rx_ring->size = ALIGN(rx_ring->size, 4096);
4096
4097         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4098
4099         if (!rx_ring->desc) {
4100                 DPRINTK(PROBE, ERR,
4101                         "Memory allocation failed for the rx desc ring\n");
4102                 vfree(rx_ring->rx_buffer_info);
4103                 goto alloc_failed;
4104         }
4105
4106         rx_ring->next_to_clean = 0;
4107         rx_ring->next_to_use = 0;
4108
4109         return 0;
4110
4111 alloc_failed:
4112         return -ENOMEM;
4113 }
4114
4115 /**
4116  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4117  * @adapter: board private structure
4118  *
4119  * If this function returns with an error, then it's possible one or
4120  * more of the rings is populated (while the rest are not).  It is the
4121  * callers duty to clean those orphaned rings.
4122  *
4123  * Return 0 on success, negative on failure
4124  **/
4125
4126 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4127 {
4128         int i, err = 0;
4129
4130         for (i = 0; i < adapter->num_rx_queues; i++) {
4131                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4132                 if (!err)
4133                         continue;
4134                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4135                 break;
4136         }
4137
4138         return err;
4139 }
4140
4141 /**
4142  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4143  * @adapter: board private structure
4144  * @tx_ring: Tx descriptor ring for a specific queue
4145  *
4146  * Free all transmit software resources
4147  **/
4148 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4149                              struct ixgbe_ring *tx_ring)
4150 {
4151         struct pci_dev *pdev = adapter->pdev;
4152
4153         ixgbe_clean_tx_ring(adapter, tx_ring);
4154
4155         vfree(tx_ring->tx_buffer_info);
4156         tx_ring->tx_buffer_info = NULL;
4157
4158         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4159
4160         tx_ring->desc = NULL;
4161 }
4162
4163 /**
4164  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4165  * @adapter: board private structure
4166  *
4167  * Free all transmit software resources
4168  **/
4169 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4170 {
4171         int i;
4172
4173         for (i = 0; i < adapter->num_tx_queues; i++)
4174                 if (adapter->tx_ring[i].desc)
4175                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4176 }
4177
4178 /**
4179  * ixgbe_free_rx_resources - Free Rx Resources
4180  * @adapter: board private structure
4181  * @rx_ring: ring to clean the resources from
4182  *
4183  * Free all receive software resources
4184  **/
4185 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4186                              struct ixgbe_ring *rx_ring)
4187 {
4188         struct pci_dev *pdev = adapter->pdev;
4189
4190         ixgbe_clean_rx_ring(adapter, rx_ring);
4191
4192         vfree(rx_ring->rx_buffer_info);
4193         rx_ring->rx_buffer_info = NULL;
4194
4195         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4196
4197         rx_ring->desc = NULL;
4198 }
4199
4200 /**
4201  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4202  * @adapter: board private structure
4203  *
4204  * Free all receive software resources
4205  **/
4206 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4207 {
4208         int i;
4209
4210         for (i = 0; i < adapter->num_rx_queues; i++)
4211                 if (adapter->rx_ring[i].desc)
4212                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4213 }
4214
4215 /**
4216  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4217  * @netdev: network interface device structure
4218  * @new_mtu: new value for maximum frame size
4219  *
4220  * Returns 0 on success, negative on failure
4221  **/
4222 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4223 {
4224         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4225         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4226
4227         /* MTU < 68 is an error and causes problems on some kernels */
4228         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4229                 return -EINVAL;
4230
4231         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4232                 netdev->mtu, new_mtu);
4233         /* must set new MTU before calling down or up */
4234         netdev->mtu = new_mtu;
4235
4236         if (netif_running(netdev))
4237                 ixgbe_reinit_locked(adapter);
4238
4239         return 0;
4240 }
4241
4242 /**
4243  * ixgbe_open - Called when a network interface is made active
4244  * @netdev: network interface device structure
4245  *
4246  * Returns 0 on success, negative value on failure
4247  *
4248  * The open entry point is called when a network interface is made
4249  * active by the system (IFF_UP).  At this point all resources needed
4250  * for transmit and receive operations are allocated, the interrupt
4251  * handler is registered with the OS, the watchdog timer is started,
4252  * and the stack is notified that the interface is ready.
4253  **/
4254 static int ixgbe_open(struct net_device *netdev)
4255 {
4256         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4257         int err;
4258
4259         /* disallow open during test */
4260         if (test_bit(__IXGBE_TESTING, &adapter->state))
4261                 return -EBUSY;
4262
4263         netif_carrier_off(netdev);
4264
4265         /* allocate transmit descriptors */
4266         err = ixgbe_setup_all_tx_resources(adapter);
4267         if (err)
4268                 goto err_setup_tx;
4269
4270         /* allocate receive descriptors */
4271         err = ixgbe_setup_all_rx_resources(adapter);
4272         if (err)
4273                 goto err_setup_rx;
4274
4275         ixgbe_configure(adapter);
4276
4277         err = ixgbe_request_irq(adapter);
4278         if (err)
4279                 goto err_req_irq;
4280
4281         err = ixgbe_up_complete(adapter);
4282         if (err)
4283                 goto err_up;
4284
4285         netif_tx_start_all_queues(netdev);
4286
4287         return 0;
4288
4289 err_up:
4290         ixgbe_release_hw_control(adapter);
4291         ixgbe_free_irq(adapter);
4292 err_req_irq:
4293 err_setup_rx:
4294         ixgbe_free_all_rx_resources(adapter);
4295 err_setup_tx:
4296         ixgbe_free_all_tx_resources(adapter);
4297         ixgbe_reset(adapter);
4298
4299         return err;
4300 }
4301
4302 /**
4303  * ixgbe_close - Disables a network interface
4304  * @netdev: network interface device structure
4305  *
4306  * Returns 0, this is not allowed to fail
4307  *
4308  * The close entry point is called when an interface is de-activated
4309  * by the OS.  The hardware is still under the drivers control, but
4310  * needs to be disabled.  A global MAC reset is issued to stop the
4311  * hardware, and all transmit and receive resources are freed.
4312  **/
4313 static int ixgbe_close(struct net_device *netdev)
4314 {
4315         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4316
4317         ixgbe_down(adapter);
4318         ixgbe_free_irq(adapter);
4319
4320         ixgbe_free_all_tx_resources(adapter);
4321         ixgbe_free_all_rx_resources(adapter);
4322
4323         ixgbe_release_hw_control(adapter);
4324
4325         return 0;
4326 }
4327
4328 #ifdef CONFIG_PM
4329 static int ixgbe_resume(struct pci_dev *pdev)
4330 {
4331         struct net_device *netdev = pci_get_drvdata(pdev);
4332         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4333         u32 err;
4334
4335         pci_set_power_state(pdev, PCI_D0);
4336         pci_restore_state(pdev);
4337
4338         err = pci_enable_device_mem(pdev);
4339         if (err) {
4340                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4341                                 "suspend\n");
4342                 return err;
4343         }
4344         pci_set_master(pdev);
4345
4346         pci_wake_from_d3(pdev, false);
4347
4348         err = ixgbe_init_interrupt_scheme(adapter);
4349         if (err) {
4350                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4351                                 "device\n");
4352                 return err;
4353         }
4354
4355         ixgbe_reset(adapter);
4356
4357         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4358
4359         if (netif_running(netdev)) {
4360                 err = ixgbe_open(adapter->netdev);
4361                 if (err)
4362                         return err;
4363         }
4364
4365         netif_device_attach(netdev);
4366
4367         return 0;
4368 }
4369 #endif /* CONFIG_PM */
4370
4371 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4372 {
4373         struct net_device *netdev = pci_get_drvdata(pdev);
4374         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4375         struct ixgbe_hw *hw = &adapter->hw;
4376         u32 ctrl, fctrl;
4377         u32 wufc = adapter->wol;
4378 #ifdef CONFIG_PM
4379         int retval = 0;
4380 #endif
4381
4382         netif_device_detach(netdev);
4383
4384         if (netif_running(netdev)) {
4385                 ixgbe_down(adapter);
4386                 ixgbe_free_irq(adapter);
4387                 ixgbe_free_all_tx_resources(adapter);
4388                 ixgbe_free_all_rx_resources(adapter);
4389         }
4390         ixgbe_clear_interrupt_scheme(adapter);
4391
4392 #ifdef CONFIG_PM
4393         retval = pci_save_state(pdev);
4394         if (retval)
4395                 return retval;
4396
4397 #endif
4398         if (wufc) {
4399                 ixgbe_set_rx_mode(netdev);
4400
4401                 /* turn on all-multi mode if wake on multicast is enabled */
4402                 if (wufc & IXGBE_WUFC_MC) {
4403                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4404                         fctrl |= IXGBE_FCTRL_MPE;
4405                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4406                 }
4407
4408                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4409                 ctrl |= IXGBE_CTRL_GIO_DIS;
4410                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4411
4412                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4413         } else {
4414                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4415                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4416         }
4417
4418         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4419                 pci_wake_from_d3(pdev, true);
4420         else
4421                 pci_wake_from_d3(pdev, false);
4422
4423         *enable_wake = !!wufc;
4424
4425         ixgbe_release_hw_control(adapter);
4426
4427         pci_disable_device(pdev);
4428
4429         return 0;
4430 }
4431
4432 #ifdef CONFIG_PM
4433 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4434 {
4435         int retval;
4436         bool wake;
4437
4438         retval = __ixgbe_shutdown(pdev, &wake);
4439         if (retval)
4440                 return retval;
4441
4442         if (wake) {
4443                 pci_prepare_to_sleep(pdev);
4444         } else {
4445                 pci_wake_from_d3(pdev, false);
4446                 pci_set_power_state(pdev, PCI_D3hot);
4447         }
4448
4449         return 0;
4450 }
4451 #endif /* CONFIG_PM */
4452
4453 static void ixgbe_shutdown(struct pci_dev *pdev)
4454 {
4455         bool wake;
4456
4457         __ixgbe_shutdown(pdev, &wake);
4458
4459         if (system_state == SYSTEM_POWER_OFF) {
4460                 pci_wake_from_d3(pdev, wake);
4461                 pci_set_power_state(pdev, PCI_D3hot);
4462         }
4463 }
4464
4465 /**
4466  * ixgbe_update_stats - Update the board statistics counters.
4467  * @adapter: board private structure
4468  **/
4469 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4470 {
4471         struct net_device *netdev = adapter->netdev;
4472         struct ixgbe_hw *hw = &adapter->hw;
4473         u64 total_mpc = 0;
4474         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4475
4476         if (hw->mac.type == ixgbe_mac_82599EB) {
4477                 u64 rsc_count = 0;
4478                 for (i = 0; i < 16; i++)
4479                         adapter->hw_rx_no_dma_resources +=
4480                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4481                 for (i = 0; i < adapter->num_rx_queues; i++)
4482                         rsc_count += adapter->rx_ring[i].rsc_count;
4483                 adapter->rsc_count = rsc_count;
4484         }
4485
4486         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4487         for (i = 0; i < 8; i++) {
4488                 /* for packet buffers not used, the register should read 0 */
4489                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4490                 missed_rx += mpc;
4491                 adapter->stats.mpc[i] += mpc;
4492                 total_mpc += adapter->stats.mpc[i];
4493                 if (hw->mac.type == ixgbe_mac_82598EB)
4494                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4495                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4496                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4497                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4498                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4499                 if (hw->mac.type == ixgbe_mac_82599EB) {
4500                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4501                                                             IXGBE_PXONRXCNT(i));
4502                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4503                                                            IXGBE_PXOFFRXCNT(i));
4504                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4505                 } else {
4506                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4507                                                               IXGBE_PXONRXC(i));
4508                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4509                                                              IXGBE_PXOFFRXC(i));
4510                 }
4511                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4512                                                             IXGBE_PXONTXC(i));
4513                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4514                                                              IXGBE_PXOFFTXC(i));
4515         }
4516         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4517         /* work around hardware counting issue */
4518         adapter->stats.gprc -= missed_rx;
4519
4520         /* 82598 hardware only has a 32 bit counter in the high register */
4521         if (hw->mac.type == ixgbe_mac_82599EB) {
4522                 u64 tmp;
4523                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4524                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4525                 adapter->stats.gorc += (tmp << 32);
4526                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4527                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4528                 adapter->stats.gotc += (tmp << 32);
4529                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4530                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4531                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4532                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4533                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4534                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4535 #ifdef IXGBE_FCOE
4536                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4537                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4538                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4539                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4540                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4541                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4542 #endif /* IXGBE_FCOE */
4543         } else {
4544                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4545                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4546                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4547                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4548                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4549         }
4550         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4551         adapter->stats.bprc += bprc;
4552         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4553         if (hw->mac.type == ixgbe_mac_82598EB)
4554                 adapter->stats.mprc -= bprc;
4555         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4556         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4557         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4558         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4559         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4560         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4561         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4562         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4563         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4564         adapter->stats.lxontxc += lxon;
4565         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4566         adapter->stats.lxofftxc += lxoff;
4567         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4568         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4569         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4570         /*
4571          * 82598 errata - tx of flow control packets is included in tx counters
4572          */
4573         xon_off_tot = lxon + lxoff;
4574         adapter->stats.gptc -= xon_off_tot;
4575         adapter->stats.mptc -= xon_off_tot;
4576         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4577         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4578         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4579         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4580         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4581         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4582         adapter->stats.ptc64 -= xon_off_tot;
4583         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4584         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4585         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4586         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4587         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4588         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4589
4590         /* Fill out the OS statistics structure */
4591         netdev->stats.multicast = adapter->stats.mprc;
4592
4593         /* Rx Errors */
4594         netdev->stats.rx_errors = adapter->stats.crcerrs +
4595                                        adapter->stats.rlec;
4596         netdev->stats.rx_dropped = 0;
4597         netdev->stats.rx_length_errors = adapter->stats.rlec;
4598         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4599         netdev->stats.rx_missed_errors = total_mpc;
4600 }
4601
4602 /**
4603  * ixgbe_watchdog - Timer Call-back
4604  * @data: pointer to adapter cast into an unsigned long
4605  **/
4606 static void ixgbe_watchdog(unsigned long data)
4607 {
4608         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4609         struct ixgbe_hw *hw = &adapter->hw;
4610         u64 eics = 0;
4611         int i;
4612
4613         /*
4614          *  Do the watchdog outside of interrupt context due to the lovely
4615          * delays that some of the newer hardware requires
4616          */
4617
4618         if (test_bit(__IXGBE_DOWN, &adapter->state))
4619                 goto watchdog_short_circuit;
4620
4621         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4622                 /*
4623                  * for legacy and MSI interrupts don't set any bits
4624                  * that are enabled for EIAM, because this operation
4625                  * would set *both* EIMS and EICS for any bit in EIAM
4626                  */
4627                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4628                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4629                 goto watchdog_reschedule;
4630         }
4631
4632         /* get one bit for every active tx/rx interrupt vector */
4633         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4634                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4635                 if (qv->rxr_count || qv->txr_count)
4636                         eics |= ((u64)1 << i);
4637         }
4638
4639         /* Cause software interrupt to ensure rx rings are cleaned */
4640         ixgbe_irq_rearm_queues(adapter, eics);
4641
4642 watchdog_reschedule:
4643         /* Reset the timer */
4644         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4645
4646 watchdog_short_circuit:
4647         schedule_work(&adapter->watchdog_task);
4648 }
4649
4650 /**
4651  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4652  * @work: pointer to work_struct containing our data
4653  **/
4654 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4655 {
4656         struct ixgbe_adapter *adapter = container_of(work,
4657                                                      struct ixgbe_adapter,
4658                                                      multispeed_fiber_task);
4659         struct ixgbe_hw *hw = &adapter->hw;
4660         u32 autoneg;
4661         bool negotiation;
4662
4663         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4664         autoneg = hw->phy.autoneg_advertised;
4665         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4666                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4667         if (hw->mac.ops.setup_link)
4668                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4669         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4670         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4671 }
4672
4673 /**
4674  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4675  * @work: pointer to work_struct containing our data
4676  **/
4677 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4678 {
4679         struct ixgbe_adapter *adapter = container_of(work,
4680                                                      struct ixgbe_adapter,
4681                                                      sfp_config_module_task);
4682         struct ixgbe_hw *hw = &adapter->hw;
4683         u32 err;
4684
4685         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4686
4687         /* Time for electrical oscillations to settle down */
4688         msleep(100);
4689         err = hw->phy.ops.identify_sfp(hw);
4690
4691         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4692                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4693                         "an unsupported SFP+ module type was detected.\n"
4694                         "Reload the driver after installing a supported "
4695                         "module.\n");
4696                 unregister_netdev(adapter->netdev);
4697                 return;
4698         }
4699         hw->mac.ops.setup_sfp(hw);
4700
4701         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4702                 /* This will also work for DA Twinax connections */
4703                 schedule_work(&adapter->multispeed_fiber_task);
4704         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4705 }
4706
4707 /**
4708  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4709  * @work: pointer to work_struct containing our data
4710  **/
4711 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4712 {
4713         struct ixgbe_adapter *adapter = container_of(work,
4714                                                      struct ixgbe_adapter,
4715                                                      fdir_reinit_task);
4716         struct ixgbe_hw *hw = &adapter->hw;
4717         int i;
4718
4719         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4720                 for (i = 0; i < adapter->num_tx_queues; i++)
4721                         set_bit(__IXGBE_FDIR_INIT_DONE,
4722                                 &(adapter->tx_ring[i].reinit_state));
4723         } else {
4724                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4725                         "ignored adding FDIR ATR filters \n");
4726         }
4727         /* Done FDIR Re-initialization, enable transmits */
4728         netif_tx_start_all_queues(adapter->netdev);
4729 }
4730
4731 /**
4732  * ixgbe_watchdog_task - worker thread to bring link up
4733  * @work: pointer to work_struct containing our data
4734  **/
4735 static void ixgbe_watchdog_task(struct work_struct *work)
4736 {
4737         struct ixgbe_adapter *adapter = container_of(work,
4738                                                      struct ixgbe_adapter,
4739                                                      watchdog_task);
4740         struct net_device *netdev = adapter->netdev;
4741         struct ixgbe_hw *hw = &adapter->hw;
4742         u32 link_speed = adapter->link_speed;
4743         bool link_up = adapter->link_up;
4744         int i;
4745         struct ixgbe_ring *tx_ring;
4746         int some_tx_pending = 0;
4747
4748         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4749
4750         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4751                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4752                 if (link_up) {
4753 #ifdef CONFIG_DCB
4754                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4755                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4756                                         hw->mac.ops.fc_enable(hw, i);
4757                         } else {
4758                                 hw->mac.ops.fc_enable(hw, 0);
4759                         }
4760 #else
4761                         hw->mac.ops.fc_enable(hw, 0);
4762 #endif
4763                 }
4764
4765                 if (link_up ||
4766                     time_after(jiffies, (adapter->link_check_timeout +
4767                                          IXGBE_TRY_LINK_TIMEOUT))) {
4768                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4769                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4770                 }
4771                 adapter->link_up = link_up;
4772                 adapter->link_speed = link_speed;
4773         }
4774
4775         if (link_up) {
4776                 if (!netif_carrier_ok(netdev)) {
4777                         bool flow_rx, flow_tx;
4778
4779                         if (hw->mac.type == ixgbe_mac_82599EB) {
4780                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4781                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4782                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4783                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4784                         } else {
4785                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4786                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4787                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4788                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4789                         }
4790
4791                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4792                                "Flow Control: %s\n",
4793                                netdev->name,
4794                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4795                                 "10 Gbps" :
4796                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4797                                  "1 Gbps" : "unknown speed")),
4798                                ((flow_rx && flow_tx) ? "RX/TX" :
4799                                 (flow_rx ? "RX" :
4800                                 (flow_tx ? "TX" : "None"))));
4801
4802                         netif_carrier_on(netdev);
4803                 } else {
4804                         /* Force detection of hung controller */
4805                         adapter->detect_tx_hung = true;
4806                 }
4807         } else {
4808                 adapter->link_up = false;
4809                 adapter->link_speed = 0;
4810                 if (netif_carrier_ok(netdev)) {
4811                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4812                                netdev->name);
4813                         netif_carrier_off(netdev);
4814                 }
4815         }
4816
4817         if (!netif_carrier_ok(netdev)) {
4818                 for (i = 0; i < adapter->num_tx_queues; i++) {
4819                         tx_ring = &adapter->tx_ring[i];
4820                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4821                                 some_tx_pending = 1;
4822                                 break;
4823                         }
4824                 }
4825
4826                 if (some_tx_pending) {
4827                         /* We've lost link, so the controller stops DMA,
4828                          * but we've got queued Tx work that's never going
4829                          * to get done, so reset controller to flush Tx.
4830                          * (Do the reset outside of interrupt context).
4831                          */
4832                          schedule_work(&adapter->reset_task);
4833                 }
4834         }
4835
4836         ixgbe_update_stats(adapter);
4837         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4838 }
4839
4840 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4841                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4842                      u32 tx_flags, u8 *hdr_len)
4843 {
4844         struct ixgbe_adv_tx_context_desc *context_desc;
4845         unsigned int i;
4846         int err;
4847         struct ixgbe_tx_buffer *tx_buffer_info;
4848         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4849         u32 mss_l4len_idx, l4len;
4850
4851         if (skb_is_gso(skb)) {
4852                 if (skb_header_cloned(skb)) {
4853                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4854                         if (err)
4855                                 return err;
4856                 }
4857                 l4len = tcp_hdrlen(skb);
4858                 *hdr_len += l4len;
4859
4860                 if (skb->protocol == htons(ETH_P_IP)) {
4861                         struct iphdr *iph = ip_hdr(skb);
4862                         iph->tot_len = 0;
4863                         iph->check = 0;
4864                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4865                                                                  iph->daddr, 0,
4866                                                                  IPPROTO_TCP,
4867                                                                  0);
4868                         adapter->hw_tso_ctxt++;
4869                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4870                         ipv6_hdr(skb)->payload_len = 0;
4871                         tcp_hdr(skb)->check =
4872                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4873                                              &ipv6_hdr(skb)->daddr,
4874                                              0, IPPROTO_TCP, 0);
4875                         adapter->hw_tso6_ctxt++;
4876                 }
4877
4878                 i = tx_ring->next_to_use;
4879
4880                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4881                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4882
4883                 /* VLAN MACLEN IPLEN */
4884                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4885                         vlan_macip_lens |=
4886                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4887                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4888                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4889                 *hdr_len += skb_network_offset(skb);
4890                 vlan_macip_lens |=
4891                     (skb_transport_header(skb) - skb_network_header(skb));
4892                 *hdr_len +=
4893                     (skb_transport_header(skb) - skb_network_header(skb));
4894                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4895                 context_desc->seqnum_seed = 0;
4896
4897                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4898                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4899                                    IXGBE_ADVTXD_DTYP_CTXT);
4900
4901                 if (skb->protocol == htons(ETH_P_IP))
4902                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4903                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4904                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4905
4906                 /* MSS L4LEN IDX */
4907                 mss_l4len_idx =
4908                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4909                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4910                 /* use index 1 for TSO */
4911                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4912                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4913
4914                 tx_buffer_info->time_stamp = jiffies;
4915                 tx_buffer_info->next_to_watch = i;
4916
4917                 i++;
4918                 if (i == tx_ring->count)
4919                         i = 0;
4920                 tx_ring->next_to_use = i;
4921
4922                 return true;
4923         }
4924         return false;
4925 }
4926
4927 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4928                           struct ixgbe_ring *tx_ring,
4929                           struct sk_buff *skb, u32 tx_flags)
4930 {
4931         struct ixgbe_adv_tx_context_desc *context_desc;
4932         unsigned int i;
4933         struct ixgbe_tx_buffer *tx_buffer_info;
4934         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4935
4936         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4937             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4938                 i = tx_ring->next_to_use;
4939                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4940                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4941
4942                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4943                         vlan_macip_lens |=
4944                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4945                 vlan_macip_lens |= (skb_network_offset(skb) <<
4946                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4947                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4948                         vlan_macip_lens |= (skb_transport_header(skb) -
4949                                             skb_network_header(skb));
4950
4951                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4952                 context_desc->seqnum_seed = 0;
4953
4954                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4955                                     IXGBE_ADVTXD_DTYP_CTXT);
4956
4957                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4958                         switch (skb->protocol) {
4959                         case cpu_to_be16(ETH_P_IP):
4960                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4961                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4962                                         type_tucmd_mlhl |=
4963                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4964                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4965                                         type_tucmd_mlhl |=
4966                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4967                                 break;
4968                         case cpu_to_be16(ETH_P_IPV6):
4969                                 /* XXX what about other V6 headers?? */
4970                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4971                                         type_tucmd_mlhl |=
4972                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4973                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4974                                         type_tucmd_mlhl |=
4975                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4976                                 break;
4977                         default:
4978                                 if (unlikely(net_ratelimit())) {
4979                                         DPRINTK(PROBE, WARNING,
4980                                          "partial checksum but proto=%x!\n",
4981                                          skb->protocol);
4982                                 }
4983                                 break;
4984                         }
4985                 }
4986
4987                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4988                 /* use index zero for tx checksum offload */
4989                 context_desc->mss_l4len_idx = 0;
4990
4991                 tx_buffer_info->time_stamp = jiffies;
4992                 tx_buffer_info->next_to_watch = i;
4993
4994                 adapter->hw_csum_tx_good++;
4995                 i++;
4996                 if (i == tx_ring->count)
4997                         i = 0;
4998                 tx_ring->next_to_use = i;
4999
5000                 return true;
5001         }
5002
5003         return false;
5004 }
5005
5006 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5007                         struct ixgbe_ring *tx_ring,
5008                         struct sk_buff *skb, u32 tx_flags,
5009                         unsigned int first)
5010 {
5011         struct ixgbe_tx_buffer *tx_buffer_info;
5012         unsigned int len;
5013         unsigned int total = skb->len;
5014         unsigned int offset = 0, size, count = 0, i;
5015         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5016         unsigned int f;
5017         dma_addr_t *map;
5018
5019         i = tx_ring->next_to_use;
5020
5021         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
5022                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
5023                 return 0;
5024         }
5025
5026         map = skb_shinfo(skb)->dma_maps;
5027
5028         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5029                 /* excluding fcoe_crc_eof for FCoE */
5030                 total -= sizeof(struct fcoe_crc_eof);
5031
5032         len = min(skb_headlen(skb), total);
5033         while (len) {
5034                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5035                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5036
5037                 tx_buffer_info->length = size;
5038                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
5039                 tx_buffer_info->time_stamp = jiffies;
5040                 tx_buffer_info->next_to_watch = i;
5041
5042                 len -= size;
5043                 total -= size;
5044                 offset += size;
5045                 count++;
5046
5047                 if (len) {
5048                         i++;
5049                         if (i == tx_ring->count)
5050                                 i = 0;
5051                 }
5052         }
5053
5054         for (f = 0; f < nr_frags; f++) {
5055                 struct skb_frag_struct *frag;
5056
5057                 frag = &skb_shinfo(skb)->frags[f];
5058                 len = min((unsigned int)frag->size, total);
5059                 offset = 0;
5060
5061                 while (len) {
5062                         i++;
5063                         if (i == tx_ring->count)
5064                                 i = 0;
5065
5066                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5067                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5068
5069                         tx_buffer_info->length = size;
5070                         tx_buffer_info->dma = map[f] + offset;
5071                         tx_buffer_info->time_stamp = jiffies;
5072                         tx_buffer_info->next_to_watch = i;
5073
5074                         len -= size;
5075                         total -= size;
5076                         offset += size;
5077                         count++;
5078                 }
5079                 if (total == 0)
5080                         break;
5081         }
5082
5083         tx_ring->tx_buffer_info[i].skb = skb;
5084         tx_ring->tx_buffer_info[first].next_to_watch = i;
5085
5086         return count;
5087 }
5088
5089 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5090                            struct ixgbe_ring *tx_ring,
5091                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5092 {
5093         union ixgbe_adv_tx_desc *tx_desc = NULL;
5094         struct ixgbe_tx_buffer *tx_buffer_info;
5095         u32 olinfo_status = 0, cmd_type_len = 0;
5096         unsigned int i;
5097         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5098
5099         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5100
5101         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5102
5103         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5104                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5105
5106         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5107                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5108
5109                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5110                                  IXGBE_ADVTXD_POPTS_SHIFT;
5111
5112                 /* use index 1 context for tso */
5113                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5114                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5115                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5116                                          IXGBE_ADVTXD_POPTS_SHIFT;
5117
5118         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5119                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5120                                  IXGBE_ADVTXD_POPTS_SHIFT;
5121
5122         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5123                 olinfo_status |= IXGBE_ADVTXD_CC;
5124                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5125                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5126                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5127         }
5128
5129         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5130
5131         i = tx_ring->next_to_use;
5132         while (count--) {
5133                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5134                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5135                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5136                 tx_desc->read.cmd_type_len =
5137                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5138                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5139                 i++;
5140                 if (i == tx_ring->count)
5141                         i = 0;
5142         }
5143
5144         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5145
5146         /*
5147          * Force memory writes to complete before letting h/w
5148          * know there are new descriptors to fetch.  (Only
5149          * applicable for weak-ordered memory model archs,
5150          * such as IA-64).
5151          */
5152         wmb();
5153
5154         tx_ring->next_to_use = i;
5155         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5156 }
5157
5158 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5159                       int queue, u32 tx_flags)
5160 {
5161         /* Right now, we support IPv4 only */
5162         struct ixgbe_atr_input atr_input;
5163         struct tcphdr *th;
5164         struct iphdr *iph = ip_hdr(skb);
5165         struct ethhdr *eth = (struct ethhdr *)skb->data;
5166         u16 vlan_id, src_port, dst_port, flex_bytes;
5167         u32 src_ipv4_addr, dst_ipv4_addr;
5168         u8 l4type = 0;
5169
5170         /* check if we're UDP or TCP */
5171         if (iph->protocol == IPPROTO_TCP) {
5172                 th = tcp_hdr(skb);
5173                 src_port = th->source;
5174                 dst_port = th->dest;
5175                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5176                 /* l4type IPv4 type is 0, no need to assign */
5177         } else {
5178                 /* Unsupported L4 header, just bail here */
5179                 return;
5180         }
5181
5182         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5183
5184         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5185                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5186         src_ipv4_addr = iph->saddr;
5187         dst_ipv4_addr = iph->daddr;
5188         flex_bytes = eth->h_proto;
5189
5190         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5191         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5192         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5193         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5194         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5195         /* src and dst are inverted, think how the receiver sees them */
5196         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5197         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5198
5199         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5200         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5201 }
5202
5203 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5204                                  struct ixgbe_ring *tx_ring, int size)
5205 {
5206         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5207
5208         netif_stop_subqueue(netdev, tx_ring->queue_index);
5209         /* Herbert's original patch had:
5210          *  smp_mb__after_netif_stop_queue();
5211          * but since that doesn't exist yet, just open code it. */
5212         smp_mb();
5213
5214         /* We need to check again in a case another CPU has just
5215          * made room available. */
5216         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5217                 return -EBUSY;
5218
5219         /* A reprieve! - use start_queue because it doesn't call schedule */
5220         netif_start_subqueue(netdev, tx_ring->queue_index);
5221         ++adapter->restart_queue;
5222         return 0;
5223 }
5224
5225 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5226                               struct ixgbe_ring *tx_ring, int size)
5227 {
5228         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5229                 return 0;
5230         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5231 }
5232
5233 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5234 {
5235         struct ixgbe_adapter *adapter = netdev_priv(dev);
5236
5237         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5238                 return smp_processor_id();
5239
5240         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5241                 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5242
5243         return skb_tx_hash(dev, skb);
5244 }
5245
5246 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5247                                     struct net_device *netdev)
5248 {
5249         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5250         struct ixgbe_ring *tx_ring;
5251         unsigned int first;
5252         unsigned int tx_flags = 0;
5253         u8 hdr_len = 0;
5254         int r_idx = 0, tso;
5255         int count = 0;
5256         unsigned int f;
5257
5258         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5259                 tx_flags |= vlan_tx_tag_get(skb);
5260                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5261                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5262                         tx_flags |= (skb->queue_mapping << 13);
5263                 }
5264                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5265                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5266         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5267                 if (skb->priority != TC_PRIO_CONTROL) {
5268                         tx_flags |= (skb->queue_mapping << 13);
5269                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5270                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5271                 } else {
5272                         skb->queue_mapping =
5273                                 adapter->ring_feature[RING_F_DCB].indices-1;
5274                 }
5275         }
5276
5277         r_idx = skb->queue_mapping;
5278         tx_ring = &adapter->tx_ring[r_idx];
5279
5280         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5281             (skb->protocol == htons(ETH_P_FCOE))) {
5282                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5283 #ifdef IXGBE_FCOE
5284                 r_idx = smp_processor_id();
5285                 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5286                 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5287                 tx_ring = &adapter->tx_ring[r_idx];
5288 #endif
5289         }
5290         /* four things can cause us to need a context descriptor */
5291         if (skb_is_gso(skb) ||
5292             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5293             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5294             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5295                 count++;
5296
5297         count += TXD_USE_COUNT(skb_headlen(skb));
5298         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5299                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5300
5301         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5302                 adapter->tx_busy++;
5303                 return NETDEV_TX_BUSY;
5304         }
5305
5306         first = tx_ring->next_to_use;
5307         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5308 #ifdef IXGBE_FCOE
5309                 /* setup tx offload for FCoE */
5310                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5311                 if (tso < 0) {
5312                         dev_kfree_skb_any(skb);
5313                         return NETDEV_TX_OK;
5314                 }
5315                 if (tso)
5316                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5317 #endif /* IXGBE_FCOE */
5318         } else {
5319                 if (skb->protocol == htons(ETH_P_IP))
5320                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5321                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5322                 if (tso < 0) {
5323                         dev_kfree_skb_any(skb);
5324                         return NETDEV_TX_OK;
5325                 }
5326
5327                 if (tso)
5328                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5329                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5330                          (skb->ip_summed == CHECKSUM_PARTIAL))
5331                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5332         }
5333
5334         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5335         if (count) {
5336                 /* add the ATR filter if ATR is on */
5337                 if (tx_ring->atr_sample_rate) {
5338                         ++tx_ring->atr_count;
5339                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5340                              test_bit(__IXGBE_FDIR_INIT_DONE,
5341                                       &tx_ring->reinit_state)) {
5342                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5343                                           tx_flags);
5344                                 tx_ring->atr_count = 0;
5345                         }
5346                 }
5347                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5348                                hdr_len);
5349                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5350
5351         } else {
5352                 dev_kfree_skb_any(skb);
5353                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5354                 tx_ring->next_to_use = first;
5355         }
5356
5357         return NETDEV_TX_OK;
5358 }
5359
5360 /**
5361  * ixgbe_get_stats - Get System Network Statistics
5362  * @netdev: network interface device structure
5363  *
5364  * Returns the address of the device statistics structure.
5365  * The statistics are actually updated from the timer callback.
5366  **/
5367 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5368 {
5369         /* only return the current stats */
5370         return &netdev->stats;
5371 }
5372
5373 /**
5374  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5375  * @netdev: network interface device structure
5376  * @p: pointer to an address structure
5377  *
5378  * Returns 0 on success, negative on failure
5379  **/
5380 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5381 {
5382         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5383         struct ixgbe_hw *hw = &adapter->hw;
5384         struct sockaddr *addr = p;
5385
5386         if (!is_valid_ether_addr(addr->sa_data))
5387                 return -EADDRNOTAVAIL;
5388
5389         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5390         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5391
5392         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5393
5394         return 0;
5395 }
5396
5397 static int
5398 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5399 {
5400         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5401         struct ixgbe_hw *hw = &adapter->hw;
5402         u16 value;
5403         int rc;
5404
5405         if (prtad != hw->phy.mdio.prtad)
5406                 return -EINVAL;
5407         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5408         if (!rc)
5409                 rc = value;
5410         return rc;
5411 }
5412
5413 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5414                             u16 addr, u16 value)
5415 {
5416         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5417         struct ixgbe_hw *hw = &adapter->hw;
5418
5419         if (prtad != hw->phy.mdio.prtad)
5420                 return -EINVAL;
5421         return hw->phy.ops.write_reg(hw, addr, devad, value);
5422 }
5423
5424 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5425 {
5426         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5427
5428         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5429 }
5430
5431 /**
5432  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5433  * netdev->dev_addrs
5434  * @netdev: network interface device structure
5435  *
5436  * Returns non-zero on failure
5437  **/
5438 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5439 {
5440         int err = 0;
5441         struct ixgbe_adapter *adapter = netdev_priv(dev);
5442         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5443
5444         if (is_valid_ether_addr(mac->san_addr)) {
5445                 rtnl_lock();
5446                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5447                 rtnl_unlock();
5448         }
5449         return err;
5450 }
5451
5452 /**
5453  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5454  * netdev->dev_addrs
5455  * @netdev: network interface device structure
5456  *
5457  * Returns non-zero on failure
5458  **/
5459 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5460 {
5461         int err = 0;
5462         struct ixgbe_adapter *adapter = netdev_priv(dev);
5463         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5464
5465         if (is_valid_ether_addr(mac->san_addr)) {
5466                 rtnl_lock();
5467                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5468                 rtnl_unlock();
5469         }
5470         return err;
5471 }
5472
5473 #ifdef CONFIG_NET_POLL_CONTROLLER
5474 /*
5475  * Polling 'interrupt' - used by things like netconsole to send skbs
5476  * without having to re-enable interrupts. It's not called while
5477  * the interrupt routine is executing.
5478  */
5479 static void ixgbe_netpoll(struct net_device *netdev)
5480 {
5481         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5482         int i;
5483
5484         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5485         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5486                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5487                 for (i = 0; i < num_q_vectors; i++) {
5488                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5489                         ixgbe_msix_clean_many(0, q_vector);
5490                 }
5491         } else {
5492                 ixgbe_intr(adapter->pdev->irq, netdev);
5493         }
5494         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5495 }
5496 #endif
5497
5498 static const struct net_device_ops ixgbe_netdev_ops = {
5499         .ndo_open               = ixgbe_open,
5500         .ndo_stop               = ixgbe_close,
5501         .ndo_start_xmit         = ixgbe_xmit_frame,
5502         .ndo_select_queue       = ixgbe_select_queue,
5503         .ndo_get_stats          = ixgbe_get_stats,
5504         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5505         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5506         .ndo_validate_addr      = eth_validate_addr,
5507         .ndo_set_mac_address    = ixgbe_set_mac,
5508         .ndo_change_mtu         = ixgbe_change_mtu,
5509         .ndo_tx_timeout         = ixgbe_tx_timeout,
5510         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5511         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5512         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5513         .ndo_do_ioctl           = ixgbe_ioctl,
5514 #ifdef CONFIG_NET_POLL_CONTROLLER
5515         .ndo_poll_controller    = ixgbe_netpoll,
5516 #endif
5517 #ifdef IXGBE_FCOE
5518         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5519         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5520         .ndo_fcoe_enable = ixgbe_fcoe_enable,
5521         .ndo_fcoe_disable = ixgbe_fcoe_disable,
5522         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
5523 #endif /* IXGBE_FCOE */
5524 };
5525
5526 /**
5527  * ixgbe_probe - Device Initialization Routine
5528  * @pdev: PCI device information struct
5529  * @ent: entry in ixgbe_pci_tbl
5530  *
5531  * Returns 0 on success, negative on failure
5532  *
5533  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5534  * The OS initialization, configuring of the adapter private structure,
5535  * and a hardware reset occur.
5536  **/
5537 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5538                                  const struct pci_device_id *ent)
5539 {
5540         struct net_device *netdev;
5541         struct ixgbe_adapter *adapter = NULL;
5542         struct ixgbe_hw *hw;
5543         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5544         static int cards_found;
5545         int i, err, pci_using_dac;
5546 #ifdef IXGBE_FCOE
5547         u16 device_caps;
5548 #endif
5549         u32 part_num, eec;
5550
5551         err = pci_enable_device_mem(pdev);
5552         if (err)
5553                 return err;
5554
5555         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5556             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5557                 pci_using_dac = 1;
5558         } else {
5559                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5560                 if (err) {
5561                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5562                         if (err) {
5563                                 dev_err(&pdev->dev, "No usable DMA "
5564                                         "configuration, aborting\n");
5565                                 goto err_dma;
5566                         }
5567                 }
5568                 pci_using_dac = 0;
5569         }
5570
5571         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5572                                            IORESOURCE_MEM), ixgbe_driver_name);
5573         if (err) {
5574                 dev_err(&pdev->dev,
5575                         "pci_request_selected_regions failed 0x%x\n", err);
5576                 goto err_pci_reg;
5577         }
5578
5579         pci_enable_pcie_error_reporting(pdev);
5580
5581         pci_set_master(pdev);
5582         pci_save_state(pdev);
5583
5584         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5585         if (!netdev) {
5586                 err = -ENOMEM;
5587                 goto err_alloc_etherdev;
5588         }
5589
5590         SET_NETDEV_DEV(netdev, &pdev->dev);
5591
5592         pci_set_drvdata(pdev, netdev);
5593         adapter = netdev_priv(netdev);
5594
5595         adapter->netdev = netdev;
5596         adapter->pdev = pdev;
5597         hw = &adapter->hw;
5598         hw->back = adapter;
5599         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5600
5601         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5602                               pci_resource_len(pdev, 0));
5603         if (!hw->hw_addr) {
5604                 err = -EIO;
5605                 goto err_ioremap;
5606         }
5607
5608         for (i = 1; i <= 5; i++) {
5609                 if (pci_resource_len(pdev, i) == 0)
5610                         continue;
5611         }
5612
5613         netdev->netdev_ops = &ixgbe_netdev_ops;
5614         ixgbe_set_ethtool_ops(netdev);
5615         netdev->watchdog_timeo = 5 * HZ;
5616         strcpy(netdev->name, pci_name(pdev));
5617
5618         adapter->bd_number = cards_found;
5619
5620         /* Setup hw api */
5621         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5622         hw->mac.type  = ii->mac;
5623
5624         /* EEPROM */
5625         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5626         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5627         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5628         if (!(eec & (1 << 8)))
5629                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5630
5631         /* PHY */
5632         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5633         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5634         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5635         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5636         hw->phy.mdio.mmds = 0;
5637         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5638         hw->phy.mdio.dev = netdev;
5639         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5640         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5641
5642         /* set up this timer and work struct before calling get_invariants
5643          * which might start the timer
5644          */
5645         init_timer(&adapter->sfp_timer);
5646         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5647         adapter->sfp_timer.data = (unsigned long) adapter;
5648
5649         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5650
5651         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5652         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5653
5654         /* a new SFP+ module arrival, called from GPI SDP2 context */
5655         INIT_WORK(&adapter->sfp_config_module_task,
5656                   ixgbe_sfp_config_module_task);
5657
5658         ii->get_invariants(hw);
5659
5660         /* setup the private structure */
5661         err = ixgbe_sw_init(adapter);
5662         if (err)
5663                 goto err_sw_init;
5664
5665         /*
5666          * If there is a fan on this device and it has failed log the
5667          * failure.
5668          */
5669         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5670                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5671                 if (esdp & IXGBE_ESDP_SDP1)
5672                         DPRINTK(PROBE, CRIT,
5673                                 "Fan has stopped, replace the adapter\n");
5674         }
5675
5676         /* reset_hw fills in the perm_addr as well */
5677         err = hw->mac.ops.reset_hw(hw);
5678         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5679             hw->mac.type == ixgbe_mac_82598EB) {
5680                 /*
5681                  * Start a kernel thread to watch for a module to arrive.
5682                  * Only do this for 82598, since 82599 will generate
5683                  * interrupts on module arrival.
5684                  */
5685                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5686                 mod_timer(&adapter->sfp_timer,
5687                           round_jiffies(jiffies + (2 * HZ)));
5688                 err = 0;
5689         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5690                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5691                         "an unsupported SFP+ module type was detected.\n"
5692                         "Reload the driver after installing a supported "
5693                         "module.\n");
5694                 goto err_sw_init;
5695         } else if (err) {
5696                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5697                 goto err_sw_init;
5698         }
5699
5700         netdev->features = NETIF_F_SG |
5701                            NETIF_F_IP_CSUM |
5702                            NETIF_F_HW_VLAN_TX |
5703                            NETIF_F_HW_VLAN_RX |
5704                            NETIF_F_HW_VLAN_FILTER;
5705
5706         netdev->features |= NETIF_F_IPV6_CSUM;
5707         netdev->features |= NETIF_F_TSO;
5708         netdev->features |= NETIF_F_TSO6;
5709         netdev->features |= NETIF_F_GRO;
5710
5711         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5712                 netdev->features |= NETIF_F_SCTP_CSUM;
5713
5714         netdev->vlan_features |= NETIF_F_TSO;
5715         netdev->vlan_features |= NETIF_F_TSO6;
5716         netdev->vlan_features |= NETIF_F_IP_CSUM;
5717         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5718         netdev->vlan_features |= NETIF_F_SG;
5719
5720         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5721                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5722
5723 #ifdef CONFIG_IXGBE_DCB
5724         netdev->dcbnl_ops = &dcbnl_ops;
5725 #endif
5726
5727 #ifdef IXGBE_FCOE
5728         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5729                 if (hw->mac.ops.get_device_caps) {
5730                         hw->mac.ops.get_device_caps(hw, &device_caps);
5731                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5732                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5733                 }
5734         }
5735 #endif /* IXGBE_FCOE */
5736         if (pci_using_dac)
5737                 netdev->features |= NETIF_F_HIGHDMA;
5738
5739         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5740                 netdev->features |= NETIF_F_LRO;
5741
5742         /* make sure the EEPROM is good */
5743         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5744                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5745                 err = -EIO;
5746                 goto err_eeprom;
5747         }
5748
5749         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5750         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5751
5752         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5753                 dev_err(&pdev->dev, "invalid MAC address\n");
5754                 err = -EIO;
5755                 goto err_eeprom;
5756         }
5757
5758         init_timer(&adapter->watchdog_timer);
5759         adapter->watchdog_timer.function = &ixgbe_watchdog;
5760         adapter->watchdog_timer.data = (unsigned long)adapter;
5761
5762         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5763         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5764
5765         err = ixgbe_init_interrupt_scheme(adapter);
5766         if (err)
5767                 goto err_sw_init;
5768
5769         switch (pdev->device) {
5770         case IXGBE_DEV_ID_82599_KX4:
5771                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5772                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5773                 /* Enable ACPI wakeup in GRC */
5774                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5775                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5776                 break;
5777         default:
5778                 adapter->wol = 0;
5779                 break;
5780         }
5781         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5782
5783         /* pick up the PCI bus settings for reporting later */
5784         hw->mac.ops.get_bus_info(hw);
5785
5786         /* print bus type/speed/width info */
5787         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5788                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5789                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5790                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5791                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5792                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5793                  "Unknown"),
5794                 netdev->dev_addr);
5795         ixgbe_read_pba_num_generic(hw, &part_num);
5796         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5797                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5798                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5799                          (part_num >> 8), (part_num & 0xff));
5800         else
5801                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5802                          hw->mac.type, hw->phy.type,
5803                          (part_num >> 8), (part_num & 0xff));
5804
5805         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5806                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5807                          "this card is not sufficient for optimal "
5808                          "performance.\n");
5809                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5810                          "PCI-Express slot is required.\n");
5811         }
5812
5813         /* save off EEPROM version number */
5814         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5815
5816         /* reset the hardware with the new settings */
5817         err = hw->mac.ops.start_hw(hw);
5818
5819         if (err == IXGBE_ERR_EEPROM_VERSION) {
5820                 /* We are running on a pre-production device, log a warning */
5821                 dev_warn(&pdev->dev, "This device is a pre-production "
5822                          "adapter/LOM.  Please be aware there may be issues "
5823                          "associated with your hardware.  If you are "
5824                          "experiencing problems please contact your Intel or "
5825                          "hardware representative who provided you with this "
5826                          "hardware.\n");
5827         }
5828         strcpy(netdev->name, "eth%d");
5829         err = register_netdev(netdev);
5830         if (err)
5831                 goto err_register;
5832
5833         /* carrier off reporting is important to ethtool even BEFORE open */
5834         netif_carrier_off(netdev);
5835
5836         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5837             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5838                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5839
5840 #ifdef CONFIG_IXGBE_DCA
5841         if (dca_add_requester(&pdev->dev) == 0) {
5842                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5843                 ixgbe_setup_dca(adapter);
5844         }
5845 #endif
5846         /* add san mac addr to netdev */
5847         ixgbe_add_sanmac_netdev(netdev);
5848
5849         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5850         cards_found++;
5851         return 0;
5852
5853 err_register:
5854         ixgbe_release_hw_control(adapter);
5855         ixgbe_clear_interrupt_scheme(adapter);
5856 err_sw_init:
5857 err_eeprom:
5858         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5859         del_timer_sync(&adapter->sfp_timer);
5860         cancel_work_sync(&adapter->sfp_task);
5861         cancel_work_sync(&adapter->multispeed_fiber_task);
5862         cancel_work_sync(&adapter->sfp_config_module_task);
5863         iounmap(hw->hw_addr);
5864 err_ioremap:
5865         free_netdev(netdev);
5866 err_alloc_etherdev:
5867         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5868                                      IORESOURCE_MEM));
5869 err_pci_reg:
5870 err_dma:
5871         pci_disable_device(pdev);
5872         return err;
5873 }
5874
5875 /**
5876  * ixgbe_remove - Device Removal Routine
5877  * @pdev: PCI device information struct
5878  *
5879  * ixgbe_remove is called by the PCI subsystem to alert the driver
5880  * that it should release a PCI device.  The could be caused by a
5881  * Hot-Plug event, or because the driver is going to be removed from
5882  * memory.
5883  **/
5884 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5885 {
5886         struct net_device *netdev = pci_get_drvdata(pdev);
5887         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5888
5889         set_bit(__IXGBE_DOWN, &adapter->state);
5890         /* clear the module not found bit to make sure the worker won't
5891          * reschedule
5892          */
5893         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5894         del_timer_sync(&adapter->watchdog_timer);
5895
5896         del_timer_sync(&adapter->sfp_timer);
5897         cancel_work_sync(&adapter->watchdog_task);
5898         cancel_work_sync(&adapter->sfp_task);
5899         cancel_work_sync(&adapter->multispeed_fiber_task);
5900         cancel_work_sync(&adapter->sfp_config_module_task);
5901         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5902             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5903                 cancel_work_sync(&adapter->fdir_reinit_task);
5904         flush_scheduled_work();
5905
5906 #ifdef CONFIG_IXGBE_DCA
5907         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5908                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5909                 dca_remove_requester(&pdev->dev);
5910                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5911         }
5912
5913 #endif
5914 #ifdef IXGBE_FCOE
5915         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5916                 ixgbe_cleanup_fcoe(adapter);
5917
5918 #endif /* IXGBE_FCOE */
5919
5920         /* remove the added san mac */
5921         ixgbe_del_sanmac_netdev(netdev);
5922
5923         if (netdev->reg_state == NETREG_REGISTERED)
5924                 unregister_netdev(netdev);
5925
5926         ixgbe_clear_interrupt_scheme(adapter);
5927
5928         ixgbe_release_hw_control(adapter);
5929
5930         iounmap(adapter->hw.hw_addr);
5931         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5932                                      IORESOURCE_MEM));
5933
5934         DPRINTK(PROBE, INFO, "complete\n");
5935
5936         free_netdev(netdev);
5937
5938         pci_disable_pcie_error_reporting(pdev);
5939
5940         pci_disable_device(pdev);
5941 }
5942
5943 /**
5944  * ixgbe_io_error_detected - called when PCI error is detected
5945  * @pdev: Pointer to PCI device
5946  * @state: The current pci connection state
5947  *
5948  * This function is called after a PCI bus error affecting
5949  * this device has been detected.
5950  */
5951 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5952                                                 pci_channel_state_t state)
5953 {
5954         struct net_device *netdev = pci_get_drvdata(pdev);
5955         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5956
5957         netif_device_detach(netdev);
5958
5959         if (state == pci_channel_io_perm_failure)
5960                 return PCI_ERS_RESULT_DISCONNECT;
5961
5962         if (netif_running(netdev))
5963                 ixgbe_down(adapter);
5964         pci_disable_device(pdev);
5965
5966         /* Request a slot reset. */
5967         return PCI_ERS_RESULT_NEED_RESET;
5968 }
5969
5970 /**
5971  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5972  * @pdev: Pointer to PCI device
5973  *
5974  * Restart the card from scratch, as if from a cold-boot.
5975  */
5976 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5977 {
5978         struct net_device *netdev = pci_get_drvdata(pdev);
5979         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5980         pci_ers_result_t result;
5981         int err;
5982
5983         if (pci_enable_device_mem(pdev)) {
5984                 DPRINTK(PROBE, ERR,
5985                         "Cannot re-enable PCI device after reset.\n");
5986                 result = PCI_ERS_RESULT_DISCONNECT;
5987         } else {
5988                 pci_set_master(pdev);
5989                 pci_restore_state(pdev);
5990
5991                 pci_wake_from_d3(pdev, false);
5992
5993                 ixgbe_reset(adapter);
5994                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5995                 result = PCI_ERS_RESULT_RECOVERED;
5996         }
5997
5998         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5999         if (err) {
6000                 dev_err(&pdev->dev,
6001                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6002                 /* non-fatal, continue */
6003         }
6004
6005         return result;
6006 }
6007
6008 /**
6009  * ixgbe_io_resume - called when traffic can start flowing again.
6010  * @pdev: Pointer to PCI device
6011  *
6012  * This callback is called when the error recovery driver tells us that
6013  * its OK to resume normal operation.
6014  */
6015 static void ixgbe_io_resume(struct pci_dev *pdev)
6016 {
6017         struct net_device *netdev = pci_get_drvdata(pdev);
6018         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6019
6020         if (netif_running(netdev)) {
6021                 if (ixgbe_up(adapter)) {
6022                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6023                         return;
6024                 }
6025         }
6026
6027         netif_device_attach(netdev);
6028 }
6029
6030 static struct pci_error_handlers ixgbe_err_handler = {
6031         .error_detected = ixgbe_io_error_detected,
6032         .slot_reset = ixgbe_io_slot_reset,
6033         .resume = ixgbe_io_resume,
6034 };
6035
6036 static struct pci_driver ixgbe_driver = {
6037         .name     = ixgbe_driver_name,
6038         .id_table = ixgbe_pci_tbl,
6039         .probe    = ixgbe_probe,
6040         .remove   = __devexit_p(ixgbe_remove),
6041 #ifdef CONFIG_PM
6042         .suspend  = ixgbe_suspend,
6043         .resume   = ixgbe_resume,
6044 #endif
6045         .shutdown = ixgbe_shutdown,
6046         .err_handler = &ixgbe_err_handler
6047 };
6048
6049 /**
6050  * ixgbe_init_module - Driver Registration Routine
6051  *
6052  * ixgbe_init_module is the first routine called when the driver is
6053  * loaded. All it does is register with the PCI subsystem.
6054  **/
6055 static int __init ixgbe_init_module(void)
6056 {
6057         int ret;
6058         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6059                ixgbe_driver_string, ixgbe_driver_version);
6060
6061         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6062
6063 #ifdef CONFIG_IXGBE_DCA
6064         dca_register_notify(&dca_notifier);
6065 #endif
6066
6067         ret = pci_register_driver(&ixgbe_driver);
6068         return ret;
6069 }
6070
6071 module_init(ixgbe_init_module);
6072
6073 /**
6074  * ixgbe_exit_module - Driver Exit Cleanup Routine
6075  *
6076  * ixgbe_exit_module is called just before the driver is removed
6077  * from memory.
6078  **/
6079 static void __exit ixgbe_exit_module(void)
6080 {
6081 #ifdef CONFIG_IXGBE_DCA
6082         dca_unregister_notify(&dca_notifier);
6083 #endif
6084         pci_unregister_driver(&ixgbe_driver);
6085 }
6086
6087 #ifdef CONFIG_IXGBE_DCA
6088 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6089                             void *p)
6090 {
6091         int ret_val;
6092
6093         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6094                                          __ixgbe_notify_dca);
6095
6096         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6097 }
6098
6099 #endif /* CONFIG_IXGBE_DCA */
6100 #ifdef DEBUG
6101 /**
6102  * ixgbe_get_hw_dev_name - return device name string
6103  * used by hardware layer to print debugging information
6104  **/
6105 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6106 {
6107         struct ixgbe_adapter *adapter = hw->back;
6108         return adapter->netdev->name;
6109 }
6110
6111 #endif
6112 module_exit(ixgbe_exit_module);
6113
6114 /* ixgbe_main.c */