Pileus Git - ~andy/linux/blob - drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47
  48 char ixgbe_driver_name[] = "ixgbe";
  49 static const char ixgbe_driver_string[] =
  50                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  51
  52 #define DRV_VERSION "2.0.44-k2"
  53 const char ixgbe_driver_version[] = DRV_VERSION;
  54 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  55
  56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  57         [board_82598] = &ixgbe_82598_info,
  58         [board_82599] = &ixgbe_82599_info,
  59 };
  60
  61 /* ixgbe_pci_tbl - PCI Device ID Table
  62  *
  63  * Wildcard entries (PCI_ANY_ID) should come last
  64  * Last entry must be all 0s
  65  *
  66  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  67  *   Class, Class Mask, private data (not used) }
  68  */
  69 static struct pci_device_id ixgbe_pci_tbl[] = {
  70         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  71          board_82598 },
  72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  73          board_82598 },
  74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  75          board_82598 },
  76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  77          board_82598 },
  78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  79          board_82598 },
  80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  81          board_82598 },
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  93          board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  95          board_82599 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  97          board_82599 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  99          board_82599 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 101          board_82599 },
 102
 103         /* required last entry */
 104         {0, }
 105 };
 106 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 107
 108 #ifdef CONFIG_IXGBE_DCA
 109 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 110                             void *p);
 111 static struct notifier_block dca_notifier = {
 112         .notifier_call = ixgbe_notify_dca,
 113         .next          = NULL,
 114         .priority      = 0
 115 };
 116 #endif
 117
 118 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 119 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 120 MODULE_LICENSE("GPL");
 121 MODULE_VERSION(DRV_VERSION);
 122
 123 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 124
 125 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 126 {
 127         u32 ctrl_ext;
 128
 129         /* Let firmware take over control of h/w */
 130         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 131         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 132                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 133 }
 134
 135 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 136 {
 137         u32 ctrl_ext;
 138
 139         /* Let firmware know the driver has taken over */
 140         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 141         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 142                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 143 }
 144
 145 /*
 146  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 147  * @adapter: pointer to adapter struct
 148  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 149  * @queue: queue to map the corresponding interrupt to
 150  * @msix_vector: the vector to map to the corresponding queue
 151  *
 152  */
 153 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 154                            u8 queue, u8 msix_vector)
 155 {
 156         u32 ivar, index;
 157         struct ixgbe_hw *hw = &adapter->hw;
 158         switch (hw->mac.type) {
 159         case ixgbe_mac_82598EB:
 160                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 161                 if (direction == -1)
 162                         direction = 0;
 163                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 164                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 165                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 166                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 167                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 168                 break;
 169         case ixgbe_mac_82599EB:
 170                 if (direction == -1) {
 171                         /* other causes */
 172                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 173                         index = ((queue & 1) * 8);
 174                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 175                         ivar &= ~(0xFF << index);
 176                         ivar |= (msix_vector << index);
 177                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 178                         break;
 179                 } else {
 180                         /* tx or rx causes */
 181                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 182                         index = ((16 * (queue & 1)) + (8 * direction));
 183                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 184                         ivar &= ~(0xFF << index);
 185                         ivar |= (msix_vector << index);
 186                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 187                         break;
 188                 }
 189         default:
 190                 break;
 191         }
 192 }
 193
 194 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 195                                           u64 qmask)
 196 {
 197         u32 mask;
 198
 199         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 200                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 201                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 202         } else {
 203                 mask = (qmask & 0xFFFFFFFF);
 204                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 205                 mask = (qmask >> 32);
 206                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 207         }
 208 }
 209
 210 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 211                                              struct ixgbe_tx_buffer
 212                                              *tx_buffer_info)
 213 {
 214         tx_buffer_info->dma = 0;
 215         if (tx_buffer_info->skb) {
 216                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 217                               DMA_TO_DEVICE);
 218                 dev_kfree_skb_any(tx_buffer_info->skb);
 219                 tx_buffer_info->skb = NULL;
 220         }
 221         tx_buffer_info->time_stamp = 0;
 222         /* tx_buffer_info must be completely set up in the transmit path */
 223 }
 224
 225 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 226                                        struct ixgbe_ring *tx_ring,
 227                                        unsigned int eop)
 228 {
 229         struct ixgbe_hw *hw = &adapter->hw;
 230
 231         /* Detect a transmit hang in hardware, this serializes the
 232          * check with the clearing of time_stamp and movement of eop */
 233         adapter->detect_tx_hung = false;
 234         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 235             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 236             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 237                 /* detected Tx unit hang */
 238                 union ixgbe_adv_tx_desc *tx_desc;
 239                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 240                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 241                         "  Tx Queue             <%d>\n"
 242                         "  TDH, TDT             <%x>, <%x>\n"
 243                         "  next_to_use          <%x>\n"
 244                         "  next_to_clean        <%x>\n"
 245                         "tx_buffer_info[next_to_clean]\n"
 246                         "  time_stamp           <%lx>\n"
 247                         "  jiffies              <%lx>\n",
 248                         tx_ring->queue_index,
 249                         IXGBE_READ_REG(hw, tx_ring->head),
 250                         IXGBE_READ_REG(hw, tx_ring->tail),
 251                         tx_ring->next_to_use, eop,
 252                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 253                 return true;
 254         }
 255
 256         return false;
 257 }
 258
 259 #define IXGBE_MAX_TXD_PWR       14
 260 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 261
 262 /* Tx Descriptors needed, worst case */
 263 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 264                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 265 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 266         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 267
 268 static void ixgbe_tx_timeout(struct net_device *netdev);
 269
 270 /**
 271  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 272  * @q_vector: structure containing interrupt and ring information
 273  * @tx_ring: tx ring to clean
 274  **/
 275 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 276                                struct ixgbe_ring *tx_ring)
 277 {
 278         struct ixgbe_adapter *adapter = q_vector->adapter;
 279         struct net_device *netdev = adapter->netdev;
 280         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 281         struct ixgbe_tx_buffer *tx_buffer_info;
 282         unsigned int i, eop, count = 0;
 283         unsigned int total_bytes = 0, total_packets = 0;
 284
 285         i = tx_ring->next_to_clean;
 286         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 287         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 288
 289         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 290                (count < tx_ring->work_limit)) {
 291                 bool cleaned = false;
 292                 for ( ; !cleaned; count++) {
 293                         struct sk_buff *skb;
 294                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 295                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 296                         cleaned = (i == eop);
 297                         skb = tx_buffer_info->skb;
 298
 299                         if (cleaned && skb) {
 300                                 unsigned int segs, bytecount;
 301                                 unsigned int hlen = skb_headlen(skb);
 302
 303                                 /* gso_segs is currently only valid for tcp */
 304                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 305 #ifdef IXGBE_FCOE
 306                                 /* adjust for FCoE Sequence Offload */
 307                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 308                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 309                                     skb_is_gso(skb)) {
 310                                         hlen = skb_transport_offset(skb) +
 311                                                 sizeof(struct fc_frame_header) +
 312                                                 sizeof(struct fcoe_crc_eof);
 313                                         segs = DIV_ROUND_UP(skb->len - hlen,
 314                                                 skb_shinfo(skb)->gso_size);
 315                                 }
 316 #endif /* IXGBE_FCOE */
 317                                 /* multiply data chunks by size of headers */
 318                                 bytecount = ((segs - 1) * hlen) + skb->len;
 319                                 total_packets += segs;
 320                                 total_bytes += bytecount;
 321                         }
 322
 323                         ixgbe_unmap_and_free_tx_resource(adapter,
 324                                                          tx_buffer_info);
 325
 326                         tx_desc->wb.status = 0;
 327
 328                         i++;
 329                         if (i == tx_ring->count)
 330                                 i = 0;
 331                 }
 332
 333                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 334                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 335         }
 336
 337         tx_ring->next_to_clean = i;
 338
 339 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 340         if (unlikely(count && netif_carrier_ok(netdev) &&
 341                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 342                 /* Make sure that anybody stopping the queue after this
 343                  * sees the new next_to_clean.
 344                  */
 345                 smp_mb();
 346                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 347                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 348                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 349                         ++adapter->restart_queue;
 350                 }
 351         }
 352
 353         if (adapter->detect_tx_hung) {
 354                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 355                         /* schedule immediate reset if we believe we hung */
 356                         DPRINTK(PROBE, INFO,
 357                                 "tx hang %d detected, resetting adapter\n",
 358                                 adapter->tx_timeout_count + 1);
 359                         ixgbe_tx_timeout(adapter->netdev);
 360                 }
 361         }
 362
 363         /* re-arm the interrupt */
 364         if (count >= tx_ring->work_limit)
 365                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 366
 367         tx_ring->total_bytes += total_bytes;
 368         tx_ring->total_packets += total_packets;
 369         tx_ring->stats.packets += total_packets;
 370         tx_ring->stats.bytes += total_bytes;
 371         adapter->net_stats.tx_bytes += total_bytes;
 372         adapter->net_stats.tx_packets += total_packets;
 373         return (count < tx_ring->work_limit);
 374 }
 375
 376 #ifdef CONFIG_IXGBE_DCA
 377 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 378                                 struct ixgbe_ring *rx_ring)
 379 {
 380         u32 rxctrl;
 381         int cpu = get_cpu();
 382         int q = rx_ring - adapter->rx_ring;
 383
 384         if (rx_ring->cpu != cpu) {
 385                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 386                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 387                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 388                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 389                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 390                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 391                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 392                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 393                 }
 394                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 395                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 396                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 397                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 398                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 399                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 400                 rx_ring->cpu = cpu;
 401         }
 402         put_cpu();
 403 }
 404
 405 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 406                                 struct ixgbe_ring *tx_ring)
 407 {
 408         u32 txctrl;
 409         int cpu = get_cpu();
 410         int q = tx_ring - adapter->tx_ring;
 411
 412         if (tx_ring->cpu != cpu) {
 413                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 414                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 415                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 416                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 417                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 418                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 419                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 420                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 421                 }
 422                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 423                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 424                 tx_ring->cpu = cpu;
 425         }
 426         put_cpu();
 427 }
 428
 429 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 430 {
 431         int i;
 432
 433         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 434                 return;
 435
 436         /* always use CB2 mode, difference is masked in the CB driver */
 437         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 438
 439         for (i = 0; i < adapter->num_tx_queues; i++) {
 440                 adapter->tx_ring[i].cpu = -1;
 441                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 442         }
 443         for (i = 0; i < adapter->num_rx_queues; i++) {
 444                 adapter->rx_ring[i].cpu = -1;
 445                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 446         }
 447 }
 448
 449 static int __ixgbe_notify_dca(struct device *dev, void *data)
 450 {
 451         struct net_device *netdev = dev_get_drvdata(dev);
 452         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 453         unsigned long event = *(unsigned long *)data;
 454
 455         switch (event) {
 456         case DCA_PROVIDER_ADD:
 457                 /* if we're already enabled, don't do it again */
 458                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 459                         break;
 460                 if (dca_add_requester(dev) == 0) {
 461                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 462                         ixgbe_setup_dca(adapter);
 463                         break;
 464                 }
 465                 /* Fall Through since DCA is disabled. */
 466         case DCA_PROVIDER_REMOVE:
 467                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 468                         dca_remove_requester(dev);
 469                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 470                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 471                 }
 472                 break;
 473         }
 474
 475         return 0;
 476 }
 477
 478 #endif /* CONFIG_IXGBE_DCA */
 479 /**
 480  * ixgbe_receive_skb - Send a completed packet up the stack
 481  * @adapter: board private structure
 482  * @skb: packet to send up
 483  * @status: hardware indication of status of receive
 484  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 485  * @rx_desc: rx descriptor
 486  **/
 487 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 488                               struct sk_buff *skb, u8 status,
 489                               struct ixgbe_ring *ring,
 490                               union ixgbe_adv_rx_desc *rx_desc)
 491 {
 492         struct ixgbe_adapter *adapter = q_vector->adapter;
 493         struct napi_struct *napi = &q_vector->napi;
 494         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 495         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 496
 497         skb_record_rx_queue(skb, ring->queue_index);
 498         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 499                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 500                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 501                 else
 502                         napi_gro_receive(napi, skb);
 503         } else {
 504                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 505                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 506                 else
 507                         netif_rx(skb);
 508         }
 509 }
 510
 511 /**
 512  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 513  * @adapter: address of board private structure
 514  * @status_err: hardware indication of status of receive
 515  * @skb: skb currently being received and modified
 516  **/
 517 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 518                                      union ixgbe_adv_rx_desc *rx_desc,
 519                                      struct sk_buff *skb)
 520 {
 521         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 522
 523         skb->ip_summed = CHECKSUM_NONE;
 524
 525         /* Rx csum disabled */
 526         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 527                 return;
 528
 529         /* if IP and error */
 530         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 531             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 532                 adapter->hw_csum_rx_error++;
 533                 return;
 534         }
 535
 536         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 537                 return;
 538
 539         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 540                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 541
 542                 /*
 543                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 544                  * checksum errors.
 545                  */
 546                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 547                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 548                         return;
 549
 550                 adapter->hw_csum_rx_error++;
 551                 return;
 552         }
 553
 554         /* It must be a TCP or UDP packet with a valid checksum */
 555         skb->ip_summed = CHECKSUM_UNNECESSARY;
 556         adapter->hw_csum_rx_good++;
 557 }
 558
 559 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 560                                          struct ixgbe_ring *rx_ring, u32 val)
 561 {
 562         /*
 563          * Force memory writes to complete before letting h/w
 564          * know there are new descriptors to fetch.  (Only
 565          * applicable for weak-ordered memory model archs,
 566          * such as IA-64).
 567          */
 568         wmb();
 569         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 570 }
 571
 572 /**
 573  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 574  * @adapter: address of board private structure
 575  **/
 576 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 577                                    struct ixgbe_ring *rx_ring,
 578                                    int cleaned_count)
 579 {
 580         struct pci_dev *pdev = adapter->pdev;
 581         union ixgbe_adv_rx_desc *rx_desc;
 582         struct ixgbe_rx_buffer *bi;
 583         unsigned int i;
 584
 585         i = rx_ring->next_to_use;
 586         bi = &rx_ring->rx_buffer_info[i];
 587
 588         while (cleaned_count--) {
 589                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 590
 591                 if (!bi->page_dma &&
 592                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 593                         if (!bi->page) {
 594                                 bi->page = alloc_page(GFP_ATOMIC);
 595                                 if (!bi->page) {
 596                                         adapter->alloc_rx_page_failed++;
 597                                         goto no_buffers;
 598                                 }
 599                                 bi->page_offset = 0;
 600                         } else {
 601                                 /* use a half page if we're re-using */
 602                                 bi->page_offset ^= (PAGE_SIZE / 2);
 603                         }
 604
 605                         bi->page_dma = pci_map_page(pdev, bi->page,
 606                                                     bi->page_offset,
 607                                                     (PAGE_SIZE / 2),
 608                                                     PCI_DMA_FROMDEVICE);
 609                 }
 610
 611                 if (!bi->skb) {
 612                         struct sk_buff *skb;
 613                         skb = netdev_alloc_skb(adapter->netdev,
 614                                                (rx_ring->rx_buf_len +
 615                                                 NET_IP_ALIGN));
 616
 617                         if (!skb) {
 618                                 adapter->alloc_rx_buff_failed++;
 619                                 goto no_buffers;
 620                         }
 621
 622                         /*
 623                          * Make buffer alignment 2 beyond a 16 byte boundary
 624                          * this will result in a 16 byte aligned IP header after
 625                          * the 14 byte MAC header is removed
 626                          */
 627                         skb_reserve(skb, NET_IP_ALIGN);
 628
 629                         bi->skb = skb;
 630                         bi->dma = pci_map_single(pdev, skb->data,
 631                                                  rx_ring->rx_buf_len,
 632                                                  PCI_DMA_FROMDEVICE);
 633                 }
 634                 /* Refresh the desc even if buffer_addrs didn't change because
 635                  * each write-back erases this info. */
 636                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 637                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 638                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 639                 } else {
 640                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 641                 }
 642
 643                 i++;
 644                 if (i == rx_ring->count)
 645                         i = 0;
 646                 bi = &rx_ring->rx_buffer_info[i];
 647         }
 648
 649 no_buffers:
 650         if (rx_ring->next_to_use != i) {
 651                 rx_ring->next_to_use = i;
 652                 if (i-- == 0)
 653                         i = (rx_ring->count - 1);
 654
 655                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 656         }
 657 }
 658
 659 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 660 {
 661         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 662 }
 663
 664 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 665 {
 666         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 667 }
 668
 669 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 670 {
 671         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 672                 IXGBE_RXDADV_RSCCNT_MASK) >>
 673                 IXGBE_RXDADV_RSCCNT_SHIFT;
 674 }
 675
 676 /**
 677  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 678  * @skb: pointer to the last skb in the rsc queue
 679  *
 680  * This function changes a queue full of hw rsc buffers into a completed
 681  * packet.  It uses the ->prev pointers to find the first packet and then
 682  * turns it into the frag list owner.
 683  **/
 684 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 685 {
 686         unsigned int frag_list_size = 0;
 687
 688         while (skb->prev) {
 689                 struct sk_buff *prev = skb->prev;
 690                 frag_list_size += skb->len;
 691                 skb->prev = NULL;
 692                 skb = prev;
 693         }
 694
 695         skb_shinfo(skb)->frag_list = skb->next;
 696         skb->next = NULL;
 697         skb->len += frag_list_size;
 698         skb->data_len += frag_list_size;
 699         skb->truesize += frag_list_size;
 700         return skb;
 701 }
 702
 703 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 704                                struct ixgbe_ring *rx_ring,
 705                                int *work_done, int work_to_do)
 706 {
 707         struct ixgbe_adapter *adapter = q_vector->adapter;
 708         struct pci_dev *pdev = adapter->pdev;
 709         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 710         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 711         struct sk_buff *skb;
 712         unsigned int i, rsc_count = 0;
 713         u32 len, staterr;
 714         u16 hdr_info;
 715         bool cleaned = false;
 716         int cleaned_count = 0;
 717         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 718 #ifdef IXGBE_FCOE
 719         int ddp_bytes = 0;
 720 #endif /* IXGBE_FCOE */
 721
 722         i = rx_ring->next_to_clean;
 723         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 724         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 725         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 726
 727         while (staterr & IXGBE_RXD_STAT_DD) {
 728                 u32 upper_len = 0;
 729                 if (*work_done >= work_to_do)
 730                         break;
 731                 (*work_done)++;
 732
 733                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 734                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 735                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 736                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 737                         if (hdr_info & IXGBE_RXDADV_SPH)
 738                                 adapter->rx_hdr_split++;
 739                         if (len > IXGBE_RX_HDR_SIZE)
 740                                 len = IXGBE_RX_HDR_SIZE;
 741                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 742                 } else {
 743                         len = le16_to_cpu(rx_desc->wb.upper.length);
 744                 }
 745
 746                 cleaned = true;
 747                 skb = rx_buffer_info->skb;
 748                 prefetch(skb->data - NET_IP_ALIGN);
 749                 rx_buffer_info->skb = NULL;
 750
 751                 if (rx_buffer_info->dma) {
 752                         pci_unmap_single(pdev, rx_buffer_info->dma,
 753                                          rx_ring->rx_buf_len,
 754                                          PCI_DMA_FROMDEVICE);
 755                         rx_buffer_info->dma = 0;
 756                         skb_put(skb, len);
 757                 }
 758
 759                 if (upper_len) {
 760                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 761                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 762                         rx_buffer_info->page_dma = 0;
 763                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 764                                            rx_buffer_info->page,
 765                                            rx_buffer_info->page_offset,
 766                                            upper_len);
 767
 768                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 769                             (page_count(rx_buffer_info->page) != 1))
 770                                 rx_buffer_info->page = NULL;
 771                         else
 772                                 get_page(rx_buffer_info->page);
 773
 774                         skb->len += upper_len;
 775                         skb->data_len += upper_len;
 776                         skb->truesize += upper_len;
 777                 }
 778
 779                 i++;
 780                 if (i == rx_ring->count)
 781                         i = 0;
 782
 783                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 784                 prefetch(next_rxd);
 785                 cleaned_count++;
 786
 787                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 788                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 789
 790                 if (rsc_count) {
 791                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 792                                      IXGBE_RXDADV_NEXTP_SHIFT;
 793                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 794                         rx_ring->rsc_count += (rsc_count - 1);
 795                 } else {
 796                         next_buffer = &rx_ring->rx_buffer_info[i];
 797                 }
 798
 799                 if (staterr & IXGBE_RXD_STAT_EOP) {
 800                         if (skb->prev)
 801                                 skb = ixgbe_transform_rsc_queue(skb);
 802                         rx_ring->stats.packets++;
 803                         rx_ring->stats.bytes += skb->len;
 804                 } else {
 805                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 806                                 rx_buffer_info->skb = next_buffer->skb;
 807                                 rx_buffer_info->dma = next_buffer->dma;
 808                                 next_buffer->skb = skb;
 809                                 next_buffer->dma = 0;
 810                         } else {
 811                                 skb->next = next_buffer->skb;
 812                                 skb->next->prev = skb;
 813                         }
 814                         adapter->non_eop_descs++;
 815                         goto next_desc;
 816                 }
 817
 818                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 819                         dev_kfree_skb_irq(skb);
 820                         goto next_desc;
 821                 }
 822
 823                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 824
 825                 /* probably a little skewed due to removing CRC */
 826                 total_rx_bytes += skb->len;
 827                 total_rx_packets++;
 828
 829                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 830 #ifdef IXGBE_FCOE
 831                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 832                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 833                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 834                         if (!ddp_bytes)
 835                                 goto next_desc;
 836                 }
 837 #endif /* IXGBE_FCOE */
 838                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 839
 840 next_desc:
 841                 rx_desc->wb.upper.status_error = 0;
 842
 843                 /* return some buffers to hardware, one at a time is too slow */
 844                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 845                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 846                         cleaned_count = 0;
 847                 }
 848
 849                 /* use prefetched values */
 850                 rx_desc = next_rxd;
 851                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 852
 853                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 854         }
 855
 856         rx_ring->next_to_clean = i;
 857         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 858
 859         if (cleaned_count)
 860                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 861
 862 #ifdef IXGBE_FCOE
 863         /* include DDPed FCoE data */
 864         if (ddp_bytes > 0) {
 865                 unsigned int mss;
 866
 867                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 868                         sizeof(struct fc_frame_header) -
 869                         sizeof(struct fcoe_crc_eof);
 870                 if (mss > 512)
 871                         mss &= ~511;
 872                 total_rx_bytes += ddp_bytes;
 873                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 874         }
 875 #endif /* IXGBE_FCOE */
 876
 877         rx_ring->total_packets += total_rx_packets;
 878         rx_ring->total_bytes += total_rx_bytes;
 879         adapter->net_stats.rx_bytes += total_rx_bytes;
 880         adapter->net_stats.rx_packets += total_rx_packets;
 881
 882         return cleaned;
 883 }
 884
 885 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 886 /**
 887  * ixgbe_configure_msix - Configure MSI-X hardware
 888  * @adapter: board private structure
 889  *
 890  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 891  * interrupts.
 892  **/
 893 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 894 {
 895         struct ixgbe_q_vector *q_vector;
 896         int i, j, q_vectors, v_idx, r_idx;
 897         u32 mask;
 898
 899         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 900
 901         /*
 902          * Populate the IVAR table and set the ITR values to the
 903          * corresponding register.
 904          */
 905         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 906                 q_vector = adapter->q_vector[v_idx];
 907                 /* XXX for_each_bit(...) */
 908                 r_idx = find_first_bit(q_vector->rxr_idx,
 909                                        adapter->num_rx_queues);
 910
 911                 for (i = 0; i < q_vector->rxr_count; i++) {
 912                         j = adapter->rx_ring[r_idx].reg_idx;
 913                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 914                         r_idx = find_next_bit(q_vector->rxr_idx,
 915                                               adapter->num_rx_queues,
 916                                               r_idx + 1);
 917                 }
 918                 r_idx = find_first_bit(q_vector->txr_idx,
 919                                        adapter->num_tx_queues);
 920
 921                 for (i = 0; i < q_vector->txr_count; i++) {
 922                         j = adapter->tx_ring[r_idx].reg_idx;
 923                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 924                         r_idx = find_next_bit(q_vector->txr_idx,
 925                                               adapter->num_tx_queues,
 926                                               r_idx + 1);
 927                 }
 928
 929                 if (q_vector->txr_count && !q_vector->rxr_count)
 930                         /* tx only */
 931                         q_vector->eitr = adapter->tx_eitr_param;
 932                 else if (q_vector->rxr_count)
 933                         /* rx or mixed */
 934                         q_vector->eitr = adapter->rx_eitr_param;
 935
 936                 ixgbe_write_eitr(q_vector);
 937         }
 938
 939         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 940                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 941                                v_idx);
 942         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 943                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 944         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 945
 946         /* set up to autoclear timer, and the vectors */
 947         mask = IXGBE_EIMS_ENABLE_MASK;
 948         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 949         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 950 }
 951
 952 enum latency_range {
 953         lowest_latency = 0,
 954         low_latency = 1,
 955         bulk_latency = 2,
 956         latency_invalid = 255
 957 };
 958
 959 /**
 960  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 961  * @adapter: pointer to adapter
 962  * @eitr: eitr setting (ints per sec) to give last timeslice
 963  * @itr_setting: current throttle rate in ints/second
 964  * @packets: the number of packets during this measurement interval
 965  * @bytes: the number of bytes during this measurement interval
 966  *
 967  *      Stores a new ITR value based on packets and byte
 968  *      counts during the last interrupt.  The advantage of per interrupt
 969  *      computation is faster updates and more accurate ITR for the current
 970  *      traffic pattern.  Constants in this function were computed
 971  *      based on theoretical maximum wire speed and thresholds were set based
 972  *      on testing data as well as attempting to minimize response time
 973  *      while increasing bulk throughput.
 974  *      this functionality is controlled by the InterruptThrottleRate module
 975  *      parameter (see ixgbe_param.c)
 976  **/
 977 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 978                            u32 eitr, u8 itr_setting,
 979                            int packets, int bytes)
 980 {
 981         unsigned int retval = itr_setting;
 982         u32 timepassed_us;
 983         u64 bytes_perint;
 984
 985         if (packets == 0)
 986                 goto update_itr_done;
 987
 988
 989         /* simple throttlerate management
 990          *    0-20MB/s lowest (100000 ints/s)
 991          *   20-100MB/s low   (20000 ints/s)
 992          *  100-1249MB/s bulk (8000 ints/s)
 993          */
 994         /* what was last interrupt timeslice? */
 995         timepassed_us = 1000000/eitr;
 996         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 997
 998         switch (itr_setting) {
 999         case lowest_latency:
1000                 if (bytes_perint > adapter->eitr_low)
1001                         retval = low_latency;
1002                 break;
1003         case low_latency:
1004                 if (bytes_perint > adapter->eitr_high)
1005                         retval = bulk_latency;
1006                 else if (bytes_perint <= adapter->eitr_low)
1007                         retval = lowest_latency;
1008                 break;
1009         case bulk_latency:
1010                 if (bytes_perint <= adapter->eitr_high)
1011                         retval = low_latency;
1012                 break;
1013         }
1014
1015 update_itr_done:
1016         return retval;
1017 }
1018
1019 /**
1020  * ixgbe_write_eitr - write EITR register in hardware specific way
1021  * @q_vector: structure containing interrupt and ring information
1022  *
1023  * This function is made to be called by ethtool and by the driver
1024  * when it needs to update EITR registers at runtime.  Hardware
1025  * specific quirks/differences are taken care of here.
1026  */
1027 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1028 {
1029         struct ixgbe_adapter *adapter = q_vector->adapter;
1030         struct ixgbe_hw *hw = &adapter->hw;
1031         int v_idx = q_vector->v_idx;
1032         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1033
1034         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1035                 /* must write high and low 16 bits to reset counter */
1036                 itr_reg |= (itr_reg << 16);
1037         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1038                 /*
1039                  * set the WDIS bit to not clear the timer bits and cause an
1040                  * immediate assertion of the interrupt
1041                  */
1042                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1043         }
1044         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1045 }
1046
1047 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1048 {
1049         struct ixgbe_adapter *adapter = q_vector->adapter;
1050         u32 new_itr;
1051         u8 current_itr, ret_itr;
1052         int i, r_idx;
1053         struct ixgbe_ring *rx_ring, *tx_ring;
1054
1055         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1056         for (i = 0; i < q_vector->txr_count; i++) {
1057                 tx_ring = &(adapter->tx_ring[r_idx]);
1058                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1059                                            q_vector->tx_itr,
1060                                            tx_ring->total_packets,
1061                                            tx_ring->total_bytes);
1062                 /* if the result for this queue would decrease interrupt
1063                  * rate for this vector then use that result */
1064                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1065                                     q_vector->tx_itr - 1 : ret_itr);
1066                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1067                                       r_idx + 1);
1068         }
1069
1070         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1071         for (i = 0; i < q_vector->rxr_count; i++) {
1072                 rx_ring = &(adapter->rx_ring[r_idx]);
1073                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1074                                            q_vector->rx_itr,
1075                                            rx_ring->total_packets,
1076                                            rx_ring->total_bytes);
1077                 /* if the result for this queue would decrease interrupt
1078                  * rate for this vector then use that result */
1079                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1080                                     q_vector->rx_itr - 1 : ret_itr);
1081                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1082                                       r_idx + 1);
1083         }
1084
1085         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1086
1087         switch (current_itr) {
1088         /* counts and packets in update_itr are dependent on these numbers */
1089         case lowest_latency:
1090                 new_itr = 100000;
1091                 break;
1092         case low_latency:
1093                 new_itr = 20000; /* aka hwitr = ~200 */
1094                 break;
1095         case bulk_latency:
1096         default:
1097                 new_itr = 8000;
1098                 break;
1099         }
1100
1101         if (new_itr != q_vector->eitr) {
1102                 /* do an exponential smoothing */
1103                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1104
1105                 /* save the algorithm value here, not the smoothed one */
1106                 q_vector->eitr = new_itr;
1107
1108                 ixgbe_write_eitr(q_vector);
1109         }
1110
1111         return;
1112 }
1113
1114 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1115 {
1116         struct ixgbe_hw *hw = &adapter->hw;
1117
1118         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1119             (eicr & IXGBE_EICR_GPI_SDP1)) {
1120                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1121                 /* write to clear the interrupt */
1122                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1123         }
1124 }
1125
1126 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1127 {
1128         struct ixgbe_hw *hw = &adapter->hw;
1129
1130         if (eicr & IXGBE_EICR_GPI_SDP1) {
1131                 /* Clear the interrupt */
1132                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1133                 schedule_work(&adapter->multispeed_fiber_task);
1134         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1135                 /* Clear the interrupt */
1136                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1137                 schedule_work(&adapter->sfp_config_module_task);
1138         } else {
1139                 /* Interrupt isn't for us... */
1140                 return;
1141         }
1142 }
1143
1144 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1145 {
1146         struct ixgbe_hw *hw = &adapter->hw;
1147
1148         adapter->lsc_int++;
1149         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1150         adapter->link_check_timeout = jiffies;
1151         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1152                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1153                 schedule_work(&adapter->watchdog_task);
1154         }
1155 }
1156
1157 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1158 {
1159         struct net_device *netdev = data;
1160         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1161         struct ixgbe_hw *hw = &adapter->hw;
1162         u32 eicr;
1163
1164         /*
1165          * Workaround for Silicon errata.  Use clear-by-write instead
1166          * of clear-by-read.  Reading with EICS will return the
1167          * interrupt causes without clearing, which later be done
1168          * with the write to EICR.
1169          */
1170         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1171         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1172
1173         if (eicr & IXGBE_EICR_LSC)
1174                 ixgbe_check_lsc(adapter);
1175
1176         if (hw->mac.type == ixgbe_mac_82598EB)
1177                 ixgbe_check_fan_failure(adapter, eicr);
1178
1179         if (hw->mac.type == ixgbe_mac_82599EB) {
1180                 ixgbe_check_sfp_event(adapter, eicr);
1181
1182                 /* Handle Flow Director Full threshold interrupt */
1183                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1184                         int i;
1185                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1186                         /* Disable transmits before FDIR Re-initialization */
1187                         netif_tx_stop_all_queues(netdev);
1188                         for (i = 0; i < adapter->num_tx_queues; i++) {
1189                                 struct ixgbe_ring *tx_ring =
1190                                                            &adapter->tx_ring[i];
1191                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1192                                                        &tx_ring->reinit_state))
1193                                         schedule_work(&adapter->fdir_reinit_task);
1194                         }
1195                 }
1196         }
1197         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1198                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1199
1200         return IRQ_HANDLED;
1201 }
1202
1203 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1204                                            u64 qmask)
1205 {
1206         u32 mask;
1207
1208         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1209                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1210                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1211         } else {
1212                 mask = (qmask & 0xFFFFFFFF);
1213                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1214                 mask = (qmask >> 32);
1215                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1216         }
1217         /* skip the flush */
1218 }
1219
1220 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1221                                             u64 qmask)
1222 {
1223         u32 mask;
1224
1225         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1226                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1227                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1228         } else {
1229                 mask = (qmask & 0xFFFFFFFF);
1230                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1231                 mask = (qmask >> 32);
1232                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1233         }
1234         /* skip the flush */
1235 }
1236
1237 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1238 {
1239         struct ixgbe_q_vector *q_vector = data;
1240         struct ixgbe_adapter  *adapter = q_vector->adapter;
1241         struct ixgbe_ring     *tx_ring;
1242         int i, r_idx;
1243
1244         if (!q_vector->txr_count)
1245                 return IRQ_HANDLED;
1246
1247         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1248         for (i = 0; i < q_vector->txr_count; i++) {
1249                 tx_ring = &(adapter->tx_ring[r_idx]);
1250                 tx_ring->total_bytes = 0;
1251                 tx_ring->total_packets = 0;
1252                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1253                                       r_idx + 1);
1254         }
1255
1256         /* disable interrupts on this vector only */
1257         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1258         napi_schedule(&q_vector->napi);
1259
1260         return IRQ_HANDLED;
1261 }
1262
1263 /**
1264  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1265  * @irq: unused
1266  * @data: pointer to our q_vector struct for this interrupt vector
1267  **/
1268 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1269 {
1270         struct ixgbe_q_vector *q_vector = data;
1271         struct ixgbe_adapter  *adapter = q_vector->adapter;
1272         struct ixgbe_ring  *rx_ring;
1273         int r_idx;
1274         int i;
1275
1276         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1277         for (i = 0;  i < q_vector->rxr_count; i++) {
1278                 rx_ring = &(adapter->rx_ring[r_idx]);
1279                 rx_ring->total_bytes = 0;
1280                 rx_ring->total_packets = 0;
1281                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1282                                       r_idx + 1);
1283         }
1284
1285         if (!q_vector->rxr_count)
1286                 return IRQ_HANDLED;
1287
1288         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1289         rx_ring = &(adapter->rx_ring[r_idx]);
1290         /* disable interrupts on this vector only */
1291         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1292         napi_schedule(&q_vector->napi);
1293
1294         return IRQ_HANDLED;
1295 }
1296
1297 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1298 {
1299         struct ixgbe_q_vector *q_vector = data;
1300         struct ixgbe_adapter  *adapter = q_vector->adapter;
1301         struct ixgbe_ring  *ring;
1302         int r_idx;
1303         int i;
1304
1305         if (!q_vector->txr_count && !q_vector->rxr_count)
1306                 return IRQ_HANDLED;
1307
1308         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1309         for (i = 0; i < q_vector->txr_count; i++) {
1310                 ring = &(adapter->tx_ring[r_idx]);
1311                 ring->total_bytes = 0;
1312                 ring->total_packets = 0;
1313                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1314                                       r_idx + 1);
1315         }
1316
1317         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1318         for (i = 0; i < q_vector->rxr_count; i++) {
1319                 ring = &(adapter->rx_ring[r_idx]);
1320                 ring->total_bytes = 0;
1321                 ring->total_packets = 0;
1322                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1323                                       r_idx + 1);
1324         }
1325
1326         /* disable interrupts on this vector only */
1327         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1328         napi_schedule(&q_vector->napi);
1329
1330         return IRQ_HANDLED;
1331 }
1332
1333 /**
1334  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1335  * @napi: napi struct with our devices info in it
1336  * @budget: amount of work driver is allowed to do this pass, in packets
1337  *
1338  * This function is optimized for cleaning one queue only on a single
1339  * q_vector!!!
1340  **/
1341 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1342 {
1343         struct ixgbe_q_vector *q_vector =
1344                                container_of(napi, struct ixgbe_q_vector, napi);
1345         struct ixgbe_adapter *adapter = q_vector->adapter;
1346         struct ixgbe_ring *rx_ring = NULL;
1347         int work_done = 0;
1348         long r_idx;
1349
1350         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1351         rx_ring = &(adapter->rx_ring[r_idx]);
1352 #ifdef CONFIG_IXGBE_DCA
1353         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1354                 ixgbe_update_rx_dca(adapter, rx_ring);
1355 #endif
1356
1357         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1358
1359         /* If all Rx work done, exit the polling mode */
1360         if (work_done < budget) {
1361                 napi_complete(napi);
1362                 if (adapter->rx_itr_setting & 1)
1363                         ixgbe_set_itr_msix(q_vector);
1364                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1365                         ixgbe_irq_enable_queues(adapter,
1366                                                 ((u64)1 << q_vector->v_idx));
1367         }
1368
1369         return work_done;
1370 }
1371
1372 /**
1373  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1374  * @napi: napi struct with our devices info in it
1375  * @budget: amount of work driver is allowed to do this pass, in packets
1376  *
1377  * This function will clean more than one rx queue associated with a
1378  * q_vector.
1379  **/
1380 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1381 {
1382         struct ixgbe_q_vector *q_vector =
1383                                container_of(napi, struct ixgbe_q_vector, napi);
1384         struct ixgbe_adapter *adapter = q_vector->adapter;
1385         struct ixgbe_ring *ring = NULL;
1386         int work_done = 0, i;
1387         long r_idx;
1388         bool tx_clean_complete = true;
1389
1390         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1391         for (i = 0; i < q_vector->txr_count; i++) {
1392                 ring = &(adapter->tx_ring[r_idx]);
1393 #ifdef CONFIG_IXGBE_DCA
1394                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1395                         ixgbe_update_tx_dca(adapter, ring);
1396 #endif
1397                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1398                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1399                                       r_idx + 1);
1400         }
1401
1402         /* attempt to distribute budget to each queue fairly, but don't allow
1403          * the budget to go below 1 because we'll exit polling */
1404         budget /= (q_vector->rxr_count ?: 1);
1405         budget = max(budget, 1);
1406         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1407         for (i = 0; i < q_vector->rxr_count; i++) {
1408                 ring = &(adapter->rx_ring[r_idx]);
1409 #ifdef CONFIG_IXGBE_DCA
1410                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1411                         ixgbe_update_rx_dca(adapter, ring);
1412 #endif
1413                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1414                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1415                                       r_idx + 1);
1416         }
1417
1418         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1419         ring = &(adapter->rx_ring[r_idx]);
1420         /* If all Rx work done, exit the polling mode */
1421         if (work_done < budget) {
1422                 napi_complete(napi);
1423                 if (adapter->rx_itr_setting & 1)
1424                         ixgbe_set_itr_msix(q_vector);
1425                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1426                         ixgbe_irq_enable_queues(adapter,
1427                                                 ((u64)1 << q_vector->v_idx));
1428                 return 0;
1429         }
1430
1431         return work_done;
1432 }
1433
1434 /**
1435  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1436  * @napi: napi struct with our devices info in it
1437  * @budget: amount of work driver is allowed to do this pass, in packets
1438  *
1439  * This function is optimized for cleaning one queue only on a single
1440  * q_vector!!!
1441  **/
1442 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1443 {
1444         struct ixgbe_q_vector *q_vector =
1445                                container_of(napi, struct ixgbe_q_vector, napi);
1446         struct ixgbe_adapter *adapter = q_vector->adapter;
1447         struct ixgbe_ring *tx_ring = NULL;
1448         int work_done = 0;
1449         long r_idx;
1450
1451         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1452         tx_ring = &(adapter->tx_ring[r_idx]);
1453 #ifdef CONFIG_IXGBE_DCA
1454         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1455                 ixgbe_update_tx_dca(adapter, tx_ring);
1456 #endif
1457
1458         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1459                 work_done = budget;
1460
1461         /* If all Tx work done, exit the polling mode */
1462         if (work_done < budget) {
1463                 napi_complete(napi);
1464                 if (adapter->tx_itr_setting & 1)
1465                         ixgbe_set_itr_msix(q_vector);
1466                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1467                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1468         }
1469
1470         return work_done;
1471 }
1472
1473 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1474                                      int r_idx)
1475 {
1476         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1477
1478         set_bit(r_idx, q_vector->rxr_idx);
1479         q_vector->rxr_count++;
1480 }
1481
1482 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1483                                      int t_idx)
1484 {
1485         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1486
1487         set_bit(t_idx, q_vector->txr_idx);
1488         q_vector->txr_count++;
1489 }
1490
1491 /**
1492  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1493  * @adapter: board private structure to initialize
1494  * @vectors: allotted vector count for descriptor rings
1495  *
1496  * This function maps descriptor rings to the queue-specific vectors
1497  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1498  * one vector per ring/queue, but on a constrained vector budget, we
1499  * group the rings as "efficiently" as possible.  You would add new
1500  * mapping configurations in here.
1501  **/
1502 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1503                                       int vectors)
1504 {
1505         int v_start = 0;
1506         int rxr_idx = 0, txr_idx = 0;
1507         int rxr_remaining = adapter->num_rx_queues;
1508         int txr_remaining = adapter->num_tx_queues;
1509         int i, j;
1510         int rqpv, tqpv;
1511         int err = 0;
1512
1513         /* No mapping required if MSI-X is disabled. */
1514         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1515                 goto out;
1516
1517         /*
1518          * The ideal configuration...
1519          * We have enough vectors to map one per queue.
1520          */
1521         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1522                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1523                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1524
1525                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1526                         map_vector_to_txq(adapter, v_start, txr_idx);
1527
1528                 goto out;
1529         }
1530
1531         /*
1532          * If we don't have enough vectors for a 1-to-1
1533          * mapping, we'll have to group them so there are
1534          * multiple queues per vector.
1535          */
1536         /* Re-adjusting *qpv takes care of the remainder. */
1537         for (i = v_start; i < vectors; i++) {
1538                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1539                 for (j = 0; j < rqpv; j++) {
1540                         map_vector_to_rxq(adapter, i, rxr_idx);
1541                         rxr_idx++;
1542                         rxr_remaining--;
1543                 }
1544         }
1545         for (i = v_start; i < vectors; i++) {
1546                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1547                 for (j = 0; j < tqpv; j++) {
1548                         map_vector_to_txq(adapter, i, txr_idx);
1549                         txr_idx++;
1550                         txr_remaining--;
1551                 }
1552         }
1553
1554 out:
1555         return err;
1556 }
1557
1558 /**
1559  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1560  * @adapter: board private structure
1561  *
1562  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1563  * interrupts from the kernel.
1564  **/
1565 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1566 {
1567         struct net_device *netdev = adapter->netdev;
1568         irqreturn_t (*handler)(int, void *);
1569         int i, vector, q_vectors, err;
1570         int ri=0, ti=0;
1571
1572         /* Decrement for Other and TCP Timer vectors */
1573         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1574
1575         /* Map the Tx/Rx rings to the vectors we were allotted. */
1576         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1577         if (err)
1578                 goto out;
1579
1580 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1581                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1582                          &ixgbe_msix_clean_many)
1583         for (vector = 0; vector < q_vectors; vector++) {
1584                 handler = SET_HANDLER(adapter->q_vector[vector]);
1585
1586                 if(handler == &ixgbe_msix_clean_rx) {
1587                         sprintf(adapter->name[vector], "%s-%s-%d",
1588                                 netdev->name, "rx", ri++);
1589                 }
1590                 else if(handler == &ixgbe_msix_clean_tx) {
1591                         sprintf(adapter->name[vector], "%s-%s-%d",
1592                                 netdev->name, "tx", ti++);
1593                 }
1594                 else
1595                         sprintf(adapter->name[vector], "%s-%s-%d",
1596                                 netdev->name, "TxRx", vector);
1597
1598                 err = request_irq(adapter->msix_entries[vector].vector,
1599                                   handler, 0, adapter->name[vector],
1600                                   adapter->q_vector[vector]);
1601                 if (err) {
1602                         DPRINTK(PROBE, ERR,
1603                                 "request_irq failed for MSIX interrupt "
1604                                 "Error: %d\n", err);
1605                         goto free_queue_irqs;
1606                 }
1607         }
1608
1609         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1610         err = request_irq(adapter->msix_entries[vector].vector,
1611                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1612         if (err) {
1613                 DPRINTK(PROBE, ERR,
1614                         "request_irq for msix_lsc failed: %d\n", err);
1615                 goto free_queue_irqs;
1616         }
1617
1618         return 0;
1619
1620 free_queue_irqs:
1621         for (i = vector - 1; i >= 0; i--)
1622                 free_irq(adapter->msix_entries[--vector].vector,
1623                          adapter->q_vector[i]);
1624         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1625         pci_disable_msix(adapter->pdev);
1626         kfree(adapter->msix_entries);
1627         adapter->msix_entries = NULL;
1628 out:
1629         return err;
1630 }
1631
1632 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1633 {
1634         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1635         u8 current_itr;
1636         u32 new_itr = q_vector->eitr;
1637         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1638         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1639
1640         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1641                                             q_vector->tx_itr,
1642                                             tx_ring->total_packets,
1643                                             tx_ring->total_bytes);
1644         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1645                                             q_vector->rx_itr,
1646                                             rx_ring->total_packets,
1647                                             rx_ring->total_bytes);
1648
1649         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1650
1651         switch (current_itr) {
1652         /* counts and packets in update_itr are dependent on these numbers */
1653         case lowest_latency:
1654                 new_itr = 100000;
1655                 break;
1656         case low_latency:
1657                 new_itr = 20000; /* aka hwitr = ~200 */
1658                 break;
1659         case bulk_latency:
1660                 new_itr = 8000;
1661                 break;
1662         default:
1663                 break;
1664         }
1665
1666         if (new_itr != q_vector->eitr) {
1667                 /* do an exponential smoothing */
1668                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1669
1670                 /* save the algorithm value here, not the smoothed one */
1671                 q_vector->eitr = new_itr;
1672
1673                 ixgbe_write_eitr(q_vector);
1674         }
1675
1676         return;
1677 }
1678
1679 /**
1680  * ixgbe_irq_enable - Enable default interrupt generation settings
1681  * @adapter: board private structure
1682  **/
1683 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1684 {
1685         u32 mask;
1686
1687         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1688         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1689                 mask |= IXGBE_EIMS_GPI_SDP1;
1690         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1691                 mask |= IXGBE_EIMS_ECC;
1692                 mask |= IXGBE_EIMS_GPI_SDP1;
1693                 mask |= IXGBE_EIMS_GPI_SDP2;
1694         }
1695         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1696             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1697                 mask |= IXGBE_EIMS_FLOW_DIR;
1698
1699         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1700         ixgbe_irq_enable_queues(adapter, ~0);
1701         IXGBE_WRITE_FLUSH(&adapter->hw);
1702 }
1703
1704 /**
1705  * ixgbe_intr - legacy mode Interrupt Handler
1706  * @irq: interrupt number
1707  * @data: pointer to a network interface device structure
1708  **/
1709 static irqreturn_t ixgbe_intr(int irq, void *data)
1710 {
1711         struct net_device *netdev = data;
1712         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713         struct ixgbe_hw *hw = &adapter->hw;
1714         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1715         u32 eicr;
1716
1717         /*
1718          * Workaround for silicon errata.  Mask the interrupts
1719          * before the read of EICR.
1720          */
1721         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1722
1723         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1724          * therefore no explict interrupt disable is necessary */
1725         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1726         if (!eicr) {
1727                 /* shared interrupt alert!
1728                  * make sure interrupts are enabled because the read will
1729                  * have disabled interrupts due to EIAM */
1730                 ixgbe_irq_enable(adapter);
1731                 return IRQ_NONE;        /* Not our interrupt */
1732         }
1733
1734         if (eicr & IXGBE_EICR_LSC)
1735                 ixgbe_check_lsc(adapter);
1736
1737         if (hw->mac.type == ixgbe_mac_82599EB)
1738                 ixgbe_check_sfp_event(adapter, eicr);
1739
1740         ixgbe_check_fan_failure(adapter, eicr);
1741
1742         if (napi_schedule_prep(&(q_vector->napi))) {
1743                 adapter->tx_ring[0].total_packets = 0;
1744                 adapter->tx_ring[0].total_bytes = 0;
1745                 adapter->rx_ring[0].total_packets = 0;
1746                 adapter->rx_ring[0].total_bytes = 0;
1747                 /* would disable interrupts here but EIAM disabled it */
1748                 __napi_schedule(&(q_vector->napi));
1749         }
1750
1751         return IRQ_HANDLED;
1752 }
1753
1754 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1755 {
1756         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1757
1758         for (i = 0; i < q_vectors; i++) {
1759                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1760                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1761                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1762                 q_vector->rxr_count = 0;
1763                 q_vector->txr_count = 0;
1764         }
1765 }
1766
1767 /**
1768  * ixgbe_request_irq - initialize interrupts
1769  * @adapter: board private structure
1770  *
1771  * Attempts to configure interrupts using the best available
1772  * capabilities of the hardware and kernel.
1773  **/
1774 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1775 {
1776         struct net_device *netdev = adapter->netdev;
1777         int err;
1778
1779         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1780                 err = ixgbe_request_msix_irqs(adapter);
1781         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1782                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1783                                   netdev->name, netdev);
1784         } else {
1785                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1786                                   netdev->name, netdev);
1787         }
1788
1789         if (err)
1790                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1791
1792         return err;
1793 }
1794
1795 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1796 {
1797         struct net_device *netdev = adapter->netdev;
1798
1799         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1800                 int i, q_vectors;
1801
1802                 q_vectors = adapter->num_msix_vectors;
1803
1804                 i = q_vectors - 1;
1805                 free_irq(adapter->msix_entries[i].vector, netdev);
1806
1807                 i--;
1808                 for (; i >= 0; i--) {
1809                         free_irq(adapter->msix_entries[i].vector,
1810                                  adapter->q_vector[i]);
1811                 }
1812
1813                 ixgbe_reset_q_vectors(adapter);
1814         } else {
1815                 free_irq(adapter->pdev->irq, netdev);
1816         }
1817 }
1818
1819 /**
1820  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1821  * @adapter: board private structure
1822  **/
1823 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1824 {
1825         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1826                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1827         } else {
1828                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1829                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1830                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1831         }
1832         IXGBE_WRITE_FLUSH(&adapter->hw);
1833         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1834                 int i;
1835                 for (i = 0; i < adapter->num_msix_vectors; i++)
1836                         synchronize_irq(adapter->msix_entries[i].vector);
1837         } else {
1838                 synchronize_irq(adapter->pdev->irq);
1839         }
1840 }
1841
1842 /**
1843  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1844  *
1845  **/
1846 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1847 {
1848         struct ixgbe_hw *hw = &adapter->hw;
1849
1850         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1851                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1852
1853         ixgbe_set_ivar(adapter, 0, 0, 0);
1854         ixgbe_set_ivar(adapter, 1, 0, 0);
1855
1856         map_vector_to_rxq(adapter, 0, 0);
1857         map_vector_to_txq(adapter, 0, 0);
1858
1859         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1860 }
1861
1862 /**
1863  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1864  * @adapter: board private structure
1865  *
1866  * Configure the Tx unit of the MAC after a reset.
1867  **/
1868 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1869 {
1870         u64 tdba;
1871         struct ixgbe_hw *hw = &adapter->hw;
1872         u32 i, j, tdlen, txctrl;
1873
1874         /* Setup the HW Tx Head and Tail descriptor pointers */
1875         for (i = 0; i < adapter->num_tx_queues; i++) {
1876                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1877                 j = ring->reg_idx;
1878                 tdba = ring->dma;
1879                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1880                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1881                                 (tdba & DMA_BIT_MASK(32)));
1882                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1883                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1884                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1885                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1886                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1887                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1888                 /*
1889                  * Disable Tx Head Writeback RO bit, since this hoses
1890                  * bookkeeping if things aren't delivered in order.
1891                  */
1892                 switch (hw->mac.type) {
1893                 case ixgbe_mac_82598EB:
1894                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1895                         break;
1896                 case ixgbe_mac_82599EB:
1897                 default:
1898                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1899                         break;
1900                 }
1901                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1902                 switch (hw->mac.type) {
1903                 case ixgbe_mac_82598EB:
1904                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1905                         break;
1906                 case ixgbe_mac_82599EB:
1907                 default:
1908                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1909                         break;
1910                 }
1911         }
1912         if (hw->mac.type == ixgbe_mac_82599EB) {
1913                 /* We enable 8 traffic classes, DCB only */
1914                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1915                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1916                                         IXGBE_MTQC_8TC_8TQ));
1917         }
1918 }
1919
1920 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1921
1922 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1923                                    struct ixgbe_ring *rx_ring)
1924 {
1925         u32 srrctl;
1926         int index;
1927         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1928
1929         index = rx_ring->reg_idx;
1930         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1931                 unsigned long mask;
1932                 mask = (unsigned long) feature[RING_F_RSS].mask;
1933                 index = index & mask;
1934         }
1935         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1936
1937         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1938         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1939
1940         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1941                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1942
1943         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1944 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1945                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1946 #else
1947                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1948 #endif
1949                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1950         } else {
1951                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1952                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1953                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1954         }
1955
1956         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1957 }
1958
1959 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1960 {
1961         u32 mrqc = 0;
1962         int mask;
1963
1964         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1965                 return mrqc;
1966
1967         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1968 #ifdef CONFIG_IXGBE_DCB
1969                                  | IXGBE_FLAG_DCB_ENABLED
1970 #endif
1971                                 );
1972
1973         switch (mask) {
1974         case (IXGBE_FLAG_RSS_ENABLED):
1975                 mrqc = IXGBE_MRQC_RSSEN;
1976                 break;
1977 #ifdef CONFIG_IXGBE_DCB
1978         case (IXGBE_FLAG_DCB_ENABLED):
1979                 mrqc = IXGBE_MRQC_RT8TCEN;
1980                 break;
1981 #endif /* CONFIG_IXGBE_DCB */
1982         default:
1983                 break;
1984         }
1985
1986         return mrqc;
1987 }
1988
1989 /**
1990  * ixgbe_configure_rscctl - enable RSC for the indicated ring
1991  * @adapter:    address of board private structure
1992  * @index:      index of ring to set
1993  * @rx_buf_len: rx buffer length
1994  **/
1995 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index,
1996                                    int rx_buf_len)
1997 {
1998         struct ixgbe_ring *rx_ring;
1999         struct ixgbe_hw *hw = &adapter->hw;
2000         int j;
2001         u32 rscctrl;
2002
2003         rx_ring = &adapter->rx_ring[index];
2004         j = rx_ring->reg_idx;
2005         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2006         rscctrl |= IXGBE_RSCCTL_RSCEN;
2007         /*
2008          * we must limit the number of descriptors so that the
2009          * total size of max desc * buf_len is not greater
2010          * than 65535
2011          */
2012         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2013 #if (MAX_SKB_FRAGS > 16)
2014                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2015 #elif (MAX_SKB_FRAGS > 8)
2016                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2017 #elif (MAX_SKB_FRAGS > 4)
2018                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2019 #else
2020                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2021 #endif
2022         } else {
2023                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2024                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2025                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2026                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2027                 else
2028                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2029         }
2030         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2031 }
2032
2033 /**
2034  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2035  * @adapter: board private structure
2036  *
2037  * Configure the Rx unit of the MAC after a reset.
2038  **/
2039 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2040 {
2041         u64 rdba;
2042         struct ixgbe_hw *hw = &adapter->hw;
2043         struct ixgbe_ring *rx_ring;
2044         struct net_device *netdev = adapter->netdev;
2045         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2046         int i, j;
2047         u32 rdlen, rxctrl, rxcsum;
2048         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2049                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2050                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2051         u32 fctrl, hlreg0;
2052         u32 reta = 0, mrqc = 0;
2053         u32 rdrxctl;
2054         int rx_buf_len;
2055
2056         /* Decide whether to use packet split mode or not */
2057         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2058
2059         /* Set the RX buffer length according to the mode */
2060         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2061                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2062                 if (hw->mac.type == ixgbe_mac_82599EB) {
2063                         /* PSRTYPE must be initialized in 82599 */
2064                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2065                                       IXGBE_PSRTYPE_UDPHDR |
2066                                       IXGBE_PSRTYPE_IPV4HDR |
2067                                       IXGBE_PSRTYPE_IPV6HDR |
2068                                       IXGBE_PSRTYPE_L2HDR;
2069                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2070                 }
2071         } else {
2072                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2073                     (netdev->mtu <= ETH_DATA_LEN))
2074                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2075                 else
2076                         rx_buf_len = ALIGN(max_frame, 1024);
2077         }
2078
2079         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2080         fctrl |= IXGBE_FCTRL_BAM;
2081         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2082         fctrl |= IXGBE_FCTRL_PMCF;
2083         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2084
2085         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2086         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2087                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2088         else
2089                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2090 #ifdef IXGBE_FCOE
2091         if (netdev->features & NETIF_F_FCOE_MTU)
2092                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2093 #endif
2094         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2095
2096         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2097         /* disable receives while setting up the descriptors */
2098         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2099         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2100
2101         /*
2102          * Setup the HW Rx Head and Tail Descriptor Pointers and
2103          * the Base and Length of the Rx Descriptor Ring
2104          */
2105         for (i = 0; i < adapter->num_rx_queues; i++) {
2106                 rx_ring = &adapter->rx_ring[i];
2107                 rdba = rx_ring->dma;
2108                 j = rx_ring->reg_idx;
2109                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2110                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2111                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2112                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2113                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2114                 rx_ring->head = IXGBE_RDH(j);
2115                 rx_ring->tail = IXGBE_RDT(j);
2116                 rx_ring->rx_buf_len = rx_buf_len;
2117
2118                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2119                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2120                 else
2121                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2122
2123 #ifdef IXGBE_FCOE
2124                 if (netdev->features & NETIF_F_FCOE_MTU) {
2125                         struct ixgbe_ring_feature *f;
2126                         f = &adapter->ring_feature[RING_F_FCOE];
2127                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2128                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2129                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2130                                         rx_ring->rx_buf_len =
2131                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2132                         }
2133                 }
2134
2135 #endif /* IXGBE_FCOE */
2136                 ixgbe_configure_srrctl(adapter, rx_ring);
2137         }
2138
2139         if (hw->mac.type == ixgbe_mac_82598EB) {
2140                 /*
2141                  * For VMDq support of different descriptor types or
2142                  * buffer sizes through the use of multiple SRRCTL
2143                  * registers, RDRXCTL.MVMEN must be set to 1
2144                  *
2145                  * also, the manual doesn't mention it clearly but DCA hints
2146                  * will only use queue 0's tags unless this bit is set.  Side
2147                  * effects of setting this bit are only that SRRCTL must be
2148                  * fully programmed [0..15]
2149                  */
2150                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2151                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2152                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2153         }
2154
2155         /* Program MRQC for the distribution of queues */
2156         mrqc = ixgbe_setup_mrqc(adapter);
2157
2158         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2159                 /* Fill out redirection table */
2160                 for (i = 0, j = 0; i < 128; i++, j++) {
2161                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2162                                 j = 0;
2163                         /* reta = 4-byte sliding window of
2164                          * 0x00..(indices-1)(indices-1)00..etc. */
2165                         reta = (reta << 8) | (j * 0x11);
2166                         if ((i & 3) == 3)
2167                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2168                 }
2169
2170                 /* Fill out hash function seeds */
2171                 for (i = 0; i < 10; i++)
2172                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2173
2174                 if (hw->mac.type == ixgbe_mac_82598EB)
2175                         mrqc |= IXGBE_MRQC_RSSEN;
2176                     /* Perform hash on these packet types */
2177                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2178                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2179                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2180                       | IXGBE_MRQC_RSS_FIELD_IPV6
2181                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2182                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2183         }
2184         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2185
2186         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2187
2188         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2189             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2190                 /* Disable indicating checksum in descriptor, enables
2191                  * RSS hash */
2192                 rxcsum |= IXGBE_RXCSUM_PCSD;
2193         }
2194         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2195                 /* Enable IPv4 payload checksum for UDP fragments
2196                  * if PCSD is not set */
2197                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2198         }
2199
2200         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2201
2202         if (hw->mac.type == ixgbe_mac_82599EB) {
2203                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2204                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2205                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2206                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2207         }
2208
2209         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2210                 /* Enable 82599 HW-RSC */
2211                 for (i = 0; i < adapter->num_rx_queues; i++)
2212                         ixgbe_configure_rscctl(adapter, i, rx_buf_len);
2213
2214                 /* Disable RSC for ACK packets */
2215                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2216                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2217         }
2218 }
2219
2220 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2221 {
2222         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2223         struct ixgbe_hw *hw = &adapter->hw;
2224
2225         /* add VID to filter table */
2226         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2227 }
2228
2229 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2230 {
2231         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2232         struct ixgbe_hw *hw = &adapter->hw;
2233
2234         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2235                 ixgbe_irq_disable(adapter);
2236
2237         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2238
2239         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2240                 ixgbe_irq_enable(adapter);
2241
2242         /* remove VID from filter table */
2243         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2244 }
2245
2246 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2247                                    struct vlan_group *grp)
2248 {
2249         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2250         u32 ctrl;
2251         int i, j;
2252
2253         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2254                 ixgbe_irq_disable(adapter);
2255         adapter->vlgrp = grp;
2256
2257         /*
2258          * For a DCB driver, always enable VLAN tag stripping so we can
2259          * still receive traffic from a DCB-enabled host even if we're
2260          * not in DCB mode.
2261          */
2262         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2263         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2264                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2265                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2266                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2267         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2268                 ctrl |= IXGBE_VLNCTRL_VFE;
2269                 /* enable VLAN tag insert/strip */
2270                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2271                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2272                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2273                 for (i = 0; i < adapter->num_rx_queues; i++) {
2274                         j = adapter->rx_ring[i].reg_idx;
2275                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2276                         ctrl |= IXGBE_RXDCTL_VME;
2277                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2278                 }
2279         }
2280         ixgbe_vlan_rx_add_vid(netdev, 0);
2281
2282         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2283                 ixgbe_irq_enable(adapter);
2284 }
2285
2286 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2287 {
2288         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2289
2290         if (adapter->vlgrp) {
2291                 u16 vid;
2292                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2293                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2294                                 continue;
2295                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2296                 }
2297         }
2298 }
2299
2300 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2301 {
2302         struct dev_mc_list *mc_ptr;
2303         u8 *addr = *mc_addr_ptr;
2304         *vmdq = 0;
2305
2306         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2307         if (mc_ptr->next)
2308                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2309         else
2310                 *mc_addr_ptr = NULL;
2311
2312         return addr;
2313 }
2314
2315 /**
2316  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2317  * @netdev: network interface device structure
2318  *
2319  * The set_rx_method entry point is called whenever the unicast/multicast
2320  * address list or the network interface flags are updated.  This routine is
2321  * responsible for configuring the hardware for proper unicast, multicast and
2322  * promiscuous mode.
2323  **/
2324 static void ixgbe_set_rx_mode(struct net_device *netdev)
2325 {
2326         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2327         struct ixgbe_hw *hw = &adapter->hw;
2328         u32 fctrl, vlnctrl;
2329         u8 *addr_list = NULL;
2330         int addr_count = 0;
2331
2332         /* Check for Promiscuous and All Multicast modes */
2333
2334         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2335         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2336
2337         if (netdev->flags & IFF_PROMISC) {
2338                 hw->addr_ctrl.user_set_promisc = 1;
2339                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2340                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2341         } else {
2342                 if (netdev->flags & IFF_ALLMULTI) {
2343                         fctrl |= IXGBE_FCTRL_MPE;
2344                         fctrl &= ~IXGBE_FCTRL_UPE;
2345                 } else {
2346                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2347                 }
2348                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2349                 hw->addr_ctrl.user_set_promisc = 0;
2350         }
2351
2352         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2353         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2354
2355         /* reprogram secondary unicast list */
2356         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2357
2358         /* reprogram multicast list */
2359         addr_count = netdev->mc_count;
2360         if (addr_count)
2361                 addr_list = netdev->mc_list->dmi_addr;
2362         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2363                                         ixgbe_addr_list_itr);
2364 }
2365
2366 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2367 {
2368         int q_idx;
2369         struct ixgbe_q_vector *q_vector;
2370         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2371
2372         /* legacy and MSI only use one vector */
2373         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2374                 q_vectors = 1;
2375
2376         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2377                 struct napi_struct *napi;
2378                 q_vector = adapter->q_vector[q_idx];
2379                 napi = &q_vector->napi;
2380                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2381                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2382                                 if (q_vector->txr_count == 1)
2383                                         napi->poll = &ixgbe_clean_txonly;
2384                                 else if (q_vector->rxr_count == 1)
2385                                         napi->poll = &ixgbe_clean_rxonly;
2386                         }
2387                 }
2388
2389                 napi_enable(napi);
2390         }
2391 }
2392
2393 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2394 {
2395         int q_idx;
2396         struct ixgbe_q_vector *q_vector;
2397         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2398
2399         /* legacy and MSI only use one vector */
2400         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2401                 q_vectors = 1;
2402
2403         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2404                 q_vector = adapter->q_vector[q_idx];
2405                 napi_disable(&q_vector->napi);
2406         }
2407 }
2408
2409 #ifdef CONFIG_IXGBE_DCB
2410 /*
2411  * ixgbe_configure_dcb - Configure DCB hardware
2412  * @adapter: ixgbe adapter struct
2413  *
2414  * This is called by the driver on open to configure the DCB hardware.
2415  * This is also called by the gennetlink interface when reconfiguring
2416  * the DCB state.
2417  */
2418 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2419 {
2420         struct ixgbe_hw *hw = &adapter->hw;
2421         u32 txdctl, vlnctrl;
2422         int i, j;
2423
2424         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2425         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2426         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2427
2428         /* reconfigure the hardware */
2429         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2430
2431         for (i = 0; i < adapter->num_tx_queues; i++) {
2432                 j = adapter->tx_ring[i].reg_idx;
2433                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2434                 /* PThresh workaround for Tx hang with DFP enabled. */
2435                 txdctl |= 32;
2436                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2437         }
2438         /* Enable VLAN tag insert/strip */
2439         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2440         if (hw->mac.type == ixgbe_mac_82598EB) {
2441                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2442                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2443                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2444         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2445                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2446                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2447                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2448                 for (i = 0; i < adapter->num_rx_queues; i++) {
2449                         j = adapter->rx_ring[i].reg_idx;
2450                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2451                         vlnctrl |= IXGBE_RXDCTL_VME;
2452                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2453                 }
2454         }
2455         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2456 }
2457
2458 #endif
2459 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2460 {
2461         struct net_device *netdev = adapter->netdev;
2462         struct ixgbe_hw *hw = &adapter->hw;
2463         int i;
2464
2465         ixgbe_set_rx_mode(netdev);
2466
2467         ixgbe_restore_vlan(adapter);
2468 #ifdef CONFIG_IXGBE_DCB
2469         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2470                 netif_set_gso_max_size(netdev, 32768);
2471                 ixgbe_configure_dcb(adapter);
2472         } else {
2473                 netif_set_gso_max_size(netdev, 65536);
2474         }
2475 #else
2476         netif_set_gso_max_size(netdev, 65536);
2477 #endif
2478
2479 #ifdef IXGBE_FCOE
2480         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2481                 ixgbe_configure_fcoe(adapter);
2482
2483 #endif /* IXGBE_FCOE */
2484         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2485                 for (i = 0; i < adapter->num_tx_queues; i++)
2486                         adapter->tx_ring[i].atr_sample_rate =
2487                                                        adapter->atr_sample_rate;
2488                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2489         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2490                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2491         }
2492
2493         ixgbe_configure_tx(adapter);
2494         ixgbe_configure_rx(adapter);
2495         for (i = 0; i < adapter->num_rx_queues; i++)
2496                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2497                                        (adapter->rx_ring[i].count - 1));
2498 }
2499
2500 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2501 {
2502         switch (hw->phy.type) {
2503         case ixgbe_phy_sfp_avago:
2504         case ixgbe_phy_sfp_ftl:
2505         case ixgbe_phy_sfp_intel:
2506         case ixgbe_phy_sfp_unknown:
2507         case ixgbe_phy_tw_tyco:
2508         case ixgbe_phy_tw_unknown:
2509                 return true;
2510         default:
2511                 return false;
2512         }
2513 }
2514
2515 /**
2516  * ixgbe_sfp_link_config - set up SFP+ link
2517  * @adapter: pointer to private adapter struct
2518  **/
2519 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2520 {
2521         struct ixgbe_hw *hw = &adapter->hw;
2522
2523                 if (hw->phy.multispeed_fiber) {
2524                         /*
2525                          * In multispeed fiber setups, the device may not have
2526                          * had a physical connection when the driver loaded.
2527                          * If that's the case, the initial link configuration
2528                          * couldn't get the MAC into 10G or 1G mode, so we'll
2529                          * never have a link status change interrupt fire.
2530                          * We need to try and force an autonegotiation
2531                          * session, then bring up link.
2532                          */
2533                         hw->mac.ops.setup_sfp(hw);
2534                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2535                                 schedule_work(&adapter->multispeed_fiber_task);
2536                 } else {
2537                         /*
2538                          * Direct Attach Cu and non-multispeed fiber modules
2539                          * still need to be configured properly prior to
2540                          * attempting link.
2541                          */
2542                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2543                                 schedule_work(&adapter->sfp_config_module_task);
2544                 }
2545 }
2546
2547 /**
2548  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2549  * @hw: pointer to private hardware struct
2550  *
2551  * Returns 0 on success, negative on failure
2552  **/
2553 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2554 {
2555         u32 autoneg;
2556         bool negotiation, link_up = false;
2557         u32 ret = IXGBE_ERR_LINK_SETUP;
2558
2559         if (hw->mac.ops.check_link)
2560                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2561
2562         if (ret)
2563                 goto link_cfg_out;
2564
2565         if (hw->mac.ops.get_link_capabilities)
2566                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2567         if (ret)
2568                 goto link_cfg_out;
2569
2570         if (hw->mac.ops.setup_link)
2571                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2572 link_cfg_out:
2573         return ret;
2574 }
2575
2576 #define IXGBE_MAX_RX_DESC_POLL 10
2577 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2578                                               int rxr)
2579 {
2580         int j = adapter->rx_ring[rxr].reg_idx;
2581         int k;
2582
2583         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2584                 if (IXGBE_READ_REG(&adapter->hw,
2585                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2586                         break;
2587                 else
2588                         msleep(1);
2589         }
2590         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2591                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2592                         "not set within the polling period\n", rxr);
2593         }
2594         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2595                               (adapter->rx_ring[rxr].count - 1));
2596 }
2597
2598 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2599 {
2600         struct net_device *netdev = adapter->netdev;
2601         struct ixgbe_hw *hw = &adapter->hw;
2602         int i, j = 0;
2603         int num_rx_rings = adapter->num_rx_queues;
2604         int err;
2605         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2606         u32 txdctl, rxdctl, mhadd;
2607         u32 dmatxctl;
2608         u32 gpie;
2609
2610         ixgbe_get_hw_control(adapter);
2611
2612         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2613             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2614                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2615                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2616                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2617                 } else {
2618                         /* MSI only */
2619                         gpie = 0;
2620                 }
2621                 /* XXX: to interrupt immediately for EICS writes, enable this */
2622                 /* gpie |= IXGBE_GPIE_EIMEN; */
2623                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2624         }
2625
2626         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2627                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2628                  * specifically only auto mask tx and rx interrupts */
2629                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2630         }
2631
2632         /* Enable fan failure interrupt if media type is copper */
2633         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2634                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2635                 gpie |= IXGBE_SDP1_GPIEN;
2636                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2637         }
2638
2639         if (hw->mac.type == ixgbe_mac_82599EB) {
2640                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2641                 gpie |= IXGBE_SDP1_GPIEN;
2642                 gpie |= IXGBE_SDP2_GPIEN;
2643                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2644         }
2645
2646 #ifdef IXGBE_FCOE
2647         /* adjust max frame to be able to do baby jumbo for FCoE */
2648         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2649             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2650                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2651
2652 #endif /* IXGBE_FCOE */
2653         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2654         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2655                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2656                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2657
2658                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2659         }
2660
2661         for (i = 0; i < adapter->num_tx_queues; i++) {
2662                 j = adapter->tx_ring[i].reg_idx;
2663                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2664                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2665                 txdctl |= (8 << 16);
2666                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2667         }
2668
2669         if (hw->mac.type == ixgbe_mac_82599EB) {
2670                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2671                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2672                 dmatxctl |= IXGBE_DMATXCTL_TE;
2673                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2674         }
2675         for (i = 0; i < adapter->num_tx_queues; i++) {
2676                 j = adapter->tx_ring[i].reg_idx;
2677                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2678                 txdctl |= IXGBE_TXDCTL_ENABLE;
2679                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2680         }
2681
2682         for (i = 0; i < num_rx_rings; i++) {
2683                 j = adapter->rx_ring[i].reg_idx;
2684                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2685                 /* enable PTHRESH=32 descriptors (half the internal cache)
2686                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2687                  * this also removes a pesky rx_no_buffer_count increment */
2688                 rxdctl |= 0x0020;
2689                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2690                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2691                 if (hw->mac.type == ixgbe_mac_82599EB)
2692                         ixgbe_rx_desc_queue_enable(adapter, i);
2693         }
2694         /* enable all receives */
2695         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2696         if (hw->mac.type == ixgbe_mac_82598EB)
2697                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2698         else
2699                 rxdctl |= IXGBE_RXCTRL_RXEN;
2700         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2701
2702         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2703                 ixgbe_configure_msix(adapter);
2704         else
2705                 ixgbe_configure_msi_and_legacy(adapter);
2706
2707         clear_bit(__IXGBE_DOWN, &adapter->state);
2708         ixgbe_napi_enable_all(adapter);
2709
2710         /* clear any pending interrupts, may auto mask */
2711         IXGBE_READ_REG(hw, IXGBE_EICR);
2712
2713         ixgbe_irq_enable(adapter);
2714
2715         /*
2716          * If this adapter has a fan, check to see if we had a failure
2717          * before we enabled the interrupt.
2718          */
2719         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2720                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2721                 if (esdp & IXGBE_ESDP_SDP1)
2722                         DPRINTK(DRV, CRIT,
2723                                 "Fan has stopped, replace the adapter\n");
2724         }
2725
2726         /*
2727          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2728          * arrived before interrupts were enabled but after probe.  Such
2729          * devices wouldn't have their type identified yet. We need to
2730          * kick off the SFP+ module setup first, then try to bring up link.
2731          * If we're not hot-pluggable SFP+, we just need to configure link
2732          * and bring it up.
2733          */
2734         if (hw->phy.type == ixgbe_phy_unknown) {
2735                 err = hw->phy.ops.identify(hw);
2736                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2737                         /*
2738                          * Take the device down and schedule the sfp tasklet
2739                          * which will unregister_netdev and log it.
2740                          */
2741                         ixgbe_down(adapter);
2742                         schedule_work(&adapter->sfp_config_module_task);
2743                         return err;
2744                 }
2745         }
2746
2747         if (ixgbe_is_sfp(hw)) {
2748                 ixgbe_sfp_link_config(adapter);
2749         } else {
2750                 err = ixgbe_non_sfp_link_config(hw);
2751                 if (err)
2752                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2753         }
2754
2755         for (i = 0; i < adapter->num_tx_queues; i++)
2756                 set_bit(__IXGBE_FDIR_INIT_DONE,
2757                         &(adapter->tx_ring[i].reinit_state));
2758
2759         /* enable transmits */
2760         netif_tx_start_all_queues(netdev);
2761
2762         /* bring the link up in the watchdog, this could race with our first
2763          * link up interrupt but shouldn't be a problem */
2764         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2765         adapter->link_check_timeout = jiffies;
2766         mod_timer(&adapter->watchdog_timer, jiffies);
2767         return 0;
2768 }
2769
2770 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2771 {
2772         WARN_ON(in_interrupt());
2773         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2774                 msleep(1);
2775         ixgbe_down(adapter);
2776         ixgbe_up(adapter);
2777         clear_bit(__IXGBE_RESETTING, &adapter->state);
2778 }
2779
2780 int ixgbe_up(struct ixgbe_adapter *adapter)
2781 {
2782         /* hardware has been reset, we need to reload some things */
2783         ixgbe_configure(adapter);
2784
2785         return ixgbe_up_complete(adapter);
2786 }
2787
2788 void ixgbe_reset(struct ixgbe_adapter *adapter)
2789 {
2790         struct ixgbe_hw *hw = &adapter->hw;
2791         int err;
2792
2793         err = hw->mac.ops.init_hw(hw);
2794         switch (err) {
2795         case 0:
2796         case IXGBE_ERR_SFP_NOT_PRESENT:
2797                 break;
2798         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2799                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2800                 break;
2801         case IXGBE_ERR_EEPROM_VERSION:
2802                 /* We are running on a pre-production device, log a warning */
2803                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2804                          "adapter/LOM.  Please be aware there may be issues "
2805                          "associated with your hardware.  If you are "
2806                          "experiencing problems please contact your Intel or "
2807                          "hardware representative who provided you with this "
2808                          "hardware.\n");
2809                 break;
2810         default:
2811                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2812         }
2813
2814         /* reprogram the RAR[0] in case user changed it. */
2815         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2816 }
2817
2818 /**
2819  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2820  * @adapter: board private structure
2821  * @rx_ring: ring to free buffers from
2822  **/
2823 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2824                                 struct ixgbe_ring *rx_ring)
2825 {
2826         struct pci_dev *pdev = adapter->pdev;
2827         unsigned long size;
2828         unsigned int i;
2829
2830         /* Free all the Rx ring sk_buffs */
2831
2832         for (i = 0; i < rx_ring->count; i++) {
2833                 struct ixgbe_rx_buffer *rx_buffer_info;
2834
2835                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2836                 if (rx_buffer_info->dma) {
2837                         pci_unmap_single(pdev, rx_buffer_info->dma,
2838                                          rx_ring->rx_buf_len,
2839                                          PCI_DMA_FROMDEVICE);
2840                         rx_buffer_info->dma = 0;
2841                 }
2842                 if (rx_buffer_info->skb) {
2843                         struct sk_buff *skb = rx_buffer_info->skb;
2844                         rx_buffer_info->skb = NULL;
2845                         do {
2846                                 struct sk_buff *this = skb;
2847                                 skb = skb->prev;
2848                                 dev_kfree_skb(this);
2849                         } while (skb);
2850                 }
2851                 if (!rx_buffer_info->page)
2852                         continue;
2853                 if (rx_buffer_info->page_dma) {
2854                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2855                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2856                         rx_buffer_info->page_dma = 0;
2857                 }
2858                 put_page(rx_buffer_info->page);
2859                 rx_buffer_info->page = NULL;
2860                 rx_buffer_info->page_offset = 0;
2861         }
2862
2863         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2864         memset(rx_ring->rx_buffer_info, 0, size);
2865
2866         /* Zero out the descriptor ring */
2867         memset(rx_ring->desc, 0, rx_ring->size);
2868
2869         rx_ring->next_to_clean = 0;
2870         rx_ring->next_to_use = 0;
2871
2872         if (rx_ring->head)
2873                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2874         if (rx_ring->tail)
2875                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2876 }
2877
2878 /**
2879  * ixgbe_clean_tx_ring - Free Tx Buffers
2880  * @adapter: board private structure
2881  * @tx_ring: ring to be cleaned
2882  **/
2883 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2884                                 struct ixgbe_ring *tx_ring)
2885 {
2886         struct ixgbe_tx_buffer *tx_buffer_info;
2887         unsigned long size;
2888         unsigned int i;
2889
2890         /* Free all the Tx ring sk_buffs */
2891
2892         for (i = 0; i < tx_ring->count; i++) {
2893                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2894                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2895         }
2896
2897         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2898         memset(tx_ring->tx_buffer_info, 0, size);
2899
2900         /* Zero out the descriptor ring */
2901         memset(tx_ring->desc, 0, tx_ring->size);
2902
2903         tx_ring->next_to_use = 0;
2904         tx_ring->next_to_clean = 0;
2905
2906         if (tx_ring->head)
2907                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2908         if (tx_ring->tail)
2909                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2910 }
2911
2912 /**
2913  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2914  * @adapter: board private structure
2915  **/
2916 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2917 {
2918         int i;
2919
2920         for (i = 0; i < adapter->num_rx_queues; i++)
2921                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2922 }
2923
2924 /**
2925  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2926  * @adapter: board private structure
2927  **/
2928 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2929 {
2930         int i;
2931
2932         for (i = 0; i < adapter->num_tx_queues; i++)
2933                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2934 }
2935
2936 void ixgbe_down(struct ixgbe_adapter *adapter)
2937 {
2938         struct net_device *netdev = adapter->netdev;
2939         struct ixgbe_hw *hw = &adapter->hw;
2940         u32 rxctrl;
2941         u32 txdctl;
2942         int i, j;
2943
2944         /* signal that we are down to the interrupt handler */
2945         set_bit(__IXGBE_DOWN, &adapter->state);
2946
2947         /* disable receives */
2948         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2949         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2950
2951         netif_tx_disable(netdev);
2952
2953         IXGBE_WRITE_FLUSH(hw);
2954         msleep(10);
2955
2956         netif_tx_stop_all_queues(netdev);
2957
2958         ixgbe_irq_disable(adapter);
2959
2960         ixgbe_napi_disable_all(adapter);
2961
2962         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2963         del_timer_sync(&adapter->sfp_timer);
2964         del_timer_sync(&adapter->watchdog_timer);
2965         cancel_work_sync(&adapter->watchdog_task);
2966
2967         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2968             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2969                 cancel_work_sync(&adapter->fdir_reinit_task);
2970
2971         /* disable transmits in the hardware now that interrupts are off */
2972         for (i = 0; i < adapter->num_tx_queues; i++) {
2973                 j = adapter->tx_ring[i].reg_idx;
2974                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2975                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2976                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2977         }
2978         /* Disable the Tx DMA engine on 82599 */
2979         if (hw->mac.type == ixgbe_mac_82599EB)
2980                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2981                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2982                                  ~IXGBE_DMATXCTL_TE));
2983
2984         netif_carrier_off(netdev);
2985
2986         if (!pci_channel_offline(adapter->pdev))
2987                 ixgbe_reset(adapter);
2988         ixgbe_clean_all_tx_rings(adapter);
2989         ixgbe_clean_all_rx_rings(adapter);
2990
2991 #ifdef CONFIG_IXGBE_DCA
2992         /* since we reset the hardware DCA settings were cleared */
2993         ixgbe_setup_dca(adapter);
2994 #endif
2995 }
2996
2997 /**
2998  * ixgbe_poll - NAPI Rx polling callback
2999  * @napi: structure for representing this polling device
3000  * @budget: how many packets driver is allowed to clean
3001  *
3002  * This function is used for legacy and MSI, NAPI mode
3003  **/
3004 static int ixgbe_poll(struct napi_struct *napi, int budget)
3005 {
3006         struct ixgbe_q_vector *q_vector =
3007                                 container_of(napi, struct ixgbe_q_vector, napi);
3008         struct ixgbe_adapter *adapter = q_vector->adapter;
3009         int tx_clean_complete, work_done = 0;
3010
3011 #ifdef CONFIG_IXGBE_DCA
3012         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3013                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3014                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3015         }
3016 #endif
3017
3018         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3019         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3020
3021         if (!tx_clean_complete)
3022                 work_done = budget;
3023
3024         /* If budget not fully consumed, exit the polling mode */
3025         if (work_done < budget) {
3026                 napi_complete(napi);
3027                 if (adapter->rx_itr_setting & 1)
3028                         ixgbe_set_itr(adapter);
3029                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3030                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3031         }
3032         return work_done;
3033 }
3034
3035 /**
3036  * ixgbe_tx_timeout - Respond to a Tx Hang
3037  * @netdev: network interface device structure
3038  **/
3039 static void ixgbe_tx_timeout(struct net_device *netdev)
3040 {
3041         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3042
3043         /* Do the reset outside of interrupt context */
3044         schedule_work(&adapter->reset_task);
3045 }
3046
3047 static void ixgbe_reset_task(struct work_struct *work)
3048 {
3049         struct ixgbe_adapter *adapter;
3050         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3051
3052         /* If we're already down or resetting, just bail */
3053         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3054             test_bit(__IXGBE_RESETTING, &adapter->state))
3055                 return;
3056
3057         adapter->tx_timeout_count++;
3058
3059         ixgbe_reinit_locked(adapter);
3060 }
3061
3062 #ifdef CONFIG_IXGBE_DCB
3063 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3064 {
3065         bool ret = false;
3066         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3067
3068         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3069                 return ret;
3070
3071         f->mask = 0x7 << 3;
3072         adapter->num_rx_queues = f->indices;
3073         adapter->num_tx_queues = f->indices;
3074         ret = true;
3075
3076         return ret;
3077 }
3078 #endif
3079
3080 /**
3081  * ixgbe_set_rss_queues: Allocate queues for RSS
3082  * @adapter: board private structure to initialize
3083  *
3084  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3085  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3086  *
3087  **/
3088 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3089 {
3090         bool ret = false;
3091         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3092
3093         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3094                 f->mask = 0xF;
3095                 adapter->num_rx_queues = f->indices;
3096                 adapter->num_tx_queues = f->indices;
3097                 ret = true;
3098         } else {
3099                 ret = false;
3100         }
3101
3102         return ret;
3103 }
3104
3105 /**
3106  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3107  * @adapter: board private structure to initialize
3108  *
3109  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3110  * to the original CPU that initiated the Tx session.  This runs in addition
3111  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3112  * Rx load across CPUs using RSS.
3113  *
3114  **/
3115 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3116 {
3117         bool ret = false;
3118         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3119
3120         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3121         f_fdir->mask = 0;
3122
3123         /* Flow Director must have RSS enabled */
3124         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3125             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3126              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3127                 adapter->num_tx_queues = f_fdir->indices;
3128                 adapter->num_rx_queues = f_fdir->indices;
3129                 ret = true;
3130         } else {
3131                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3132                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3133         }
3134         return ret;
3135 }
3136
3137 #ifdef IXGBE_FCOE
3138 /**
3139  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3140  * @adapter: board private structure to initialize
3141  *
3142  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3143  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3144  * rx queues out of the max number of rx queues, instead, it is used as the
3145  * index of the first rx queue used by FCoE.
3146  *
3147  **/
3148 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3149 {
3150         bool ret = false;
3151         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3152
3153         f->indices = min((int)num_online_cpus(), f->indices);
3154         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3155                 adapter->num_rx_queues = 1;
3156                 adapter->num_tx_queues = 1;
3157 #ifdef CONFIG_IXGBE_DCB
3158                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3159                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3160                         ixgbe_set_dcb_queues(adapter);
3161                 }
3162 #endif
3163                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3164                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3165                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3166                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3167                                 ixgbe_set_fdir_queues(adapter);
3168                         else
3169                                 ixgbe_set_rss_queues(adapter);
3170                 }
3171                 /* adding FCoE rx rings to the end */
3172                 f->mask = adapter->num_rx_queues;
3173                 adapter->num_rx_queues += f->indices;
3174                 adapter->num_tx_queues += f->indices;
3175
3176                 ret = true;
3177         }
3178
3179         return ret;
3180 }
3181
3182 #endif /* IXGBE_FCOE */
3183 /*
3184  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3185  * @adapter: board private structure to initialize
3186  *
3187  * This is the top level queue allocation routine.  The order here is very
3188  * important, starting with the "most" number of features turned on at once,
3189  * and ending with the smallest set of features.  This way large combinations
3190  * can be allocated if they're turned on, and smaller combinations are the
3191  * fallthrough conditions.
3192  *
3193  **/
3194 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3195 {
3196 #ifdef IXGBE_FCOE
3197         if (ixgbe_set_fcoe_queues(adapter))
3198                 goto done;
3199
3200 #endif /* IXGBE_FCOE */
3201 #ifdef CONFIG_IXGBE_DCB
3202         if (ixgbe_set_dcb_queues(adapter))
3203                 goto done;
3204
3205 #endif
3206         if (ixgbe_set_fdir_queues(adapter))
3207                 goto done;
3208
3209         if (ixgbe_set_rss_queues(adapter))
3210                 goto done;
3211
3212         /* fallback to base case */
3213         adapter->num_rx_queues = 1;
3214         adapter->num_tx_queues = 1;
3215
3216 done:
3217         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3218         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3219 }
3220
3221 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3222                                        int vectors)
3223 {
3224         int err, vector_threshold;
3225
3226         /* We'll want at least 3 (vector_threshold):
3227          * 1) TxQ[0] Cleanup
3228          * 2) RxQ[0] Cleanup
3229          * 3) Other (Link Status Change, etc.)
3230          * 4) TCP Timer (optional)
3231          */
3232         vector_threshold = MIN_MSIX_COUNT;
3233
3234         /* The more we get, the more we will assign to Tx/Rx Cleanup
3235          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3236          * Right now, we simply care about how many we'll get; we'll
3237          * set them up later while requesting irq's.
3238          */
3239         while (vectors >= vector_threshold) {
3240                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3241                                       vectors);
3242                 if (!err) /* Success in acquiring all requested vectors. */
3243                         break;
3244                 else if (err < 0)
3245                         vectors = 0; /* Nasty failure, quit now */
3246                 else /* err == number of vectors we should try again with */
3247                         vectors = err;
3248         }
3249
3250         if (vectors < vector_threshold) {
3251                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3252                  * This just means we'll go with either a single MSI
3253                  * vector or fall back to legacy interrupts.
3254                  */
3255                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3256                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3257                 kfree(adapter->msix_entries);
3258                 adapter->msix_entries = NULL;
3259         } else {
3260                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3261                 /*
3262                  * Adjust for only the vectors we'll use, which is minimum
3263                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3264                  * vectors we were allocated.
3265                  */
3266                 adapter->num_msix_vectors = min(vectors,
3267                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3268         }
3269 }
3270
3271 /**
3272  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3273  * @adapter: board private structure to initialize
3274  *
3275  * Cache the descriptor ring offsets for RSS to the assigned rings.
3276  *
3277  **/
3278 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3279 {
3280         int i;
3281         bool ret = false;
3282
3283         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3284                 for (i = 0; i < adapter->num_rx_queues; i++)
3285                         adapter->rx_ring[i].reg_idx = i;
3286                 for (i = 0; i < adapter->num_tx_queues; i++)
3287                         adapter->tx_ring[i].reg_idx = i;
3288                 ret = true;
3289         } else {
3290                 ret = false;
3291         }
3292
3293         return ret;
3294 }
3295
3296 #ifdef CONFIG_IXGBE_DCB
3297 /**
3298  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3299  * @adapter: board private structure to initialize
3300  *
3301  * Cache the descriptor ring offsets for DCB to the assigned rings.
3302  *
3303  **/
3304 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3305 {
3306         int i;
3307         bool ret = false;
3308         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3309
3310         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3311                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3312                         /* the number of queues is assumed to be symmetric */
3313                         for (i = 0; i < dcb_i; i++) {
3314                                 adapter->rx_ring[i].reg_idx = i << 3;
3315                                 adapter->tx_ring[i].reg_idx = i << 2;
3316                         }
3317                         ret = true;
3318                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3319                         if (dcb_i == 8) {
3320                                 /*
3321                                  * Tx TC0 starts at: descriptor queue 0
3322                                  * Tx TC1 starts at: descriptor queue 32
3323                                  * Tx TC2 starts at: descriptor queue 64
3324                                  * Tx TC3 starts at: descriptor queue 80
3325                                  * Tx TC4 starts at: descriptor queue 96
3326                                  * Tx TC5 starts at: descriptor queue 104
3327                                  * Tx TC6 starts at: descriptor queue 112
3328                                  * Tx TC7 starts at: descriptor queue 120
3329                                  *
3330                                  * Rx TC0-TC7 are offset by 16 queues each
3331                                  */
3332                                 for (i = 0; i < 3; i++) {
3333                                         adapter->tx_ring[i].reg_idx = i << 5;
3334                                         adapter->rx_ring[i].reg_idx = i << 4;
3335                                 }
3336                                 for ( ; i < 5; i++) {
3337                                         adapter->tx_ring[i].reg_idx =
3338                                                                  ((i + 2) << 4);
3339                                         adapter->rx_ring[i].reg_idx = i << 4;
3340                                 }
3341                                 for ( ; i < dcb_i; i++) {
3342                                         adapter->tx_ring[i].reg_idx =
3343                                                                  ((i + 8) << 3);
3344                                         adapter->rx_ring[i].reg_idx = i << 4;
3345                                 }
3346
3347                                 ret = true;
3348                         } else if (dcb_i == 4) {
3349                                 /*
3350                                  * Tx TC0 starts at: descriptor queue 0
3351                                  * Tx TC1 starts at: descriptor queue 64
3352                                  * Tx TC2 starts at: descriptor queue 96
3353                                  * Tx TC3 starts at: descriptor queue 112
3354                                  *
3355                                  * Rx TC0-TC3 are offset by 32 queues each
3356                                  */
3357                                 adapter->tx_ring[0].reg_idx = 0;
3358                                 adapter->tx_ring[1].reg_idx = 64;
3359                                 adapter->tx_ring[2].reg_idx = 96;
3360                                 adapter->tx_ring[3].reg_idx = 112;
3361                                 for (i = 0 ; i < dcb_i; i++)
3362                                         adapter->rx_ring[i].reg_idx = i << 5;
3363
3364                                 ret = true;
3365                         } else {
3366                                 ret = false;
3367                         }
3368                 } else {
3369                         ret = false;
3370                 }
3371         } else {
3372                 ret = false;
3373         }
3374
3375         return ret;
3376 }
3377 #endif
3378
3379 /**
3380  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3381  * @adapter: board private structure to initialize
3382  *
3383  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3384  *
3385  **/
3386 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3387 {
3388         int i;
3389         bool ret = false;
3390
3391         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3392             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3393              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3394                 for (i = 0; i < adapter->num_rx_queues; i++)
3395                         adapter->rx_ring[i].reg_idx = i;
3396                 for (i = 0; i < adapter->num_tx_queues; i++)
3397                         adapter->tx_ring[i].reg_idx = i;
3398                 ret = true;
3399         }
3400
3401         return ret;
3402 }
3403
3404 #ifdef IXGBE_FCOE
3405 /**
3406  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3407  * @adapter: board private structure to initialize
3408  *
3409  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3410  *
3411  */
3412 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3413 {
3414         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3415         bool ret = false;
3416         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3417
3418         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3419 #ifdef CONFIG_IXGBE_DCB
3420                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3421                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3422
3423                         ixgbe_cache_ring_dcb(adapter);
3424                         /* find out queues in TC for FCoE */
3425                         fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3426                         fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3427                         /*
3428                          * In 82599, the number of Tx queues for each traffic
3429                          * class for both 8-TC and 4-TC modes are:
3430                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3431                          * 8 TCs:  32  32  16  16   8   8   8   8
3432                          * 4 TCs:  64  64  32  32
3433                          * We have max 8 queues for FCoE, where 8 the is
3434                          * FCoE redirection table size. If TC for FCoE is
3435                          * less than or equal to TC3, we have enough queues
3436                          * to add max of 8 queues for FCoE, so we start FCoE
3437                          * tx descriptor from the next one, i.e., reg_idx + 1.
3438                          * If TC for FCoE is above TC3, implying 8 TC mode,
3439                          * and we need 8 for FCoE, we have to take all queues
3440                          * in that traffic class for FCoE.
3441                          */
3442                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3443                                 fcoe_tx_i--;
3444                 }
3445 #endif /* CONFIG_IXGBE_DCB */
3446                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3447                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3448                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3449                                 ixgbe_cache_ring_fdir(adapter);
3450                         else
3451                                 ixgbe_cache_ring_rss(adapter);
3452
3453                         fcoe_rx_i = f->mask;
3454                         fcoe_tx_i = f->mask;
3455                 }
3456                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3457                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3458                         adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3459                 }
3460                 ret = true;
3461         }
3462         return ret;
3463 }
3464
3465 #endif /* IXGBE_FCOE */
3466 /**
3467  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3468  * @adapter: board private structure to initialize
3469  *
3470  * Once we know the feature-set enabled for the device, we'll cache
3471  * the register offset the descriptor ring is assigned to.
3472  *
3473  * Note, the order the various feature calls is important.  It must start with
3474  * the "most" features enabled at the same time, then trickle down to the
3475  * least amount of features turned on at once.
3476  **/
3477 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3478 {
3479         /* start with default case */
3480         adapter->rx_ring[0].reg_idx = 0;
3481         adapter->tx_ring[0].reg_idx = 0;
3482
3483 #ifdef IXGBE_FCOE
3484         if (ixgbe_cache_ring_fcoe(adapter))
3485                 return;
3486
3487 #endif /* IXGBE_FCOE */
3488 #ifdef CONFIG_IXGBE_DCB
3489         if (ixgbe_cache_ring_dcb(adapter))
3490                 return;
3491
3492 #endif
3493         if (ixgbe_cache_ring_fdir(adapter))
3494                 return;
3495
3496         if (ixgbe_cache_ring_rss(adapter))
3497                 return;
3498 }
3499
3500 /**
3501  * ixgbe_alloc_queues - Allocate memory for all rings
3502  * @adapter: board private structure to initialize
3503  *
3504  * We allocate one ring per queue at run-time since we don't know the
3505  * number of queues at compile-time.  The polling_netdev array is
3506  * intended for Multiqueue, but should work fine with a single queue.
3507  **/
3508 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3509 {
3510         int i;
3511
3512         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3513                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3514         if (!adapter->tx_ring)
3515                 goto err_tx_ring_allocation;
3516
3517         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3518                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3519         if (!adapter->rx_ring)
3520                 goto err_rx_ring_allocation;
3521
3522         for (i = 0; i < adapter->num_tx_queues; i++) {
3523                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3524                 adapter->tx_ring[i].queue_index = i;
3525         }
3526
3527         for (i = 0; i < adapter->num_rx_queues; i++) {
3528                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3529                 adapter->rx_ring[i].queue_index = i;
3530         }
3531
3532         ixgbe_cache_ring_register(adapter);
3533
3534         return 0;
3535
3536 err_rx_ring_allocation:
3537         kfree(adapter->tx_ring);
3538 err_tx_ring_allocation:
3539         return -ENOMEM;
3540 }
3541
3542 /**
3543  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3544  * @adapter: board private structure to initialize
3545  *
3546  * Attempt to configure the interrupts using the best available
3547  * capabilities of the hardware and the kernel.
3548  **/
3549 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3550 {
3551         struct ixgbe_hw *hw = &adapter->hw;
3552         int err = 0;
3553         int vector, v_budget;
3554
3555         /*
3556          * It's easy to be greedy for MSI-X vectors, but it really
3557          * doesn't do us much good if we have a lot more vectors
3558          * than CPU's.  So let's be conservative and only ask for
3559          * (roughly) twice the number of vectors as there are CPU's.
3560          */
3561         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3562                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3563
3564         /*
3565          * At the same time, hardware can only support a maximum of
3566          * hw.mac->max_msix_vectors vectors.  With features
3567          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3568          * descriptor queues supported by our device.  Thus, we cap it off in
3569          * those rare cases where the cpu count also exceeds our vector limit.
3570          */
3571         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3572
3573         /* A failure in MSI-X entry allocation isn't fatal, but it does
3574          * mean we disable MSI-X capabilities of the adapter. */
3575         adapter->msix_entries = kcalloc(v_budget,
3576                                         sizeof(struct msix_entry), GFP_KERNEL);
3577         if (adapter->msix_entries) {
3578                 for (vector = 0; vector < v_budget; vector++)
3579                         adapter->msix_entries[vector].entry = vector;
3580
3581                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3582
3583                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3584                         goto out;
3585         }
3586
3587         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3588         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3589         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3590         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3591         adapter->atr_sample_rate = 0;
3592         ixgbe_set_num_queues(adapter);
3593
3594         err = pci_enable_msi(adapter->pdev);
3595         if (!err) {
3596                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3597         } else {
3598                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3599                         "falling back to legacy.  Error: %d\n", err);
3600                 /* reset err */
3601                 err = 0;
3602         }
3603
3604 out:
3605         return err;
3606 }
3607
3608 /**
3609  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3610  * @adapter: board private structure to initialize
3611  *
3612  * We allocate one q_vector per queue interrupt.  If allocation fails we
3613  * return -ENOMEM.
3614  **/
3615 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3616 {
3617         int q_idx, num_q_vectors;
3618         struct ixgbe_q_vector *q_vector;
3619         int napi_vectors;
3620         int (*poll)(struct napi_struct *, int);
3621
3622         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3623                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3624                 napi_vectors = adapter->num_rx_queues;
3625                 poll = &ixgbe_clean_rxtx_many;
3626         } else {
3627                 num_q_vectors = 1;
3628                 napi_vectors = 1;
3629                 poll = &ixgbe_poll;
3630         }
3631
3632         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3633                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3634                 if (!q_vector)
3635                         goto err_out;
3636                 q_vector->adapter = adapter;
3637                 if (q_vector->txr_count && !q_vector->rxr_count)
3638                         q_vector->eitr = adapter->tx_eitr_param;
3639                 else
3640                         q_vector->eitr = adapter->rx_eitr_param;
3641                 q_vector->v_idx = q_idx;
3642                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3643                 adapter->q_vector[q_idx] = q_vector;
3644         }
3645
3646         return 0;
3647
3648 err_out:
3649         while (q_idx) {
3650                 q_idx--;
3651                 q_vector = adapter->q_vector[q_idx];
3652                 netif_napi_del(&q_vector->napi);
3653                 kfree(q_vector);
3654                 adapter->q_vector[q_idx] = NULL;
3655         }
3656         return -ENOMEM;
3657 }
3658
3659 /**
3660  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3661  * @adapter: board private structure to initialize
3662  *
3663  * This function frees the memory allocated to the q_vectors.  In addition if
3664  * NAPI is enabled it will delete any references to the NAPI struct prior
3665  * to freeing the q_vector.
3666  **/
3667 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3668 {
3669         int q_idx, num_q_vectors;
3670
3671         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3672                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3673         else
3674                 num_q_vectors = 1;
3675
3676         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3677                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3678                 adapter->q_vector[q_idx] = NULL;
3679                 netif_napi_del(&q_vector->napi);
3680                 kfree(q_vector);
3681         }
3682 }
3683
3684 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3685 {
3686         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3687                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3688                 pci_disable_msix(adapter->pdev);
3689                 kfree(adapter->msix_entries);
3690                 adapter->msix_entries = NULL;
3691         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3692                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3693                 pci_disable_msi(adapter->pdev);
3694         }
3695         return;
3696 }
3697
3698 /**
3699  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3700  * @adapter: board private structure to initialize
3701  *
3702  * We determine which interrupt scheme to use based on...
3703  * - Kernel support (MSI, MSI-X)
3704  *   - which can be user-defined (via MODULE_PARAM)
3705  * - Hardware queue count (num_*_queues)
3706  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3707  **/
3708 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3709 {
3710         int err;
3711
3712         /* Number of supported queues */
3713         ixgbe_set_num_queues(adapter);
3714
3715         err = ixgbe_set_interrupt_capability(adapter);
3716         if (err) {
3717                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3718                 goto err_set_interrupt;
3719         }
3720
3721         err = ixgbe_alloc_q_vectors(adapter);
3722         if (err) {
3723                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3724                         "vectors\n");
3725                 goto err_alloc_q_vectors;
3726         }
3727
3728         err = ixgbe_alloc_queues(adapter);
3729         if (err) {
3730                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3731                 goto err_alloc_queues;
3732         }
3733
3734         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3735                 "Tx Queue count = %u\n",
3736                 (adapter->num_rx_queues > 1) ? "Enabled" :
3737                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3738
3739         set_bit(__IXGBE_DOWN, &adapter->state);
3740
3741         return 0;
3742
3743 err_alloc_queues:
3744         ixgbe_free_q_vectors(adapter);
3745 err_alloc_q_vectors:
3746         ixgbe_reset_interrupt_capability(adapter);
3747 err_set_interrupt:
3748         return err;
3749 }
3750
3751 /**
3752  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3753  * @adapter: board private structure to clear interrupt scheme on
3754  *
3755  * We go through and clear interrupt specific resources and reset the structure
3756  * to pre-load conditions
3757  **/
3758 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3759 {
3760         kfree(adapter->tx_ring);
3761         kfree(adapter->rx_ring);
3762         adapter->tx_ring = NULL;
3763         adapter->rx_ring = NULL;
3764
3765         ixgbe_free_q_vectors(adapter);
3766         ixgbe_reset_interrupt_capability(adapter);
3767 }
3768
3769 /**
3770  * ixgbe_sfp_timer - worker thread to find a missing module
3771  * @data: pointer to our adapter struct
3772  **/
3773 static void ixgbe_sfp_timer(unsigned long data)
3774 {
3775         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3776
3777         /*
3778          * Do the sfp_timer outside of interrupt context due to the
3779          * delays that sfp+ detection requires
3780          */
3781         schedule_work(&adapter->sfp_task);
3782 }
3783
3784 /**
3785  * ixgbe_sfp_task - worker thread to find a missing module
3786  * @work: pointer to work_struct containing our data
3787  **/
3788 static void ixgbe_sfp_task(struct work_struct *work)
3789 {
3790         struct ixgbe_adapter *adapter = container_of(work,
3791                                                      struct ixgbe_adapter,
3792                                                      sfp_task);
3793         struct ixgbe_hw *hw = &adapter->hw;
3794
3795         if ((hw->phy.type == ixgbe_phy_nl) &&
3796             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3797                 s32 ret = hw->phy.ops.identify_sfp(hw);
3798                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3799                         goto reschedule;
3800                 ret = hw->phy.ops.reset(hw);
3801                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3802                         dev_err(&adapter->pdev->dev, "failed to initialize "
3803                                 "because an unsupported SFP+ module type "
3804                                 "was detected.\n"
3805                                 "Reload the driver after installing a "
3806                                 "supported module.\n");
3807                         unregister_netdev(adapter->netdev);
3808                 } else {
3809                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3810                                 hw->phy.sfp_type);
3811                 }
3812                 /* don't need this routine any more */
3813                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3814         }
3815         return;
3816 reschedule:
3817         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3818                 mod_timer(&adapter->sfp_timer,
3819                           round_jiffies(jiffies + (2 * HZ)));
3820 }
3821
3822 /**
3823  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3824  * @adapter: board private structure to initialize
3825  *
3826  * ixgbe_sw_init initializes the Adapter private data structure.
3827  * Fields are initialized based on PCI device information and
3828  * OS network device settings (MTU size).
3829  **/
3830 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3831 {
3832         struct ixgbe_hw *hw = &adapter->hw;
3833         struct pci_dev *pdev = adapter->pdev;
3834         unsigned int rss;
3835 #ifdef CONFIG_IXGBE_DCB
3836         int j;
3837         struct tc_configuration *tc;
3838 #endif
3839
3840         /* PCI config space info */
3841
3842         hw->vendor_id = pdev->vendor;
3843         hw->device_id = pdev->device;
3844         hw->revision_id = pdev->revision;
3845         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3846         hw->subsystem_device_id = pdev->subsystem_device;
3847
3848         /* Set capability flags */
3849         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3850         adapter->ring_feature[RING_F_RSS].indices = rss;
3851         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3852         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3853         if (hw->mac.type == ixgbe_mac_82598EB) {
3854                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3855                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3856                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3857         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3858                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3859                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3860                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3861                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3862                 adapter->ring_feature[RING_F_FDIR].indices =
3863                                                          IXGBE_MAX_FDIR_INDICES;
3864                 adapter->atr_sample_rate = 20;
3865                 adapter->fdir_pballoc = 0;
3866 #ifdef IXGBE_FCOE
3867                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3868                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3869                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3870                 /* Default traffic class to use for FCoE */
3871                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3872 #endif /* IXGBE_FCOE */
3873         }
3874
3875 #ifdef CONFIG_IXGBE_DCB
3876         /* Configure DCB traffic classes */
3877         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3878                 tc = &adapter->dcb_cfg.tc_config[j];
3879                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3880                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3881                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3882                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3883                 tc->dcb_pfc = pfc_disabled;
3884         }
3885         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3886         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3887         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3888         adapter->dcb_cfg.pfc_mode_enable = false;
3889         adapter->dcb_cfg.round_robin_enable = false;
3890         adapter->dcb_set_bitmap = 0x00;
3891         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3892                            adapter->ring_feature[RING_F_DCB].indices);
3893
3894 #endif
3895
3896         /* default flow control settings */
3897         hw->fc.requested_mode = ixgbe_fc_full;
3898         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3899 #ifdef CONFIG_DCB
3900         adapter->last_lfc_mode = hw->fc.current_mode;
3901 #endif
3902         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3903         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3904         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3905         hw->fc.send_xon = true;
3906         hw->fc.disable_fc_autoneg = false;
3907
3908         /* enable itr by default in dynamic mode */
3909         adapter->rx_itr_setting = 1;
3910         adapter->rx_eitr_param = 20000;
3911         adapter->tx_itr_setting = 1;
3912         adapter->tx_eitr_param = 10000;
3913
3914         /* set defaults for eitr in MegaBytes */
3915         adapter->eitr_low = 10;
3916         adapter->eitr_high = 20;
3917
3918         /* set default ring sizes */
3919         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3920         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3921
3922         /* initialize eeprom parameters */
3923         if (ixgbe_init_eeprom_params_generic(hw)) {
3924                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3925                 return -EIO;
3926         }
3927
3928         /* enable rx csum by default */
3929         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3930
3931         set_bit(__IXGBE_DOWN, &adapter->state);
3932
3933         return 0;
3934 }
3935
3936 /**
3937  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3938  * @adapter: board private structure
3939  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3940  *
3941  * Return 0 on success, negative on failure
3942  **/
3943 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3944                              struct ixgbe_ring *tx_ring)
3945 {
3946         struct pci_dev *pdev = adapter->pdev;
3947         int size;
3948
3949         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3950         tx_ring->tx_buffer_info = vmalloc(size);
3951         if (!tx_ring->tx_buffer_info)
3952                 goto err;
3953         memset(tx_ring->tx_buffer_info, 0, size);
3954
3955         /* round up to nearest 4K */
3956         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3957         tx_ring->size = ALIGN(tx_ring->size, 4096);
3958
3959         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3960                                              &tx_ring->dma);
3961         if (!tx_ring->desc)
3962                 goto err;
3963
3964         tx_ring->next_to_use = 0;
3965         tx_ring->next_to_clean = 0;
3966         tx_ring->work_limit = tx_ring->count;
3967         return 0;
3968
3969 err:
3970         vfree(tx_ring->tx_buffer_info);
3971         tx_ring->tx_buffer_info = NULL;
3972         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3973                             "descriptor ring\n");
3974         return -ENOMEM;
3975 }
3976
3977 /**
3978  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3979  * @adapter: board private structure
3980  *
3981  * If this function returns with an error, then it's possible one or
3982  * more of the rings is populated (while the rest are not).  It is the
3983  * callers duty to clean those orphaned rings.
3984  *
3985  * Return 0 on success, negative on failure
3986  **/
3987 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3988 {
3989         int i, err = 0;
3990
3991         for (i = 0; i < adapter->num_tx_queues; i++) {
3992                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3993                 if (!err)
3994                         continue;
3995                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3996                 break;
3997         }
3998
3999         return err;
4000 }
4001
4002 /**
4003  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4004  * @adapter: board private structure
4005  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4006  *
4007  * Returns 0 on success, negative on failure
4008  **/
4009 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4010                              struct ixgbe_ring *rx_ring)
4011 {
4012         struct pci_dev *pdev = adapter->pdev;
4013         int size;
4014
4015         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4016         rx_ring->rx_buffer_info = vmalloc(size);
4017         if (!rx_ring->rx_buffer_info) {
4018                 DPRINTK(PROBE, ERR,
4019                         "vmalloc allocation failed for the rx desc ring\n");
4020                 goto alloc_failed;
4021         }
4022         memset(rx_ring->rx_buffer_info, 0, size);
4023
4024         /* Round up to nearest 4K */
4025         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4026         rx_ring->size = ALIGN(rx_ring->size, 4096);
4027
4028         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4029
4030         if (!rx_ring->desc) {
4031                 DPRINTK(PROBE, ERR,
4032                         "Memory allocation failed for the rx desc ring\n");
4033                 vfree(rx_ring->rx_buffer_info);
4034                 goto alloc_failed;
4035         }
4036
4037         rx_ring->next_to_clean = 0;
4038         rx_ring->next_to_use = 0;
4039
4040         return 0;
4041
4042 alloc_failed:
4043         return -ENOMEM;
4044 }
4045
4046 /**
4047  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4048  * @adapter: board private structure
4049  *
4050  * If this function returns with an error, then it's possible one or
4051  * more of the rings is populated (while the rest are not).  It is the
4052  * callers duty to clean those orphaned rings.
4053  *
4054  * Return 0 on success, negative on failure
4055  **/
4056
4057 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4058 {
4059         int i, err = 0;
4060
4061         for (i = 0; i < adapter->num_rx_queues; i++) {
4062                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4063                 if (!err)
4064                         continue;
4065                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4066                 break;
4067         }
4068
4069         return err;
4070 }
4071
4072 /**
4073  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4074  * @adapter: board private structure
4075  * @tx_ring: Tx descriptor ring for a specific queue
4076  *
4077  * Free all transmit software resources
4078  **/
4079 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4080                              struct ixgbe_ring *tx_ring)
4081 {
4082         struct pci_dev *pdev = adapter->pdev;
4083
4084         ixgbe_clean_tx_ring(adapter, tx_ring);
4085
4086         vfree(tx_ring->tx_buffer_info);
4087         tx_ring->tx_buffer_info = NULL;
4088
4089         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4090
4091         tx_ring->desc = NULL;
4092 }
4093
4094 /**
4095  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4096  * @adapter: board private structure
4097  *
4098  * Free all transmit software resources
4099  **/
4100 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4101 {
4102         int i;
4103
4104         for (i = 0; i < adapter->num_tx_queues; i++)
4105                 if (adapter->tx_ring[i].desc)
4106                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4107 }
4108
4109 /**
4110  * ixgbe_free_rx_resources - Free Rx Resources
4111  * @adapter: board private structure
4112  * @rx_ring: ring to clean the resources from
4113  *
4114  * Free all receive software resources
4115  **/
4116 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4117                              struct ixgbe_ring *rx_ring)
4118 {
4119         struct pci_dev *pdev = adapter->pdev;
4120
4121         ixgbe_clean_rx_ring(adapter, rx_ring);
4122
4123         vfree(rx_ring->rx_buffer_info);
4124         rx_ring->rx_buffer_info = NULL;
4125
4126         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4127
4128         rx_ring->desc = NULL;
4129 }
4130
4131 /**
4132  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4133  * @adapter: board private structure
4134  *
4135  * Free all receive software resources
4136  **/
4137 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4138 {
4139         int i;
4140
4141         for (i = 0; i < adapter->num_rx_queues; i++)
4142                 if (adapter->rx_ring[i].desc)
4143                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4144 }
4145
4146 /**
4147  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4148  * @netdev: network interface device structure
4149  * @new_mtu: new value for maximum frame size
4150  *
4151  * Returns 0 on success, negative on failure
4152  **/
4153 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4154 {
4155         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4156         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4157
4158         /* MTU < 68 is an error and causes problems on some kernels */
4159         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4160                 return -EINVAL;
4161
4162         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4163                 netdev->mtu, new_mtu);
4164         /* must set new MTU before calling down or up */
4165         netdev->mtu = new_mtu;
4166
4167         if (netif_running(netdev))
4168                 ixgbe_reinit_locked(adapter);
4169
4170         return 0;
4171 }
4172
4173 /**
4174  * ixgbe_open - Called when a network interface is made active
4175  * @netdev: network interface device structure
4176  *
4177  * Returns 0 on success, negative value on failure
4178  *
4179  * The open entry point is called when a network interface is made
4180  * active by the system (IFF_UP).  At this point all resources needed
4181  * for transmit and receive operations are allocated, the interrupt
4182  * handler is registered with the OS, the watchdog timer is started,
4183  * and the stack is notified that the interface is ready.
4184  **/
4185 static int ixgbe_open(struct net_device *netdev)
4186 {
4187         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4188         int err;
4189
4190         /* disallow open during test */
4191         if (test_bit(__IXGBE_TESTING, &adapter->state))
4192                 return -EBUSY;
4193
4194         netif_carrier_off(netdev);
4195
4196         /* allocate transmit descriptors */
4197         err = ixgbe_setup_all_tx_resources(adapter);
4198         if (err)
4199                 goto err_setup_tx;
4200
4201         /* allocate receive descriptors */
4202         err = ixgbe_setup_all_rx_resources(adapter);
4203         if (err)
4204                 goto err_setup_rx;
4205
4206         ixgbe_configure(adapter);
4207
4208         err = ixgbe_request_irq(adapter);
4209         if (err)
4210                 goto err_req_irq;
4211
4212         err = ixgbe_up_complete(adapter);
4213         if (err)
4214                 goto err_up;
4215
4216         netif_tx_start_all_queues(netdev);
4217
4218         return 0;
4219
4220 err_up:
4221         ixgbe_release_hw_control(adapter);
4222         ixgbe_free_irq(adapter);
4223 err_req_irq:
4224 err_setup_rx:
4225         ixgbe_free_all_rx_resources(adapter);
4226 err_setup_tx:
4227         ixgbe_free_all_tx_resources(adapter);
4228         ixgbe_reset(adapter);
4229
4230         return err;
4231 }
4232
4233 /**
4234  * ixgbe_close - Disables a network interface
4235  * @netdev: network interface device structure
4236  *
4237  * Returns 0, this is not allowed to fail
4238  *
4239  * The close entry point is called when an interface is de-activated
4240  * by the OS.  The hardware is still under the drivers control, but
4241  * needs to be disabled.  A global MAC reset is issued to stop the
4242  * hardware, and all transmit and receive resources are freed.
4243  **/
4244 static int ixgbe_close(struct net_device *netdev)
4245 {
4246         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4247
4248         ixgbe_down(adapter);
4249         ixgbe_free_irq(adapter);
4250
4251         ixgbe_free_all_tx_resources(adapter);
4252         ixgbe_free_all_rx_resources(adapter);
4253
4254         ixgbe_release_hw_control(adapter);
4255
4256         return 0;
4257 }
4258
4259 #ifdef CONFIG_PM
4260 static int ixgbe_resume(struct pci_dev *pdev)
4261 {
4262         struct net_device *netdev = pci_get_drvdata(pdev);
4263         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4264         u32 err;
4265
4266         pci_set_power_state(pdev, PCI_D0);
4267         pci_restore_state(pdev);
4268
4269         err = pci_enable_device_mem(pdev);
4270         if (err) {
4271                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4272                                 "suspend\n");
4273                 return err;
4274         }
4275         pci_set_master(pdev);
4276
4277         pci_wake_from_d3(pdev, false);
4278
4279         err = ixgbe_init_interrupt_scheme(adapter);
4280         if (err) {
4281                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4282                                 "device\n");
4283                 return err;
4284         }
4285
4286         ixgbe_reset(adapter);
4287
4288         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4289
4290         if (netif_running(netdev)) {
4291                 err = ixgbe_open(adapter->netdev);
4292                 if (err)
4293                         return err;
4294         }
4295
4296         netif_device_attach(netdev);
4297
4298         return 0;
4299 }
4300 #endif /* CONFIG_PM */
4301
4302 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4303 {
4304         struct net_device *netdev = pci_get_drvdata(pdev);
4305         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4306         struct ixgbe_hw *hw = &adapter->hw;
4307         u32 ctrl, fctrl;
4308         u32 wufc = adapter->wol;
4309 #ifdef CONFIG_PM
4310         int retval = 0;
4311 #endif
4312
4313         netif_device_detach(netdev);
4314
4315         if (netif_running(netdev)) {
4316                 ixgbe_down(adapter);
4317                 ixgbe_free_irq(adapter);
4318                 ixgbe_free_all_tx_resources(adapter);
4319                 ixgbe_free_all_rx_resources(adapter);
4320         }
4321         ixgbe_clear_interrupt_scheme(adapter);
4322
4323 #ifdef CONFIG_PM
4324         retval = pci_save_state(pdev);
4325         if (retval)
4326                 return retval;
4327
4328 #endif
4329         if (wufc) {
4330                 ixgbe_set_rx_mode(netdev);
4331
4332                 /* turn on all-multi mode if wake on multicast is enabled */
4333                 if (wufc & IXGBE_WUFC_MC) {
4334                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4335                         fctrl |= IXGBE_FCTRL_MPE;
4336                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4337                 }
4338
4339                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4340                 ctrl |= IXGBE_CTRL_GIO_DIS;
4341                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4342
4343                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4344         } else {
4345                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4346                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4347         }
4348
4349         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4350                 pci_wake_from_d3(pdev, true);
4351         else
4352                 pci_wake_from_d3(pdev, false);
4353
4354         *enable_wake = !!wufc;
4355
4356         ixgbe_release_hw_control(adapter);
4357
4358         pci_disable_device(pdev);
4359
4360         return 0;
4361 }
4362
4363 #ifdef CONFIG_PM
4364 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4365 {
4366         int retval;
4367         bool wake;
4368
4369         retval = __ixgbe_shutdown(pdev, &wake);
4370         if (retval)
4371                 return retval;
4372
4373         if (wake) {
4374                 pci_prepare_to_sleep(pdev);
4375         } else {
4376                 pci_wake_from_d3(pdev, false);
4377                 pci_set_power_state(pdev, PCI_D3hot);
4378         }
4379
4380         return 0;
4381 }
4382 #endif /* CONFIG_PM */
4383
4384 static void ixgbe_shutdown(struct pci_dev *pdev)
4385 {
4386         bool wake;
4387
4388         __ixgbe_shutdown(pdev, &wake);
4389
4390         if (system_state == SYSTEM_POWER_OFF) {
4391                 pci_wake_from_d3(pdev, wake);
4392                 pci_set_power_state(pdev, PCI_D3hot);
4393         }
4394 }
4395
4396 /**
4397  * ixgbe_update_stats - Update the board statistics counters.
4398  * @adapter: board private structure
4399  **/
4400 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4401 {
4402         struct ixgbe_hw *hw = &adapter->hw;
4403         u64 total_mpc = 0;
4404         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4405
4406         if (hw->mac.type == ixgbe_mac_82599EB) {
4407                 u64 rsc_count = 0;
4408                 for (i = 0; i < 16; i++)
4409                         adapter->hw_rx_no_dma_resources +=
4410                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4411                 for (i = 0; i < adapter->num_rx_queues; i++)
4412                         rsc_count += adapter->rx_ring[i].rsc_count;
4413                 adapter->rsc_count = rsc_count;
4414         }
4415
4416         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4417         for (i = 0; i < 8; i++) {
4418                 /* for packet buffers not used, the register should read 0 */
4419                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4420                 missed_rx += mpc;
4421                 adapter->stats.mpc[i] += mpc;
4422                 total_mpc += adapter->stats.mpc[i];
4423                 if (hw->mac.type == ixgbe_mac_82598EB)
4424                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4425                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4426                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4427                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4428                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4429                 if (hw->mac.type == ixgbe_mac_82599EB) {
4430                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4431                                                             IXGBE_PXONRXCNT(i));
4432                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4433                                                            IXGBE_PXOFFRXCNT(i));
4434                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4435                 } else {
4436                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4437                                                               IXGBE_PXONRXC(i));
4438                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4439                                                              IXGBE_PXOFFRXC(i));
4440                 }
4441                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4442                                                             IXGBE_PXONTXC(i));
4443                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4444                                                              IXGBE_PXOFFTXC(i));
4445         }
4446         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4447         /* work around hardware counting issue */
4448         adapter->stats.gprc -= missed_rx;
4449
4450         /* 82598 hardware only has a 32 bit counter in the high register */
4451         if (hw->mac.type == ixgbe_mac_82599EB) {
4452                 u64 tmp;
4453                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4454                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4455                 adapter->stats.gorc += (tmp << 32);
4456                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4457                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4458                 adapter->stats.gotc += (tmp << 32);
4459                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4460                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4461                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4462                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4463                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4464                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4465 #ifdef IXGBE_FCOE
4466                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4467                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4468                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4469                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4470                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4471                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4472 #endif /* IXGBE_FCOE */
4473         } else {
4474                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4475                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4476                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4477                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4478                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4479         }
4480         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4481         adapter->stats.bprc += bprc;
4482         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4483         if (hw->mac.type == ixgbe_mac_82598EB)
4484                 adapter->stats.mprc -= bprc;
4485         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4486         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4487         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4488         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4489         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4490         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4491         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4492         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4493         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4494         adapter->stats.lxontxc += lxon;
4495         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4496         adapter->stats.lxofftxc += lxoff;
4497         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4498         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4499         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4500         /*
4501          * 82598 errata - tx of flow control packets is included in tx counters
4502          */
4503         xon_off_tot = lxon + lxoff;
4504         adapter->stats.gptc -= xon_off_tot;
4505         adapter->stats.mptc -= xon_off_tot;
4506         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4507         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4508         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4509         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4510         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4511         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4512         adapter->stats.ptc64 -= xon_off_tot;
4513         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4514         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4515         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4516         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4517         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4518         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4519
4520         /* Fill out the OS statistics structure */
4521         adapter->net_stats.multicast = adapter->stats.mprc;
4522
4523         /* Rx Errors */
4524         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4525                                        adapter->stats.rlec;
4526         adapter->net_stats.rx_dropped = 0;
4527         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4528         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4529         adapter->net_stats.rx_missed_errors = total_mpc;
4530 }
4531
4532 /**
4533  * ixgbe_watchdog - Timer Call-back
4534  * @data: pointer to adapter cast into an unsigned long
4535  **/
4536 static void ixgbe_watchdog(unsigned long data)
4537 {
4538         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4539         struct ixgbe_hw *hw = &adapter->hw;
4540         u64 eics = 0;
4541         int i;
4542
4543         /*
4544          *  Do the watchdog outside of interrupt context due to the lovely
4545          * delays that some of the newer hardware requires
4546          */
4547
4548         if (test_bit(__IXGBE_DOWN, &adapter->state))
4549                 goto watchdog_short_circuit;
4550
4551         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4552                 /*
4553                  * for legacy and MSI interrupts don't set any bits
4554                  * that are enabled for EIAM, because this operation
4555                  * would set *both* EIMS and EICS for any bit in EIAM
4556                  */
4557                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4558                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4559                 goto watchdog_reschedule;
4560         }
4561
4562         /* get one bit for every active tx/rx interrupt vector */
4563         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4564                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4565                 if (qv->rxr_count || qv->txr_count)
4566                         eics |= ((u64)1 << i);
4567         }
4568
4569         /* Cause software interrupt to ensure rx rings are cleaned */
4570         ixgbe_irq_rearm_queues(adapter, eics);
4571
4572 watchdog_reschedule:
4573         /* Reset the timer */
4574         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4575
4576 watchdog_short_circuit:
4577         schedule_work(&adapter->watchdog_task);
4578 }
4579
4580 /**
4581  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4582  * @work: pointer to work_struct containing our data
4583  **/
4584 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4585 {
4586         struct ixgbe_adapter *adapter = container_of(work,
4587                                                      struct ixgbe_adapter,
4588                                                      multispeed_fiber_task);
4589         struct ixgbe_hw *hw = &adapter->hw;
4590         u32 autoneg;
4591         bool negotiation;
4592
4593         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4594         autoneg = hw->phy.autoneg_advertised;
4595         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4596                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4597         if (hw->mac.ops.setup_link)
4598                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4599         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4600         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4601 }
4602
4603 /**
4604  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4605  * @work: pointer to work_struct containing our data
4606  **/
4607 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4608 {
4609         struct ixgbe_adapter *adapter = container_of(work,
4610                                                      struct ixgbe_adapter,
4611                                                      sfp_config_module_task);
4612         struct ixgbe_hw *hw = &adapter->hw;
4613         u32 err;
4614
4615         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4616
4617         /* Time for electrical oscillations to settle down */
4618         msleep(100);
4619         err = hw->phy.ops.identify_sfp(hw);
4620
4621         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4622                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4623                         "an unsupported SFP+ module type was detected.\n"
4624                         "Reload the driver after installing a supported "
4625                         "module.\n");
4626                 unregister_netdev(adapter->netdev);
4627                 return;
4628         }
4629         hw->mac.ops.setup_sfp(hw);
4630
4631         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4632                 /* This will also work for DA Twinax connections */
4633                 schedule_work(&adapter->multispeed_fiber_task);
4634         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4635 }
4636
4637 /**
4638  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4639  * @work: pointer to work_struct containing our data
4640  **/
4641 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4642 {
4643         struct ixgbe_adapter *adapter = container_of(work,
4644                                                      struct ixgbe_adapter,
4645                                                      fdir_reinit_task);
4646         struct ixgbe_hw *hw = &adapter->hw;
4647         int i;
4648
4649         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4650                 for (i = 0; i < adapter->num_tx_queues; i++)
4651                         set_bit(__IXGBE_FDIR_INIT_DONE,
4652                                 &(adapter->tx_ring[i].reinit_state));
4653         } else {
4654                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4655                         "ignored adding FDIR ATR filters \n");
4656         }
4657         /* Done FDIR Re-initialization, enable transmits */
4658         netif_tx_start_all_queues(adapter->netdev);
4659 }
4660
4661 /**
4662  * ixgbe_watchdog_task - worker thread to bring link up
4663  * @work: pointer to work_struct containing our data
4664  **/
4665 static void ixgbe_watchdog_task(struct work_struct *work)
4666 {
4667         struct ixgbe_adapter *adapter = container_of(work,
4668                                                      struct ixgbe_adapter,
4669                                                      watchdog_task);
4670         struct net_device *netdev = adapter->netdev;
4671         struct ixgbe_hw *hw = &adapter->hw;
4672         u32 link_speed = adapter->link_speed;
4673         bool link_up = adapter->link_up;
4674         int i;
4675         struct ixgbe_ring *tx_ring;
4676         int some_tx_pending = 0;
4677
4678         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4679
4680         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4681                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4682                 if (link_up) {
4683 #ifdef CONFIG_DCB
4684                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4685                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4686                                         hw->mac.ops.fc_enable(hw, i);
4687                         } else {
4688                                 hw->mac.ops.fc_enable(hw, 0);
4689                         }
4690 #else
4691                         hw->mac.ops.fc_enable(hw, 0);
4692 #endif
4693                 }
4694
4695                 if (link_up ||
4696                     time_after(jiffies, (adapter->link_check_timeout +
4697                                          IXGBE_TRY_LINK_TIMEOUT))) {
4698                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4699                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4700                 }
4701                 adapter->link_up = link_up;
4702                 adapter->link_speed = link_speed;
4703         }
4704
4705         if (link_up) {
4706                 if (!netif_carrier_ok(netdev)) {
4707                         bool flow_rx, flow_tx;
4708
4709                         if (hw->mac.type == ixgbe_mac_82599EB) {
4710                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4711                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4712                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4713                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4714                         } else {
4715                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4716                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4717                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4718                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4719                         }
4720
4721                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4722                                "Flow Control: %s\n",
4723                                netdev->name,
4724                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4725                                 "10 Gbps" :
4726                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4727                                  "1 Gbps" : "unknown speed")),
4728                                ((flow_rx && flow_tx) ? "RX/TX" :
4729                                 (flow_rx ? "RX" :
4730                                 (flow_tx ? "TX" : "None"))));
4731
4732                         netif_carrier_on(netdev);
4733                 } else {
4734                         /* Force detection of hung controller */
4735                         adapter->detect_tx_hung = true;
4736                 }
4737         } else {
4738                 adapter->link_up = false;
4739                 adapter->link_speed = 0;
4740                 if (netif_carrier_ok(netdev)) {
4741                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4742                                netdev->name);
4743                         netif_carrier_off(netdev);
4744                 }
4745         }
4746
4747         if (!netif_carrier_ok(netdev)) {
4748                 for (i = 0; i < adapter->num_tx_queues; i++) {
4749                         tx_ring = &adapter->tx_ring[i];
4750                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4751                                 some_tx_pending = 1;
4752                                 break;
4753                         }
4754                 }
4755
4756                 if (some_tx_pending) {
4757                         /* We've lost link, so the controller stops DMA,
4758                          * but we've got queued Tx work that's never going
4759                          * to get done, so reset controller to flush Tx.
4760                          * (Do the reset outside of interrupt context).
4761                          */
4762                          schedule_work(&adapter->reset_task);
4763                 }
4764         }
4765
4766         ixgbe_update_stats(adapter);
4767         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4768 }
4769
4770 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4771                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4772                      u32 tx_flags, u8 *hdr_len)
4773 {
4774         struct ixgbe_adv_tx_context_desc *context_desc;
4775         unsigned int i;
4776         int err;
4777         struct ixgbe_tx_buffer *tx_buffer_info;
4778         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4779         u32 mss_l4len_idx, l4len;
4780
4781         if (skb_is_gso(skb)) {
4782                 if (skb_header_cloned(skb)) {
4783                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4784                         if (err)
4785                                 return err;
4786                 }
4787                 l4len = tcp_hdrlen(skb);
4788                 *hdr_len += l4len;
4789
4790                 if (skb->protocol == htons(ETH_P_IP)) {
4791                         struct iphdr *iph = ip_hdr(skb);
4792                         iph->tot_len = 0;
4793                         iph->check = 0;
4794                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4795                                                                  iph->daddr, 0,
4796                                                                  IPPROTO_TCP,
4797                                                                  0);
4798                         adapter->hw_tso_ctxt++;
4799                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4800                         ipv6_hdr(skb)->payload_len = 0;
4801                         tcp_hdr(skb)->check =
4802                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4803                                              &ipv6_hdr(skb)->daddr,
4804                                              0, IPPROTO_TCP, 0);
4805                         adapter->hw_tso6_ctxt++;
4806                 }
4807
4808                 i = tx_ring->next_to_use;
4809
4810                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4811                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4812
4813                 /* VLAN MACLEN IPLEN */
4814                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4815                         vlan_macip_lens |=
4816                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4817                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4818                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4819                 *hdr_len += skb_network_offset(skb);
4820                 vlan_macip_lens |=
4821                     (skb_transport_header(skb) - skb_network_header(skb));
4822                 *hdr_len +=
4823                     (skb_transport_header(skb) - skb_network_header(skb));
4824                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4825                 context_desc->seqnum_seed = 0;
4826
4827                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4828                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4829                                    IXGBE_ADVTXD_DTYP_CTXT);
4830
4831                 if (skb->protocol == htons(ETH_P_IP))
4832                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4833                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4834                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4835
4836                 /* MSS L4LEN IDX */
4837                 mss_l4len_idx =
4838                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4839                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4840                 /* use index 1 for TSO */
4841                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4842                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4843
4844                 tx_buffer_info->time_stamp = jiffies;
4845                 tx_buffer_info->next_to_watch = i;
4846
4847                 i++;
4848                 if (i == tx_ring->count)
4849                         i = 0;
4850                 tx_ring->next_to_use = i;
4851
4852                 return true;
4853         }
4854         return false;
4855 }
4856
4857 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4858                           struct ixgbe_ring *tx_ring,
4859                           struct sk_buff *skb, u32 tx_flags)
4860 {
4861         struct ixgbe_adv_tx_context_desc *context_desc;
4862         unsigned int i;
4863         struct ixgbe_tx_buffer *tx_buffer_info;
4864         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4865
4866         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4867             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4868                 i = tx_ring->next_to_use;
4869                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4870                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4871
4872                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4873                         vlan_macip_lens |=
4874                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4875                 vlan_macip_lens |= (skb_network_offset(skb) <<
4876                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4877                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4878                         vlan_macip_lens |= (skb_transport_header(skb) -
4879                                             skb_network_header(skb));
4880
4881                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4882                 context_desc->seqnum_seed = 0;
4883
4884                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4885                                     IXGBE_ADVTXD_DTYP_CTXT);
4886
4887                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4888                         switch (skb->protocol) {
4889                         case cpu_to_be16(ETH_P_IP):
4890                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4891                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4892                                         type_tucmd_mlhl |=
4893                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4894                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4895                                         type_tucmd_mlhl |=
4896                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4897                                 break;
4898                         case cpu_to_be16(ETH_P_IPV6):
4899                                 /* XXX what about other V6 headers?? */
4900                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4901                                         type_tucmd_mlhl |=
4902                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4903                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4904                                         type_tucmd_mlhl |=
4905                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4906                                 break;
4907                         default:
4908                                 if (unlikely(net_ratelimit())) {
4909                                         DPRINTK(PROBE, WARNING,
4910                                          "partial checksum but proto=%x!\n",
4911                                          skb->protocol);
4912                                 }
4913                                 break;
4914                         }
4915                 }
4916
4917                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4918                 /* use index zero for tx checksum offload */
4919                 context_desc->mss_l4len_idx = 0;
4920
4921                 tx_buffer_info->time_stamp = jiffies;
4922                 tx_buffer_info->next_to_watch = i;
4923
4924                 adapter->hw_csum_tx_good++;
4925                 i++;
4926                 if (i == tx_ring->count)
4927                         i = 0;
4928                 tx_ring->next_to_use = i;
4929
4930                 return true;
4931         }
4932
4933         return false;
4934 }
4935
4936 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4937                         struct ixgbe_ring *tx_ring,
4938                         struct sk_buff *skb, u32 tx_flags,
4939                         unsigned int first)
4940 {
4941         struct ixgbe_tx_buffer *tx_buffer_info;
4942         unsigned int len;
4943         unsigned int total = skb->len;
4944         unsigned int offset = 0, size, count = 0, i;
4945         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4946         unsigned int f;
4947         dma_addr_t *map;
4948
4949         i = tx_ring->next_to_use;
4950
4951         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4952                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4953                 return 0;
4954         }
4955
4956         map = skb_shinfo(skb)->dma_maps;
4957
4958         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4959                 /* excluding fcoe_crc_eof for FCoE */
4960                 total -= sizeof(struct fcoe_crc_eof);
4961
4962         len = min(skb_headlen(skb), total);
4963         while (len) {
4964                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4965                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4966
4967                 tx_buffer_info->length = size;
4968                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
4969                 tx_buffer_info->time_stamp = jiffies;
4970                 tx_buffer_info->next_to_watch = i;
4971
4972                 len -= size;
4973                 total -= size;
4974                 offset += size;
4975                 count++;
4976
4977                 if (len) {
4978                         i++;
4979                         if (i == tx_ring->count)
4980                                 i = 0;
4981                 }
4982         }
4983
4984         for (f = 0; f < nr_frags; f++) {
4985                 struct skb_frag_struct *frag;
4986
4987                 frag = &skb_shinfo(skb)->frags[f];
4988                 len = min((unsigned int)frag->size, total);
4989                 offset = 0;
4990
4991                 while (len) {
4992                         i++;
4993                         if (i == tx_ring->count)
4994                                 i = 0;
4995
4996                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4997                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4998
4999                         tx_buffer_info->length = size;
5000                         tx_buffer_info->dma = map[f] + offset;
5001                         tx_buffer_info->time_stamp = jiffies;
5002                         tx_buffer_info->next_to_watch = i;
5003
5004                         len -= size;
5005                         total -= size;
5006                         offset += size;
5007                         count++;
5008                 }
5009                 if (total == 0)
5010                         break;
5011         }
5012
5013         tx_ring->tx_buffer_info[i].skb = skb;
5014         tx_ring->tx_buffer_info[first].next_to_watch = i;
5015
5016         return count;
5017 }
5018
5019 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5020                            struct ixgbe_ring *tx_ring,
5021                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5022 {
5023         union ixgbe_adv_tx_desc *tx_desc = NULL;
5024         struct ixgbe_tx_buffer *tx_buffer_info;
5025         u32 olinfo_status = 0, cmd_type_len = 0;
5026         unsigned int i;
5027         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5028
5029         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5030
5031         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5032
5033         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5034                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5035
5036         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5037                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5038
5039                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5040                                  IXGBE_ADVTXD_POPTS_SHIFT;
5041
5042                 /* use index 1 context for tso */
5043                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5044                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5045                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5046                                          IXGBE_ADVTXD_POPTS_SHIFT;
5047
5048         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5049                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5050                                  IXGBE_ADVTXD_POPTS_SHIFT;
5051
5052         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5053                 olinfo_status |= IXGBE_ADVTXD_CC;
5054                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5055                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5056                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5057         }
5058
5059         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5060
5061         i = tx_ring->next_to_use;
5062         while (count--) {
5063                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5064                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5065                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5066                 tx_desc->read.cmd_type_len =
5067                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5068                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5069                 i++;
5070                 if (i == tx_ring->count)
5071                         i = 0;
5072         }
5073
5074         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5075
5076         /*
5077          * Force memory writes to complete before letting h/w
5078          * know there are new descriptors to fetch.  (Only
5079          * applicable for weak-ordered memory model archs,
5080          * such as IA-64).
5081          */
5082         wmb();
5083
5084         tx_ring->next_to_use = i;
5085         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5086 }
5087
5088 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5089                       int queue, u32 tx_flags)
5090 {
5091         /* Right now, we support IPv4 only */
5092         struct ixgbe_atr_input atr_input;
5093         struct tcphdr *th;
5094         struct iphdr *iph = ip_hdr(skb);
5095         struct ethhdr *eth = (struct ethhdr *)skb->data;
5096         u16 vlan_id, src_port, dst_port, flex_bytes;
5097         u32 src_ipv4_addr, dst_ipv4_addr;
5098         u8 l4type = 0;
5099
5100         /* check if we're UDP or TCP */
5101         if (iph->protocol == IPPROTO_TCP) {
5102                 th = tcp_hdr(skb);
5103                 src_port = th->source;
5104                 dst_port = th->dest;
5105                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5106                 /* l4type IPv4 type is 0, no need to assign */
5107         } else {
5108                 /* Unsupported L4 header, just bail here */
5109                 return;
5110         }
5111
5112         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5113
5114         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5115                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5116         src_ipv4_addr = iph->saddr;
5117         dst_ipv4_addr = iph->daddr;
5118         flex_bytes = eth->h_proto;
5119
5120         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5121         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5122         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5123         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5124         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5125         /* src and dst are inverted, think how the receiver sees them */
5126         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5127         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5128
5129         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5130         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5131 }
5132
5133 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5134                                  struct ixgbe_ring *tx_ring, int size)
5135 {
5136         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5137
5138         netif_stop_subqueue(netdev, tx_ring->queue_index);
5139         /* Herbert's original patch had:
5140          *  smp_mb__after_netif_stop_queue();
5141          * but since that doesn't exist yet, just open code it. */
5142         smp_mb();
5143
5144         /* We need to check again in a case another CPU has just
5145          * made room available. */
5146         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5147                 return -EBUSY;
5148
5149         /* A reprieve! - use start_queue because it doesn't call schedule */
5150         netif_start_subqueue(netdev, tx_ring->queue_index);
5151         ++adapter->restart_queue;
5152         return 0;
5153 }
5154
5155 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5156                               struct ixgbe_ring *tx_ring, int size)
5157 {
5158         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5159                 return 0;
5160         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5161 }
5162
5163 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5164 {
5165         struct ixgbe_adapter *adapter = netdev_priv(dev);
5166
5167         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5168                 return smp_processor_id();
5169
5170         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5171                 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5172
5173         return skb_tx_hash(dev, skb);
5174 }
5175
5176 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5177                                     struct net_device *netdev)
5178 {
5179         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5180         struct ixgbe_ring *tx_ring;
5181         unsigned int first;
5182         unsigned int tx_flags = 0;
5183         u8 hdr_len = 0;
5184         int r_idx = 0, tso;
5185         int count = 0;
5186         unsigned int f;
5187
5188         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5189                 tx_flags |= vlan_tx_tag_get(skb);
5190                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5191                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5192                         tx_flags |= (skb->queue_mapping << 13);
5193                 }
5194                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5195                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5196         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5197                 if (skb->priority != TC_PRIO_CONTROL) {
5198                         tx_flags |= (skb->queue_mapping << 13);
5199                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5200                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5201                 } else {
5202                         skb->queue_mapping =
5203                                 adapter->ring_feature[RING_F_DCB].indices-1;
5204                 }
5205         }
5206
5207         r_idx = skb->queue_mapping;
5208         tx_ring = &adapter->tx_ring[r_idx];
5209
5210         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5211             (skb->protocol == htons(ETH_P_FCOE))) {
5212                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5213 #ifdef IXGBE_FCOE
5214                 r_idx = smp_processor_id();
5215                 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5216                 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5217                 tx_ring = &adapter->tx_ring[r_idx];
5218 #endif
5219         }
5220         /* four things can cause us to need a context descriptor */
5221         if (skb_is_gso(skb) ||
5222             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5223             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5224             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5225                 count++;
5226
5227         count += TXD_USE_COUNT(skb_headlen(skb));
5228         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5229                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5230
5231         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5232                 adapter->tx_busy++;
5233                 return NETDEV_TX_BUSY;
5234         }
5235
5236         first = tx_ring->next_to_use;
5237         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5238 #ifdef IXGBE_FCOE
5239                 /* setup tx offload for FCoE */
5240                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5241                 if (tso < 0) {
5242                         dev_kfree_skb_any(skb);
5243                         return NETDEV_TX_OK;
5244                 }
5245                 if (tso)
5246                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5247 #endif /* IXGBE_FCOE */
5248         } else {
5249                 if (skb->protocol == htons(ETH_P_IP))
5250                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5251                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5252                 if (tso < 0) {
5253                         dev_kfree_skb_any(skb);
5254                         return NETDEV_TX_OK;
5255                 }
5256
5257                 if (tso)
5258                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5259                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5260                          (skb->ip_summed == CHECKSUM_PARTIAL))
5261                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5262         }
5263
5264         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5265         if (count) {
5266                 /* add the ATR filter if ATR is on */
5267                 if (tx_ring->atr_sample_rate) {
5268                         ++tx_ring->atr_count;
5269                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5270                              test_bit(__IXGBE_FDIR_INIT_DONE,
5271                                       &tx_ring->reinit_state)) {
5272                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5273                                           tx_flags);
5274                                 tx_ring->atr_count = 0;
5275                         }
5276                 }
5277                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5278                                hdr_len);
5279                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5280
5281         } else {
5282                 dev_kfree_skb_any(skb);
5283                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5284                 tx_ring->next_to_use = first;
5285         }
5286
5287         return NETDEV_TX_OK;
5288 }
5289
5290 /**
5291  * ixgbe_get_stats - Get System Network Statistics
5292  * @netdev: network interface device structure
5293  *
5294  * Returns the address of the device statistics structure.
5295  * The statistics are actually updated from the timer callback.
5296  **/
5297 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5298 {
5299         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5300
5301         /* only return the current stats */
5302         return &adapter->net_stats;
5303 }
5304
5305 /**
5306  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5307  * @netdev: network interface device structure
5308  * @p: pointer to an address structure
5309  *
5310  * Returns 0 on success, negative on failure
5311  **/
5312 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5313 {
5314         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5315         struct ixgbe_hw *hw = &adapter->hw;
5316         struct sockaddr *addr = p;
5317
5318         if (!is_valid_ether_addr(addr->sa_data))
5319                 return -EADDRNOTAVAIL;
5320
5321         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5322         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5323
5324         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5325
5326         return 0;
5327 }
5328
5329 static int
5330 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5331 {
5332         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5333         struct ixgbe_hw *hw = &adapter->hw;
5334         u16 value;
5335         int rc;
5336
5337         if (prtad != hw->phy.mdio.prtad)
5338                 return -EINVAL;
5339         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5340         if (!rc)
5341                 rc = value;
5342         return rc;
5343 }
5344
5345 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5346                             u16 addr, u16 value)
5347 {
5348         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5349         struct ixgbe_hw *hw = &adapter->hw;
5350
5351         if (prtad != hw->phy.mdio.prtad)
5352                 return -EINVAL;
5353         return hw->phy.ops.write_reg(hw, addr, devad, value);
5354 }
5355
5356 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5357 {
5358         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5359
5360         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5361 }
5362
5363 /**
5364  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5365  * netdev->dev_addrs
5366  * @netdev: network interface device structure
5367  *
5368  * Returns non-zero on failure
5369  **/
5370 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5371 {
5372         int err = 0;
5373         struct ixgbe_adapter *adapter = netdev_priv(dev);
5374         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5375
5376         if (is_valid_ether_addr(mac->san_addr)) {
5377                 rtnl_lock();
5378                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5379                 rtnl_unlock();
5380         }
5381         return err;
5382 }
5383
5384 /**
5385  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5386  * netdev->dev_addrs
5387  * @netdev: network interface device structure
5388  *
5389  * Returns non-zero on failure
5390  **/
5391 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5392 {
5393         int err = 0;
5394         struct ixgbe_adapter *adapter = netdev_priv(dev);
5395         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5396
5397         if (is_valid_ether_addr(mac->san_addr)) {
5398                 rtnl_lock();
5399                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5400                 rtnl_unlock();
5401         }
5402         return err;
5403 }
5404
5405 #ifdef CONFIG_NET_POLL_CONTROLLER
5406 /*
5407  * Polling 'interrupt' - used by things like netconsole to send skbs
5408  * without having to re-enable interrupts. It's not called while
5409  * the interrupt routine is executing.
5410  */
5411 static void ixgbe_netpoll(struct net_device *netdev)
5412 {
5413         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5414         int i;
5415
5416         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5417         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5418                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5419                 for (i = 0; i < num_q_vectors; i++) {
5420                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5421                         ixgbe_msix_clean_many(0, q_vector);
5422                 }
5423         } else {
5424                 ixgbe_intr(adapter->pdev->irq, netdev);
5425         }
5426         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5427 }
5428 #endif
5429
5430 static const struct net_device_ops ixgbe_netdev_ops = {
5431         .ndo_open               = ixgbe_open,
5432         .ndo_stop               = ixgbe_close,
5433         .ndo_start_xmit         = ixgbe_xmit_frame,
5434         .ndo_select_queue       = ixgbe_select_queue,
5435         .ndo_get_stats          = ixgbe_get_stats,
5436         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5437         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5438         .ndo_validate_addr      = eth_validate_addr,
5439         .ndo_set_mac_address    = ixgbe_set_mac,
5440         .ndo_change_mtu         = ixgbe_change_mtu,
5441         .ndo_tx_timeout         = ixgbe_tx_timeout,
5442         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5443         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5444         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5445         .ndo_do_ioctl           = ixgbe_ioctl,
5446 #ifdef CONFIG_NET_POLL_CONTROLLER
5447         .ndo_poll_controller    = ixgbe_netpoll,
5448 #endif
5449 #ifdef IXGBE_FCOE
5450         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5451         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5452         .ndo_fcoe_enable = ixgbe_fcoe_enable,
5453         .ndo_fcoe_disable = ixgbe_fcoe_disable,
5454 #endif /* IXGBE_FCOE */
5455 };
5456
5457 /**
5458  * ixgbe_probe - Device Initialization Routine
5459  * @pdev: PCI device information struct
5460  * @ent: entry in ixgbe_pci_tbl
5461  *
5462  * Returns 0 on success, negative on failure
5463  *
5464  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5465  * The OS initialization, configuring of the adapter private structure,
5466  * and a hardware reset occur.
5467  **/
5468 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5469                                  const struct pci_device_id *ent)
5470 {
5471         struct net_device *netdev;
5472         struct ixgbe_adapter *adapter = NULL;
5473         struct ixgbe_hw *hw;
5474         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5475         static int cards_found;
5476         int i, err, pci_using_dac;
5477 #ifdef IXGBE_FCOE
5478         u16 device_caps;
5479 #endif
5480         u32 part_num, eec;
5481
5482         err = pci_enable_device_mem(pdev);
5483         if (err)
5484                 return err;
5485
5486         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5487             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5488                 pci_using_dac = 1;
5489         } else {
5490                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5491                 if (err) {
5492                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5493                         if (err) {
5494                                 dev_err(&pdev->dev, "No usable DMA "
5495                                         "configuration, aborting\n");
5496                                 goto err_dma;
5497                         }
5498                 }
5499                 pci_using_dac = 0;
5500         }
5501
5502         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5503                                            IORESOURCE_MEM), ixgbe_driver_name);
5504         if (err) {
5505                 dev_err(&pdev->dev,
5506                         "pci_request_selected_regions failed 0x%x\n", err);
5507                 goto err_pci_reg;
5508         }
5509
5510         pci_enable_pcie_error_reporting(pdev);
5511
5512         pci_set_master(pdev);
5513         pci_save_state(pdev);
5514
5515         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5516         if (!netdev) {
5517                 err = -ENOMEM;
5518                 goto err_alloc_etherdev;
5519         }
5520
5521         SET_NETDEV_DEV(netdev, &pdev->dev);
5522
5523         pci_set_drvdata(pdev, netdev);
5524         adapter = netdev_priv(netdev);
5525
5526         adapter->netdev = netdev;
5527         adapter->pdev = pdev;
5528         hw = &adapter->hw;
5529         hw->back = adapter;
5530         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5531
5532         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5533                               pci_resource_len(pdev, 0));
5534         if (!hw->hw_addr) {
5535                 err = -EIO;
5536                 goto err_ioremap;
5537         }
5538
5539         for (i = 1; i <= 5; i++) {
5540                 if (pci_resource_len(pdev, i) == 0)
5541                         continue;
5542         }
5543
5544         netdev->netdev_ops = &ixgbe_netdev_ops;
5545         ixgbe_set_ethtool_ops(netdev);
5546         netdev->watchdog_timeo = 5 * HZ;
5547         strcpy(netdev->name, pci_name(pdev));
5548
5549         adapter->bd_number = cards_found;
5550
5551         /* Setup hw api */
5552         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5553         hw->mac.type  = ii->mac;
5554
5555         /* EEPROM */
5556         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5557         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5558         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5559         if (!(eec & (1 << 8)))
5560                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5561
5562         /* PHY */
5563         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5564         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5565         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5566         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5567         hw->phy.mdio.mmds = 0;
5568         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5569         hw->phy.mdio.dev = netdev;
5570         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5571         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5572
5573         /* set up this timer and work struct before calling get_invariants
5574          * which might start the timer
5575          */
5576         init_timer(&adapter->sfp_timer);
5577         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5578         adapter->sfp_timer.data = (unsigned long) adapter;
5579
5580         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5581
5582         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5583         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5584
5585         /* a new SFP+ module arrival, called from GPI SDP2 context */
5586         INIT_WORK(&adapter->sfp_config_module_task,
5587                   ixgbe_sfp_config_module_task);
5588
5589         ii->get_invariants(hw);
5590
5591         /* setup the private structure */
5592         err = ixgbe_sw_init(adapter);
5593         if (err)
5594                 goto err_sw_init;
5595
5596         /*
5597          * If there is a fan on this device and it has failed log the
5598          * failure.
5599          */
5600         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5601                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5602                 if (esdp & IXGBE_ESDP_SDP1)
5603                         DPRINTK(PROBE, CRIT,
5604                                 "Fan has stopped, replace the adapter\n");
5605         }
5606
5607         /* reset_hw fills in the perm_addr as well */
5608         err = hw->mac.ops.reset_hw(hw);
5609         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5610             hw->mac.type == ixgbe_mac_82598EB) {
5611                 /*
5612                  * Start a kernel thread to watch for a module to arrive.
5613                  * Only do this for 82598, since 82599 will generate
5614                  * interrupts on module arrival.
5615                  */
5616                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5617                 mod_timer(&adapter->sfp_timer,
5618                           round_jiffies(jiffies + (2 * HZ)));
5619                 err = 0;
5620         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5621                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5622                         "an unsupported SFP+ module type was detected.\n"
5623                         "Reload the driver after installing a supported "
5624                         "module.\n");
5625                 goto err_sw_init;
5626         } else if (err) {
5627                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5628                 goto err_sw_init;
5629         }
5630
5631         netdev->features = NETIF_F_SG |
5632                            NETIF_F_IP_CSUM |
5633                            NETIF_F_HW_VLAN_TX |
5634                            NETIF_F_HW_VLAN_RX |
5635                            NETIF_F_HW_VLAN_FILTER;
5636
5637         netdev->features |= NETIF_F_IPV6_CSUM;
5638         netdev->features |= NETIF_F_TSO;
5639         netdev->features |= NETIF_F_TSO6;
5640         netdev->features |= NETIF_F_GRO;
5641
5642         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5643                 netdev->features |= NETIF_F_SCTP_CSUM;
5644
5645         netdev->vlan_features |= NETIF_F_TSO;
5646         netdev->vlan_features |= NETIF_F_TSO6;
5647         netdev->vlan_features |= NETIF_F_IP_CSUM;
5648         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5649         netdev->vlan_features |= NETIF_F_SG;
5650
5651         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5652                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5653
5654 #ifdef CONFIG_IXGBE_DCB
5655         netdev->dcbnl_ops = &dcbnl_ops;
5656 #endif
5657
5658 #ifdef IXGBE_FCOE
5659         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5660                 if (hw->mac.ops.get_device_caps) {
5661                         hw->mac.ops.get_device_caps(hw, &device_caps);
5662                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5663                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5664                 }
5665         }
5666 #endif /* IXGBE_FCOE */
5667         if (pci_using_dac)
5668                 netdev->features |= NETIF_F_HIGHDMA;
5669
5670         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5671                 netdev->features |= NETIF_F_LRO;
5672
5673         /* make sure the EEPROM is good */
5674         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5675                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5676                 err = -EIO;
5677                 goto err_eeprom;
5678         }
5679
5680         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5681         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5682
5683         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5684                 dev_err(&pdev->dev, "invalid MAC address\n");
5685                 err = -EIO;
5686                 goto err_eeprom;
5687         }
5688
5689         init_timer(&adapter->watchdog_timer);
5690         adapter->watchdog_timer.function = &ixgbe_watchdog;
5691         adapter->watchdog_timer.data = (unsigned long)adapter;
5692
5693         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5694         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5695
5696         err = ixgbe_init_interrupt_scheme(adapter);
5697         if (err)
5698                 goto err_sw_init;
5699
5700         switch (pdev->device) {
5701         case IXGBE_DEV_ID_82599_KX4:
5702                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5703                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5704                 /* Enable ACPI wakeup in GRC */
5705                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5706                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5707                 break;
5708         default:
5709                 adapter->wol = 0;
5710                 break;
5711         }
5712         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5713
5714         /* pick up the PCI bus settings for reporting later */
5715         hw->mac.ops.get_bus_info(hw);
5716
5717         /* print bus type/speed/width info */
5718         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5719                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5720                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5721                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5722                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5723                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5724                  "Unknown"),
5725                 netdev->dev_addr);
5726         ixgbe_read_pba_num_generic(hw, &part_num);
5727         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5728                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5729                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5730                          (part_num >> 8), (part_num & 0xff));
5731         else
5732                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5733                          hw->mac.type, hw->phy.type,
5734                          (part_num >> 8), (part_num & 0xff));
5735
5736         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5737                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5738                          "this card is not sufficient for optimal "
5739                          "performance.\n");
5740                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5741                          "PCI-Express slot is required.\n");
5742         }
5743
5744         /* save off EEPROM version number */
5745         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5746
5747         /* reset the hardware with the new settings */
5748         err = hw->mac.ops.start_hw(hw);
5749
5750         if (err == IXGBE_ERR_EEPROM_VERSION) {
5751                 /* We are running on a pre-production device, log a warning */
5752                 dev_warn(&pdev->dev, "This device is a pre-production "
5753                          "adapter/LOM.  Please be aware there may be issues "
5754                          "associated with your hardware.  If you are "
5755                          "experiencing problems please contact your Intel or "
5756                          "hardware representative who provided you with this "
5757                          "hardware.\n");
5758         }
5759         strcpy(netdev->name, "eth%d");
5760         err = register_netdev(netdev);
5761         if (err)
5762                 goto err_register;
5763
5764         /* carrier off reporting is important to ethtool even BEFORE open */
5765         netif_carrier_off(netdev);
5766
5767         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5768             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5769                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5770
5771 #ifdef CONFIG_IXGBE_DCA
5772         if (dca_add_requester(&pdev->dev) == 0) {
5773                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5774                 ixgbe_setup_dca(adapter);
5775         }
5776 #endif
5777         /* add san mac addr to netdev */
5778         ixgbe_add_sanmac_netdev(netdev);
5779
5780         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5781         cards_found++;
5782         return 0;
5783
5784 err_register:
5785         ixgbe_release_hw_control(adapter);
5786         ixgbe_clear_interrupt_scheme(adapter);
5787 err_sw_init:
5788 err_eeprom:
5789         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5790         del_timer_sync(&adapter->sfp_timer);
5791         cancel_work_sync(&adapter->sfp_task);
5792         cancel_work_sync(&adapter->multispeed_fiber_task);
5793         cancel_work_sync(&adapter->sfp_config_module_task);
5794         iounmap(hw->hw_addr);
5795 err_ioremap:
5796         free_netdev(netdev);
5797 err_alloc_etherdev:
5798         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5799                                      IORESOURCE_MEM));
5800 err_pci_reg:
5801 err_dma:
5802         pci_disable_device(pdev);
5803         return err;
5804 }
5805
5806 /**
5807  * ixgbe_remove - Device Removal Routine
5808  * @pdev: PCI device information struct
5809  *
5810  * ixgbe_remove is called by the PCI subsystem to alert the driver
5811  * that it should release a PCI device.  The could be caused by a
5812  * Hot-Plug event, or because the driver is going to be removed from
5813  * memory.
5814  **/
5815 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5816 {
5817         struct net_device *netdev = pci_get_drvdata(pdev);
5818         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5819
5820         set_bit(__IXGBE_DOWN, &adapter->state);
5821         /* clear the module not found bit to make sure the worker won't
5822          * reschedule
5823          */
5824         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5825         del_timer_sync(&adapter->watchdog_timer);
5826
5827         del_timer_sync(&adapter->sfp_timer);
5828         cancel_work_sync(&adapter->watchdog_task);
5829         cancel_work_sync(&adapter->sfp_task);
5830         cancel_work_sync(&adapter->multispeed_fiber_task);
5831         cancel_work_sync(&adapter->sfp_config_module_task);
5832         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5833             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5834                 cancel_work_sync(&adapter->fdir_reinit_task);
5835         flush_scheduled_work();
5836
5837 #ifdef CONFIG_IXGBE_DCA
5838         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5839                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5840                 dca_remove_requester(&pdev->dev);
5841                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5842         }
5843
5844 #endif
5845 #ifdef IXGBE_FCOE
5846         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5847                 ixgbe_cleanup_fcoe(adapter);
5848
5849 #endif /* IXGBE_FCOE */
5850
5851         /* remove the added san mac */
5852         ixgbe_del_sanmac_netdev(netdev);
5853
5854         if (netdev->reg_state == NETREG_REGISTERED)
5855                 unregister_netdev(netdev);
5856
5857         ixgbe_clear_interrupt_scheme(adapter);
5858
5859         ixgbe_release_hw_control(adapter);
5860
5861         iounmap(adapter->hw.hw_addr);
5862         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5863                                      IORESOURCE_MEM));
5864
5865         DPRINTK(PROBE, INFO, "complete\n");
5866
5867         free_netdev(netdev);
5868
5869         pci_disable_pcie_error_reporting(pdev);
5870
5871         pci_disable_device(pdev);
5872 }
5873
5874 /**
5875  * ixgbe_io_error_detected - called when PCI error is detected
5876  * @pdev: Pointer to PCI device
5877  * @state: The current pci connection state
5878  *
5879  * This function is called after a PCI bus error affecting
5880  * this device has been detected.
5881  */
5882 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5883                                                 pci_channel_state_t state)
5884 {
5885         struct net_device *netdev = pci_get_drvdata(pdev);
5886         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5887
5888         netif_device_detach(netdev);
5889
5890         if (state == pci_channel_io_perm_failure)
5891                 return PCI_ERS_RESULT_DISCONNECT;
5892
5893         if (netif_running(netdev))
5894                 ixgbe_down(adapter);
5895         pci_disable_device(pdev);
5896
5897         /* Request a slot reset. */
5898         return PCI_ERS_RESULT_NEED_RESET;
5899 }
5900
5901 /**
5902  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5903  * @pdev: Pointer to PCI device
5904  *
5905  * Restart the card from scratch, as if from a cold-boot.
5906  */
5907 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5908 {
5909         struct net_device *netdev = pci_get_drvdata(pdev);
5910         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5911         pci_ers_result_t result;
5912         int err;
5913
5914         if (pci_enable_device_mem(pdev)) {
5915                 DPRINTK(PROBE, ERR,
5916                         "Cannot re-enable PCI device after reset.\n");
5917                 result = PCI_ERS_RESULT_DISCONNECT;
5918         } else {
5919                 pci_set_master(pdev);
5920                 pci_restore_state(pdev);
5921
5922                 pci_wake_from_d3(pdev, false);
5923
5924                 ixgbe_reset(adapter);
5925                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5926                 result = PCI_ERS_RESULT_RECOVERED;
5927         }
5928
5929         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5930         if (err) {
5931                 dev_err(&pdev->dev,
5932                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5933                 /* non-fatal, continue */
5934         }
5935
5936         return result;
5937 }
5938
5939 /**
5940  * ixgbe_io_resume - called when traffic can start flowing again.
5941  * @pdev: Pointer to PCI device
5942  *
5943  * This callback is called when the error recovery driver tells us that
5944  * its OK to resume normal operation.
5945  */
5946 static void ixgbe_io_resume(struct pci_dev *pdev)
5947 {
5948         struct net_device *netdev = pci_get_drvdata(pdev);
5949         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5950
5951         if (netif_running(netdev)) {
5952                 if (ixgbe_up(adapter)) {
5953                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5954                         return;
5955                 }
5956         }
5957
5958         netif_device_attach(netdev);
5959 }
5960
5961 static struct pci_error_handlers ixgbe_err_handler = {
5962         .error_detected = ixgbe_io_error_detected,
5963         .slot_reset = ixgbe_io_slot_reset,
5964         .resume = ixgbe_io_resume,
5965 };
5966
5967 static struct pci_driver ixgbe_driver = {
5968         .name     = ixgbe_driver_name,
5969         .id_table = ixgbe_pci_tbl,
5970         .probe    = ixgbe_probe,
5971         .remove   = __devexit_p(ixgbe_remove),
5972 #ifdef CONFIG_PM
5973         .suspend  = ixgbe_suspend,
5974         .resume   = ixgbe_resume,
5975 #endif
5976         .shutdown = ixgbe_shutdown,
5977         .err_handler = &ixgbe_err_handler
5978 };
5979
5980 /**
5981  * ixgbe_init_module - Driver Registration Routine
5982  *
5983  * ixgbe_init_module is the first routine called when the driver is
5984  * loaded. All it does is register with the PCI subsystem.
5985  **/
5986 static int __init ixgbe_init_module(void)
5987 {
5988         int ret;
5989         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5990                ixgbe_driver_string, ixgbe_driver_version);
5991
5992         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5993
5994 #ifdef CONFIG_IXGBE_DCA
5995         dca_register_notify(&dca_notifier);
5996 #endif
5997
5998         ret = pci_register_driver(&ixgbe_driver);
5999         return ret;
6000 }
6001
6002 module_init(ixgbe_init_module);
6003
6004 /**
6005  * ixgbe_exit_module - Driver Exit Cleanup Routine
6006  *
6007  * ixgbe_exit_module is called just before the driver is removed
6008  * from memory.
6009  **/
6010 static void __exit ixgbe_exit_module(void)
6011 {
6012 #ifdef CONFIG_IXGBE_DCA
6013         dca_unregister_notify(&dca_notifier);
6014 #endif
6015         pci_unregister_driver(&ixgbe_driver);
6016 }
6017
6018 #ifdef CONFIG_IXGBE_DCA
6019 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6020                             void *p)
6021 {
6022         int ret_val;
6023
6024         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6025                                          __ixgbe_notify_dca);
6026
6027         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6028 }
6029
6030 #endif /* CONFIG_IXGBE_DCA */
6031 #ifdef DEBUG
6032 /**
6033  * ixgbe_get_hw_dev_name - return device name string
6034  * used by hardware layer to print debugging information
6035  **/
6036 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6037 {
6038         struct ixgbe_adapter *adapter = hw->back;
6039         return adapter->netdev->name;
6040 }
6041
6042 #endif
6043 module_exit(ixgbe_exit_module);
6044
6045 /* ixgbe_main.c */