Pileus Git - ~andy/linux/blob - drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47 #include "ixgbe_dcb_82599.h"
  48
  49 char ixgbe_driver_name[] = "ixgbe";
  50 static const char ixgbe_driver_string[] =
  51                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  52
  53 #define DRV_VERSION "2.0.44-k2"
  54 const char ixgbe_driver_version[] = DRV_VERSION;
  55 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  56
  57 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  58         [board_82598] = &ixgbe_82598_info,
  59         [board_82599] = &ixgbe_82599_info,
  60 };
  61
  62 /* ixgbe_pci_tbl - PCI Device ID Table
  63  *
  64  * Wildcard entries (PCI_ANY_ID) should come last
  65  * Last entry must be all 0s
  66  *
  67  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  68  *   Class, Class Mask, private data (not used) }
  69  */
  70 static struct pci_device_id ixgbe_pci_tbl[] = {
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  96          board_82599 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 108          board_82599 },
 109
 110         /* required last entry */
 111         {0, }
 112 };
 113 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 114
 115 #ifdef CONFIG_IXGBE_DCA
 116 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 117                             void *p);
 118 static struct notifier_block dca_notifier = {
 119         .notifier_call = ixgbe_notify_dca,
 120         .next          = NULL,
 121         .priority      = 0
 122 };
 123 #endif
 124
 125 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 126 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 127 MODULE_LICENSE("GPL");
 128 MODULE_VERSION(DRV_VERSION);
 129
 130 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 131
 132 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 133 {
 134         u32 ctrl_ext;
 135
 136         /* Let firmware take over control of h/w */
 137         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 138         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 139                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 140 }
 141
 142 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 143 {
 144         u32 ctrl_ext;
 145
 146         /* Let firmware know the driver has taken over */
 147         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 148         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 149                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 150 }
 151
 152 /*
 153  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 154  * @adapter: pointer to adapter struct
 155  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 156  * @queue: queue to map the corresponding interrupt to
 157  * @msix_vector: the vector to map to the corresponding queue
 158  *
 159  */
 160 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 161                            u8 queue, u8 msix_vector)
 162 {
 163         u32 ivar, index;
 164         struct ixgbe_hw *hw = &adapter->hw;
 165         switch (hw->mac.type) {
 166         case ixgbe_mac_82598EB:
 167                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 168                 if (direction == -1)
 169                         direction = 0;
 170                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 171                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 172                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 173                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 174                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 175                 break;
 176         case ixgbe_mac_82599EB:
 177                 if (direction == -1) {
 178                         /* other causes */
 179                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 180                         index = ((queue & 1) * 8);
 181                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 182                         ivar &= ~(0xFF << index);
 183                         ivar |= (msix_vector << index);
 184                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 185                         break;
 186                 } else {
 187                         /* tx or rx causes */
 188                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 189                         index = ((16 * (queue & 1)) + (8 * direction));
 190                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 191                         ivar &= ~(0xFF << index);
 192                         ivar |= (msix_vector << index);
 193                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 194                         break;
 195                 }
 196         default:
 197                 break;
 198         }
 199 }
 200
 201 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 202                                           u64 qmask)
 203 {
 204         u32 mask;
 205
 206         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 207                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 208                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 209         } else {
 210                 mask = (qmask & 0xFFFFFFFF);
 211                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 212                 mask = (qmask >> 32);
 213                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 214         }
 215 }
 216
 217 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 218                                              struct ixgbe_tx_buffer
 219                                              *tx_buffer_info)
 220 {
 221         tx_buffer_info->dma = 0;
 222         if (tx_buffer_info->skb) {
 223                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 224                               DMA_TO_DEVICE);
 225                 dev_kfree_skb_any(tx_buffer_info->skb);
 226                 tx_buffer_info->skb = NULL;
 227         }
 228         tx_buffer_info->time_stamp = 0;
 229         /* tx_buffer_info must be completely set up in the transmit path */
 230 }
 231
 232 /**
 233  * ixgbe_tx_is_paused - check if the tx ring is paused
 234  * @adapter: the ixgbe adapter
 235  * @tx_ring: the corresponding tx_ring
 236  *
 237  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 238  * corresponding TC of this tx_ring when checking TFCS.
 239  *
 240  * Returns : true if paused
 241  */
 242 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
 243                                       struct ixgbe_ring *tx_ring)
 244 {
 245         int tc;
 246         u32 txoff = IXGBE_TFCS_TXOFF;
 247
 248 #ifdef CONFIG_IXGBE_DCB
 249         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 250                 int reg_idx = tx_ring->reg_idx;
 251                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 252
 253                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 254                         tc = reg_idx >> 2;
 255                         txoff = IXGBE_TFCS_TXOFF0;
 256                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 257                         tc = 0;
 258                         txoff = IXGBE_TFCS_TXOFF;
 259                         if (dcb_i == 8) {
 260                                 /* TC0, TC1 */
 261                                 tc = reg_idx >> 5;
 262                                 if (tc == 2) /* TC2, TC3 */
 263                                         tc += (reg_idx - 64) >> 4;
 264                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 265                                         tc += 1 + ((reg_idx - 96) >> 3);
 266                         } else if (dcb_i == 4) {
 267                                 /* TC0, TC1 */
 268                                 tc = reg_idx >> 6;
 269                                 if (tc == 1) {
 270                                         tc += (reg_idx - 64) >> 5;
 271                                         if (tc == 2) /* TC2, TC3 */
 272                                                 tc += (reg_idx - 96) >> 4;
 273                                 }
 274                         }
 275                 }
 276                 txoff <<= tc;
 277         }
 278 #endif
 279         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 280 }
 281
 282 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 283                                        struct ixgbe_ring *tx_ring,
 284                                        unsigned int eop)
 285 {
 286         struct ixgbe_hw *hw = &adapter->hw;
 287
 288         /* Detect a transmit hang in hardware, this serializes the
 289          * check with the clearing of time_stamp and movement of eop */
 290         adapter->detect_tx_hung = false;
 291         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 292             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 293             !ixgbe_tx_is_paused(adapter, tx_ring)) {
 294                 /* detected Tx unit hang */
 295                 union ixgbe_adv_tx_desc *tx_desc;
 296                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 297                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 298                         "  Tx Queue             <%d>\n"
 299                         "  TDH, TDT             <%x>, <%x>\n"
 300                         "  next_to_use          <%x>\n"
 301                         "  next_to_clean        <%x>\n"
 302                         "tx_buffer_info[next_to_clean]\n"
 303                         "  time_stamp           <%lx>\n"
 304                         "  jiffies              <%lx>\n",
 305                         tx_ring->queue_index,
 306                         IXGBE_READ_REG(hw, tx_ring->head),
 307                         IXGBE_READ_REG(hw, tx_ring->tail),
 308                         tx_ring->next_to_use, eop,
 309                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 310                 return true;
 311         }
 312
 313         return false;
 314 }
 315
 316 #define IXGBE_MAX_TXD_PWR       14
 317 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 318
 319 /* Tx Descriptors needed, worst case */
 320 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 321                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 322 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 323         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 324
 325 static void ixgbe_tx_timeout(struct net_device *netdev);
 326
 327 /**
 328  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 329  * @q_vector: structure containing interrupt and ring information
 330  * @tx_ring: tx ring to clean
 331  **/
 332 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 333                                struct ixgbe_ring *tx_ring)
 334 {
 335         struct ixgbe_adapter *adapter = q_vector->adapter;
 336         struct net_device *netdev = adapter->netdev;
 337         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 338         struct ixgbe_tx_buffer *tx_buffer_info;
 339         unsigned int i, eop, count = 0;
 340         unsigned int total_bytes = 0, total_packets = 0;
 341
 342         i = tx_ring->next_to_clean;
 343         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 344         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 345
 346         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 347                (count < tx_ring->work_limit)) {
 348                 bool cleaned = false;
 349                 for ( ; !cleaned; count++) {
 350                         struct sk_buff *skb;
 351                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 352                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 353                         cleaned = (i == eop);
 354                         skb = tx_buffer_info->skb;
 355
 356                         if (cleaned && skb) {
 357                                 unsigned int segs, bytecount;
 358                                 unsigned int hlen = skb_headlen(skb);
 359
 360                                 /* gso_segs is currently only valid for tcp */
 361                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 362 #ifdef IXGBE_FCOE
 363                                 /* adjust for FCoE Sequence Offload */
 364                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 365                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 366                                     skb_is_gso(skb)) {
 367                                         hlen = skb_transport_offset(skb) +
 368                                                 sizeof(struct fc_frame_header) +
 369                                                 sizeof(struct fcoe_crc_eof);
 370                                         segs = DIV_ROUND_UP(skb->len - hlen,
 371                                                 skb_shinfo(skb)->gso_size);
 372                                 }
 373 #endif /* IXGBE_FCOE */
 374                                 /* multiply data chunks by size of headers */
 375                                 bytecount = ((segs - 1) * hlen) + skb->len;
 376                                 total_packets += segs;
 377                                 total_bytes += bytecount;
 378                         }
 379
 380                         ixgbe_unmap_and_free_tx_resource(adapter,
 381                                                          tx_buffer_info);
 382
 383                         tx_desc->wb.status = 0;
 384
 385                         i++;
 386                         if (i == tx_ring->count)
 387                                 i = 0;
 388                 }
 389
 390                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 391                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 392         }
 393
 394         tx_ring->next_to_clean = i;
 395
 396 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 397         if (unlikely(count && netif_carrier_ok(netdev) &&
 398                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 399                 /* Make sure that anybody stopping the queue after this
 400                  * sees the new next_to_clean.
 401                  */
 402                 smp_mb();
 403                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 404                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 405                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 406                         ++adapter->restart_queue;
 407                 }
 408         }
 409
 410         if (adapter->detect_tx_hung) {
 411                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 412                         /* schedule immediate reset if we believe we hung */
 413                         DPRINTK(PROBE, INFO,
 414                                 "tx hang %d detected, resetting adapter\n",
 415                                 adapter->tx_timeout_count + 1);
 416                         ixgbe_tx_timeout(adapter->netdev);
 417                 }
 418         }
 419
 420         /* re-arm the interrupt */
 421         if (count >= tx_ring->work_limit)
 422                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 423
 424         tx_ring->total_bytes += total_bytes;
 425         tx_ring->total_packets += total_packets;
 426         tx_ring->stats.packets += total_packets;
 427         tx_ring->stats.bytes += total_bytes;
 428         netdev->stats.tx_bytes += total_bytes;
 429         netdev->stats.tx_packets += total_packets;
 430         return (count < tx_ring->work_limit);
 431 }
 432
 433 #ifdef CONFIG_IXGBE_DCA
 434 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 435                                 struct ixgbe_ring *rx_ring)
 436 {
 437         u32 rxctrl;
 438         int cpu = get_cpu();
 439         int q = rx_ring - adapter->rx_ring;
 440
 441         if (rx_ring->cpu != cpu) {
 442                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 443                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 444                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 445                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 446                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 447                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 448                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 449                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 450                 }
 451                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 452                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 453                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 454                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 455                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 456                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 457                 rx_ring->cpu = cpu;
 458         }
 459         put_cpu();
 460 }
 461
 462 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 463                                 struct ixgbe_ring *tx_ring)
 464 {
 465         u32 txctrl;
 466         int cpu = get_cpu();
 467         int q = tx_ring - adapter->tx_ring;
 468         struct ixgbe_hw *hw = &adapter->hw;
 469
 470         if (tx_ring->cpu != cpu) {
 471                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 472                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 473                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 474                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 475                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 476                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 477                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 478                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 479                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 480                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 481                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 482                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 483                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 484                 }
 485                 tx_ring->cpu = cpu;
 486         }
 487         put_cpu();
 488 }
 489
 490 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 491 {
 492         int i;
 493
 494         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 495                 return;
 496
 497         /* always use CB2 mode, difference is masked in the CB driver */
 498         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 499
 500         for (i = 0; i < adapter->num_tx_queues; i++) {
 501                 adapter->tx_ring[i].cpu = -1;
 502                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 503         }
 504         for (i = 0; i < adapter->num_rx_queues; i++) {
 505                 adapter->rx_ring[i].cpu = -1;
 506                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 507         }
 508 }
 509
 510 static int __ixgbe_notify_dca(struct device *dev, void *data)
 511 {
 512         struct net_device *netdev = dev_get_drvdata(dev);
 513         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 514         unsigned long event = *(unsigned long *)data;
 515
 516         switch (event) {
 517         case DCA_PROVIDER_ADD:
 518                 /* if we're already enabled, don't do it again */
 519                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 520                         break;
 521                 if (dca_add_requester(dev) == 0) {
 522                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 523                         ixgbe_setup_dca(adapter);
 524                         break;
 525                 }
 526                 /* Fall Through since DCA is disabled. */
 527         case DCA_PROVIDER_REMOVE:
 528                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 529                         dca_remove_requester(dev);
 530                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 531                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 532                 }
 533                 break;
 534         }
 535
 536         return 0;
 537 }
 538
 539 #endif /* CONFIG_IXGBE_DCA */
 540 /**
 541  * ixgbe_receive_skb - Send a completed packet up the stack
 542  * @adapter: board private structure
 543  * @skb: packet to send up
 544  * @status: hardware indication of status of receive
 545  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 546  * @rx_desc: rx descriptor
 547  **/
 548 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 549                               struct sk_buff *skb, u8 status,
 550                               struct ixgbe_ring *ring,
 551                               union ixgbe_adv_rx_desc *rx_desc)
 552 {
 553         struct ixgbe_adapter *adapter = q_vector->adapter;
 554         struct napi_struct *napi = &q_vector->napi;
 555         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 556         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 557
 558         skb_record_rx_queue(skb, ring->queue_index);
 559         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 560                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 561                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 562                 else
 563                         napi_gro_receive(napi, skb);
 564         } else {
 565                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 566                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 567                 else
 568                         netif_rx(skb);
 569         }
 570 }
 571
 572 /**
 573  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 574  * @adapter: address of board private structure
 575  * @status_err: hardware indication of status of receive
 576  * @skb: skb currently being received and modified
 577  **/
 578 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 579                                      union ixgbe_adv_rx_desc *rx_desc,
 580                                      struct sk_buff *skb)
 581 {
 582         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 583
 584         skb->ip_summed = CHECKSUM_NONE;
 585
 586         /* Rx csum disabled */
 587         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 588                 return;
 589
 590         /* if IP and error */
 591         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 592             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 593                 adapter->hw_csum_rx_error++;
 594                 return;
 595         }
 596
 597         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 598                 return;
 599
 600         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 601                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 602
 603                 /*
 604                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 605                  * checksum errors.
 606                  */
 607                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 608                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 609                         return;
 610
 611                 adapter->hw_csum_rx_error++;
 612                 return;
 613         }
 614
 615         /* It must be a TCP or UDP packet with a valid checksum */
 616         skb->ip_summed = CHECKSUM_UNNECESSARY;
 617         adapter->hw_csum_rx_good++;
 618 }
 619
 620 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 621                                          struct ixgbe_ring *rx_ring, u32 val)
 622 {
 623         /*
 624          * Force memory writes to complete before letting h/w
 625          * know there are new descriptors to fetch.  (Only
 626          * applicable for weak-ordered memory model archs,
 627          * such as IA-64).
 628          */
 629         wmb();
 630         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 631 }
 632
 633 /**
 634  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 635  * @adapter: address of board private structure
 636  **/
 637 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 638                                    struct ixgbe_ring *rx_ring,
 639                                    int cleaned_count)
 640 {
 641         struct pci_dev *pdev = adapter->pdev;
 642         union ixgbe_adv_rx_desc *rx_desc;
 643         struct ixgbe_rx_buffer *bi;
 644         unsigned int i;
 645
 646         i = rx_ring->next_to_use;
 647         bi = &rx_ring->rx_buffer_info[i];
 648
 649         while (cleaned_count--) {
 650                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 651
 652                 if (!bi->page_dma &&
 653                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 654                         if (!bi->page) {
 655                                 bi->page = alloc_page(GFP_ATOMIC);
 656                                 if (!bi->page) {
 657                                         adapter->alloc_rx_page_failed++;
 658                                         goto no_buffers;
 659                                 }
 660                                 bi->page_offset = 0;
 661                         } else {
 662                                 /* use a half page if we're re-using */
 663                                 bi->page_offset ^= (PAGE_SIZE / 2);
 664                         }
 665
 666                         bi->page_dma = pci_map_page(pdev, bi->page,
 667                                                     bi->page_offset,
 668                                                     (PAGE_SIZE / 2),
 669                                                     PCI_DMA_FROMDEVICE);
 670                 }
 671
 672                 if (!bi->skb) {
 673                         struct sk_buff *skb;
 674                         skb = netdev_alloc_skb_ip_align(adapter->netdev,
 675                                                         rx_ring->rx_buf_len);
 676
 677                         if (!skb) {
 678                                 adapter->alloc_rx_buff_failed++;
 679                                 goto no_buffers;
 680                         }
 681
 682                         bi->skb = skb;
 683                         bi->dma = pci_map_single(pdev, skb->data,
 684                                                  rx_ring->rx_buf_len,
 685                                                  PCI_DMA_FROMDEVICE);
 686                 }
 687                 /* Refresh the desc even if buffer_addrs didn't change because
 688                  * each write-back erases this info. */
 689                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 690                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 691                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 692                 } else {
 693                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 694                 }
 695
 696                 i++;
 697                 if (i == rx_ring->count)
 698                         i = 0;
 699                 bi = &rx_ring->rx_buffer_info[i];
 700         }
 701
 702 no_buffers:
 703         if (rx_ring->next_to_use != i) {
 704                 rx_ring->next_to_use = i;
 705                 if (i-- == 0)
 706                         i = (rx_ring->count - 1);
 707
 708                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 709         }
 710 }
 711
 712 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 713 {
 714         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 715 }
 716
 717 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 718 {
 719         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 720 }
 721
 722 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 723 {
 724         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 725                 IXGBE_RXDADV_RSCCNT_MASK) >>
 726                 IXGBE_RXDADV_RSCCNT_SHIFT;
 727 }
 728
 729 /**
 730  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 731  * @skb: pointer to the last skb in the rsc queue
 732  *
 733  * This function changes a queue full of hw rsc buffers into a completed
 734  * packet.  It uses the ->prev pointers to find the first packet and then
 735  * turns it into the frag list owner.
 736  **/
 737 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 738 {
 739         unsigned int frag_list_size = 0;
 740
 741         while (skb->prev) {
 742                 struct sk_buff *prev = skb->prev;
 743                 frag_list_size += skb->len;
 744                 skb->prev = NULL;
 745                 skb = prev;
 746         }
 747
 748         skb_shinfo(skb)->frag_list = skb->next;
 749         skb->next = NULL;
 750         skb->len += frag_list_size;
 751         skb->data_len += frag_list_size;
 752         skb->truesize += frag_list_size;
 753         return skb;
 754 }
 755
 756 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 757                                struct ixgbe_ring *rx_ring,
 758                                int *work_done, int work_to_do)
 759 {
 760         struct ixgbe_adapter *adapter = q_vector->adapter;
 761         struct net_device *netdev = adapter->netdev;
 762         struct pci_dev *pdev = adapter->pdev;
 763         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 764         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 765         struct sk_buff *skb;
 766         unsigned int i, rsc_count = 0;
 767         u32 len, staterr;
 768         u16 hdr_info;
 769         bool cleaned = false;
 770         int cleaned_count = 0;
 771         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 772 #ifdef IXGBE_FCOE
 773         int ddp_bytes = 0;
 774 #endif /* IXGBE_FCOE */
 775
 776         i = rx_ring->next_to_clean;
 777         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 778         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 779         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 780
 781         while (staterr & IXGBE_RXD_STAT_DD) {
 782                 u32 upper_len = 0;
 783                 if (*work_done >= work_to_do)
 784                         break;
 785                 (*work_done)++;
 786
 787                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 788                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 789                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 790                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 791                         if (hdr_info & IXGBE_RXDADV_SPH)
 792                                 adapter->rx_hdr_split++;
 793                         if (len > IXGBE_RX_HDR_SIZE)
 794                                 len = IXGBE_RX_HDR_SIZE;
 795                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 796                 } else {
 797                         len = le16_to_cpu(rx_desc->wb.upper.length);
 798                 }
 799
 800                 cleaned = true;
 801                 skb = rx_buffer_info->skb;
 802                 prefetch(skb->data - NET_IP_ALIGN);
 803                 rx_buffer_info->skb = NULL;
 804
 805                 if (rx_buffer_info->dma) {
 806                         pci_unmap_single(pdev, rx_buffer_info->dma,
 807                                          rx_ring->rx_buf_len,
 808                                          PCI_DMA_FROMDEVICE);
 809                         rx_buffer_info->dma = 0;
 810                         skb_put(skb, len);
 811                 }
 812
 813                 if (upper_len) {
 814                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 815                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 816                         rx_buffer_info->page_dma = 0;
 817                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 818                                            rx_buffer_info->page,
 819                                            rx_buffer_info->page_offset,
 820                                            upper_len);
 821
 822                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 823                             (page_count(rx_buffer_info->page) != 1))
 824                                 rx_buffer_info->page = NULL;
 825                         else
 826                                 get_page(rx_buffer_info->page);
 827
 828                         skb->len += upper_len;
 829                         skb->data_len += upper_len;
 830                         skb->truesize += upper_len;
 831                 }
 832
 833                 i++;
 834                 if (i == rx_ring->count)
 835                         i = 0;
 836
 837                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 838                 prefetch(next_rxd);
 839                 cleaned_count++;
 840
 841                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 842                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 843
 844                 if (rsc_count) {
 845                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 846                                      IXGBE_RXDADV_NEXTP_SHIFT;
 847                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 848                         rx_ring->rsc_count += (rsc_count - 1);
 849                 } else {
 850                         next_buffer = &rx_ring->rx_buffer_info[i];
 851                 }
 852
 853                 if (staterr & IXGBE_RXD_STAT_EOP) {
 854                         if (skb->prev)
 855                                 skb = ixgbe_transform_rsc_queue(skb);
 856                         rx_ring->stats.packets++;
 857                         rx_ring->stats.bytes += skb->len;
 858                 } else {
 859                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 860                                 rx_buffer_info->skb = next_buffer->skb;
 861                                 rx_buffer_info->dma = next_buffer->dma;
 862                                 next_buffer->skb = skb;
 863                                 next_buffer->dma = 0;
 864                         } else {
 865                                 skb->next = next_buffer->skb;
 866                                 skb->next->prev = skb;
 867                         }
 868                         adapter->non_eop_descs++;
 869                         goto next_desc;
 870                 }
 871
 872                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 873                         dev_kfree_skb_irq(skb);
 874                         goto next_desc;
 875                 }
 876
 877                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 878
 879                 /* probably a little skewed due to removing CRC */
 880                 total_rx_bytes += skb->len;
 881                 total_rx_packets++;
 882
 883                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 884 #ifdef IXGBE_FCOE
 885                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 886                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 887                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 888                         if (!ddp_bytes)
 889                                 goto next_desc;
 890                 }
 891 #endif /* IXGBE_FCOE */
 892                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 893
 894 next_desc:
 895                 rx_desc->wb.upper.status_error = 0;
 896
 897                 /* return some buffers to hardware, one at a time is too slow */
 898                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 899                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 900                         cleaned_count = 0;
 901                 }
 902
 903                 /* use prefetched values */
 904                 rx_desc = next_rxd;
 905                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 906
 907                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 908         }
 909
 910         rx_ring->next_to_clean = i;
 911         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 912
 913         if (cleaned_count)
 914                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 915
 916 #ifdef IXGBE_FCOE
 917         /* include DDPed FCoE data */
 918         if (ddp_bytes > 0) {
 919                 unsigned int mss;
 920
 921                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 922                         sizeof(struct fc_frame_header) -
 923                         sizeof(struct fcoe_crc_eof);
 924                 if (mss > 512)
 925                         mss &= ~511;
 926                 total_rx_bytes += ddp_bytes;
 927                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 928         }
 929 #endif /* IXGBE_FCOE */
 930
 931         rx_ring->total_packets += total_rx_packets;
 932         rx_ring->total_bytes += total_rx_bytes;
 933         netdev->stats.rx_bytes += total_rx_bytes;
 934         netdev->stats.rx_packets += total_rx_packets;
 935
 936         return cleaned;
 937 }
 938
 939 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 940 /**
 941  * ixgbe_configure_msix - Configure MSI-X hardware
 942  * @adapter: board private structure
 943  *
 944  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 945  * interrupts.
 946  **/
 947 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 948 {
 949         struct ixgbe_q_vector *q_vector;
 950         int i, j, q_vectors, v_idx, r_idx;
 951         u32 mask;
 952
 953         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 954
 955         /*
 956          * Populate the IVAR table and set the ITR values to the
 957          * corresponding register.
 958          */
 959         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 960                 q_vector = adapter->q_vector[v_idx];
 961                 /* XXX for_each_bit(...) */
 962                 r_idx = find_first_bit(q_vector->rxr_idx,
 963                                        adapter->num_rx_queues);
 964
 965                 for (i = 0; i < q_vector->rxr_count; i++) {
 966                         j = adapter->rx_ring[r_idx].reg_idx;
 967                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 968                         r_idx = find_next_bit(q_vector->rxr_idx,
 969                                               adapter->num_rx_queues,
 970                                               r_idx + 1);
 971                 }
 972                 r_idx = find_first_bit(q_vector->txr_idx,
 973                                        adapter->num_tx_queues);
 974
 975                 for (i = 0; i < q_vector->txr_count; i++) {
 976                         j = adapter->tx_ring[r_idx].reg_idx;
 977                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 978                         r_idx = find_next_bit(q_vector->txr_idx,
 979                                               adapter->num_tx_queues,
 980                                               r_idx + 1);
 981                 }
 982
 983                 if (q_vector->txr_count && !q_vector->rxr_count)
 984                         /* tx only */
 985                         q_vector->eitr = adapter->tx_eitr_param;
 986                 else if (q_vector->rxr_count)
 987                         /* rx or mixed */
 988                         q_vector->eitr = adapter->rx_eitr_param;
 989
 990                 ixgbe_write_eitr(q_vector);
 991         }
 992
 993         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 994                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 995                                v_idx);
 996         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 997                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 998         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 999
1000         /* set up to autoclear timer, and the vectors */
1001         mask = IXGBE_EIMS_ENABLE_MASK;
1002         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1003         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1004 }
1005
1006 enum latency_range {
1007         lowest_latency = 0,
1008         low_latency = 1,
1009         bulk_latency = 2,
1010         latency_invalid = 255
1011 };
1012
1013 /**
1014  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1015  * @adapter: pointer to adapter
1016  * @eitr: eitr setting (ints per sec) to give last timeslice
1017  * @itr_setting: current throttle rate in ints/second
1018  * @packets: the number of packets during this measurement interval
1019  * @bytes: the number of bytes during this measurement interval
1020  *
1021  *      Stores a new ITR value based on packets and byte
1022  *      counts during the last interrupt.  The advantage of per interrupt
1023  *      computation is faster updates and more accurate ITR for the current
1024  *      traffic pattern.  Constants in this function were computed
1025  *      based on theoretical maximum wire speed and thresholds were set based
1026  *      on testing data as well as attempting to minimize response time
1027  *      while increasing bulk throughput.
1028  *      this functionality is controlled by the InterruptThrottleRate module
1029  *      parameter (see ixgbe_param.c)
1030  **/
1031 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1032                            u32 eitr, u8 itr_setting,
1033                            int packets, int bytes)
1034 {
1035         unsigned int retval = itr_setting;
1036         u32 timepassed_us;
1037         u64 bytes_perint;
1038
1039         if (packets == 0)
1040                 goto update_itr_done;
1041
1042
1043         /* simple throttlerate management
1044          *    0-20MB/s lowest (100000 ints/s)
1045          *   20-100MB/s low   (20000 ints/s)
1046          *  100-1249MB/s bulk (8000 ints/s)
1047          */
1048         /* what was last interrupt timeslice? */
1049         timepassed_us = 1000000/eitr;
1050         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1051
1052         switch (itr_setting) {
1053         case lowest_latency:
1054                 if (bytes_perint > adapter->eitr_low)
1055                         retval = low_latency;
1056                 break;
1057         case low_latency:
1058                 if (bytes_perint > adapter->eitr_high)
1059                         retval = bulk_latency;
1060                 else if (bytes_perint <= adapter->eitr_low)
1061                         retval = lowest_latency;
1062                 break;
1063         case bulk_latency:
1064                 if (bytes_perint <= adapter->eitr_high)
1065                         retval = low_latency;
1066                 break;
1067         }
1068
1069 update_itr_done:
1070         return retval;
1071 }
1072
1073 /**
1074  * ixgbe_write_eitr - write EITR register in hardware specific way
1075  * @q_vector: structure containing interrupt and ring information
1076  *
1077  * This function is made to be called by ethtool and by the driver
1078  * when it needs to update EITR registers at runtime.  Hardware
1079  * specific quirks/differences are taken care of here.
1080  */
1081 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1082 {
1083         struct ixgbe_adapter *adapter = q_vector->adapter;
1084         struct ixgbe_hw *hw = &adapter->hw;
1085         int v_idx = q_vector->v_idx;
1086         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1087
1088         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1089                 /* must write high and low 16 bits to reset counter */
1090                 itr_reg |= (itr_reg << 16);
1091         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1092                 /*
1093                  * set the WDIS bit to not clear the timer bits and cause an
1094                  * immediate assertion of the interrupt
1095                  */
1096                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1097         }
1098         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1099 }
1100
1101 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1102 {
1103         struct ixgbe_adapter *adapter = q_vector->adapter;
1104         u32 new_itr;
1105         u8 current_itr, ret_itr;
1106         int i, r_idx;
1107         struct ixgbe_ring *rx_ring, *tx_ring;
1108
1109         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1110         for (i = 0; i < q_vector->txr_count; i++) {
1111                 tx_ring = &(adapter->tx_ring[r_idx]);
1112                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1113                                            q_vector->tx_itr,
1114                                            tx_ring->total_packets,
1115                                            tx_ring->total_bytes);
1116                 /* if the result for this queue would decrease interrupt
1117                  * rate for this vector then use that result */
1118                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1119                                     q_vector->tx_itr - 1 : ret_itr);
1120                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1121                                       r_idx + 1);
1122         }
1123
1124         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1125         for (i = 0; i < q_vector->rxr_count; i++) {
1126                 rx_ring = &(adapter->rx_ring[r_idx]);
1127                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1128                                            q_vector->rx_itr,
1129                                            rx_ring->total_packets,
1130                                            rx_ring->total_bytes);
1131                 /* if the result for this queue would decrease interrupt
1132                  * rate for this vector then use that result */
1133                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1134                                     q_vector->rx_itr - 1 : ret_itr);
1135                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1136                                       r_idx + 1);
1137         }
1138
1139         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1140
1141         switch (current_itr) {
1142         /* counts and packets in update_itr are dependent on these numbers */
1143         case lowest_latency:
1144                 new_itr = 100000;
1145                 break;
1146         case low_latency:
1147                 new_itr = 20000; /* aka hwitr = ~200 */
1148                 break;
1149         case bulk_latency:
1150         default:
1151                 new_itr = 8000;
1152                 break;
1153         }
1154
1155         if (new_itr != q_vector->eitr) {
1156                 /* do an exponential smoothing */
1157                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1158
1159                 /* save the algorithm value here, not the smoothed one */
1160                 q_vector->eitr = new_itr;
1161
1162                 ixgbe_write_eitr(q_vector);
1163         }
1164
1165         return;
1166 }
1167
1168 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1169 {
1170         struct ixgbe_hw *hw = &adapter->hw;
1171
1172         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1173             (eicr & IXGBE_EICR_GPI_SDP1)) {
1174                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1175                 /* write to clear the interrupt */
1176                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1177         }
1178 }
1179
1180 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1181 {
1182         struct ixgbe_hw *hw = &adapter->hw;
1183
1184         if (eicr & IXGBE_EICR_GPI_SDP1) {
1185                 /* Clear the interrupt */
1186                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1187                 schedule_work(&adapter->multispeed_fiber_task);
1188         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1189                 /* Clear the interrupt */
1190                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1191                 schedule_work(&adapter->sfp_config_module_task);
1192         } else {
1193                 /* Interrupt isn't for us... */
1194                 return;
1195         }
1196 }
1197
1198 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1199 {
1200         struct ixgbe_hw *hw = &adapter->hw;
1201
1202         adapter->lsc_int++;
1203         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1204         adapter->link_check_timeout = jiffies;
1205         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1206                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1207                 schedule_work(&adapter->watchdog_task);
1208         }
1209 }
1210
1211 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1212 {
1213         struct net_device *netdev = data;
1214         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1215         struct ixgbe_hw *hw = &adapter->hw;
1216         u32 eicr;
1217
1218         /*
1219          * Workaround for Silicon errata.  Use clear-by-write instead
1220          * of clear-by-read.  Reading with EICS will return the
1221          * interrupt causes without clearing, which later be done
1222          * with the write to EICR.
1223          */
1224         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1225         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1226
1227         if (eicr & IXGBE_EICR_LSC)
1228                 ixgbe_check_lsc(adapter);
1229
1230         if (hw->mac.type == ixgbe_mac_82598EB)
1231                 ixgbe_check_fan_failure(adapter, eicr);
1232
1233         if (hw->mac.type == ixgbe_mac_82599EB) {
1234                 ixgbe_check_sfp_event(adapter, eicr);
1235
1236                 /* Handle Flow Director Full threshold interrupt */
1237                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1238                         int i;
1239                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1240                         /* Disable transmits before FDIR Re-initialization */
1241                         netif_tx_stop_all_queues(netdev);
1242                         for (i = 0; i < adapter->num_tx_queues; i++) {
1243                                 struct ixgbe_ring *tx_ring =
1244                                                            &adapter->tx_ring[i];
1245                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1246                                                        &tx_ring->reinit_state))
1247                                         schedule_work(&adapter->fdir_reinit_task);
1248                         }
1249                 }
1250         }
1251         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1252                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1253
1254         return IRQ_HANDLED;
1255 }
1256
1257 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1258                                            u64 qmask)
1259 {
1260         u32 mask;
1261
1262         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1263                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1264                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1265         } else {
1266                 mask = (qmask & 0xFFFFFFFF);
1267                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1268                 mask = (qmask >> 32);
1269                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1270         }
1271         /* skip the flush */
1272 }
1273
1274 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1275                                             u64 qmask)
1276 {
1277         u32 mask;
1278
1279         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1280                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1281                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1282         } else {
1283                 mask = (qmask & 0xFFFFFFFF);
1284                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1285                 mask = (qmask >> 32);
1286                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1287         }
1288         /* skip the flush */
1289 }
1290
1291 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1292 {
1293         struct ixgbe_q_vector *q_vector = data;
1294         struct ixgbe_adapter  *adapter = q_vector->adapter;
1295         struct ixgbe_ring     *tx_ring;
1296         int i, r_idx;
1297
1298         if (!q_vector->txr_count)
1299                 return IRQ_HANDLED;
1300
1301         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1302         for (i = 0; i < q_vector->txr_count; i++) {
1303                 tx_ring = &(adapter->tx_ring[r_idx]);
1304                 tx_ring->total_bytes = 0;
1305                 tx_ring->total_packets = 0;
1306                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1307                                       r_idx + 1);
1308         }
1309
1310         /* disable interrupts on this vector only */
1311         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1312         napi_schedule(&q_vector->napi);
1313
1314         return IRQ_HANDLED;
1315 }
1316
1317 /**
1318  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1319  * @irq: unused
1320  * @data: pointer to our q_vector struct for this interrupt vector
1321  **/
1322 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1323 {
1324         struct ixgbe_q_vector *q_vector = data;
1325         struct ixgbe_adapter  *adapter = q_vector->adapter;
1326         struct ixgbe_ring  *rx_ring;
1327         int r_idx;
1328         int i;
1329
1330         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1331         for (i = 0;  i < q_vector->rxr_count; i++) {
1332                 rx_ring = &(adapter->rx_ring[r_idx]);
1333                 rx_ring->total_bytes = 0;
1334                 rx_ring->total_packets = 0;
1335                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1336                                       r_idx + 1);
1337         }
1338
1339         if (!q_vector->rxr_count)
1340                 return IRQ_HANDLED;
1341
1342         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1343         rx_ring = &(adapter->rx_ring[r_idx]);
1344         /* disable interrupts on this vector only */
1345         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1346         napi_schedule(&q_vector->napi);
1347
1348         return IRQ_HANDLED;
1349 }
1350
1351 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1352 {
1353         struct ixgbe_q_vector *q_vector = data;
1354         struct ixgbe_adapter  *adapter = q_vector->adapter;
1355         struct ixgbe_ring  *ring;
1356         int r_idx;
1357         int i;
1358
1359         if (!q_vector->txr_count && !q_vector->rxr_count)
1360                 return IRQ_HANDLED;
1361
1362         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1363         for (i = 0; i < q_vector->txr_count; i++) {
1364                 ring = &(adapter->tx_ring[r_idx]);
1365                 ring->total_bytes = 0;
1366                 ring->total_packets = 0;
1367                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1368                                       r_idx + 1);
1369         }
1370
1371         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1372         for (i = 0; i < q_vector->rxr_count; i++) {
1373                 ring = &(adapter->rx_ring[r_idx]);
1374                 ring->total_bytes = 0;
1375                 ring->total_packets = 0;
1376                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1377                                       r_idx + 1);
1378         }
1379
1380         /* disable interrupts on this vector only */
1381         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1382         napi_schedule(&q_vector->napi);
1383
1384         return IRQ_HANDLED;
1385 }
1386
1387 /**
1388  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1389  * @napi: napi struct with our devices info in it
1390  * @budget: amount of work driver is allowed to do this pass, in packets
1391  *
1392  * This function is optimized for cleaning one queue only on a single
1393  * q_vector!!!
1394  **/
1395 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1396 {
1397         struct ixgbe_q_vector *q_vector =
1398                                container_of(napi, struct ixgbe_q_vector, napi);
1399         struct ixgbe_adapter *adapter = q_vector->adapter;
1400         struct ixgbe_ring *rx_ring = NULL;
1401         int work_done = 0;
1402         long r_idx;
1403
1404         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1405         rx_ring = &(adapter->rx_ring[r_idx]);
1406 #ifdef CONFIG_IXGBE_DCA
1407         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1408                 ixgbe_update_rx_dca(adapter, rx_ring);
1409 #endif
1410
1411         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1412
1413         /* If all Rx work done, exit the polling mode */
1414         if (work_done < budget) {
1415                 napi_complete(napi);
1416                 if (adapter->rx_itr_setting & 1)
1417                         ixgbe_set_itr_msix(q_vector);
1418                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1419                         ixgbe_irq_enable_queues(adapter,
1420                                                 ((u64)1 << q_vector->v_idx));
1421         }
1422
1423         return work_done;
1424 }
1425
1426 /**
1427  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1428  * @napi: napi struct with our devices info in it
1429  * @budget: amount of work driver is allowed to do this pass, in packets
1430  *
1431  * This function will clean more than one rx queue associated with a
1432  * q_vector.
1433  **/
1434 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1435 {
1436         struct ixgbe_q_vector *q_vector =
1437                                container_of(napi, struct ixgbe_q_vector, napi);
1438         struct ixgbe_adapter *adapter = q_vector->adapter;
1439         struct ixgbe_ring *ring = NULL;
1440         int work_done = 0, i;
1441         long r_idx;
1442         bool tx_clean_complete = true;
1443
1444         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1445         for (i = 0; i < q_vector->txr_count; i++) {
1446                 ring = &(adapter->tx_ring[r_idx]);
1447 #ifdef CONFIG_IXGBE_DCA
1448                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1449                         ixgbe_update_tx_dca(adapter, ring);
1450 #endif
1451                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1452                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1453                                       r_idx + 1);
1454         }
1455
1456         /* attempt to distribute budget to each queue fairly, but don't allow
1457          * the budget to go below 1 because we'll exit polling */
1458         budget /= (q_vector->rxr_count ?: 1);
1459         budget = max(budget, 1);
1460         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1461         for (i = 0; i < q_vector->rxr_count; i++) {
1462                 ring = &(adapter->rx_ring[r_idx]);
1463 #ifdef CONFIG_IXGBE_DCA
1464                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1465                         ixgbe_update_rx_dca(adapter, ring);
1466 #endif
1467                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1468                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1469                                       r_idx + 1);
1470         }
1471
1472         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1473         ring = &(adapter->rx_ring[r_idx]);
1474         /* If all Rx work done, exit the polling mode */
1475         if (work_done < budget) {
1476                 napi_complete(napi);
1477                 if (adapter->rx_itr_setting & 1)
1478                         ixgbe_set_itr_msix(q_vector);
1479                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1480                         ixgbe_irq_enable_queues(adapter,
1481                                                 ((u64)1 << q_vector->v_idx));
1482                 return 0;
1483         }
1484
1485         return work_done;
1486 }
1487
1488 /**
1489  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1490  * @napi: napi struct with our devices info in it
1491  * @budget: amount of work driver is allowed to do this pass, in packets
1492  *
1493  * This function is optimized for cleaning one queue only on a single
1494  * q_vector!!!
1495  **/
1496 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1497 {
1498         struct ixgbe_q_vector *q_vector =
1499                                container_of(napi, struct ixgbe_q_vector, napi);
1500         struct ixgbe_adapter *adapter = q_vector->adapter;
1501         struct ixgbe_ring *tx_ring = NULL;
1502         int work_done = 0;
1503         long r_idx;
1504
1505         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1506         tx_ring = &(adapter->tx_ring[r_idx]);
1507 #ifdef CONFIG_IXGBE_DCA
1508         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1509                 ixgbe_update_tx_dca(adapter, tx_ring);
1510 #endif
1511
1512         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1513                 work_done = budget;
1514
1515         /* If all Tx work done, exit the polling mode */
1516         if (work_done < budget) {
1517                 napi_complete(napi);
1518                 if (adapter->tx_itr_setting & 1)
1519                         ixgbe_set_itr_msix(q_vector);
1520                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1521                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1522         }
1523
1524         return work_done;
1525 }
1526
1527 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1528                                      int r_idx)
1529 {
1530         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1531
1532         set_bit(r_idx, q_vector->rxr_idx);
1533         q_vector->rxr_count++;
1534 }
1535
1536 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1537                                      int t_idx)
1538 {
1539         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1540
1541         set_bit(t_idx, q_vector->txr_idx);
1542         q_vector->txr_count++;
1543 }
1544
1545 /**
1546  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1547  * @adapter: board private structure to initialize
1548  * @vectors: allotted vector count for descriptor rings
1549  *
1550  * This function maps descriptor rings to the queue-specific vectors
1551  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1552  * one vector per ring/queue, but on a constrained vector budget, we
1553  * group the rings as "efficiently" as possible.  You would add new
1554  * mapping configurations in here.
1555  **/
1556 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1557                                       int vectors)
1558 {
1559         int v_start = 0;
1560         int rxr_idx = 0, txr_idx = 0;
1561         int rxr_remaining = adapter->num_rx_queues;
1562         int txr_remaining = adapter->num_tx_queues;
1563         int i, j;
1564         int rqpv, tqpv;
1565         int err = 0;
1566
1567         /* No mapping required if MSI-X is disabled. */
1568         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1569                 goto out;
1570
1571         /*
1572          * The ideal configuration...
1573          * We have enough vectors to map one per queue.
1574          */
1575         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1576                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1577                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1578
1579                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1580                         map_vector_to_txq(adapter, v_start, txr_idx);
1581
1582                 goto out;
1583         }
1584
1585         /*
1586          * If we don't have enough vectors for a 1-to-1
1587          * mapping, we'll have to group them so there are
1588          * multiple queues per vector.
1589          */
1590         /* Re-adjusting *qpv takes care of the remainder. */
1591         for (i = v_start; i < vectors; i++) {
1592                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1593                 for (j = 0; j < rqpv; j++) {
1594                         map_vector_to_rxq(adapter, i, rxr_idx);
1595                         rxr_idx++;
1596                         rxr_remaining--;
1597                 }
1598         }
1599         for (i = v_start; i < vectors; i++) {
1600                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1601                 for (j = 0; j < tqpv; j++) {
1602                         map_vector_to_txq(adapter, i, txr_idx);
1603                         txr_idx++;
1604                         txr_remaining--;
1605                 }
1606         }
1607
1608 out:
1609         return err;
1610 }
1611
1612 /**
1613  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1614  * @adapter: board private structure
1615  *
1616  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1617  * interrupts from the kernel.
1618  **/
1619 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1620 {
1621         struct net_device *netdev = adapter->netdev;
1622         irqreturn_t (*handler)(int, void *);
1623         int i, vector, q_vectors, err;
1624         int ri=0, ti=0;
1625
1626         /* Decrement for Other and TCP Timer vectors */
1627         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1628
1629         /* Map the Tx/Rx rings to the vectors we were allotted. */
1630         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1631         if (err)
1632                 goto out;
1633
1634 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1635                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1636                          &ixgbe_msix_clean_many)
1637         for (vector = 0; vector < q_vectors; vector++) {
1638                 handler = SET_HANDLER(adapter->q_vector[vector]);
1639
1640                 if(handler == &ixgbe_msix_clean_rx) {
1641                         sprintf(adapter->name[vector], "%s-%s-%d",
1642                                 netdev->name, "rx", ri++);
1643                 }
1644                 else if(handler == &ixgbe_msix_clean_tx) {
1645                         sprintf(adapter->name[vector], "%s-%s-%d",
1646                                 netdev->name, "tx", ti++);
1647                 }
1648                 else
1649                         sprintf(adapter->name[vector], "%s-%s-%d",
1650                                 netdev->name, "TxRx", vector);
1651
1652                 err = request_irq(adapter->msix_entries[vector].vector,
1653                                   handler, 0, adapter->name[vector],
1654                                   adapter->q_vector[vector]);
1655                 if (err) {
1656                         DPRINTK(PROBE, ERR,
1657                                 "request_irq failed for MSIX interrupt "
1658                                 "Error: %d\n", err);
1659                         goto free_queue_irqs;
1660                 }
1661         }
1662
1663         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1664         err = request_irq(adapter->msix_entries[vector].vector,
1665                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1666         if (err) {
1667                 DPRINTK(PROBE, ERR,
1668                         "request_irq for msix_lsc failed: %d\n", err);
1669                 goto free_queue_irqs;
1670         }
1671
1672         return 0;
1673
1674 free_queue_irqs:
1675         for (i = vector - 1; i >= 0; i--)
1676                 free_irq(adapter->msix_entries[--vector].vector,
1677                          adapter->q_vector[i]);
1678         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1679         pci_disable_msix(adapter->pdev);
1680         kfree(adapter->msix_entries);
1681         adapter->msix_entries = NULL;
1682 out:
1683         return err;
1684 }
1685
1686 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1687 {
1688         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1689         u8 current_itr;
1690         u32 new_itr = q_vector->eitr;
1691         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1692         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1693
1694         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1695                                             q_vector->tx_itr,
1696                                             tx_ring->total_packets,
1697                                             tx_ring->total_bytes);
1698         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1699                                             q_vector->rx_itr,
1700                                             rx_ring->total_packets,
1701                                             rx_ring->total_bytes);
1702
1703         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1704
1705         switch (current_itr) {
1706         /* counts and packets in update_itr are dependent on these numbers */
1707         case lowest_latency:
1708                 new_itr = 100000;
1709                 break;
1710         case low_latency:
1711                 new_itr = 20000; /* aka hwitr = ~200 */
1712                 break;
1713         case bulk_latency:
1714                 new_itr = 8000;
1715                 break;
1716         default:
1717                 break;
1718         }
1719
1720         if (new_itr != q_vector->eitr) {
1721                 /* do an exponential smoothing */
1722                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1723
1724                 /* save the algorithm value here, not the smoothed one */
1725                 q_vector->eitr = new_itr;
1726
1727                 ixgbe_write_eitr(q_vector);
1728         }
1729
1730         return;
1731 }
1732
1733 /**
1734  * ixgbe_irq_enable - Enable default interrupt generation settings
1735  * @adapter: board private structure
1736  **/
1737 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1738 {
1739         u32 mask;
1740
1741         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1742         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1743                 mask |= IXGBE_EIMS_GPI_SDP1;
1744         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1745                 mask |= IXGBE_EIMS_ECC;
1746                 mask |= IXGBE_EIMS_GPI_SDP1;
1747                 mask |= IXGBE_EIMS_GPI_SDP2;
1748         }
1749         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1750             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1751                 mask |= IXGBE_EIMS_FLOW_DIR;
1752
1753         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1754         ixgbe_irq_enable_queues(adapter, ~0);
1755         IXGBE_WRITE_FLUSH(&adapter->hw);
1756 }
1757
1758 /**
1759  * ixgbe_intr - legacy mode Interrupt Handler
1760  * @irq: interrupt number
1761  * @data: pointer to a network interface device structure
1762  **/
1763 static irqreturn_t ixgbe_intr(int irq, void *data)
1764 {
1765         struct net_device *netdev = data;
1766         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1767         struct ixgbe_hw *hw = &adapter->hw;
1768         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1769         u32 eicr;
1770
1771         /*
1772          * Workaround for silicon errata.  Mask the interrupts
1773          * before the read of EICR.
1774          */
1775         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1776
1777         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1778          * therefore no explict interrupt disable is necessary */
1779         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1780         if (!eicr) {
1781                 /* shared interrupt alert!
1782                  * make sure interrupts are enabled because the read will
1783                  * have disabled interrupts due to EIAM */
1784                 ixgbe_irq_enable(adapter);
1785                 return IRQ_NONE;        /* Not our interrupt */
1786         }
1787
1788         if (eicr & IXGBE_EICR_LSC)
1789                 ixgbe_check_lsc(adapter);
1790
1791         if (hw->mac.type == ixgbe_mac_82599EB)
1792                 ixgbe_check_sfp_event(adapter, eicr);
1793
1794         ixgbe_check_fan_failure(adapter, eicr);
1795
1796         if (napi_schedule_prep(&(q_vector->napi))) {
1797                 adapter->tx_ring[0].total_packets = 0;
1798                 adapter->tx_ring[0].total_bytes = 0;
1799                 adapter->rx_ring[0].total_packets = 0;
1800                 adapter->rx_ring[0].total_bytes = 0;
1801                 /* would disable interrupts here but EIAM disabled it */
1802                 __napi_schedule(&(q_vector->napi));
1803         }
1804
1805         return IRQ_HANDLED;
1806 }
1807
1808 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1809 {
1810         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1811
1812         for (i = 0; i < q_vectors; i++) {
1813                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1814                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1815                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1816                 q_vector->rxr_count = 0;
1817                 q_vector->txr_count = 0;
1818         }
1819 }
1820
1821 /**
1822  * ixgbe_request_irq - initialize interrupts
1823  * @adapter: board private structure
1824  *
1825  * Attempts to configure interrupts using the best available
1826  * capabilities of the hardware and kernel.
1827  **/
1828 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1829 {
1830         struct net_device *netdev = adapter->netdev;
1831         int err;
1832
1833         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1834                 err = ixgbe_request_msix_irqs(adapter);
1835         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1836                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1837                                   netdev->name, netdev);
1838         } else {
1839                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1840                                   netdev->name, netdev);
1841         }
1842
1843         if (err)
1844                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1845
1846         return err;
1847 }
1848
1849 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1850 {
1851         struct net_device *netdev = adapter->netdev;
1852
1853         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1854                 int i, q_vectors;
1855
1856                 q_vectors = adapter->num_msix_vectors;
1857
1858                 i = q_vectors - 1;
1859                 free_irq(adapter->msix_entries[i].vector, netdev);
1860
1861                 i--;
1862                 for (; i >= 0; i--) {
1863                         free_irq(adapter->msix_entries[i].vector,
1864                                  adapter->q_vector[i]);
1865                 }
1866
1867                 ixgbe_reset_q_vectors(adapter);
1868         } else {
1869                 free_irq(adapter->pdev->irq, netdev);
1870         }
1871 }
1872
1873 /**
1874  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1875  * @adapter: board private structure
1876  **/
1877 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1878 {
1879         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1880                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1881         } else {
1882                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1883                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1884                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1885         }
1886         IXGBE_WRITE_FLUSH(&adapter->hw);
1887         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1888                 int i;
1889                 for (i = 0; i < adapter->num_msix_vectors; i++)
1890                         synchronize_irq(adapter->msix_entries[i].vector);
1891         } else {
1892                 synchronize_irq(adapter->pdev->irq);
1893         }
1894 }
1895
1896 /**
1897  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1898  *
1899  **/
1900 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1901 {
1902         struct ixgbe_hw *hw = &adapter->hw;
1903
1904         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1905                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1906
1907         ixgbe_set_ivar(adapter, 0, 0, 0);
1908         ixgbe_set_ivar(adapter, 1, 0, 0);
1909
1910         map_vector_to_rxq(adapter, 0, 0);
1911         map_vector_to_txq(adapter, 0, 0);
1912
1913         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1914 }
1915
1916 /**
1917  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1918  * @adapter: board private structure
1919  *
1920  * Configure the Tx unit of the MAC after a reset.
1921  **/
1922 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1923 {
1924         u64 tdba;
1925         struct ixgbe_hw *hw = &adapter->hw;
1926         u32 i, j, tdlen, txctrl;
1927
1928         /* Setup the HW Tx Head and Tail descriptor pointers */
1929         for (i = 0; i < adapter->num_tx_queues; i++) {
1930                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1931                 j = ring->reg_idx;
1932                 tdba = ring->dma;
1933                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1934                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1935                                 (tdba & DMA_BIT_MASK(32)));
1936                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1937                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1938                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1939                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1940                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1941                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1942                 /*
1943                  * Disable Tx Head Writeback RO bit, since this hoses
1944                  * bookkeeping if things aren't delivered in order.
1945                  */
1946                 switch (hw->mac.type) {
1947                 case ixgbe_mac_82598EB:
1948                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1949                         break;
1950                 case ixgbe_mac_82599EB:
1951                 default:
1952                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1953                         break;
1954                 }
1955                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1956                 switch (hw->mac.type) {
1957                 case ixgbe_mac_82598EB:
1958                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1959                         break;
1960                 case ixgbe_mac_82599EB:
1961                 default:
1962                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1963                         break;
1964                 }
1965         }
1966
1967         if (hw->mac.type == ixgbe_mac_82599EB) {
1968                 u32 rttdcs;
1969
1970                 /* disable the arbiter while setting MTQC */
1971                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
1972                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
1973                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1974
1975                 /* We enable 8 traffic classes, DCB only */
1976                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1977                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1978                                         IXGBE_MTQC_8TC_8TQ));
1979                 else
1980                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1981
1982                 /* re-eable the arbiter */
1983                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
1984                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1985         }
1986 }
1987
1988 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1989
1990 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1991                                    struct ixgbe_ring *rx_ring)
1992 {
1993         u32 srrctl;
1994         int index;
1995         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1996
1997         index = rx_ring->reg_idx;
1998         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1999                 unsigned long mask;
2000                 mask = (unsigned long) feature[RING_F_RSS].mask;
2001                 index = index & mask;
2002         }
2003         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2004
2005         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2006         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2007
2008         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2009                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2010
2011         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2012 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2013                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2014 #else
2015                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2016 #endif
2017                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2018         } else {
2019                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2020                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2021                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2022         }
2023
2024         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2025 }
2026
2027 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2028 {
2029         u32 mrqc = 0;
2030         int mask;
2031
2032         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2033                 return mrqc;
2034
2035         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2036 #ifdef CONFIG_IXGBE_DCB
2037                                  | IXGBE_FLAG_DCB_ENABLED
2038 #endif
2039                                 );
2040
2041         switch (mask) {
2042         case (IXGBE_FLAG_RSS_ENABLED):
2043                 mrqc = IXGBE_MRQC_RSSEN;
2044                 break;
2045 #ifdef CONFIG_IXGBE_DCB
2046         case (IXGBE_FLAG_DCB_ENABLED):
2047                 mrqc = IXGBE_MRQC_RT8TCEN;
2048                 break;
2049 #endif /* CONFIG_IXGBE_DCB */
2050         default:
2051                 break;
2052         }
2053
2054         return mrqc;
2055 }
2056
2057 /**
2058  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2059  * @adapter:    address of board private structure
2060  * @index:      index of ring to set
2061  * @rx_buf_len: rx buffer length
2062  **/
2063 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index,
2064                                    int rx_buf_len)
2065 {
2066         struct ixgbe_ring *rx_ring;
2067         struct ixgbe_hw *hw = &adapter->hw;
2068         int j;
2069         u32 rscctrl;
2070
2071         rx_ring = &adapter->rx_ring[index];
2072         j = rx_ring->reg_idx;
2073         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2074         rscctrl |= IXGBE_RSCCTL_RSCEN;
2075         /*
2076          * we must limit the number of descriptors so that the
2077          * total size of max desc * buf_len is not greater
2078          * than 65535
2079          */
2080         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2081 #if (MAX_SKB_FRAGS > 16)
2082                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2083 #elif (MAX_SKB_FRAGS > 8)
2084                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2085 #elif (MAX_SKB_FRAGS > 4)
2086                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2087 #else
2088                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2089 #endif
2090         } else {
2091                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2092                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2093                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2094                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2095                 else
2096                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2097         }
2098         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2099 }
2100
2101 /**
2102  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2103  * @adapter: board private structure
2104  *
2105  * Configure the Rx unit of the MAC after a reset.
2106  **/
2107 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2108 {
2109         u64 rdba;
2110         struct ixgbe_hw *hw = &adapter->hw;
2111         struct ixgbe_ring *rx_ring;
2112         struct net_device *netdev = adapter->netdev;
2113         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2114         int i, j;
2115         u32 rdlen, rxctrl, rxcsum;
2116         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2117                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2118                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2119         u32 fctrl, hlreg0;
2120         u32 reta = 0, mrqc = 0;
2121         u32 rdrxctl;
2122         int rx_buf_len;
2123
2124         /* Decide whether to use packet split mode or not */
2125         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2126
2127         /* Set the RX buffer length according to the mode */
2128         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2129                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2130                 if (hw->mac.type == ixgbe_mac_82599EB) {
2131                         /* PSRTYPE must be initialized in 82599 */
2132                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2133                                       IXGBE_PSRTYPE_UDPHDR |
2134                                       IXGBE_PSRTYPE_IPV4HDR |
2135                                       IXGBE_PSRTYPE_IPV6HDR |
2136                                       IXGBE_PSRTYPE_L2HDR;
2137                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2138                 }
2139         } else {
2140                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2141                     (netdev->mtu <= ETH_DATA_LEN))
2142                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2143                 else
2144                         rx_buf_len = ALIGN(max_frame, 1024);
2145         }
2146
2147         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2148         fctrl |= IXGBE_FCTRL_BAM;
2149         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2150         fctrl |= IXGBE_FCTRL_PMCF;
2151         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2152
2153         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2154         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2155                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2156         else
2157                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2158 #ifdef IXGBE_FCOE
2159         if (netdev->features & NETIF_F_FCOE_MTU)
2160                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2161 #endif
2162         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2163
2164         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2165         /* disable receives while setting up the descriptors */
2166         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2167         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2168
2169         /*
2170          * Setup the HW Rx Head and Tail Descriptor Pointers and
2171          * the Base and Length of the Rx Descriptor Ring
2172          */
2173         for (i = 0; i < adapter->num_rx_queues; i++) {
2174                 rx_ring = &adapter->rx_ring[i];
2175                 rdba = rx_ring->dma;
2176                 j = rx_ring->reg_idx;
2177                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2178                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2179                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2180                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2181                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2182                 rx_ring->head = IXGBE_RDH(j);
2183                 rx_ring->tail = IXGBE_RDT(j);
2184                 rx_ring->rx_buf_len = rx_buf_len;
2185
2186                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2187                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2188                 else
2189                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2190
2191 #ifdef IXGBE_FCOE
2192                 if (netdev->features & NETIF_F_FCOE_MTU) {
2193                         struct ixgbe_ring_feature *f;
2194                         f = &adapter->ring_feature[RING_F_FCOE];
2195                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2196                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2197                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2198                                         rx_ring->rx_buf_len =
2199                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2200                         }
2201                 }
2202
2203 #endif /* IXGBE_FCOE */
2204                 ixgbe_configure_srrctl(adapter, rx_ring);
2205         }
2206
2207         if (hw->mac.type == ixgbe_mac_82598EB) {
2208                 /*
2209                  * For VMDq support of different descriptor types or
2210                  * buffer sizes through the use of multiple SRRCTL
2211                  * registers, RDRXCTL.MVMEN must be set to 1
2212                  *
2213                  * also, the manual doesn't mention it clearly but DCA hints
2214                  * will only use queue 0's tags unless this bit is set.  Side
2215                  * effects of setting this bit are only that SRRCTL must be
2216                  * fully programmed [0..15]
2217                  */
2218                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2219                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2220                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2221         }
2222
2223         /* Program MRQC for the distribution of queues */
2224         mrqc = ixgbe_setup_mrqc(adapter);
2225
2226         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2227                 /* Fill out redirection table */
2228                 for (i = 0, j = 0; i < 128; i++, j++) {
2229                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2230                                 j = 0;
2231                         /* reta = 4-byte sliding window of
2232                          * 0x00..(indices-1)(indices-1)00..etc. */
2233                         reta = (reta << 8) | (j * 0x11);
2234                         if ((i & 3) == 3)
2235                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2236                 }
2237
2238                 /* Fill out hash function seeds */
2239                 for (i = 0; i < 10; i++)
2240                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2241
2242                 if (hw->mac.type == ixgbe_mac_82598EB)
2243                         mrqc |= IXGBE_MRQC_RSSEN;
2244                     /* Perform hash on these packet types */
2245                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2246                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2247                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2248                       | IXGBE_MRQC_RSS_FIELD_IPV6
2249                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2250                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2251         }
2252         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2253
2254         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2255
2256         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2257             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2258                 /* Disable indicating checksum in descriptor, enables
2259                  * RSS hash */
2260                 rxcsum |= IXGBE_RXCSUM_PCSD;
2261         }
2262         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2263                 /* Enable IPv4 payload checksum for UDP fragments
2264                  * if PCSD is not set */
2265                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2266         }
2267
2268         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2269
2270         if (hw->mac.type == ixgbe_mac_82599EB) {
2271                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2272                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2273                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2274                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2275         }
2276
2277         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2278                 /* Enable 82599 HW-RSC */
2279                 for (i = 0; i < adapter->num_rx_queues; i++)
2280                         ixgbe_configure_rscctl(adapter, i, rx_buf_len);
2281
2282                 /* Disable RSC for ACK packets */
2283                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2284                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2285         }
2286 }
2287
2288 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2289 {
2290         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2291         struct ixgbe_hw *hw = &adapter->hw;
2292
2293         /* add VID to filter table */
2294         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2295 }
2296
2297 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2298 {
2299         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2300         struct ixgbe_hw *hw = &adapter->hw;
2301
2302         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2303                 ixgbe_irq_disable(adapter);
2304
2305         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2306
2307         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2308                 ixgbe_irq_enable(adapter);
2309
2310         /* remove VID from filter table */
2311         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2312 }
2313
2314 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2315                                    struct vlan_group *grp)
2316 {
2317         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2318         u32 ctrl;
2319         int i, j;
2320
2321         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2322                 ixgbe_irq_disable(adapter);
2323         adapter->vlgrp = grp;
2324
2325         /*
2326          * For a DCB driver, always enable VLAN tag stripping so we can
2327          * still receive traffic from a DCB-enabled host even if we're
2328          * not in DCB mode.
2329          */
2330         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2331         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2332                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2333                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2334                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2335         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2336                 ctrl |= IXGBE_VLNCTRL_VFE;
2337                 /* enable VLAN tag insert/strip */
2338                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2339                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2340                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2341                 for (i = 0; i < adapter->num_rx_queues; i++) {
2342                         j = adapter->rx_ring[i].reg_idx;
2343                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2344                         ctrl |= IXGBE_RXDCTL_VME;
2345                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2346                 }
2347         }
2348         ixgbe_vlan_rx_add_vid(netdev, 0);
2349
2350         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2351                 ixgbe_irq_enable(adapter);
2352 }
2353
2354 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2355 {
2356         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2357
2358         if (adapter->vlgrp) {
2359                 u16 vid;
2360                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2361                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2362                                 continue;
2363                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2364                 }
2365         }
2366 }
2367
2368 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2369 {
2370         struct dev_mc_list *mc_ptr;
2371         u8 *addr = *mc_addr_ptr;
2372         *vmdq = 0;
2373
2374         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2375         if (mc_ptr->next)
2376                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2377         else
2378                 *mc_addr_ptr = NULL;
2379
2380         return addr;
2381 }
2382
2383 /**
2384  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2385  * @netdev: network interface device structure
2386  *
2387  * The set_rx_method entry point is called whenever the unicast/multicast
2388  * address list or the network interface flags are updated.  This routine is
2389  * responsible for configuring the hardware for proper unicast, multicast and
2390  * promiscuous mode.
2391  **/
2392 static void ixgbe_set_rx_mode(struct net_device *netdev)
2393 {
2394         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2395         struct ixgbe_hw *hw = &adapter->hw;
2396         u32 fctrl, vlnctrl;
2397         u8 *addr_list = NULL;
2398         int addr_count = 0;
2399
2400         /* Check for Promiscuous and All Multicast modes */
2401
2402         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2403         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2404
2405         if (netdev->flags & IFF_PROMISC) {
2406                 hw->addr_ctrl.user_set_promisc = 1;
2407                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2408                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2409         } else {
2410                 if (netdev->flags & IFF_ALLMULTI) {
2411                         fctrl |= IXGBE_FCTRL_MPE;
2412                         fctrl &= ~IXGBE_FCTRL_UPE;
2413                 } else {
2414                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2415                 }
2416                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2417                 hw->addr_ctrl.user_set_promisc = 0;
2418         }
2419
2420         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2421         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2422
2423         /* reprogram secondary unicast list */
2424         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2425
2426         /* reprogram multicast list */
2427         addr_count = netdev->mc_count;
2428         if (addr_count)
2429                 addr_list = netdev->mc_list->dmi_addr;
2430         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2431                                         ixgbe_addr_list_itr);
2432 }
2433
2434 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2435 {
2436         int q_idx;
2437         struct ixgbe_q_vector *q_vector;
2438         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2439
2440         /* legacy and MSI only use one vector */
2441         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2442                 q_vectors = 1;
2443
2444         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2445                 struct napi_struct *napi;
2446                 q_vector = adapter->q_vector[q_idx];
2447                 napi = &q_vector->napi;
2448                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2449                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2450                                 if (q_vector->txr_count == 1)
2451                                         napi->poll = &ixgbe_clean_txonly;
2452                                 else if (q_vector->rxr_count == 1)
2453                                         napi->poll = &ixgbe_clean_rxonly;
2454                         }
2455                 }
2456
2457                 napi_enable(napi);
2458         }
2459 }
2460
2461 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2462 {
2463         int q_idx;
2464         struct ixgbe_q_vector *q_vector;
2465         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2466
2467         /* legacy and MSI only use one vector */
2468         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2469                 q_vectors = 1;
2470
2471         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2472                 q_vector = adapter->q_vector[q_idx];
2473                 napi_disable(&q_vector->napi);
2474         }
2475 }
2476
2477 #ifdef CONFIG_IXGBE_DCB
2478 /*
2479  * ixgbe_configure_dcb - Configure DCB hardware
2480  * @adapter: ixgbe adapter struct
2481  *
2482  * This is called by the driver on open to configure the DCB hardware.
2483  * This is also called by the gennetlink interface when reconfiguring
2484  * the DCB state.
2485  */
2486 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2487 {
2488         struct ixgbe_hw *hw = &adapter->hw;
2489         u32 txdctl, vlnctrl;
2490         int i, j;
2491
2492         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2493         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2494         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2495
2496         /* reconfigure the hardware */
2497         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2498
2499         for (i = 0; i < adapter->num_tx_queues; i++) {
2500                 j = adapter->tx_ring[i].reg_idx;
2501                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2502                 /* PThresh workaround for Tx hang with DFP enabled. */
2503                 txdctl |= 32;
2504                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2505         }
2506         /* Enable VLAN tag insert/strip */
2507         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2508         if (hw->mac.type == ixgbe_mac_82598EB) {
2509                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2510                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2511                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2512         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2513                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2514                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2515                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2516                 for (i = 0; i < adapter->num_rx_queues; i++) {
2517                         j = adapter->rx_ring[i].reg_idx;
2518                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2519                         vlnctrl |= IXGBE_RXDCTL_VME;
2520                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2521                 }
2522         }
2523         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2524 }
2525
2526 #endif
2527 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2528 {
2529         struct net_device *netdev = adapter->netdev;
2530         struct ixgbe_hw *hw = &adapter->hw;
2531         int i;
2532
2533         ixgbe_set_rx_mode(netdev);
2534
2535         ixgbe_restore_vlan(adapter);
2536 #ifdef CONFIG_IXGBE_DCB
2537         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2538                 if (hw->mac.type == ixgbe_mac_82598EB)
2539                         netif_set_gso_max_size(netdev, 32768);
2540                 else
2541                         netif_set_gso_max_size(netdev, 65536);
2542                 ixgbe_configure_dcb(adapter);
2543         } else {
2544                 netif_set_gso_max_size(netdev, 65536);
2545         }
2546 #else
2547         netif_set_gso_max_size(netdev, 65536);
2548 #endif
2549
2550 #ifdef IXGBE_FCOE
2551         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2552                 ixgbe_configure_fcoe(adapter);
2553
2554 #endif /* IXGBE_FCOE */
2555         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2556                 for (i = 0; i < adapter->num_tx_queues; i++)
2557                         adapter->tx_ring[i].atr_sample_rate =
2558                                                        adapter->atr_sample_rate;
2559                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2560         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2561                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2562         }
2563
2564         ixgbe_configure_tx(adapter);
2565         ixgbe_configure_rx(adapter);
2566         for (i = 0; i < adapter->num_rx_queues; i++)
2567                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2568                                        (adapter->rx_ring[i].count - 1));
2569 }
2570
2571 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2572 {
2573         switch (hw->phy.type) {
2574         case ixgbe_phy_sfp_avago:
2575         case ixgbe_phy_sfp_ftl:
2576         case ixgbe_phy_sfp_intel:
2577         case ixgbe_phy_sfp_unknown:
2578         case ixgbe_phy_tw_tyco:
2579         case ixgbe_phy_tw_unknown:
2580                 return true;
2581         default:
2582                 return false;
2583         }
2584 }
2585
2586 /**
2587  * ixgbe_sfp_link_config - set up SFP+ link
2588  * @adapter: pointer to private adapter struct
2589  **/
2590 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2591 {
2592         struct ixgbe_hw *hw = &adapter->hw;
2593
2594                 if (hw->phy.multispeed_fiber) {
2595                         /*
2596                          * In multispeed fiber setups, the device may not have
2597                          * had a physical connection when the driver loaded.
2598                          * If that's the case, the initial link configuration
2599                          * couldn't get the MAC into 10G or 1G mode, so we'll
2600                          * never have a link status change interrupt fire.
2601                          * We need to try and force an autonegotiation
2602                          * session, then bring up link.
2603                          */
2604                         hw->mac.ops.setup_sfp(hw);
2605                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2606                                 schedule_work(&adapter->multispeed_fiber_task);
2607                 } else {
2608                         /*
2609                          * Direct Attach Cu and non-multispeed fiber modules
2610                          * still need to be configured properly prior to
2611                          * attempting link.
2612                          */
2613                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2614                                 schedule_work(&adapter->sfp_config_module_task);
2615                 }
2616 }
2617
2618 /**
2619  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2620  * @hw: pointer to private hardware struct
2621  *
2622  * Returns 0 on success, negative on failure
2623  **/
2624 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2625 {
2626         u32 autoneg;
2627         bool negotiation, link_up = false;
2628         u32 ret = IXGBE_ERR_LINK_SETUP;
2629
2630         if (hw->mac.ops.check_link)
2631                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2632
2633         if (ret)
2634                 goto link_cfg_out;
2635
2636         if (hw->mac.ops.get_link_capabilities)
2637                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2638         if (ret)
2639                 goto link_cfg_out;
2640
2641         if (hw->mac.ops.setup_link)
2642                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2643 link_cfg_out:
2644         return ret;
2645 }
2646
2647 #define IXGBE_MAX_RX_DESC_POLL 10
2648 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2649                                               int rxr)
2650 {
2651         int j = adapter->rx_ring[rxr].reg_idx;
2652         int k;
2653
2654         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2655                 if (IXGBE_READ_REG(&adapter->hw,
2656                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2657                         break;
2658                 else
2659                         msleep(1);
2660         }
2661         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2662                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2663                         "not set within the polling period\n", rxr);
2664         }
2665         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2666                               (adapter->rx_ring[rxr].count - 1));
2667 }
2668
2669 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2670 {
2671         struct net_device *netdev = adapter->netdev;
2672         struct ixgbe_hw *hw = &adapter->hw;
2673         int i, j = 0;
2674         int num_rx_rings = adapter->num_rx_queues;
2675         int err;
2676         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2677         u32 txdctl, rxdctl, mhadd;
2678         u32 dmatxctl;
2679         u32 gpie;
2680
2681         ixgbe_get_hw_control(adapter);
2682
2683         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2684             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2685                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2686                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2687                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2688                 } else {
2689                         /* MSI only */
2690                         gpie = 0;
2691                 }
2692                 /* XXX: to interrupt immediately for EICS writes, enable this */
2693                 /* gpie |= IXGBE_GPIE_EIMEN; */
2694                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2695         }
2696
2697         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2698                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2699                  * specifically only auto mask tx and rx interrupts */
2700                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2701         }
2702
2703         /* Enable fan failure interrupt if media type is copper */
2704         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2705                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2706                 gpie |= IXGBE_SDP1_GPIEN;
2707                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2708         }
2709
2710         if (hw->mac.type == ixgbe_mac_82599EB) {
2711                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2712                 gpie |= IXGBE_SDP1_GPIEN;
2713                 gpie |= IXGBE_SDP2_GPIEN;
2714                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2715         }
2716
2717 #ifdef IXGBE_FCOE
2718         /* adjust max frame to be able to do baby jumbo for FCoE */
2719         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2720             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2721                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2722
2723 #endif /* IXGBE_FCOE */
2724         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2725         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2726                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2727                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2728
2729                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2730         }
2731
2732         for (i = 0; i < adapter->num_tx_queues; i++) {
2733                 j = adapter->tx_ring[i].reg_idx;
2734                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2735                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2736                 txdctl |= (8 << 16);
2737                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2738         }
2739
2740         if (hw->mac.type == ixgbe_mac_82599EB) {
2741                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2742                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2743                 dmatxctl |= IXGBE_DMATXCTL_TE;
2744                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2745         }
2746         for (i = 0; i < adapter->num_tx_queues; i++) {
2747                 j = adapter->tx_ring[i].reg_idx;
2748                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2749                 txdctl |= IXGBE_TXDCTL_ENABLE;
2750                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2751         }
2752
2753         for (i = 0; i < num_rx_rings; i++) {
2754                 j = adapter->rx_ring[i].reg_idx;
2755                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2756                 /* enable PTHRESH=32 descriptors (half the internal cache)
2757                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2758                  * this also removes a pesky rx_no_buffer_count increment */
2759                 rxdctl |= 0x0020;
2760                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2761                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2762                 if (hw->mac.type == ixgbe_mac_82599EB)
2763                         ixgbe_rx_desc_queue_enable(adapter, i);
2764         }
2765         /* enable all receives */
2766         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2767         if (hw->mac.type == ixgbe_mac_82598EB)
2768                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2769         else
2770                 rxdctl |= IXGBE_RXCTRL_RXEN;
2771         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2772
2773         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2774                 ixgbe_configure_msix(adapter);
2775         else
2776                 ixgbe_configure_msi_and_legacy(adapter);
2777
2778         clear_bit(__IXGBE_DOWN, &adapter->state);
2779         ixgbe_napi_enable_all(adapter);
2780
2781         /* clear any pending interrupts, may auto mask */
2782         IXGBE_READ_REG(hw, IXGBE_EICR);
2783
2784         ixgbe_irq_enable(adapter);
2785
2786         /*
2787          * If this adapter has a fan, check to see if we had a failure
2788          * before we enabled the interrupt.
2789          */
2790         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2791                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2792                 if (esdp & IXGBE_ESDP_SDP1)
2793                         DPRINTK(DRV, CRIT,
2794                                 "Fan has stopped, replace the adapter\n");
2795         }
2796
2797         /*
2798          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2799          * arrived before interrupts were enabled but after probe.  Such
2800          * devices wouldn't have their type identified yet. We need to
2801          * kick off the SFP+ module setup first, then try to bring up link.
2802          * If we're not hot-pluggable SFP+, we just need to configure link
2803          * and bring it up.
2804          */
2805         if (hw->phy.type == ixgbe_phy_unknown) {
2806                 err = hw->phy.ops.identify(hw);
2807                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2808                         /*
2809                          * Take the device down and schedule the sfp tasklet
2810                          * which will unregister_netdev and log it.
2811                          */
2812                         ixgbe_down(adapter);
2813                         schedule_work(&adapter->sfp_config_module_task);
2814                         return err;
2815                 }
2816         }
2817
2818         if (ixgbe_is_sfp(hw)) {
2819                 ixgbe_sfp_link_config(adapter);
2820         } else {
2821                 err = ixgbe_non_sfp_link_config(hw);
2822                 if (err)
2823                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2824         }
2825
2826         for (i = 0; i < adapter->num_tx_queues; i++)
2827                 set_bit(__IXGBE_FDIR_INIT_DONE,
2828                         &(adapter->tx_ring[i].reinit_state));
2829
2830         /* enable transmits */
2831         netif_tx_start_all_queues(netdev);
2832
2833         /* bring the link up in the watchdog, this could race with our first
2834          * link up interrupt but shouldn't be a problem */
2835         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2836         adapter->link_check_timeout = jiffies;
2837         mod_timer(&adapter->watchdog_timer, jiffies);
2838         return 0;
2839 }
2840
2841 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2842 {
2843         WARN_ON(in_interrupt());
2844         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2845                 msleep(1);
2846         ixgbe_down(adapter);
2847         ixgbe_up(adapter);
2848         clear_bit(__IXGBE_RESETTING, &adapter->state);
2849 }
2850
2851 int ixgbe_up(struct ixgbe_adapter *adapter)
2852 {
2853         /* hardware has been reset, we need to reload some things */
2854         ixgbe_configure(adapter);
2855
2856         return ixgbe_up_complete(adapter);
2857 }
2858
2859 void ixgbe_reset(struct ixgbe_adapter *adapter)
2860 {
2861         struct ixgbe_hw *hw = &adapter->hw;
2862         int err;
2863
2864         err = hw->mac.ops.init_hw(hw);
2865         switch (err) {
2866         case 0:
2867         case IXGBE_ERR_SFP_NOT_PRESENT:
2868                 break;
2869         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2870                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2871                 break;
2872         case IXGBE_ERR_EEPROM_VERSION:
2873                 /* We are running on a pre-production device, log a warning */
2874                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2875                          "adapter/LOM.  Please be aware there may be issues "
2876                          "associated with your hardware.  If you are "
2877                          "experiencing problems please contact your Intel or "
2878                          "hardware representative who provided you with this "
2879                          "hardware.\n");
2880                 break;
2881         default:
2882                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2883         }
2884
2885         /* reprogram the RAR[0] in case user changed it. */
2886         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2887 }
2888
2889 /**
2890  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2891  * @adapter: board private structure
2892  * @rx_ring: ring to free buffers from
2893  **/
2894 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2895                                 struct ixgbe_ring *rx_ring)
2896 {
2897         struct pci_dev *pdev = adapter->pdev;
2898         unsigned long size;
2899         unsigned int i;
2900
2901         /* Free all the Rx ring sk_buffs */
2902
2903         for (i = 0; i < rx_ring->count; i++) {
2904                 struct ixgbe_rx_buffer *rx_buffer_info;
2905
2906                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2907                 if (rx_buffer_info->dma) {
2908                         pci_unmap_single(pdev, rx_buffer_info->dma,
2909                                          rx_ring->rx_buf_len,
2910                                          PCI_DMA_FROMDEVICE);
2911                         rx_buffer_info->dma = 0;
2912                 }
2913                 if (rx_buffer_info->skb) {
2914                         struct sk_buff *skb = rx_buffer_info->skb;
2915                         rx_buffer_info->skb = NULL;
2916                         do {
2917                                 struct sk_buff *this = skb;
2918                                 skb = skb->prev;
2919                                 dev_kfree_skb(this);
2920                         } while (skb);
2921                 }
2922                 if (!rx_buffer_info->page)
2923                         continue;
2924                 if (rx_buffer_info->page_dma) {
2925                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2926                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2927                         rx_buffer_info->page_dma = 0;
2928                 }
2929                 put_page(rx_buffer_info->page);
2930                 rx_buffer_info->page = NULL;
2931                 rx_buffer_info->page_offset = 0;
2932         }
2933
2934         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2935         memset(rx_ring->rx_buffer_info, 0, size);
2936
2937         /* Zero out the descriptor ring */
2938         memset(rx_ring->desc, 0, rx_ring->size);
2939
2940         rx_ring->next_to_clean = 0;
2941         rx_ring->next_to_use = 0;
2942
2943         if (rx_ring->head)
2944                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2945         if (rx_ring->tail)
2946                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2947 }
2948
2949 /**
2950  * ixgbe_clean_tx_ring - Free Tx Buffers
2951  * @adapter: board private structure
2952  * @tx_ring: ring to be cleaned
2953  **/
2954 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2955                                 struct ixgbe_ring *tx_ring)
2956 {
2957         struct ixgbe_tx_buffer *tx_buffer_info;
2958         unsigned long size;
2959         unsigned int i;
2960
2961         /* Free all the Tx ring sk_buffs */
2962
2963         for (i = 0; i < tx_ring->count; i++) {
2964                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2965                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2966         }
2967
2968         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2969         memset(tx_ring->tx_buffer_info, 0, size);
2970
2971         /* Zero out the descriptor ring */
2972         memset(tx_ring->desc, 0, tx_ring->size);
2973
2974         tx_ring->next_to_use = 0;
2975         tx_ring->next_to_clean = 0;
2976
2977         if (tx_ring->head)
2978                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2979         if (tx_ring->tail)
2980                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2981 }
2982
2983 /**
2984  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2985  * @adapter: board private structure
2986  **/
2987 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2988 {
2989         int i;
2990
2991         for (i = 0; i < adapter->num_rx_queues; i++)
2992                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2993 }
2994
2995 /**
2996  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2997  * @adapter: board private structure
2998  **/
2999 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3000 {
3001         int i;
3002
3003         for (i = 0; i < adapter->num_tx_queues; i++)
3004                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
3005 }
3006
3007 void ixgbe_down(struct ixgbe_adapter *adapter)
3008 {
3009         struct net_device *netdev = adapter->netdev;
3010         struct ixgbe_hw *hw = &adapter->hw;
3011         u32 rxctrl;
3012         u32 txdctl;
3013         int i, j;
3014
3015         /* signal that we are down to the interrupt handler */
3016         set_bit(__IXGBE_DOWN, &adapter->state);
3017
3018         /* disable receives */
3019         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3020         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3021
3022         netif_tx_disable(netdev);
3023
3024         IXGBE_WRITE_FLUSH(hw);
3025         msleep(10);
3026
3027         netif_tx_stop_all_queues(netdev);
3028
3029         ixgbe_irq_disable(adapter);
3030
3031         ixgbe_napi_disable_all(adapter);
3032
3033         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3034         del_timer_sync(&adapter->sfp_timer);
3035         del_timer_sync(&adapter->watchdog_timer);
3036         cancel_work_sync(&adapter->watchdog_task);
3037
3038         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3039             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3040                 cancel_work_sync(&adapter->fdir_reinit_task);
3041
3042         /* disable transmits in the hardware now that interrupts are off */
3043         for (i = 0; i < adapter->num_tx_queues; i++) {
3044                 j = adapter->tx_ring[i].reg_idx;
3045                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3046                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3047                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3048         }
3049         /* Disable the Tx DMA engine on 82599 */
3050         if (hw->mac.type == ixgbe_mac_82599EB)
3051                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3052                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3053                                  ~IXGBE_DMATXCTL_TE));
3054
3055         netif_carrier_off(netdev);
3056
3057         if (!pci_channel_offline(adapter->pdev))
3058                 ixgbe_reset(adapter);
3059         ixgbe_clean_all_tx_rings(adapter);
3060         ixgbe_clean_all_rx_rings(adapter);
3061
3062 #ifdef CONFIG_IXGBE_DCA
3063         /* since we reset the hardware DCA settings were cleared */
3064         ixgbe_setup_dca(adapter);
3065 #endif
3066 }
3067
3068 /**
3069  * ixgbe_poll - NAPI Rx polling callback
3070  * @napi: structure for representing this polling device
3071  * @budget: how many packets driver is allowed to clean
3072  *
3073  * This function is used for legacy and MSI, NAPI mode
3074  **/
3075 static int ixgbe_poll(struct napi_struct *napi, int budget)
3076 {
3077         struct ixgbe_q_vector *q_vector =
3078                                 container_of(napi, struct ixgbe_q_vector, napi);
3079         struct ixgbe_adapter *adapter = q_vector->adapter;
3080         int tx_clean_complete, work_done = 0;
3081
3082 #ifdef CONFIG_IXGBE_DCA
3083         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3084                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3085                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3086         }
3087 #endif
3088
3089         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3090         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3091
3092         if (!tx_clean_complete)
3093                 work_done = budget;
3094
3095         /* If budget not fully consumed, exit the polling mode */
3096         if (work_done < budget) {
3097                 napi_complete(napi);
3098                 if (adapter->rx_itr_setting & 1)
3099                         ixgbe_set_itr(adapter);
3100                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3101                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3102         }
3103         return work_done;
3104 }
3105
3106 /**
3107  * ixgbe_tx_timeout - Respond to a Tx Hang
3108  * @netdev: network interface device structure
3109  **/
3110 static void ixgbe_tx_timeout(struct net_device *netdev)
3111 {
3112         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3113
3114         /* Do the reset outside of interrupt context */
3115         schedule_work(&adapter->reset_task);
3116 }
3117
3118 static void ixgbe_reset_task(struct work_struct *work)
3119 {
3120         struct ixgbe_adapter *adapter;
3121         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3122
3123         /* If we're already down or resetting, just bail */
3124         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3125             test_bit(__IXGBE_RESETTING, &adapter->state))
3126                 return;
3127
3128         adapter->tx_timeout_count++;
3129
3130         ixgbe_reinit_locked(adapter);
3131 }
3132
3133 #ifdef CONFIG_IXGBE_DCB
3134 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3135 {
3136         bool ret = false;
3137         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3138
3139         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3140                 return ret;
3141
3142         f->mask = 0x7 << 3;
3143         adapter->num_rx_queues = f->indices;
3144         adapter->num_tx_queues = f->indices;
3145         ret = true;
3146
3147         return ret;
3148 }
3149 #endif
3150
3151 /**
3152  * ixgbe_set_rss_queues: Allocate queues for RSS
3153  * @adapter: board private structure to initialize
3154  *
3155  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3156  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3157  *
3158  **/
3159 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3160 {
3161         bool ret = false;
3162         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3163
3164         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3165                 f->mask = 0xF;
3166                 adapter->num_rx_queues = f->indices;
3167                 adapter->num_tx_queues = f->indices;
3168                 ret = true;
3169         } else {
3170                 ret = false;
3171         }
3172
3173         return ret;
3174 }
3175
3176 /**
3177  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3178  * @adapter: board private structure to initialize
3179  *
3180  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3181  * to the original CPU that initiated the Tx session.  This runs in addition
3182  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3183  * Rx load across CPUs using RSS.
3184  *
3185  **/
3186 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3187 {
3188         bool ret = false;
3189         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3190
3191         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3192         f_fdir->mask = 0;
3193
3194         /* Flow Director must have RSS enabled */
3195         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3196             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3197              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3198                 adapter->num_tx_queues = f_fdir->indices;
3199                 adapter->num_rx_queues = f_fdir->indices;
3200                 ret = true;
3201         } else {
3202                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3203                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3204         }
3205         return ret;
3206 }
3207
3208 #ifdef IXGBE_FCOE
3209 /**
3210  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3211  * @adapter: board private structure to initialize
3212  *
3213  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3214  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3215  * rx queues out of the max number of rx queues, instead, it is used as the
3216  * index of the first rx queue used by FCoE.
3217  *
3218  **/
3219 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3220 {
3221         bool ret = false;
3222         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3223
3224         f->indices = min((int)num_online_cpus(), f->indices);
3225         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3226                 adapter->num_rx_queues = 1;
3227                 adapter->num_tx_queues = 1;
3228 #ifdef CONFIG_IXGBE_DCB
3229                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3230                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3231                         ixgbe_set_dcb_queues(adapter);
3232                 }
3233 #endif
3234                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3235                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3236                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3237                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3238                                 ixgbe_set_fdir_queues(adapter);
3239                         else
3240                                 ixgbe_set_rss_queues(adapter);
3241                 }
3242                 /* adding FCoE rx rings to the end */
3243                 f->mask = adapter->num_rx_queues;
3244                 adapter->num_rx_queues += f->indices;
3245                 adapter->num_tx_queues += f->indices;
3246
3247                 ret = true;
3248         }
3249
3250         return ret;
3251 }
3252
3253 #endif /* IXGBE_FCOE */
3254 /*
3255  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3256  * @adapter: board private structure to initialize
3257  *
3258  * This is the top level queue allocation routine.  The order here is very
3259  * important, starting with the "most" number of features turned on at once,
3260  * and ending with the smallest set of features.  This way large combinations
3261  * can be allocated if they're turned on, and smaller combinations are the
3262  * fallthrough conditions.
3263  *
3264  **/
3265 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3266 {
3267 #ifdef IXGBE_FCOE
3268         if (ixgbe_set_fcoe_queues(adapter))
3269                 goto done;
3270
3271 #endif /* IXGBE_FCOE */
3272 #ifdef CONFIG_IXGBE_DCB
3273         if (ixgbe_set_dcb_queues(adapter))
3274                 goto done;
3275
3276 #endif
3277         if (ixgbe_set_fdir_queues(adapter))
3278                 goto done;
3279
3280         if (ixgbe_set_rss_queues(adapter))
3281                 goto done;
3282
3283         /* fallback to base case */
3284         adapter->num_rx_queues = 1;
3285         adapter->num_tx_queues = 1;
3286
3287 done:
3288         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3289         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3290 }
3291
3292 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3293                                        int vectors)
3294 {
3295         int err, vector_threshold;
3296
3297         /* We'll want at least 3 (vector_threshold):
3298          * 1) TxQ[0] Cleanup
3299          * 2) RxQ[0] Cleanup
3300          * 3) Other (Link Status Change, etc.)
3301          * 4) TCP Timer (optional)
3302          */
3303         vector_threshold = MIN_MSIX_COUNT;
3304
3305         /* The more we get, the more we will assign to Tx/Rx Cleanup
3306          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3307          * Right now, we simply care about how many we'll get; we'll
3308          * set them up later while requesting irq's.
3309          */
3310         while (vectors >= vector_threshold) {
3311                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3312                                       vectors);
3313                 if (!err) /* Success in acquiring all requested vectors. */
3314                         break;
3315                 else if (err < 0)
3316                         vectors = 0; /* Nasty failure, quit now */
3317                 else /* err == number of vectors we should try again with */
3318                         vectors = err;
3319         }
3320
3321         if (vectors < vector_threshold) {
3322                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3323                  * This just means we'll go with either a single MSI
3324                  * vector or fall back to legacy interrupts.
3325                  */
3326                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3327                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3328                 kfree(adapter->msix_entries);
3329                 adapter->msix_entries = NULL;
3330         } else {
3331                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3332                 /*
3333                  * Adjust for only the vectors we'll use, which is minimum
3334                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3335                  * vectors we were allocated.
3336                  */
3337                 adapter->num_msix_vectors = min(vectors,
3338                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3339         }
3340 }
3341
3342 /**
3343  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3344  * @adapter: board private structure to initialize
3345  *
3346  * Cache the descriptor ring offsets for RSS to the assigned rings.
3347  *
3348  **/
3349 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3350 {
3351         int i;
3352         bool ret = false;
3353
3354         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3355                 for (i = 0; i < adapter->num_rx_queues; i++)
3356                         adapter->rx_ring[i].reg_idx = i;
3357                 for (i = 0; i < adapter->num_tx_queues; i++)
3358                         adapter->tx_ring[i].reg_idx = i;
3359                 ret = true;
3360         } else {
3361                 ret = false;
3362         }
3363
3364         return ret;
3365 }
3366
3367 #ifdef CONFIG_IXGBE_DCB
3368 /**
3369  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3370  * @adapter: board private structure to initialize
3371  *
3372  * Cache the descriptor ring offsets for DCB to the assigned rings.
3373  *
3374  **/
3375 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3376 {
3377         int i;
3378         bool ret = false;
3379         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3380
3381         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3382                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3383                         /* the number of queues is assumed to be symmetric */
3384                         for (i = 0; i < dcb_i; i++) {
3385                                 adapter->rx_ring[i].reg_idx = i << 3;
3386                                 adapter->tx_ring[i].reg_idx = i << 2;
3387                         }
3388                         ret = true;
3389                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3390                         if (dcb_i == 8) {
3391                                 /*
3392                                  * Tx TC0 starts at: descriptor queue 0
3393                                  * Tx TC1 starts at: descriptor queue 32
3394                                  * Tx TC2 starts at: descriptor queue 64
3395                                  * Tx TC3 starts at: descriptor queue 80
3396                                  * Tx TC4 starts at: descriptor queue 96
3397                                  * Tx TC5 starts at: descriptor queue 104
3398                                  * Tx TC6 starts at: descriptor queue 112
3399                                  * Tx TC7 starts at: descriptor queue 120
3400                                  *
3401                                  * Rx TC0-TC7 are offset by 16 queues each
3402                                  */
3403                                 for (i = 0; i < 3; i++) {
3404                                         adapter->tx_ring[i].reg_idx = i << 5;
3405                                         adapter->rx_ring[i].reg_idx = i << 4;
3406                                 }
3407                                 for ( ; i < 5; i++) {
3408                                         adapter->tx_ring[i].reg_idx =
3409                                                                  ((i + 2) << 4);
3410                                         adapter->rx_ring[i].reg_idx = i << 4;
3411                                 }
3412                                 for ( ; i < dcb_i; i++) {
3413                                         adapter->tx_ring[i].reg_idx =
3414                                                                  ((i + 8) << 3);
3415                                         adapter->rx_ring[i].reg_idx = i << 4;
3416                                 }
3417
3418                                 ret = true;
3419                         } else if (dcb_i == 4) {
3420                                 /*
3421                                  * Tx TC0 starts at: descriptor queue 0
3422                                  * Tx TC1 starts at: descriptor queue 64
3423                                  * Tx TC2 starts at: descriptor queue 96
3424                                  * Tx TC3 starts at: descriptor queue 112
3425                                  *
3426                                  * Rx TC0-TC3 are offset by 32 queues each
3427                                  */
3428                                 adapter->tx_ring[0].reg_idx = 0;
3429                                 adapter->tx_ring[1].reg_idx = 64;
3430                                 adapter->tx_ring[2].reg_idx = 96;
3431                                 adapter->tx_ring[3].reg_idx = 112;
3432                                 for (i = 0 ; i < dcb_i; i++)
3433                                         adapter->rx_ring[i].reg_idx = i << 5;
3434
3435                                 ret = true;
3436                         } else {
3437                                 ret = false;
3438                         }
3439                 } else {
3440                         ret = false;
3441                 }
3442         } else {
3443                 ret = false;
3444         }
3445
3446         return ret;
3447 }
3448 #endif
3449
3450 /**
3451  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3452  * @adapter: board private structure to initialize
3453  *
3454  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3455  *
3456  **/
3457 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3458 {
3459         int i;
3460         bool ret = false;
3461
3462         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3463             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3464              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3465                 for (i = 0; i < adapter->num_rx_queues; i++)
3466                         adapter->rx_ring[i].reg_idx = i;
3467                 for (i = 0; i < adapter->num_tx_queues; i++)
3468                         adapter->tx_ring[i].reg_idx = i;
3469                 ret = true;
3470         }
3471
3472         return ret;
3473 }
3474
3475 #ifdef IXGBE_FCOE
3476 /**
3477  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3478  * @adapter: board private structure to initialize
3479  *
3480  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3481  *
3482  */
3483 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3484 {
3485         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3486         bool ret = false;
3487         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3488
3489         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3490 #ifdef CONFIG_IXGBE_DCB
3491                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3492                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3493
3494                         ixgbe_cache_ring_dcb(adapter);
3495                         /* find out queues in TC for FCoE */
3496                         fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3497                         fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3498                         /*
3499                          * In 82599, the number of Tx queues for each traffic
3500                          * class for both 8-TC and 4-TC modes are:
3501                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3502                          * 8 TCs:  32  32  16  16   8   8   8   8
3503                          * 4 TCs:  64  64  32  32
3504                          * We have max 8 queues for FCoE, where 8 the is
3505                          * FCoE redirection table size. If TC for FCoE is
3506                          * less than or equal to TC3, we have enough queues
3507                          * to add max of 8 queues for FCoE, so we start FCoE
3508                          * tx descriptor from the next one, i.e., reg_idx + 1.
3509                          * If TC for FCoE is above TC3, implying 8 TC mode,
3510                          * and we need 8 for FCoE, we have to take all queues
3511                          * in that traffic class for FCoE.
3512                          */
3513                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3514                                 fcoe_tx_i--;
3515                 }
3516 #endif /* CONFIG_IXGBE_DCB */
3517                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3518                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3519                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3520                                 ixgbe_cache_ring_fdir(adapter);
3521                         else
3522                                 ixgbe_cache_ring_rss(adapter);
3523
3524                         fcoe_rx_i = f->mask;
3525                         fcoe_tx_i = f->mask;
3526                 }
3527                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3528                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3529                         adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3530                 }
3531                 ret = true;
3532         }
3533         return ret;
3534 }
3535
3536 #endif /* IXGBE_FCOE */
3537 /**
3538  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3539  * @adapter: board private structure to initialize
3540  *
3541  * Once we know the feature-set enabled for the device, we'll cache
3542  * the register offset the descriptor ring is assigned to.
3543  *
3544  * Note, the order the various feature calls is important.  It must start with
3545  * the "most" features enabled at the same time, then trickle down to the
3546  * least amount of features turned on at once.
3547  **/
3548 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3549 {
3550         /* start with default case */
3551         adapter->rx_ring[0].reg_idx = 0;
3552         adapter->tx_ring[0].reg_idx = 0;
3553
3554 #ifdef IXGBE_FCOE
3555         if (ixgbe_cache_ring_fcoe(adapter))
3556                 return;
3557
3558 #endif /* IXGBE_FCOE */
3559 #ifdef CONFIG_IXGBE_DCB
3560         if (ixgbe_cache_ring_dcb(adapter))
3561                 return;
3562
3563 #endif
3564         if (ixgbe_cache_ring_fdir(adapter))
3565                 return;
3566
3567         if (ixgbe_cache_ring_rss(adapter))
3568                 return;
3569 }
3570
3571 /**
3572  * ixgbe_alloc_queues - Allocate memory for all rings
3573  * @adapter: board private structure to initialize
3574  *
3575  * We allocate one ring per queue at run-time since we don't know the
3576  * number of queues at compile-time.  The polling_netdev array is
3577  * intended for Multiqueue, but should work fine with a single queue.
3578  **/
3579 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3580 {
3581         int i;
3582
3583         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3584                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3585         if (!adapter->tx_ring)
3586                 goto err_tx_ring_allocation;
3587
3588         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3589                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3590         if (!adapter->rx_ring)
3591                 goto err_rx_ring_allocation;
3592
3593         for (i = 0; i < adapter->num_tx_queues; i++) {
3594                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3595                 adapter->tx_ring[i].queue_index = i;
3596         }
3597
3598         for (i = 0; i < adapter->num_rx_queues; i++) {
3599                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3600                 adapter->rx_ring[i].queue_index = i;
3601         }
3602
3603         ixgbe_cache_ring_register(adapter);
3604
3605         return 0;
3606
3607 err_rx_ring_allocation:
3608         kfree(adapter->tx_ring);
3609 err_tx_ring_allocation:
3610         return -ENOMEM;
3611 }
3612
3613 /**
3614  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3615  * @adapter: board private structure to initialize
3616  *
3617  * Attempt to configure the interrupts using the best available
3618  * capabilities of the hardware and the kernel.
3619  **/
3620 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3621 {
3622         struct ixgbe_hw *hw = &adapter->hw;
3623         int err = 0;
3624         int vector, v_budget;
3625
3626         /*
3627          * It's easy to be greedy for MSI-X vectors, but it really
3628          * doesn't do us much good if we have a lot more vectors
3629          * than CPU's.  So let's be conservative and only ask for
3630          * (roughly) twice the number of vectors as there are CPU's.
3631          */
3632         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3633                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3634
3635         /*
3636          * At the same time, hardware can only support a maximum of
3637          * hw.mac->max_msix_vectors vectors.  With features
3638          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3639          * descriptor queues supported by our device.  Thus, we cap it off in
3640          * those rare cases where the cpu count also exceeds our vector limit.
3641          */
3642         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3643
3644         /* A failure in MSI-X entry allocation isn't fatal, but it does
3645          * mean we disable MSI-X capabilities of the adapter. */
3646         adapter->msix_entries = kcalloc(v_budget,
3647                                         sizeof(struct msix_entry), GFP_KERNEL);
3648         if (adapter->msix_entries) {
3649                 for (vector = 0; vector < v_budget; vector++)
3650                         adapter->msix_entries[vector].entry = vector;
3651
3652                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3653
3654                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3655                         goto out;
3656         }
3657
3658         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3659         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3660         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3661         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3662         adapter->atr_sample_rate = 0;
3663         ixgbe_set_num_queues(adapter);
3664
3665         err = pci_enable_msi(adapter->pdev);
3666         if (!err) {
3667                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3668         } else {
3669                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3670                         "falling back to legacy.  Error: %d\n", err);
3671                 /* reset err */
3672                 err = 0;
3673         }
3674
3675 out:
3676         return err;
3677 }
3678
3679 /**
3680  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3681  * @adapter: board private structure to initialize
3682  *
3683  * We allocate one q_vector per queue interrupt.  If allocation fails we
3684  * return -ENOMEM.
3685  **/
3686 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3687 {
3688         int q_idx, num_q_vectors;
3689         struct ixgbe_q_vector *q_vector;
3690         int napi_vectors;
3691         int (*poll)(struct napi_struct *, int);
3692
3693         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3694                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3695                 napi_vectors = adapter->num_rx_queues;
3696                 poll = &ixgbe_clean_rxtx_many;
3697         } else {
3698                 num_q_vectors = 1;
3699                 napi_vectors = 1;
3700                 poll = &ixgbe_poll;
3701         }
3702
3703         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3704                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3705                 if (!q_vector)
3706                         goto err_out;
3707                 q_vector->adapter = adapter;
3708                 if (q_vector->txr_count && !q_vector->rxr_count)
3709                         q_vector->eitr = adapter->tx_eitr_param;
3710                 else
3711                         q_vector->eitr = adapter->rx_eitr_param;
3712                 q_vector->v_idx = q_idx;
3713                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3714                 adapter->q_vector[q_idx] = q_vector;
3715         }
3716
3717         return 0;
3718
3719 err_out:
3720         while (q_idx) {
3721                 q_idx--;
3722                 q_vector = adapter->q_vector[q_idx];
3723                 netif_napi_del(&q_vector->napi);
3724                 kfree(q_vector);
3725                 adapter->q_vector[q_idx] = NULL;
3726         }
3727         return -ENOMEM;
3728 }
3729
3730 /**
3731  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3732  * @adapter: board private structure to initialize
3733  *
3734  * This function frees the memory allocated to the q_vectors.  In addition if
3735  * NAPI is enabled it will delete any references to the NAPI struct prior
3736  * to freeing the q_vector.
3737  **/
3738 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3739 {
3740         int q_idx, num_q_vectors;
3741
3742         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3743                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3744         else
3745                 num_q_vectors = 1;
3746
3747         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3748                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3749                 adapter->q_vector[q_idx] = NULL;
3750                 netif_napi_del(&q_vector->napi);
3751                 kfree(q_vector);
3752         }
3753 }
3754
3755 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3756 {
3757         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3758                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3759                 pci_disable_msix(adapter->pdev);
3760                 kfree(adapter->msix_entries);
3761                 adapter->msix_entries = NULL;
3762         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3763                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3764                 pci_disable_msi(adapter->pdev);
3765         }
3766         return;
3767 }
3768
3769 /**
3770  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3771  * @adapter: board private structure to initialize
3772  *
3773  * We determine which interrupt scheme to use based on...
3774  * - Kernel support (MSI, MSI-X)
3775  *   - which can be user-defined (via MODULE_PARAM)
3776  * - Hardware queue count (num_*_queues)
3777  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3778  **/
3779 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3780 {
3781         int err;
3782
3783         /* Number of supported queues */
3784         ixgbe_set_num_queues(adapter);
3785
3786         err = ixgbe_set_interrupt_capability(adapter);
3787         if (err) {
3788                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3789                 goto err_set_interrupt;
3790         }
3791
3792         err = ixgbe_alloc_q_vectors(adapter);
3793         if (err) {
3794                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3795                         "vectors\n");
3796                 goto err_alloc_q_vectors;
3797         }
3798
3799         err = ixgbe_alloc_queues(adapter);
3800         if (err) {
3801                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3802                 goto err_alloc_queues;
3803         }
3804
3805         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3806                 "Tx Queue count = %u\n",
3807                 (adapter->num_rx_queues > 1) ? "Enabled" :
3808                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3809
3810         set_bit(__IXGBE_DOWN, &adapter->state);
3811
3812         return 0;
3813
3814 err_alloc_queues:
3815         ixgbe_free_q_vectors(adapter);
3816 err_alloc_q_vectors:
3817         ixgbe_reset_interrupt_capability(adapter);
3818 err_set_interrupt:
3819         return err;
3820 }
3821
3822 /**
3823  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3824  * @adapter: board private structure to clear interrupt scheme on
3825  *
3826  * We go through and clear interrupt specific resources and reset the structure
3827  * to pre-load conditions
3828  **/
3829 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3830 {
3831         kfree(adapter->tx_ring);
3832         kfree(adapter->rx_ring);
3833         adapter->tx_ring = NULL;
3834         adapter->rx_ring = NULL;
3835
3836         ixgbe_free_q_vectors(adapter);
3837         ixgbe_reset_interrupt_capability(adapter);
3838 }
3839
3840 /**
3841  * ixgbe_sfp_timer - worker thread to find a missing module
3842  * @data: pointer to our adapter struct
3843  **/
3844 static void ixgbe_sfp_timer(unsigned long data)
3845 {
3846         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3847
3848         /*
3849          * Do the sfp_timer outside of interrupt context due to the
3850          * delays that sfp+ detection requires
3851          */
3852         schedule_work(&adapter->sfp_task);
3853 }
3854
3855 /**
3856  * ixgbe_sfp_task - worker thread to find a missing module
3857  * @work: pointer to work_struct containing our data
3858  **/
3859 static void ixgbe_sfp_task(struct work_struct *work)
3860 {
3861         struct ixgbe_adapter *adapter = container_of(work,
3862                                                      struct ixgbe_adapter,
3863                                                      sfp_task);
3864         struct ixgbe_hw *hw = &adapter->hw;
3865
3866         if ((hw->phy.type == ixgbe_phy_nl) &&
3867             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3868                 s32 ret = hw->phy.ops.identify_sfp(hw);
3869                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3870                         goto reschedule;
3871                 ret = hw->phy.ops.reset(hw);
3872                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3873                         dev_err(&adapter->pdev->dev, "failed to initialize "
3874                                 "because an unsupported SFP+ module type "
3875                                 "was detected.\n"
3876                                 "Reload the driver after installing a "
3877                                 "supported module.\n");
3878                         unregister_netdev(adapter->netdev);
3879                 } else {
3880                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3881                                 hw->phy.sfp_type);
3882                 }
3883                 /* don't need this routine any more */
3884                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3885         }
3886         return;
3887 reschedule:
3888         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3889                 mod_timer(&adapter->sfp_timer,
3890                           round_jiffies(jiffies + (2 * HZ)));
3891 }
3892
3893 /**
3894  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3895  * @adapter: board private structure to initialize
3896  *
3897  * ixgbe_sw_init initializes the Adapter private data structure.
3898  * Fields are initialized based on PCI device information and
3899  * OS network device settings (MTU size).
3900  **/
3901 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3902 {
3903         struct ixgbe_hw *hw = &adapter->hw;
3904         struct pci_dev *pdev = adapter->pdev;
3905         unsigned int rss;
3906 #ifdef CONFIG_IXGBE_DCB
3907         int j;
3908         struct tc_configuration *tc;
3909 #endif
3910
3911         /* PCI config space info */
3912
3913         hw->vendor_id = pdev->vendor;
3914         hw->device_id = pdev->device;
3915         hw->revision_id = pdev->revision;
3916         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3917         hw->subsystem_device_id = pdev->subsystem_device;
3918
3919         /* Set capability flags */
3920         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3921         adapter->ring_feature[RING_F_RSS].indices = rss;
3922         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3923         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3924         if (hw->mac.type == ixgbe_mac_82598EB) {
3925                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3926                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3927                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3928         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3929                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3930                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3931                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3932                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3933                 adapter->ring_feature[RING_F_FDIR].indices =
3934                                                          IXGBE_MAX_FDIR_INDICES;
3935                 adapter->atr_sample_rate = 20;
3936                 adapter->fdir_pballoc = 0;
3937 #ifdef IXGBE_FCOE
3938                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3939                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3940                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3941                 /* Default traffic class to use for FCoE */
3942                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3943 #endif /* IXGBE_FCOE */
3944         }
3945
3946 #ifdef CONFIG_IXGBE_DCB
3947         /* Configure DCB traffic classes */
3948         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3949                 tc = &adapter->dcb_cfg.tc_config[j];
3950                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3951                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3952                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3953                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3954                 tc->dcb_pfc = pfc_disabled;
3955         }
3956         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3957         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3958         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3959         adapter->dcb_cfg.pfc_mode_enable = false;
3960         adapter->dcb_cfg.round_robin_enable = false;
3961         adapter->dcb_set_bitmap = 0x00;
3962         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3963                            adapter->ring_feature[RING_F_DCB].indices);
3964
3965 #endif
3966
3967         /* default flow control settings */
3968         hw->fc.requested_mode = ixgbe_fc_full;
3969         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3970 #ifdef CONFIG_DCB
3971         adapter->last_lfc_mode = hw->fc.current_mode;
3972 #endif
3973         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3974         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3975         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3976         hw->fc.send_xon = true;
3977         hw->fc.disable_fc_autoneg = false;
3978
3979         /* enable itr by default in dynamic mode */
3980         adapter->rx_itr_setting = 1;
3981         adapter->rx_eitr_param = 20000;
3982         adapter->tx_itr_setting = 1;
3983         adapter->tx_eitr_param = 10000;
3984
3985         /* set defaults for eitr in MegaBytes */
3986         adapter->eitr_low = 10;
3987         adapter->eitr_high = 20;
3988
3989         /* set default ring sizes */
3990         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3991         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3992
3993         /* initialize eeprom parameters */
3994         if (ixgbe_init_eeprom_params_generic(hw)) {
3995                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3996                 return -EIO;
3997         }
3998
3999         /* enable rx csum by default */
4000         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4001
4002         set_bit(__IXGBE_DOWN, &adapter->state);
4003
4004         return 0;
4005 }
4006
4007 /**
4008  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4009  * @adapter: board private structure
4010  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4011  *
4012  * Return 0 on success, negative on failure
4013  **/
4014 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4015                              struct ixgbe_ring *tx_ring)
4016 {
4017         struct pci_dev *pdev = adapter->pdev;
4018         int size;
4019
4020         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4021         tx_ring->tx_buffer_info = vmalloc(size);
4022         if (!tx_ring->tx_buffer_info)
4023                 goto err;
4024         memset(tx_ring->tx_buffer_info, 0, size);
4025
4026         /* round up to nearest 4K */
4027         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4028         tx_ring->size = ALIGN(tx_ring->size, 4096);
4029
4030         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4031                                              &tx_ring->dma);
4032         if (!tx_ring->desc)
4033                 goto err;
4034
4035         tx_ring->next_to_use = 0;
4036         tx_ring->next_to_clean = 0;
4037         tx_ring->work_limit = tx_ring->count;
4038         return 0;
4039
4040 err:
4041         vfree(tx_ring->tx_buffer_info);
4042         tx_ring->tx_buffer_info = NULL;
4043         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4044                             "descriptor ring\n");
4045         return -ENOMEM;
4046 }
4047
4048 /**
4049  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4050  * @adapter: board private structure
4051  *
4052  * If this function returns with an error, then it's possible one or
4053  * more of the rings is populated (while the rest are not).  It is the
4054  * callers duty to clean those orphaned rings.
4055  *
4056  * Return 0 on success, negative on failure
4057  **/
4058 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4059 {
4060         int i, err = 0;
4061
4062         for (i = 0; i < adapter->num_tx_queues; i++) {
4063                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4064                 if (!err)
4065                         continue;
4066                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4067                 break;
4068         }
4069
4070         return err;
4071 }
4072
4073 /**
4074  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4075  * @adapter: board private structure
4076  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4077  *
4078  * Returns 0 on success, negative on failure
4079  **/
4080 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4081                              struct ixgbe_ring *rx_ring)
4082 {
4083         struct pci_dev *pdev = adapter->pdev;
4084         int size;
4085
4086         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4087         rx_ring->rx_buffer_info = vmalloc(size);
4088         if (!rx_ring->rx_buffer_info) {
4089                 DPRINTK(PROBE, ERR,
4090                         "vmalloc allocation failed for the rx desc ring\n");
4091                 goto alloc_failed;
4092         }
4093         memset(rx_ring->rx_buffer_info, 0, size);
4094
4095         /* Round up to nearest 4K */
4096         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4097         rx_ring->size = ALIGN(rx_ring->size, 4096);
4098
4099         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4100
4101         if (!rx_ring->desc) {
4102                 DPRINTK(PROBE, ERR,
4103                         "Memory allocation failed for the rx desc ring\n");
4104                 vfree(rx_ring->rx_buffer_info);
4105                 goto alloc_failed;
4106         }
4107
4108         rx_ring->next_to_clean = 0;
4109         rx_ring->next_to_use = 0;
4110
4111         return 0;
4112
4113 alloc_failed:
4114         return -ENOMEM;
4115 }
4116
4117 /**
4118  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4119  * @adapter: board private structure
4120  *
4121  * If this function returns with an error, then it's possible one or
4122  * more of the rings is populated (while the rest are not).  It is the
4123  * callers duty to clean those orphaned rings.
4124  *
4125  * Return 0 on success, negative on failure
4126  **/
4127
4128 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4129 {
4130         int i, err = 0;
4131
4132         for (i = 0; i < adapter->num_rx_queues; i++) {
4133                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4134                 if (!err)
4135                         continue;
4136                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4137                 break;
4138         }
4139
4140         return err;
4141 }
4142
4143 /**
4144  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4145  * @adapter: board private structure
4146  * @tx_ring: Tx descriptor ring for a specific queue
4147  *
4148  * Free all transmit software resources
4149  **/
4150 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4151                              struct ixgbe_ring *tx_ring)
4152 {
4153         struct pci_dev *pdev = adapter->pdev;
4154
4155         ixgbe_clean_tx_ring(adapter, tx_ring);
4156
4157         vfree(tx_ring->tx_buffer_info);
4158         tx_ring->tx_buffer_info = NULL;
4159
4160         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4161
4162         tx_ring->desc = NULL;
4163 }
4164
4165 /**
4166  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4167  * @adapter: board private structure
4168  *
4169  * Free all transmit software resources
4170  **/
4171 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4172 {
4173         int i;
4174
4175         for (i = 0; i < adapter->num_tx_queues; i++)
4176                 if (adapter->tx_ring[i].desc)
4177                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4178 }
4179
4180 /**
4181  * ixgbe_free_rx_resources - Free Rx Resources
4182  * @adapter: board private structure
4183  * @rx_ring: ring to clean the resources from
4184  *
4185  * Free all receive software resources
4186  **/
4187 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4188                              struct ixgbe_ring *rx_ring)
4189 {
4190         struct pci_dev *pdev = adapter->pdev;
4191
4192         ixgbe_clean_rx_ring(adapter, rx_ring);
4193
4194         vfree(rx_ring->rx_buffer_info);
4195         rx_ring->rx_buffer_info = NULL;
4196
4197         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4198
4199         rx_ring->desc = NULL;
4200 }
4201
4202 /**
4203  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4204  * @adapter: board private structure
4205  *
4206  * Free all receive software resources
4207  **/
4208 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4209 {
4210         int i;
4211
4212         for (i = 0; i < adapter->num_rx_queues; i++)
4213                 if (adapter->rx_ring[i].desc)
4214                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4215 }
4216
4217 /**
4218  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4219  * @netdev: network interface device structure
4220  * @new_mtu: new value for maximum frame size
4221  *
4222  * Returns 0 on success, negative on failure
4223  **/
4224 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4225 {
4226         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4227         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4228
4229         /* MTU < 68 is an error and causes problems on some kernels */
4230         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4231                 return -EINVAL;
4232
4233         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4234                 netdev->mtu, new_mtu);
4235         /* must set new MTU before calling down or up */
4236         netdev->mtu = new_mtu;
4237
4238         if (netif_running(netdev))
4239                 ixgbe_reinit_locked(adapter);
4240
4241         return 0;
4242 }
4243
4244 /**
4245  * ixgbe_open - Called when a network interface is made active
4246  * @netdev: network interface device structure
4247  *
4248  * Returns 0 on success, negative value on failure
4249  *
4250  * The open entry point is called when a network interface is made
4251  * active by the system (IFF_UP).  At this point all resources needed
4252  * for transmit and receive operations are allocated, the interrupt
4253  * handler is registered with the OS, the watchdog timer is started,
4254  * and the stack is notified that the interface is ready.
4255  **/
4256 static int ixgbe_open(struct net_device *netdev)
4257 {
4258         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4259         int err;
4260
4261         /* disallow open during test */
4262         if (test_bit(__IXGBE_TESTING, &adapter->state))
4263                 return -EBUSY;
4264
4265         netif_carrier_off(netdev);
4266
4267         /* allocate transmit descriptors */
4268         err = ixgbe_setup_all_tx_resources(adapter);
4269         if (err)
4270                 goto err_setup_tx;
4271
4272         /* allocate receive descriptors */
4273         err = ixgbe_setup_all_rx_resources(adapter);
4274         if (err)
4275                 goto err_setup_rx;
4276
4277         ixgbe_configure(adapter);
4278
4279         err = ixgbe_request_irq(adapter);
4280         if (err)
4281                 goto err_req_irq;
4282
4283         err = ixgbe_up_complete(adapter);
4284         if (err)
4285                 goto err_up;
4286
4287         netif_tx_start_all_queues(netdev);
4288
4289         return 0;
4290
4291 err_up:
4292         ixgbe_release_hw_control(adapter);
4293         ixgbe_free_irq(adapter);
4294 err_req_irq:
4295 err_setup_rx:
4296         ixgbe_free_all_rx_resources(adapter);
4297 err_setup_tx:
4298         ixgbe_free_all_tx_resources(adapter);
4299         ixgbe_reset(adapter);
4300
4301         return err;
4302 }
4303
4304 /**
4305  * ixgbe_close - Disables a network interface
4306  * @netdev: network interface device structure
4307  *
4308  * Returns 0, this is not allowed to fail
4309  *
4310  * The close entry point is called when an interface is de-activated
4311  * by the OS.  The hardware is still under the drivers control, but
4312  * needs to be disabled.  A global MAC reset is issued to stop the
4313  * hardware, and all transmit and receive resources are freed.
4314  **/
4315 static int ixgbe_close(struct net_device *netdev)
4316 {
4317         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4318
4319         ixgbe_down(adapter);
4320         ixgbe_free_irq(adapter);
4321
4322         ixgbe_free_all_tx_resources(adapter);
4323         ixgbe_free_all_rx_resources(adapter);
4324
4325         ixgbe_release_hw_control(adapter);
4326
4327         return 0;
4328 }
4329
4330 #ifdef CONFIG_PM
4331 static int ixgbe_resume(struct pci_dev *pdev)
4332 {
4333         struct net_device *netdev = pci_get_drvdata(pdev);
4334         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4335         u32 err;
4336
4337         pci_set_power_state(pdev, PCI_D0);
4338         pci_restore_state(pdev);
4339
4340         err = pci_enable_device_mem(pdev);
4341         if (err) {
4342                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4343                                 "suspend\n");
4344                 return err;
4345         }
4346         pci_set_master(pdev);
4347
4348         pci_wake_from_d3(pdev, false);
4349
4350         err = ixgbe_init_interrupt_scheme(adapter);
4351         if (err) {
4352                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4353                                 "device\n");
4354                 return err;
4355         }
4356
4357         ixgbe_reset(adapter);
4358
4359         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4360
4361         if (netif_running(netdev)) {
4362                 err = ixgbe_open(adapter->netdev);
4363                 if (err)
4364                         return err;
4365         }
4366
4367         netif_device_attach(netdev);
4368
4369         return 0;
4370 }
4371 #endif /* CONFIG_PM */
4372
4373 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4374 {
4375         struct net_device *netdev = pci_get_drvdata(pdev);
4376         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4377         struct ixgbe_hw *hw = &adapter->hw;
4378         u32 ctrl, fctrl;
4379         u32 wufc = adapter->wol;
4380 #ifdef CONFIG_PM
4381         int retval = 0;
4382 #endif
4383
4384         netif_device_detach(netdev);
4385
4386         if (netif_running(netdev)) {
4387                 ixgbe_down(adapter);
4388                 ixgbe_free_irq(adapter);
4389                 ixgbe_free_all_tx_resources(adapter);
4390                 ixgbe_free_all_rx_resources(adapter);
4391         }
4392         ixgbe_clear_interrupt_scheme(adapter);
4393
4394 #ifdef CONFIG_PM
4395         retval = pci_save_state(pdev);
4396         if (retval)
4397                 return retval;
4398
4399 #endif
4400         if (wufc) {
4401                 ixgbe_set_rx_mode(netdev);
4402
4403                 /* turn on all-multi mode if wake on multicast is enabled */
4404                 if (wufc & IXGBE_WUFC_MC) {
4405                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4406                         fctrl |= IXGBE_FCTRL_MPE;
4407                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4408                 }
4409
4410                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4411                 ctrl |= IXGBE_CTRL_GIO_DIS;
4412                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4413
4414                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4415         } else {
4416                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4417                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4418         }
4419
4420         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4421                 pci_wake_from_d3(pdev, true);
4422         else
4423                 pci_wake_from_d3(pdev, false);
4424
4425         *enable_wake = !!wufc;
4426
4427         ixgbe_release_hw_control(adapter);
4428
4429         pci_disable_device(pdev);
4430
4431         return 0;
4432 }
4433
4434 #ifdef CONFIG_PM
4435 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4436 {
4437         int retval;
4438         bool wake;
4439
4440         retval = __ixgbe_shutdown(pdev, &wake);
4441         if (retval)
4442                 return retval;
4443
4444         if (wake) {
4445                 pci_prepare_to_sleep(pdev);
4446         } else {
4447                 pci_wake_from_d3(pdev, false);
4448                 pci_set_power_state(pdev, PCI_D3hot);
4449         }
4450
4451         return 0;
4452 }
4453 #endif /* CONFIG_PM */
4454
4455 static void ixgbe_shutdown(struct pci_dev *pdev)
4456 {
4457         bool wake;
4458
4459         __ixgbe_shutdown(pdev, &wake);
4460
4461         if (system_state == SYSTEM_POWER_OFF) {
4462                 pci_wake_from_d3(pdev, wake);
4463                 pci_set_power_state(pdev, PCI_D3hot);
4464         }
4465 }
4466
4467 /**
4468  * ixgbe_update_stats - Update the board statistics counters.
4469  * @adapter: board private structure
4470  **/
4471 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4472 {
4473         struct net_device *netdev = adapter->netdev;
4474         struct ixgbe_hw *hw = &adapter->hw;
4475         u64 total_mpc = 0;
4476         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4477
4478         if (hw->mac.type == ixgbe_mac_82599EB) {
4479                 u64 rsc_count = 0;
4480                 for (i = 0; i < 16; i++)
4481                         adapter->hw_rx_no_dma_resources +=
4482                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4483                 for (i = 0; i < adapter->num_rx_queues; i++)
4484                         rsc_count += adapter->rx_ring[i].rsc_count;
4485                 adapter->rsc_count = rsc_count;
4486         }
4487
4488         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4489         for (i = 0; i < 8; i++) {
4490                 /* for packet buffers not used, the register should read 0 */
4491                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4492                 missed_rx += mpc;
4493                 adapter->stats.mpc[i] += mpc;
4494                 total_mpc += adapter->stats.mpc[i];
4495                 if (hw->mac.type == ixgbe_mac_82598EB)
4496                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4497                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4498                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4499                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4500                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4501                 if (hw->mac.type == ixgbe_mac_82599EB) {
4502                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4503                                                             IXGBE_PXONRXCNT(i));
4504                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4505                                                            IXGBE_PXOFFRXCNT(i));
4506                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4507                 } else {
4508                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4509                                                               IXGBE_PXONRXC(i));
4510                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4511                                                              IXGBE_PXOFFRXC(i));
4512                 }
4513                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4514                                                             IXGBE_PXONTXC(i));
4515                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4516                                                              IXGBE_PXOFFTXC(i));
4517         }
4518         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4519         /* work around hardware counting issue */
4520         adapter->stats.gprc -= missed_rx;
4521
4522         /* 82598 hardware only has a 32 bit counter in the high register */
4523         if (hw->mac.type == ixgbe_mac_82599EB) {
4524                 u64 tmp;
4525                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4526                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4527                 adapter->stats.gorc += (tmp << 32);
4528                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4529                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4530                 adapter->stats.gotc += (tmp << 32);
4531                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4532                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4533                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4534                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4535                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4536                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4537 #ifdef IXGBE_FCOE
4538                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4539                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4540                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4541                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4542                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4543                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4544 #endif /* IXGBE_FCOE */
4545         } else {
4546                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4547                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4548                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4549                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4550                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4551         }
4552         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4553         adapter->stats.bprc += bprc;
4554         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4555         if (hw->mac.type == ixgbe_mac_82598EB)
4556                 adapter->stats.mprc -= bprc;
4557         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4558         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4559         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4560         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4561         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4562         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4563         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4564         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4565         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4566         adapter->stats.lxontxc += lxon;
4567         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4568         adapter->stats.lxofftxc += lxoff;
4569         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4570         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4571         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4572         /*
4573          * 82598 errata - tx of flow control packets is included in tx counters
4574          */
4575         xon_off_tot = lxon + lxoff;
4576         adapter->stats.gptc -= xon_off_tot;
4577         adapter->stats.mptc -= xon_off_tot;
4578         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4579         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4580         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4581         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4582         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4583         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4584         adapter->stats.ptc64 -= xon_off_tot;
4585         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4586         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4587         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4588         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4589         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4590         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4591
4592         /* Fill out the OS statistics structure */
4593         netdev->stats.multicast = adapter->stats.mprc;
4594
4595         /* Rx Errors */
4596         netdev->stats.rx_errors = adapter->stats.crcerrs +
4597                                        adapter->stats.rlec;
4598         netdev->stats.rx_dropped = 0;
4599         netdev->stats.rx_length_errors = adapter->stats.rlec;
4600         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4601         netdev->stats.rx_missed_errors = total_mpc;
4602 }
4603
4604 /**
4605  * ixgbe_watchdog - Timer Call-back
4606  * @data: pointer to adapter cast into an unsigned long
4607  **/
4608 static void ixgbe_watchdog(unsigned long data)
4609 {
4610         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4611         struct ixgbe_hw *hw = &adapter->hw;
4612         u64 eics = 0;
4613         int i;
4614
4615         /*
4616          *  Do the watchdog outside of interrupt context due to the lovely
4617          * delays that some of the newer hardware requires
4618          */
4619
4620         if (test_bit(__IXGBE_DOWN, &adapter->state))
4621                 goto watchdog_short_circuit;
4622
4623         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4624                 /*
4625                  * for legacy and MSI interrupts don't set any bits
4626                  * that are enabled for EIAM, because this operation
4627                  * would set *both* EIMS and EICS for any bit in EIAM
4628                  */
4629                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4630                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4631                 goto watchdog_reschedule;
4632         }
4633
4634         /* get one bit for every active tx/rx interrupt vector */
4635         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4636                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4637                 if (qv->rxr_count || qv->txr_count)
4638                         eics |= ((u64)1 << i);
4639         }
4640
4641         /* Cause software interrupt to ensure rx rings are cleaned */
4642         ixgbe_irq_rearm_queues(adapter, eics);
4643
4644 watchdog_reschedule:
4645         /* Reset the timer */
4646         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4647
4648 watchdog_short_circuit:
4649         schedule_work(&adapter->watchdog_task);
4650 }
4651
4652 /**
4653  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4654  * @work: pointer to work_struct containing our data
4655  **/
4656 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4657 {
4658         struct ixgbe_adapter *adapter = container_of(work,
4659                                                      struct ixgbe_adapter,
4660                                                      multispeed_fiber_task);
4661         struct ixgbe_hw *hw = &adapter->hw;
4662         u32 autoneg;
4663         bool negotiation;
4664
4665         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4666         autoneg = hw->phy.autoneg_advertised;
4667         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4668                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4669         if (hw->mac.ops.setup_link)
4670                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4671         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4672         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4673 }
4674
4675 /**
4676  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4677  * @work: pointer to work_struct containing our data
4678  **/
4679 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4680 {
4681         struct ixgbe_adapter *adapter = container_of(work,
4682                                                      struct ixgbe_adapter,
4683                                                      sfp_config_module_task);
4684         struct ixgbe_hw *hw = &adapter->hw;
4685         u32 err;
4686
4687         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4688
4689         /* Time for electrical oscillations to settle down */
4690         msleep(100);
4691         err = hw->phy.ops.identify_sfp(hw);
4692
4693         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4694                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4695                         "an unsupported SFP+ module type was detected.\n"
4696                         "Reload the driver after installing a supported "
4697                         "module.\n");
4698                 unregister_netdev(adapter->netdev);
4699                 return;
4700         }
4701         hw->mac.ops.setup_sfp(hw);
4702
4703         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4704                 /* This will also work for DA Twinax connections */
4705                 schedule_work(&adapter->multispeed_fiber_task);
4706         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4707 }
4708
4709 /**
4710  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4711  * @work: pointer to work_struct containing our data
4712  **/
4713 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4714 {
4715         struct ixgbe_adapter *adapter = container_of(work,
4716                                                      struct ixgbe_adapter,
4717                                                      fdir_reinit_task);
4718         struct ixgbe_hw *hw = &adapter->hw;
4719         int i;
4720
4721         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4722                 for (i = 0; i < adapter->num_tx_queues; i++)
4723                         set_bit(__IXGBE_FDIR_INIT_DONE,
4724                                 &(adapter->tx_ring[i].reinit_state));
4725         } else {
4726                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4727                         "ignored adding FDIR ATR filters \n");
4728         }
4729         /* Done FDIR Re-initialization, enable transmits */
4730         netif_tx_start_all_queues(adapter->netdev);
4731 }
4732
4733 /**
4734  * ixgbe_watchdog_task - worker thread to bring link up
4735  * @work: pointer to work_struct containing our data
4736  **/
4737 static void ixgbe_watchdog_task(struct work_struct *work)
4738 {
4739         struct ixgbe_adapter *adapter = container_of(work,
4740                                                      struct ixgbe_adapter,
4741                                                      watchdog_task);
4742         struct net_device *netdev = adapter->netdev;
4743         struct ixgbe_hw *hw = &adapter->hw;
4744         u32 link_speed = adapter->link_speed;
4745         bool link_up = adapter->link_up;
4746         int i;
4747         struct ixgbe_ring *tx_ring;
4748         int some_tx_pending = 0;
4749
4750         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4751
4752         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4753                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4754                 if (link_up) {
4755 #ifdef CONFIG_DCB
4756                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4757                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4758                                         hw->mac.ops.fc_enable(hw, i);
4759                         } else {
4760                                 hw->mac.ops.fc_enable(hw, 0);
4761                         }
4762 #else
4763                         hw->mac.ops.fc_enable(hw, 0);
4764 #endif
4765                 }
4766
4767                 if (link_up ||
4768                     time_after(jiffies, (adapter->link_check_timeout +
4769                                          IXGBE_TRY_LINK_TIMEOUT))) {
4770                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4771                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4772                 }
4773                 adapter->link_up = link_up;
4774                 adapter->link_speed = link_speed;
4775         }
4776
4777         if (link_up) {
4778                 if (!netif_carrier_ok(netdev)) {
4779                         bool flow_rx, flow_tx;
4780
4781                         if (hw->mac.type == ixgbe_mac_82599EB) {
4782                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4783                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4784                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4785                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4786                         } else {
4787                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4788                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4789                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4790                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4791                         }
4792
4793                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4794                                "Flow Control: %s\n",
4795                                netdev->name,
4796                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4797                                 "10 Gbps" :
4798                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4799                                  "1 Gbps" : "unknown speed")),
4800                                ((flow_rx && flow_tx) ? "RX/TX" :
4801                                 (flow_rx ? "RX" :
4802                                 (flow_tx ? "TX" : "None"))));
4803
4804                         netif_carrier_on(netdev);
4805                 } else {
4806                         /* Force detection of hung controller */
4807                         adapter->detect_tx_hung = true;
4808                 }
4809         } else {
4810                 adapter->link_up = false;
4811                 adapter->link_speed = 0;
4812                 if (netif_carrier_ok(netdev)) {
4813                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4814                                netdev->name);
4815                         netif_carrier_off(netdev);
4816                 }
4817         }
4818
4819         if (!netif_carrier_ok(netdev)) {
4820                 for (i = 0; i < adapter->num_tx_queues; i++) {
4821                         tx_ring = &adapter->tx_ring[i];
4822                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4823                                 some_tx_pending = 1;
4824                                 break;
4825                         }
4826                 }
4827
4828                 if (some_tx_pending) {
4829                         /* We've lost link, so the controller stops DMA,
4830                          * but we've got queued Tx work that's never going
4831                          * to get done, so reset controller to flush Tx.
4832                          * (Do the reset outside of interrupt context).
4833                          */
4834                          schedule_work(&adapter->reset_task);
4835                 }
4836         }
4837
4838         ixgbe_update_stats(adapter);
4839         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4840 }
4841
4842 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4843                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4844                      u32 tx_flags, u8 *hdr_len)
4845 {
4846         struct ixgbe_adv_tx_context_desc *context_desc;
4847         unsigned int i;
4848         int err;
4849         struct ixgbe_tx_buffer *tx_buffer_info;
4850         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4851         u32 mss_l4len_idx, l4len;
4852
4853         if (skb_is_gso(skb)) {
4854                 if (skb_header_cloned(skb)) {
4855                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4856                         if (err)
4857                                 return err;
4858                 }
4859                 l4len = tcp_hdrlen(skb);
4860                 *hdr_len += l4len;
4861
4862                 if (skb->protocol == htons(ETH_P_IP)) {
4863                         struct iphdr *iph = ip_hdr(skb);
4864                         iph->tot_len = 0;
4865                         iph->check = 0;
4866                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4867                                                                  iph->daddr, 0,
4868                                                                  IPPROTO_TCP,
4869                                                                  0);
4870                         adapter->hw_tso_ctxt++;
4871                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4872                         ipv6_hdr(skb)->payload_len = 0;
4873                         tcp_hdr(skb)->check =
4874                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4875                                              &ipv6_hdr(skb)->daddr,
4876                                              0, IPPROTO_TCP, 0);
4877                         adapter->hw_tso6_ctxt++;
4878                 }
4879
4880                 i = tx_ring->next_to_use;
4881
4882                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4883                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4884
4885                 /* VLAN MACLEN IPLEN */
4886                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4887                         vlan_macip_lens |=
4888                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4889                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4890                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4891                 *hdr_len += skb_network_offset(skb);
4892                 vlan_macip_lens |=
4893                     (skb_transport_header(skb) - skb_network_header(skb));
4894                 *hdr_len +=
4895                     (skb_transport_header(skb) - skb_network_header(skb));
4896                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4897                 context_desc->seqnum_seed = 0;
4898
4899                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4900                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4901                                    IXGBE_ADVTXD_DTYP_CTXT);
4902
4903                 if (skb->protocol == htons(ETH_P_IP))
4904                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4905                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4906                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4907
4908                 /* MSS L4LEN IDX */
4909                 mss_l4len_idx =
4910                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4911                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4912                 /* use index 1 for TSO */
4913                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4914                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4915
4916                 tx_buffer_info->time_stamp = jiffies;
4917                 tx_buffer_info->next_to_watch = i;
4918
4919                 i++;
4920                 if (i == tx_ring->count)
4921                         i = 0;
4922                 tx_ring->next_to_use = i;
4923
4924                 return true;
4925         }
4926         return false;
4927 }
4928
4929 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4930                           struct ixgbe_ring *tx_ring,
4931                           struct sk_buff *skb, u32 tx_flags)
4932 {
4933         struct ixgbe_adv_tx_context_desc *context_desc;
4934         unsigned int i;
4935         struct ixgbe_tx_buffer *tx_buffer_info;
4936         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4937
4938         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4939             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4940                 i = tx_ring->next_to_use;
4941                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4942                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4943
4944                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4945                         vlan_macip_lens |=
4946                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4947                 vlan_macip_lens |= (skb_network_offset(skb) <<
4948                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4949                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4950                         vlan_macip_lens |= (skb_transport_header(skb) -
4951                                             skb_network_header(skb));
4952
4953                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4954                 context_desc->seqnum_seed = 0;
4955
4956                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4957                                     IXGBE_ADVTXD_DTYP_CTXT);
4958
4959                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4960                         switch (skb->protocol) {
4961                         case cpu_to_be16(ETH_P_IP):
4962                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4963                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4964                                         type_tucmd_mlhl |=
4965                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4966                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4967                                         type_tucmd_mlhl |=
4968                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4969                                 break;
4970                         case cpu_to_be16(ETH_P_IPV6):
4971                                 /* XXX what about other V6 headers?? */
4972                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4973                                         type_tucmd_mlhl |=
4974                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4975                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4976                                         type_tucmd_mlhl |=
4977                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4978                                 break;
4979                         default:
4980                                 if (unlikely(net_ratelimit())) {
4981                                         DPRINTK(PROBE, WARNING,
4982                                          "partial checksum but proto=%x!\n",
4983                                          skb->protocol);
4984                                 }
4985                                 break;
4986                         }
4987                 }
4988
4989                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4990                 /* use index zero for tx checksum offload */
4991                 context_desc->mss_l4len_idx = 0;
4992
4993                 tx_buffer_info->time_stamp = jiffies;
4994                 tx_buffer_info->next_to_watch = i;
4995
4996                 adapter->hw_csum_tx_good++;
4997                 i++;
4998                 if (i == tx_ring->count)
4999                         i = 0;
5000                 tx_ring->next_to_use = i;
5001
5002                 return true;
5003         }
5004
5005         return false;
5006 }
5007
5008 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5009                         struct ixgbe_ring *tx_ring,
5010                         struct sk_buff *skb, u32 tx_flags,
5011                         unsigned int first)
5012 {
5013         struct ixgbe_tx_buffer *tx_buffer_info;
5014         unsigned int len;
5015         unsigned int total = skb->len;
5016         unsigned int offset = 0, size, count = 0, i;
5017         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5018         unsigned int f;
5019         dma_addr_t *map;
5020
5021         i = tx_ring->next_to_use;
5022
5023         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
5024                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
5025                 return 0;
5026         }
5027
5028         map = skb_shinfo(skb)->dma_maps;
5029
5030         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5031                 /* excluding fcoe_crc_eof for FCoE */
5032                 total -= sizeof(struct fcoe_crc_eof);
5033
5034         len = min(skb_headlen(skb), total);
5035         while (len) {
5036                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5037                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5038
5039                 tx_buffer_info->length = size;
5040                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
5041                 tx_buffer_info->time_stamp = jiffies;
5042                 tx_buffer_info->next_to_watch = i;
5043
5044                 len -= size;
5045                 total -= size;
5046                 offset += size;
5047                 count++;
5048
5049                 if (len) {
5050                         i++;
5051                         if (i == tx_ring->count)
5052                                 i = 0;
5053                 }
5054         }
5055
5056         for (f = 0; f < nr_frags; f++) {
5057                 struct skb_frag_struct *frag;
5058
5059                 frag = &skb_shinfo(skb)->frags[f];
5060                 len = min((unsigned int)frag->size, total);
5061                 offset = 0;
5062
5063                 while (len) {
5064                         i++;
5065                         if (i == tx_ring->count)
5066                                 i = 0;
5067
5068                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5069                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5070
5071                         tx_buffer_info->length = size;
5072                         tx_buffer_info->dma = map[f] + offset;
5073                         tx_buffer_info->time_stamp = jiffies;
5074                         tx_buffer_info->next_to_watch = i;
5075
5076                         len -= size;
5077                         total -= size;
5078                         offset += size;
5079                         count++;
5080                 }
5081                 if (total == 0)
5082                         break;
5083         }
5084
5085         tx_ring->tx_buffer_info[i].skb = skb;
5086         tx_ring->tx_buffer_info[first].next_to_watch = i;
5087
5088         return count;
5089 }
5090
5091 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5092                            struct ixgbe_ring *tx_ring,
5093                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5094 {
5095         union ixgbe_adv_tx_desc *tx_desc = NULL;
5096         struct ixgbe_tx_buffer *tx_buffer_info;
5097         u32 olinfo_status = 0, cmd_type_len = 0;
5098         unsigned int i;
5099         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5100
5101         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5102
5103         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5104
5105         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5106                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5107
5108         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5109                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5110
5111                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5112                                  IXGBE_ADVTXD_POPTS_SHIFT;
5113
5114                 /* use index 1 context for tso */
5115                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5116                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5117                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5118                                          IXGBE_ADVTXD_POPTS_SHIFT;
5119
5120         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5121                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5122                                  IXGBE_ADVTXD_POPTS_SHIFT;
5123
5124         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5125                 olinfo_status |= IXGBE_ADVTXD_CC;
5126                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5127                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5128                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5129         }
5130
5131         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5132
5133         i = tx_ring->next_to_use;
5134         while (count--) {
5135                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5136                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5137                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5138                 tx_desc->read.cmd_type_len =
5139                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5140                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5141                 i++;
5142                 if (i == tx_ring->count)
5143                         i = 0;
5144         }
5145
5146         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5147
5148         /*
5149          * Force memory writes to complete before letting h/w
5150          * know there are new descriptors to fetch.  (Only
5151          * applicable for weak-ordered memory model archs,
5152          * such as IA-64).
5153          */
5154         wmb();
5155
5156         tx_ring->next_to_use = i;
5157         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5158 }
5159
5160 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5161                       int queue, u32 tx_flags)
5162 {
5163         /* Right now, we support IPv4 only */
5164         struct ixgbe_atr_input atr_input;
5165         struct tcphdr *th;
5166         struct iphdr *iph = ip_hdr(skb);
5167         struct ethhdr *eth = (struct ethhdr *)skb->data;
5168         u16 vlan_id, src_port, dst_port, flex_bytes;
5169         u32 src_ipv4_addr, dst_ipv4_addr;
5170         u8 l4type = 0;
5171
5172         /* check if we're UDP or TCP */
5173         if (iph->protocol == IPPROTO_TCP) {
5174                 th = tcp_hdr(skb);
5175                 src_port = th->source;
5176                 dst_port = th->dest;
5177                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5178                 /* l4type IPv4 type is 0, no need to assign */
5179         } else {
5180                 /* Unsupported L4 header, just bail here */
5181                 return;
5182         }
5183
5184         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5185
5186         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5187                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5188         src_ipv4_addr = iph->saddr;
5189         dst_ipv4_addr = iph->daddr;
5190         flex_bytes = eth->h_proto;
5191
5192         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5193         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5194         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5195         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5196         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5197         /* src and dst are inverted, think how the receiver sees them */
5198         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5199         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5200
5201         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5202         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5203 }
5204
5205 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5206                                  struct ixgbe_ring *tx_ring, int size)
5207 {
5208         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5209
5210         netif_stop_subqueue(netdev, tx_ring->queue_index);
5211         /* Herbert's original patch had:
5212          *  smp_mb__after_netif_stop_queue();
5213          * but since that doesn't exist yet, just open code it. */
5214         smp_mb();
5215
5216         /* We need to check again in a case another CPU has just
5217          * made room available. */
5218         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5219                 return -EBUSY;
5220
5221         /* A reprieve! - use start_queue because it doesn't call schedule */
5222         netif_start_subqueue(netdev, tx_ring->queue_index);
5223         ++adapter->restart_queue;
5224         return 0;
5225 }
5226
5227 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5228                               struct ixgbe_ring *tx_ring, int size)
5229 {
5230         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5231                 return 0;
5232         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5233 }
5234
5235 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5236 {
5237         struct ixgbe_adapter *adapter = netdev_priv(dev);
5238
5239         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5240                 return smp_processor_id();
5241
5242         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5243                 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5244
5245         return skb_tx_hash(dev, skb);
5246 }
5247
5248 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5249                                     struct net_device *netdev)
5250 {
5251         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5252         struct ixgbe_ring *tx_ring;
5253         unsigned int first;
5254         unsigned int tx_flags = 0;
5255         u8 hdr_len = 0;
5256         int r_idx = 0, tso;
5257         int count = 0;
5258         unsigned int f;
5259
5260         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5261                 tx_flags |= vlan_tx_tag_get(skb);
5262                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5263                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5264                         tx_flags |= (skb->queue_mapping << 13);
5265                 }
5266                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5267                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5268         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5269                 if (skb->priority != TC_PRIO_CONTROL) {
5270                         tx_flags |= (skb->queue_mapping << 13);
5271                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5272                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5273                 } else {
5274                         skb->queue_mapping =
5275                                 adapter->ring_feature[RING_F_DCB].indices-1;
5276                 }
5277         }
5278
5279         r_idx = skb->queue_mapping;
5280         tx_ring = &adapter->tx_ring[r_idx];
5281
5282         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5283             (skb->protocol == htons(ETH_P_FCOE))) {
5284                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5285 #ifdef IXGBE_FCOE
5286                 r_idx = smp_processor_id();
5287                 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5288                 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5289                 tx_ring = &adapter->tx_ring[r_idx];
5290 #endif
5291         }
5292         /* four things can cause us to need a context descriptor */
5293         if (skb_is_gso(skb) ||
5294             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5295             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5296             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5297                 count++;
5298
5299         count += TXD_USE_COUNT(skb_headlen(skb));
5300         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5301                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5302
5303         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5304                 adapter->tx_busy++;
5305                 return NETDEV_TX_BUSY;
5306         }
5307
5308         first = tx_ring->next_to_use;
5309         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5310 #ifdef IXGBE_FCOE
5311                 /* setup tx offload for FCoE */
5312                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5313                 if (tso < 0) {
5314                         dev_kfree_skb_any(skb);
5315                         return NETDEV_TX_OK;
5316                 }
5317                 if (tso)
5318                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5319 #endif /* IXGBE_FCOE */
5320         } else {
5321                 if (skb->protocol == htons(ETH_P_IP))
5322                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5323                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5324                 if (tso < 0) {
5325                         dev_kfree_skb_any(skb);
5326                         return NETDEV_TX_OK;
5327                 }
5328
5329                 if (tso)
5330                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5331                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5332                          (skb->ip_summed == CHECKSUM_PARTIAL))
5333                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5334         }
5335
5336         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5337         if (count) {
5338                 /* add the ATR filter if ATR is on */
5339                 if (tx_ring->atr_sample_rate) {
5340                         ++tx_ring->atr_count;
5341                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5342                              test_bit(__IXGBE_FDIR_INIT_DONE,
5343                                       &tx_ring->reinit_state)) {
5344                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5345                                           tx_flags);
5346                                 tx_ring->atr_count = 0;
5347                         }
5348                 }
5349                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5350                                hdr_len);
5351                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5352
5353         } else {
5354                 dev_kfree_skb_any(skb);
5355                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5356                 tx_ring->next_to_use = first;
5357         }
5358
5359         return NETDEV_TX_OK;
5360 }
5361
5362 /**
5363  * ixgbe_get_stats - Get System Network Statistics
5364  * @netdev: network interface device structure
5365  *
5366  * Returns the address of the device statistics structure.
5367  * The statistics are actually updated from the timer callback.
5368  **/
5369 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5370 {
5371         /* only return the current stats */
5372         return &netdev->stats;
5373 }
5374
5375 /**
5376  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5377  * @netdev: network interface device structure
5378  * @p: pointer to an address structure
5379  *
5380  * Returns 0 on success, negative on failure
5381  **/
5382 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5383 {
5384         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5385         struct ixgbe_hw *hw = &adapter->hw;
5386         struct sockaddr *addr = p;
5387
5388         if (!is_valid_ether_addr(addr->sa_data))
5389                 return -EADDRNOTAVAIL;
5390
5391         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5392         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5393
5394         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5395
5396         return 0;
5397 }
5398
5399 static int
5400 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5401 {
5402         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5403         struct ixgbe_hw *hw = &adapter->hw;
5404         u16 value;
5405         int rc;
5406
5407         if (prtad != hw->phy.mdio.prtad)
5408                 return -EINVAL;
5409         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5410         if (!rc)
5411                 rc = value;
5412         return rc;
5413 }
5414
5415 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5416                             u16 addr, u16 value)
5417 {
5418         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5419         struct ixgbe_hw *hw = &adapter->hw;
5420
5421         if (prtad != hw->phy.mdio.prtad)
5422                 return -EINVAL;
5423         return hw->phy.ops.write_reg(hw, addr, devad, value);
5424 }
5425
5426 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5427 {
5428         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5429
5430         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5431 }
5432
5433 /**
5434  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5435  * netdev->dev_addrs
5436  * @netdev: network interface device structure
5437  *
5438  * Returns non-zero on failure
5439  **/
5440 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5441 {
5442         int err = 0;
5443         struct ixgbe_adapter *adapter = netdev_priv(dev);
5444         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5445
5446         if (is_valid_ether_addr(mac->san_addr)) {
5447                 rtnl_lock();
5448                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5449                 rtnl_unlock();
5450         }
5451         return err;
5452 }
5453
5454 /**
5455  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5456  * netdev->dev_addrs
5457  * @netdev: network interface device structure
5458  *
5459  * Returns non-zero on failure
5460  **/
5461 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5462 {
5463         int err = 0;
5464         struct ixgbe_adapter *adapter = netdev_priv(dev);
5465         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5466
5467         if (is_valid_ether_addr(mac->san_addr)) {
5468                 rtnl_lock();
5469                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5470                 rtnl_unlock();
5471         }
5472         return err;
5473 }
5474
5475 #ifdef CONFIG_NET_POLL_CONTROLLER
5476 /*
5477  * Polling 'interrupt' - used by things like netconsole to send skbs
5478  * without having to re-enable interrupts. It's not called while
5479  * the interrupt routine is executing.
5480  */
5481 static void ixgbe_netpoll(struct net_device *netdev)
5482 {
5483         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5484         int i;
5485
5486         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5487         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5488                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5489                 for (i = 0; i < num_q_vectors; i++) {
5490                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5491                         ixgbe_msix_clean_many(0, q_vector);
5492                 }
5493         } else {
5494                 ixgbe_intr(adapter->pdev->irq, netdev);
5495         }
5496         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5497 }
5498 #endif
5499
5500 static const struct net_device_ops ixgbe_netdev_ops = {
5501         .ndo_open               = ixgbe_open,
5502         .ndo_stop               = ixgbe_close,
5503         .ndo_start_xmit         = ixgbe_xmit_frame,
5504         .ndo_select_queue       = ixgbe_select_queue,
5505         .ndo_get_stats          = ixgbe_get_stats,
5506         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5507         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5508         .ndo_validate_addr      = eth_validate_addr,
5509         .ndo_set_mac_address    = ixgbe_set_mac,
5510         .ndo_change_mtu         = ixgbe_change_mtu,
5511         .ndo_tx_timeout         = ixgbe_tx_timeout,
5512         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5513         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5514         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5515         .ndo_do_ioctl           = ixgbe_ioctl,
5516 #ifdef CONFIG_NET_POLL_CONTROLLER
5517         .ndo_poll_controller    = ixgbe_netpoll,
5518 #endif
5519 #ifdef IXGBE_FCOE
5520         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5521         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5522         .ndo_fcoe_enable = ixgbe_fcoe_enable,
5523         .ndo_fcoe_disable = ixgbe_fcoe_disable,
5524         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
5525 #endif /* IXGBE_FCOE */
5526 };
5527
5528 /**
5529  * ixgbe_probe - Device Initialization Routine
5530  * @pdev: PCI device information struct
5531  * @ent: entry in ixgbe_pci_tbl
5532  *
5533  * Returns 0 on success, negative on failure
5534  *
5535  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5536  * The OS initialization, configuring of the adapter private structure,
5537  * and a hardware reset occur.
5538  **/
5539 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5540                                  const struct pci_device_id *ent)
5541 {
5542         struct net_device *netdev;
5543         struct ixgbe_adapter *adapter = NULL;
5544         struct ixgbe_hw *hw;
5545         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5546         static int cards_found;
5547         int i, err, pci_using_dac;
5548 #ifdef IXGBE_FCOE
5549         u16 device_caps;
5550 #endif
5551         u32 part_num, eec;
5552
5553         err = pci_enable_device_mem(pdev);
5554         if (err)
5555                 return err;
5556
5557         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5558             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5559                 pci_using_dac = 1;
5560         } else {
5561                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5562                 if (err) {
5563                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5564                         if (err) {
5565                                 dev_err(&pdev->dev, "No usable DMA "
5566                                         "configuration, aborting\n");
5567                                 goto err_dma;
5568                         }
5569                 }
5570                 pci_using_dac = 0;
5571         }
5572
5573         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5574                                            IORESOURCE_MEM), ixgbe_driver_name);
5575         if (err) {
5576                 dev_err(&pdev->dev,
5577                         "pci_request_selected_regions failed 0x%x\n", err);
5578                 goto err_pci_reg;
5579         }
5580
5581         pci_enable_pcie_error_reporting(pdev);
5582
5583         pci_set_master(pdev);
5584         pci_save_state(pdev);
5585
5586         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5587         if (!netdev) {
5588                 err = -ENOMEM;
5589                 goto err_alloc_etherdev;
5590         }
5591
5592         SET_NETDEV_DEV(netdev, &pdev->dev);
5593
5594         pci_set_drvdata(pdev, netdev);
5595         adapter = netdev_priv(netdev);
5596
5597         adapter->netdev = netdev;
5598         adapter->pdev = pdev;
5599         hw = &adapter->hw;
5600         hw->back = adapter;
5601         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5602
5603         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5604                               pci_resource_len(pdev, 0));
5605         if (!hw->hw_addr) {
5606                 err = -EIO;
5607                 goto err_ioremap;
5608         }
5609
5610         for (i = 1; i <= 5; i++) {
5611                 if (pci_resource_len(pdev, i) == 0)
5612                         continue;
5613         }
5614
5615         netdev->netdev_ops = &ixgbe_netdev_ops;
5616         ixgbe_set_ethtool_ops(netdev);
5617         netdev->watchdog_timeo = 5 * HZ;
5618         strcpy(netdev->name, pci_name(pdev));
5619
5620         adapter->bd_number = cards_found;
5621
5622         /* Setup hw api */
5623         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5624         hw->mac.type  = ii->mac;
5625
5626         /* EEPROM */
5627         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5628         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5629         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5630         if (!(eec & (1 << 8)))
5631                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5632
5633         /* PHY */
5634         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5635         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5636         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5637         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5638         hw->phy.mdio.mmds = 0;
5639         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5640         hw->phy.mdio.dev = netdev;
5641         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5642         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5643
5644         /* set up this timer and work struct before calling get_invariants
5645          * which might start the timer
5646          */
5647         init_timer(&adapter->sfp_timer);
5648         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5649         adapter->sfp_timer.data = (unsigned long) adapter;
5650
5651         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5652
5653         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5654         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5655
5656         /* a new SFP+ module arrival, called from GPI SDP2 context */
5657         INIT_WORK(&adapter->sfp_config_module_task,
5658                   ixgbe_sfp_config_module_task);
5659
5660         ii->get_invariants(hw);
5661
5662         /* setup the private structure */
5663         err = ixgbe_sw_init(adapter);
5664         if (err)
5665                 goto err_sw_init;
5666
5667         /*
5668          * If there is a fan on this device and it has failed log the
5669          * failure.
5670          */
5671         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5672                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5673                 if (esdp & IXGBE_ESDP_SDP1)
5674                         DPRINTK(PROBE, CRIT,
5675                                 "Fan has stopped, replace the adapter\n");
5676         }
5677
5678         /* reset_hw fills in the perm_addr as well */
5679         err = hw->mac.ops.reset_hw(hw);
5680         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5681             hw->mac.type == ixgbe_mac_82598EB) {
5682                 /*
5683                  * Start a kernel thread to watch for a module to arrive.
5684                  * Only do this for 82598, since 82599 will generate
5685                  * interrupts on module arrival.
5686                  */
5687                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5688                 mod_timer(&adapter->sfp_timer,
5689                           round_jiffies(jiffies + (2 * HZ)));
5690                 err = 0;
5691         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5692                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5693                         "an unsupported SFP+ module type was detected.\n"
5694                         "Reload the driver after installing a supported "
5695                         "module.\n");
5696                 goto err_sw_init;
5697         } else if (err) {
5698                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5699                 goto err_sw_init;
5700         }
5701
5702         netdev->features = NETIF_F_SG |
5703                            NETIF_F_IP_CSUM |
5704                            NETIF_F_HW_VLAN_TX |
5705                            NETIF_F_HW_VLAN_RX |
5706                            NETIF_F_HW_VLAN_FILTER;
5707
5708         netdev->features |= NETIF_F_IPV6_CSUM;
5709         netdev->features |= NETIF_F_TSO;
5710         netdev->features |= NETIF_F_TSO6;
5711         netdev->features |= NETIF_F_GRO;
5712
5713         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5714                 netdev->features |= NETIF_F_SCTP_CSUM;
5715
5716         netdev->vlan_features |= NETIF_F_TSO;
5717         netdev->vlan_features |= NETIF_F_TSO6;
5718         netdev->vlan_features |= NETIF_F_IP_CSUM;
5719         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5720         netdev->vlan_features |= NETIF_F_SG;
5721
5722         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5723                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5724
5725 #ifdef CONFIG_IXGBE_DCB
5726         netdev->dcbnl_ops = &dcbnl_ops;
5727 #endif
5728
5729 #ifdef IXGBE_FCOE
5730         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5731                 if (hw->mac.ops.get_device_caps) {
5732                         hw->mac.ops.get_device_caps(hw, &device_caps);
5733                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5734                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5735                 }
5736         }
5737 #endif /* IXGBE_FCOE */
5738         if (pci_using_dac)
5739                 netdev->features |= NETIF_F_HIGHDMA;
5740
5741         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5742                 netdev->features |= NETIF_F_LRO;
5743
5744         /* make sure the EEPROM is good */
5745         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5746                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5747                 err = -EIO;
5748                 goto err_eeprom;
5749         }
5750
5751         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5752         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5753
5754         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5755                 dev_err(&pdev->dev, "invalid MAC address\n");
5756                 err = -EIO;
5757                 goto err_eeprom;
5758         }
5759
5760         init_timer(&adapter->watchdog_timer);
5761         adapter->watchdog_timer.function = &ixgbe_watchdog;
5762         adapter->watchdog_timer.data = (unsigned long)adapter;
5763
5764         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5765         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5766
5767         err = ixgbe_init_interrupt_scheme(adapter);
5768         if (err)
5769                 goto err_sw_init;
5770
5771         switch (pdev->device) {
5772         case IXGBE_DEV_ID_82599_KX4:
5773                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5774                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5775                 /* Enable ACPI wakeup in GRC */
5776                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5777                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5778                 break;
5779         default:
5780                 adapter->wol = 0;
5781                 break;
5782         }
5783         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5784
5785         /* pick up the PCI bus settings for reporting later */
5786         hw->mac.ops.get_bus_info(hw);
5787
5788         /* print bus type/speed/width info */
5789         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5790                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5791                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5792                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5793                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5794                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5795                  "Unknown"),
5796                 netdev->dev_addr);
5797         ixgbe_read_pba_num_generic(hw, &part_num);
5798         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5799                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5800                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5801                          (part_num >> 8), (part_num & 0xff));
5802         else
5803                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5804                          hw->mac.type, hw->phy.type,
5805                          (part_num >> 8), (part_num & 0xff));
5806
5807         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5808                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5809                          "this card is not sufficient for optimal "
5810                          "performance.\n");
5811                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5812                          "PCI-Express slot is required.\n");
5813         }
5814
5815         /* save off EEPROM version number */
5816         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5817
5818         /* reset the hardware with the new settings */
5819         err = hw->mac.ops.start_hw(hw);
5820
5821         if (err == IXGBE_ERR_EEPROM_VERSION) {
5822                 /* We are running on a pre-production device, log a warning */
5823                 dev_warn(&pdev->dev, "This device is a pre-production "
5824                          "adapter/LOM.  Please be aware there may be issues "
5825                          "associated with your hardware.  If you are "
5826                          "experiencing problems please contact your Intel or "
5827                          "hardware representative who provided you with this "
5828                          "hardware.\n");
5829         }
5830         strcpy(netdev->name, "eth%d");
5831         err = register_netdev(netdev);
5832         if (err)
5833                 goto err_register;
5834
5835         /* carrier off reporting is important to ethtool even BEFORE open */
5836         netif_carrier_off(netdev);
5837
5838         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5839             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5840                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5841
5842 #ifdef CONFIG_IXGBE_DCA
5843         if (dca_add_requester(&pdev->dev) == 0) {
5844                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5845                 ixgbe_setup_dca(adapter);
5846         }
5847 #endif
5848         /* add san mac addr to netdev */
5849         ixgbe_add_sanmac_netdev(netdev);
5850
5851         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5852         cards_found++;
5853         return 0;
5854
5855 err_register:
5856         ixgbe_release_hw_control(adapter);
5857         ixgbe_clear_interrupt_scheme(adapter);
5858 err_sw_init:
5859 err_eeprom:
5860         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5861         del_timer_sync(&adapter->sfp_timer);
5862         cancel_work_sync(&adapter->sfp_task);
5863         cancel_work_sync(&adapter->multispeed_fiber_task);
5864         cancel_work_sync(&adapter->sfp_config_module_task);
5865         iounmap(hw->hw_addr);
5866 err_ioremap:
5867         free_netdev(netdev);
5868 err_alloc_etherdev:
5869         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5870                                      IORESOURCE_MEM));
5871 err_pci_reg:
5872 err_dma:
5873         pci_disable_device(pdev);
5874         return err;
5875 }
5876
5877 /**
5878  * ixgbe_remove - Device Removal Routine
5879  * @pdev: PCI device information struct
5880  *
5881  * ixgbe_remove is called by the PCI subsystem to alert the driver
5882  * that it should release a PCI device.  The could be caused by a
5883  * Hot-Plug event, or because the driver is going to be removed from
5884  * memory.
5885  **/
5886 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5887 {
5888         struct net_device *netdev = pci_get_drvdata(pdev);
5889         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5890
5891         set_bit(__IXGBE_DOWN, &adapter->state);
5892         /* clear the module not found bit to make sure the worker won't
5893          * reschedule
5894          */
5895         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5896         del_timer_sync(&adapter->watchdog_timer);
5897
5898         del_timer_sync(&adapter->sfp_timer);
5899         cancel_work_sync(&adapter->watchdog_task);
5900         cancel_work_sync(&adapter->sfp_task);
5901         cancel_work_sync(&adapter->multispeed_fiber_task);
5902         cancel_work_sync(&adapter->sfp_config_module_task);
5903         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5904             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5905                 cancel_work_sync(&adapter->fdir_reinit_task);
5906         flush_scheduled_work();
5907
5908 #ifdef CONFIG_IXGBE_DCA
5909         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5910                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5911                 dca_remove_requester(&pdev->dev);
5912                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5913         }
5914
5915 #endif
5916 #ifdef IXGBE_FCOE
5917         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5918                 ixgbe_cleanup_fcoe(adapter);
5919
5920 #endif /* IXGBE_FCOE */
5921
5922         /* remove the added san mac */
5923         ixgbe_del_sanmac_netdev(netdev);
5924
5925         if (netdev->reg_state == NETREG_REGISTERED)
5926                 unregister_netdev(netdev);
5927
5928         ixgbe_clear_interrupt_scheme(adapter);
5929
5930         ixgbe_release_hw_control(adapter);
5931
5932         iounmap(adapter->hw.hw_addr);
5933         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5934                                      IORESOURCE_MEM));
5935
5936         DPRINTK(PROBE, INFO, "complete\n");
5937
5938         free_netdev(netdev);
5939
5940         pci_disable_pcie_error_reporting(pdev);
5941
5942         pci_disable_device(pdev);
5943 }
5944
5945 /**
5946  * ixgbe_io_error_detected - called when PCI error is detected
5947  * @pdev: Pointer to PCI device
5948  * @state: The current pci connection state
5949  *
5950  * This function is called after a PCI bus error affecting
5951  * this device has been detected.
5952  */
5953 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5954                                                 pci_channel_state_t state)
5955 {
5956         struct net_device *netdev = pci_get_drvdata(pdev);
5957         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5958
5959         netif_device_detach(netdev);
5960
5961         if (state == pci_channel_io_perm_failure)
5962                 return PCI_ERS_RESULT_DISCONNECT;
5963
5964         if (netif_running(netdev))
5965                 ixgbe_down(adapter);
5966         pci_disable_device(pdev);
5967
5968         /* Request a slot reset. */
5969         return PCI_ERS_RESULT_NEED_RESET;
5970 }
5971
5972 /**
5973  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5974  * @pdev: Pointer to PCI device
5975  *
5976  * Restart the card from scratch, as if from a cold-boot.
5977  */
5978 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5979 {
5980         struct net_device *netdev = pci_get_drvdata(pdev);
5981         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5982         pci_ers_result_t result;
5983         int err;
5984
5985         if (pci_enable_device_mem(pdev)) {
5986                 DPRINTK(PROBE, ERR,
5987                         "Cannot re-enable PCI device after reset.\n");
5988                 result = PCI_ERS_RESULT_DISCONNECT;
5989         } else {
5990                 pci_set_master(pdev);
5991                 pci_restore_state(pdev);
5992
5993                 pci_wake_from_d3(pdev, false);
5994
5995                 ixgbe_reset(adapter);
5996                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5997                 result = PCI_ERS_RESULT_RECOVERED;
5998         }
5999
6000         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6001         if (err) {
6002                 dev_err(&pdev->dev,
6003                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6004                 /* non-fatal, continue */
6005         }
6006
6007         return result;
6008 }
6009
6010 /**
6011  * ixgbe_io_resume - called when traffic can start flowing again.
6012  * @pdev: Pointer to PCI device
6013  *
6014  * This callback is called when the error recovery driver tells us that
6015  * its OK to resume normal operation.
6016  */
6017 static void ixgbe_io_resume(struct pci_dev *pdev)
6018 {
6019         struct net_device *netdev = pci_get_drvdata(pdev);
6020         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6021
6022         if (netif_running(netdev)) {
6023                 if (ixgbe_up(adapter)) {
6024                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6025                         return;
6026                 }
6027         }
6028
6029         netif_device_attach(netdev);
6030 }
6031
6032 static struct pci_error_handlers ixgbe_err_handler = {
6033         .error_detected = ixgbe_io_error_detected,
6034         .slot_reset = ixgbe_io_slot_reset,
6035         .resume = ixgbe_io_resume,
6036 };
6037
6038 static struct pci_driver ixgbe_driver = {
6039         .name     = ixgbe_driver_name,
6040         .id_table = ixgbe_pci_tbl,
6041         .probe    = ixgbe_probe,
6042         .remove   = __devexit_p(ixgbe_remove),
6043 #ifdef CONFIG_PM
6044         .suspend  = ixgbe_suspend,
6045         .resume   = ixgbe_resume,
6046 #endif
6047         .shutdown = ixgbe_shutdown,
6048         .err_handler = &ixgbe_err_handler
6049 };
6050
6051 /**
6052  * ixgbe_init_module - Driver Registration Routine
6053  *
6054  * ixgbe_init_module is the first routine called when the driver is
6055  * loaded. All it does is register with the PCI subsystem.
6056  **/
6057 static int __init ixgbe_init_module(void)
6058 {
6059         int ret;
6060         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6061                ixgbe_driver_string, ixgbe_driver_version);
6062
6063         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6064
6065 #ifdef CONFIG_IXGBE_DCA
6066         dca_register_notify(&dca_notifier);
6067 #endif
6068
6069         ret = pci_register_driver(&ixgbe_driver);
6070         return ret;
6071 }
6072
6073 module_init(ixgbe_init_module);
6074
6075 /**
6076  * ixgbe_exit_module - Driver Exit Cleanup Routine
6077  *
6078  * ixgbe_exit_module is called just before the driver is removed
6079  * from memory.
6080  **/
6081 static void __exit ixgbe_exit_module(void)
6082 {
6083 #ifdef CONFIG_IXGBE_DCA
6084         dca_unregister_notify(&dca_notifier);
6085 #endif
6086         pci_unregister_driver(&ixgbe_driver);
6087 }
6088
6089 #ifdef CONFIG_IXGBE_DCA
6090 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6091                             void *p)
6092 {
6093         int ret_val;
6094
6095         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6096                                          __ixgbe_notify_dca);
6097
6098         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6099 }
6100
6101 #endif /* CONFIG_IXGBE_DCA */
6102 #ifdef DEBUG
6103 /**
6104  * ixgbe_get_hw_dev_name - return device name string
6105  * used by hardware layer to print debugging information
6106  **/
6107 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6108 {
6109         struct ixgbe_adapter *adapter = hw->back;
6110         return adapter->netdev->name;
6111 }
6112
6113 #endif
6114 module_exit(ixgbe_exit_module);
6115
6116 /* ixgbe_main.c */