1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 #include "ixgbe_type.h"
31 #include "ixgbe_dcb.h"
32 #include "ixgbe_dcb_82598.h"
35 * ixgbe_dcb_config_packet_buffers_82598 - Configure packet buffers
36 * @hw: pointer to hardware structure
37 * @dcb_config: pointer to ixgbe_dcb_config structure
39 * Configure packet buffers for DCB mode.
41 static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw, u8 rx_pba)
44 u32 value = IXGBE_RXPBSIZE_64KB;
47 /* Setup Rx packet buffer sizes */
50 /* Setup the first four at 80KB */
51 value = IXGBE_RXPBSIZE_80KB;
53 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
54 /* Setup the last four at 48KB...don't re-init i */
55 value = IXGBE_RXPBSIZE_48KB;
59 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
60 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
62 /* Setup Tx packet buffer sizes */
63 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
64 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i),
74 * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
75 * @hw: pointer to hardware structure
76 * @dcb_config: pointer to ixgbe_dcb_config structure
78 * Configure Rx Data Arbiter and credits for each traffic class.
80 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
86 u32 credit_refill = 0;
90 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
91 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
93 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
95 reg &= ~IXGBE_RMCS_ARBDIS;
96 /* Enable Receive Recycle within the BWG */
97 reg |= IXGBE_RMCS_RRM;
98 /* Enable Deficit Fixed Priority arbitration*/
99 reg |= IXGBE_RMCS_DFP;
101 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
103 /* Configure traffic class credits and priority */
104 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
105 credit_refill = refill[i];
108 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
110 if (prio_type[i] == prio_link)
111 reg |= IXGBE_RT2CR_LSP;
113 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
116 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
117 reg |= IXGBE_RDRXCTL_RDMTS_1_2;
118 reg |= IXGBE_RDRXCTL_MPBEN;
119 reg |= IXGBE_RDRXCTL_MCEN;
120 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
122 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
123 /* Make sure there is enough descriptors before arbitration */
124 reg &= ~IXGBE_RXCTRL_DMBYPS;
125 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
131 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
132 * @hw: pointer to hardware structure
133 * @dcb_config: pointer to ixgbe_dcb_config structure
135 * Configure Tx Descriptor Arbiter and credits for each traffic class.
137 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
143 u32 reg, max_credits;
146 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
149 reg &= ~IXGBE_DPMCS_ARBDIS;
150 /* Enable DFP and Recycle mode */
151 reg |= (IXGBE_DPMCS_TDPAC | IXGBE_DPMCS_TRM);
152 reg |= IXGBE_DPMCS_TSOEF;
153 /* Configure Max TSO packet size 34KB including payload and headers */
154 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
156 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
158 /* Configure traffic class credits and priority */
159 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
160 max_credits = max[i];
161 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
163 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
165 if (prio_type[i] == prio_group)
166 reg |= IXGBE_TDTQ2TCCR_GSP;
168 if (prio_type[i] == prio_link)
169 reg |= IXGBE_TDTQ2TCCR_LSP;
171 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
178 * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
179 * @hw: pointer to hardware structure
180 * @dcb_config: pointer to ixgbe_dcb_config structure
182 * Configure Tx Data Arbiter and credits for each traffic class.
184 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
193 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
194 /* Enable Data Plane Arbiter */
195 reg &= ~IXGBE_PDPMCS_ARBDIS;
196 /* Enable DFP and Transmit Recycle Mode */
197 reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
199 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
201 /* Configure traffic class credits and priority */
202 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
204 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
205 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
207 if (prio_type[i] == prio_group)
208 reg |= IXGBE_TDPT2TCCR_GSP;
210 if (prio_type[i] == prio_link)
211 reg |= IXGBE_TDPT2TCCR_LSP;
213 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
216 /* Enable Tx packet buffer division */
217 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
218 reg |= IXGBE_DTXCTL_ENDBUBD;
219 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
225 * ixgbe_dcb_config_pfc_82598 - Config priority flow control
226 * @hw: pointer to hardware structure
227 * @dcb_config: pointer to ixgbe_dcb_config structure
229 * Configure Priority Flow Control for each traffic class.
231 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
233 u32 reg, rx_pba_size;
239 /* Enable Transmit Priority Flow Control */
240 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
241 reg &= ~IXGBE_RMCS_TFCE_802_3X;
242 /* correct the reporting of our flow control status */
243 reg |= IXGBE_RMCS_TFCE_PRIORITY;
244 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
246 /* Enable Receive Priority Flow Control */
247 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
248 reg &= ~IXGBE_FCTRL_RFCE;
249 reg |= IXGBE_FCTRL_RPFCE;
250 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
253 * Configure flow control thresholds and enable priority flow control
254 * for each traffic class.
256 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
257 int enabled = pfc_en & (1 << i);
258 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
259 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
260 reg = (rx_pba_size - hw->fc.low_water) << 10;
262 if (enabled == pfc_enabled_tx ||
263 enabled == pfc_enabled_full)
264 reg |= IXGBE_FCRTL_XONE;
266 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), reg);
268 reg = (rx_pba_size - hw->fc.high_water) << 10;
269 if (enabled == pfc_enabled_tx ||
270 enabled == pfc_enabled_full)
271 reg |= IXGBE_FCRTH_FCEN;
273 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
276 /* Configure pause time */
277 for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++)
278 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800);
280 /* Configure flow control refresh threshold value */
281 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);
288 * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
289 * @hw: pointer to hardware structure
291 * Configure queue statistics registers, all queues belonging to same traffic
292 * class uses a single set of queue statistics counters.
294 s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
300 /* Receive Queues stats setting - 8 queues per statistics reg */
301 for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
302 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
303 reg |= ((0x1010101) * j);
304 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
305 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
306 reg |= ((0x1010101) * j);
307 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
309 /* Transmit Queues stats setting - 4 queues per statistics reg */
310 for (i = 0; i < 8; i++) {
311 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
312 reg |= ((0x1010101) * i);
313 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
320 * ixgbe_dcb_hw_config_82598 - Config and enable DCB
321 * @hw: pointer to hardware structure
322 * @dcb_config: pointer to ixgbe_dcb_config structure
324 * Configure dcb settings and enable dcb mode.
326 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
327 u8 rx_pba, u8 pfc_en, u16 *refill,
328 u16 *max, u8 *bwg_id, u8 *prio_type)
330 ixgbe_dcb_config_packet_buffers_82598(hw, rx_pba);
331 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type);
332 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
334 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
336 ixgbe_dcb_config_pfc_82598(hw, pfc_en);
337 ixgbe_dcb_config_tc_stats_82598(hw);