Pileus Git - ~andy/linux/blob - drivers/net/ixgbe/ixgbe_82599.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe.h"
  33 #include "ixgbe_phy.h"
  34
  35 #define IXGBE_82599_MAX_TX_QUEUES 128
  36 #define IXGBE_82599_MAX_RX_QUEUES 128
  37 #define IXGBE_82599_RAR_ENTRIES   128
  38 #define IXGBE_82599_MC_TBL_SIZE   128
  39 #define IXGBE_82599_VFT_TBL_SIZE  128
  40
  41 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
  42                                       ixgbe_link_speed *speed,
  43                                       bool *autoneg);
  44 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
  45 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
  46 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
  47                                      ixgbe_link_speed speed, bool autoneg,
  48                                      bool autoneg_wait_to_complete);
  49 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
  50 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
  51                                ixgbe_link_speed *speed,
  52                                bool *link_up, bool link_up_wait_to_complete);
  53 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
  54                                      ixgbe_link_speed speed,
  55                                      bool autoneg,
  56                                      bool autoneg_wait_to_complete);
  57 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
  58                                              ixgbe_link_speed *speed,
  59                                              bool *autoneg);
  60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
  61 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
  62                                                ixgbe_link_speed speed,
  63                                                bool autoneg,
  64                                                bool autoneg_wait_to_complete);
  65 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
  66 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
  67 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
  68 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
  69                          u32 vind, bool vlan_on);
  70 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
  71 s32 ixgbe_blink_led_stop_82599(struct ixgbe_hw *hw, u32 index);
  72 s32 ixgbe_blink_led_start_82599(struct ixgbe_hw *hw, u32 index);
  73 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
  74 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
  75 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
  76 s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
  77 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
  78 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
  79 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
  80
  81 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
  82 {
  83         struct ixgbe_mac_info *mac = &hw->mac;
  84         if (hw->phy.multispeed_fiber) {
  85                 /* Set up dual speed SFP+ support */
  86                 mac->ops.setup_link =
  87                           &ixgbe_setup_mac_link_multispeed_fiber;
  88                 mac->ops.setup_link_speed =
  89                           &ixgbe_setup_mac_link_speed_multispeed_fiber;
  90         } else {
  91                 mac->ops.setup_link =
  92                           &ixgbe_setup_mac_link_82599;
  93                 mac->ops.setup_link_speed =
  94                           &ixgbe_setup_mac_link_speed_82599;
  95         }
  96 }
  97
  98 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
  99 {
 100         s32 ret_val = 0;
 101         u16 list_offset, data_offset, data_value;
 102
 103         if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
 104                 ixgbe_init_mac_link_ops_82599(hw);
 105                 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 106                                                               &data_offset);
 107
 108                 if (ret_val != 0)
 109                         goto setup_sfp_out;
 110
 111                 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
 112                 while (data_value != 0xffff) {
 113                         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
 114                         IXGBE_WRITE_FLUSH(hw);
 115                         hw->eeprom.ops.read(hw, ++data_offset, &data_value);
 116                 }
 117                 /* Now restart DSP */
 118                 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000102);
 119                 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000b1d);
 120                 IXGBE_WRITE_FLUSH(hw);
 121         }
 122
 123 setup_sfp_out:
 124         return ret_val;
 125 }
 126
 127 /**
 128  *  ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
 129  *  @hw: pointer to hardware structure
 130  *
 131  *  Read PCIe configuration space, and get the MSI-X vector count from
 132  *  the capabilities table.
 133  **/
 134 u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
 135 {
 136         struct ixgbe_adapter *adapter = hw->back;
 137         u16 msix_count;
 138         pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
 139                              &msix_count);
 140         msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
 141
 142         /* MSI-X count is zero-based in HW, so increment to give proper value */
 143         msix_count++;
 144
 145         return msix_count;
 146 }
 147
 148 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
 149 {
 150         struct ixgbe_mac_info *mac = &hw->mac;
 151
 152         ixgbe_init_mac_link_ops_82599(hw);
 153
 154         mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
 155         mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
 156         mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
 157         mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
 158         mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
 159         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
 160
 161         return 0;
 162 }
 163
 164 /**
 165  *  ixgbe_init_phy_ops_82599 - PHY/SFP specific init
 166  *  @hw: pointer to hardware structure
 167  *
 168  *  Initialize any function pointers that were not able to be
 169  *  set during get_invariants because the PHY/SFP type was
 170  *  not known.  Perform the SFP init if necessary.
 171  *
 172  **/
 173 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
 174 {
 175         struct ixgbe_mac_info *mac = &hw->mac;
 176         struct ixgbe_phy_info *phy = &hw->phy;
 177         s32 ret_val = 0;
 178
 179         /* Identify the PHY or SFP module */
 180         ret_val = phy->ops.identify(hw);
 181
 182         /* Setup function pointers based on detected SFP module and speeds */
 183         ixgbe_init_mac_link_ops_82599(hw);
 184
 185         /* If copper media, overwrite with copper function pointers */
 186         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 187                 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
 188                 mac->ops.setup_link_speed =
 189                                      &ixgbe_setup_copper_link_speed_82599;
 190                 mac->ops.get_link_capabilities =
 191                                   &ixgbe_get_copper_link_capabilities_82599;
 192         }
 193
 194         /* Set necessary function pointers based on phy type */
 195         switch (hw->phy.type) {
 196         case ixgbe_phy_tn:
 197                 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
 198                 phy->ops.get_firmware_version =
 199                              &ixgbe_get_phy_firmware_version_tnx;
 200                 break;
 201         default:
 202                 break;
 203         }
 204
 205         return ret_val;
 206 }
 207
 208 /**
 209  *  ixgbe_get_link_capabilities_82599 - Determines link capabilities
 210  *  @hw: pointer to hardware structure
 211  *  @speed: pointer to link speed
 212  *  @negotiation: true when autoneg or autotry is enabled
 213  *
 214  *  Determines the link capabilities by reading the AUTOC register.
 215  **/
 216 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
 217                                       ixgbe_link_speed *speed,
 218                                       bool *negotiation)
 219 {
 220         s32 status = 0;
 221
 222         switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) {
 223         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 224                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 225                 *negotiation = false;
 226                 break;
 227
 228         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 229                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 230                 *negotiation = false;
 231                 break;
 232
 233         case IXGBE_AUTOC_LMS_1G_AN:
 234                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 235                 *negotiation = true;
 236                 break;
 237
 238         case IXGBE_AUTOC_LMS_10G_SERIAL:
 239                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 240                 *negotiation = false;
 241                 break;
 242
 243         case IXGBE_AUTOC_LMS_KX4_KX_KR:
 244         case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
 245                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
 246                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
 247                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 248                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 249                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 250                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
 251                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 252                 *negotiation = true;
 253                 break;
 254
 255         case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
 256                 *speed = IXGBE_LINK_SPEED_100_FULL;
 257                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
 258                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 259                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 260                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 261                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
 262                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 263                 *negotiation = true;
 264                 break;
 265
 266         case IXGBE_AUTOC_LMS_SGMII_1G_100M:
 267                 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
 268                 *negotiation = false;
 269                 break;
 270
 271         default:
 272                 status = IXGBE_ERR_LINK_SETUP;
 273                 goto out;
 274                 break;
 275         }
 276
 277         if (hw->phy.multispeed_fiber) {
 278                 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
 279                           IXGBE_LINK_SPEED_1GB_FULL;
 280                 *negotiation = true;
 281         }
 282
 283 out:
 284         return status;
 285 }
 286
 287 /**
 288  *  ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
 289  *  @hw: pointer to hardware structure
 290  *  @speed: pointer to link speed
 291  *  @autoneg: boolean auto-negotiation value
 292  *
 293  *  Determines the link capabilities by reading the AUTOC register.
 294  **/
 295 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
 296                                                     ixgbe_link_speed *speed,
 297                                                     bool *autoneg)
 298 {
 299         s32 status = IXGBE_ERR_LINK_SETUP;
 300         u16 speed_ability;
 301
 302         *speed = 0;
 303         *autoneg = true;
 304
 305         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 306                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 307                                       &speed_ability);
 308
 309         if (status == 0) {
 310                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 311                     *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 312                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 313                     *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 314         }
 315
 316         return status;
 317 }
 318
 319 /**
 320  *  ixgbe_get_media_type_82599 - Get media type
 321  *  @hw: pointer to hardware structure
 322  *
 323  *  Returns the media type (fiber, copper, backplane)
 324  **/
 325 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
 326 {
 327         enum ixgbe_media_type media_type;
 328
 329         /* Detect if there is a copper PHY attached. */
 330         if (hw->phy.type == ixgbe_phy_cu_unknown ||
 331             hw->phy.type == ixgbe_phy_tn) {
 332                 media_type = ixgbe_media_type_copper;
 333                 goto out;
 334         }
 335
 336         switch (hw->device_id) {
 337         case IXGBE_DEV_ID_82599:
 338         case IXGBE_DEV_ID_82599_KX4:
 339                 /* Default device ID is mezzanine card KX/KX4 */
 340                 media_type = ixgbe_media_type_backplane;
 341                 break;
 342         case IXGBE_DEV_ID_82599_SFP:
 343                 media_type = ixgbe_media_type_fiber;
 344                 break;
 345         default:
 346                 media_type = ixgbe_media_type_unknown;
 347                 break;
 348         }
 349 out:
 350         return media_type;
 351 }
 352
 353 /**
 354  *  ixgbe_setup_mac_link_82599 - Setup MAC link settings
 355  *  @hw: pointer to hardware structure
 356  *
 357  *  Configures link settings based on values in the ixgbe_hw struct.
 358  *  Restarts the link.  Performs autonegotiation if needed.
 359  **/
 360 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
 361 {
 362         u32 autoc_reg;
 363         u32 links_reg;
 364         u32 i;
 365         s32 status = 0;
 366
 367         /* Restart link */
 368         autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 369         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 370         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 371
 372         /* Only poll for autoneg to complete if specified to do so */
 373         if (hw->phy.autoneg_wait_to_complete) {
 374                 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 375                      IXGBE_AUTOC_LMS_KX4_KX_KR ||
 376                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 377                      IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 378                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 379                      IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 380                         links_reg = 0; /* Just in case Autoneg time = 0 */
 381                         for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 382                                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 383                                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 384                                         break;
 385                                 msleep(100);
 386                         }
 387                         if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 388                                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 389                                 hw_dbg(hw, "Autoneg did not complete.\n");
 390                         }
 391                 }
 392         }
 393
 394         /* Set up flow control */
 395         status = ixgbe_setup_fc_generic(hw, 0);
 396
 397         /* Add delay to filter out noises during initial link setup */
 398         msleep(50);
 399
 400         return status;
 401 }
 402
 403 /**
 404  *  ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
 405  *  @hw: pointer to hardware structure
 406  *
 407  *  Configures link settings based on values in the ixgbe_hw struct.
 408  *  Restarts the link for multi-speed fiber at 1G speed, if link
 409  *  fails at 10G.
 410  *  Performs autonegotiation if needed.
 411  **/
 412 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
 413 {
 414         s32 status = 0;
 415         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
 416         status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed,
 417                                                              true, true);
 418         return status;
 419 }
 420
 421 /**
 422  *  ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
 423  *  @hw: pointer to hardware structure
 424  *  @speed: new link speed
 425  *  @autoneg: true if autonegotiation enabled
 426  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 427  *
 428  *  Set the link speed in the AUTOC register and restarts link.
 429  **/
 430 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
 431                                                 ixgbe_link_speed speed,
 432                                                 bool autoneg,
 433                                                 bool autoneg_wait_to_complete)
 434 {
 435         s32 status = 0;
 436         ixgbe_link_speed phy_link_speed;
 437         ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
 438         u32 speedcnt = 0;
 439         u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
 440         bool link_up = false;
 441         bool negotiation;
 442
 443         /* Mask off requested but non-supported speeds */
 444         hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
 445         speed &= phy_link_speed;
 446
 447         /*
 448          * Try each speed one by one, highest priority first.  We do this in
 449          * software because 10gb fiber doesn't support speed autonegotiation.
 450          */
 451         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 452                 speedcnt++;
 453                 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
 454
 455                 /* Set hardware SDP's */
 456                 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
 457                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 458
 459                 ixgbe_setup_mac_link_speed_82599(hw,
 460                                                  IXGBE_LINK_SPEED_10GB_FULL,
 461                                                  autoneg,
 462                                                  autoneg_wait_to_complete);
 463
 464                 msleep(50);
 465
 466                 /* If we have link, just jump out */
 467                 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
 468                 if (link_up)
 469                         goto out;
 470         }
 471
 472         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 473                 speedcnt++;
 474                 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
 475                         highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
 476
 477                 /* Set hardware SDP's */
 478                 esdp_reg &= ~IXGBE_ESDP_SDP5;
 479                 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
 480                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 481
 482                 ixgbe_setup_mac_link_speed_82599(
 483                         hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
 484                         autoneg_wait_to_complete);
 485
 486                 msleep(50);
 487
 488                 /* If we have link, just jump out */
 489                 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
 490                 if (link_up)
 491                         goto out;
 492         }
 493
 494         /*
 495          * We didn't get link.  Configure back to the highest speed we tried,
 496          * (if there was more than one).  We call ourselves back with just the
 497          * single highest speed that the user requested.
 498          */
 499         if (speedcnt > 1)
 500                 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
 501                                                      highest_link_speed,
 502                                                      autoneg,
 503                                                      autoneg_wait_to_complete);
 504
 505 out:
 506         return status;
 507 }
 508
 509 /**
 510  *  ixgbe_check_mac_link_82599 - Determine link and speed status
 511  *  @hw: pointer to hardware structure
 512  *  @speed: pointer to link speed
 513  *  @link_up: true when link is up
 514  *  @link_up_wait_to_complete: bool used to wait for link up or not
 515  *
 516  *  Reads the links register to determine if link is up and the current speed
 517  **/
 518 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 519                                bool *link_up, bool link_up_wait_to_complete)
 520 {
 521         u32 links_reg;
 522         u32 i;
 523
 524         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 525         if (link_up_wait_to_complete) {
 526                 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 527                         if (links_reg & IXGBE_LINKS_UP) {
 528                                 *link_up = true;
 529                                 break;
 530                         } else {
 531                                 *link_up = false;
 532                         }
 533                         msleep(100);
 534                         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 535                 }
 536         } else {
 537                 if (links_reg & IXGBE_LINKS_UP)
 538                         *link_up = true;
 539                 else
 540                         *link_up = false;
 541         }
 542
 543         if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
 544             IXGBE_LINKS_SPEED_10G_82599)
 545                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 546         else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
 547                  IXGBE_LINKS_SPEED_1G_82599)
 548                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 549         else
 550                 *speed = IXGBE_LINK_SPEED_100_FULL;
 551
 552
 553         return 0;
 554 }
 555
 556 /**
 557  *  ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
 558  *  @hw: pointer to hardware structure
 559  *  @speed: new link speed
 560  *  @autoneg: true if autonegotiation enabled
 561  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 562  *
 563  *  Set the link speed in the AUTOC register and restarts link.
 564  **/
 565 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
 566                                      ixgbe_link_speed speed, bool autoneg,
 567                                      bool autoneg_wait_to_complete)
 568 {
 569         s32 status = 0;
 570         u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 571         u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 572         u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
 573         u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
 574         u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
 575         u32 links_reg;
 576         u32 i;
 577         ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
 578
 579         /* Check to see if speed passed in is supported. */
 580         hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
 581         speed &= link_capabilities;
 582
 583         if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
 584                 status = IXGBE_ERR_LINK_SETUP;
 585         } else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
 586                    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 587                    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 588                 /* Set KX4/KX/KR support according to speed requested */
 589                 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
 590                 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 591                         if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 592                                 autoc |= IXGBE_AUTOC_KX4_SUPP;
 593                         if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
 594                                 autoc |= IXGBE_AUTOC_KR_SUPP;
 595                 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 596                         autoc |= IXGBE_AUTOC_KX_SUPP;
 597         } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
 598                    (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
 599                     link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
 600                 /* Switch from 1G SFI to 10G SFI if requested */
 601                 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
 602                     (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
 603                         autoc &= ~IXGBE_AUTOC_LMS_MASK;
 604                         autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
 605                 }
 606         } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
 607                    (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
 608                 /* Switch from 10G SFI to 1G SFI if requested */
 609                 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
 610                     (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
 611                         autoc &= ~IXGBE_AUTOC_LMS_MASK;
 612                         if (autoneg)
 613                                 autoc |= IXGBE_AUTOC_LMS_1G_AN;
 614                         else
 615                                 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
 616                 }
 617         }
 618
 619         if (status == 0) {
 620                 /* Restart link */
 621                 autoc |= IXGBE_AUTOC_AN_RESTART;
 622                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
 623
 624                 /* Only poll for autoneg to complete if specified to do so */
 625                 if (autoneg_wait_to_complete) {
 626                         if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
 627                             link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 628                             link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 629                                 links_reg = 0; /*Just in case Autoneg time=0*/
 630                                 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 631                                         links_reg =
 632                                                IXGBE_READ_REG(hw, IXGBE_LINKS);
 633                                         if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 634                                                 break;
 635                                         msleep(100);
 636                                 }
 637                                 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 638                                         status =
 639                                                 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 640                                         hw_dbg(hw, "Autoneg did not "
 641                                                "complete.\n");
 642                                 }
 643                         }
 644                 }
 645
 646                 /* Set up flow control */
 647                 status = ixgbe_setup_fc_generic(hw, 0);
 648
 649                 /* Add delay to filter out noises during initial link setup */
 650                 msleep(50);
 651         }
 652
 653         return status;
 654 }
 655
 656 /**
 657  *  ixgbe_setup_copper_link_82599 - Setup copper link settings
 658  *  @hw: pointer to hardware structure
 659  *
 660  *  Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
 661  **/
 662 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
 663 {
 664         s32 status;
 665
 666         /* Restart autonegotiation on PHY */
 667         status = hw->phy.ops.setup_link(hw);
 668
 669         /* Set up MAC */
 670         ixgbe_setup_mac_link_82599(hw);
 671
 672         return status;
 673 }
 674
 675 /**
 676  *  ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
 677  *  @hw: pointer to hardware structure
 678  *  @speed: new link speed
 679  *  @autoneg: true if autonegotiation enabled
 680  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 681  *
 682  *  Restarts link on PHY and MAC based on settings passed in.
 683  **/
 684 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
 685                                                ixgbe_link_speed speed,
 686                                                bool autoneg,
 687                                                bool autoneg_wait_to_complete)
 688 {
 689         s32 status;
 690
 691         /* Setup the PHY according to input speed */
 692         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 693                                               autoneg_wait_to_complete);
 694         /* Set up MAC */
 695         ixgbe_setup_mac_link_82599(hw);
 696
 697         return status;
 698 }
 699
 700 /**
 701  *  ixgbe_reset_hw_82599 - Perform hardware reset
 702  *  @hw: pointer to hardware structure
 703  *
 704  *  Resets the hardware by resetting the transmit and receive units, masks
 705  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
 706  *  reset.
 707  **/
 708 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
 709 {
 710         s32 status = 0;
 711         u32 ctrl, ctrl_ext;
 712         u32 i;
 713         u32 autoc;
 714         u32 autoc2;
 715
 716         /* Call adapter stop to disable tx/rx and clear interrupts */
 717         hw->mac.ops.stop_adapter(hw);
 718
 719         /* Reset PHY */
 720         if (hw->phy.reset_disable == false) {
 721                 /* PHY ops must be identified and initialized prior to reset */
 722
 723                 /* Init PHY and function pointers, perform SFP setup */
 724                 status = hw->phy.ops.init(hw);
 725
 726                 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 727                         goto reset_hw_out;
 728
 729                 hw->phy.ops.reset(hw);
 730         }
 731
 732         /*
 733          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 734          * access and verify no pending requests before reset
 735          */
 736         status = ixgbe_disable_pcie_master(hw);
 737         if (status != 0) {
 738                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 739                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 740         }
 741
 742         /*
 743          * Issue global reset to the MAC.  This needs to be a SW reset.
 744          * If link reset is used, it might reset the MAC when mng is using it
 745          */
 746         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 747         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
 748         IXGBE_WRITE_FLUSH(hw);
 749
 750         /* Poll for reset bit to self-clear indicating reset is complete */
 751         for (i = 0; i < 10; i++) {
 752                 udelay(1);
 753                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 754                 if (!(ctrl & IXGBE_CTRL_RST))
 755                         break;
 756         }
 757         if (ctrl & IXGBE_CTRL_RST) {
 758                 status = IXGBE_ERR_RESET_FAILED;
 759                 hw_dbg(hw, "Reset polling failed to complete.\n");
 760         }
 761         /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
 762         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 763         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 764         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 765
 766         msleep(50);
 767
 768
 769
 770         /*
 771          * Store the original AUTOC/AUTOC2 values if they have not been
 772          * stored off yet.  Otherwise restore the stored original
 773          * values since the reset operation sets back to defaults.
 774          */
 775         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 776         autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 777         if (hw->mac.orig_link_settings_stored == false) {
 778                 hw->mac.orig_autoc = autoc;
 779                 hw->mac.orig_autoc2 = autoc2;
 780                 hw->mac.orig_link_settings_stored = true;
 781         } else {
 782                 if (autoc != hw->mac.orig_autoc)
 783                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
 784                                         IXGBE_AUTOC_AN_RESTART));
 785
 786                 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
 787                     (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
 788                         autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
 789                         autoc2 |= (hw->mac.orig_autoc2 &
 790                                    IXGBE_AUTOC2_UPPER_MASK);
 791                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
 792                 }
 793         }
 794
 795         /* Store the permanent mac address */
 796         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 797
 798 reset_hw_out:
 799         return status;
 800 }
 801
 802 /**
 803  *  ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
 804  *  @hw: pointer to hardware struct
 805  *  @rar: receive address register index to disassociate
 806  *  @vmdq: VMDq pool index to remove from the rar
 807  **/
 808 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 809 {
 810         u32 mpsar_lo, mpsar_hi;
 811         u32 rar_entries = hw->mac.num_rar_entries;
 812
 813         if (rar < rar_entries) {
 814                 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
 815                 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
 816
 817                 if (!mpsar_lo && !mpsar_hi)
 818                         goto done;
 819
 820                 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
 821                         if (mpsar_lo) {
 822                                 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
 823                                 mpsar_lo = 0;
 824                         }
 825                         if (mpsar_hi) {
 826                                 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
 827                                 mpsar_hi = 0;
 828                         }
 829                 } else if (vmdq < 32) {
 830                         mpsar_lo &= ~(1 << vmdq);
 831                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
 832                 } else {
 833                         mpsar_hi &= ~(1 << (vmdq - 32));
 834                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
 835                 }
 836
 837                 /* was that the last pool using this rar? */
 838                 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
 839                         hw->mac.ops.clear_rar(hw, rar);
 840         } else {
 841                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 842         }
 843
 844 done:
 845         return 0;
 846 }
 847
 848 /**
 849  *  ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
 850  *  @hw: pointer to hardware struct
 851  *  @rar: receive address register index to associate with a VMDq index
 852  *  @vmdq: VMDq pool index
 853  **/
 854 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 855 {
 856         u32 mpsar;
 857         u32 rar_entries = hw->mac.num_rar_entries;
 858
 859         if (rar < rar_entries) {
 860                 if (vmdq < 32) {
 861                         mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
 862                         mpsar |= 1 << vmdq;
 863                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
 864                 } else {
 865                         mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
 866                         mpsar |= 1 << (vmdq - 32);
 867                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
 868                 }
 869         } else {
 870                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 871         }
 872         return 0;
 873 }
 874
 875 /**
 876  *  ixgbe_set_vfta_82599 - Set VLAN filter table
 877  *  @hw: pointer to hardware structure
 878  *  @vlan: VLAN id to write to VLAN filter
 879  *  @vind: VMDq output index that maps queue to VLAN id in VFVFB
 880  *  @vlan_on: boolean flag to turn on/off VLAN in VFVF
 881  *
 882  *  Turn on/off specified VLAN in the VLAN filter table.
 883  **/
 884 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
 885                          bool vlan_on)
 886 {
 887         u32 regindex;
 888         u32 bitindex;
 889         u32 bits;
 890         u32 first_empty_slot;
 891
 892         if (vlan > 4095)
 893                 return IXGBE_ERR_PARAM;
 894
 895         /*
 896          * this is a 2 part operation - first the VFTA, then the
 897          * VLVF and VLVFB if vind is set
 898          */
 899
 900         /* Part 1
 901          * The VFTA is a bitstring made up of 128 32-bit registers
 902          * that enable the particular VLAN id, much like the MTA:
 903          *    bits[11-5]: which register
 904          *    bits[4-0]:  which bit in the register
 905          */
 906         regindex = (vlan >> 5) & 0x7F;
 907         bitindex = vlan & 0x1F;
 908         bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
 909         if (vlan_on)
 910                 bits |= (1 << bitindex);
 911         else
 912                 bits &= ~(1 << bitindex);
 913         IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
 914
 915
 916         /* Part 2
 917          * If the vind is set
 918          *   Either vlan_on
 919          *     make sure the vlan is in VLVF
 920          *     set the vind bit in the matching VLVFB
 921          *   Or !vlan_on
 922          *     clear the pool bit and possibly the vind
 923          */
 924         if (vind) {
 925                 /* find the vlanid or the first empty slot */
 926                 first_empty_slot = 0;
 927
 928                 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
 929                         bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
 930                         if (!bits && !first_empty_slot)
 931                                 first_empty_slot = regindex;
 932                         else if ((bits & 0x0FFF) == vlan)
 933                                 break;
 934                 }
 935
 936                 if (regindex >= IXGBE_VLVF_ENTRIES) {
 937                         if (first_empty_slot)
 938                                 regindex = first_empty_slot;
 939                         else {
 940                                 hw_dbg(hw, "No space in VLVF.\n");
 941                                 goto out;
 942                         }
 943                 }
 944
 945                 if (vlan_on) {
 946                         /* set the pool bit */
 947                         if (vind < 32) {
 948                                 bits = IXGBE_READ_REG(hw,
 949                                                     IXGBE_VLVFB(regindex * 2));
 950                                 bits |= (1 << vind);
 951                                 IXGBE_WRITE_REG(hw,
 952                                               IXGBE_VLVFB(regindex * 2), bits);
 953                         } else {
 954                                 bits = IXGBE_READ_REG(hw,
 955                                               IXGBE_VLVFB((regindex * 2) + 1));
 956                                 bits |= (1 << vind);
 957                                 IXGBE_WRITE_REG(hw,
 958                                         IXGBE_VLVFB((regindex * 2) + 1), bits);
 959                         }
 960                 } else {
 961                         /* clear the pool bit */
 962                         if (vind < 32) {
 963                                 bits = IXGBE_READ_REG(hw,
 964                                      IXGBE_VLVFB(regindex * 2));
 965                         bits &= ~(1 << vind);
 966                                 IXGBE_WRITE_REG(hw,
 967                                               IXGBE_VLVFB(regindex * 2), bits);
 968                                 bits |= IXGBE_READ_REG(hw,
 969                                               IXGBE_VLVFB((regindex * 2) + 1));
 970                         } else {
 971                                 bits = IXGBE_READ_REG(hw,
 972                                               IXGBE_VLVFB((regindex * 2) + 1));
 973                                 bits &= ~(1 << vind);
 974                                 IXGBE_WRITE_REG(hw,
 975                                         IXGBE_VLVFB((regindex * 2) + 1), bits);
 976                                 bits |= IXGBE_READ_REG(hw,
 977                                                     IXGBE_VLVFB(regindex * 2));
 978                         }
 979                 }
 980
 981                 if (bits)
 982                         IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
 983                                         (IXGBE_VLVF_VIEN | vlan));
 984                 else
 985                         IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
 986         }
 987
 988 out:
 989         return 0;
 990 }
 991
 992 /**
 993  *  ixgbe_clear_vfta_82599 - Clear VLAN filter table
 994  *  @hw: pointer to hardware structure
 995  *
 996  *  Clears the VLAN filer table, and the VMDq index associated with the filter
 997  **/
 998 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
 999 {
1000         u32 offset;
1001
1002         for (offset = 0; offset < hw->mac.vft_size; offset++)
1003                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1004
1005         for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1006                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1007                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1008                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1009         }
1010
1011         return 0;
1012 }
1013
1014 /**
1015  *  ixgbe_blink_led_start_82599 - Blink LED based on index.
1016  *  @hw: pointer to hardware structure
1017  *  @index: led number to blink
1018  **/
1019 s32 ixgbe_blink_led_start_82599(struct ixgbe_hw *hw, u32 index)
1020 {
1021         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1022
1023         led_reg &= ~IXGBE_LED_MODE_MASK(index);
1024         led_reg |= IXGBE_LED_BLINK(index);
1025         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1026         IXGBE_WRITE_FLUSH(hw);
1027
1028         return 0;
1029 }
1030
1031 /**
1032  *  ixgbe_blink_led_stop_82599 - Stop blinking LED based on index.
1033  *  @hw: pointer to hardware structure
1034  *  @index: led number to stop blinking
1035  **/
1036 s32 ixgbe_blink_led_stop_82599(struct ixgbe_hw *hw, u32 index)
1037 {
1038         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1039
1040         led_reg &= ~IXGBE_LED_MODE_MASK(index);
1041         led_reg &= ~IXGBE_LED_BLINK(index);
1042         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1043         IXGBE_WRITE_FLUSH(hw);
1044
1045         return 0;
1046 }
1047
1048 /**
1049  *  ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1050  *  @hw: pointer to hardware structure
1051  **/
1052 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1053 {
1054         int i;
1055         hw_dbg(hw, " Clearing UTA\n");
1056
1057         for (i = 0; i < 128; i++)
1058                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1059
1060         return 0;
1061 }
1062
1063 /**
1064  *  ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1065  *  @hw: pointer to hardware structure
1066  *  @reg: analog register to read
1067  *  @val: read value
1068  *
1069  *  Performs read operation to Omer analog register specified.
1070  **/
1071 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1072 {
1073         u32  core_ctl;
1074
1075         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1076                         (reg << 8));
1077         IXGBE_WRITE_FLUSH(hw);
1078         udelay(10);
1079         core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1080         *val = (u8)core_ctl;
1081
1082         return 0;
1083 }
1084
1085 /**
1086  *  ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1087  *  @hw: pointer to hardware structure
1088  *  @reg: atlas register to write
1089  *  @val: value to write
1090  *
1091  *  Performs write operation to Omer analog register specified.
1092  **/
1093 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1094 {
1095         u32  core_ctl;
1096
1097         core_ctl = (reg << 8) | val;
1098         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1099         IXGBE_WRITE_FLUSH(hw);
1100         udelay(10);
1101
1102         return 0;
1103 }
1104
1105 /**
1106  *  ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1107  *  @hw: pointer to hardware structure
1108  *
1109  *  Starts the hardware using the generic start_hw function.
1110  *  Then performs device-specific:
1111  *  Clears the rate limiter registers.
1112  **/
1113 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1114 {
1115         u32 q_num;
1116
1117         ixgbe_start_hw_generic(hw);
1118
1119         /* Clear the rate limiters */
1120         for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1121                 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1122                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1123         }
1124         IXGBE_WRITE_FLUSH(hw);
1125
1126         return 0;
1127 }
1128
1129 /**
1130  *  ixgbe_identify_phy_82599 - Get physical layer module
1131  *  @hw: pointer to hardware structure
1132  *
1133  *  Determines the physical layer module found on the current adapter.
1134  **/
1135 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1136 {
1137         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1138         status = ixgbe_identify_phy_generic(hw);
1139         if (status != 0)
1140                 status = ixgbe_identify_sfp_module_generic(hw);
1141         return status;
1142 }
1143
1144 /**
1145  *  ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1146  *  @hw: pointer to hardware structure
1147  *
1148  *  Determines physical layer capabilities of the current configuration.
1149  **/
1150 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1151 {
1152         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1153         u8 comp_codes_10g = 0;
1154
1155         switch (hw->device_id) {
1156         case IXGBE_DEV_ID_82599:
1157         case IXGBE_DEV_ID_82599_KX4:
1158                 /* Default device ID is mezzanine card KX/KX4 */
1159                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1160                                   IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1161                 break;
1162         case IXGBE_DEV_ID_82599_SFP:
1163                 hw->phy.ops.identify_sfp(hw);
1164
1165                 switch (hw->phy.sfp_type) {
1166                 case ixgbe_sfp_type_da_cu:
1167                 case ixgbe_sfp_type_da_cu_core0:
1168                 case ixgbe_sfp_type_da_cu_core1:
1169                         physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1170                         break;
1171                 case ixgbe_sfp_type_sr:
1172                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1173                         break;
1174                 case ixgbe_sfp_type_lr:
1175                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1176                         break;
1177                 case ixgbe_sfp_type_srlr_core0:
1178                 case ixgbe_sfp_type_srlr_core1:
1179                         hw->phy.ops.read_i2c_eeprom(hw,
1180                                                     IXGBE_SFF_10GBE_COMP_CODES,
1181                                                     &comp_codes_10g);
1182                         if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1183                                 physical_layer =
1184                                                 IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1185                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1186                                 physical_layer =
1187                                                 IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1188                         else
1189                                 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1190                 default:
1191                         physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1192                         break;
1193                 }
1194                 break;
1195         default:
1196                 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1197                 break;
1198         }
1199
1200         return physical_layer;
1201 }
1202
1203 /**
1204  *  ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1205  *  @hw: pointer to hardware structure
1206  *  @regval: register value to write to RXCTRL
1207  *
1208  *  Enables the Rx DMA unit for 82599
1209  **/
1210 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1211 {
1212 #define IXGBE_MAX_SECRX_POLL 30
1213         int i;
1214         int secrxreg;
1215
1216         /*
1217          * Workaround for 82599 silicon errata when enabling the Rx datapath.
1218          * If traffic is incoming before we enable the Rx unit, it could hang
1219          * the Rx DMA unit.  Therefore, make sure the security engine is
1220          * completely disabled prior to enabling the Rx unit.
1221          */
1222         secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1223         secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1224         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1225         for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1226                 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1227                 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1228                         break;
1229                 else
1230                         udelay(10);
1231         }
1232
1233         /* For informational purposes only */
1234         if (i >= IXGBE_MAX_SECRX_POLL)
1235                 hw_dbg(hw, "Rx unit being enabled before security "
1236                        "path fully disabled.  Continuing with init.\n");
1237
1238         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1239         secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1240         secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1241         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1242         IXGBE_WRITE_FLUSH(hw);
1243
1244         return 0;
1245 }
1246
1247 static struct ixgbe_mac_operations mac_ops_82599 = {
1248         .init_hw                = &ixgbe_init_hw_generic,
1249         .reset_hw               = &ixgbe_reset_hw_82599,
1250         .start_hw               = &ixgbe_start_hw_82599,
1251         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
1252         .get_media_type         = &ixgbe_get_media_type_82599,
1253         .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1254         .enable_rx_dma          = &ixgbe_enable_rx_dma_82599,
1255         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
1256         .stop_adapter           = &ixgbe_stop_adapter_generic,
1257         .get_bus_info           = &ixgbe_get_bus_info_generic,
1258         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
1259         .read_analog_reg8       = &ixgbe_read_analog_reg8_82599,
1260         .write_analog_reg8      = &ixgbe_write_analog_reg8_82599,
1261         .setup_link             = &ixgbe_setup_mac_link_82599,
1262         .setup_link_speed       = &ixgbe_setup_mac_link_speed_82599,
1263         .check_link             = &ixgbe_check_mac_link_82599,
1264         .get_link_capabilities  = &ixgbe_get_link_capabilities_82599,
1265         .led_on                 = &ixgbe_led_on_generic,
1266         .led_off                = &ixgbe_led_off_generic,
1267         .blink_led_start        = &ixgbe_blink_led_start_82599,
1268         .blink_led_stop         = &ixgbe_blink_led_stop_82599,
1269         .set_rar                = &ixgbe_set_rar_generic,
1270         .clear_rar              = &ixgbe_clear_rar_generic,
1271         .set_vmdq               = &ixgbe_set_vmdq_82599,
1272         .clear_vmdq             = &ixgbe_clear_vmdq_82599,
1273         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
1274         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
1275         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1276         .enable_mc              = &ixgbe_enable_mc_generic,
1277         .disable_mc             = &ixgbe_disable_mc_generic,
1278         .clear_vfta             = &ixgbe_clear_vfta_82599,
1279         .set_vfta               = &ixgbe_set_vfta_82599,
1280         .setup_fc               = &ixgbe_setup_fc_generic,
1281         .init_uta_tables        = &ixgbe_init_uta_tables_82599,
1282         .setup_sfp              = &ixgbe_setup_sfp_modules_82599,
1283 };
1284
1285 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1286         .init_params            = &ixgbe_init_eeprom_params_generic,
1287         .read                   = &ixgbe_read_eeprom_generic,
1288         .write                  = &ixgbe_write_eeprom_generic,
1289         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
1290         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
1291 };
1292
1293 static struct ixgbe_phy_operations phy_ops_82599 = {
1294         .identify               = &ixgbe_identify_phy_82599,
1295         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
1296         .init                   = &ixgbe_init_phy_ops_82599,
1297         .reset                  = &ixgbe_reset_phy_generic,
1298         .read_reg               = &ixgbe_read_phy_reg_generic,
1299         .write_reg              = &ixgbe_write_phy_reg_generic,
1300         .setup_link             = &ixgbe_setup_phy_link_generic,
1301         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
1302         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic,
1303         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic,
1304         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic,
1305         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic,
1306 };
1307
1308 struct ixgbe_info ixgbe_82599_info = {
1309         .mac                    = ixgbe_mac_82599EB,
1310         .get_invariants         = &ixgbe_get_invariants_82599,
1311         .mac_ops                = &mac_ops_82599,
1312         .eeprom_ops             = &eeprom_ops_82599,
1313         .phy_ops                = &phy_ops_82599,
1314 };