1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
34 #include "ixgbe_phy.h"
36 #define IXGBE_82598_MAX_TX_QUEUES 32
37 #define IXGBE_82598_MAX_RX_QUEUES 64
38 #define IXGBE_82598_RAR_ENTRIES 16
39 #define IXGBE_82598_MC_TBL_SIZE 128
40 #define IXGBE_82598_VFT_TBL_SIZE 128
42 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
43 ixgbe_link_speed *speed,
45 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
46 static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
47 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw);
48 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
49 ixgbe_link_speed *speed,
50 bool *link_up, bool link_up_wait_to_complete);
51 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
52 ixgbe_link_speed speed,
54 bool autoneg_wait_to_complete);
55 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
56 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
57 ixgbe_link_speed speed,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
61 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
62 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
63 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan,
64 u32 vind, bool vlan_on);
65 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
66 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index);
67 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index);
68 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
69 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
70 static s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
71 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw);
75 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
77 struct ixgbe_mac_info *mac = &hw->mac;
78 struct ixgbe_phy_info *phy = &hw->phy;
80 /* Call PHY identify routine to get the phy type */
81 ixgbe_identify_phy_generic(hw);
89 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
90 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
91 mac->ops.setup_link_speed =
92 &ixgbe_setup_copper_link_speed_82598;
93 mac->ops.get_link_capabilities =
94 &ixgbe_get_copper_link_capabilities_82598;
97 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
98 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
99 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
100 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
101 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
107 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
108 * @hw: pointer to hardware structure
109 * @speed: pointer to link speed
110 * @autoneg: boolean auto-negotiation value
112 * Determines the link capabilities by reading the AUTOC register.
114 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
115 ixgbe_link_speed *speed,
121 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
123 if (hw->mac.link_settings_loaded) {
124 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
125 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
126 autoc_reg |= hw->mac.link_attach_type;
127 autoc_reg |= hw->mac.link_mode_select;
130 switch (autoc_reg & IXGBE_AUTOC_LMS_MASK) {
131 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
132 *speed = IXGBE_LINK_SPEED_1GB_FULL;
136 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
137 *speed = IXGBE_LINK_SPEED_10GB_FULL;
141 case IXGBE_AUTOC_LMS_1G_AN:
142 *speed = IXGBE_LINK_SPEED_1GB_FULL;
146 case IXGBE_AUTOC_LMS_KX4_AN:
147 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
148 *speed = IXGBE_LINK_SPEED_UNKNOWN;
149 if (autoc_reg & IXGBE_AUTOC_KX4_SUPP)
150 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
151 if (autoc_reg & IXGBE_AUTOC_KX_SUPP)
152 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
157 status = IXGBE_ERR_LINK_SETUP;
165 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
166 * @hw: pointer to hardware structure
167 * @speed: pointer to link speed
168 * @autoneg: boolean auto-negotiation value
170 * Determines the link capabilities by reading the AUTOC register.
172 s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
173 ixgbe_link_speed *speed,
176 s32 status = IXGBE_ERR_LINK_SETUP;
182 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
183 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
187 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
188 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
189 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
190 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
197 * ixgbe_get_media_type_82598 - Determines media type
198 * @hw: pointer to hardware structure
200 * Returns the media type (fiber, copper, backplane)
202 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
204 enum ixgbe_media_type media_type;
206 /* Media type for I82598 is based on device ID */
207 switch (hw->device_id) {
208 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
209 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
210 case IXGBE_DEV_ID_82598EB_CX4:
211 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
212 case IXGBE_DEV_ID_82598EB_XF_LR:
213 media_type = ixgbe_media_type_fiber;
216 media_type = ixgbe_media_type_unknown;
224 * ixgbe_setup_fc_82598 - Configure flow control settings
225 * @hw: pointer to hardware structure
226 * @packetbuf_num: packet buffer number (0-7)
228 * Configures the flow control settings based on SW configuration. This
229 * function is used for 802.3x flow control configuration only.
231 s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
236 if (packetbuf_num < 0 || packetbuf_num > 7) {
237 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
238 " 0-7\n", packetbuf_num);
241 frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
242 frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
244 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
245 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
248 * 10 gig parts do not have a word in the EEPROM to determine the
249 * default flow control setting, so we explicitly set it to full.
251 if (hw->fc.type == ixgbe_fc_default)
252 hw->fc.type = ixgbe_fc_full;
255 * We want to save off the original Flow Control configuration just in
256 * case we get disconnected and then reconnected into a different hub
257 * or switch with different Flow Control capabilities.
259 hw->fc.original_type = hw->fc.type;
262 * The possible values of the "flow_control" parameter are:
263 * 0: Flow control is completely disabled
264 * 1: Rx flow control is enabled (we can receive pause frames but not
265 * send pause frames).
266 * 2: Tx flow control is enabled (we can send pause frames but we do not
267 * support receiving pause frames)
268 * 3: Both Rx and Tx flow control (symmetric) are enabled.
271 switch (hw->fc.type) {
274 case ixgbe_fc_rx_pause:
276 * Rx Flow control is enabled,
277 * and Tx Flow control is disabled.
279 frctl_reg |= IXGBE_FCTRL_RFCE;
281 case ixgbe_fc_tx_pause:
283 * Tx Flow control is enabled, and Rx Flow control is disabled,
284 * by a software over-ride.
286 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
290 * Flow control (both Rx and Tx) is enabled by a software
293 frctl_reg |= IXGBE_FCTRL_RFCE;
294 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
297 /* We should never get here. The value should be 0-3. */
298 hw_dbg(hw, "Flow control param set incorrectly\n");
302 /* Enable 802.3x based flow control settings. */
303 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg);
304 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
307 * Check for invalid software configuration, zeros are completely
308 * invalid for all parameters used past this point, and if we enable
309 * flow control with zero water marks, we blast flow control packets.
311 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
312 hw_dbg(hw, "Flow control structure initialized incorrectly\n");
313 return IXGBE_ERR_INVALID_LINK_SETTINGS;
317 * We need to set up the Receive Threshold high and low water
318 * marks as well as (optionally) enabling the transmission of
321 if (hw->fc.type & ixgbe_fc_tx_pause) {
322 if (hw->fc.send_xon) {
323 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
324 (hw->fc.low_water | IXGBE_FCRTL_XONE));
326 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
329 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
330 (hw->fc.high_water)|IXGBE_FCRTH_FCEN);
333 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time);
334 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
340 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
341 * @hw: pointer to hardware structure
343 * Configures link settings based on values in the ixgbe_hw struct.
344 * Restarts the link. Performs autonegotiation if needed.
346 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
353 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
355 if (hw->mac.link_settings_loaded) {
356 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
357 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
358 autoc_reg |= hw->mac.link_attach_type;
359 autoc_reg |= hw->mac.link_mode_select;
361 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
362 IXGBE_WRITE_FLUSH(hw);
367 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
368 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
370 /* Only poll for autoneg to complete if specified to do so */
371 if (hw->phy.autoneg_wait_to_complete) {
372 if (hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN ||
373 hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
374 links_reg = 0; /* Just in case Autoneg time = 0 */
375 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
376 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
377 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
381 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
382 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
383 hw_dbg(hw, "Autonegotiation did not complete.\n");
389 * We want to save off the original Flow Control configuration just in
390 * case we get disconnected and then reconnected into a different hub
391 * or switch with different Flow Control capabilities.
393 hw->fc.original_type = hw->fc.type;
394 ixgbe_setup_fc_82598(hw, 0);
396 /* Add delay to filter out noises during initial link setup */
403 * ixgbe_check_mac_link_82598 - Get link/speed status
404 * @hw: pointer to hardware structure
405 * @speed: pointer to link speed
406 * @link_up: true is link is up, false otherwise
407 * @link_up_wait_to_complete: bool used to wait for link up or not
409 * Reads the links register to determine if link is up and the current speed
411 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
412 bool *link_up, bool link_up_wait_to_complete)
417 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
418 if (link_up_wait_to_complete) {
419 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
420 if (links_reg & IXGBE_LINKS_UP) {
427 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
430 if (links_reg & IXGBE_LINKS_UP)
436 if (links_reg & IXGBE_LINKS_SPEED)
437 *speed = IXGBE_LINK_SPEED_10GB_FULL;
439 *speed = IXGBE_LINK_SPEED_1GB_FULL;
446 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
447 * @hw: pointer to hardware structure
448 * @speed: new link speed
449 * @autoneg: true if auto-negotiation enabled
450 * @autoneg_wait_to_complete: true if waiting is needed to complete
452 * Set the link speed in the AUTOC register and restarts link.
454 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
455 ixgbe_link_speed speed, bool autoneg,
456 bool autoneg_wait_to_complete)
460 /* If speed is 10G, then check for CX4 or XAUI. */
461 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
462 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) {
463 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
464 } else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) {
465 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
466 } else if (autoneg) {
467 /* BX mode - Autonegotiate 1G */
468 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD))
469 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN;
470 else /* KX/KX4 mode */
471 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN_1G_AN;
473 status = IXGBE_ERR_LINK_SETUP;
477 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
479 hw->mac.link_settings_loaded = true;
481 * Setup and restart the link based on the new values in
482 * ixgbe_hw This will write the AUTOC register based on the new
485 ixgbe_setup_mac_link_82598(hw);
493 * ixgbe_setup_copper_link_82598 - Setup copper link settings
494 * @hw: pointer to hardware structure
496 * Configures link settings based on values in the ixgbe_hw struct.
497 * Restarts the link. Performs autonegotiation if needed. Restart
498 * phy and wait for autonegotiate to finish. Then synchronize the
501 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
505 /* Restart autonegotiation on PHY */
506 status = hw->phy.ops.setup_link(hw);
508 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
509 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
510 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
513 ixgbe_setup_mac_link_82598(hw);
519 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
520 * @hw: pointer to hardware structure
521 * @speed: new link speed
522 * @autoneg: true if autonegotiation enabled
523 * @autoneg_wait_to_complete: true if waiting is needed to complete
525 * Sets the link speed in the AUTOC register in the MAC and restarts link.
527 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
528 ixgbe_link_speed speed,
530 bool autoneg_wait_to_complete)
534 /* Setup the PHY according to input speed */
535 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
536 autoneg_wait_to_complete);
538 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
539 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
540 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
543 ixgbe_setup_mac_link_82598(hw);
549 * ixgbe_reset_hw_82598 - Performs hardware reset
550 * @hw: pointer to hardware structure
552 * Resets the hardware by resetting the transmit and receive units, masks and
553 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
556 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
565 /* Call adapter stop to disable tx/rx and clear interrupts */
566 hw->mac.ops.stop_adapter(hw);
569 * Power up the Atlas Tx lanes if they are currently powered down.
570 * Atlas Tx lanes are powered down for MAC loopback tests, but
571 * they are not automatically restored on reset.
573 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
574 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
575 /* Enable Tx Atlas so packets can be transmitted again */
576 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
578 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
579 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
582 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
584 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
585 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
588 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
590 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
591 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
594 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
596 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
597 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
602 if (hw->phy.reset_disable == false)
603 hw->phy.ops.reset(hw);
606 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
607 * access and verify no pending requests before reset
609 if (ixgbe_disable_pcie_master(hw) != 0) {
610 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
611 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
615 * Issue global reset to the MAC. This needs to be a SW reset.
616 * If link reset is used, it might reset the MAC when mng is using it
618 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
619 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
620 IXGBE_WRITE_FLUSH(hw);
622 /* Poll for reset bit to self-clear indicating reset is complete */
623 for (i = 0; i < 10; i++) {
625 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
626 if (!(ctrl & IXGBE_CTRL_RST))
629 if (ctrl & IXGBE_CTRL_RST) {
630 status = IXGBE_ERR_RESET_FAILED;
631 hw_dbg(hw, "Reset polling failed to complete.\n");
636 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
637 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
638 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
641 * AUTOC register which stores link settings gets cleared
642 * and reloaded from EEPROM after reset. We need to restore
643 * our stored value from init in case SW changed the attach
644 * type or speed. If this is the first time and link settings
645 * have not been stored, store default settings from AUTOC.
647 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
648 if (hw->mac.link_settings_loaded) {
649 autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE);
650 autoc &= ~(IXGBE_AUTOC_LMS_MASK);
651 autoc |= hw->mac.link_attach_type;
652 autoc |= hw->mac.link_mode_select;
653 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
655 hw->mac.link_attach_type =
656 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE);
657 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK);
658 hw->mac.link_settings_loaded = true;
661 /* Store the permanent mac address */
662 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
668 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
669 * @hw: pointer to hardware struct
670 * @rar: receive address register index to associate with a VMDq index
671 * @vmdq: VMDq set index
673 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
677 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
678 rar_high &= ~IXGBE_RAH_VIND_MASK;
679 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
680 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
685 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
686 * @hw: pointer to hardware struct
687 * @rar: receive address register index to associate with a VMDq index
688 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
690 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
693 u32 rar_entries = hw->mac.num_rar_entries;
695 if (rar < rar_entries) {
696 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
697 if (rar_high & IXGBE_RAH_VIND_MASK) {
698 rar_high &= ~IXGBE_RAH_VIND_MASK;
699 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
702 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
709 * ixgbe_set_vfta_82598 - Set VLAN filter table
710 * @hw: pointer to hardware structure
711 * @vlan: VLAN id to write to VLAN filter
712 * @vind: VMDq output index that maps queue to VLAN id in VFTA
713 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
715 * Turn on/off specified VLAN in the VLAN filter table.
717 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
726 return IXGBE_ERR_PARAM;
728 /* Determine 32-bit word position in array */
729 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
731 /* Determine the location of the (VMD) queue index */
732 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
733 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
735 /* Set the nibble for VMD queue index */
736 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
737 bits &= (~(0x0F << bitindex));
738 bits |= (vind << bitindex);
739 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
741 /* Determine the location of the bit for this VLAN id */
742 bitindex = vlan & 0x1F; /* lower five bits */
744 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
746 /* Turn on this VLAN id */
747 bits |= (1 << bitindex);
749 /* Turn off this VLAN id */
750 bits &= ~(1 << bitindex);
751 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
757 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
758 * @hw: pointer to hardware structure
760 * Clears the VLAN filer table, and the VMDq index associated with the filter
762 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
767 for (offset = 0; offset < hw->mac.vft_size; offset++)
768 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
770 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
771 for (offset = 0; offset < hw->mac.vft_size; offset++)
772 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
779 * ixgbe_blink_led_start_82598 - Blink LED based on index.
780 * @hw: pointer to hardware structure
781 * @index: led number to blink
783 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
785 ixgbe_link_speed speed = 0;
787 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
788 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
791 * Link must be up to auto-blink the LEDs on the 82598EB MAC;
792 * force it if link is down.
794 hw->mac.ops.check_link(hw, &speed, &link_up, false);
797 autoc_reg |= IXGBE_AUTOC_FLU;
798 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
802 led_reg &= ~IXGBE_LED_MODE_MASK(index);
803 led_reg |= IXGBE_LED_BLINK(index);
804 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
805 IXGBE_WRITE_FLUSH(hw);
811 * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
812 * @hw: pointer to hardware structure
813 * @index: led number to stop blinking
815 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
817 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
818 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
820 autoc_reg &= ~IXGBE_AUTOC_FLU;
821 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
822 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
824 led_reg &= ~IXGBE_LED_MODE_MASK(index);
825 led_reg &= ~IXGBE_LED_BLINK(index);
826 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
827 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
828 IXGBE_WRITE_FLUSH(hw);
834 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
835 * @hw: pointer to hardware structure
836 * @reg: analog register to read
839 * Performs read operation to Atlas analog register specified.
841 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
845 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
846 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
847 IXGBE_WRITE_FLUSH(hw);
849 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
850 *val = (u8)atlas_ctl;
856 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
857 * @hw: pointer to hardware structure
858 * @reg: atlas register to write
859 * @val: value to write
861 * Performs write operation to Atlas analog register specified.
863 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
867 atlas_ctl = (reg << 8) | val;
868 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
869 IXGBE_WRITE_FLUSH(hw);
876 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
877 * @hw: pointer to hardware structure
879 * Determines physical layer capabilities of the current configuration.
881 s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
883 s32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
885 switch (hw->device_id) {
886 case IXGBE_DEV_ID_82598EB_CX4:
887 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
888 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
890 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
891 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
892 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
894 case IXGBE_DEV_ID_82598EB_XF_LR:
895 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
899 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
903 return physical_layer;
906 static struct ixgbe_mac_operations mac_ops_82598 = {
907 .init_hw = &ixgbe_init_hw_generic,
908 .reset_hw = &ixgbe_reset_hw_82598,
909 .start_hw = &ixgbe_start_hw_generic,
910 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
911 .get_media_type = &ixgbe_get_media_type_82598,
912 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
913 .get_mac_addr = &ixgbe_get_mac_addr_generic,
914 .stop_adapter = &ixgbe_stop_adapter_generic,
915 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
916 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
917 .setup_link = &ixgbe_setup_mac_link_82598,
918 .setup_link_speed = &ixgbe_setup_mac_link_speed_82598,
919 .check_link = &ixgbe_check_mac_link_82598,
920 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
921 .led_on = &ixgbe_led_on_generic,
922 .led_off = &ixgbe_led_off_generic,
923 .blink_led_start = &ixgbe_blink_led_start_82598,
924 .blink_led_stop = &ixgbe_blink_led_stop_82598,
925 .set_rar = &ixgbe_set_rar_generic,
926 .clear_rar = &ixgbe_clear_rar_generic,
927 .set_vmdq = &ixgbe_set_vmdq_82598,
928 .clear_vmdq = &ixgbe_clear_vmdq_82598,
929 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
930 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
931 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
932 .enable_mc = &ixgbe_enable_mc_generic,
933 .disable_mc = &ixgbe_disable_mc_generic,
934 .clear_vfta = &ixgbe_clear_vfta_82598,
935 .set_vfta = &ixgbe_set_vfta_82598,
936 .setup_fc = &ixgbe_setup_fc_82598,
939 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
940 .init_params = &ixgbe_init_eeprom_params_generic,
941 .read = &ixgbe_read_eeprom_generic,
942 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
943 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
946 static struct ixgbe_phy_operations phy_ops_82598 = {
947 .identify = &ixgbe_identify_phy_generic,
948 /* .identify_sfp = &ixgbe_identify_sfp_module_generic, */
949 .reset = &ixgbe_reset_phy_generic,
950 .read_reg = &ixgbe_read_phy_reg_generic,
951 .write_reg = &ixgbe_write_phy_reg_generic,
952 .setup_link = &ixgbe_setup_phy_link_generic,
953 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
956 struct ixgbe_info ixgbe_82598_info = {
957 .mac = ixgbe_mac_82598EB,
958 .get_invariants = &ixgbe_get_invariants_82598,
959 .mac_ops = &mac_ops_82598,
960 .eeprom_ops = &eeprom_ops_82598,
961 .phy_ops = &phy_ops_82598,