Pileus Git - ~andy/linux/blob - drivers/net/irda/sh_sir.c

   1 /*
   2  * SuperH IrDA Driver
   3  *
   4  * Copyright (C) 2009 Renesas Solutions Corp.
   5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   6  *
   7  * Based on bfin_sir.c
   8  * Copyright 2006-2009 Analog Devices Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <net/irda/wrapper.h>
  18 #include <net/irda/irda_device.h>
  19 #include <asm/clock.h>
  20
  21 #define DRIVER_NAME "sh_sir"
  22
  23 #define RX_PHASE        (1 << 0)
  24 #define TX_PHASE        (1 << 1)
  25 #define TX_COMP_PHASE   (1 << 2) /* tx complete */
  26 #define NONE_PHASE      (1 << 31)
  27
  28 #define IRIF_RINTCLR    0x0016 /* DMA rx interrupt source clear */
  29 #define IRIF_TINTCLR    0x0018 /* DMA tx interrupt source clear */
  30 #define IRIF_SIR0       0x0020 /* IrDA-SIR10 control */
  31 #define IRIF_SIR1       0x0022 /* IrDA-SIR10 baudrate error correction */
  32 #define IRIF_SIR2       0x0024 /* IrDA-SIR10 baudrate count */
  33 #define IRIF_SIR3       0x0026 /* IrDA-SIR10 status */
  34 #define IRIF_SIR_FRM    0x0028 /* Hardware frame processing set */
  35 #define IRIF_SIR_EOF    0x002A /* EOF value */
  36 #define IRIF_SIR_FLG    0x002C /* Flag clear */
  37 #define IRIF_UART_STS2  0x002E /* UART status 2 */
  38 #define IRIF_UART0      0x0030 /* UART control */
  39 #define IRIF_UART1      0x0032 /* UART status */
  40 #define IRIF_UART2      0x0034 /* UART mode */
  41 #define IRIF_UART3      0x0036 /* UART transmit data */
  42 #define IRIF_UART4      0x0038 /* UART receive data */
  43 #define IRIF_UART5      0x003A /* UART interrupt mask */
  44 #define IRIF_UART6      0x003C /* UART baud rate error correction */
  45 #define IRIF_UART7      0x003E /* UART baud rate count set */
  46 #define IRIF_CRC0       0x0040 /* CRC engine control */
  47 #define IRIF_CRC1       0x0042 /* CRC engine input data */
  48 #define IRIF_CRC2       0x0044 /* CRC engine calculation */
  49 #define IRIF_CRC3       0x0046 /* CRC engine output data 1 */
  50 #define IRIF_CRC4       0x0048 /* CRC engine output data 2 */
  51
  52 /* IRIF_SIR0 */
  53 #define IRTPW           (1 << 1) /* transmit pulse width select */
  54 #define IRERRC          (1 << 0) /* Clear receive pulse width error */
  55
  56 /* IRIF_SIR3 */
  57 #define IRERR           (1 << 0) /* received pulse width Error */
  58
  59 /* IRIF_SIR_FRM */
  60 #define EOFD            (1 << 9) /* EOF detection flag */
  61 #define FRER            (1 << 8) /* Frame Error bit */
  62 #define FRP             (1 << 0) /* Frame processing set */
  63
  64 /* IRIF_UART_STS2 */
  65 #define IRSME           (1 << 6) /* Receive Sum     Error flag */
  66 #define IROVE           (1 << 5) /* Receive Overrun Error flag */
  67 #define IRFRE           (1 << 4) /* Receive Framing Error flag */
  68 #define IRPRE           (1 << 3) /* Receive Parity  Error flag */
  69
  70 /* IRIF_UART0_*/
  71 #define TBEC            (1 << 2) /* Transmit Data Clear */
  72 #define RIE             (1 << 1) /* Receive Enable */
  73 #define TIE             (1 << 0) /* Transmit Enable */
  74
  75 /* IRIF_UART1 */
  76 #define URSME           (1 << 6) /* Receive Sum Error Flag */
  77 #define UROVE           (1 << 5) /* Receive Overrun Error Flag */
  78 #define URFRE           (1 << 4) /* Receive Framing Error Flag */
  79 #define URPRE           (1 << 3) /* Receive Parity Error Flag */
  80 #define RBF             (1 << 2) /* Receive Buffer Full Flag */
  81 #define TSBE            (1 << 1) /* Transmit Shift Buffer Empty Flag */
  82 #define TBE             (1 << 0) /* Transmit Buffer Empty flag */
  83 #define TBCOMP          (TSBE | TBE)
  84
  85 /* IRIF_UART5 */
  86 #define RSEIM           (1 << 6) /* Receive Sum Error Flag IRQ Mask */
  87 #define RBFIM           (1 << 2) /* Receive Buffer Full Flag IRQ Mask */
  88 #define TSBEIM          (1 << 1) /* Transmit Shift Buffer Empty Flag IRQ Mask */
  89 #define TBEIM           (1 << 0) /* Transmit Buffer Empty Flag IRQ Mask */
  90 #define RX_MASK         (RSEIM  | RBFIM)
  91
  92 /* IRIF_CRC0 */
  93 #define CRC_RST         (1 << 15) /* CRC Engine Reset */
  94 #define CRC_CT_MASK     0x0FFF
  95
  96 /************************************************************************
  97
  98
  99                         structure
 100
 101
 102 ************************************************************************/
 103 struct sh_sir_self {
 104         void __iomem            *membase;
 105         unsigned int             irq;
 106         struct clk              *clk;
 107
 108         struct net_device       *ndev;
 109
 110         struct irlap_cb         *irlap;
 111         struct qos_info         qos;
 112
 113         iobuff_t                tx_buff;
 114         iobuff_t                rx_buff;
 115 };
 116
 117 /************************************************************************
 118
 119
 120                         common function
 121
 122
 123 ************************************************************************/
 124 static void sh_sir_write(struct sh_sir_self *self, u32 offset, u16 data)
 125 {
 126         iowrite16(data, self->membase + offset);
 127 }
 128
 129 static u16 sh_sir_read(struct sh_sir_self *self, u32 offset)
 130 {
 131         return ioread16(self->membase + offset);
 132 }
 133
 134 static void sh_sir_update_bits(struct sh_sir_self *self, u32 offset,
 135                                u16 mask, u16 data)
 136 {
 137         u16 old, new;
 138
 139         old = sh_sir_read(self, offset);
 140         new = (old & ~mask) | data;
 141         if (old != new)
 142                 sh_sir_write(self, offset, new);
 143 }
 144
 145 /************************************************************************
 146
 147
 148                         CRC function
 149
 150
 151 ************************************************************************/
 152 static void sh_sir_crc_reset(struct sh_sir_self *self)
 153 {
 154         sh_sir_write(self, IRIF_CRC0, CRC_RST);
 155 }
 156
 157 static void sh_sir_crc_add(struct sh_sir_self *self, u8 data)
 158 {
 159         sh_sir_write(self, IRIF_CRC1, (u16)data);
 160 }
 161
 162 static u16 sh_sir_crc_cnt(struct sh_sir_self *self)
 163 {
 164         return CRC_CT_MASK & sh_sir_read(self, IRIF_CRC0);
 165 }
 166
 167 static u16 sh_sir_crc_out(struct sh_sir_self *self)
 168 {
 169         return sh_sir_read(self, IRIF_CRC4);
 170 }
 171
 172 static int sh_sir_crc_init(struct sh_sir_self *self)
 173 {
 174         struct device *dev = &self->ndev->dev;
 175         int ret = -EIO;
 176         u16 val;
 177
 178         sh_sir_crc_reset(self);
 179
 180         sh_sir_crc_add(self, 0xCC);
 181         sh_sir_crc_add(self, 0xF5);
 182         sh_sir_crc_add(self, 0xF1);
 183         sh_sir_crc_add(self, 0xA7);
 184
 185         val = sh_sir_crc_cnt(self);
 186         if (4 != val) {
 187                 dev_err(dev, "CRC count error %x\n", val);
 188                 goto crc_init_out;
 189         }
 190
 191         val = sh_sir_crc_out(self);
 192         if (0x51DF != val) {
 193                 dev_err(dev, "CRC result error%x\n", val);
 194                 goto crc_init_out;
 195         }
 196
 197         ret = 0;
 198
 199 crc_init_out:
 200
 201         sh_sir_crc_reset(self);
 202         return ret;
 203 }
 204
 205 /************************************************************************
 206
 207
 208                         baud rate functions
 209
 210
 211 ************************************************************************/
 212 #define SCLK_BASE 1843200 /* 1.8432MHz */
 213
 214 static u32 sh_sir_find_sclk(struct clk *irda_clk)
 215 {
 216         struct cpufreq_frequency_table *freq_table = irda_clk->freq_table;
 217         struct clk *pclk = clk_get(NULL, "peripheral_clk");
 218         u32 limit, min = 0xffffffff, tmp;
 219         int i, index = 0;
 220
 221         limit = clk_get_rate(pclk);
 222         clk_put(pclk);
 223
 224         /* IrDA can not set over peripheral_clk */
 225         for (i = 0;
 226              freq_table[i].frequency != CPUFREQ_TABLE_END;
 227              i++) {
 228                 u32 freq = freq_table[i].frequency;
 229
 230                 if (freq == CPUFREQ_ENTRY_INVALID)
 231                         continue;
 232
 233                 /* IrDA should not over peripheral_clk */
 234                 if (freq > limit)
 235                         continue;
 236
 237                 tmp = freq % SCLK_BASE;
 238                 if (tmp < min) {
 239                         min = tmp;
 240                         index = i;
 241                 }
 242         }
 243
 244         return freq_table[index].frequency;
 245 }
 246
 247 #define ERR_ROUNDING(a) ((a + 5000) / 10000)
 248 static int sh_sir_set_baudrate(struct sh_sir_self *self, u32 baudrate)
 249 {
 250         struct clk *clk;
 251         struct device *dev = &self->ndev->dev;
 252         u32 rate;
 253         u16 uabca, uabc;
 254         u16 irbca, irbc;
 255         u32 min, rerr, tmp;
 256         int i;
 257
 258         /* Baud Rate Error Correction x 10000 */
 259         u32 rate_err_array[] = {
 260                 0000, 0625, 1250, 1875,
 261                 2500, 3125, 3750, 4375,
 262                 5000, 5625, 6250, 6875,
 263                 7500, 8125, 8750, 9375,
 264         };
 265
 266         /*
 267          * FIXME
 268          *
 269          * it support 9600 only now
 270          */
 271         switch (baudrate) {
 272         case 9600:
 273                 break;
 274         default:
 275                 dev_err(dev, "un-supported baudrate %d\n", baudrate);
 276                 return -EIO;
 277         }
 278
 279         clk = clk_get(NULL, "irda_clk");
 280         if (!clk) {
 281                 dev_err(dev, "can not get irda_clk\n");
 282                 return -EIO;
 283         }
 284
 285         clk_set_rate(clk, sh_sir_find_sclk(clk));
 286         rate = clk_get_rate(clk);
 287         clk_put(clk);
 288
 289         dev_dbg(dev, "selected sclk = %d\n", rate);
 290
 291         /*
 292          * CALCULATION
 293          *
 294          * 1843200 = system rate / (irbca + (irbc + 1))
 295          */
 296
 297         irbc = rate / SCLK_BASE;
 298
 299         tmp = rate - (SCLK_BASE * irbc);
 300         tmp *= 10000;
 301
 302         rerr = tmp / SCLK_BASE;
 303
 304         min = 0xffffffff;
 305         irbca = 0;
 306         for (i = 0; i < ARRAY_SIZE(rate_err_array); i++) {
 307                 tmp = abs(rate_err_array[i] - rerr);
 308                 if (min > tmp) {
 309                         min = tmp;
 310                         irbca = i;
 311                 }
 312         }
 313
 314         tmp = rate / (irbc + ERR_ROUNDING(rate_err_array[irbca]));
 315         if ((SCLK_BASE / 100) < abs(tmp - SCLK_BASE))
 316                 dev_warn(dev, "IrDA freq error margin over %d\n", tmp);
 317
 318         dev_dbg(dev, "target = %d, result = %d, infrared = %d.%d\n",
 319                SCLK_BASE, tmp, irbc, rate_err_array[irbca]);
 320
 321         irbca = (irbca & 0xF) << 4;
 322         irbc  = (irbc - 1) & 0xF;
 323
 324         if (!irbc) {
 325                 dev_err(dev, "sh_sir can not set 0 in IRIF_SIR2\n");
 326                 return -EIO;
 327         }
 328
 329         sh_sir_write(self, IRIF_SIR0, IRTPW | IRERRC);
 330         sh_sir_write(self, IRIF_SIR1, irbca);
 331         sh_sir_write(self, IRIF_SIR2, irbc);
 332
 333         /*
 334          * CALCULATION
 335          *
 336          * BaudRate[bps] = system rate / (uabca + (uabc + 1) x 16)
 337          */
 338
 339         uabc = rate / baudrate;
 340         uabc = (uabc / 16) - 1;
 341         uabc = (uabc + 1) * 16;
 342
 343         tmp = rate - (uabc * baudrate);
 344         tmp *= 10000;
 345
 346         rerr = tmp / baudrate;
 347
 348         min = 0xffffffff;
 349         uabca = 0;
 350         for (i = 0; i < ARRAY_SIZE(rate_err_array); i++) {
 351                 tmp = abs(rate_err_array[i] - rerr);
 352                 if (min > tmp) {
 353                         min = tmp;
 354                         uabca = i;
 355                 }
 356         }
 357
 358         tmp = rate / (uabc + ERR_ROUNDING(rate_err_array[uabca]));
 359         if ((baudrate / 100) < abs(tmp - baudrate))
 360                 dev_warn(dev, "UART freq error margin over %d\n", tmp);
 361
 362         dev_dbg(dev, "target = %d, result = %d, uart = %d.%d\n",
 363                baudrate, tmp,
 364                uabc, rate_err_array[uabca]);
 365
 366         uabca = (uabca & 0xF) << 4;
 367         uabc  = (uabc / 16) - 1;
 368
 369         sh_sir_write(self, IRIF_UART6, uabca);
 370         sh_sir_write(self, IRIF_UART7, uabc);
 371
 372         return 0;
 373 }
 374
 375 /************************************************************************
 376
 377
 378                         iobuf function
 379
 380
 381 ************************************************************************/
 382 static int __sh_sir_init_iobuf(iobuff_t *io, int size)
 383 {
 384         io->head = kmalloc(size, GFP_KERNEL);
 385         if (!io->head)
 386                 return -ENOMEM;
 387
 388         io->truesize    = size;
 389         io->in_frame    = FALSE;
 390         io->state       = OUTSIDE_FRAME;
 391         io->data        = io->head;
 392
 393         return 0;
 394 }
 395
 396 static void sh_sir_remove_iobuf(struct sh_sir_self *self)
 397 {
 398         kfree(self->rx_buff.head);
 399         kfree(self->tx_buff.head);
 400
 401         self->rx_buff.head = NULL;
 402         self->tx_buff.head = NULL;
 403 }
 404
 405 static int sh_sir_init_iobuf(struct sh_sir_self *self, int rxsize, int txsize)
 406 {
 407         int err = -ENOMEM;
 408
 409         if (self->rx_buff.head ||
 410             self->tx_buff.head) {
 411                 dev_err(&self->ndev->dev, "iobuff has already existed.");
 412                 return err;
 413         }
 414
 415         err = __sh_sir_init_iobuf(&self->rx_buff, rxsize);
 416         if (err)
 417                 goto iobuf_err;
 418
 419         err = __sh_sir_init_iobuf(&self->tx_buff, txsize);
 420
 421 iobuf_err:
 422         if (err)
 423                 sh_sir_remove_iobuf(self);
 424
 425         return err;
 426 }
 427
 428 /************************************************************************
 429
 430
 431                         status function
 432
 433
 434 ************************************************************************/
 435 static void sh_sir_clear_all_err(struct sh_sir_self *self)
 436 {
 437         /* Clear error flag for receive pulse width */
 438         sh_sir_update_bits(self, IRIF_SIR0, IRERRC, IRERRC);
 439
 440         /* Clear frame / EOF error flag */
 441         sh_sir_write(self, IRIF_SIR_FLG, 0xffff);
 442
 443         /* Clear all status error */
 444         sh_sir_write(self, IRIF_UART_STS2, 0);
 445 }
 446
 447 static void sh_sir_set_phase(struct sh_sir_self *self, int phase)
 448 {
 449         u16 uart5 = 0;
 450         u16 uart0 = 0;
 451
 452         switch (phase) {
 453         case TX_PHASE:
 454                 uart5 = TBEIM;
 455                 uart0 = TBEC | TIE;
 456                 break;
 457         case TX_COMP_PHASE:
 458                 uart5 = TSBEIM;
 459                 uart0 = TIE;
 460                 break;
 461         case RX_PHASE:
 462                 uart5 = RX_MASK;
 463                 uart0 = RIE;
 464                 break;
 465         default:
 466                 break;
 467         }
 468
 469         sh_sir_write(self, IRIF_UART5, uart5);
 470         sh_sir_write(self, IRIF_UART0, uart0);
 471 }
 472
 473 static int sh_sir_is_which_phase(struct sh_sir_self *self)
 474 {
 475         u16 val = sh_sir_read(self, IRIF_UART5);
 476
 477         if (val & TBEIM)
 478                 return TX_PHASE;
 479
 480         if (val & TSBEIM)
 481                 return TX_COMP_PHASE;
 482
 483         if (val & RX_MASK)
 484                 return RX_PHASE;
 485
 486         return NONE_PHASE;
 487 }
 488
 489 static void sh_sir_tx(struct sh_sir_self *self, int phase)
 490 {
 491         switch (phase) {
 492         case TX_PHASE:
 493                 if (0 >= self->tx_buff.len) {
 494                         sh_sir_set_phase(self, TX_COMP_PHASE);
 495                 } else {
 496                         sh_sir_write(self, IRIF_UART3, self->tx_buff.data[0]);
 497                         self->tx_buff.len--;
 498                         self->tx_buff.data++;
 499                 }
 500                 break;
 501         case TX_COMP_PHASE:
 502                 sh_sir_set_phase(self, RX_PHASE);
 503                 netif_wake_queue(self->ndev);
 504                 break;
 505         default:
 506                 dev_err(&self->ndev->dev, "should not happen\n");
 507                 break;
 508         }
 509 }
 510
 511 static int sh_sir_read_data(struct sh_sir_self *self)
 512 {
 513         u16 val;
 514         int timeout = 1024;
 515
 516         while (timeout--) {
 517                 val = sh_sir_read(self, IRIF_UART1);
 518
 519                 /* data get */
 520                 if (val & RBF) {
 521                         if (val & (URSME | UROVE | URFRE | URPRE))
 522                                 break;
 523
 524                         return (int)sh_sir_read(self, IRIF_UART4);
 525                 }
 526
 527                 udelay(1);
 528         }
 529
 530         dev_err(&self->ndev->dev, "UART1 %04x : STATUS %04x\n",
 531                 val, sh_sir_read(self, IRIF_UART_STS2));
 532
 533         /* read data register for clear error */
 534         sh_sir_read(self, IRIF_UART4);
 535
 536         return -1;
 537 }
 538
 539 static void sh_sir_rx(struct sh_sir_self *self)
 540 {
 541         int timeout = 1024;
 542         int data;
 543
 544         while (timeout--) {
 545                 data = sh_sir_read_data(self);
 546                 if (data < 0)
 547                         break;
 548
 549                 async_unwrap_char(self->ndev, &self->ndev->stats,
 550                                   &self->rx_buff, (u8)data);
 551                 self->ndev->last_rx = jiffies;
 552
 553                 if (EOFD & sh_sir_read(self, IRIF_SIR_FRM))
 554                         continue;
 555
 556                 break;
 557         }
 558 }
 559
 560 static irqreturn_t sh_sir_irq(int irq, void *dev_id)
 561 {
 562         struct sh_sir_self *self = dev_id;
 563         struct device *dev = &self->ndev->dev;
 564         int phase = sh_sir_is_which_phase(self);
 565
 566         switch (phase) {
 567         case TX_COMP_PHASE:
 568         case TX_PHASE:
 569                 sh_sir_tx(self, phase);
 570                 break;
 571         case RX_PHASE:
 572                 if (sh_sir_read(self, IRIF_SIR3))
 573                         dev_err(dev, "rcv pulse width error occurred\n");
 574
 575                 sh_sir_rx(self);
 576                 sh_sir_clear_all_err(self);
 577                 break;
 578         default:
 579                 dev_err(dev, "unknown interrupt\n");
 580         }
 581
 582          return IRQ_HANDLED;
 583 }
 584
 585 /************************************************************************
 586
 587
 588                         net_device_ops function
 589
 590
 591 ************************************************************************/
 592 static int sh_sir_hard_xmit(struct sk_buff *skb, struct net_device *ndev)
 593 {
 594         struct sh_sir_self *self = netdev_priv(ndev);
 595         int speed = irda_get_next_speed(skb);
 596
 597         if ((0 < speed) &&
 598             (9600 != speed)) {
 599                 dev_err(&ndev->dev, "support 9600 only (%d)\n", speed);
 600                 return -EIO;
 601         }
 602
 603         netif_stop_queue(ndev);
 604
 605         self->tx_buff.data = self->tx_buff.head;
 606         self->tx_buff.len = 0;
 607         if (skb->len)
 608                 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
 609                                                    self->tx_buff.truesize);
 610
 611         sh_sir_set_phase(self, TX_PHASE);
 612         dev_kfree_skb(skb);
 613
 614         return 0;
 615 }
 616
 617 static int sh_sir_ioctl(struct net_device *ndev, struct ifreq *ifreq, int cmd)
 618 {
 619         /*
 620          * FIXME
 621          *
 622          * This function is needed for irda framework.
 623          * But nothing to do now
 624          */
 625         return 0;
 626 }
 627
 628 static struct net_device_stats *sh_sir_stats(struct net_device *ndev)
 629 {
 630         struct sh_sir_self *self = netdev_priv(ndev);
 631
 632         return &self->ndev->stats;
 633 }
 634
 635 static int sh_sir_open(struct net_device *ndev)
 636 {
 637         struct sh_sir_self *self = netdev_priv(ndev);
 638         int err;
 639
 640         clk_enable(self->clk);
 641         err = sh_sir_crc_init(self);
 642         if (err)
 643                 goto open_err;
 644
 645         sh_sir_set_baudrate(self, 9600);
 646
 647         self->irlap = irlap_open(ndev, &self->qos, DRIVER_NAME);
 648         if (!self->irlap)
 649                 goto open_err;
 650
 651         /*
 652          * Now enable the interrupt then start the queue
 653          */
 654         sh_sir_update_bits(self, IRIF_SIR_FRM, FRP, FRP);
 655         sh_sir_read(self, IRIF_UART1); /* flag clear */
 656         sh_sir_read(self, IRIF_UART4); /* flag clear */
 657         sh_sir_set_phase(self, RX_PHASE);
 658
 659         netif_start_queue(ndev);
 660
 661         dev_info(&self->ndev->dev, "opened\n");
 662
 663         return 0;
 664
 665 open_err:
 666         clk_disable(self->clk);
 667
 668         return err;
 669 }
 670
 671 static int sh_sir_stop(struct net_device *ndev)
 672 {
 673         struct sh_sir_self *self = netdev_priv(ndev);
 674
 675         /* Stop IrLAP */
 676         if (self->irlap) {
 677                 irlap_close(self->irlap);
 678                 self->irlap = NULL;
 679         }
 680
 681         netif_stop_queue(ndev);
 682
 683         dev_info(&ndev->dev, "stoped\n");
 684
 685         return 0;
 686 }
 687
 688 static const struct net_device_ops sh_sir_ndo = {
 689         .ndo_open               = sh_sir_open,
 690         .ndo_stop               = sh_sir_stop,
 691         .ndo_start_xmit         = sh_sir_hard_xmit,
 692         .ndo_do_ioctl           = sh_sir_ioctl,
 693         .ndo_get_stats          = sh_sir_stats,
 694 };
 695
 696 /************************************************************************
 697
 698
 699                         platform_driver function
 700
 701
 702 ************************************************************************/
 703 static int __devinit sh_sir_probe(struct platform_device *pdev)
 704 {
 705         struct net_device *ndev;
 706         struct sh_sir_self *self;
 707         struct resource *res;
 708         char clk_name[8];
 709         void __iomem *base;
 710         unsigned int irq;
 711         int err = -ENOMEM;
 712
 713         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 714         irq = platform_get_irq(pdev, 0);
 715         if (!res || irq < 0) {
 716                 dev_err(&pdev->dev, "Not enough platform resources.\n");
 717                 goto exit;
 718         }
 719
 720         ndev = alloc_irdadev(sizeof(*self));
 721         if (!ndev)
 722                 goto exit;
 723
 724         base = ioremap_nocache(res->start, resource_size(res));
 725         if (!base) {
 726                 err = -ENXIO;
 727                 dev_err(&pdev->dev, "Unable to ioremap.\n");
 728                 goto err_mem_1;
 729         }
 730
 731         self = netdev_priv(ndev);
 732         err = sh_sir_init_iobuf(self, IRDA_SKB_MAX_MTU, IRDA_SIR_MAX_FRAME);
 733         if (err)
 734                 goto err_mem_2;
 735
 736         snprintf(clk_name, sizeof(clk_name), "irda%d", pdev->id);
 737         self->clk = clk_get(&pdev->dev, clk_name);
 738         if (IS_ERR(self->clk)) {
 739                 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
 740                 goto err_mem_3;
 741         }
 742
 743         irda_init_max_qos_capabilies(&self->qos);
 744
 745         ndev->netdev_ops        = &sh_sir_ndo;
 746         ndev->irq               = irq;
 747
 748         self->membase                   = base;
 749         self->ndev                      = ndev;
 750         self->qos.baud_rate.bits        &= IR_9600; /* FIXME */
 751         self->qos.min_turn_time.bits    = 1; /* 10 ms or more */
 752
 753         irda_qos_bits_to_value(&self->qos);
 754
 755         err = register_netdev(ndev);
 756         if (err)
 757                 goto err_mem_4;
 758
 759         platform_set_drvdata(pdev, ndev);
 760
 761         if (request_irq(irq, sh_sir_irq, IRQF_DISABLED, "sh_sir", self)) {
 762                 dev_warn(&pdev->dev, "Unable to attach sh_sir interrupt\n");
 763                 goto err_mem_4;
 764         }
 765
 766         dev_info(&pdev->dev, "SuperH IrDA probed\n");
 767
 768         goto exit;
 769
 770 err_mem_4:
 771         clk_put(self->clk);
 772 err_mem_3:
 773         sh_sir_remove_iobuf(self);
 774 err_mem_2:
 775         iounmap(self->membase);
 776 err_mem_1:
 777         free_netdev(ndev);
 778 exit:
 779         return err;
 780 }
 781
 782 static int __devexit sh_sir_remove(struct platform_device *pdev)
 783 {
 784         struct net_device *ndev = platform_get_drvdata(pdev);
 785         struct sh_sir_self *self = netdev_priv(ndev);
 786
 787         if (!self)
 788                 return 0;
 789
 790         unregister_netdev(ndev);
 791         clk_put(self->clk);
 792         sh_sir_remove_iobuf(self);
 793         iounmap(self->membase);
 794         free_netdev(ndev);
 795         platform_set_drvdata(pdev, NULL);
 796
 797         return 0;
 798 }
 799
 800 static struct platform_driver sh_sir_driver = {
 801         .probe   = sh_sir_probe,
 802         .remove  = __devexit_p(sh_sir_remove),
 803         .driver  = {
 804                 .name = DRIVER_NAME,
 805         },
 806 };
 807
 808 static int __init sh_sir_init(void)
 809 {
 810         return platform_driver_register(&sh_sir_driver);
 811 }
 812
 813 static void __exit sh_sir_exit(void)
 814 {
 815         platform_driver_unregister(&sh_sir_driver);
 816 }
 817
 818 module_init(sh_sir_init);
 819 module_exit(sh_sir_exit);
 820
 821 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
 822 MODULE_DESCRIPTION("SuperH IrDA driver");
 823 MODULE_LICENSE("GPL");