Pileus Git - ~andy/linux/blob - drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4,5 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  93  *      0.40: 19 Jul 2005: Add support for mac address change.
  94  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  95  *                         of nv_remove
  96  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  97  *                         in the second (and later) nv_open call
  98  *      0.43: 10 Aug 2005: Add support for tx checksum.
  99  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
 100  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 101  *      0.46: 20 Oct 2005: Add irq optimization modes.
 102  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 103  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 104  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 105  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 106  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 107  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 108  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 109  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 110  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 111  *
 112  * Known bugs:
 113  * We suspect that on some hardware no TX done interrupts are generated.
 114  * This means recovery from netif_stop_queue only happens if the hw timer
 115  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 116  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 117  * If your hardware reliably generates tx done interrupts, then you can remove
 118  * DEV_NEED_TIMERIRQ from the driver_data flags.
 119  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 120  * superfluous timer interrupts from the nic.
 121  */
 122 #define FORCEDETH_VERSION               "0.55"
 123 #define DRV_NAME                        "forcedeth"
 124
 125 #include <linux/module.h>
 126 #include <linux/types.h>
 127 #include <linux/pci.h>
 128 #include <linux/interrupt.h>
 129 #include <linux/netdevice.h>
 130 #include <linux/etherdevice.h>
 131 #include <linux/delay.h>
 132 #include <linux/spinlock.h>
 133 #include <linux/ethtool.h>
 134 #include <linux/timer.h>
 135 #include <linux/skbuff.h>
 136 #include <linux/mii.h>
 137 #include <linux/random.h>
 138 #include <linux/init.h>
 139 #include <linux/if_vlan.h>
 140 #include <linux/dma-mapping.h>
 141
 142 #include <asm/irq.h>
 143 #include <asm/io.h>
 144 #include <asm/uaccess.h>
 145 #include <asm/system.h>
 146
 147 #if 0
 148 #define dprintk                 printk
 149 #else
 150 #define dprintk(x...)           do { } while (0)
 151 #endif
 152
 153
 154 /*
 155  * Hardware access:
 156  */
 157
 158 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 159 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 160 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 161 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 162 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 163 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 164 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 165 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 166 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 167 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 168 #define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */
 169
 170 enum {
 171         NvRegIrqStatus = 0x000,
 172 #define NVREG_IRQSTAT_MIIEVENT  0x040
 173 #define NVREG_IRQSTAT_MASK              0x1ff
 174         NvRegIrqMask = 0x004,
 175 #define NVREG_IRQ_RX_ERROR              0x0001
 176 #define NVREG_IRQ_RX                    0x0002
 177 #define NVREG_IRQ_RX_NOBUF              0x0004
 178 #define NVREG_IRQ_TX_ERR                0x0008
 179 #define NVREG_IRQ_TX_OK                 0x0010
 180 #define NVREG_IRQ_TIMER                 0x0020
 181 #define NVREG_IRQ_LINK                  0x0040
 182 #define NVREG_IRQ_RX_FORCED             0x0080
 183 #define NVREG_IRQ_TX_FORCED             0x0100
 184 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 185 #define NVREG_IRQMASK_CPU               0x0040
 186 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 187 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 188 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
 189
 190 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 191                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 192                                         NVREG_IRQ_TX_FORCED))
 193
 194         NvRegUnknownSetupReg6 = 0x008,
 195 #define NVREG_UNKSETUP6_VAL             3
 196
 197 /*
 198  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 199  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 200  */
 201         NvRegPollingInterval = 0x00c,
 202 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
 203 #define NVREG_POLL_DEFAULT_CPU  13
 204         NvRegMSIMap0 = 0x020,
 205         NvRegMSIMap1 = 0x024,
 206         NvRegMSIIrqMask = 0x030,
 207 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 208         NvRegMisc1 = 0x080,
 209 #define NVREG_MISC1_PAUSE_TX    0x01
 210 #define NVREG_MISC1_HD          0x02
 211 #define NVREG_MISC1_FORCE       0x3b0f3c
 212
 213         NvRegMacReset = 0x3c,
 214 #define NVREG_MAC_RESET_ASSERT  0x0F3
 215         NvRegTransmitterControl = 0x084,
 216 #define NVREG_XMITCTL_START     0x01
 217         NvRegTransmitterStatus = 0x088,
 218 #define NVREG_XMITSTAT_BUSY     0x01
 219
 220         NvRegPacketFilterFlags = 0x8c,
 221 #define NVREG_PFF_PAUSE_RX      0x08
 222 #define NVREG_PFF_ALWAYS        0x7F0000
 223 #define NVREG_PFF_PROMISC       0x80
 224 #define NVREG_PFF_MYADDR        0x20
 225
 226         NvRegOffloadConfig = 0x90,
 227 #define NVREG_OFFLOAD_HOMEPHY   0x601
 228 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 229         NvRegReceiverControl = 0x094,
 230 #define NVREG_RCVCTL_START      0x01
 231         NvRegReceiverStatus = 0x98,
 232 #define NVREG_RCVSTAT_BUSY      0x01
 233
 234         NvRegRandomSeed = 0x9c,
 235 #define NVREG_RNDSEED_MASK      0x00ff
 236 #define NVREG_RNDSEED_FORCE     0x7f00
 237 #define NVREG_RNDSEED_FORCE2    0x2d00
 238 #define NVREG_RNDSEED_FORCE3    0x7400
 239
 240         NvRegUnknownSetupReg1 = 0xA0,
 241 #define NVREG_UNKSETUP1_VAL     0x16070f
 242         NvRegUnknownSetupReg2 = 0xA4,
 243 #define NVREG_UNKSETUP2_VAL     0x16
 244         NvRegMacAddrA = 0xA8,
 245         NvRegMacAddrB = 0xAC,
 246         NvRegMulticastAddrA = 0xB0,
 247 #define NVREG_MCASTADDRA_FORCE  0x01
 248         NvRegMulticastAddrB = 0xB4,
 249         NvRegMulticastMaskA = 0xB8,
 250         NvRegMulticastMaskB = 0xBC,
 251
 252         NvRegPhyInterface = 0xC0,
 253 #define PHY_RGMII               0x10000000
 254
 255         NvRegTxRingPhysAddr = 0x100,
 256         NvRegRxRingPhysAddr = 0x104,
 257         NvRegRingSizes = 0x108,
 258 #define NVREG_RINGSZ_TXSHIFT 0
 259 #define NVREG_RINGSZ_RXSHIFT 16
 260         NvRegUnknownTransmitterReg = 0x10c,
 261         NvRegLinkSpeed = 0x110,
 262 #define NVREG_LINKSPEED_FORCE 0x10000
 263 #define NVREG_LINKSPEED_10      1000
 264 #define NVREG_LINKSPEED_100     100
 265 #define NVREG_LINKSPEED_1000    50
 266 #define NVREG_LINKSPEED_MASK    (0xFFF)
 267         NvRegUnknownSetupReg5 = 0x130,
 268 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 269         NvRegUnknownSetupReg3 = 0x13c,
 270 #define NVREG_UNKSETUP3_VAL1    0x200010
 271         NvRegTxRxControl = 0x144,
 272 #define NVREG_TXRXCTL_KICK      0x0001
 273 #define NVREG_TXRXCTL_BIT1      0x0002
 274 #define NVREG_TXRXCTL_BIT2      0x0004
 275 #define NVREG_TXRXCTL_IDLE      0x0008
 276 #define NVREG_TXRXCTL_RESET     0x0010
 277 #define NVREG_TXRXCTL_RXCHECK   0x0400
 278 #define NVREG_TXRXCTL_DESC_1    0
 279 #define NVREG_TXRXCTL_DESC_2    0x02100
 280 #define NVREG_TXRXCTL_DESC_3    0x02200
 281 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 282 #define NVREG_TXRXCTL_VLANINS   0x00080
 283         NvRegTxRingPhysAddrHigh = 0x148,
 284         NvRegRxRingPhysAddrHigh = 0x14C,
 285         NvRegTxPauseFrame = 0x170,
 286 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 287 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 288         NvRegMIIStatus = 0x180,
 289 #define NVREG_MIISTAT_ERROR             0x0001
 290 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 291 #define NVREG_MIISTAT_MASK              0x000f
 292 #define NVREG_MIISTAT_MASK2             0x000f
 293         NvRegUnknownSetupReg4 = 0x184,
 294 #define NVREG_UNKSETUP4_VAL     8
 295
 296         NvRegAdapterControl = 0x188,
 297 #define NVREG_ADAPTCTL_START    0x02
 298 #define NVREG_ADAPTCTL_LINKUP   0x04
 299 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 300 #define NVREG_ADAPTCTL_RUNNING  0x100000
 301 #define NVREG_ADAPTCTL_PHYSHIFT 24
 302         NvRegMIISpeed = 0x18c,
 303 #define NVREG_MIISPEED_BIT8     (1<<8)
 304 #define NVREG_MIIDELAY  5
 305         NvRegMIIControl = 0x190,
 306 #define NVREG_MIICTL_INUSE      0x08000
 307 #define NVREG_MIICTL_WRITE      0x00400
 308 #define NVREG_MIICTL_ADDRSHIFT  5
 309         NvRegMIIData = 0x194,
 310         NvRegWakeUpFlags = 0x200,
 311 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 312 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 313 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 314 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 315 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 316 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 317 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 318 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 319 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 320 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 321 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 322
 323         NvRegPatternCRC = 0x204,
 324         NvRegPatternMask = 0x208,
 325         NvRegPowerCap = 0x268,
 326 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 327 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 328 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 329         NvRegPowerState = 0x26c,
 330 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 331 #define NVREG_POWERSTATE_VALID          0x0100
 332 #define NVREG_POWERSTATE_MASK           0x0003
 333 #define NVREG_POWERSTATE_D0             0x0000
 334 #define NVREG_POWERSTATE_D1             0x0001
 335 #define NVREG_POWERSTATE_D2             0x0002
 336 #define NVREG_POWERSTATE_D3             0x0003
 337         NvRegTxCnt = 0x280,
 338         NvRegTxZeroReXmt = 0x284,
 339         NvRegTxOneReXmt = 0x288,
 340         NvRegTxManyReXmt = 0x28c,
 341         NvRegTxLateCol = 0x290,
 342         NvRegTxUnderflow = 0x294,
 343         NvRegTxLossCarrier = 0x298,
 344         NvRegTxExcessDef = 0x29c,
 345         NvRegTxRetryErr = 0x2a0,
 346         NvRegRxFrameErr = 0x2a4,
 347         NvRegRxExtraByte = 0x2a8,
 348         NvRegRxLateCol = 0x2ac,
 349         NvRegRxRunt = 0x2b0,
 350         NvRegRxFrameTooLong = 0x2b4,
 351         NvRegRxOverflow = 0x2b8,
 352         NvRegRxFCSErr = 0x2bc,
 353         NvRegRxFrameAlignErr = 0x2c0,
 354         NvRegRxLenErr = 0x2c4,
 355         NvRegRxUnicast = 0x2c8,
 356         NvRegRxMulticast = 0x2cc,
 357         NvRegRxBroadcast = 0x2d0,
 358         NvRegTxDef = 0x2d4,
 359         NvRegTxFrame = 0x2d8,
 360         NvRegRxCnt = 0x2dc,
 361         NvRegTxPause = 0x2e0,
 362         NvRegRxPause = 0x2e4,
 363         NvRegRxDropFrame = 0x2e8,
 364         NvRegVlanControl = 0x300,
 365 #define NVREG_VLANCONTROL_ENABLE        0x2000
 366         NvRegMSIXMap0 = 0x3e0,
 367         NvRegMSIXMap1 = 0x3e4,
 368         NvRegMSIXIrqStatus = 0x3f0,
 369
 370         NvRegPowerState2 = 0x600,
 371 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 372 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 373 };
 374
 375 /* Big endian: should work, but is untested */
 376 struct ring_desc {
 377         u32 PacketBuffer;
 378         u32 FlagLen;
 379 };
 380
 381 struct ring_desc_ex {
 382         u32 PacketBufferHigh;
 383         u32 PacketBufferLow;
 384         u32 TxVlan;
 385         u32 FlagLen;
 386 };
 387
 388 typedef union _ring_type {
 389         struct ring_desc* orig;
 390         struct ring_desc_ex* ex;
 391 } ring_type;
 392
 393 #define FLAG_MASK_V1 0xffff0000
 394 #define FLAG_MASK_V2 0xffffc000
 395 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 396 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 397
 398 #define NV_TX_LASTPACKET        (1<<16)
 399 #define NV_TX_RETRYERROR        (1<<19)
 400 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 401 #define NV_TX_DEFERRED          (1<<26)
 402 #define NV_TX_CARRIERLOST       (1<<27)
 403 #define NV_TX_LATECOLLISION     (1<<28)
 404 #define NV_TX_UNDERFLOW         (1<<29)
 405 #define NV_TX_ERROR             (1<<30)
 406 #define NV_TX_VALID             (1<<31)
 407
 408 #define NV_TX2_LASTPACKET       (1<<29)
 409 #define NV_TX2_RETRYERROR       (1<<18)
 410 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 411 #define NV_TX2_DEFERRED         (1<<25)
 412 #define NV_TX2_CARRIERLOST      (1<<26)
 413 #define NV_TX2_LATECOLLISION    (1<<27)
 414 #define NV_TX2_UNDERFLOW        (1<<28)
 415 /* error and valid are the same for both */
 416 #define NV_TX2_ERROR            (1<<30)
 417 #define NV_TX2_VALID            (1<<31)
 418 #define NV_TX2_TSO              (1<<28)
 419 #define NV_TX2_TSO_SHIFT        14
 420 #define NV_TX2_TSO_MAX_SHIFT    14
 421 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 422 #define NV_TX2_CHECKSUM_L3      (1<<27)
 423 #define NV_TX2_CHECKSUM_L4      (1<<26)
 424
 425 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 426
 427 #define NV_RX_DESCRIPTORVALID   (1<<16)
 428 #define NV_RX_MISSEDFRAME       (1<<17)
 429 #define NV_RX_SUBSTRACT1        (1<<18)
 430 #define NV_RX_ERROR1            (1<<23)
 431 #define NV_RX_ERROR2            (1<<24)
 432 #define NV_RX_ERROR3            (1<<25)
 433 #define NV_RX_ERROR4            (1<<26)
 434 #define NV_RX_CRCERR            (1<<27)
 435 #define NV_RX_OVERFLOW          (1<<28)
 436 #define NV_RX_FRAMINGERR        (1<<29)
 437 #define NV_RX_ERROR             (1<<30)
 438 #define NV_RX_AVAIL             (1<<31)
 439
 440 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 441 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 442 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 443 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 444 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 445 #define NV_RX2_SUBSTRACT1       (1<<25)
 446 #define NV_RX2_ERROR1           (1<<18)
 447 #define NV_RX2_ERROR2           (1<<19)
 448 #define NV_RX2_ERROR3           (1<<20)
 449 #define NV_RX2_ERROR4           (1<<21)
 450 #define NV_RX2_CRCERR           (1<<22)
 451 #define NV_RX2_OVERFLOW         (1<<23)
 452 #define NV_RX2_FRAMINGERR       (1<<24)
 453 /* error and avail are the same for both */
 454 #define NV_RX2_ERROR            (1<<30)
 455 #define NV_RX2_AVAIL            (1<<31)
 456
 457 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 458 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 459
 460 /* Miscelaneous hardware related defines: */
 461 #define NV_PCI_REGSZ_VER1       0x270
 462 #define NV_PCI_REGSZ_VER2       0x604
 463
 464 /* various timeout delays: all in usec */
 465 #define NV_TXRX_RESET_DELAY     4
 466 #define NV_TXSTOP_DELAY1        10
 467 #define NV_TXSTOP_DELAY1MAX     500000
 468 #define NV_TXSTOP_DELAY2        100
 469 #define NV_RXSTOP_DELAY1        10
 470 #define NV_RXSTOP_DELAY1MAX     500000
 471 #define NV_RXSTOP_DELAY2        100
 472 #define NV_SETUP5_DELAY         5
 473 #define NV_SETUP5_DELAYMAX      50000
 474 #define NV_POWERUP_DELAY        5
 475 #define NV_POWERUP_DELAYMAX     5000
 476 #define NV_MIIBUSY_DELAY        50
 477 #define NV_MIIPHY_DELAY 10
 478 #define NV_MIIPHY_DELAYMAX      10000
 479 #define NV_MAC_RESET_DELAY      64
 480
 481 #define NV_WAKEUPPATTERNS       5
 482 #define NV_WAKEUPMASKENTRIES    4
 483
 484 /* General driver defaults */
 485 #define NV_WATCHDOG_TIMEO       (5*HZ)
 486
 487 #define RX_RING_DEFAULT         128
 488 #define TX_RING_DEFAULT         256
 489 #define RX_RING_MIN             128
 490 #define TX_RING_MIN             64
 491 #define RING_MAX_DESC_VER_1     1024
 492 #define RING_MAX_DESC_VER_2_3   16384
 493 /*
 494  * Difference between the get and put pointers for the tx ring.
 495  * This is used to throttle the amount of data outstanding in the
 496  * tx ring.
 497  */
 498 #define TX_LIMIT_DIFFERENCE     1
 499
 500 /* rx/tx mac addr + type + vlan + align + slack*/
 501 #define NV_RX_HEADERS           (64)
 502 /* even more slack. */
 503 #define NV_RX_ALLOC_PAD         (64)
 504
 505 /* maximum mtu size */
 506 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 507 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 508
 509 #define OOM_REFILL      (1+HZ/20)
 510 #define POLL_WAIT       (1+HZ/100)
 511 #define LINK_TIMEOUT    (3*HZ)
 512 #define STATS_INTERVAL  (10*HZ)
 513
 514 /*
 515  * desc_ver values:
 516  * The nic supports three different descriptor types:
 517  * - DESC_VER_1: Original
 518  * - DESC_VER_2: support for jumbo frames.
 519  * - DESC_VER_3: 64-bit format.
 520  */
 521 #define DESC_VER_1      1
 522 #define DESC_VER_2      2
 523 #define DESC_VER_3      3
 524
 525 /* PHY defines */
 526 #define PHY_OUI_MARVELL 0x5043
 527 #define PHY_OUI_CICADA  0x03f1
 528 #define PHYID1_OUI_MASK 0x03ff
 529 #define PHYID1_OUI_SHFT 6
 530 #define PHYID2_OUI_MASK 0xfc00
 531 #define PHYID2_OUI_SHFT 10
 532 #define PHY_INIT1       0x0f000
 533 #define PHY_INIT2       0x0e00
 534 #define PHY_INIT3       0x01000
 535 #define PHY_INIT4       0x0200
 536 #define PHY_INIT5       0x0004
 537 #define PHY_INIT6       0x02000
 538 #define PHY_GIGABIT     0x0100
 539
 540 #define PHY_TIMEOUT     0x1
 541 #define PHY_ERROR       0x2
 542
 543 #define PHY_100 0x1
 544 #define PHY_1000        0x2
 545 #define PHY_HALF        0x100
 546
 547 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 548 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 549 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 550 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 551 #define NV_PAUSEFRAME_RX_REQ     0x0010
 552 #define NV_PAUSEFRAME_TX_REQ     0x0020
 553 #define NV_PAUSEFRAME_AUTONEG    0x0040
 554
 555 /* MSI/MSI-X defines */
 556 #define NV_MSI_X_MAX_VECTORS  8
 557 #define NV_MSI_X_VECTORS_MASK 0x000f
 558 #define NV_MSI_CAPABLE        0x0010
 559 #define NV_MSI_X_CAPABLE      0x0020
 560 #define NV_MSI_ENABLED        0x0040
 561 #define NV_MSI_X_ENABLED      0x0080
 562
 563 #define NV_MSI_X_VECTOR_ALL   0x0
 564 #define NV_MSI_X_VECTOR_RX    0x0
 565 #define NV_MSI_X_VECTOR_TX    0x1
 566 #define NV_MSI_X_VECTOR_OTHER 0x2
 567
 568 /* statistics */
 569 struct nv_ethtool_str {
 570         char name[ETH_GSTRING_LEN];
 571 };
 572
 573 static const struct nv_ethtool_str nv_estats_str[] = {
 574         { "tx_bytes" },
 575         { "tx_zero_rexmt" },
 576         { "tx_one_rexmt" },
 577         { "tx_many_rexmt" },
 578         { "tx_late_collision" },
 579         { "tx_fifo_errors" },
 580         { "tx_carrier_errors" },
 581         { "tx_excess_deferral" },
 582         { "tx_retry_error" },
 583         { "tx_deferral" },
 584         { "tx_packets" },
 585         { "tx_pause" },
 586         { "rx_frame_error" },
 587         { "rx_extra_byte" },
 588         { "rx_late_collision" },
 589         { "rx_runt" },
 590         { "rx_frame_too_long" },
 591         { "rx_over_errors" },
 592         { "rx_crc_errors" },
 593         { "rx_frame_align_error" },
 594         { "rx_length_error" },
 595         { "rx_unicast" },
 596         { "rx_multicast" },
 597         { "rx_broadcast" },
 598         { "rx_bytes" },
 599         { "rx_pause" },
 600         { "rx_drop_frame" },
 601         { "rx_packets" },
 602         { "rx_errors_total" }
 603 };
 604
 605 struct nv_ethtool_stats {
 606         u64 tx_bytes;
 607         u64 tx_zero_rexmt;
 608         u64 tx_one_rexmt;
 609         u64 tx_many_rexmt;
 610         u64 tx_late_collision;
 611         u64 tx_fifo_errors;
 612         u64 tx_carrier_errors;
 613         u64 tx_excess_deferral;
 614         u64 tx_retry_error;
 615         u64 tx_deferral;
 616         u64 tx_packets;
 617         u64 tx_pause;
 618         u64 rx_frame_error;
 619         u64 rx_extra_byte;
 620         u64 rx_late_collision;
 621         u64 rx_runt;
 622         u64 rx_frame_too_long;
 623         u64 rx_over_errors;
 624         u64 rx_crc_errors;
 625         u64 rx_frame_align_error;
 626         u64 rx_length_error;
 627         u64 rx_unicast;
 628         u64 rx_multicast;
 629         u64 rx_broadcast;
 630         u64 rx_bytes;
 631         u64 rx_pause;
 632         u64 rx_drop_frame;
 633         u64 rx_packets;
 634         u64 rx_errors_total;
 635 };
 636
 637 /*
 638  * SMP locking:
 639  * All hardware access under dev->priv->lock, except the performance
 640  * critical parts:
 641  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 642  *      by the arch code for interrupts.
 643  * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
 644  *      needs dev->priv->lock :-(
 645  * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
 646  */
 647
 648 /* in dev: base, irq */
 649 struct fe_priv {
 650         spinlock_t lock;
 651
 652         /* General data:
 653          * Locking: spin_lock(&np->lock); */
 654         struct net_device_stats stats;
 655         struct nv_ethtool_stats estats;
 656         int in_shutdown;
 657         u32 linkspeed;
 658         int duplex;
 659         int autoneg;
 660         int fixed_mode;
 661         int phyaddr;
 662         int wolenabled;
 663         unsigned int phy_oui;
 664         u16 gigabit;
 665
 666         /* General data: RO fields */
 667         dma_addr_t ring_addr;
 668         struct pci_dev *pci_dev;
 669         u32 orig_mac[2];
 670         u32 irqmask;
 671         u32 desc_ver;
 672         u32 txrxctl_bits;
 673         u32 vlanctl_bits;
 674         u32 driver_data;
 675         u32 register_size;
 676
 677         void __iomem *base;
 678
 679         /* rx specific fields.
 680          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 681          */
 682         ring_type rx_ring;
 683         unsigned int cur_rx, refill_rx;
 684         struct sk_buff **rx_skbuff;
 685         dma_addr_t *rx_dma;
 686         unsigned int rx_buf_sz;
 687         unsigned int pkt_limit;
 688         struct timer_list oom_kick;
 689         struct timer_list nic_poll;
 690         struct timer_list stats_poll;
 691         u32 nic_poll_irq;
 692         int rx_ring_size;
 693
 694         /* media detection workaround.
 695          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 696          */
 697         int need_linktimer;
 698         unsigned long link_timeout;
 699         /*
 700          * tx specific fields.
 701          */
 702         ring_type tx_ring;
 703         unsigned int next_tx, nic_tx;
 704         struct sk_buff **tx_skbuff;
 705         dma_addr_t *tx_dma;
 706         unsigned int *tx_dma_len;
 707         u32 tx_flags;
 708         int tx_ring_size;
 709         int tx_limit_start;
 710         int tx_limit_stop;
 711
 712         /* vlan fields */
 713         struct vlan_group *vlangrp;
 714
 715         /* msi/msi-x fields */
 716         u32 msi_flags;
 717         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 718
 719         /* flow control */
 720         u32 pause_flags;
 721 };
 722
 723 /*
 724  * Maximum number of loops until we assume that a bit in the irq mask
 725  * is stuck. Overridable with module param.
 726  */
 727 static int max_interrupt_work = 5;
 728
 729 /*
 730  * Optimization can be either throuput mode or cpu mode
 731  *
 732  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 733  * CPU Mode: Interrupts are controlled by a timer.
 734  */
 735 #define NV_OPTIMIZATION_MODE_THROUGHPUT 0
 736 #define NV_OPTIMIZATION_MODE_CPU        1
 737 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 738
 739 /*
 740  * Poll interval for timer irq
 741  *
 742  * This interval determines how frequent an interrupt is generated.
 743  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 744  * Min = 0, and Max = 65535
 745  */
 746 static int poll_interval = -1;
 747
 748 /*
 749  * Disable MSI interrupts
 750  */
 751 static int disable_msi = 0;
 752
 753 /*
 754  * Disable MSIX interrupts
 755  */
 756 static int disable_msix = 0;
 757
 758 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 759 {
 760         return netdev_priv(dev);
 761 }
 762
 763 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 764 {
 765         return ((struct fe_priv *)netdev_priv(dev))->base;
 766 }
 767
 768 static inline void pci_push(u8 __iomem *base)
 769 {
 770         /* force out pending posted writes */
 771         readl(base);
 772 }
 773
 774 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 775 {
 776         return le32_to_cpu(prd->FlagLen)
 777                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 778 }
 779
 780 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 781 {
 782         return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
 783 }
 784
 785 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 786                                 int delay, int delaymax, const char *msg)
 787 {
 788         u8 __iomem *base = get_hwbase(dev);
 789
 790         pci_push(base);
 791         do {
 792                 udelay(delay);
 793                 delaymax -= delay;
 794                 if (delaymax < 0) {
 795                         if (msg)
 796                                 printk(msg);
 797                         return 1;
 798                 }
 799         } while ((readl(base + offset) & mask) != target);
 800         return 0;
 801 }
 802
 803 #define NV_SETUP_RX_RING 0x01
 804 #define NV_SETUP_TX_RING 0x02
 805
 806 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 807 {
 808         struct fe_priv *np = get_nvpriv(dev);
 809         u8 __iomem *base = get_hwbase(dev);
 810
 811         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 812                 if (rxtx_flags & NV_SETUP_RX_RING) {
 813                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 814                 }
 815                 if (rxtx_flags & NV_SETUP_TX_RING) {
 816                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 817                 }
 818         } else {
 819                 if (rxtx_flags & NV_SETUP_RX_RING) {
 820                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 821                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 822                 }
 823                 if (rxtx_flags & NV_SETUP_TX_RING) {
 824                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 825                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 826                 }
 827         }
 828 }
 829
 830 static void free_rings(struct net_device *dev)
 831 {
 832         struct fe_priv *np = get_nvpriv(dev);
 833
 834         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 835                 if(np->rx_ring.orig)
 836                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 837                                             np->rx_ring.orig, np->ring_addr);
 838         } else {
 839                 if (np->rx_ring.ex)
 840                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 841                                             np->rx_ring.ex, np->ring_addr);
 842         }
 843         if (np->rx_skbuff)
 844                 kfree(np->rx_skbuff);
 845         if (np->rx_dma)
 846                 kfree(np->rx_dma);
 847         if (np->tx_skbuff)
 848                 kfree(np->tx_skbuff);
 849         if (np->tx_dma)
 850                 kfree(np->tx_dma);
 851         if (np->tx_dma_len)
 852                 kfree(np->tx_dma_len);
 853 }
 854
 855 static int using_multi_irqs(struct net_device *dev)
 856 {
 857         struct fe_priv *np = get_nvpriv(dev);
 858
 859         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 860             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 861              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 862                 return 0;
 863         else
 864                 return 1;
 865 }
 866
 867 static void nv_enable_irq(struct net_device *dev)
 868 {
 869         struct fe_priv *np = get_nvpriv(dev);
 870
 871         if (!using_multi_irqs(dev)) {
 872                 if (np->msi_flags & NV_MSI_X_ENABLED)
 873                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 874                 else
 875                         enable_irq(dev->irq);
 876         } else {
 877                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 878                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 879                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 880         }
 881 }
 882
 883 static void nv_disable_irq(struct net_device *dev)
 884 {
 885         struct fe_priv *np = get_nvpriv(dev);
 886
 887         if (!using_multi_irqs(dev)) {
 888                 if (np->msi_flags & NV_MSI_X_ENABLED)
 889                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 890                 else
 891                         disable_irq(dev->irq);
 892         } else {
 893                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 894                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 895                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 896         }
 897 }
 898
 899 /* In MSIX mode, a write to irqmask behaves as XOR */
 900 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
 901 {
 902         u8 __iomem *base = get_hwbase(dev);
 903
 904         writel(mask, base + NvRegIrqMask);
 905 }
 906
 907 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
 908 {
 909         struct fe_priv *np = get_nvpriv(dev);
 910         u8 __iomem *base = get_hwbase(dev);
 911
 912         if (np->msi_flags & NV_MSI_X_ENABLED) {
 913                 writel(mask, base + NvRegIrqMask);
 914         } else {
 915                 if (np->msi_flags & NV_MSI_ENABLED)
 916                         writel(0, base + NvRegMSIIrqMask);
 917                 writel(0, base + NvRegIrqMask);
 918         }
 919 }
 920
 921 #define MII_READ        (-1)
 922 /* mii_rw: read/write a register on the PHY.
 923  *
 924  * Caller must guarantee serialization
 925  */
 926 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
 927 {
 928         u8 __iomem *base = get_hwbase(dev);
 929         u32 reg;
 930         int retval;
 931
 932         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
 933
 934         reg = readl(base + NvRegMIIControl);
 935         if (reg & NVREG_MIICTL_INUSE) {
 936                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
 937                 udelay(NV_MIIBUSY_DELAY);
 938         }
 939
 940         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
 941         if (value != MII_READ) {
 942                 writel(value, base + NvRegMIIData);
 943                 reg |= NVREG_MIICTL_WRITE;
 944         }
 945         writel(reg, base + NvRegMIIControl);
 946
 947         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
 948                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
 949                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
 950                                 dev->name, miireg, addr);
 951                 retval = -1;
 952         } else if (value != MII_READ) {
 953                 /* it was a write operation - fewer failures are detectable */
 954                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
 955                                 dev->name, value, miireg, addr);
 956                 retval = 0;
 957         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
 958                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
 959                                 dev->name, miireg, addr);
 960                 retval = -1;
 961         } else {
 962                 retval = readl(base + NvRegMIIData);
 963                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
 964                                 dev->name, miireg, addr, retval);
 965         }
 966
 967         return retval;
 968 }
 969
 970 static int phy_reset(struct net_device *dev)
 971 {
 972         struct fe_priv *np = netdev_priv(dev);
 973         u32 miicontrol;
 974         unsigned int tries = 0;
 975
 976         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 977         miicontrol |= BMCR_RESET;
 978         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
 979                 return -1;
 980         }
 981
 982         /* wait for 500ms */
 983         msleep(500);
 984
 985         /* must wait till reset is deasserted */
 986         while (miicontrol & BMCR_RESET) {
 987                 msleep(10);
 988                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 989                 /* FIXME: 100 tries seem excessive */
 990                 if (tries++ > 100)
 991                         return -1;
 992         }
 993         return 0;
 994 }
 995
 996 static int phy_init(struct net_device *dev)
 997 {
 998         struct fe_priv *np = get_nvpriv(dev);
 999         u8 __iomem *base = get_hwbase(dev);
1000         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1001
1002         /* set advertise register */
1003         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1004         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1005         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1006                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1007                 return PHY_ERROR;
1008         }
1009
1010         /* get phy interface type */
1011         phyinterface = readl(base + NvRegPhyInterface);
1012
1013         /* see if gigabit phy */
1014         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1015         if (mii_status & PHY_GIGABIT) {
1016                 np->gigabit = PHY_GIGABIT;
1017                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1018                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1019                 if (phyinterface & PHY_RGMII)
1020                         mii_control_1000 |= ADVERTISE_1000FULL;
1021                 else
1022                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1023
1024                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1025                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1026                         return PHY_ERROR;
1027                 }
1028         }
1029         else
1030                 np->gigabit = 0;
1031
1032         /* reset the phy */
1033         if (phy_reset(dev)) {
1034                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1035                 return PHY_ERROR;
1036         }
1037
1038         /* phy vendor specific configuration */
1039         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1040                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1041                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1042                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1043                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1044                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1045                         return PHY_ERROR;
1046                 }
1047                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1048                 phy_reserved |= PHY_INIT5;
1049                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1050                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1051                         return PHY_ERROR;
1052                 }
1053         }
1054         if (np->phy_oui == PHY_OUI_CICADA) {
1055                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1056                 phy_reserved |= PHY_INIT6;
1057                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1058                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1059                         return PHY_ERROR;
1060                 }
1061         }
1062         /* some phys clear out pause advertisment on reset, set it back */
1063         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1064
1065         /* restart auto negotiation */
1066         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1067         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1068         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1069                 return PHY_ERROR;
1070         }
1071
1072         return 0;
1073 }
1074
1075 static void nv_start_rx(struct net_device *dev)
1076 {
1077         struct fe_priv *np = netdev_priv(dev);
1078         u8 __iomem *base = get_hwbase(dev);
1079
1080         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1081         /* Already running? Stop it. */
1082         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
1083                 writel(0, base + NvRegReceiverControl);
1084                 pci_push(base);
1085         }
1086         writel(np->linkspeed, base + NvRegLinkSpeed);
1087         pci_push(base);
1088         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
1089         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1090                                 dev->name, np->duplex, np->linkspeed);
1091         pci_push(base);
1092 }
1093
1094 static void nv_stop_rx(struct net_device *dev)
1095 {
1096         u8 __iomem *base = get_hwbase(dev);
1097
1098         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1099         writel(0, base + NvRegReceiverControl);
1100         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1101                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1102                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1103
1104         udelay(NV_RXSTOP_DELAY2);
1105         writel(0, base + NvRegLinkSpeed);
1106 }
1107
1108 static void nv_start_tx(struct net_device *dev)
1109 {
1110         u8 __iomem *base = get_hwbase(dev);
1111
1112         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1113         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
1114         pci_push(base);
1115 }
1116
1117 static void nv_stop_tx(struct net_device *dev)
1118 {
1119         u8 __iomem *base = get_hwbase(dev);
1120
1121         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1122         writel(0, base + NvRegTransmitterControl);
1123         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1124                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1125                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1126
1127         udelay(NV_TXSTOP_DELAY2);
1128         writel(0, base + NvRegUnknownTransmitterReg);
1129 }
1130
1131 static void nv_txrx_reset(struct net_device *dev)
1132 {
1133         struct fe_priv *np = netdev_priv(dev);
1134         u8 __iomem *base = get_hwbase(dev);
1135
1136         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1137         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1138         pci_push(base);
1139         udelay(NV_TXRX_RESET_DELAY);
1140         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1141         pci_push(base);
1142 }
1143
1144 static void nv_mac_reset(struct net_device *dev)
1145 {
1146         struct fe_priv *np = netdev_priv(dev);
1147         u8 __iomem *base = get_hwbase(dev);
1148
1149         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1150         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1151         pci_push(base);
1152         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1153         pci_push(base);
1154         udelay(NV_MAC_RESET_DELAY);
1155         writel(0, base + NvRegMacReset);
1156         pci_push(base);
1157         udelay(NV_MAC_RESET_DELAY);
1158         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1159         pci_push(base);
1160 }
1161
1162 /*
1163  * nv_get_stats: dev->get_stats function
1164  * Get latest stats value from the nic.
1165  * Called with read_lock(&dev_base_lock) held for read -
1166  * only synchronized against unregister_netdevice.
1167  */
1168 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1169 {
1170         struct fe_priv *np = netdev_priv(dev);
1171
1172         /* It seems that the nic always generates interrupts and doesn't
1173          * accumulate errors internally. Thus the current values in np->stats
1174          * are already up to date.
1175          */
1176         return &np->stats;
1177 }
1178
1179 /*
1180  * nv_alloc_rx: fill rx ring entries.
1181  * Return 1 if the allocations for the skbs failed and the
1182  * rx engine is without Available descriptors
1183  */
1184 static int nv_alloc_rx(struct net_device *dev)
1185 {
1186         struct fe_priv *np = netdev_priv(dev);
1187         unsigned int refill_rx = np->refill_rx;
1188         int nr;
1189
1190         while (np->cur_rx != refill_rx) {
1191                 struct sk_buff *skb;
1192
1193                 nr = refill_rx % np->rx_ring_size;
1194                 if (np->rx_skbuff[nr] == NULL) {
1195
1196                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1197                         if (!skb)
1198                                 break;
1199
1200                         skb->dev = dev;
1201                         np->rx_skbuff[nr] = skb;
1202                 } else {
1203                         skb = np->rx_skbuff[nr];
1204                 }
1205                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1206                                         skb->end-skb->data, PCI_DMA_FROMDEVICE);
1207                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1208                         np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
1209                         wmb();
1210                         np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1211                 } else {
1212                         np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1213                         np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1214                         wmb();
1215                         np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1216                 }
1217                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1218                                         dev->name, refill_rx);
1219                 refill_rx++;
1220         }
1221         np->refill_rx = refill_rx;
1222         if (np->cur_rx - refill_rx == np->rx_ring_size)
1223                 return 1;
1224         return 0;
1225 }
1226
1227 static void nv_do_rx_refill(unsigned long data)
1228 {
1229         struct net_device *dev = (struct net_device *) data;
1230         struct fe_priv *np = netdev_priv(dev);
1231
1232         if (!using_multi_irqs(dev)) {
1233                 if (np->msi_flags & NV_MSI_X_ENABLED)
1234                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1235                 else
1236                         disable_irq(dev->irq);
1237         } else {
1238                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1239         }
1240         if (nv_alloc_rx(dev)) {
1241                 spin_lock_irq(&np->lock);
1242                 if (!np->in_shutdown)
1243                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1244                 spin_unlock_irq(&np->lock);
1245         }
1246         if (!using_multi_irqs(dev)) {
1247                 if (np->msi_flags & NV_MSI_X_ENABLED)
1248                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1249                 else
1250                         enable_irq(dev->irq);
1251         } else {
1252                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1253         }
1254 }
1255
1256 static void nv_init_rx(struct net_device *dev)
1257 {
1258         struct fe_priv *np = netdev_priv(dev);
1259         int i;
1260
1261         np->cur_rx = np->rx_ring_size;
1262         np->refill_rx = 0;
1263         for (i = 0; i < np->rx_ring_size; i++)
1264                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1265                         np->rx_ring.orig[i].FlagLen = 0;
1266                 else
1267                         np->rx_ring.ex[i].FlagLen = 0;
1268 }
1269
1270 static void nv_init_tx(struct net_device *dev)
1271 {
1272         struct fe_priv *np = netdev_priv(dev);
1273         int i;
1274
1275         np->next_tx = np->nic_tx = 0;
1276         for (i = 0; i < np->tx_ring_size; i++) {
1277                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1278                         np->tx_ring.orig[i].FlagLen = 0;
1279                 else
1280                         np->tx_ring.ex[i].FlagLen = 0;
1281                 np->tx_skbuff[i] = NULL;
1282                 np->tx_dma[i] = 0;
1283         }
1284 }
1285
1286 static int nv_init_ring(struct net_device *dev)
1287 {
1288         nv_init_tx(dev);
1289         nv_init_rx(dev);
1290         return nv_alloc_rx(dev);
1291 }
1292
1293 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1294 {
1295         struct fe_priv *np = netdev_priv(dev);
1296
1297         dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1298                 dev->name, skbnr);
1299
1300         if (np->tx_dma[skbnr]) {
1301                 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1302                                np->tx_dma_len[skbnr],
1303                                PCI_DMA_TODEVICE);
1304                 np->tx_dma[skbnr] = 0;
1305         }
1306
1307         if (np->tx_skbuff[skbnr]) {
1308                 dev_kfree_skb_any(np->tx_skbuff[skbnr]);
1309                 np->tx_skbuff[skbnr] = NULL;
1310                 return 1;
1311         } else {
1312                 return 0;
1313         }
1314 }
1315
1316 static void nv_drain_tx(struct net_device *dev)
1317 {
1318         struct fe_priv *np = netdev_priv(dev);
1319         unsigned int i;
1320
1321         for (i = 0; i < np->tx_ring_size; i++) {
1322                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1323                         np->tx_ring.orig[i].FlagLen = 0;
1324                 else
1325                         np->tx_ring.ex[i].FlagLen = 0;
1326                 if (nv_release_txskb(dev, i))
1327                         np->stats.tx_dropped++;
1328         }
1329 }
1330
1331 static void nv_drain_rx(struct net_device *dev)
1332 {
1333         struct fe_priv *np = netdev_priv(dev);
1334         int i;
1335         for (i = 0; i < np->rx_ring_size; i++) {
1336                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1337                         np->rx_ring.orig[i].FlagLen = 0;
1338                 else
1339                         np->rx_ring.ex[i].FlagLen = 0;
1340                 wmb();
1341                 if (np->rx_skbuff[i]) {
1342                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
1343                                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1344                                                 PCI_DMA_FROMDEVICE);
1345                         dev_kfree_skb(np->rx_skbuff[i]);
1346                         np->rx_skbuff[i] = NULL;
1347                 }
1348         }
1349 }
1350
1351 static void drain_ring(struct net_device *dev)
1352 {
1353         nv_drain_tx(dev);
1354         nv_drain_rx(dev);
1355 }
1356
1357 /*
1358  * nv_start_xmit: dev->hard_start_xmit function
1359  * Called with dev->xmit_lock held.
1360  */
1361 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1362 {
1363         struct fe_priv *np = netdev_priv(dev);
1364         u32 tx_flags = 0;
1365         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1366         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1367         unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1368         unsigned int start_nr = np->next_tx % np->tx_ring_size;
1369         unsigned int i;
1370         u32 offset = 0;
1371         u32 bcnt;
1372         u32 size = skb->len-skb->data_len;
1373         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1374         u32 tx_flags_vlan = 0;
1375
1376         /* add fragments to entries count */
1377         for (i = 0; i < fragments; i++) {
1378                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1379                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1380         }
1381
1382         spin_lock_irq(&np->lock);
1383
1384         if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
1385                 spin_unlock_irq(&np->lock);
1386                 netif_stop_queue(dev);
1387                 return NETDEV_TX_BUSY;
1388         }
1389
1390         /* setup the header buffer */
1391         do {
1392                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1393                 nr = (nr + 1) % np->tx_ring_size;
1394
1395                 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1396                                                 PCI_DMA_TODEVICE);
1397                 np->tx_dma_len[nr] = bcnt;
1398
1399                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1400                         np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1401                         np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1402                 } else {
1403                         np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1404                         np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1405                         np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1406                 }
1407                 tx_flags = np->tx_flags;
1408                 offset += bcnt;
1409                 size -= bcnt;
1410         } while(size);
1411
1412         /* setup the fragments */
1413         for (i = 0; i < fragments; i++) {
1414                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1415                 u32 size = frag->size;
1416                 offset = 0;
1417
1418                 do {
1419                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1420                         nr = (nr + 1) % np->tx_ring_size;
1421
1422                         np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1423                                                       PCI_DMA_TODEVICE);
1424                         np->tx_dma_len[nr] = bcnt;
1425
1426                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1427                                 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1428                                 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1429                         } else {
1430                                 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1431                                 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1432                                 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1433                         }
1434                         offset += bcnt;
1435                         size -= bcnt;
1436                 } while (size);
1437         }
1438
1439         /* set last fragment flag  */
1440         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1441                 np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1442         } else {
1443                 np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1444         }
1445
1446         np->tx_skbuff[nr] = skb;
1447
1448 #ifdef NETIF_F_TSO
1449         if (skb_shinfo(skb)->tso_size)
1450                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT);
1451         else
1452 #endif
1453         tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1454
1455         /* vlan tag */
1456         if (np->vlangrp && vlan_tx_tag_present(skb)) {
1457                 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1458         }
1459
1460         /* set tx flags */
1461         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1462                 np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1463         } else {
1464                 np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan);
1465                 np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1466         }
1467
1468         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1469                 dev->name, np->next_tx, entries, tx_flags_extra);
1470         {
1471                 int j;
1472                 for (j=0; j<64; j++) {
1473                         if ((j%16) == 0)
1474                                 dprintk("\n%03x:", j);
1475                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1476                 }
1477                 dprintk("\n");
1478         }
1479
1480         np->next_tx += entries;
1481
1482         dev->trans_start = jiffies;
1483         spin_unlock_irq(&np->lock);
1484         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1485         pci_push(get_hwbase(dev));
1486         return NETDEV_TX_OK;
1487 }
1488
1489 /*
1490  * nv_tx_done: check for completed packets, release the skbs.
1491  *
1492  * Caller must own np->lock.
1493  */
1494 static void nv_tx_done(struct net_device *dev)
1495 {
1496         struct fe_priv *np = netdev_priv(dev);
1497         u32 Flags;
1498         unsigned int i;
1499         struct sk_buff *skb;
1500
1501         while (np->nic_tx != np->next_tx) {
1502                 i = np->nic_tx % np->tx_ring_size;
1503
1504                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1505                         Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1506                 else
1507                         Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1508
1509                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1510                                         dev->name, np->nic_tx, Flags);
1511                 if (Flags & NV_TX_VALID)
1512                         break;
1513                 if (np->desc_ver == DESC_VER_1) {
1514                         if (Flags & NV_TX_LASTPACKET) {
1515                                 skb = np->tx_skbuff[i];
1516                                 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1517                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1518                                         if (Flags & NV_TX_UNDERFLOW)
1519                                                 np->stats.tx_fifo_errors++;
1520                                         if (Flags & NV_TX_CARRIERLOST)
1521                                                 np->stats.tx_carrier_errors++;
1522                                         np->stats.tx_errors++;
1523                                 } else {
1524                                         np->stats.tx_packets++;
1525                                         np->stats.tx_bytes += skb->len;
1526                                 }
1527                         }
1528                 } else {
1529                         if (Flags & NV_TX2_LASTPACKET) {
1530                                 skb = np->tx_skbuff[i];
1531                                 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1532                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1533                                         if (Flags & NV_TX2_UNDERFLOW)
1534                                                 np->stats.tx_fifo_errors++;
1535                                         if (Flags & NV_TX2_CARRIERLOST)
1536                                                 np->stats.tx_carrier_errors++;
1537                                         np->stats.tx_errors++;
1538                                 } else {
1539                                         np->stats.tx_packets++;
1540                                         np->stats.tx_bytes += skb->len;
1541                                 }
1542                         }
1543                 }
1544                 nv_release_txskb(dev, i);
1545                 np->nic_tx++;
1546         }
1547         if (np->next_tx - np->nic_tx < np->tx_limit_start)
1548                 netif_wake_queue(dev);
1549 }
1550
1551 /*
1552  * nv_tx_timeout: dev->tx_timeout function
1553  * Called with dev->xmit_lock held.
1554  */
1555 static void nv_tx_timeout(struct net_device *dev)
1556 {
1557         struct fe_priv *np = netdev_priv(dev);
1558         u8 __iomem *base = get_hwbase(dev);
1559         u32 status;
1560
1561         if (np->msi_flags & NV_MSI_X_ENABLED)
1562                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1563         else
1564                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1565
1566         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1567
1568         {
1569                 int i;
1570
1571                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1572                                 dev->name, (unsigned long)np->ring_addr,
1573                                 np->next_tx, np->nic_tx);
1574                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1575                 for (i=0;i<=np->register_size;i+= 32) {
1576                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1577                                         i,
1578                                         readl(base + i + 0), readl(base + i + 4),
1579                                         readl(base + i + 8), readl(base + i + 12),
1580                                         readl(base + i + 16), readl(base + i + 20),
1581                                         readl(base + i + 24), readl(base + i + 28));
1582                 }
1583                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1584                 for (i=0;i<np->tx_ring_size;i+= 4) {
1585                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1586                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1587                                        i,
1588                                        le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1589                                        le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1590                                        le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1591                                        le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1592                                        le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1593                                        le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1594                                        le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1595                                        le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1596                         } else {
1597                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1598                                        i,
1599                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1600                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1601                                        le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1602                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1603                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1604                                        le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1605                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1606                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1607                                        le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1608                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1609                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1610                                        le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1611                         }
1612                 }
1613         }
1614
1615         spin_lock_irq(&np->lock);
1616
1617         /* 1) stop tx engine */
1618         nv_stop_tx(dev);
1619
1620         /* 2) check that the packets were not sent already: */
1621         nv_tx_done(dev);
1622
1623         /* 3) if there are dead entries: clear everything */
1624         if (np->next_tx != np->nic_tx) {
1625                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1626                 nv_drain_tx(dev);
1627                 np->next_tx = np->nic_tx = 0;
1628                 setup_hw_rings(dev, NV_SETUP_TX_RING);
1629                 netif_wake_queue(dev);
1630         }
1631
1632         /* 4) restart tx engine */
1633         nv_start_tx(dev);
1634         spin_unlock_irq(&np->lock);
1635 }
1636
1637 /*
1638  * Called when the nic notices a mismatch between the actual data len on the
1639  * wire and the len indicated in the 802 header
1640  */
1641 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1642 {
1643         int hdrlen;     /* length of the 802 header */
1644         int protolen;   /* length as stored in the proto field */
1645
1646         /* 1) calculate len according to header */
1647         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1648                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1649                 hdrlen = VLAN_HLEN;
1650         } else {
1651                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1652                 hdrlen = ETH_HLEN;
1653         }
1654         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1655                                 dev->name, datalen, protolen, hdrlen);
1656         if (protolen > ETH_DATA_LEN)
1657                 return datalen; /* Value in proto field not a len, no checks possible */
1658
1659         protolen += hdrlen;
1660         /* consistency checks: */
1661         if (datalen > ETH_ZLEN) {
1662                 if (datalen >= protolen) {
1663                         /* more data on wire than in 802 header, trim of
1664                          * additional data.
1665                          */
1666                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1667                                         dev->name, protolen);
1668                         return protolen;
1669                 } else {
1670                         /* less data on wire than mentioned in header.
1671                          * Discard the packet.
1672                          */
1673                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1674                                         dev->name);
1675                         return -1;
1676                 }
1677         } else {
1678                 /* short packet. Accept only if 802 values are also short */
1679                 if (protolen > ETH_ZLEN) {
1680                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1681                                         dev->name);
1682                         return -1;
1683                 }
1684                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1685                                 dev->name, datalen);
1686                 return datalen;
1687         }
1688 }
1689
1690 static void nv_rx_process(struct net_device *dev)
1691 {
1692         struct fe_priv *np = netdev_priv(dev);
1693         u32 Flags;
1694         u32 vlanflags = 0;
1695
1696         for (;;) {
1697                 struct sk_buff *skb;
1698                 int len;
1699                 int i;
1700                 if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1701                         break;  /* we scanned the whole ring - do not continue */
1702
1703                 i = np->cur_rx % np->rx_ring_size;
1704                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1705                         Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1706                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1707                 } else {
1708                         Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1709                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1710                         vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow);
1711                 }
1712
1713                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1714                                         dev->name, np->cur_rx, Flags);
1715
1716                 if (Flags & NV_RX_AVAIL)
1717                         break;  /* still owned by hardware, */
1718
1719                 /*
1720                  * the packet is for us - immediately tear down the pci mapping.
1721                  * TODO: check if a prefetch of the first cacheline improves
1722                  * the performance.
1723                  */
1724                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1725                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1726                                 PCI_DMA_FROMDEVICE);
1727
1728                 {
1729                         int j;
1730                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1731                         for (j=0; j<64; j++) {
1732                                 if ((j%16) == 0)
1733                                         dprintk("\n%03x:", j);
1734                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1735                         }
1736                         dprintk("\n");
1737                 }
1738                 /* look at what we actually got: */
1739                 if (np->desc_ver == DESC_VER_1) {
1740                         if (!(Flags & NV_RX_DESCRIPTORVALID))
1741                                 goto next_pkt;
1742
1743                         if (Flags & NV_RX_ERROR) {
1744                                 if (Flags & NV_RX_MISSEDFRAME) {
1745                                         np->stats.rx_missed_errors++;
1746                                         np->stats.rx_errors++;
1747                                         goto next_pkt;
1748                                 }
1749                                 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1750                                         np->stats.rx_errors++;
1751                                         goto next_pkt;
1752                                 }
1753                                 if (Flags & NV_RX_CRCERR) {
1754                                         np->stats.rx_crc_errors++;
1755                                         np->stats.rx_errors++;
1756                                         goto next_pkt;
1757                                 }
1758                                 if (Flags & NV_RX_OVERFLOW) {
1759                                         np->stats.rx_over_errors++;
1760                                         np->stats.rx_errors++;
1761                                         goto next_pkt;
1762                                 }
1763                                 if (Flags & NV_RX_ERROR4) {
1764                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1765                                         if (len < 0) {
1766                                                 np->stats.rx_errors++;
1767                                                 goto next_pkt;
1768                                         }
1769                                 }
1770                                 /* framing errors are soft errors. */
1771                                 if (Flags & NV_RX_FRAMINGERR) {
1772                                         if (Flags & NV_RX_SUBSTRACT1) {
1773                                                 len--;
1774                                         }
1775                                 }
1776                         }
1777                 } else {
1778                         if (!(Flags & NV_RX2_DESCRIPTORVALID))
1779                                 goto next_pkt;
1780
1781                         if (Flags & NV_RX2_ERROR) {
1782                                 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1783                                         np->stats.rx_errors++;
1784                                         goto next_pkt;
1785                                 }
1786                                 if (Flags & NV_RX2_CRCERR) {
1787                                         np->stats.rx_crc_errors++;
1788                                         np->stats.rx_errors++;
1789                                         goto next_pkt;
1790                                 }
1791                                 if (Flags & NV_RX2_OVERFLOW) {
1792                                         np->stats.rx_over_errors++;
1793                                         np->stats.rx_errors++;
1794                                         goto next_pkt;
1795                                 }
1796                                 if (Flags & NV_RX2_ERROR4) {
1797                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1798                                         if (len < 0) {
1799                                                 np->stats.rx_errors++;
1800                                                 goto next_pkt;
1801                                         }
1802                                 }
1803                                 /* framing errors are soft errors */
1804                                 if (Flags & NV_RX2_FRAMINGERR) {
1805                                         if (Flags & NV_RX2_SUBSTRACT1) {
1806                                                 len--;
1807                                         }
1808                                 }
1809                         }
1810                         if (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) {
1811                                 Flags &= NV_RX2_CHECKSUMMASK;
1812                                 if (Flags == NV_RX2_CHECKSUMOK1 ||
1813                                     Flags == NV_RX2_CHECKSUMOK2 ||
1814                                     Flags == NV_RX2_CHECKSUMOK3) {
1815                                         dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1816                                         np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1817                                 } else {
1818                                         dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1819                                 }
1820                         }
1821                 }
1822                 /* got a valid packet - forward it to the network core */
1823                 skb = np->rx_skbuff[i];
1824                 np->rx_skbuff[i] = NULL;
1825
1826                 skb_put(skb, len);
1827                 skb->protocol = eth_type_trans(skb, dev);
1828                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1829                                         dev->name, np->cur_rx, len, skb->protocol);
1830                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) {
1831                         vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK);
1832                 } else {
1833                         netif_rx(skb);
1834                 }
1835                 dev->last_rx = jiffies;
1836                 np->stats.rx_packets++;
1837                 np->stats.rx_bytes += len;
1838 next_pkt:
1839                 np->cur_rx++;
1840         }
1841 }
1842
1843 static void set_bufsize(struct net_device *dev)
1844 {
1845         struct fe_priv *np = netdev_priv(dev);
1846
1847         if (dev->mtu <= ETH_DATA_LEN)
1848                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1849         else
1850                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1851 }
1852
1853 /*
1854  * nv_change_mtu: dev->change_mtu function
1855  * Called with dev_base_lock held for read.
1856  */
1857 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1858 {
1859         struct fe_priv *np = netdev_priv(dev);
1860         int old_mtu;
1861
1862         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1863                 return -EINVAL;
1864
1865         old_mtu = dev->mtu;
1866         dev->mtu = new_mtu;
1867
1868         /* return early if the buffer sizes will not change */
1869         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1870                 return 0;
1871         if (old_mtu == new_mtu)
1872                 return 0;
1873
1874         /* synchronized against open : rtnl_lock() held by caller */
1875         if (netif_running(dev)) {
1876                 u8 __iomem *base = get_hwbase(dev);
1877                 /*
1878                  * It seems that the nic preloads valid ring entries into an
1879                  * internal buffer. The procedure for flushing everything is
1880                  * guessed, there is probably a simpler approach.
1881                  * Changing the MTU is a rare event, it shouldn't matter.
1882                  */
1883                 nv_disable_irq(dev);
1884                 spin_lock_bh(&dev->xmit_lock);
1885                 spin_lock(&np->lock);
1886                 /* stop engines */
1887                 nv_stop_rx(dev);
1888                 nv_stop_tx(dev);
1889                 nv_txrx_reset(dev);
1890                 /* drain rx queue */
1891                 nv_drain_rx(dev);
1892                 nv_drain_tx(dev);
1893                 /* reinit driver view of the rx queue */
1894                 set_bufsize(dev);
1895                 if (nv_init_ring(dev)) {
1896                         if (!np->in_shutdown)
1897                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1898                 }
1899                 /* reinit nic view of the rx queue */
1900                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1901                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
1902                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
1903                         base + NvRegRingSizes);
1904                 pci_push(base);
1905                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1906                 pci_push(base);
1907
1908                 /* restart rx engine */
1909                 nv_start_rx(dev);
1910                 nv_start_tx(dev);
1911                 spin_unlock(&np->lock);
1912                 spin_unlock_bh(&dev->xmit_lock);
1913                 nv_enable_irq(dev);
1914         }
1915         return 0;
1916 }
1917
1918 static void nv_copy_mac_to_hw(struct net_device *dev)
1919 {
1920         u8 __iomem *base = get_hwbase(dev);
1921         u32 mac[2];
1922
1923         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1924                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1925         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1926
1927         writel(mac[0], base + NvRegMacAddrA);
1928         writel(mac[1], base + NvRegMacAddrB);
1929 }
1930
1931 /*
1932  * nv_set_mac_address: dev->set_mac_address function
1933  * Called with rtnl_lock() held.
1934  */
1935 static int nv_set_mac_address(struct net_device *dev, void *addr)
1936 {
1937         struct fe_priv *np = netdev_priv(dev);
1938         struct sockaddr *macaddr = (struct sockaddr*)addr;
1939
1940         if(!is_valid_ether_addr(macaddr->sa_data))
1941                 return -EADDRNOTAVAIL;
1942
1943         /* synchronized against open : rtnl_lock() held by caller */
1944         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1945
1946         if (netif_running(dev)) {
1947                 spin_lock_bh(&dev->xmit_lock);
1948                 spin_lock_irq(&np->lock);
1949
1950                 /* stop rx engine */
1951                 nv_stop_rx(dev);
1952
1953                 /* set mac address */
1954                 nv_copy_mac_to_hw(dev);
1955
1956                 /* restart rx engine */
1957                 nv_start_rx(dev);
1958                 spin_unlock_irq(&np->lock);
1959                 spin_unlock_bh(&dev->xmit_lock);
1960         } else {
1961                 nv_copy_mac_to_hw(dev);
1962         }
1963         return 0;
1964 }
1965
1966 /*
1967  * nv_set_multicast: dev->set_multicast function
1968  * Called with dev->xmit_lock held.
1969  */
1970 static void nv_set_multicast(struct net_device *dev)
1971 {
1972         struct fe_priv *np = netdev_priv(dev);
1973         u8 __iomem *base = get_hwbase(dev);
1974         u32 addr[2];
1975         u32 mask[2];
1976         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
1977
1978         memset(addr, 0, sizeof(addr));
1979         memset(mask, 0, sizeof(mask));
1980
1981         if (dev->flags & IFF_PROMISC) {
1982                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1983                 pff |= NVREG_PFF_PROMISC;
1984         } else {
1985                 pff |= NVREG_PFF_MYADDR;
1986
1987                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1988                         u32 alwaysOff[2];
1989                         u32 alwaysOn[2];
1990
1991                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1992                         if (dev->flags & IFF_ALLMULTI) {
1993                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1994                         } else {
1995                                 struct dev_mc_list *walk;
1996
1997                                 walk = dev->mc_list;
1998                                 while (walk != NULL) {
1999                                         u32 a, b;
2000                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2001                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2002                                         alwaysOn[0] &= a;
2003                                         alwaysOff[0] &= ~a;
2004                                         alwaysOn[1] &= b;
2005                                         alwaysOff[1] &= ~b;
2006                                         walk = walk->next;
2007                                 }
2008                         }
2009                         addr[0] = alwaysOn[0];
2010                         addr[1] = alwaysOn[1];
2011                         mask[0] = alwaysOn[0] | alwaysOff[0];
2012                         mask[1] = alwaysOn[1] | alwaysOff[1];
2013                 }
2014         }
2015         addr[0] |= NVREG_MCASTADDRA_FORCE;
2016         pff |= NVREG_PFF_ALWAYS;
2017         spin_lock_irq(&np->lock);
2018         nv_stop_rx(dev);
2019         writel(addr[0], base + NvRegMulticastAddrA);
2020         writel(addr[1], base + NvRegMulticastAddrB);
2021         writel(mask[0], base + NvRegMulticastMaskA);
2022         writel(mask[1], base + NvRegMulticastMaskB);
2023         writel(pff, base + NvRegPacketFilterFlags);
2024         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2025                 dev->name);
2026         nv_start_rx(dev);
2027         spin_unlock_irq(&np->lock);
2028 }
2029
2030 void nv_update_pause(struct net_device *dev, u32 pause_flags)
2031 {
2032         struct fe_priv *np = netdev_priv(dev);
2033         u8 __iomem *base = get_hwbase(dev);
2034
2035         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2036
2037         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2038                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2039                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2040                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2041                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2042                 } else {
2043                         writel(pff, base + NvRegPacketFilterFlags);
2044                 }
2045         }
2046         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2047                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2048                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2049                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2050                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2051                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2052                 } else {
2053                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2054                         writel(regmisc, base + NvRegMisc1);
2055                 }
2056         }
2057 }
2058
2059 /**
2060  * nv_update_linkspeed: Setup the MAC according to the link partner
2061  * @dev: Network device to be configured
2062  *
2063  * The function queries the PHY and checks if there is a link partner.
2064  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2065  * set to 10 MBit HD.
2066  *
2067  * The function returns 0 if there is no link partner and 1 if there is
2068  * a good link partner.
2069  */
2070 static int nv_update_linkspeed(struct net_device *dev)
2071 {
2072         struct fe_priv *np = netdev_priv(dev);
2073         u8 __iomem *base = get_hwbase(dev);
2074         int adv = 0;
2075         int lpa = 0;
2076         int adv_lpa, adv_pause, lpa_pause;
2077         int newls = np->linkspeed;
2078         int newdup = np->duplex;
2079         int mii_status;
2080         int retval = 0;
2081         u32 control_1000, status_1000, phyreg, pause_flags;
2082
2083         /* BMSR_LSTATUS is latched, read it twice:
2084          * we want the current value.
2085          */
2086         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2087         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2088
2089         if (!(mii_status & BMSR_LSTATUS)) {
2090                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2091                                 dev->name);
2092                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2093                 newdup = 0;
2094                 retval = 0;
2095                 goto set_speed;
2096         }
2097
2098         if (np->autoneg == 0) {
2099                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2100                                 dev->name, np->fixed_mode);
2101                 if (np->fixed_mode & LPA_100FULL) {
2102                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2103                         newdup = 1;
2104                 } else if (np->fixed_mode & LPA_100HALF) {
2105                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2106                         newdup = 0;
2107                 } else if (np->fixed_mode & LPA_10FULL) {
2108                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2109                         newdup = 1;
2110                 } else {
2111                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2112                         newdup = 0;
2113                 }
2114                 retval = 1;
2115                 goto set_speed;
2116         }
2117         /* check auto negotiation is complete */
2118         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2119                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2120                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2121                 newdup = 0;
2122                 retval = 0;
2123                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2124                 goto set_speed;
2125         }
2126
2127         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2128         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2129         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2130                                 dev->name, adv, lpa);
2131
2132         retval = 1;
2133         if (np->gigabit == PHY_GIGABIT) {
2134                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2135                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2136
2137                 if ((control_1000 & ADVERTISE_1000FULL) &&
2138                         (status_1000 & LPA_1000FULL)) {
2139                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2140                                 dev->name);
2141                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2142                         newdup = 1;
2143                         goto set_speed;
2144                 }
2145         }
2146
2147         /* FIXME: handle parallel detection properly */
2148         adv_lpa = lpa & adv;
2149         if (adv_lpa & LPA_100FULL) {
2150                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2151                 newdup = 1;
2152         } else if (adv_lpa & LPA_100HALF) {
2153                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2154                 newdup = 0;
2155         } else if (adv_lpa & LPA_10FULL) {
2156                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2157                 newdup = 1;
2158         } else if (adv_lpa & LPA_10HALF) {
2159                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2160                 newdup = 0;
2161         } else {
2162                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2163                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2164                 newdup = 0;
2165         }
2166
2167 set_speed:
2168         if (np->duplex == newdup && np->linkspeed == newls)
2169                 return retval;
2170
2171         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2172                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2173
2174         np->duplex = newdup;
2175         np->linkspeed = newls;
2176
2177         if (np->gigabit == PHY_GIGABIT) {
2178                 phyreg = readl(base + NvRegRandomSeed);
2179                 phyreg &= ~(0x3FF00);
2180                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2181                         phyreg |= NVREG_RNDSEED_FORCE3;
2182                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2183                         phyreg |= NVREG_RNDSEED_FORCE2;
2184                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2185                         phyreg |= NVREG_RNDSEED_FORCE;
2186                 writel(phyreg, base + NvRegRandomSeed);
2187         }
2188
2189         phyreg = readl(base + NvRegPhyInterface);
2190         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2191         if (np->duplex == 0)
2192                 phyreg |= PHY_HALF;
2193         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2194                 phyreg |= PHY_100;
2195         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2196                 phyreg |= PHY_1000;
2197         writel(phyreg, base + NvRegPhyInterface);
2198
2199         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2200                 base + NvRegMisc1);
2201         pci_push(base);
2202         writel(np->linkspeed, base + NvRegLinkSpeed);
2203         pci_push(base);
2204
2205         pause_flags = 0;
2206         /* setup pause frame */
2207         if (np->duplex != 0) {
2208                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2209                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2210                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2211
2212                         switch (adv_pause) {
2213                         case (ADVERTISE_PAUSE_CAP):
2214                                 if (lpa_pause & LPA_PAUSE_CAP) {
2215                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2216                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2217                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2218                                 }
2219                                 break;
2220                         case (ADVERTISE_PAUSE_ASYM):
2221                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2222                                 {
2223                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2224                                 }
2225                                 break;
2226                         case (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM):
2227                                 if (lpa_pause & LPA_PAUSE_CAP)
2228                                 {
2229                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2230                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2231                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2232                                 }
2233                                 if (lpa_pause == LPA_PAUSE_ASYM)
2234                                 {
2235                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2236                                 }
2237                                 break;
2238                         }
2239                 } else {
2240                         pause_flags = np->pause_flags;
2241                 }
2242         }
2243         nv_update_pause(dev, pause_flags);
2244
2245         return retval;
2246 }
2247
2248 static void nv_linkchange(struct net_device *dev)
2249 {
2250         if (nv_update_linkspeed(dev)) {
2251                 if (!netif_carrier_ok(dev)) {
2252                         netif_carrier_on(dev);
2253                         printk(KERN_INFO "%s: link up.\n", dev->name);
2254                         nv_start_rx(dev);
2255                 }
2256         } else {
2257                 if (netif_carrier_ok(dev)) {
2258                         netif_carrier_off(dev);
2259                         printk(KERN_INFO "%s: link down.\n", dev->name);
2260                         nv_stop_rx(dev);
2261                 }
2262         }
2263 }
2264
2265 static void nv_link_irq(struct net_device *dev)
2266 {
2267         u8 __iomem *base = get_hwbase(dev);
2268         u32 miistat;
2269
2270         miistat = readl(base + NvRegMIIStatus);
2271         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2272         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2273
2274         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2275                 nv_linkchange(dev);
2276         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2277 }
2278
2279 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
2280 {
2281         struct net_device *dev = (struct net_device *) data;
2282         struct fe_priv *np = netdev_priv(dev);
2283         u8 __iomem *base = get_hwbase(dev);
2284         u32 events;
2285         int i;
2286
2287         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2288
2289         for (i=0; ; i++) {
2290                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2291                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2292                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2293                 } else {
2294                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2295                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2296                 }
2297                 pci_push(base);
2298                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2299                 if (!(events & np->irqmask))
2300                         break;
2301
2302                 spin_lock(&np->lock);
2303                 nv_tx_done(dev);
2304                 spin_unlock(&np->lock);
2305
2306                 nv_rx_process(dev);
2307                 if (nv_alloc_rx(dev)) {
2308                         spin_lock(&np->lock);
2309                         if (!np->in_shutdown)
2310                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2311                         spin_unlock(&np->lock);
2312                 }
2313
2314                 if (events & NVREG_IRQ_LINK) {
2315                         spin_lock(&np->lock);
2316                         nv_link_irq(dev);
2317                         spin_unlock(&np->lock);
2318                 }
2319                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2320                         spin_lock(&np->lock);
2321                         nv_linkchange(dev);
2322                         spin_unlock(&np->lock);
2323                         np->link_timeout = jiffies + LINK_TIMEOUT;
2324                 }
2325                 if (events & (NVREG_IRQ_TX_ERR)) {
2326                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2327                                                 dev->name, events);
2328                 }
2329                 if (events & (NVREG_IRQ_UNKNOWN)) {
2330                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2331                                                 dev->name, events);
2332                 }
2333                 if (i > max_interrupt_work) {
2334                         spin_lock(&np->lock);
2335                         /* disable interrupts on the nic */
2336                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2337                                 writel(0, base + NvRegIrqMask);
2338                         else
2339                                 writel(np->irqmask, base + NvRegIrqMask);
2340                         pci_push(base);
2341
2342                         if (!np->in_shutdown) {
2343                                 np->nic_poll_irq = np->irqmask;
2344                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2345                         }
2346                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2347                         spin_unlock(&np->lock);
2348                         break;
2349                 }
2350
2351         }
2352         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2353
2354         return IRQ_RETVAL(i);
2355 }
2356
2357 static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs)
2358 {
2359         struct net_device *dev = (struct net_device *) data;
2360         struct fe_priv *np = netdev_priv(dev);
2361         u8 __iomem *base = get_hwbase(dev);
2362         u32 events;
2363         int i;
2364
2365         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2366
2367         for (i=0; ; i++) {
2368                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2369                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2370                 pci_push(base);
2371                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2372                 if (!(events & np->irqmask))
2373                         break;
2374
2375                 spin_lock_irq(&np->lock);
2376                 nv_tx_done(dev);
2377                 spin_unlock_irq(&np->lock);
2378
2379                 if (events & (NVREG_IRQ_TX_ERR)) {
2380                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2381                                                 dev->name, events);
2382                 }
2383                 if (i > max_interrupt_work) {
2384                         spin_lock_irq(&np->lock);
2385                         /* disable interrupts on the nic */
2386                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2387                         pci_push(base);
2388
2389                         if (!np->in_shutdown) {
2390                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2391                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2392                         }
2393                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2394                         spin_unlock_irq(&np->lock);
2395                         break;
2396                 }
2397
2398         }
2399         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2400
2401         return IRQ_RETVAL(i);
2402 }
2403
2404 static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2405 {
2406         struct net_device *dev = (struct net_device *) data;
2407         struct fe_priv *np = netdev_priv(dev);
2408         u8 __iomem *base = get_hwbase(dev);
2409         u32 events;
2410         int i;
2411
2412         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2413
2414         for (i=0; ; i++) {
2415                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2416                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2417                 pci_push(base);
2418                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2419                 if (!(events & np->irqmask))
2420                         break;
2421
2422                 nv_rx_process(dev);
2423                 if (nv_alloc_rx(dev)) {
2424                         spin_lock_irq(&np->lock);
2425                         if (!np->in_shutdown)
2426                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2427                         spin_unlock_irq(&np->lock);
2428                 }
2429
2430                 if (i > max_interrupt_work) {
2431                         spin_lock_irq(&np->lock);
2432                         /* disable interrupts on the nic */
2433                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2434                         pci_push(base);
2435
2436                         if (!np->in_shutdown) {
2437                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2438                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2439                         }
2440                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2441                         spin_unlock_irq(&np->lock);
2442                         break;
2443                 }
2444
2445         }
2446         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2447
2448         return IRQ_RETVAL(i);
2449 }
2450
2451 static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
2452 {
2453         struct net_device *dev = (struct net_device *) data;
2454         struct fe_priv *np = netdev_priv(dev);
2455         u8 __iomem *base = get_hwbase(dev);
2456         u32 events;
2457         int i;
2458
2459         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2460
2461         for (i=0; ; i++) {
2462                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2463                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2464                 pci_push(base);
2465                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2466                 if (!(events & np->irqmask))
2467                         break;
2468
2469                 if (events & NVREG_IRQ_LINK) {
2470                         spin_lock_irq(&np->lock);
2471                         nv_link_irq(dev);
2472                         spin_unlock_irq(&np->lock);
2473                 }
2474                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2475                         spin_lock_irq(&np->lock);
2476                         nv_linkchange(dev);
2477                         spin_unlock_irq(&np->lock);
2478                         np->link_timeout = jiffies + LINK_TIMEOUT;
2479                 }
2480                 if (events & (NVREG_IRQ_UNKNOWN)) {
2481                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2482                                                 dev->name, events);
2483                 }
2484                 if (i > max_interrupt_work) {
2485                         spin_lock_irq(&np->lock);
2486                         /* disable interrupts on the nic */
2487                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2488                         pci_push(base);
2489
2490                         if (!np->in_shutdown) {
2491                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2492                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2493                         }
2494                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2495                         spin_unlock_irq(&np->lock);
2496                         break;
2497                 }
2498
2499         }
2500         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2501
2502         return IRQ_RETVAL(i);
2503 }
2504
2505 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2506 {
2507         u8 __iomem *base = get_hwbase(dev);
2508         int i;
2509         u32 msixmap = 0;
2510
2511         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2512          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2513          * the remaining 8 interrupts.
2514          */
2515         for (i = 0; i < 8; i++) {
2516                 if ((irqmask >> i) & 0x1) {
2517                         msixmap |= vector << (i << 2);
2518                 }
2519         }
2520         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2521
2522         msixmap = 0;
2523         for (i = 0; i < 8; i++) {
2524                 if ((irqmask >> (i + 8)) & 0x1) {
2525                         msixmap |= vector << (i << 2);
2526                 }
2527         }
2528         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2529 }
2530
2531 static int nv_request_irq(struct net_device *dev)
2532 {
2533         struct fe_priv *np = get_nvpriv(dev);
2534         u8 __iomem *base = get_hwbase(dev);
2535         int ret = 1;
2536         int i;
2537
2538         if (np->msi_flags & NV_MSI_X_CAPABLE) {
2539                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2540                         np->msi_x_entry[i].entry = i;
2541                 }
2542                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2543                         np->msi_flags |= NV_MSI_X_ENABLED;
2544                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
2545                                 /* Request irq for rx handling */
2546                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, SA_SHIRQ, dev->name, dev) != 0) {
2547                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2548                                         pci_disable_msix(np->pci_dev);
2549                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2550                                         goto out_err;
2551                                 }
2552                                 /* Request irq for tx handling */
2553                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, SA_SHIRQ, dev->name, dev) != 0) {
2554                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2555                                         pci_disable_msix(np->pci_dev);
2556                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2557                                         goto out_free_rx;
2558                                 }
2559                                 /* Request irq for link and timer handling */
2560                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, SA_SHIRQ, dev->name, dev) != 0) {
2561                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2562                                         pci_disable_msix(np->pci_dev);
2563                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2564                                         goto out_free_tx;
2565                                 }
2566                                 /* map interrupts to their respective vector */
2567                                 writel(0, base + NvRegMSIXMap0);
2568                                 writel(0, base + NvRegMSIXMap1);
2569                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2570                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2571                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2572                         } else {
2573                                 /* Request irq for all interrupts */
2574                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) {
2575                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2576                                         pci_disable_msix(np->pci_dev);
2577                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2578                                         goto out_err;
2579                                 }
2580
2581                                 /* map interrupts to vector 0 */
2582                                 writel(0, base + NvRegMSIXMap0);
2583                                 writel(0, base + NvRegMSIXMap1);
2584                         }
2585                 }
2586         }
2587         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2588                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2589                         np->msi_flags |= NV_MSI_ENABLED;
2590                         if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) {
2591                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2592                                 pci_disable_msi(np->pci_dev);
2593                                 np->msi_flags &= ~NV_MSI_ENABLED;
2594                                 goto out_err;
2595                         }
2596
2597                         /* map interrupts to vector 0 */
2598                         writel(0, base + NvRegMSIMap0);
2599                         writel(0, base + NvRegMSIMap1);
2600                         /* enable msi vector 0 */
2601                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
2602                 }
2603         }
2604         if (ret != 0) {
2605                 if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0)
2606                         goto out_err;
2607         }
2608
2609         return 0;
2610 out_free_tx:
2611         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
2612 out_free_rx:
2613         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
2614 out_err:
2615         return 1;
2616 }
2617
2618 static void nv_free_irq(struct net_device *dev)
2619 {
2620         struct fe_priv *np = get_nvpriv(dev);
2621         int i;
2622
2623         if (np->msi_flags & NV_MSI_X_ENABLED) {
2624                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2625                         free_irq(np->msi_x_entry[i].vector, dev);
2626                 }
2627                 pci_disable_msix(np->pci_dev);
2628                 np->msi_flags &= ~NV_MSI_X_ENABLED;
2629         } else {
2630                 free_irq(np->pci_dev->irq, dev);
2631                 if (np->msi_flags & NV_MSI_ENABLED) {
2632                         pci_disable_msi(np->pci_dev);
2633                         np->msi_flags &= ~NV_MSI_ENABLED;
2634                 }
2635         }
2636 }
2637
2638 static void nv_do_nic_poll(unsigned long data)
2639 {
2640         struct net_device *dev = (struct net_device *) data;
2641         struct fe_priv *np = netdev_priv(dev);
2642         u8 __iomem *base = get_hwbase(dev);
2643         u32 mask = 0;
2644
2645         /*
2646          * First disable irq(s) and then
2647          * reenable interrupts on the nic, we have to do this before calling
2648          * nv_nic_irq because that may decide to do otherwise
2649          */
2650
2651         if (!using_multi_irqs(dev)) {
2652                 if (np->msi_flags & NV_MSI_X_ENABLED)
2653                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2654                 else
2655                         disable_irq(dev->irq);
2656                 mask = np->irqmask;
2657         } else {
2658                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2659                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2660                         mask |= NVREG_IRQ_RX_ALL;
2661                 }
2662                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2663                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2664                         mask |= NVREG_IRQ_TX_ALL;
2665                 }
2666                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2667                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2668                         mask |= NVREG_IRQ_OTHER;
2669                 }
2670         }
2671         np->nic_poll_irq = 0;
2672
2673         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2674
2675         writel(mask, base + NvRegIrqMask);
2676         pci_push(base);
2677
2678         if (!using_multi_irqs(dev)) {
2679                 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
2680                 if (np->msi_flags & NV_MSI_X_ENABLED)
2681                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2682                 else
2683                         enable_irq(dev->irq);
2684         } else {
2685                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2686                         nv_nic_irq_rx((int) 0, (void *) data, (struct pt_regs *) NULL);
2687                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2688                 }
2689                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2690                         nv_nic_irq_tx((int) 0, (void *) data, (struct pt_regs *) NULL);
2691                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2692                 }
2693                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2694                         nv_nic_irq_other((int) 0, (void *) data, (struct pt_regs *) NULL);
2695                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2696                 }
2697         }
2698 }
2699
2700 #ifdef CONFIG_NET_POLL_CONTROLLER
2701 static void nv_poll_controller(struct net_device *dev)
2702 {
2703         nv_do_nic_poll((unsigned long) dev);
2704 }
2705 #endif
2706
2707 static void nv_do_stats_poll(unsigned long data)
2708 {
2709         struct net_device *dev = (struct net_device *) data;
2710         struct fe_priv *np = netdev_priv(dev);
2711         u8 __iomem *base = get_hwbase(dev);
2712
2713         np->estats.tx_bytes += readl(base + NvRegTxCnt);
2714         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
2715         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
2716         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
2717         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
2718         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
2719         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
2720         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
2721         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
2722         np->estats.tx_deferral += readl(base + NvRegTxDef);
2723         np->estats.tx_packets += readl(base + NvRegTxFrame);
2724         np->estats.tx_pause += readl(base + NvRegTxPause);
2725         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
2726         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
2727         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
2728         np->estats.rx_runt += readl(base + NvRegRxRunt);
2729         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
2730         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
2731         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
2732         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
2733         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
2734         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
2735         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
2736         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
2737         np->estats.rx_bytes += readl(base + NvRegRxCnt);
2738         np->estats.rx_pause += readl(base + NvRegRxPause);
2739         np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
2740         np->estats.rx_packets =
2741                 np->estats.rx_unicast +
2742                 np->estats.rx_multicast +
2743                 np->estats.rx_broadcast;
2744         np->estats.rx_errors_total =
2745                 np->estats.rx_crc_errors +
2746                 np->estats.rx_over_errors +
2747                 np->estats.rx_frame_error +
2748                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
2749                 np->estats.rx_late_collision +
2750                 np->estats.rx_runt +
2751                 np->estats.rx_frame_too_long;
2752
2753         if (!np->in_shutdown)
2754                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
2755 }
2756
2757 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2758 {
2759         struct fe_priv *np = netdev_priv(dev);
2760         strcpy(info->driver, "forcedeth");
2761         strcpy(info->version, FORCEDETH_VERSION);
2762         strcpy(info->bus_info, pci_name(np->pci_dev));
2763 }
2764
2765 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2766 {
2767         struct fe_priv *np = netdev_priv(dev);
2768         wolinfo->supported = WAKE_MAGIC;
2769
2770         spin_lock_irq(&np->lock);
2771         if (np->wolenabled)
2772                 wolinfo->wolopts = WAKE_MAGIC;
2773         spin_unlock_irq(&np->lock);
2774 }
2775
2776 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2777 {
2778         struct fe_priv *np = netdev_priv(dev);
2779         u8 __iomem *base = get_hwbase(dev);
2780         u32 flags = 0;
2781
2782         if (wolinfo->wolopts == 0) {
2783                 np->wolenabled = 0;
2784         } else if (wolinfo->wolopts & WAKE_MAGIC) {
2785                 np->wolenabled = 1;
2786                 flags = NVREG_WAKEUPFLAGS_ENABLE;
2787         }
2788         if (netif_running(dev)) {
2789                 spin_lock_irq(&np->lock);
2790                 writel(flags, base + NvRegWakeUpFlags);
2791                 spin_unlock_irq(&np->lock);
2792         }
2793         return 0;
2794 }
2795
2796 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2797 {
2798         struct fe_priv *np = netdev_priv(dev);
2799         int adv;
2800
2801         spin_lock_irq(&np->lock);
2802         ecmd->port = PORT_MII;
2803         if (!netif_running(dev)) {
2804                 /* We do not track link speed / duplex setting if the
2805                  * interface is disabled. Force a link check */
2806                 if (nv_update_linkspeed(dev)) {
2807                         if (!netif_carrier_ok(dev))
2808                                 netif_carrier_on(dev);
2809                 } else {
2810                         if (netif_carrier_ok(dev))
2811                                 netif_carrier_off(dev);
2812                 }
2813         }
2814
2815         if (netif_carrier_ok(dev)) {
2816                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
2817                 case NVREG_LINKSPEED_10:
2818                         ecmd->speed = SPEED_10;
2819                         break;
2820                 case NVREG_LINKSPEED_100:
2821                         ecmd->speed = SPEED_100;
2822                         break;
2823                 case NVREG_LINKSPEED_1000:
2824                         ecmd->speed = SPEED_1000;
2825                         break;
2826                 }
2827                 ecmd->duplex = DUPLEX_HALF;
2828                 if (np->duplex)
2829                         ecmd->duplex = DUPLEX_FULL;
2830         } else {
2831                 ecmd->speed = -1;
2832                 ecmd->duplex = -1;
2833         }
2834
2835         ecmd->autoneg = np->autoneg;
2836
2837         ecmd->advertising = ADVERTISED_MII;
2838         if (np->autoneg) {
2839                 ecmd->advertising |= ADVERTISED_Autoneg;
2840                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2841                 if (adv & ADVERTISE_10HALF)
2842                         ecmd->advertising |= ADVERTISED_10baseT_Half;
2843                 if (adv & ADVERTISE_10FULL)
2844                         ecmd->advertising |= ADVERTISED_10baseT_Full;
2845                 if (adv & ADVERTISE_100HALF)
2846                         ecmd->advertising |= ADVERTISED_100baseT_Half;
2847                 if (adv & ADVERTISE_100FULL)
2848                         ecmd->advertising |= ADVERTISED_100baseT_Full;
2849                 if (np->gigabit == PHY_GIGABIT) {
2850                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2851                         if (adv & ADVERTISE_1000FULL)
2852                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
2853                 }
2854         }
2855         ecmd->supported = (SUPPORTED_Autoneg |
2856                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2857                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2858                 SUPPORTED_MII);
2859         if (np->gigabit == PHY_GIGABIT)
2860                 ecmd->supported |= SUPPORTED_1000baseT_Full;
2861
2862         ecmd->phy_address = np->phyaddr;
2863         ecmd->transceiver = XCVR_EXTERNAL;
2864
2865         /* ignore maxtxpkt, maxrxpkt for now */
2866         spin_unlock_irq(&np->lock);
2867         return 0;
2868 }
2869
2870 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2871 {
2872         struct fe_priv *np = netdev_priv(dev);
2873
2874         if (ecmd->port != PORT_MII)
2875                 return -EINVAL;
2876         if (ecmd->transceiver != XCVR_EXTERNAL)
2877                 return -EINVAL;
2878         if (ecmd->phy_address != np->phyaddr) {
2879                 /* TODO: support switching between multiple phys. Should be
2880                  * trivial, but not enabled due to lack of test hardware. */
2881                 return -EINVAL;
2882         }
2883         if (ecmd->autoneg == AUTONEG_ENABLE) {
2884                 u32 mask;
2885
2886                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2887                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
2888                 if (np->gigabit == PHY_GIGABIT)
2889                         mask |= ADVERTISED_1000baseT_Full;
2890
2891                 if ((ecmd->advertising & mask) == 0)
2892                         return -EINVAL;
2893
2894         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2895                 /* Note: autonegotiation disable, speed 1000 intentionally
2896                  * forbidden - noone should need that. */
2897
2898                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2899                         return -EINVAL;
2900                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2901                         return -EINVAL;
2902         } else {
2903                 return -EINVAL;
2904         }
2905
2906         netif_carrier_off(dev);
2907         if (netif_running(dev)) {
2908                 nv_disable_irq(dev);
2909                 spin_lock_bh(&dev->xmit_lock);
2910                 spin_lock(&np->lock);
2911                 /* stop engines */
2912                 nv_stop_rx(dev);
2913                 nv_stop_tx(dev);
2914                 spin_unlock(&np->lock);
2915                 spin_unlock_bh(&dev->xmit_lock);
2916         }
2917
2918         if (ecmd->autoneg == AUTONEG_ENABLE) {
2919                 int adv, bmcr;
2920
2921                 np->autoneg = 1;
2922
2923                 /* advertise only what has been requested */
2924                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2925                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2926                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2927                         adv |= ADVERTISE_10HALF;
2928                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2929                         adv |= ADVERTISE_10FULL;
2930                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2931                         adv |= ADVERTISE_100HALF;
2932                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2933                         adv |= ADVERTISE_100FULL;
2934                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
2935                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2936                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2937                         adv |=  ADVERTISE_PAUSE_ASYM;
2938                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2939
2940                 if (np->gigabit == PHY_GIGABIT) {
2941                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2942                         adv &= ~ADVERTISE_1000FULL;
2943                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
2944                                 adv |= ADVERTISE_1000FULL;
2945                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
2946                 }
2947
2948                 if (netif_running(dev))
2949                         printk(KERN_INFO "%s: link down.\n", dev->name);
2950                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2951                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2952                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2953
2954         } else {
2955                 int adv, bmcr;
2956
2957                 np->autoneg = 0;
2958
2959                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2960                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2961                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
2962                         adv |= ADVERTISE_10HALF;
2963                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
2964                         adv |= ADVERTISE_10FULL;
2965                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
2966                         adv |= ADVERTISE_100HALF;
2967                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
2968                         adv |= ADVERTISE_100FULL;
2969                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
2970                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
2971                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2972                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2973                 }
2974                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
2975                         adv |=  ADVERTISE_PAUSE_ASYM;
2976                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2977                 }
2978                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2979                 np->fixed_mode = adv;
2980
2981                 if (np->gigabit == PHY_GIGABIT) {
2982                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2983                         adv &= ~ADVERTISE_1000FULL;
2984                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
2985                 }
2986
2987                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2988                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
2989                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
2990                         bmcr |= BMCR_FULLDPLX;
2991                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
2992                         bmcr |= BMCR_SPEED100;
2993                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2994                 if (np->phy_oui == PHY_OUI_MARVELL) {
2995                         /* reset the phy */
2996                         if (phy_reset(dev)) {
2997                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
2998                                 return -EINVAL;
2999                         }
3000                 } else if (netif_running(dev)) {
3001                         /* Wait a bit and then reconfigure the nic. */
3002                         udelay(10);
3003                         nv_linkchange(dev);
3004                 }
3005         }
3006
3007         if (netif_running(dev)) {
3008                 nv_start_rx(dev);
3009                 nv_start_tx(dev);
3010                 nv_enable_irq(dev);
3011         }
3012
3013         return 0;
3014 }
3015
3016 #define FORCEDETH_REGS_VER      1
3017
3018 static int nv_get_regs_len(struct net_device *dev)
3019 {
3020         struct fe_priv *np = netdev_priv(dev);
3021         return np->register_size;
3022 }
3023
3024 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3025 {
3026         struct fe_priv *np = netdev_priv(dev);
3027         u8 __iomem *base = get_hwbase(dev);
3028         u32 *rbuf = buf;
3029         int i;
3030
3031         regs->version = FORCEDETH_REGS_VER;
3032         spin_lock_irq(&np->lock);
3033         for (i = 0;i <= np->register_size/sizeof(u32); i++)
3034                 rbuf[i] = readl(base + i*sizeof(u32));
3035         spin_unlock_irq(&np->lock);
3036 }
3037
3038 static int nv_nway_reset(struct net_device *dev)
3039 {
3040         struct fe_priv *np = netdev_priv(dev);
3041         int ret;
3042
3043         if (np->autoneg) {
3044                 int bmcr;
3045
3046                 netif_carrier_off(dev);
3047                 if (netif_running(dev)) {
3048                         nv_disable_irq(dev);
3049                         spin_lock_bh(&dev->xmit_lock);
3050                         spin_lock(&np->lock);
3051                         /* stop engines */
3052                         nv_stop_rx(dev);
3053                         nv_stop_tx(dev);
3054                         spin_unlock(&np->lock);
3055                         spin_unlock_bh(&dev->xmit_lock);
3056                         printk(KERN_INFO "%s: link down.\n", dev->name);
3057                 }
3058
3059                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3060                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3061                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3062
3063                 if (netif_running(dev)) {
3064                         nv_start_rx(dev);
3065                         nv_start_tx(dev);
3066                         nv_enable_irq(dev);
3067                 }
3068                 ret = 0;
3069         } else {
3070                 ret = -EINVAL;
3071         }
3072
3073         return ret;
3074 }
3075
3076 static int nv_set_tso(struct net_device *dev, u32 value)
3077 {
3078         struct fe_priv *np = netdev_priv(dev);
3079
3080         if ((np->driver_data & DEV_HAS_CHECKSUM))
3081                 return ethtool_op_set_tso(dev, value);
3082         else
3083                 return -EOPNOTSUPP;
3084 }
3085
3086 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3087 {
3088         struct fe_priv *np = netdev_priv(dev);
3089
3090         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3091         ring->rx_mini_max_pending = 0;
3092         ring->rx_jumbo_max_pending = 0;
3093         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3094
3095         ring->rx_pending = np->rx_ring_size;
3096         ring->rx_mini_pending = 0;
3097         ring->rx_jumbo_pending = 0;
3098         ring->tx_pending = np->tx_ring_size;
3099 }
3100
3101 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3102 {
3103         struct fe_priv *np = netdev_priv(dev);
3104         u8 __iomem *base = get_hwbase(dev);
3105         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
3106         dma_addr_t ring_addr;
3107
3108         if (ring->rx_pending < RX_RING_MIN ||
3109             ring->tx_pending < TX_RING_MIN ||
3110             ring->rx_mini_pending != 0 ||
3111             ring->rx_jumbo_pending != 0 ||
3112             (np->desc_ver == DESC_VER_1 &&
3113              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3114               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3115             (np->desc_ver != DESC_VER_1 &&
3116              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3117               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3118                 return -EINVAL;
3119         }
3120
3121         /* allocate new rings */
3122         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3123                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3124                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3125                                             &ring_addr);
3126         } else {
3127                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3128                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3129                                             &ring_addr);
3130         }
3131         rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
3132         rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
3133         tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
3134         tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
3135         tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
3136         if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
3137                 /* fall back to old rings */
3138                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3139                         if(rxtx_ring)
3140                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3141                                                     rxtx_ring, ring_addr);
3142                 } else {
3143                         if (rxtx_ring)
3144                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3145                                                     rxtx_ring, ring_addr);
3146                 }
3147                 if (rx_skbuff)
3148                         kfree(rx_skbuff);
3149                 if (rx_dma)
3150                         kfree(rx_dma);
3151                 if (tx_skbuff)
3152                         kfree(tx_skbuff);
3153                 if (tx_dma)
3154                         kfree(tx_dma);
3155                 if (tx_dma_len)
3156                         kfree(tx_dma_len);
3157                 goto exit;
3158         }
3159
3160         if (netif_running(dev)) {
3161                 nv_disable_irq(dev);
3162                 spin_lock_bh(&dev->xmit_lock);
3163                 spin_lock(&np->lock);
3164                 /* stop engines */
3165                 nv_stop_rx(dev);
3166                 nv_stop_tx(dev);
3167                 nv_txrx_reset(dev);
3168                 /* drain queues */
3169                 nv_drain_rx(dev);
3170                 nv_drain_tx(dev);
3171                 /* delete queues */
3172                 free_rings(dev);
3173         }
3174
3175         /* set new values */
3176         np->rx_ring_size = ring->rx_pending;
3177         np->tx_ring_size = ring->tx_pending;
3178         np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
3179         np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
3180         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3181                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3182                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3183         } else {
3184                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3185                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3186         }
3187         np->rx_skbuff = (struct sk_buff**)rx_skbuff;
3188         np->rx_dma = (dma_addr_t*)rx_dma;
3189         np->tx_skbuff = (struct sk_buff**)tx_skbuff;
3190         np->tx_dma = (dma_addr_t*)tx_dma;
3191         np->tx_dma_len = (unsigned int*)tx_dma_len;
3192         np->ring_addr = ring_addr;
3193
3194         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3195         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3196         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3197         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3198         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3199
3200         if (netif_running(dev)) {
3201                 /* reinit driver view of the queues */
3202                 set_bufsize(dev);
3203                 if (nv_init_ring(dev)) {
3204                         if (!np->in_shutdown)
3205                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3206                 }
3207
3208                 /* reinit nic view of the queues */
3209                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3210                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3211                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3212                         base + NvRegRingSizes);
3213                 pci_push(base);
3214                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3215                 pci_push(base);
3216
3217                 /* restart engines */
3218                 nv_start_rx(dev);
3219                 nv_start_tx(dev);
3220                 spin_unlock(&np->lock);
3221                 spin_unlock_bh(&dev->xmit_lock);
3222                 nv_enable_irq(dev);
3223         }
3224         return 0;
3225 exit:
3226         return -ENOMEM;
3227 }
3228
3229 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3230 {
3231         struct fe_priv *np = netdev_priv(dev);
3232
3233         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3234         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3235         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3236 }
3237
3238 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3239 {
3240         struct fe_priv *np = netdev_priv(dev);
3241         int adv, bmcr;
3242
3243         if ((!np->autoneg && np->duplex == 0) ||
3244             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3245                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3246                        dev->name);
3247                 return -EINVAL;
3248         }
3249         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3250                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3251                 return -EINVAL;
3252         }
3253
3254         netif_carrier_off(dev);
3255         if (netif_running(dev)) {
3256                 nv_disable_irq(dev);
3257                 spin_lock_bh(&dev->xmit_lock);
3258                 spin_lock(&np->lock);
3259                 /* stop engines */
3260                 nv_stop_rx(dev);
3261                 nv_stop_tx(dev);
3262                 spin_unlock(&np->lock);
3263                 spin_unlock_bh(&dev->xmit_lock);
3264         }
3265
3266         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3267         if (pause->rx_pause)
3268                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3269         if (pause->tx_pause)
3270                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3271
3272         if (np->autoneg && pause->autoneg) {
3273                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3274
3275                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3276                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3277                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3278                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3279                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3280                         adv |=  ADVERTISE_PAUSE_ASYM;
3281                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3282
3283                 if (netif_running(dev))
3284                         printk(KERN_INFO "%s: link down.\n", dev->name);
3285                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3286                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3287                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3288         } else {
3289                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3290                 if (pause->rx_pause)
3291                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3292                 if (pause->tx_pause)
3293                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3294
3295                 if (!netif_running(dev))
3296                         nv_update_linkspeed(dev);
3297                 else
3298                         nv_update_pause(dev, np->pause_flags);
3299         }
3300
3301         if (netif_running(dev)) {
3302                 nv_start_rx(dev);
3303                 nv_start_tx(dev);
3304                 nv_enable_irq(dev);
3305         }
3306         return 0;
3307 }
3308
3309 static u32 nv_get_rx_csum(struct net_device *dev)
3310 {
3311         struct fe_priv *np = netdev_priv(dev);
3312         return (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) != 0;
3313 }
3314
3315 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3316 {
3317         struct fe_priv *np = netdev_priv(dev);
3318         u8 __iomem *base = get_hwbase(dev);
3319         int retcode = 0;
3320
3321         if (np->driver_data & DEV_HAS_CHECKSUM) {
3322
3323                 if (((np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && data) ||
3324                     (!(np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && !data)) {
3325                         /* already set or unset */
3326                         return 0;
3327                 }
3328
3329                 if (data) {
3330                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3331                 } else if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) {
3332                         np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3333                 } else {
3334                         printk(KERN_INFO "Can not disable rx checksum if vlan is enabled\n");
3335                         return -EINVAL;
3336                 }
3337
3338                 if (netif_running(dev)) {
3339                         spin_lock_irq(&np->lock);
3340                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3341                         spin_unlock_irq(&np->lock);
3342                 }
3343         } else {
3344                 return -EINVAL;
3345         }
3346
3347         return retcode;
3348 }
3349
3350 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3351 {
3352         struct fe_priv *np = netdev_priv(dev);
3353
3354         if (np->driver_data & DEV_HAS_CHECKSUM)
3355                 return ethtool_op_set_tx_hw_csum(dev, data);
3356         else
3357                 return -EOPNOTSUPP;
3358 }
3359
3360 static int nv_set_sg(struct net_device *dev, u32 data)
3361 {
3362         struct fe_priv *np = netdev_priv(dev);
3363
3364         if (np->driver_data & DEV_HAS_CHECKSUM)
3365                 return ethtool_op_set_sg(dev, data);
3366         else
3367                 return -EOPNOTSUPP;
3368 }
3369
3370 static int nv_get_stats_count(struct net_device *dev)
3371 {
3372         struct fe_priv *np = netdev_priv(dev);
3373
3374         if (np->driver_data & DEV_HAS_STATISTICS)
3375                 return (sizeof(struct nv_ethtool_stats)/sizeof(u64));
3376         else
3377                 return 0;
3378 }
3379
3380 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3381 {
3382         struct fe_priv *np = netdev_priv(dev);
3383
3384         /* update stats */
3385         nv_do_stats_poll((unsigned long)dev);
3386
3387         memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3388 }
3389
3390 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
3391 {
3392         switch (stringset) {
3393         case ETH_SS_STATS:
3394                 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
3395                 break;
3396         }
3397 }
3398
3399 static struct ethtool_ops ops = {
3400         .get_drvinfo = nv_get_drvinfo,
3401         .get_link = ethtool_op_get_link,
3402         .get_wol = nv_get_wol,
3403         .set_wol = nv_set_wol,
3404         .get_settings = nv_get_settings,
3405         .set_settings = nv_set_settings,
3406         .get_regs_len = nv_get_regs_len,
3407         .get_regs = nv_get_regs,
3408         .nway_reset = nv_nway_reset,
3409         .get_perm_addr = ethtool_op_get_perm_addr,
3410         .get_tso = ethtool_op_get_tso,
3411         .set_tso = nv_set_tso,
3412         .get_ringparam = nv_get_ringparam,
3413         .set_ringparam = nv_set_ringparam,
3414         .get_pauseparam = nv_get_pauseparam,
3415         .set_pauseparam = nv_set_pauseparam,
3416         .get_rx_csum = nv_get_rx_csum,
3417         .set_rx_csum = nv_set_rx_csum,
3418         .get_tx_csum = ethtool_op_get_tx_csum,
3419         .set_tx_csum = nv_set_tx_csum,
3420         .get_sg = ethtool_op_get_sg,
3421         .set_sg = nv_set_sg,
3422         .get_strings = nv_get_strings,
3423         .get_stats_count = nv_get_stats_count,
3424         .get_ethtool_stats = nv_get_ethtool_stats,
3425 };
3426
3427 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
3428 {
3429         struct fe_priv *np = get_nvpriv(dev);
3430
3431         spin_lock_irq(&np->lock);
3432
3433         /* save vlan group */
3434         np->vlangrp = grp;
3435
3436         if (grp) {
3437                 /* enable vlan on MAC */
3438                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
3439         } else {
3440                 /* disable vlan on MAC */
3441                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
3442                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
3443         }
3444
3445         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3446
3447         spin_unlock_irq(&np->lock);
3448 };
3449
3450 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
3451 {
3452         /* nothing to do */
3453 };
3454
3455 static int nv_open(struct net_device *dev)
3456 {
3457         struct fe_priv *np = netdev_priv(dev);
3458         u8 __iomem *base = get_hwbase(dev);
3459         int ret = 1;
3460         int oom, i;
3461
3462         dprintk(KERN_DEBUG "nv_open: begin\n");
3463
3464         /* 1) erase previous misconfiguration */
3465         if (np->driver_data & DEV_HAS_POWER_CNTRL)
3466                 nv_mac_reset(dev);
3467         /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
3468         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
3469         writel(0, base + NvRegMulticastAddrB);
3470         writel(0, base + NvRegMulticastMaskA);
3471         writel(0, base + NvRegMulticastMaskB);
3472         writel(0, base + NvRegPacketFilterFlags);
3473
3474         writel(0, base + NvRegTransmitterControl);
3475         writel(0, base + NvRegReceiverControl);
3476
3477         writel(0, base + NvRegAdapterControl);
3478
3479         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
3480                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3481
3482         /* 2) initialize descriptor rings */
3483         set_bufsize(dev);
3484         oom = nv_init_ring(dev);
3485
3486         writel(0, base + NvRegLinkSpeed);
3487         writel(0, base + NvRegUnknownTransmitterReg);
3488         nv_txrx_reset(dev);
3489         writel(0, base + NvRegUnknownSetupReg6);
3490
3491         np->in_shutdown = 0;
3492
3493         /* 3) set mac address */
3494         nv_copy_mac_to_hw(dev);
3495
3496         /* 4) give hw rings */
3497         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3498         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3499                 base + NvRegRingSizes);
3500
3501         /* 5) continue setup */
3502         writel(np->linkspeed, base + NvRegLinkSpeed);
3503         writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
3504         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3505         writel(np->vlanctl_bits, base + NvRegVlanControl);
3506         pci_push(base);
3507         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
3508         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
3509                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
3510                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
3511
3512         writel(0, base + NvRegUnknownSetupReg4);
3513         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3514         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3515
3516         /* 6) continue setup */
3517         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
3518         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
3519         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
3520         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3521
3522         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
3523         get_random_bytes(&i, sizeof(i));
3524         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
3525         writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
3526         writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
3527         if (poll_interval == -1) {
3528                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
3529                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
3530                 else
3531                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3532         }
3533         else
3534                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
3535         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3536         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
3537                         base + NvRegAdapterControl);
3538         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
3539         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
3540         if (np->wolenabled)
3541                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
3542
3543         i = readl(base + NvRegPowerState);
3544         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
3545                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
3546
3547         pci_push(base);
3548         udelay(10);
3549         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
3550
3551         nv_disable_hw_interrupts(dev, np->irqmask);
3552         pci_push(base);
3553         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3554         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3555         pci_push(base);
3556
3557         if (nv_request_irq(dev)) {
3558                 goto out_drain;
3559         }
3560
3561         /* ask for interrupts */
3562         nv_enable_hw_interrupts(dev, np->irqmask);
3563
3564         spin_lock_irq(&np->lock);
3565         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
3566         writel(0, base + NvRegMulticastAddrB);
3567         writel(0, base + NvRegMulticastMaskA);
3568         writel(0, base + NvRegMulticastMaskB);
3569         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
3570         /* One manual link speed update: Interrupts are enabled, future link
3571          * speed changes cause interrupts and are handled by nv_link_irq().
3572          */
3573         {
3574                 u32 miistat;
3575                 miistat = readl(base + NvRegMIIStatus);
3576                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
3577                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
3578         }
3579         /* set linkspeed to invalid value, thus force nv_update_linkspeed
3580          * to init hw */
3581         np->linkspeed = 0;
3582         ret = nv_update_linkspeed(dev);
3583         nv_start_rx(dev);
3584         nv_start_tx(dev);
3585         netif_start_queue(dev);
3586         if (ret) {
3587                 netif_carrier_on(dev);
3588         } else {
3589                 printk("%s: no link during initialization.\n", dev->name);
3590                 netif_carrier_off(dev);
3591         }
3592         if (oom)
3593                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3594
3595         /* start statistics timer */
3596         if (np->driver_data & DEV_HAS_STATISTICS)
3597                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3598
3599         spin_unlock_irq(&np->lock);
3600
3601         return 0;
3602 out_drain:
3603         drain_ring(dev);
3604         return ret;
3605 }
3606
3607 static int nv_close(struct net_device *dev)
3608 {
3609         struct fe_priv *np = netdev_priv(dev);
3610         u8 __iomem *base;
3611
3612         spin_lock_irq(&np->lock);
3613         np->in_shutdown = 1;
3614         spin_unlock_irq(&np->lock);
3615         synchronize_irq(dev->irq);
3616
3617         del_timer_sync(&np->oom_kick);
3618         del_timer_sync(&np->nic_poll);
3619         del_timer_sync(&np->stats_poll);
3620
3621         netif_stop_queue(dev);
3622         spin_lock_irq(&np->lock);
3623         nv_stop_tx(dev);
3624         nv_stop_rx(dev);
3625         nv_txrx_reset(dev);
3626
3627         /* disable interrupts on the nic or we will lock up */
3628         base = get_hwbase(dev);
3629         nv_disable_hw_interrupts(dev, np->irqmask);
3630         pci_push(base);
3631         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
3632
3633         spin_unlock_irq(&np->lock);
3634
3635         nv_free_irq(dev);
3636
3637         drain_ring(dev);
3638
3639         if (np->wolenabled)
3640                 nv_start_rx(dev);
3641
3642         /* special op: write back the misordered MAC address - otherwise
3643          * the next nv_probe would see a wrong address.
3644          */
3645         writel(np->orig_mac[0], base + NvRegMacAddrA);
3646         writel(np->orig_mac[1], base + NvRegMacAddrB);
3647
3648         /* FIXME: power down nic */
3649
3650         return 0;
3651 }
3652
3653 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
3654 {
3655         struct net_device *dev;
3656         struct fe_priv *np;
3657         unsigned long addr;
3658         u8 __iomem *base;
3659         int err, i;
3660         u32 powerstate;
3661
3662         dev = alloc_etherdev(sizeof(struct fe_priv));
3663         err = -ENOMEM;
3664         if (!dev)
3665                 goto out;
3666
3667         np = netdev_priv(dev);
3668         np->pci_dev = pci_dev;
3669         spin_lock_init(&np->lock);
3670         SET_MODULE_OWNER(dev);
3671         SET_NETDEV_DEV(dev, &pci_dev->dev);
3672
3673         init_timer(&np->oom_kick);
3674         np->oom_kick.data = (unsigned long) dev;
3675         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
3676         init_timer(&np->nic_poll);
3677         np->nic_poll.data = (unsigned long) dev;
3678         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
3679         init_timer(&np->stats_poll);
3680         np->stats_poll.data = (unsigned long) dev;
3681         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
3682
3683         err = pci_enable_device(pci_dev);
3684         if (err) {
3685                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
3686                                 err, pci_name(pci_dev));
3687                 goto out_free;
3688         }
3689
3690         pci_set_master(pci_dev);
3691
3692         err = pci_request_regions(pci_dev, DRV_NAME);
3693         if (err < 0)
3694                 goto out_disable;
3695
3696         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
3697                 np->register_size = NV_PCI_REGSZ_VER2;
3698         else
3699                 np->register_size = NV_PCI_REGSZ_VER1;
3700
3701         err = -EINVAL;
3702         addr = 0;
3703         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
3704                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
3705                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
3706                                 pci_resource_len(pci_dev, i),
3707                                 pci_resource_flags(pci_dev, i));
3708                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
3709                                 pci_resource_len(pci_dev, i) >= np->register_size) {
3710                         addr = pci_resource_start(pci_dev, i);
3711                         break;
3712                 }
3713         }
3714         if (i == DEVICE_COUNT_RESOURCE) {
3715                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
3716                                         pci_name(pci_dev));
3717                 goto out_relreg;
3718         }
3719
3720         /* copy of driver data */
3721         np->driver_data = id->driver_data;
3722
3723         /* handle different descriptor versions */
3724         if (id->driver_data & DEV_HAS_HIGH_DMA) {
3725                 /* packet format 3: supports 40-bit addressing */
3726                 np->desc_ver = DESC_VER_3;
3727                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
3728                 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
3729                         printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
3730                                         pci_name(pci_dev));
3731                 } else {
3732                         dev->features |= NETIF_F_HIGHDMA;
3733                         printk(KERN_INFO "forcedeth: using HIGHDMA\n");
3734                 }
3735                 if (pci_set_consistent_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
3736                         printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed for device %s.\n",
3737                                pci_name(pci_dev));
3738                 }
3739         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
3740                 /* packet format 2: supports jumbo frames */
3741                 np->desc_ver = DESC_VER_2;
3742                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
3743         } else {
3744                 /* original packet format */
3745                 np->desc_ver = DESC_VER_1;
3746                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
3747         }
3748
3749         np->pkt_limit = NV_PKTLIMIT_1;
3750         if (id->driver_data & DEV_HAS_LARGEDESC)
3751                 np->pkt_limit = NV_PKTLIMIT_2;
3752
3753         if (id->driver_data & DEV_HAS_CHECKSUM) {
3754                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3755                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
3756 #ifdef NETIF_F_TSO
3757                 dev->features |= NETIF_F_TSO;
3758 #endif
3759         }
3760
3761         np->vlanctl_bits = 0;
3762         if (id->driver_data & DEV_HAS_VLAN) {
3763                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
3764                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
3765                 dev->vlan_rx_register = nv_vlan_rx_register;
3766                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
3767         }
3768
3769         np->msi_flags = 0;
3770         if ((id->driver_data & DEV_HAS_MSI) && !disable_msi) {
3771                 np->msi_flags |= NV_MSI_CAPABLE;
3772         }
3773         if ((id->driver_data & DEV_HAS_MSI_X) && !disable_msix) {
3774                 np->msi_flags |= NV_MSI_X_CAPABLE;
3775         }
3776
3777         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
3778         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
3779                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
3780         }
3781
3782
3783         err = -ENOMEM;
3784         np->base = ioremap(addr, np->register_size);
3785         if (!np->base)
3786                 goto out_relreg;
3787         dev->base_addr = (unsigned long)np->base;
3788
3789         dev->irq = pci_dev->irq;
3790
3791         np->rx_ring_size = RX_RING_DEFAULT;
3792         np->tx_ring_size = TX_RING_DEFAULT;
3793         np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
3794         np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
3795
3796         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3797                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
3798                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
3799                                         &np->ring_addr);
3800                 if (!np->rx_ring.orig)
3801                         goto out_unmap;
3802                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3803         } else {
3804                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
3805                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
3806                                         &np->ring_addr);
3807                 if (!np->rx_ring.ex)
3808                         goto out_unmap;
3809                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3810         }
3811         np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
3812         np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
3813         np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
3814         np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
3815         np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
3816         if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
3817                 goto out_freering;
3818         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3819         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3820         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3821         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3822         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3823
3824         dev->open = nv_open;
3825         dev->stop = nv_close;
3826         dev->hard_start_xmit = nv_start_xmit;
3827         dev->get_stats = nv_get_stats;
3828         dev->change_mtu = nv_change_mtu;
3829         dev->set_mac_address = nv_set_mac_address;
3830         dev->set_multicast_list = nv_set_multicast;
3831 #ifdef CONFIG_NET_POLL_CONTROLLER
3832         dev->poll_controller = nv_poll_controller;
3833 #endif
3834         SET_ETHTOOL_OPS(dev, &ops);
3835         dev->tx_timeout = nv_tx_timeout;
3836         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
3837
3838         pci_set_drvdata(pci_dev, dev);
3839
3840         /* read the mac address */
3841         base = get_hwbase(dev);
3842         np->orig_mac[0] = readl(base + NvRegMacAddrA);
3843         np->orig_mac[1] = readl(base + NvRegMacAddrB);
3844
3845         dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
3846         dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
3847         dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
3848         dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
3849         dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
3850         dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
3851         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3852
3853         if (!is_valid_ether_addr(dev->perm_addr)) {
3854                 /*
3855                  * Bad mac address. At least one bios sets the mac address
3856                  * to 01:23:45:67:89:ab
3857                  */
3858                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
3859                         pci_name(pci_dev),
3860                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3861                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3862                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
3863                 dev->dev_addr[0] = 0x00;
3864                 dev->dev_addr[1] = 0x00;
3865                 dev->dev_addr[2] = 0x6c;
3866                 get_random_bytes(&dev->dev_addr[3], 3);
3867         }
3868
3869         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
3870                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3871                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3872
3873         /* disable WOL */
3874         writel(0, base + NvRegWakeUpFlags);
3875         np->wolenabled = 0;
3876
3877         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
3878                 u8 revision_id;
3879                 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
3880
3881                 /* take phy and nic out of low power mode */
3882                 powerstate = readl(base + NvRegPowerState2);
3883                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
3884                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
3885                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
3886                     revision_id >= 0xA3)
3887                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
3888                 writel(powerstate, base + NvRegPowerState2);
3889         }
3890
3891         if (np->desc_ver == DESC_VER_1) {
3892                 np->tx_flags = NV_TX_VALID;
3893         } else {
3894                 np->tx_flags = NV_TX2_VALID;
3895         }
3896         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
3897                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3898                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
3899                         np->msi_flags |= 0x0003;
3900         } else {
3901                 np->irqmask = NVREG_IRQMASK_CPU;
3902                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
3903                         np->msi_flags |= 0x0001;
3904         }
3905
3906         if (id->driver_data & DEV_NEED_TIMERIRQ)
3907                 np->irqmask |= NVREG_IRQ_TIMER;
3908         if (id->driver_data & DEV_NEED_LINKTIMER) {
3909                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
3910                 np->need_linktimer = 1;
3911                 np->link_timeout = jiffies + LINK_TIMEOUT;
3912         } else {
3913                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
3914                 np->need_linktimer = 0;
3915         }
3916
3917         /* find a suitable phy */
3918         for (i = 1; i <= 32; i++) {
3919                 int id1, id2;
3920                 int phyaddr = i & 0x1F;
3921
3922                 spin_lock_irq(&np->lock);
3923                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
3924                 spin_unlock_irq(&np->lock);
3925                 if (id1 < 0 || id1 == 0xffff)
3926                         continue;
3927                 spin_lock_irq(&np->lock);
3928                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
3929                 spin_unlock_irq(&np->lock);
3930                 if (id2 < 0 || id2 == 0xffff)
3931                         continue;
3932
3933                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
3934                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
3935                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
3936                         pci_name(pci_dev), id1, id2, phyaddr);
3937                 np->phyaddr = phyaddr;
3938                 np->phy_oui = id1 | id2;
3939                 break;
3940         }
3941         if (i == 33) {
3942                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
3943                        pci_name(pci_dev));
3944                 goto out_error;
3945         }
3946
3947         /* reset it */
3948         phy_init(dev);
3949
3950         /* set default link speed settings */
3951         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3952         np->duplex = 0;
3953         np->autoneg = 1;
3954
3955         err = register_netdev(dev);
3956         if (err) {
3957                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
3958                 goto out_error;
3959         }
3960         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
3961                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
3962                         pci_name(pci_dev));
3963
3964         return 0;
3965
3966 out_error:
3967         pci_set_drvdata(pci_dev, NULL);
3968 out_freering:
3969         free_rings(dev);
3970 out_unmap:
3971         iounmap(get_hwbase(dev));
3972 out_relreg:
3973         pci_release_regions(pci_dev);
3974 out_disable:
3975         pci_disable_device(pci_dev);
3976 out_free:
3977         free_netdev(dev);
3978 out:
3979         return err;
3980 }
3981
3982 static void __devexit nv_remove(struct pci_dev *pci_dev)
3983 {
3984         struct net_device *dev = pci_get_drvdata(pci_dev);
3985
3986         unregister_netdev(dev);
3987
3988         /* free all structures */
3989         free_rings(dev);
3990         iounmap(get_hwbase(dev));
3991         pci_release_regions(pci_dev);
3992         pci_disable_device(pci_dev);
3993         free_netdev(dev);
3994         pci_set_drvdata(pci_dev, NULL);
3995 }
3996
3997 static struct pci_device_id pci_tbl[] = {
3998         {       /* nForce Ethernet Controller */
3999                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4000                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4001         },
4002         {       /* nForce2 Ethernet Controller */
4003                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4004                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4005         },
4006         {       /* nForce3 Ethernet Controller */
4007                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4008                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4009         },
4010         {       /* nForce3 Ethernet Controller */
4011                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4012                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4013         },
4014         {       /* nForce3 Ethernet Controller */
4015                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4016                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4017         },
4018         {       /* nForce3 Ethernet Controller */
4019                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4020                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4021         },
4022         {       /* nForce3 Ethernet Controller */
4023                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4024                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4025         },
4026         {       /* CK804 Ethernet Controller */
4027                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4028                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4029         },
4030         {       /* CK804 Ethernet Controller */
4031                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4032                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4033         },
4034         {       /* MCP04 Ethernet Controller */
4035                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4036                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4037         },
4038         {       /* MCP04 Ethernet Controller */
4039                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4040                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4041         },
4042         {       /* MCP51 Ethernet Controller */
4043                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4044                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4045         },
4046         {       /* MCP51 Ethernet Controller */
4047                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4048                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4049         },
4050         {       /* MCP55 Ethernet Controller */
4051                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4052                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS,
4053         },
4054         {       /* MCP55 Ethernet Controller */
4055                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4056                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS,
4057         },
4058         {0,},
4059 };
4060
4061 static struct pci_driver driver = {
4062         .name = "forcedeth",
4063         .id_table = pci_tbl,
4064         .probe = nv_probe,
4065         .remove = __devexit_p(nv_remove),
4066 };
4067
4068
4069 static int __init init_nic(void)
4070 {
4071         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
4072         return pci_module_init(&driver);
4073 }
4074
4075 static void __exit exit_nic(void)
4076 {
4077         pci_unregister_driver(&driver);
4078 }
4079
4080 module_param(max_interrupt_work, int, 0);
4081 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
4082 module_param(optimization_mode, int, 0);
4083 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
4084 module_param(poll_interval, int, 0);
4085 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
4086 module_param(disable_msi, int, 0);
4087 MODULE_PARM_DESC(disable_msi, "Disable MSI interrupts by setting to 1.");
4088 module_param(disable_msix, int, 0);
4089 MODULE_PARM_DESC(disable_msix, "Disable MSIX interrupts by setting to 1.");
4090
4091 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4092 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4093 MODULE_LICENSE("GPL");
4094
4095 MODULE_DEVICE_TABLE(pci, pci_tbl);
4096
4097 module_init(init_nic);
4098 module_exit(exit_nic);