2 * Texas Instruments 3-Port Ethernet Switch Address Lookup Engine
4 * Copyright (C) 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/platform_device.h>
17 #include <linux/seq_file.h>
18 #include <linux/slab.h>
19 #include <linux/err.h>
21 #include <linux/stat.h>
22 #include <linux/sysfs.h>
26 #define BITMASK(bits) (BIT(bits) - 1)
27 #define ALE_ENTRY_BITS 68
28 #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
30 #define ALE_VERSION_MAJOR(rev) ((rev >> 8) & 0xff)
31 #define ALE_VERSION_MINOR(rev) (rev & 0xff)
34 #define ALE_IDVER 0x00
35 #define ALE_CONTROL 0x08
36 #define ALE_PRESCALE 0x10
37 #define ALE_UNKNOWNVLAN 0x18
38 #define ALE_TABLE_CONTROL 0x20
39 #define ALE_TABLE 0x34
40 #define ALE_PORTCTL 0x40
42 #define ALE_TABLE_WRITE BIT(31)
44 #define ALE_TYPE_FREE 0
45 #define ALE_TYPE_ADDR 1
46 #define ALE_TYPE_VLAN 2
47 #define ALE_TYPE_VLAN_ADDR 3
49 #define ALE_UCAST_PERSISTANT 0
50 #define ALE_UCAST_UNTOUCHED 1
51 #define ALE_UCAST_OUI 2
52 #define ALE_UCAST_TOUCHED 3
54 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
60 idx = 2 - idx; /* flip */
61 return (ale_entry[idx] >> start) & BITMASK(bits);
64 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
69 value &= BITMASK(bits);
72 idx = 2 - idx; /* flip */
73 ale_entry[idx] &= ~(BITMASK(bits) << start);
74 ale_entry[idx] |= (value << start);
77 #define DEFINE_ALE_FIELD(name, start, bits) \
78 static inline int cpsw_ale_get_##name(u32 *ale_entry) \
80 return cpsw_ale_get_field(ale_entry, start, bits); \
82 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
84 cpsw_ale_set_field(ale_entry, start, bits, value); \
87 DEFINE_ALE_FIELD(entry_type, 60, 2)
88 DEFINE_ALE_FIELD(vlan_id, 48, 12)
89 DEFINE_ALE_FIELD(mcast_state, 62, 2)
90 DEFINE_ALE_FIELD(port_mask, 66, 3)
91 DEFINE_ALE_FIELD(super, 65, 1)
92 DEFINE_ALE_FIELD(ucast_type, 62, 2)
93 DEFINE_ALE_FIELD(port_num, 66, 2)
94 DEFINE_ALE_FIELD(blocked, 65, 1)
95 DEFINE_ALE_FIELD(secure, 64, 1)
96 DEFINE_ALE_FIELD(vlan_untag_force, 24, 3)
97 DEFINE_ALE_FIELD(vlan_reg_mcast, 16, 3)
98 DEFINE_ALE_FIELD(vlan_unreg_mcast, 8, 3)
99 DEFINE_ALE_FIELD(vlan_member_list, 0, 3)
100 DEFINE_ALE_FIELD(mcast, 40, 1)
102 /* The MAC address field in the ALE entry cannot be macroized as above */
103 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
107 for (i = 0; i < 6; i++)
108 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
111 static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
115 for (i = 0; i < 6; i++)
116 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
119 static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry)
123 WARN_ON(idx > ale->params.ale_entries);
125 __raw_writel(idx, ale->params.ale_regs + ALE_TABLE_CONTROL);
127 for (i = 0; i < ALE_ENTRY_WORDS; i++)
128 ale_entry[i] = __raw_readl(ale->params.ale_regs +
134 static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry)
138 WARN_ON(idx > ale->params.ale_entries);
140 for (i = 0; i < ALE_ENTRY_WORDS; i++)
141 __raw_writel(ale_entry[i], ale->params.ale_regs +
144 __raw_writel(idx | ALE_TABLE_WRITE, ale->params.ale_regs +
150 static int cpsw_ale_match_addr(struct cpsw_ale *ale, u8 *addr)
152 u32 ale_entry[ALE_ENTRY_WORDS];
155 for (idx = 0; idx < ale->params.ale_entries; idx++) {
158 cpsw_ale_read(ale, idx, ale_entry);
159 type = cpsw_ale_get_entry_type(ale_entry);
160 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
162 cpsw_ale_get_addr(ale_entry, entry_addr);
163 if (memcmp(entry_addr, addr, 6) == 0)
169 static int cpsw_ale_match_free(struct cpsw_ale *ale)
171 u32 ale_entry[ALE_ENTRY_WORDS];
174 for (idx = 0; idx < ale->params.ale_entries; idx++) {
175 cpsw_ale_read(ale, idx, ale_entry);
176 type = cpsw_ale_get_entry_type(ale_entry);
177 if (type == ALE_TYPE_FREE)
183 static int cpsw_ale_find_ageable(struct cpsw_ale *ale)
185 u32 ale_entry[ALE_ENTRY_WORDS];
188 for (idx = 0; idx < ale->params.ale_entries; idx++) {
189 cpsw_ale_read(ale, idx, ale_entry);
190 type = cpsw_ale_get_entry_type(ale_entry);
191 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
193 if (cpsw_ale_get_mcast(ale_entry))
195 type = cpsw_ale_get_ucast_type(ale_entry);
196 if (type != ALE_UCAST_PERSISTANT &&
197 type != ALE_UCAST_OUI)
203 static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry,
208 mask = cpsw_ale_get_port_mask(ale_entry);
209 if ((mask & port_mask) == 0)
210 return; /* ports dont intersect, not interested */
213 /* free if only remaining port is host port */
214 if (mask == BIT(ale->params.ale_ports))
215 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
217 cpsw_ale_set_port_mask(ale_entry, mask);
220 static void cpsw_ale_flush_ucast(struct cpsw_ale *ale, u32 *ale_entry,
225 port = cpsw_ale_get_port_num(ale_entry);
226 if ((BIT(port) & port_mask) == 0)
227 return; /* ports dont intersect, not interested */
228 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
231 int cpsw_ale_flush(struct cpsw_ale *ale, int port_mask)
233 u32 ale_entry[ALE_ENTRY_WORDS];
236 for (idx = 0; idx < ale->params.ale_entries; idx++) {
237 cpsw_ale_read(ale, idx, ale_entry);
238 ret = cpsw_ale_get_entry_type(ale_entry);
239 if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
242 if (cpsw_ale_get_mcast(ale_entry))
243 cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
245 cpsw_ale_flush_ucast(ale, ale_entry, port_mask);
247 cpsw_ale_write(ale, idx, ale_entry);
252 int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port, int flags)
254 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
257 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
258 cpsw_ale_set_addr(ale_entry, addr);
259 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
260 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
261 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
262 cpsw_ale_set_port_num(ale_entry, port);
264 idx = cpsw_ale_match_addr(ale, addr);
266 idx = cpsw_ale_match_free(ale);
268 idx = cpsw_ale_find_ageable(ale);
272 cpsw_ale_write(ale, idx, ale_entry);
276 int cpsw_ale_del_ucast(struct cpsw_ale *ale, u8 *addr, int port)
278 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
281 idx = cpsw_ale_match_addr(ale, addr);
285 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
286 cpsw_ale_write(ale, idx, ale_entry);
290 int cpsw_ale_add_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask,
291 int super, int mcast_state)
293 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
296 idx = cpsw_ale_match_addr(ale, addr);
298 cpsw_ale_read(ale, idx, ale_entry);
300 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
301 cpsw_ale_set_addr(ale_entry, addr);
302 cpsw_ale_set_super(ale_entry, super);
303 cpsw_ale_set_mcast_state(ale_entry, mcast_state);
305 mask = cpsw_ale_get_port_mask(ale_entry);
307 cpsw_ale_set_port_mask(ale_entry, port_mask);
310 idx = cpsw_ale_match_free(ale);
312 idx = cpsw_ale_find_ageable(ale);
316 cpsw_ale_write(ale, idx, ale_entry);
320 int cpsw_ale_del_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask)
322 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
325 idx = cpsw_ale_match_addr(ale, addr);
329 cpsw_ale_read(ale, idx, ale_entry);
332 cpsw_ale_set_port_mask(ale_entry, port_mask);
334 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
336 cpsw_ale_write(ale, idx, ale_entry);
340 struct ale_control_info {
342 int offset, port_offset;
343 int shift, port_shift;
347 static const struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = {
350 .offset = ALE_CONTROL,
358 .offset = ALE_CONTROL,
366 .offset = ALE_CONTROL,
372 [ALE_VLAN_NOLEARN] = {
373 .name = "vlan_nolearn",
374 .offset = ALE_CONTROL,
380 [ALE_NO_PORT_VLAN] = {
381 .name = "no_port_vlan",
382 .offset = ALE_CONTROL,
390 .offset = ALE_CONTROL,
398 .offset = ALE_CONTROL,
404 [ALE_RATE_LIMIT_TX] = {
405 .name = "rate_limit_tx",
406 .offset = ALE_CONTROL,
413 .name = "vlan_aware",
414 .offset = ALE_CONTROL,
420 [ALE_AUTH_ENABLE] = {
421 .name = "auth_enable",
422 .offset = ALE_CONTROL,
429 .name = "rate_limit",
430 .offset = ALE_CONTROL,
437 .name = "port_state",
438 .offset = ALE_PORTCTL,
444 [ALE_PORT_DROP_UNTAGGED] = {
445 .name = "drop_untagged",
446 .offset = ALE_PORTCTL,
452 [ALE_PORT_DROP_UNKNOWN_VLAN] = {
453 .name = "drop_unknown",
454 .offset = ALE_PORTCTL,
460 [ALE_PORT_NOLEARN] = {
462 .offset = ALE_PORTCTL,
468 [ALE_PORT_MCAST_LIMIT] = {
469 .name = "mcast_limit",
470 .offset = ALE_PORTCTL,
476 [ALE_PORT_BCAST_LIMIT] = {
477 .name = "bcast_limit",
478 .offset = ALE_PORTCTL,
484 [ALE_PORT_UNKNOWN_VLAN_MEMBER] = {
485 .name = "unknown_vlan_member",
486 .offset = ALE_UNKNOWNVLAN,
492 [ALE_PORT_UNKNOWN_MCAST_FLOOD] = {
493 .name = "unknown_mcast_flood",
494 .offset = ALE_UNKNOWNVLAN,
500 [ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = {
501 .name = "unknown_reg_flood",
502 .offset = ALE_UNKNOWNVLAN,
508 [ALE_PORT_UNTAGGED_EGRESS] = {
509 .name = "untagged_egress",
510 .offset = ALE_UNKNOWNVLAN,
518 int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control,
521 const struct ale_control_info *info;
525 if (control < 0 || control >= ARRAY_SIZE(ale_controls))
528 info = &ale_controls[control];
529 if (info->port_offset == 0 && info->port_shift == 0)
530 port = 0; /* global, port is a dont care */
532 if (port < 0 || port > ale->params.ale_ports)
535 mask = BITMASK(info->bits);
539 offset = info->offset + (port * info->port_offset);
540 shift = info->shift + (port * info->port_shift);
542 tmp = __raw_readl(ale->params.ale_regs + offset);
543 tmp = (tmp & ~(mask << shift)) | (value << shift);
544 __raw_writel(tmp, ale->params.ale_regs + offset);
549 int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
551 const struct ale_control_info *info;
555 if (control < 0 || control >= ARRAY_SIZE(ale_controls))
558 info = &ale_controls[control];
559 if (info->port_offset == 0 && info->port_shift == 0)
560 port = 0; /* global, port is a dont care */
562 if (port < 0 || port > ale->params.ale_ports)
565 offset = info->offset + (port * info->port_offset);
566 shift = info->shift + (port * info->port_shift);
568 tmp = __raw_readl(ale->params.ale_regs + offset) >> shift;
569 return tmp & BITMASK(info->bits);
572 static void cpsw_ale_timer(unsigned long arg)
574 struct cpsw_ale *ale = (struct cpsw_ale *)arg;
576 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
579 ale->timer.expires = jiffies + ale->ageout;
580 add_timer(&ale->timer);
584 int cpsw_ale_set_ageout(struct cpsw_ale *ale, int ageout)
586 del_timer_sync(&ale->timer);
587 ale->ageout = ageout * HZ;
589 ale->timer.expires = jiffies + ale->ageout;
590 add_timer(&ale->timer);
595 void cpsw_ale_start(struct cpsw_ale *ale)
599 rev = __raw_readl(ale->params.ale_regs + ALE_IDVER);
600 dev_dbg(ale->params.dev, "initialized cpsw ale revision %d.%d\n",
601 ALE_VERSION_MAJOR(rev), ALE_VERSION_MINOR(rev));
602 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1);
603 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
605 init_timer(&ale->timer);
606 ale->timer.data = (unsigned long)ale;
607 ale->timer.function = cpsw_ale_timer;
609 ale->timer.expires = jiffies + ale->ageout;
610 add_timer(&ale->timer);
614 void cpsw_ale_stop(struct cpsw_ale *ale)
616 del_timer_sync(&ale->timer);
619 struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params)
621 struct cpsw_ale *ale;
623 ale = kzalloc(sizeof(*ale), GFP_KERNEL);
627 ale->params = *params;
628 ale->ageout = ale->params.ale_ageout * HZ;
633 int cpsw_ale_destroy(struct cpsw_ale *ale)
638 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);