Pileus Git - ~andy/linux/blob - drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of.h>
  33 #include <linux/of_net.h>
  34 #include <linux/of_device.h>
  35
  36 #include <linux/platform_data/cpsw.h>
  37
  38 #include "cpsw_ale.h"
  39 #include "cpts.h"
  40 #include "davinci_cpdma.h"
  41
  42 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  43                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  44                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  45                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  46                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  47                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  48                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  49                          NETIF_MSG_RX_STATUS)
  50
  51 #define cpsw_info(priv, type, format, ...)              \
  52 do {                                                            \
  53         if (netif_msg_##type(priv) && net_ratelimit())          \
  54                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  55 } while (0)
  56
  57 #define cpsw_err(priv, type, format, ...)               \
  58 do {                                                            \
  59         if (netif_msg_##type(priv) && net_ratelimit())          \
  60                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  61 } while (0)
  62
  63 #define cpsw_dbg(priv, type, format, ...)               \
  64 do {                                                            \
  65         if (netif_msg_##type(priv) && net_ratelimit())          \
  66                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  67 } while (0)
  68
  69 #define cpsw_notice(priv, type, format, ...)            \
  70 do {                                                            \
  71         if (netif_msg_##type(priv) && net_ratelimit())          \
  72                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  73 } while (0)
  74
  75 #define ALE_ALL_PORTS           0x7
  76
  77 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  78 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  79 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  80
  81 #define CPSW_VERSION_1          0x19010a
  82 #define CPSW_VERSION_2          0x19010c
  83 #define CPDMA_RXTHRESH          0x0c0
  84 #define CPDMA_RXFREE            0x0e0
  85 #define CPDMA_TXHDP             0x00
  86 #define CPDMA_RXHDP             0x20
  87 #define CPDMA_TXCP              0x40
  88 #define CPDMA_RXCP              0x60
  89
  90 #define cpsw_dma_regs(base, offset)             \
  91         (void __iomem *)((base) + (offset))
  92 #define cpsw_dma_rxthresh(base, offset)         \
  93         (void __iomem *)((base) + (offset) + CPDMA_RXTHRESH)
  94 #define cpsw_dma_rxfree(base, offset)           \
  95         (void __iomem *)((base) + (offset) + CPDMA_RXFREE)
  96 #define cpsw_dma_txhdp(base, offset)            \
  97         (void __iomem *)((base) + (offset) + CPDMA_TXHDP)
  98 #define cpsw_dma_rxhdp(base, offset)            \
  99         (void __iomem *)((base) + (offset) + CPDMA_RXHDP)
 100 #define cpsw_dma_txcp(base, offset)             \
 101         (void __iomem *)((base) + (offset) + CPDMA_TXCP)
 102 #define cpsw_dma_rxcp(base, offset)             \
 103         (void __iomem *)((base) + (offset) + CPDMA_RXCP)
 104
 105 #define CPSW_POLL_WEIGHT        64
 106 #define CPSW_MIN_PACKET_SIZE    60
 107 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 108
 109 #define RX_PRIORITY_MAPPING     0x76543210
 110 #define TX_PRIORITY_MAPPING     0x33221100
 111 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 112
 113 #define cpsw_enable_irq(priv)   \
 114         do {                    \
 115                 u32 i;          \
 116                 for (i = 0; i < priv->num_irqs; i++) \
 117                         enable_irq(priv->irqs_table[i]); \
 118         } while (0);
 119 #define cpsw_disable_irq(priv)  \
 120         do {                    \
 121                 u32 i;          \
 122                 for (i = 0; i < priv->num_irqs; i++) \
 123                         disable_irq_nosync(priv->irqs_table[i]); \
 124         } while (0);
 125
 126 static int debug_level;
 127 module_param(debug_level, int, 0);
 128 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 129
 130 static int ale_ageout = 10;
 131 module_param(ale_ageout, int, 0);
 132 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 133
 134 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 135 module_param(rx_packet_max, int, 0);
 136 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 137
 138 struct cpsw_wr_regs {
 139         u32     id_ver;
 140         u32     soft_reset;
 141         u32     control;
 142         u32     int_control;
 143         u32     rx_thresh_en;
 144         u32     rx_en;
 145         u32     tx_en;
 146         u32     misc_en;
 147 };
 148
 149 struct cpsw_ss_regs {
 150         u32     id_ver;
 151         u32     control;
 152         u32     soft_reset;
 153         u32     stat_port_en;
 154         u32     ptype;
 155         u32     soft_idle;
 156         u32     thru_rate;
 157         u32     gap_thresh;
 158         u32     tx_start_wds;
 159         u32     flow_control;
 160         u32     vlan_ltype;
 161         u32     ts_ltype;
 162         u32     dlr_ltype;
 163 };
 164
 165 /* CPSW_PORT_V1 */
 166 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 167 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 168 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 169 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 170 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 171 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 172 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 173 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 174
 175 /* CPSW_PORT_V2 */
 176 #define CPSW2_CONTROL       0x00 /* Control Register */
 177 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 178 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 179 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 180 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 181 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 182 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 183
 184 /* CPSW_PORT_V1 and V2 */
 185 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 186 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 187 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 188
 189 /* CPSW_PORT_V2 only */
 190 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 191 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 192 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 193 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 194 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 195 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 196 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 197 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 198
 199 /* Bit definitions for the CPSW2_CONTROL register */
 200 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 201 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 202 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 203 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 204 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 205 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 206 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 207 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 208 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 209 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 210 #define TS_BIT8             (1<<8)  /* ts_ttl_nonzero? */
 211 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 212 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 213 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 214 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 215 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 216
 217 #define CTRL_TS_BITS \
 218         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
 219          TS_ANNEX_D_EN | TS_LTYPE1_EN)
 220
 221 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
 222 #define CTRL_TX_TS_BITS  (CTRL_TS_BITS | TS_TX_EN)
 223 #define CTRL_RX_TS_BITS  (CTRL_TS_BITS | TS_RX_EN)
 224
 225 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 226 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 227 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 228 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 229 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 230
 231 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 232 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 233
 234 /* Bit definitions for the CPSW1_TS_CTL register */
 235 #define CPSW_V1_TS_RX_EN                BIT(0)
 236 #define CPSW_V1_TS_TX_EN                BIT(4)
 237 #define CPSW_V1_MSG_TYPE_OFS            16
 238
 239 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 240 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 241
 242 struct cpsw_host_regs {
 243         u32     max_blks;
 244         u32     blk_cnt;
 245         u32     flow_thresh;
 246         u32     port_vlan;
 247         u32     tx_pri_map;
 248         u32     cpdma_tx_pri_map;
 249         u32     cpdma_rx_chan_map;
 250 };
 251
 252 struct cpsw_sliver_regs {
 253         u32     id_ver;
 254         u32     mac_control;
 255         u32     mac_status;
 256         u32     soft_reset;
 257         u32     rx_maxlen;
 258         u32     __reserved_0;
 259         u32     rx_pause;
 260         u32     tx_pause;
 261         u32     __reserved_1;
 262         u32     rx_pri_map;
 263 };
 264
 265 struct cpsw_slave {
 266         void __iomem                    *regs;
 267         struct cpsw_sliver_regs __iomem *sliver;
 268         int                             slave_num;
 269         u32                             mac_control;
 270         struct cpsw_slave_data          *data;
 271         struct phy_device               *phy;
 272 };
 273
 274 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 275 {
 276         return __raw_readl(slave->regs + offset);
 277 }
 278
 279 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 280 {
 281         __raw_writel(val, slave->regs + offset);
 282 }
 283
 284 struct cpsw_priv {
 285         spinlock_t                      lock;
 286         struct platform_device          *pdev;
 287         struct net_device               *ndev;
 288         struct resource                 *cpsw_res;
 289         struct resource                 *cpsw_wr_res;
 290         struct napi_struct              napi;
 291         struct device                   *dev;
 292         struct cpsw_platform_data       data;
 293         struct cpsw_ss_regs __iomem     *regs;
 294         struct cpsw_wr_regs __iomem     *wr_regs;
 295         struct cpsw_host_regs __iomem   *host_port_regs;
 296         u32                             msg_enable;
 297         u32                             version;
 298         struct net_device_stats         stats;
 299         int                             rx_packet_max;
 300         int                             host_port;
 301         struct clk                      *clk;
 302         u8                              mac_addr[ETH_ALEN];
 303         struct cpsw_slave               *slaves;
 304         struct cpdma_ctlr               *dma;
 305         struct cpdma_chan               *txch, *rxch;
 306         struct cpsw_ale                 *ale;
 307         /* snapshot of IRQ numbers */
 308         u32 irqs_table[4];
 309         u32 num_irqs;
 310         struct cpts cpts;
 311 };
 312
 313 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 314 #define for_each_slave(priv, func, arg...)                      \
 315         do {                                                    \
 316                 int idx;                                        \
 317                 for (idx = 0; idx < (priv)->data.slaves; idx++) \
 318                         (func)((priv)->slaves + idx, ##arg);    \
 319         } while (0)
 320
 321 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 322 {
 323         struct cpsw_priv *priv = netdev_priv(ndev);
 324
 325         if (ndev->flags & IFF_PROMISC) {
 326                 /* Enable promiscuous mode */
 327                 dev_err(priv->dev, "Ignoring Promiscuous mode\n");
 328                 return;
 329         }
 330
 331         /* Clear all mcast from ALE */
 332         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
 333
 334         if (!netdev_mc_empty(ndev)) {
 335                 struct netdev_hw_addr *ha;
 336
 337                 /* program multicast address list into ALE register */
 338                 netdev_for_each_mc_addr(ha, ndev) {
 339                         cpsw_ale_add_mcast(priv->ale, (u8 *)ha->addr,
 340                                 ALE_ALL_PORTS << priv->host_port, 0, 0);
 341                 }
 342         }
 343 }
 344
 345 static void cpsw_intr_enable(struct cpsw_priv *priv)
 346 {
 347         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 348         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 349
 350         cpdma_ctlr_int_ctrl(priv->dma, true);
 351         return;
 352 }
 353
 354 static void cpsw_intr_disable(struct cpsw_priv *priv)
 355 {
 356         __raw_writel(0, &priv->wr_regs->tx_en);
 357         __raw_writel(0, &priv->wr_regs->rx_en);
 358
 359         cpdma_ctlr_int_ctrl(priv->dma, false);
 360         return;
 361 }
 362
 363 void cpsw_tx_handler(void *token, int len, int status)
 364 {
 365         struct sk_buff          *skb = token;
 366         struct net_device       *ndev = skb->dev;
 367         struct cpsw_priv        *priv = netdev_priv(ndev);
 368
 369         if (unlikely(netif_queue_stopped(ndev)))
 370                 netif_start_queue(ndev);
 371         cpts_tx_timestamp(&priv->cpts, skb);
 372         priv->stats.tx_packets++;
 373         priv->stats.tx_bytes += len;
 374         dev_kfree_skb_any(skb);
 375 }
 376
 377 void cpsw_rx_handler(void *token, int len, int status)
 378 {
 379         struct sk_buff          *skb = token;
 380         struct net_device       *ndev = skb->dev;
 381         struct cpsw_priv        *priv = netdev_priv(ndev);
 382         int                     ret = 0;
 383
 384         /* free and bail if we are shutting down */
 385         if (unlikely(!netif_running(ndev)) ||
 386                         unlikely(!netif_carrier_ok(ndev))) {
 387                 dev_kfree_skb_any(skb);
 388                 return;
 389         }
 390         if (likely(status >= 0)) {
 391                 skb_put(skb, len);
 392                 cpts_rx_timestamp(&priv->cpts, skb);
 393                 skb->protocol = eth_type_trans(skb, ndev);
 394                 netif_receive_skb(skb);
 395                 priv->stats.rx_bytes += len;
 396                 priv->stats.rx_packets++;
 397                 skb = NULL;
 398         }
 399
 400         if (unlikely(!netif_running(ndev))) {
 401                 if (skb)
 402                         dev_kfree_skb_any(skb);
 403                 return;
 404         }
 405
 406         if (likely(!skb)) {
 407                 skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 408                 if (WARN_ON(!skb))
 409                         return;
 410
 411                 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
 412                                         skb_tailroom(skb), GFP_KERNEL);
 413         }
 414         WARN_ON(ret < 0);
 415 }
 416
 417 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
 418 {
 419         struct cpsw_priv *priv = dev_id;
 420
 421         if (likely(netif_running(priv->ndev))) {
 422                 cpsw_intr_disable(priv);
 423                 cpsw_disable_irq(priv);
 424                 napi_schedule(&priv->napi);
 425         }
 426         return IRQ_HANDLED;
 427 }
 428
 429 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 430 {
 431         if (priv->host_port == 0)
 432                 return slave_num + 1;
 433         else
 434                 return slave_num;
 435 }
 436
 437 static int cpsw_poll(struct napi_struct *napi, int budget)
 438 {
 439         struct cpsw_priv        *priv = napi_to_priv(napi);
 440         int                     num_tx, num_rx;
 441
 442         num_tx = cpdma_chan_process(priv->txch, 128);
 443         num_rx = cpdma_chan_process(priv->rxch, budget);
 444
 445         if (num_rx || num_tx)
 446                 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
 447                          num_rx, num_tx);
 448
 449         if (num_rx < budget) {
 450                 napi_complete(napi);
 451                 cpsw_intr_enable(priv);
 452                 cpdma_ctlr_eoi(priv->dma);
 453                 cpsw_enable_irq(priv);
 454         }
 455
 456         return num_rx;
 457 }
 458
 459 static inline void soft_reset(const char *module, void __iomem *reg)
 460 {
 461         unsigned long timeout = jiffies + HZ;
 462
 463         __raw_writel(1, reg);
 464         do {
 465                 cpu_relax();
 466         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 467
 468         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 469 }
 470
 471 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 472                          ((mac)[2] << 16) | ((mac)[3] << 24))
 473 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 474
 475 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 476                                struct cpsw_priv *priv)
 477 {
 478         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 479         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 480 }
 481
 482 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 483                               struct cpsw_priv *priv, bool *link)
 484 {
 485         struct phy_device       *phy = slave->phy;
 486         u32                     mac_control = 0;
 487         u32                     slave_port;
 488
 489         if (!phy)
 490                 return;
 491
 492         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 493
 494         if (phy->link) {
 495                 mac_control = priv->data.mac_control;
 496
 497                 /* enable forwarding */
 498                 cpsw_ale_control_set(priv->ale, slave_port,
 499                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 500
 501                 if (phy->speed == 1000)
 502                         mac_control |= BIT(7);  /* GIGABITEN    */
 503                 if (phy->duplex)
 504                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 505
 506                 /* set speed_in input in case RMII mode is used in 100Mbps */
 507                 if (phy->speed == 100)
 508                         mac_control |= BIT(15);
 509
 510                 *link = true;
 511         } else {
 512                 mac_control = 0;
 513                 /* disable forwarding */
 514                 cpsw_ale_control_set(priv->ale, slave_port,
 515                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 516         }
 517
 518         if (mac_control != slave->mac_control) {
 519                 phy_print_status(phy);
 520                 __raw_writel(mac_control, &slave->sliver->mac_control);
 521         }
 522
 523         slave->mac_control = mac_control;
 524 }
 525
 526 static void cpsw_adjust_link(struct net_device *ndev)
 527 {
 528         struct cpsw_priv        *priv = netdev_priv(ndev);
 529         bool                    link = false;
 530
 531         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 532
 533         if (link) {
 534                 netif_carrier_on(ndev);
 535                 if (netif_running(ndev))
 536                         netif_wake_queue(ndev);
 537         } else {
 538                 netif_carrier_off(ndev);
 539                 netif_stop_queue(ndev);
 540         }
 541 }
 542
 543 static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
 544 {
 545         static char *leader = "........................................";
 546
 547         if (!val)
 548                 return 0;
 549         else
 550                 return snprintf(buf, maxlen, "%s %s %10d\n", name,
 551                                 leader + strlen(name), val);
 552 }
 553
 554 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
 555 {
 556         char name[32];
 557         u32 slave_port;
 558
 559         sprintf(name, "slave-%d", slave->slave_num);
 560
 561         soft_reset(name, &slave->sliver->soft_reset);
 562
 563         /* setup priority mapping */
 564         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
 565
 566         switch (priv->version) {
 567         case CPSW_VERSION_1:
 568                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
 569                 break;
 570         case CPSW_VERSION_2:
 571                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
 572                 break;
 573         }
 574
 575         /* setup max packet size, and mac address */
 576         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
 577         cpsw_set_slave_mac(slave, priv);
 578
 579         slave->mac_control = 0; /* no link yet */
 580
 581         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 582
 583         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
 584                            1 << slave_port, 0, ALE_MCAST_FWD_2);
 585
 586         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
 587                                  &cpsw_adjust_link, 0, slave->data->phy_if);
 588         if (IS_ERR(slave->phy)) {
 589                 dev_err(priv->dev, "phy %s not found on slave %d\n",
 590                         slave->data->phy_id, slave->slave_num);
 591                 slave->phy = NULL;
 592         } else {
 593                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
 594                          slave->phy->phy_id);
 595                 phy_start(slave->phy);
 596         }
 597 }
 598
 599 static void cpsw_init_host_port(struct cpsw_priv *priv)
 600 {
 601         /* soft reset the controller and initialize ale */
 602         soft_reset("cpsw", &priv->regs->soft_reset);
 603         cpsw_ale_start(priv->ale);
 604
 605         /* switch to vlan unaware mode */
 606         cpsw_ale_control_set(priv->ale, 0, ALE_VLAN_AWARE, 0);
 607
 608         /* setup host port priority mapping */
 609         __raw_writel(CPDMA_TX_PRIORITY_MAP,
 610                      &priv->host_port_regs->cpdma_tx_pri_map);
 611         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
 612
 613         cpsw_ale_control_set(priv->ale, priv->host_port,
 614                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 615
 616         cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 0);
 617         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
 618                            1 << priv->host_port, 0, ALE_MCAST_FWD_2);
 619 }
 620
 621 static int cpsw_ndo_open(struct net_device *ndev)
 622 {
 623         struct cpsw_priv *priv = netdev_priv(ndev);
 624         int i, ret;
 625         u32 reg;
 626
 627         cpsw_intr_disable(priv);
 628         netif_carrier_off(ndev);
 629
 630         pm_runtime_get_sync(&priv->pdev->dev);
 631
 632         reg = __raw_readl(&priv->regs->id_ver);
 633         priv->version = reg;
 634
 635         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
 636                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
 637                  CPSW_RTL_VERSION(reg));
 638
 639         /* initialize host and slave ports */
 640         cpsw_init_host_port(priv);
 641         for_each_slave(priv, cpsw_slave_open, priv);
 642
 643         /* setup tx dma to fixed prio and zero offset */
 644         cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
 645         cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
 646
 647         /* disable priority elevation and enable statistics on all ports */
 648         __raw_writel(0, &priv->regs->ptype);
 649
 650         /* enable statistics collection only on the host port */
 651         __raw_writel(0x7, &priv->regs->stat_port_en);
 652
 653         if (WARN_ON(!priv->data.rx_descs))
 654                 priv->data.rx_descs = 128;
 655
 656         for (i = 0; i < priv->data.rx_descs; i++) {
 657                 struct sk_buff *skb;
 658
 659                 ret = -ENOMEM;
 660                 skb = netdev_alloc_skb_ip_align(priv->ndev,
 661                                                 priv->rx_packet_max);
 662                 if (!skb)
 663                         break;
 664                 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
 665                                         skb_tailroom(skb), GFP_KERNEL);
 666                 if (WARN_ON(ret < 0))
 667                         break;
 668         }
 669         /* continue even if we didn't manage to submit all receive descs */
 670         cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
 671
 672         cpdma_ctlr_start(priv->dma);
 673         cpsw_intr_enable(priv);
 674         napi_enable(&priv->napi);
 675         cpdma_ctlr_eoi(priv->dma);
 676
 677         return 0;
 678 }
 679
 680 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
 681 {
 682         if (!slave->phy)
 683                 return;
 684         phy_stop(slave->phy);
 685         phy_disconnect(slave->phy);
 686         slave->phy = NULL;
 687 }
 688
 689 static int cpsw_ndo_stop(struct net_device *ndev)
 690 {
 691         struct cpsw_priv *priv = netdev_priv(ndev);
 692
 693         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
 694         cpsw_intr_disable(priv);
 695         cpdma_ctlr_int_ctrl(priv->dma, false);
 696         cpdma_ctlr_stop(priv->dma);
 697         netif_stop_queue(priv->ndev);
 698         napi_disable(&priv->napi);
 699         netif_carrier_off(priv->ndev);
 700         cpsw_ale_stop(priv->ale);
 701         for_each_slave(priv, cpsw_slave_stop, priv);
 702         pm_runtime_put_sync(&priv->pdev->dev);
 703         return 0;
 704 }
 705
 706 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
 707                                        struct net_device *ndev)
 708 {
 709         struct cpsw_priv *priv = netdev_priv(ndev);
 710         int ret;
 711
 712         ndev->trans_start = jiffies;
 713
 714         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
 715                 cpsw_err(priv, tx_err, "packet pad failed\n");
 716                 priv->stats.tx_dropped++;
 717                 return NETDEV_TX_OK;
 718         }
 719
 720         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && priv->cpts.tx_enable)
 721                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
 722
 723         skb_tx_timestamp(skb);
 724
 725         ret = cpdma_chan_submit(priv->txch, skb, skb->data,
 726                                 skb->len, GFP_KERNEL);
 727         if (unlikely(ret != 0)) {
 728                 cpsw_err(priv, tx_err, "desc submit failed\n");
 729                 goto fail;
 730         }
 731
 732         return NETDEV_TX_OK;
 733 fail:
 734         priv->stats.tx_dropped++;
 735         netif_stop_queue(ndev);
 736         return NETDEV_TX_BUSY;
 737 }
 738
 739 static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
 740 {
 741         /*
 742          * The switch cannot operate in promiscuous mode without substantial
 743          * headache.  For promiscuous mode to work, we would need to put the
 744          * ALE in bypass mode and route all traffic to the host port.
 745          * Subsequently, the host will need to operate as a "bridge", learn,
 746          * and flood as needed.  For now, we simply complain here and
 747          * do nothing about it :-)
 748          */
 749         if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
 750                 dev_err(&ndev->dev, "promiscuity ignored!\n");
 751
 752         /*
 753          * The switch cannot filter multicast traffic unless it is configured
 754          * in "VLAN Aware" mode.  Unfortunately, VLAN awareness requires a
 755          * whole bunch of additional logic that this driver does not implement
 756          * at present.
 757          */
 758         if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
 759                 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
 760 }
 761
 762 #ifdef CONFIG_TI_CPTS
 763
 764 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
 765 {
 766         struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave];
 767         u32 ts_en, seq_id;
 768
 769         if (!priv->cpts.tx_enable && !priv->cpts.rx_enable) {
 770                 slave_write(slave, 0, CPSW1_TS_CTL);
 771                 return;
 772         }
 773
 774         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
 775         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
 776
 777         if (priv->cpts.tx_enable)
 778                 ts_en |= CPSW_V1_TS_TX_EN;
 779
 780         if (priv->cpts.rx_enable)
 781                 ts_en |= CPSW_V1_TS_RX_EN;
 782
 783         slave_write(slave, ts_en, CPSW1_TS_CTL);
 784         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
 785 }
 786
 787 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
 788 {
 789         struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave];
 790         u32 ctrl, mtype;
 791
 792         ctrl = slave_read(slave, CPSW2_CONTROL);
 793         ctrl &= ~CTRL_ALL_TS_MASK;
 794
 795         if (priv->cpts.tx_enable)
 796                 ctrl |= CTRL_TX_TS_BITS;
 797
 798         if (priv->cpts.rx_enable)
 799                 ctrl |= CTRL_RX_TS_BITS;
 800
 801         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
 802
 803         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
 804         slave_write(slave, ctrl, CPSW2_CONTROL);
 805         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
 806 }
 807
 808 static int cpsw_hwtstamp_ioctl(struct cpsw_priv *priv, struct ifreq *ifr)
 809 {
 810         struct cpts *cpts = &priv->cpts;
 811         struct hwtstamp_config cfg;
 812
 813         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
 814                 return -EFAULT;
 815
 816         /* reserved for future extensions */
 817         if (cfg.flags)
 818                 return -EINVAL;
 819
 820         switch (cfg.tx_type) {
 821         case HWTSTAMP_TX_OFF:
 822                 cpts->tx_enable = 0;
 823                 break;
 824         case HWTSTAMP_TX_ON:
 825                 cpts->tx_enable = 1;
 826                 break;
 827         default:
 828                 return -ERANGE;
 829         }
 830
 831         switch (cfg.rx_filter) {
 832         case HWTSTAMP_FILTER_NONE:
 833                 cpts->rx_enable = 0;
 834                 break;
 835         case HWTSTAMP_FILTER_ALL:
 836         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 837         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 838         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 839                 return -ERANGE;
 840         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 841         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 842         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 843         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 844         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 845         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 846         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 847         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 848         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 849                 cpts->rx_enable = 1;
 850                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 851                 break;
 852         default:
 853                 return -ERANGE;
 854         }
 855
 856         switch (priv->version) {
 857         case CPSW_VERSION_1:
 858                 cpsw_hwtstamp_v1(priv);
 859                 break;
 860         case CPSW_VERSION_2:
 861                 cpsw_hwtstamp_v2(priv);
 862                 break;
 863         default:
 864                 return -ENOTSUPP;
 865         }
 866
 867         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 868 }
 869
 870 #endif /*CONFIG_TI_CPTS*/
 871
 872 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
 873 {
 874         struct cpsw_priv *priv = netdev_priv(dev);
 875
 876         if (!netif_running(dev))
 877                 return -EINVAL;
 878
 879 #ifdef CONFIG_TI_CPTS
 880         if (cmd == SIOCSHWTSTAMP)
 881                 return cpsw_hwtstamp_ioctl(priv, req);
 882 #endif
 883         return -ENOTSUPP;
 884 }
 885
 886 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
 887 {
 888         struct cpsw_priv *priv = netdev_priv(ndev);
 889
 890         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
 891         priv->stats.tx_errors++;
 892         cpsw_intr_disable(priv);
 893         cpdma_ctlr_int_ctrl(priv->dma, false);
 894         cpdma_chan_stop(priv->txch);
 895         cpdma_chan_start(priv->txch);
 896         cpdma_ctlr_int_ctrl(priv->dma, true);
 897         cpsw_intr_enable(priv);
 898         cpdma_ctlr_eoi(priv->dma);
 899 }
 900
 901 static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
 902 {
 903         struct cpsw_priv *priv = netdev_priv(ndev);
 904         return &priv->stats;
 905 }
 906
 907 #ifdef CONFIG_NET_POLL_CONTROLLER
 908 static void cpsw_ndo_poll_controller(struct net_device *ndev)
 909 {
 910         struct cpsw_priv *priv = netdev_priv(ndev);
 911
 912         cpsw_intr_disable(priv);
 913         cpdma_ctlr_int_ctrl(priv->dma, false);
 914         cpsw_interrupt(ndev->irq, priv);
 915         cpdma_ctlr_int_ctrl(priv->dma, true);
 916         cpsw_intr_enable(priv);
 917         cpdma_ctlr_eoi(priv->dma);
 918 }
 919 #endif
 920
 921 static const struct net_device_ops cpsw_netdev_ops = {
 922         .ndo_open               = cpsw_ndo_open,
 923         .ndo_stop               = cpsw_ndo_stop,
 924         .ndo_start_xmit         = cpsw_ndo_start_xmit,
 925         .ndo_change_rx_flags    = cpsw_ndo_change_rx_flags,
 926         .ndo_do_ioctl           = cpsw_ndo_ioctl,
 927         .ndo_validate_addr      = eth_validate_addr,
 928         .ndo_change_mtu         = eth_change_mtu,
 929         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
 930         .ndo_get_stats          = cpsw_ndo_get_stats,
 931         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
 932 #ifdef CONFIG_NET_POLL_CONTROLLER
 933         .ndo_poll_controller    = cpsw_ndo_poll_controller,
 934 #endif
 935 };
 936
 937 static void cpsw_get_drvinfo(struct net_device *ndev,
 938                              struct ethtool_drvinfo *info)
 939 {
 940         struct cpsw_priv *priv = netdev_priv(ndev);
 941         strcpy(info->driver, "TI CPSW Driver v1.0");
 942         strcpy(info->version, "1.0");
 943         strcpy(info->bus_info, priv->pdev->name);
 944 }
 945
 946 static u32 cpsw_get_msglevel(struct net_device *ndev)
 947 {
 948         struct cpsw_priv *priv = netdev_priv(ndev);
 949         return priv->msg_enable;
 950 }
 951
 952 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
 953 {
 954         struct cpsw_priv *priv = netdev_priv(ndev);
 955         priv->msg_enable = value;
 956 }
 957
 958 static int cpsw_get_ts_info(struct net_device *ndev,
 959                             struct ethtool_ts_info *info)
 960 {
 961 #ifdef CONFIG_TI_CPTS
 962         struct cpsw_priv *priv = netdev_priv(ndev);
 963
 964         info->so_timestamping =
 965                 SOF_TIMESTAMPING_TX_HARDWARE |
 966                 SOF_TIMESTAMPING_TX_SOFTWARE |
 967                 SOF_TIMESTAMPING_RX_HARDWARE |
 968                 SOF_TIMESTAMPING_RX_SOFTWARE |
 969                 SOF_TIMESTAMPING_SOFTWARE |
 970                 SOF_TIMESTAMPING_RAW_HARDWARE;
 971         info->phc_index = priv->cpts.phc_index;
 972         info->tx_types =
 973                 (1 << HWTSTAMP_TX_OFF) |
 974                 (1 << HWTSTAMP_TX_ON);
 975         info->rx_filters =
 976                 (1 << HWTSTAMP_FILTER_NONE) |
 977                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
 978 #else
 979         info->so_timestamping =
 980                 SOF_TIMESTAMPING_TX_SOFTWARE |
 981                 SOF_TIMESTAMPING_RX_SOFTWARE |
 982                 SOF_TIMESTAMPING_SOFTWARE;
 983         info->phc_index = -1;
 984         info->tx_types = 0;
 985         info->rx_filters = 0;
 986 #endif
 987         return 0;
 988 }
 989
 990 static const struct ethtool_ops cpsw_ethtool_ops = {
 991         .get_drvinfo    = cpsw_get_drvinfo,
 992         .get_msglevel   = cpsw_get_msglevel,
 993         .set_msglevel   = cpsw_set_msglevel,
 994         .get_link       = ethtool_op_get_link,
 995         .get_ts_info    = cpsw_get_ts_info,
 996 };
 997
 998 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
 999 {
1000         void __iomem            *regs = priv->regs;
1001         int                     slave_num = slave->slave_num;
1002         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1003
1004         slave->data     = data;
1005         slave->regs     = regs + data->slave_reg_ofs;
1006         slave->sliver   = regs + data->sliver_reg_ofs;
1007 }
1008
1009 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1010                          struct platform_device *pdev)
1011 {
1012         struct device_node *node = pdev->dev.of_node;
1013         struct device_node *slave_node;
1014         int i = 0, ret;
1015         u32 prop;
1016
1017         if (!node)
1018                 return -EINVAL;
1019
1020         if (of_property_read_u32(node, "slaves", &prop)) {
1021                 pr_err("Missing slaves property in the DT.\n");
1022                 return -EINVAL;
1023         }
1024         data->slaves = prop;
1025
1026         if (of_property_read_u32(node, "cpts_active_slave", &prop)) {
1027                 pr_err("Missing cpts_active_slave property in the DT.\n");
1028                 ret = -EINVAL;
1029                 goto error_ret;
1030         }
1031         data->cpts_active_slave = prop;
1032
1033         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1034                 pr_err("Missing cpts_clock_mult property in the DT.\n");
1035                 ret = -EINVAL;
1036                 goto error_ret;
1037         }
1038         data->cpts_clock_mult = prop;
1039
1040         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1041                 pr_err("Missing cpts_clock_shift property in the DT.\n");
1042                 ret = -EINVAL;
1043                 goto error_ret;
1044         }
1045         data->cpts_clock_shift = prop;
1046
1047         data->slave_data = kzalloc(sizeof(struct cpsw_slave_data) *
1048                                    data->slaves, GFP_KERNEL);
1049         if (!data->slave_data) {
1050                 pr_err("Could not allocate slave memory.\n");
1051                 return -EINVAL;
1052         }
1053
1054         data->no_bd_ram = of_property_read_bool(node, "no_bd_ram");
1055
1056         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1057                 pr_err("Missing cpdma_channels property in the DT.\n");
1058                 ret = -EINVAL;
1059                 goto error_ret;
1060         }
1061         data->channels = prop;
1062
1063         if (of_property_read_u32(node, "host_port_no", &prop)) {
1064                 pr_err("Missing host_port_no property in the DT.\n");
1065                 ret = -EINVAL;
1066                 goto error_ret;
1067         }
1068         data->host_port_num = prop;
1069
1070         if (of_property_read_u32(node, "cpdma_reg_ofs", &prop)) {
1071                 pr_err("Missing cpdma_reg_ofs property in the DT.\n");
1072                 ret = -EINVAL;
1073                 goto error_ret;
1074         }
1075         data->cpdma_reg_ofs = prop;
1076
1077         if (of_property_read_u32(node, "cpdma_sram_ofs", &prop)) {
1078                 pr_err("Missing cpdma_sram_ofs property in the DT.\n");
1079                 ret = -EINVAL;
1080                 goto error_ret;
1081         }
1082         data->cpdma_sram_ofs = prop;
1083
1084         if (of_property_read_u32(node, "ale_reg_ofs", &prop)) {
1085                 pr_err("Missing ale_reg_ofs property in the DT.\n");
1086                 ret = -EINVAL;
1087                 goto error_ret;
1088         }
1089         data->ale_reg_ofs = prop;
1090
1091         if (of_property_read_u32(node, "ale_entries", &prop)) {
1092                 pr_err("Missing ale_entries property in the DT.\n");
1093                 ret = -EINVAL;
1094                 goto error_ret;
1095         }
1096         data->ale_entries = prop;
1097
1098         if (of_property_read_u32(node, "host_port_reg_ofs", &prop)) {
1099                 pr_err("Missing host_port_reg_ofs property in the DT.\n");
1100                 ret = -EINVAL;
1101                 goto error_ret;
1102         }
1103         data->host_port_reg_ofs = prop;
1104
1105         if (of_property_read_u32(node, "hw_stats_reg_ofs", &prop)) {
1106                 pr_err("Missing hw_stats_reg_ofs property in the DT.\n");
1107                 ret = -EINVAL;
1108                 goto error_ret;
1109         }
1110         data->hw_stats_reg_ofs = prop;
1111
1112         if (of_property_read_u32(node, "cpts_reg_ofs", &prop)) {
1113                 pr_err("Missing cpts_reg_ofs property in the DT.\n");
1114                 ret = -EINVAL;
1115                 goto error_ret;
1116         }
1117         data->cpts_reg_ofs = prop;
1118
1119         if (of_property_read_u32(node, "bd_ram_ofs", &prop)) {
1120                 pr_err("Missing bd_ram_ofs property in the DT.\n");
1121                 ret = -EINVAL;
1122                 goto error_ret;
1123         }
1124         data->bd_ram_ofs = prop;
1125
1126         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1127                 pr_err("Missing bd_ram_size property in the DT.\n");
1128                 ret = -EINVAL;
1129                 goto error_ret;
1130         }
1131         data->bd_ram_size = prop;
1132
1133         if (of_property_read_u32(node, "rx_descs", &prop)) {
1134                 pr_err("Missing rx_descs property in the DT.\n");
1135                 ret = -EINVAL;
1136                 goto error_ret;
1137         }
1138         data->rx_descs = prop;
1139
1140         if (of_property_read_u32(node, "mac_control", &prop)) {
1141                 pr_err("Missing mac_control property in the DT.\n");
1142                 ret = -EINVAL;
1143                 goto error_ret;
1144         }
1145         data->mac_control = prop;
1146
1147         for_each_node_by_name(slave_node, "slave") {
1148                 struct cpsw_slave_data *slave_data = data->slave_data + i;
1149                 const char *phy_id = NULL;
1150                 const void *mac_addr = NULL;
1151
1152                 if (of_property_read_string(slave_node, "phy_id", &phy_id)) {
1153                         pr_err("Missing slave[%d] phy_id property\n", i);
1154                         ret = -EINVAL;
1155                         goto error_ret;
1156                 }
1157                 slave_data->phy_id = phy_id;
1158
1159                 if (of_property_read_u32(slave_node, "slave_reg_ofs", &prop)) {
1160                         pr_err("Missing slave[%d] slave_reg_ofs property\n", i);
1161                         ret = -EINVAL;
1162                         goto error_ret;
1163                 }
1164                 slave_data->slave_reg_ofs = prop;
1165
1166                 if (of_property_read_u32(slave_node, "sliver_reg_ofs",
1167                                          &prop)) {
1168                         pr_err("Missing slave[%d] sliver_reg_ofs property\n",
1169                                 i);
1170                         ret = -EINVAL;
1171                         goto error_ret;
1172                 }
1173                 slave_data->sliver_reg_ofs = prop;
1174
1175                 mac_addr = of_get_mac_address(slave_node);
1176                 if (mac_addr)
1177                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1178
1179                 i++;
1180         }
1181
1182         /*
1183          * Populate all the child nodes here...
1184          */
1185         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1186         /* We do not want to force this, as in some cases may not have child */
1187         if (ret)
1188                 pr_warn("Doesn't have any child node\n");
1189
1190         return 0;
1191
1192 error_ret:
1193         kfree(data->slave_data);
1194         return ret;
1195 }
1196
1197 static int __devinit cpsw_probe(struct platform_device *pdev)
1198 {
1199         struct cpsw_platform_data       *data = pdev->dev.platform_data;
1200         struct net_device               *ndev;
1201         struct cpsw_priv                *priv;
1202         struct cpdma_params             dma_params;
1203         struct cpsw_ale_params          ale_params;
1204         void __iomem                    *regs;
1205         struct resource                 *res;
1206         int ret = 0, i, k = 0;
1207
1208         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1209         if (!ndev) {
1210                 pr_err("error allocating net_device\n");
1211                 return -ENOMEM;
1212         }
1213
1214         platform_set_drvdata(pdev, ndev);
1215         priv = netdev_priv(ndev);
1216         spin_lock_init(&priv->lock);
1217         priv->pdev = pdev;
1218         priv->ndev = ndev;
1219         priv->dev  = &ndev->dev;
1220         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1221         priv->rx_packet_max = max(rx_packet_max, 128);
1222
1223         /*
1224          * This may be required here for child devices.
1225          */
1226         pm_runtime_enable(&pdev->dev);
1227
1228         if (cpsw_probe_dt(&priv->data, pdev)) {
1229                 pr_err("cpsw: platform data missing\n");
1230                 ret = -ENODEV;
1231                 goto clean_ndev_ret;
1232         }
1233         data = &priv->data;
1234
1235         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
1236                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
1237                 pr_info("Detected MACID = %pM", priv->mac_addr);
1238         } else {
1239                 eth_random_addr(priv->mac_addr);
1240                 pr_info("Random MACID = %pM", priv->mac_addr);
1241         }
1242
1243         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1244
1245         priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
1246                                GFP_KERNEL);
1247         if (!priv->slaves) {
1248                 ret = -EBUSY;
1249                 goto clean_ndev_ret;
1250         }
1251         for (i = 0; i < data->slaves; i++)
1252                 priv->slaves[i].slave_num = i;
1253
1254         priv->clk = clk_get(&pdev->dev, "fck");
1255         if (IS_ERR(priv->clk)) {
1256                 dev_err(&pdev->dev, "fck is not found\n");
1257                 ret = -ENODEV;
1258                 goto clean_slave_ret;
1259         }
1260
1261         priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1262         if (!priv->cpsw_res) {
1263                 dev_err(priv->dev, "error getting i/o resource\n");
1264                 ret = -ENOENT;
1265                 goto clean_clk_ret;
1266         }
1267         if (!request_mem_region(priv->cpsw_res->start,
1268                                 resource_size(priv->cpsw_res), ndev->name)) {
1269                 dev_err(priv->dev, "failed request i/o region\n");
1270                 ret = -ENXIO;
1271                 goto clean_clk_ret;
1272         }
1273         regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
1274         if (!regs) {
1275                 dev_err(priv->dev, "unable to map i/o region\n");
1276                 goto clean_cpsw_iores_ret;
1277         }
1278         priv->regs = regs;
1279         priv->host_port = data->host_port_num;
1280         priv->host_port_regs = regs + data->host_port_reg_ofs;
1281         priv->cpts.reg = regs + data->cpts_reg_ofs;
1282
1283         priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1284         if (!priv->cpsw_wr_res) {
1285                 dev_err(priv->dev, "error getting i/o resource\n");
1286                 ret = -ENOENT;
1287                 goto clean_iomap_ret;
1288         }
1289         if (!request_mem_region(priv->cpsw_wr_res->start,
1290                         resource_size(priv->cpsw_wr_res), ndev->name)) {
1291                 dev_err(priv->dev, "failed request i/o region\n");
1292                 ret = -ENXIO;
1293                 goto clean_iomap_ret;
1294         }
1295         regs = ioremap(priv->cpsw_wr_res->start,
1296                                 resource_size(priv->cpsw_wr_res));
1297         if (!regs) {
1298                 dev_err(priv->dev, "unable to map i/o region\n");
1299                 goto clean_cpsw_wr_iores_ret;
1300         }
1301         priv->wr_regs = regs;
1302
1303         for_each_slave(priv, cpsw_slave_init, priv);
1304
1305         memset(&dma_params, 0, sizeof(dma_params));
1306         dma_params.dev          = &pdev->dev;
1307         dma_params.dmaregs      = cpsw_dma_regs((u32)priv->regs,
1308                                                 data->cpdma_reg_ofs);
1309         dma_params.rxthresh     = cpsw_dma_rxthresh((u32)priv->regs,
1310                                                     data->cpdma_reg_ofs);
1311         dma_params.rxfree       = cpsw_dma_rxfree((u32)priv->regs,
1312                                                   data->cpdma_reg_ofs);
1313         dma_params.txhdp        = cpsw_dma_txhdp((u32)priv->regs,
1314                                                  data->cpdma_sram_ofs);
1315         dma_params.rxhdp        = cpsw_dma_rxhdp((u32)priv->regs,
1316                                                  data->cpdma_sram_ofs);
1317         dma_params.txcp         = cpsw_dma_txcp((u32)priv->regs,
1318                                                 data->cpdma_sram_ofs);
1319         dma_params.rxcp         = cpsw_dma_rxcp((u32)priv->regs,
1320                                                 data->cpdma_sram_ofs);
1321
1322         dma_params.num_chan             = data->channels;
1323         dma_params.has_soft_reset       = true;
1324         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
1325         dma_params.desc_mem_size        = data->bd_ram_size;
1326         dma_params.desc_align           = 16;
1327         dma_params.has_ext_regs         = true;
1328         dma_params.desc_mem_phys        = data->no_bd_ram ? 0 :
1329                         (u32 __force)priv->cpsw_res->start + data->bd_ram_ofs;
1330         dma_params.desc_hw_addr         = data->hw_ram_addr ?
1331                         data->hw_ram_addr : dma_params.desc_mem_phys ;
1332
1333         priv->dma = cpdma_ctlr_create(&dma_params);
1334         if (!priv->dma) {
1335                 dev_err(priv->dev, "error initializing dma\n");
1336                 ret = -ENOMEM;
1337                 goto clean_wr_iomap_ret;
1338         }
1339
1340         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
1341                                        cpsw_tx_handler);
1342         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
1343                                        cpsw_rx_handler);
1344
1345         if (WARN_ON(!priv->txch || !priv->rxch)) {
1346                 dev_err(priv->dev, "error initializing dma channels\n");
1347                 ret = -ENOMEM;
1348                 goto clean_dma_ret;
1349         }
1350
1351         memset(&ale_params, 0, sizeof(ale_params));
1352         ale_params.dev                  = &ndev->dev;
1353         ale_params.ale_regs             = (void *)((u32)priv->regs) +
1354                                                 ((u32)data->ale_reg_ofs);
1355         ale_params.ale_ageout           = ale_ageout;
1356         ale_params.ale_entries          = data->ale_entries;
1357         ale_params.ale_ports            = data->slaves;
1358
1359         priv->ale = cpsw_ale_create(&ale_params);
1360         if (!priv->ale) {
1361                 dev_err(priv->dev, "error initializing ale engine\n");
1362                 ret = -ENODEV;
1363                 goto clean_dma_ret;
1364         }
1365
1366         ndev->irq = platform_get_irq(pdev, 0);
1367         if (ndev->irq < 0) {
1368                 dev_err(priv->dev, "error getting irq resource\n");
1369                 ret = -ENOENT;
1370                 goto clean_ale_ret;
1371         }
1372
1373         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1374                 for (i = res->start; i <= res->end; i++) {
1375                         if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
1376                                         dev_name(&pdev->dev), priv)) {
1377                                 dev_err(priv->dev, "error attaching irq\n");
1378                                 goto clean_ale_ret;
1379                         }
1380                         priv->irqs_table[k] = i;
1381                         priv->num_irqs = k;
1382                 }
1383                 k++;
1384         }
1385
1386         ndev->flags |= IFF_ALLMULTI;    /* see cpsw_ndo_change_rx_flags() */
1387
1388         ndev->netdev_ops = &cpsw_netdev_ops;
1389         SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1390         netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1391
1392         /* register the network device */
1393         SET_NETDEV_DEV(ndev, &pdev->dev);
1394         ret = register_netdev(ndev);
1395         if (ret) {
1396                 dev_err(priv->dev, "error registering net device\n");
1397                 ret = -ENODEV;
1398                 goto clean_irq_ret;
1399         }
1400
1401         if (cpts_register(&pdev->dev, &priv->cpts,
1402                           data->cpts_clock_mult, data->cpts_clock_shift))
1403                 dev_err(priv->dev, "error registering cpts device\n");
1404
1405         cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
1406                   priv->cpsw_res->start, ndev->irq);
1407
1408         return 0;
1409
1410 clean_irq_ret:
1411         free_irq(ndev->irq, priv);
1412 clean_ale_ret:
1413         cpsw_ale_destroy(priv->ale);
1414 clean_dma_ret:
1415         cpdma_chan_destroy(priv->txch);
1416         cpdma_chan_destroy(priv->rxch);
1417         cpdma_ctlr_destroy(priv->dma);
1418 clean_wr_iomap_ret:
1419         iounmap(priv->wr_regs);
1420 clean_cpsw_wr_iores_ret:
1421         release_mem_region(priv->cpsw_wr_res->start,
1422                            resource_size(priv->cpsw_wr_res));
1423 clean_iomap_ret:
1424         iounmap(priv->regs);
1425 clean_cpsw_iores_ret:
1426         release_mem_region(priv->cpsw_res->start,
1427                            resource_size(priv->cpsw_res));
1428 clean_clk_ret:
1429         clk_put(priv->clk);
1430 clean_slave_ret:
1431         pm_runtime_disable(&pdev->dev);
1432         kfree(priv->slaves);
1433 clean_ndev_ret:
1434         free_netdev(ndev);
1435         return ret;
1436 }
1437
1438 static int __devexit cpsw_remove(struct platform_device *pdev)
1439 {
1440         struct net_device *ndev = platform_get_drvdata(pdev);
1441         struct cpsw_priv *priv = netdev_priv(ndev);
1442
1443         pr_info("removing device");
1444         platform_set_drvdata(pdev, NULL);
1445
1446         cpts_unregister(&priv->cpts);
1447         free_irq(ndev->irq, priv);
1448         cpsw_ale_destroy(priv->ale);
1449         cpdma_chan_destroy(priv->txch);
1450         cpdma_chan_destroy(priv->rxch);
1451         cpdma_ctlr_destroy(priv->dma);
1452         iounmap(priv->regs);
1453         release_mem_region(priv->cpsw_res->start,
1454                            resource_size(priv->cpsw_res));
1455         iounmap(priv->wr_regs);
1456         release_mem_region(priv->cpsw_wr_res->start,
1457                            resource_size(priv->cpsw_wr_res));
1458         pm_runtime_disable(&pdev->dev);
1459         clk_put(priv->clk);
1460         kfree(priv->slaves);
1461         free_netdev(ndev);
1462
1463         return 0;
1464 }
1465
1466 static int cpsw_suspend(struct device *dev)
1467 {
1468         struct platform_device  *pdev = to_platform_device(dev);
1469         struct net_device       *ndev = platform_get_drvdata(pdev);
1470
1471         if (netif_running(ndev))
1472                 cpsw_ndo_stop(ndev);
1473         pm_runtime_put_sync(&pdev->dev);
1474
1475         return 0;
1476 }
1477
1478 static int cpsw_resume(struct device *dev)
1479 {
1480         struct platform_device  *pdev = to_platform_device(dev);
1481         struct net_device       *ndev = platform_get_drvdata(pdev);
1482
1483         pm_runtime_get_sync(&pdev->dev);
1484         if (netif_running(ndev))
1485                 cpsw_ndo_open(ndev);
1486         return 0;
1487 }
1488
1489 static const struct dev_pm_ops cpsw_pm_ops = {
1490         .suspend        = cpsw_suspend,
1491         .resume         = cpsw_resume,
1492 };
1493
1494 static const struct of_device_id cpsw_of_mtable[] = {
1495         { .compatible = "ti,cpsw", },
1496         { /* sentinel */ },
1497 };
1498
1499 static struct platform_driver cpsw_driver = {
1500         .driver = {
1501                 .name    = "cpsw",
1502                 .owner   = THIS_MODULE,
1503                 .pm      = &cpsw_pm_ops,
1504                 .of_match_table = of_match_ptr(cpsw_of_mtable),
1505         },
1506         .probe = cpsw_probe,
1507         .remove = __devexit_p(cpsw_remove),
1508 };
1509
1510 static int __init cpsw_init(void)
1511 {
1512         return platform_driver_register(&cpsw_driver);
1513 }
1514 late_initcall(cpsw_init);
1515
1516 static void __exit cpsw_exit(void)
1517 {
1518         platform_driver_unregister(&cpsw_driver);
1519 }
1520 module_exit(cpsw_exit);
1521
1522 MODULE_LICENSE("GPL");
1523 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
1524 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
1525 MODULE_DESCRIPTION("TI CPSW Ethernet driver");