1 /* niu.c: Neptune ethernet driver.
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/netdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/etherdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/delay.h>
18 #include <linux/bitops.h>
19 #include <linux/mii.h>
21 #include <linux/if_ether.h>
22 #include <linux/if_vlan.h>
25 #include <linux/ipv6.h>
26 #include <linux/log2.h>
27 #include <linux/jiffies.h>
28 #include <linux/crc32.h>
29 #include <linux/list.h>
30 #include <linux/slab.h>
33 #include <linux/of_device.h>
37 #define DRV_MODULE_NAME "niu"
38 #define DRV_MODULE_VERSION "1.1"
39 #define DRV_MODULE_RELDATE "Apr 22, 2010"
41 static char version[] __devinitdata =
42 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
44 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
45 MODULE_DESCRIPTION("NIU ethernet driver");
46 MODULE_LICENSE("GPL");
47 MODULE_VERSION(DRV_MODULE_VERSION);
50 static u64 readq(void __iomem *reg)
52 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
55 static void writeq(u64 val, void __iomem *reg)
57 writel(val & 0xffffffff, reg);
58 writel(val >> 32, reg + 0x4UL);
62 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
63 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
67 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
69 #define NIU_TX_TIMEOUT (5 * HZ)
71 #define nr64(reg) readq(np->regs + (reg))
72 #define nw64(reg, val) writeq((val), np->regs + (reg))
74 #define nr64_mac(reg) readq(np->mac_regs + (reg))
75 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
77 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
78 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
80 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
81 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
83 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
84 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
86 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
89 static int debug = -1;
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "NIU debug level");
93 #define niu_lock_parent(np, flags) \
94 spin_lock_irqsave(&np->parent->lock, flags)
95 #define niu_unlock_parent(np, flags) \
96 spin_unlock_irqrestore(&np->parent->lock, flags)
98 static int serdes_init_10g_serdes(struct niu *np);
100 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
101 u64 bits, int limit, int delay)
103 while (--limit >= 0) {
104 u64 val = nr64_mac(reg);
115 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
116 u64 bits, int limit, int delay,
117 const char *reg_name)
122 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
124 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
125 (unsigned long long)bits, reg_name,
126 (unsigned long long)nr64_mac(reg));
130 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
131 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
132 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
135 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
136 u64 bits, int limit, int delay)
138 while (--limit >= 0) {
139 u64 val = nr64_ipp(reg);
150 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
151 u64 bits, int limit, int delay,
152 const char *reg_name)
161 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
163 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
164 (unsigned long long)bits, reg_name,
165 (unsigned long long)nr64_ipp(reg));
169 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
170 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
171 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
174 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
175 u64 bits, int limit, int delay)
177 while (--limit >= 0) {
189 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
190 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
191 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
194 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
195 u64 bits, int limit, int delay,
196 const char *reg_name)
201 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
203 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
204 (unsigned long long)bits, reg_name,
205 (unsigned long long)nr64(reg));
209 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
210 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
211 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
214 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
216 u64 val = (u64) lp->timer;
219 val |= LDG_IMGMT_ARM;
221 nw64(LDG_IMGMT(lp->ldg_num), val);
224 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
226 unsigned long mask_reg, bits;
229 if (ldn < 0 || ldn > LDN_MAX)
233 mask_reg = LD_IM0(ldn);
236 mask_reg = LD_IM1(ldn - 64);
240 val = nr64(mask_reg);
250 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
252 struct niu_parent *parent = np->parent;
255 for (i = 0; i <= LDN_MAX; i++) {
258 if (parent->ldg_map[i] != lp->ldg_num)
261 err = niu_ldn_irq_enable(np, i, on);
268 static int niu_enable_interrupts(struct niu *np, int on)
272 for (i = 0; i < np->num_ldg; i++) {
273 struct niu_ldg *lp = &np->ldg[i];
276 err = niu_enable_ldn_in_ldg(np, lp, on);
280 for (i = 0; i < np->num_ldg; i++)
281 niu_ldg_rearm(np, &np->ldg[i], on);
286 static u32 phy_encode(u32 type, int port)
288 return type << (port * 2);
291 static u32 phy_decode(u32 val, int port)
293 return (val >> (port * 2)) & PORT_TYPE_MASK;
296 static int mdio_wait(struct niu *np)
301 while (--limit > 0) {
302 val = nr64(MIF_FRAME_OUTPUT);
303 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
304 return val & MIF_FRAME_OUTPUT_DATA;
312 static int mdio_read(struct niu *np, int port, int dev, int reg)
316 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
321 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
322 return mdio_wait(np);
325 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
329 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
334 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
342 static int mii_read(struct niu *np, int port, int reg)
344 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
345 return mdio_wait(np);
348 static int mii_write(struct niu *np, int port, int reg, int data)
352 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
360 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
364 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
365 ESR2_TI_PLL_TX_CFG_L(channel),
368 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
369 ESR2_TI_PLL_TX_CFG_H(channel),
374 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
378 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
379 ESR2_TI_PLL_RX_CFG_L(channel),
382 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
383 ESR2_TI_PLL_RX_CFG_H(channel),
388 /* Mode is always 10G fiber. */
389 static int serdes_init_niu_10g_fiber(struct niu *np)
391 struct niu_link_config *lp = &np->link_config;
395 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
396 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
397 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
398 PLL_RX_CFG_EQ_LP_ADAPTIVE);
400 if (lp->loopback_mode == LOOPBACK_PHY) {
401 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
403 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
404 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
406 tx_cfg |= PLL_TX_CFG_ENTEST;
407 rx_cfg |= PLL_RX_CFG_ENTEST;
410 /* Initialize all 4 lanes of the SERDES. */
411 for (i = 0; i < 4; i++) {
412 int err = esr2_set_tx_cfg(np, i, tx_cfg);
417 for (i = 0; i < 4; i++) {
418 int err = esr2_set_rx_cfg(np, i, rx_cfg);
426 static int serdes_init_niu_1g_serdes(struct niu *np)
428 struct niu_link_config *lp = &np->link_config;
429 u16 pll_cfg, pll_sts;
431 u64 uninitialized_var(sig), mask, val;
436 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
437 PLL_TX_CFG_RATE_HALF);
438 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
439 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
440 PLL_RX_CFG_RATE_HALF);
443 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
445 if (lp->loopback_mode == LOOPBACK_PHY) {
446 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
448 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
449 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
451 tx_cfg |= PLL_TX_CFG_ENTEST;
452 rx_cfg |= PLL_RX_CFG_ENTEST;
455 /* Initialize PLL for 1G */
456 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
458 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
459 ESR2_TI_PLL_CFG_L, pll_cfg);
461 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
466 pll_sts = PLL_CFG_ENPLL;
468 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
469 ESR2_TI_PLL_STS_L, pll_sts);
471 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
478 /* Initialize all 4 lanes of the SERDES. */
479 for (i = 0; i < 4; i++) {
480 err = esr2_set_tx_cfg(np, i, tx_cfg);
485 for (i = 0; i < 4; i++) {
486 err = esr2_set_rx_cfg(np, i, rx_cfg);
493 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
498 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
506 while (max_retry--) {
507 sig = nr64(ESR_INT_SIGNALS);
508 if ((sig & mask) == val)
514 if ((sig & mask) != val) {
515 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
516 np->port, (int)(sig & mask), (int)val);
523 static int serdes_init_niu_10g_serdes(struct niu *np)
525 struct niu_link_config *lp = &np->link_config;
526 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
528 u64 uninitialized_var(sig), mask, val;
532 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
533 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
534 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
535 PLL_RX_CFG_EQ_LP_ADAPTIVE);
537 if (lp->loopback_mode == LOOPBACK_PHY) {
538 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
540 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
541 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
543 tx_cfg |= PLL_TX_CFG_ENTEST;
544 rx_cfg |= PLL_RX_CFG_ENTEST;
547 /* Initialize PLL for 10G */
548 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
550 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
551 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
553 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
558 pll_sts = PLL_CFG_ENPLL;
560 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
561 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
563 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
570 /* Initialize all 4 lanes of the SERDES. */
571 for (i = 0; i < 4; i++) {
572 err = esr2_set_tx_cfg(np, i, tx_cfg);
577 for (i = 0; i < 4; i++) {
578 err = esr2_set_rx_cfg(np, i, rx_cfg);
583 /* check if serdes is ready */
587 mask = ESR_INT_SIGNALS_P0_BITS;
588 val = (ESR_INT_SRDY0_P0 |
598 mask = ESR_INT_SIGNALS_P1_BITS;
599 val = (ESR_INT_SRDY0_P1 |
612 while (max_retry--) {
613 sig = nr64(ESR_INT_SIGNALS);
614 if ((sig & mask) == val)
620 if ((sig & mask) != val) {
621 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
622 np->port, (int)(sig & mask), (int)val);
624 /* 10G failed, try initializing at 1G */
625 err = serdes_init_niu_1g_serdes(np);
627 np->flags &= ~NIU_FLAGS_10G;
628 np->mac_xcvr = MAC_XCVR_PCS;
630 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
638 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
642 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
644 *val = (err & 0xffff);
645 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
646 ESR_RXTX_CTRL_H(chan));
648 *val |= ((err & 0xffff) << 16);
654 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
658 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
659 ESR_GLUE_CTRL0_L(chan));
661 *val = (err & 0xffff);
662 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
663 ESR_GLUE_CTRL0_H(chan));
665 *val |= ((err & 0xffff) << 16);
672 static int esr_read_reset(struct niu *np, u32 *val)
676 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
677 ESR_RXTX_RESET_CTRL_L);
679 *val = (err & 0xffff);
680 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
681 ESR_RXTX_RESET_CTRL_H);
683 *val |= ((err & 0xffff) << 16);
690 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
694 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
695 ESR_RXTX_CTRL_L(chan), val & 0xffff);
697 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
698 ESR_RXTX_CTRL_H(chan), (val >> 16));
702 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
706 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
707 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
709 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
710 ESR_GLUE_CTRL0_H(chan), (val >> 16));
714 static int esr_reset(struct niu *np)
716 u32 uninitialized_var(reset);
719 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
720 ESR_RXTX_RESET_CTRL_L, 0x0000);
723 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
724 ESR_RXTX_RESET_CTRL_H, 0xffff);
729 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
730 ESR_RXTX_RESET_CTRL_L, 0xffff);
735 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
736 ESR_RXTX_RESET_CTRL_H, 0x0000);
741 err = esr_read_reset(np, &reset);
745 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
753 static int serdes_init_10g(struct niu *np)
755 struct niu_link_config *lp = &np->link_config;
756 unsigned long ctrl_reg, test_cfg_reg, i;
757 u64 ctrl_val, test_cfg_val, sig, mask, val;
762 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
763 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
766 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
767 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
773 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
774 ENET_SERDES_CTRL_SDET_1 |
775 ENET_SERDES_CTRL_SDET_2 |
776 ENET_SERDES_CTRL_SDET_3 |
777 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
778 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
779 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
780 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
781 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
783 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
784 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
787 if (lp->loopback_mode == LOOPBACK_PHY) {
788 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
789 ENET_SERDES_TEST_MD_0_SHIFT) |
790 (ENET_TEST_MD_PAD_LOOPBACK <<
791 ENET_SERDES_TEST_MD_1_SHIFT) |
792 (ENET_TEST_MD_PAD_LOOPBACK <<
793 ENET_SERDES_TEST_MD_2_SHIFT) |
794 (ENET_TEST_MD_PAD_LOOPBACK <<
795 ENET_SERDES_TEST_MD_3_SHIFT));
798 nw64(ctrl_reg, ctrl_val);
799 nw64(test_cfg_reg, test_cfg_val);
801 /* Initialize all 4 lanes of the SERDES. */
802 for (i = 0; i < 4; i++) {
803 u32 rxtx_ctrl, glue0;
805 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
808 err = esr_read_glue0(np, i, &glue0);
812 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
813 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
814 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
816 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
817 ESR_GLUE_CTRL0_THCNT |
818 ESR_GLUE_CTRL0_BLTIME);
819 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
820 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
821 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
822 (BLTIME_300_CYCLES <<
823 ESR_GLUE_CTRL0_BLTIME_SHIFT));
825 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
828 err = esr_write_glue0(np, i, glue0);
837 sig = nr64(ESR_INT_SIGNALS);
840 mask = ESR_INT_SIGNALS_P0_BITS;
841 val = (ESR_INT_SRDY0_P0 |
851 mask = ESR_INT_SIGNALS_P1_BITS;
852 val = (ESR_INT_SRDY0_P1 |
865 if ((sig & mask) != val) {
866 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
867 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
870 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
871 np->port, (int)(sig & mask), (int)val);
874 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
875 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
879 static int serdes_init_1g(struct niu *np)
883 val = nr64(ENET_SERDES_1_PLL_CFG);
884 val &= ~ENET_SERDES_PLL_FBDIV2;
887 val |= ENET_SERDES_PLL_HRATE0;
890 val |= ENET_SERDES_PLL_HRATE1;
893 val |= ENET_SERDES_PLL_HRATE2;
896 val |= ENET_SERDES_PLL_HRATE3;
901 nw64(ENET_SERDES_1_PLL_CFG, val);
906 static int serdes_init_1g_serdes(struct niu *np)
908 struct niu_link_config *lp = &np->link_config;
909 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
910 u64 ctrl_val, test_cfg_val, sig, mask, val;
912 u64 reset_val, val_rd;
914 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
915 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
916 ENET_SERDES_PLL_FBDIV0;
919 reset_val = ENET_SERDES_RESET_0;
920 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
921 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
922 pll_cfg = ENET_SERDES_0_PLL_CFG;
925 reset_val = ENET_SERDES_RESET_1;
926 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
927 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
928 pll_cfg = ENET_SERDES_1_PLL_CFG;
934 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
935 ENET_SERDES_CTRL_SDET_1 |
936 ENET_SERDES_CTRL_SDET_2 |
937 ENET_SERDES_CTRL_SDET_3 |
938 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
939 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
940 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
941 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
942 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
944 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
945 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
948 if (lp->loopback_mode == LOOPBACK_PHY) {
949 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
950 ENET_SERDES_TEST_MD_0_SHIFT) |
951 (ENET_TEST_MD_PAD_LOOPBACK <<
952 ENET_SERDES_TEST_MD_1_SHIFT) |
953 (ENET_TEST_MD_PAD_LOOPBACK <<
954 ENET_SERDES_TEST_MD_2_SHIFT) |
955 (ENET_TEST_MD_PAD_LOOPBACK <<
956 ENET_SERDES_TEST_MD_3_SHIFT));
959 nw64(ENET_SERDES_RESET, reset_val);
961 val_rd = nr64(ENET_SERDES_RESET);
962 val_rd &= ~reset_val;
964 nw64(ctrl_reg, ctrl_val);
965 nw64(test_cfg_reg, test_cfg_val);
966 nw64(ENET_SERDES_RESET, val_rd);
969 /* Initialize all 4 lanes of the SERDES. */
970 for (i = 0; i < 4; i++) {
971 u32 rxtx_ctrl, glue0;
973 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
976 err = esr_read_glue0(np, i, &glue0);
980 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
981 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
982 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
984 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
985 ESR_GLUE_CTRL0_THCNT |
986 ESR_GLUE_CTRL0_BLTIME);
987 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
988 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
989 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
990 (BLTIME_300_CYCLES <<
991 ESR_GLUE_CTRL0_BLTIME_SHIFT));
993 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
996 err = esr_write_glue0(np, i, glue0);
1002 sig = nr64(ESR_INT_SIGNALS);
1005 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1010 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1018 if ((sig & mask) != val) {
1019 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1020 np->port, (int)(sig & mask), (int)val);
1027 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1029 struct niu_link_config *lp = &np->link_config;
1033 unsigned long flags;
1037 current_speed = SPEED_INVALID;
1038 current_duplex = DUPLEX_INVALID;
1040 spin_lock_irqsave(&np->lock, flags);
1042 val = nr64_pcs(PCS_MII_STAT);
1044 if (val & PCS_MII_STAT_LINK_STATUS) {
1046 current_speed = SPEED_1000;
1047 current_duplex = DUPLEX_FULL;
1050 lp->active_speed = current_speed;
1051 lp->active_duplex = current_duplex;
1052 spin_unlock_irqrestore(&np->lock, flags);
1054 *link_up_p = link_up;
1058 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1060 unsigned long flags;
1061 struct niu_link_config *lp = &np->link_config;
1068 if (!(np->flags & NIU_FLAGS_10G))
1069 return link_status_1g_serdes(np, link_up_p);
1071 current_speed = SPEED_INVALID;
1072 current_duplex = DUPLEX_INVALID;
1073 spin_lock_irqsave(&np->lock, flags);
1075 val = nr64_xpcs(XPCS_STATUS(0));
1076 val2 = nr64_mac(XMAC_INTER2);
1077 if (val2 & 0x01000000)
1080 if ((val & 0x1000ULL) && link_ok) {
1082 current_speed = SPEED_10000;
1083 current_duplex = DUPLEX_FULL;
1085 lp->active_speed = current_speed;
1086 lp->active_duplex = current_duplex;
1087 spin_unlock_irqrestore(&np->lock, flags);
1088 *link_up_p = link_up;
1092 static int link_status_mii(struct niu *np, int *link_up_p)
1094 struct niu_link_config *lp = &np->link_config;
1096 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1097 int supported, advertising, active_speed, active_duplex;
1099 err = mii_read(np, np->phy_addr, MII_BMCR);
1100 if (unlikely(err < 0))
1104 err = mii_read(np, np->phy_addr, MII_BMSR);
1105 if (unlikely(err < 0))
1109 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1110 if (unlikely(err < 0))
1114 err = mii_read(np, np->phy_addr, MII_LPA);
1115 if (unlikely(err < 0))
1119 if (likely(bmsr & BMSR_ESTATEN)) {
1120 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1121 if (unlikely(err < 0))
1125 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1126 if (unlikely(err < 0))
1130 err = mii_read(np, np->phy_addr, MII_STAT1000);
1131 if (unlikely(err < 0))
1135 estatus = ctrl1000 = stat1000 = 0;
1138 if (bmsr & BMSR_ANEGCAPABLE)
1139 supported |= SUPPORTED_Autoneg;
1140 if (bmsr & BMSR_10HALF)
1141 supported |= SUPPORTED_10baseT_Half;
1142 if (bmsr & BMSR_10FULL)
1143 supported |= SUPPORTED_10baseT_Full;
1144 if (bmsr & BMSR_100HALF)
1145 supported |= SUPPORTED_100baseT_Half;
1146 if (bmsr & BMSR_100FULL)
1147 supported |= SUPPORTED_100baseT_Full;
1148 if (estatus & ESTATUS_1000_THALF)
1149 supported |= SUPPORTED_1000baseT_Half;
1150 if (estatus & ESTATUS_1000_TFULL)
1151 supported |= SUPPORTED_1000baseT_Full;
1152 lp->supported = supported;
1154 advertising = mii_adv_to_ethtool_adv_t(advert);
1155 advertising |= mii_ctrl1000_to_ethtool_adv_t(ctrl1000);
1157 if (bmcr & BMCR_ANENABLE) {
1160 lp->active_autoneg = 1;
1161 advertising |= ADVERTISED_Autoneg;
1164 neg1000 = (ctrl1000 << 2) & stat1000;
1166 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1167 active_speed = SPEED_1000;
1168 else if (neg & LPA_100)
1169 active_speed = SPEED_100;
1170 else if (neg & (LPA_10HALF | LPA_10FULL))
1171 active_speed = SPEED_10;
1173 active_speed = SPEED_INVALID;
1175 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1176 active_duplex = DUPLEX_FULL;
1177 else if (active_speed != SPEED_INVALID)
1178 active_duplex = DUPLEX_HALF;
1180 active_duplex = DUPLEX_INVALID;
1182 lp->active_autoneg = 0;
1184 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1185 active_speed = SPEED_1000;
1186 else if (bmcr & BMCR_SPEED100)
1187 active_speed = SPEED_100;
1189 active_speed = SPEED_10;
1191 if (bmcr & BMCR_FULLDPLX)
1192 active_duplex = DUPLEX_FULL;
1194 active_duplex = DUPLEX_HALF;
1197 lp->active_advertising = advertising;
1198 lp->active_speed = active_speed;
1199 lp->active_duplex = active_duplex;
1200 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1205 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1207 struct niu_link_config *lp = &np->link_config;
1208 u16 current_speed, bmsr;
1209 unsigned long flags;
1214 current_speed = SPEED_INVALID;
1215 current_duplex = DUPLEX_INVALID;
1217 spin_lock_irqsave(&np->lock, flags);
1221 err = mii_read(np, np->phy_addr, MII_BMSR);
1226 if (bmsr & BMSR_LSTATUS) {
1229 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1234 err = mii_read(np, np->phy_addr, MII_LPA);
1239 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1243 current_speed = SPEED_1000;
1244 current_duplex = DUPLEX_FULL;
1247 lp->active_speed = current_speed;
1248 lp->active_duplex = current_duplex;
1252 spin_unlock_irqrestore(&np->lock, flags);
1254 *link_up_p = link_up;
1258 static int link_status_1g(struct niu *np, int *link_up_p)
1260 struct niu_link_config *lp = &np->link_config;
1261 unsigned long flags;
1264 spin_lock_irqsave(&np->lock, flags);
1266 err = link_status_mii(np, link_up_p);
1267 lp->supported |= SUPPORTED_TP;
1268 lp->active_advertising |= ADVERTISED_TP;
1270 spin_unlock_irqrestore(&np->lock, flags);
1274 static int bcm8704_reset(struct niu *np)
1278 err = mdio_read(np, np->phy_addr,
1279 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1280 if (err < 0 || err == 0xffff)
1283 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1289 while (--limit >= 0) {
1290 err = mdio_read(np, np->phy_addr,
1291 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1294 if (!(err & BMCR_RESET))
1298 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1299 np->port, (err & 0xffff));
1305 /* When written, certain PHY registers need to be read back twice
1306 * in order for the bits to settle properly.
1308 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1310 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1313 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1319 static int bcm8706_init_user_dev3(struct niu *np)
1324 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1325 BCM8704_USER_OPT_DIGITAL_CTRL);
1328 err &= ~USER_ODIG_CTRL_GPIOS;
1329 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1330 err |= USER_ODIG_CTRL_RESV2;
1331 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1332 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1341 static int bcm8704_init_user_dev3(struct niu *np)
1345 err = mdio_write(np, np->phy_addr,
1346 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1347 (USER_CONTROL_OPTXRST_LVL |
1348 USER_CONTROL_OPBIASFLT_LVL |
1349 USER_CONTROL_OBTMPFLT_LVL |
1350 USER_CONTROL_OPPRFLT_LVL |
1351 USER_CONTROL_OPTXFLT_LVL |
1352 USER_CONTROL_OPRXLOS_LVL |
1353 USER_CONTROL_OPRXFLT_LVL |
1354 USER_CONTROL_OPTXON_LVL |
1355 (0x3f << USER_CONTROL_RES1_SHIFT)));
1359 err = mdio_write(np, np->phy_addr,
1360 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1361 (USER_PMD_TX_CTL_XFP_CLKEN |
1362 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1363 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1364 USER_PMD_TX_CTL_TSCK_LPWREN));
1368 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1371 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1375 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1376 BCM8704_USER_OPT_DIGITAL_CTRL);
1379 err &= ~USER_ODIG_CTRL_GPIOS;
1380 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1381 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1382 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1391 static int mrvl88x2011_act_led(struct niu *np, int val)
1395 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1396 MRVL88X2011_LED_8_TO_11_CTL);
1400 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1401 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1403 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1404 MRVL88X2011_LED_8_TO_11_CTL, err);
1407 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1411 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1412 MRVL88X2011_LED_BLINK_CTL);
1414 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1417 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1418 MRVL88X2011_LED_BLINK_CTL, err);
1424 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1428 /* Set LED functions */
1429 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1434 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1438 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1439 MRVL88X2011_GENERAL_CTL);
1443 err |= MRVL88X2011_ENA_XFPREFCLK;
1445 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1446 MRVL88X2011_GENERAL_CTL, err);
1450 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1451 MRVL88X2011_PMA_PMD_CTL_1);
1455 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1456 err |= MRVL88X2011_LOOPBACK;
1458 err &= ~MRVL88X2011_LOOPBACK;
1460 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1461 MRVL88X2011_PMA_PMD_CTL_1, err);
1466 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1467 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1471 static int xcvr_diag_bcm870x(struct niu *np)
1473 u16 analog_stat0, tx_alarm_status;
1477 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1481 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1483 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1486 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1488 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1492 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1495 /* XXX dig this out it might not be so useful XXX */
1496 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1497 BCM8704_USER_ANALOG_STATUS0);
1500 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1501 BCM8704_USER_ANALOG_STATUS0);
1506 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1507 BCM8704_USER_TX_ALARM_STATUS);
1510 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1511 BCM8704_USER_TX_ALARM_STATUS);
1514 tx_alarm_status = err;
1516 if (analog_stat0 != 0x03fc) {
1517 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1518 pr_info("Port %u cable not connected or bad cable\n",
1520 } else if (analog_stat0 == 0x639c) {
1521 pr_info("Port %u optical module is bad or missing\n",
1529 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1531 struct niu_link_config *lp = &np->link_config;
1534 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1539 err &= ~BMCR_LOOPBACK;
1541 if (lp->loopback_mode == LOOPBACK_MAC)
1542 err |= BMCR_LOOPBACK;
1544 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1552 static int xcvr_init_10g_bcm8706(struct niu *np)
1557 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1558 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1561 val = nr64_mac(XMAC_CONFIG);
1562 val &= ~XMAC_CONFIG_LED_POLARITY;
1563 val |= XMAC_CONFIG_FORCE_LED_ON;
1564 nw64_mac(XMAC_CONFIG, val);
1566 val = nr64(MIF_CONFIG);
1567 val |= MIF_CONFIG_INDIRECT_MODE;
1568 nw64(MIF_CONFIG, val);
1570 err = bcm8704_reset(np);
1574 err = xcvr_10g_set_lb_bcm870x(np);
1578 err = bcm8706_init_user_dev3(np);
1582 err = xcvr_diag_bcm870x(np);
1589 static int xcvr_init_10g_bcm8704(struct niu *np)
1593 err = bcm8704_reset(np);
1597 err = bcm8704_init_user_dev3(np);
1601 err = xcvr_10g_set_lb_bcm870x(np);
1605 err = xcvr_diag_bcm870x(np);
1612 static int xcvr_init_10g(struct niu *np)
1617 val = nr64_mac(XMAC_CONFIG);
1618 val &= ~XMAC_CONFIG_LED_POLARITY;
1619 val |= XMAC_CONFIG_FORCE_LED_ON;
1620 nw64_mac(XMAC_CONFIG, val);
1622 /* XXX shared resource, lock parent XXX */
1623 val = nr64(MIF_CONFIG);
1624 val |= MIF_CONFIG_INDIRECT_MODE;
1625 nw64(MIF_CONFIG, val);
1627 phy_id = phy_decode(np->parent->port_phy, np->port);
1628 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1630 /* handle different phy types */
1631 switch (phy_id & NIU_PHY_ID_MASK) {
1632 case NIU_PHY_ID_MRVL88X2011:
1633 err = xcvr_init_10g_mrvl88x2011(np);
1636 default: /* bcom 8704 */
1637 err = xcvr_init_10g_bcm8704(np);
1644 static int mii_reset(struct niu *np)
1648 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1653 while (--limit >= 0) {
1655 err = mii_read(np, np->phy_addr, MII_BMCR);
1658 if (!(err & BMCR_RESET))
1662 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1670 static int xcvr_init_1g_rgmii(struct niu *np)
1674 u16 bmcr, bmsr, estat;
1676 val = nr64(MIF_CONFIG);
1677 val &= ~MIF_CONFIG_INDIRECT_MODE;
1678 nw64(MIF_CONFIG, val);
1680 err = mii_reset(np);
1684 err = mii_read(np, np->phy_addr, MII_BMSR);
1690 if (bmsr & BMSR_ESTATEN) {
1691 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1698 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1702 if (bmsr & BMSR_ESTATEN) {
1705 if (estat & ESTATUS_1000_TFULL)
1706 ctrl1000 |= ADVERTISE_1000FULL;
1707 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1712 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1714 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1718 err = mii_read(np, np->phy_addr, MII_BMCR);
1721 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1723 err = mii_read(np, np->phy_addr, MII_BMSR);
1730 static int mii_init_common(struct niu *np)
1732 struct niu_link_config *lp = &np->link_config;
1733 u16 bmcr, bmsr, adv, estat;
1736 err = mii_reset(np);
1740 err = mii_read(np, np->phy_addr, MII_BMSR);
1746 if (bmsr & BMSR_ESTATEN) {
1747 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1754 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1758 if (lp->loopback_mode == LOOPBACK_MAC) {
1759 bmcr |= BMCR_LOOPBACK;
1760 if (lp->active_speed == SPEED_1000)
1761 bmcr |= BMCR_SPEED1000;
1762 if (lp->active_duplex == DUPLEX_FULL)
1763 bmcr |= BMCR_FULLDPLX;
1766 if (lp->loopback_mode == LOOPBACK_PHY) {
1769 aux = (BCM5464R_AUX_CTL_EXT_LB |
1770 BCM5464R_AUX_CTL_WRITE_1);
1771 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1779 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1780 if ((bmsr & BMSR_10HALF) &&
1781 (lp->advertising & ADVERTISED_10baseT_Half))
1782 adv |= ADVERTISE_10HALF;
1783 if ((bmsr & BMSR_10FULL) &&
1784 (lp->advertising & ADVERTISED_10baseT_Full))
1785 adv |= ADVERTISE_10FULL;
1786 if ((bmsr & BMSR_100HALF) &&
1787 (lp->advertising & ADVERTISED_100baseT_Half))
1788 adv |= ADVERTISE_100HALF;
1789 if ((bmsr & BMSR_100FULL) &&
1790 (lp->advertising & ADVERTISED_100baseT_Full))
1791 adv |= ADVERTISE_100FULL;
1792 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1796 if (likely(bmsr & BMSR_ESTATEN)) {
1798 if ((estat & ESTATUS_1000_THALF) &&
1799 (lp->advertising & ADVERTISED_1000baseT_Half))
1800 ctrl1000 |= ADVERTISE_1000HALF;
1801 if ((estat & ESTATUS_1000_TFULL) &&
1802 (lp->advertising & ADVERTISED_1000baseT_Full))
1803 ctrl1000 |= ADVERTISE_1000FULL;
1804 err = mii_write(np, np->phy_addr,
1805 MII_CTRL1000, ctrl1000);
1810 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1815 if (lp->duplex == DUPLEX_FULL) {
1816 bmcr |= BMCR_FULLDPLX;
1818 } else if (lp->duplex == DUPLEX_HALF)
1823 if (lp->speed == SPEED_1000) {
1824 /* if X-full requested while not supported, or
1825 X-half requested while not supported... */
1826 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1827 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1829 bmcr |= BMCR_SPEED1000;
1830 } else if (lp->speed == SPEED_100) {
1831 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1832 (!fulldpx && !(bmsr & BMSR_100HALF)))
1834 bmcr |= BMCR_SPEED100;
1835 } else if (lp->speed == SPEED_10) {
1836 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1837 (!fulldpx && !(bmsr & BMSR_10HALF)))
1843 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1848 err = mii_read(np, np->phy_addr, MII_BMCR);
1853 err = mii_read(np, np->phy_addr, MII_BMSR);
1858 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1859 np->port, bmcr, bmsr);
1865 static int xcvr_init_1g(struct niu *np)
1869 /* XXX shared resource, lock parent XXX */
1870 val = nr64(MIF_CONFIG);
1871 val &= ~MIF_CONFIG_INDIRECT_MODE;
1872 nw64(MIF_CONFIG, val);
1874 return mii_init_common(np);
1877 static int niu_xcvr_init(struct niu *np)
1879 const struct niu_phy_ops *ops = np->phy_ops;
1884 err = ops->xcvr_init(np);
1889 static int niu_serdes_init(struct niu *np)
1891 const struct niu_phy_ops *ops = np->phy_ops;
1895 if (ops->serdes_init)
1896 err = ops->serdes_init(np);
1901 static void niu_init_xif(struct niu *);
1902 static void niu_handle_led(struct niu *, int status);
1904 static int niu_link_status_common(struct niu *np, int link_up)
1906 struct niu_link_config *lp = &np->link_config;
1907 struct net_device *dev = np->dev;
1908 unsigned long flags;
1910 if (!netif_carrier_ok(dev) && link_up) {
1911 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1912 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1913 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1914 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1916 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1918 spin_lock_irqsave(&np->lock, flags);
1920 niu_handle_led(np, 1);
1921 spin_unlock_irqrestore(&np->lock, flags);
1923 netif_carrier_on(dev);
1924 } else if (netif_carrier_ok(dev) && !link_up) {
1925 netif_warn(np, link, dev, "Link is down\n");
1926 spin_lock_irqsave(&np->lock, flags);
1927 niu_handle_led(np, 0);
1928 spin_unlock_irqrestore(&np->lock, flags);
1929 netif_carrier_off(dev);
1935 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1937 int err, link_up, pma_status, pcs_status;
1941 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1942 MRVL88X2011_10G_PMD_STATUS_2);
1946 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1947 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1948 MRVL88X2011_PMA_PMD_STATUS_1);
1952 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1954 /* Check PMC Register : 3.0001.2 == 1: read twice */
1955 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1956 MRVL88X2011_PMA_PMD_STATUS_1);
1960 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1961 MRVL88X2011_PMA_PMD_STATUS_1);
1965 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1967 /* Check XGXS Register : 4.0018.[0-3,12] */
1968 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1969 MRVL88X2011_10G_XGXS_LANE_STAT);
1973 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1974 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1975 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1977 link_up = (pma_status && pcs_status) ? 1 : 0;
1979 np->link_config.active_speed = SPEED_10000;
1980 np->link_config.active_duplex = DUPLEX_FULL;
1983 mrvl88x2011_act_led(np, (link_up ?
1984 MRVL88X2011_LED_CTL_PCS_ACT :
1985 MRVL88X2011_LED_CTL_OFF));
1987 *link_up_p = link_up;
1991 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
1996 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1997 BCM8704_PMD_RCV_SIGDET);
1998 if (err < 0 || err == 0xffff)
2000 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2005 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2006 BCM8704_PCS_10G_R_STATUS);
2010 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2015 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2016 BCM8704_PHYXS_XGXS_LANE_STAT);
2019 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2020 PHYXS_XGXS_LANE_STAT_MAGIC |
2021 PHYXS_XGXS_LANE_STAT_PATTEST |
2022 PHYXS_XGXS_LANE_STAT_LANE3 |
2023 PHYXS_XGXS_LANE_STAT_LANE2 |
2024 PHYXS_XGXS_LANE_STAT_LANE1 |
2025 PHYXS_XGXS_LANE_STAT_LANE0)) {
2027 np->link_config.active_speed = SPEED_INVALID;
2028 np->link_config.active_duplex = DUPLEX_INVALID;
2033 np->link_config.active_speed = SPEED_10000;
2034 np->link_config.active_duplex = DUPLEX_FULL;
2038 *link_up_p = link_up;
2042 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2048 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2049 BCM8704_PMD_RCV_SIGDET);
2052 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2057 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2058 BCM8704_PCS_10G_R_STATUS);
2061 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2066 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2067 BCM8704_PHYXS_XGXS_LANE_STAT);
2071 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2072 PHYXS_XGXS_LANE_STAT_MAGIC |
2073 PHYXS_XGXS_LANE_STAT_LANE3 |
2074 PHYXS_XGXS_LANE_STAT_LANE2 |
2075 PHYXS_XGXS_LANE_STAT_LANE1 |
2076 PHYXS_XGXS_LANE_STAT_LANE0)) {
2082 np->link_config.active_speed = SPEED_10000;
2083 np->link_config.active_duplex = DUPLEX_FULL;
2087 *link_up_p = link_up;
2091 static int link_status_10g(struct niu *np, int *link_up_p)
2093 unsigned long flags;
2096 spin_lock_irqsave(&np->lock, flags);
2098 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2101 phy_id = phy_decode(np->parent->port_phy, np->port);
2102 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2104 /* handle different phy types */
2105 switch (phy_id & NIU_PHY_ID_MASK) {
2106 case NIU_PHY_ID_MRVL88X2011:
2107 err = link_status_10g_mrvl(np, link_up_p);
2110 default: /* bcom 8704 */
2111 err = link_status_10g_bcom(np, link_up_p);
2116 spin_unlock_irqrestore(&np->lock, flags);
2121 static int niu_10g_phy_present(struct niu *np)
2125 sig = nr64(ESR_INT_SIGNALS);
2128 mask = ESR_INT_SIGNALS_P0_BITS;
2129 val = (ESR_INT_SRDY0_P0 |
2132 ESR_INT_XDP_P0_CH3 |
2133 ESR_INT_XDP_P0_CH2 |
2134 ESR_INT_XDP_P0_CH1 |
2135 ESR_INT_XDP_P0_CH0);
2139 mask = ESR_INT_SIGNALS_P1_BITS;
2140 val = (ESR_INT_SRDY0_P1 |
2143 ESR_INT_XDP_P1_CH3 |
2144 ESR_INT_XDP_P1_CH2 |
2145 ESR_INT_XDP_P1_CH1 |
2146 ESR_INT_XDP_P1_CH0);
2153 if ((sig & mask) != val)
2158 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2160 unsigned long flags;
2163 int phy_present_prev;
2165 spin_lock_irqsave(&np->lock, flags);
2167 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2168 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2170 phy_present = niu_10g_phy_present(np);
2171 if (phy_present != phy_present_prev) {
2174 /* A NEM was just plugged in */
2175 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2176 if (np->phy_ops->xcvr_init)
2177 err = np->phy_ops->xcvr_init(np);
2179 err = mdio_read(np, np->phy_addr,
2180 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2181 if (err == 0xffff) {
2182 /* No mdio, back-to-back XAUI */
2186 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2189 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2191 netif_warn(np, link, np->dev,
2192 "Hotplug PHY Removed\n");
2196 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2197 err = link_status_10g_bcm8706(np, link_up_p);
2198 if (err == 0xffff) {
2199 /* No mdio, back-to-back XAUI: it is C10NEM */
2201 np->link_config.active_speed = SPEED_10000;
2202 np->link_config.active_duplex = DUPLEX_FULL;
2207 spin_unlock_irqrestore(&np->lock, flags);
2212 static int niu_link_status(struct niu *np, int *link_up_p)
2214 const struct niu_phy_ops *ops = np->phy_ops;
2218 if (ops->link_status)
2219 err = ops->link_status(np, link_up_p);
2224 static void niu_timer(unsigned long __opaque)
2226 struct niu *np = (struct niu *) __opaque;
2230 err = niu_link_status(np, &link_up);
2232 niu_link_status_common(np, link_up);
2234 if (netif_carrier_ok(np->dev))
2238 np->timer.expires = jiffies + off;
2240 add_timer(&np->timer);
2243 static const struct niu_phy_ops phy_ops_10g_serdes = {
2244 .serdes_init = serdes_init_10g_serdes,
2245 .link_status = link_status_10g_serdes,
2248 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2249 .serdes_init = serdes_init_niu_10g_serdes,
2250 .link_status = link_status_10g_serdes,
2253 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2254 .serdes_init = serdes_init_niu_1g_serdes,
2255 .link_status = link_status_1g_serdes,
2258 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2259 .xcvr_init = xcvr_init_1g_rgmii,
2260 .link_status = link_status_1g_rgmii,
2263 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2264 .serdes_init = serdes_init_niu_10g_fiber,
2265 .xcvr_init = xcvr_init_10g,
2266 .link_status = link_status_10g,
2269 static const struct niu_phy_ops phy_ops_10g_fiber = {
2270 .serdes_init = serdes_init_10g,
2271 .xcvr_init = xcvr_init_10g,
2272 .link_status = link_status_10g,
2275 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2276 .serdes_init = serdes_init_10g,
2277 .xcvr_init = xcvr_init_10g_bcm8706,
2278 .link_status = link_status_10g_hotplug,
2281 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2282 .serdes_init = serdes_init_niu_10g_fiber,
2283 .xcvr_init = xcvr_init_10g_bcm8706,
2284 .link_status = link_status_10g_hotplug,
2287 static const struct niu_phy_ops phy_ops_10g_copper = {
2288 .serdes_init = serdes_init_10g,
2289 .link_status = link_status_10g, /* XXX */
2292 static const struct niu_phy_ops phy_ops_1g_fiber = {
2293 .serdes_init = serdes_init_1g,
2294 .xcvr_init = xcvr_init_1g,
2295 .link_status = link_status_1g,
2298 static const struct niu_phy_ops phy_ops_1g_copper = {
2299 .xcvr_init = xcvr_init_1g,
2300 .link_status = link_status_1g,
2303 struct niu_phy_template {
2304 const struct niu_phy_ops *ops;
2308 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2309 .ops = &phy_ops_10g_fiber_niu,
2310 .phy_addr_base = 16,
2313 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2314 .ops = &phy_ops_10g_serdes_niu,
2318 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2319 .ops = &phy_ops_1g_serdes_niu,
2323 static const struct niu_phy_template phy_template_10g_fiber = {
2324 .ops = &phy_ops_10g_fiber,
2328 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2329 .ops = &phy_ops_10g_fiber_hotplug,
2333 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2334 .ops = &phy_ops_niu_10g_hotplug,
2338 static const struct niu_phy_template phy_template_10g_copper = {
2339 .ops = &phy_ops_10g_copper,
2340 .phy_addr_base = 10,
2343 static const struct niu_phy_template phy_template_1g_fiber = {
2344 .ops = &phy_ops_1g_fiber,
2348 static const struct niu_phy_template phy_template_1g_copper = {
2349 .ops = &phy_ops_1g_copper,
2353 static const struct niu_phy_template phy_template_1g_rgmii = {
2354 .ops = &phy_ops_1g_rgmii,
2358 static const struct niu_phy_template phy_template_10g_serdes = {
2359 .ops = &phy_ops_10g_serdes,
2363 static int niu_atca_port_num[4] = {
2367 static int serdes_init_10g_serdes(struct niu *np)
2369 struct niu_link_config *lp = &np->link_config;
2370 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2371 u64 ctrl_val, test_cfg_val, sig, mask, val;
2375 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2376 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2377 pll_cfg = ENET_SERDES_0_PLL_CFG;
2380 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2381 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2382 pll_cfg = ENET_SERDES_1_PLL_CFG;
2388 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2389 ENET_SERDES_CTRL_SDET_1 |
2390 ENET_SERDES_CTRL_SDET_2 |
2391 ENET_SERDES_CTRL_SDET_3 |
2392 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2393 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2394 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2395 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2396 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2397 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2398 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2399 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2402 if (lp->loopback_mode == LOOPBACK_PHY) {
2403 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2404 ENET_SERDES_TEST_MD_0_SHIFT) |
2405 (ENET_TEST_MD_PAD_LOOPBACK <<
2406 ENET_SERDES_TEST_MD_1_SHIFT) |
2407 (ENET_TEST_MD_PAD_LOOPBACK <<
2408 ENET_SERDES_TEST_MD_2_SHIFT) |
2409 (ENET_TEST_MD_PAD_LOOPBACK <<
2410 ENET_SERDES_TEST_MD_3_SHIFT));
2414 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2415 nw64(ctrl_reg, ctrl_val);
2416 nw64(test_cfg_reg, test_cfg_val);
2418 /* Initialize all 4 lanes of the SERDES. */
2419 for (i = 0; i < 4; i++) {
2420 u32 rxtx_ctrl, glue0;
2423 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2426 err = esr_read_glue0(np, i, &glue0);
2430 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2431 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2432 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2434 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2435 ESR_GLUE_CTRL0_THCNT |
2436 ESR_GLUE_CTRL0_BLTIME);
2437 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2438 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2439 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2440 (BLTIME_300_CYCLES <<
2441 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2443 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2446 err = esr_write_glue0(np, i, glue0);
2452 sig = nr64(ESR_INT_SIGNALS);
2455 mask = ESR_INT_SIGNALS_P0_BITS;
2456 val = (ESR_INT_SRDY0_P0 |
2459 ESR_INT_XDP_P0_CH3 |
2460 ESR_INT_XDP_P0_CH2 |
2461 ESR_INT_XDP_P0_CH1 |
2462 ESR_INT_XDP_P0_CH0);
2466 mask = ESR_INT_SIGNALS_P1_BITS;
2467 val = (ESR_INT_SRDY0_P1 |
2470 ESR_INT_XDP_P1_CH3 |
2471 ESR_INT_XDP_P1_CH2 |
2472 ESR_INT_XDP_P1_CH1 |
2473 ESR_INT_XDP_P1_CH0);
2480 if ((sig & mask) != val) {
2482 err = serdes_init_1g_serdes(np);
2484 np->flags &= ~NIU_FLAGS_10G;
2485 np->mac_xcvr = MAC_XCVR_PCS;
2487 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2496 static int niu_determine_phy_disposition(struct niu *np)
2498 struct niu_parent *parent = np->parent;
2499 u8 plat_type = parent->plat_type;
2500 const struct niu_phy_template *tp;
2501 u32 phy_addr_off = 0;
2503 if (plat_type == PLAT_TYPE_NIU) {
2507 NIU_FLAGS_XCVR_SERDES)) {
2508 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2510 tp = &phy_template_niu_10g_serdes;
2512 case NIU_FLAGS_XCVR_SERDES:
2514 tp = &phy_template_niu_1g_serdes;
2516 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2519 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2520 tp = &phy_template_niu_10g_hotplug;
2526 tp = &phy_template_niu_10g_fiber;
2527 phy_addr_off += np->port;
2535 NIU_FLAGS_XCVR_SERDES)) {
2538 tp = &phy_template_1g_copper;
2539 if (plat_type == PLAT_TYPE_VF_P0)
2541 else if (plat_type == PLAT_TYPE_VF_P1)
2544 phy_addr_off += (np->port ^ 0x3);
2549 tp = &phy_template_10g_copper;
2552 case NIU_FLAGS_FIBER:
2554 tp = &phy_template_1g_fiber;
2557 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2559 tp = &phy_template_10g_fiber;
2560 if (plat_type == PLAT_TYPE_VF_P0 ||
2561 plat_type == PLAT_TYPE_VF_P1)
2563 phy_addr_off += np->port;
2564 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2565 tp = &phy_template_10g_fiber_hotplug;
2573 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2574 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2575 case NIU_FLAGS_XCVR_SERDES:
2579 tp = &phy_template_10g_serdes;
2583 tp = &phy_template_1g_rgmii;
2589 phy_addr_off = niu_atca_port_num[np->port];
2597 np->phy_ops = tp->ops;
2598 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2603 static int niu_init_link(struct niu *np)
2605 struct niu_parent *parent = np->parent;
2608 if (parent->plat_type == PLAT_TYPE_NIU) {
2609 err = niu_xcvr_init(np);
2614 err = niu_serdes_init(np);
2615 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2618 err = niu_xcvr_init(np);
2619 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2620 niu_link_status(np, &ignore);
2624 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2626 u16 reg0 = addr[4] << 8 | addr[5];
2627 u16 reg1 = addr[2] << 8 | addr[3];
2628 u16 reg2 = addr[0] << 8 | addr[1];
2630 if (np->flags & NIU_FLAGS_XMAC) {
2631 nw64_mac(XMAC_ADDR0, reg0);
2632 nw64_mac(XMAC_ADDR1, reg1);
2633 nw64_mac(XMAC_ADDR2, reg2);
2635 nw64_mac(BMAC_ADDR0, reg0);
2636 nw64_mac(BMAC_ADDR1, reg1);
2637 nw64_mac(BMAC_ADDR2, reg2);
2641 static int niu_num_alt_addr(struct niu *np)
2643 if (np->flags & NIU_FLAGS_XMAC)
2644 return XMAC_NUM_ALT_ADDR;
2646 return BMAC_NUM_ALT_ADDR;
2649 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2651 u16 reg0 = addr[4] << 8 | addr[5];
2652 u16 reg1 = addr[2] << 8 | addr[3];
2653 u16 reg2 = addr[0] << 8 | addr[1];
2655 if (index >= niu_num_alt_addr(np))
2658 if (np->flags & NIU_FLAGS_XMAC) {
2659 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2660 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2661 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2663 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2664 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2665 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2671 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2676 if (index >= niu_num_alt_addr(np))
2679 if (np->flags & NIU_FLAGS_XMAC) {
2680 reg = XMAC_ADDR_CMPEN;
2683 reg = BMAC_ADDR_CMPEN;
2684 mask = 1 << (index + 1);
2687 val = nr64_mac(reg);
2697 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2698 int num, int mac_pref)
2700 u64 val = nr64_mac(reg);
2701 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2704 val |= HOST_INFO_MPR;
2708 static int __set_rdc_table_num(struct niu *np,
2709 int xmac_index, int bmac_index,
2710 int rdc_table_num, int mac_pref)
2714 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2716 if (np->flags & NIU_FLAGS_XMAC)
2717 reg = XMAC_HOST_INFO(xmac_index);
2719 reg = BMAC_HOST_INFO(bmac_index);
2720 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2724 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2727 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2730 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2733 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2736 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2737 int table_num, int mac_pref)
2739 if (idx >= niu_num_alt_addr(np))
2741 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2744 static u64 vlan_entry_set_parity(u64 reg_val)
2749 port01_mask = 0x00ff;
2750 port23_mask = 0xff00;
2752 if (hweight64(reg_val & port01_mask) & 1)
2753 reg_val |= ENET_VLAN_TBL_PARITY0;
2755 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2757 if (hweight64(reg_val & port23_mask) & 1)
2758 reg_val |= ENET_VLAN_TBL_PARITY1;
2760 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2765 static void vlan_tbl_write(struct niu *np, unsigned long index,
2766 int port, int vpr, int rdc_table)
2768 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2770 reg_val &= ~((ENET_VLAN_TBL_VPR |
2771 ENET_VLAN_TBL_VLANRDCTBLN) <<
2772 ENET_VLAN_TBL_SHIFT(port));
2774 reg_val |= (ENET_VLAN_TBL_VPR <<
2775 ENET_VLAN_TBL_SHIFT(port));
2776 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2778 reg_val = vlan_entry_set_parity(reg_val);
2780 nw64(ENET_VLAN_TBL(index), reg_val);
2783 static void vlan_tbl_clear(struct niu *np)
2787 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2788 nw64(ENET_VLAN_TBL(i), 0);
2791 static int tcam_wait_bit(struct niu *np, u64 bit)
2795 while (--limit > 0) {
2796 if (nr64(TCAM_CTL) & bit)
2806 static int tcam_flush(struct niu *np, int index)
2808 nw64(TCAM_KEY_0, 0x00);
2809 nw64(TCAM_KEY_MASK_0, 0xff);
2810 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2812 return tcam_wait_bit(np, TCAM_CTL_STAT);
2816 static int tcam_read(struct niu *np, int index,
2817 u64 *key, u64 *mask)
2821 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2822 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2824 key[0] = nr64(TCAM_KEY_0);
2825 key[1] = nr64(TCAM_KEY_1);
2826 key[2] = nr64(TCAM_KEY_2);
2827 key[3] = nr64(TCAM_KEY_3);
2828 mask[0] = nr64(TCAM_KEY_MASK_0);
2829 mask[1] = nr64(TCAM_KEY_MASK_1);
2830 mask[2] = nr64(TCAM_KEY_MASK_2);
2831 mask[3] = nr64(TCAM_KEY_MASK_3);
2837 static int tcam_write(struct niu *np, int index,
2838 u64 *key, u64 *mask)
2840 nw64(TCAM_KEY_0, key[0]);
2841 nw64(TCAM_KEY_1, key[1]);
2842 nw64(TCAM_KEY_2, key[2]);
2843 nw64(TCAM_KEY_3, key[3]);
2844 nw64(TCAM_KEY_MASK_0, mask[0]);
2845 nw64(TCAM_KEY_MASK_1, mask[1]);
2846 nw64(TCAM_KEY_MASK_2, mask[2]);
2847 nw64(TCAM_KEY_MASK_3, mask[3]);
2848 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2850 return tcam_wait_bit(np, TCAM_CTL_STAT);
2854 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2858 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2859 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2861 *data = nr64(TCAM_KEY_1);
2867 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2869 nw64(TCAM_KEY_1, assoc_data);
2870 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2872 return tcam_wait_bit(np, TCAM_CTL_STAT);
2875 static void tcam_enable(struct niu *np, int on)
2877 u64 val = nr64(FFLP_CFG_1);
2880 val &= ~FFLP_CFG_1_TCAM_DIS;
2882 val |= FFLP_CFG_1_TCAM_DIS;
2883 nw64(FFLP_CFG_1, val);
2886 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2888 u64 val = nr64(FFLP_CFG_1);
2890 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2892 FFLP_CFG_1_CAMRATIO);
2893 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2894 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2895 nw64(FFLP_CFG_1, val);
2897 val = nr64(FFLP_CFG_1);
2898 val |= FFLP_CFG_1_FFLPINITDONE;
2899 nw64(FFLP_CFG_1, val);
2902 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2908 if (class < CLASS_CODE_ETHERTYPE1 ||
2909 class > CLASS_CODE_ETHERTYPE2)
2912 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2924 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2930 if (class < CLASS_CODE_ETHERTYPE1 ||
2931 class > CLASS_CODE_ETHERTYPE2 ||
2932 (ether_type & ~(u64)0xffff) != 0)
2935 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2937 val &= ~L2_CLS_ETYPE;
2938 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2945 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2951 if (class < CLASS_CODE_USER_PROG1 ||
2952 class > CLASS_CODE_USER_PROG4)
2955 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2958 val |= L3_CLS_VALID;
2960 val &= ~L3_CLS_VALID;
2966 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2967 int ipv6, u64 protocol_id,
2968 u64 tos_mask, u64 tos_val)
2973 if (class < CLASS_CODE_USER_PROG1 ||
2974 class > CLASS_CODE_USER_PROG4 ||
2975 (protocol_id & ~(u64)0xff) != 0 ||
2976 (tos_mask & ~(u64)0xff) != 0 ||
2977 (tos_val & ~(u64)0xff) != 0)
2980 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2982 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2983 L3_CLS_TOSMASK | L3_CLS_TOS);
2985 val |= L3_CLS_IPVER;
2986 val |= (protocol_id << L3_CLS_PID_SHIFT);
2987 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2988 val |= (tos_val << L3_CLS_TOS_SHIFT);
2994 static int tcam_early_init(struct niu *np)
3000 tcam_set_lat_and_ratio(np,
3001 DEFAULT_TCAM_LATENCY,
3002 DEFAULT_TCAM_ACCESS_RATIO);
3003 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3004 err = tcam_user_eth_class_enable(np, i, 0);
3008 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3009 err = tcam_user_ip_class_enable(np, i, 0);
3017 static int tcam_flush_all(struct niu *np)
3021 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3022 int err = tcam_flush(np, i);
3029 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3031 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0);
3035 static int hash_read(struct niu *np, unsigned long partition,
3036 unsigned long index, unsigned long num_entries,
3039 u64 val = hash_addr_regval(index, num_entries);
3042 if (partition >= FCRAM_NUM_PARTITIONS ||
3043 index + num_entries > FCRAM_SIZE)
3046 nw64(HASH_TBL_ADDR(partition), val);
3047 for (i = 0; i < num_entries; i++)
3048 data[i] = nr64(HASH_TBL_DATA(partition));
3054 static int hash_write(struct niu *np, unsigned long partition,
3055 unsigned long index, unsigned long num_entries,
3058 u64 val = hash_addr_regval(index, num_entries);
3061 if (partition >= FCRAM_NUM_PARTITIONS ||
3062 index + (num_entries * 8) > FCRAM_SIZE)
3065 nw64(HASH_TBL_ADDR(partition), val);
3066 for (i = 0; i < num_entries; i++)
3067 nw64(HASH_TBL_DATA(partition), data[i]);
3072 static void fflp_reset(struct niu *np)
3076 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3078 nw64(FFLP_CFG_1, 0);
3080 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3081 nw64(FFLP_CFG_1, val);
3084 static void fflp_set_timings(struct niu *np)
3086 u64 val = nr64(FFLP_CFG_1);
3088 val &= ~FFLP_CFG_1_FFLPINITDONE;
3089 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3090 nw64(FFLP_CFG_1, val);
3092 val = nr64(FFLP_CFG_1);
3093 val |= FFLP_CFG_1_FFLPINITDONE;
3094 nw64(FFLP_CFG_1, val);
3096 val = nr64(FCRAM_REF_TMR);
3097 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3098 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3099 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3100 nw64(FCRAM_REF_TMR, val);
3103 static int fflp_set_partition(struct niu *np, u64 partition,
3104 u64 mask, u64 base, int enable)
3109 if (partition >= FCRAM_NUM_PARTITIONS ||
3110 (mask & ~(u64)0x1f) != 0 ||
3111 (base & ~(u64)0x1f) != 0)
3114 reg = FLW_PRT_SEL(partition);
3117 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3118 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3119 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3121 val |= FLW_PRT_SEL_EXT;
3127 static int fflp_disable_all_partitions(struct niu *np)
3131 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3132 int err = fflp_set_partition(np, 0, 0, 0, 0);
3139 static void fflp_llcsnap_enable(struct niu *np, int on)
3141 u64 val = nr64(FFLP_CFG_1);
3144 val |= FFLP_CFG_1_LLCSNAP;
3146 val &= ~FFLP_CFG_1_LLCSNAP;
3147 nw64(FFLP_CFG_1, val);
3150 static void fflp_errors_enable(struct niu *np, int on)
3152 u64 val = nr64(FFLP_CFG_1);
3155 val &= ~FFLP_CFG_1_ERRORDIS;
3157 val |= FFLP_CFG_1_ERRORDIS;
3158 nw64(FFLP_CFG_1, val);
3161 static int fflp_hash_clear(struct niu *np)
3163 struct fcram_hash_ipv4 ent;
3166 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3167 memset(&ent, 0, sizeof(ent));
3168 ent.header = HASH_HEADER_EXT;
3170 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3171 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3178 static int fflp_early_init(struct niu *np)
3180 struct niu_parent *parent;
3181 unsigned long flags;
3184 niu_lock_parent(np, flags);
3186 parent = np->parent;
3188 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3189 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3191 fflp_set_timings(np);
3192 err = fflp_disable_all_partitions(np);
3194 netif_printk(np, probe, KERN_DEBUG, np->dev,
3195 "fflp_disable_all_partitions failed, err=%d\n",
3201 err = tcam_early_init(np);
3203 netif_printk(np, probe, KERN_DEBUG, np->dev,
3204 "tcam_early_init failed, err=%d\n", err);
3207 fflp_llcsnap_enable(np, 1);
3208 fflp_errors_enable(np, 0);
3212 err = tcam_flush_all(np);
3214 netif_printk(np, probe, KERN_DEBUG, np->dev,
3215 "tcam_flush_all failed, err=%d\n", err);
3218 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3219 err = fflp_hash_clear(np);
3221 netif_printk(np, probe, KERN_DEBUG, np->dev,
3222 "fflp_hash_clear failed, err=%d\n",
3230 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3233 niu_unlock_parent(np, flags);
3237 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3239 if (class_code < CLASS_CODE_USER_PROG1 ||
3240 class_code > CLASS_CODE_SCTP_IPV6)
3243 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3247 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3249 if (class_code < CLASS_CODE_USER_PROG1 ||
3250 class_code > CLASS_CODE_SCTP_IPV6)
3253 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3257 /* Entries for the ports are interleaved in the TCAM */
3258 static u16 tcam_get_index(struct niu *np, u16 idx)
3260 /* One entry reserved for IP fragment rule */
3261 if (idx >= (np->clas.tcam_sz - 1))
3263 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports);
3266 static u16 tcam_get_size(struct niu *np)
3268 /* One entry reserved for IP fragment rule */
3269 return np->clas.tcam_sz - 1;
3272 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3274 /* One entry reserved for IP fragment rule */
3275 return np->clas.tcam_valid_entries - 1;
3278 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3279 u32 offset, u32 size, u32 truesize)
3281 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, offset, size);
3284 skb->data_len += size;
3285 skb->truesize += truesize;
3288 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3291 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3293 return a & (MAX_RBR_RING_SIZE - 1);
3296 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3297 struct page ***link)
3299 unsigned int h = niu_hash_rxaddr(rp, addr);
3300 struct page *p, **pp;
3303 pp = &rp->rxhash[h];
3304 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3305 if (p->index == addr) {
3316 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3318 unsigned int h = niu_hash_rxaddr(rp, base);
3321 page->mapping = (struct address_space *) rp->rxhash[h];
3322 rp->rxhash[h] = page;
3325 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3326 gfp_t mask, int start_index)
3332 page = alloc_page(mask);
3336 addr = np->ops->map_page(np->device, page, 0,
3337 PAGE_SIZE, DMA_FROM_DEVICE);
3339 niu_hash_page(rp, page, addr);
3340 if (rp->rbr_blocks_per_page > 1)
3341 atomic_add(rp->rbr_blocks_per_page - 1,
3342 &compound_head(page)->_count);
3344 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3345 __le32 *rbr = &rp->rbr[start_index + i];
3347 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3348 addr += rp->rbr_block_size;
3354 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3356 int index = rp->rbr_index;
3359 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3360 int err = niu_rbr_add_page(np, rp, mask, index);
3362 if (unlikely(err)) {
3367 rp->rbr_index += rp->rbr_blocks_per_page;
3368 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3369 if (rp->rbr_index == rp->rbr_table_size)
3372 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3373 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3374 rp->rbr_pending = 0;
3379 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3381 unsigned int index = rp->rcr_index;
3386 struct page *page, **link;
3392 val = le64_to_cpup(&rp->rcr[index]);
3393 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3394 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3395 page = niu_find_rxpage(rp, addr, &link);
3397 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3398 RCR_ENTRY_PKTBUFSZ_SHIFT];
3399 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3400 *link = (struct page *) page->mapping;
3401 np->ops->unmap_page(np->device, page->index,
3402 PAGE_SIZE, DMA_FROM_DEVICE);
3404 page->mapping = NULL;
3406 rp->rbr_refill_pending++;
3409 index = NEXT_RCR(rp, index);
3410 if (!(val & RCR_ENTRY_MULTI))
3414 rp->rcr_index = index;
3419 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3420 struct rx_ring_info *rp)
3422 unsigned int index = rp->rcr_index;
3423 struct rx_pkt_hdr1 *rh;
3424 struct sk_buff *skb;
3427 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3429 return niu_rx_pkt_ignore(np, rp);
3433 struct page *page, **link;
3434 u32 rcr_size, append_size;
3439 val = le64_to_cpup(&rp->rcr[index]);
3441 len = (val & RCR_ENTRY_L2_LEN) >>
3442 RCR_ENTRY_L2_LEN_SHIFT;
3445 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3446 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3447 page = niu_find_rxpage(rp, addr, &link);
3449 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3450 RCR_ENTRY_PKTBUFSZ_SHIFT];
3452 off = addr & ~PAGE_MASK;
3453 append_size = rcr_size;
3457 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3458 if ((ptype == RCR_PKT_TYPE_TCP ||
3459 ptype == RCR_PKT_TYPE_UDP) &&
3460 !(val & (RCR_ENTRY_NOPORT |
3462 skb->ip_summed = CHECKSUM_UNNECESSARY;
3464 skb_checksum_none_assert(skb);
3465 } else if (!(val & RCR_ENTRY_MULTI))
3466 append_size = len - skb->len;
3468 niu_rx_skb_append(skb, page, off, append_size, rcr_size);
3469 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3470 *link = (struct page *) page->mapping;
3471 np->ops->unmap_page(np->device, page->index,
3472 PAGE_SIZE, DMA_FROM_DEVICE);
3474 page->mapping = NULL;
3475 rp->rbr_refill_pending++;
3479 index = NEXT_RCR(rp, index);
3480 if (!(val & RCR_ENTRY_MULTI))
3484 rp->rcr_index = index;
3487 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3488 __pskb_pull_tail(skb, len);
3490 rh = (struct rx_pkt_hdr1 *) skb->data;
3491 if (np->dev->features & NETIF_F_RXHASH)
3492 skb->rxhash = ((u32)rh->hashval2_0 << 24 |
3493 (u32)rh->hashval2_1 << 16 |
3494 (u32)rh->hashval1_1 << 8 |
3495 (u32)rh->hashval1_2 << 0);
3496 skb_pull(skb, sizeof(*rh));
3499 rp->rx_bytes += skb->len;
3501 skb->protocol = eth_type_trans(skb, np->dev);
3502 skb_record_rx_queue(skb, rp->rx_channel);
3503 napi_gro_receive(napi, skb);
3508 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3510 int blocks_per_page = rp->rbr_blocks_per_page;
3511 int err, index = rp->rbr_index;
3514 while (index < (rp->rbr_table_size - blocks_per_page)) {
3515 err = niu_rbr_add_page(np, rp, mask, index);
3519 index += blocks_per_page;
3522 rp->rbr_index = index;
3526 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3530 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3533 page = rp->rxhash[i];
3535 struct page *next = (struct page *) page->mapping;
3536 u64 base = page->index;
3538 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3541 page->mapping = NULL;
3549 for (i = 0; i < rp->rbr_table_size; i++)
3550 rp->rbr[i] = cpu_to_le32(0);
3554 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3556 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3557 struct sk_buff *skb = tb->skb;
3558 struct tx_pkt_hdr *tp;
3562 tp = (struct tx_pkt_hdr *) skb->data;
3563 tx_flags = le64_to_cpup(&tp->flags);
3566 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3567 ((tx_flags & TXHDR_PAD) / 2));
3569 len = skb_headlen(skb);
3570 np->ops->unmap_single(np->device, tb->mapping,
3571 len, DMA_TO_DEVICE);
3573 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3578 idx = NEXT_TX(rp, idx);
3579 len -= MAX_TX_DESC_LEN;
3582 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3583 tb = &rp->tx_buffs[idx];
3584 BUG_ON(tb->skb != NULL);
3585 np->ops->unmap_page(np->device, tb->mapping,
3586 skb_frag_size(&skb_shinfo(skb)->frags[i]),
3588 idx = NEXT_TX(rp, idx);
3596 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3598 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3600 struct netdev_queue *txq;
3605 index = (rp - np->tx_rings);
3606 txq = netdev_get_tx_queue(np->dev, index);
3609 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3612 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3613 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3614 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3616 rp->last_pkt_cnt = tmp;
3620 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3621 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3624 cons = release_tx_packet(np, rp, cons);
3630 if (unlikely(netif_tx_queue_stopped(txq) &&
3631 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3632 __netif_tx_lock(txq, smp_processor_id());
3633 if (netif_tx_queue_stopped(txq) &&
3634 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3635 netif_tx_wake_queue(txq);
3636 __netif_tx_unlock(txq);
3640 static inline void niu_sync_rx_discard_stats(struct niu *np,
3641 struct rx_ring_info *rp,
3644 /* This elaborate scheme is needed for reading the RX discard
3645 * counters, as they are only 16-bit and can overflow quickly,
3646 * and because the overflow indication bit is not usable as
3647 * the counter value does not wrap, but remains at max value
3650 * In theory and in practice counters can be lost in between
3651 * reading nr64() and clearing the counter nw64(). For this
3652 * reason, the number of counter clearings nw64() is
3653 * limited/reduced though the limit parameter.
3655 int rx_channel = rp->rx_channel;
3658 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3659 * following discard events: IPP (Input Port Process),
3660 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3661 * Block Ring) prefetch buffer is empty.
3663 misc = nr64(RXMISC(rx_channel));
3664 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3665 nw64(RXMISC(rx_channel), 0);
3666 rp->rx_errors += misc & RXMISC_COUNT;
3668 if (unlikely(misc & RXMISC_OFLOW))
3669 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3672 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3673 "rx-%d: MISC drop=%u over=%u\n",
3674 rx_channel, misc, misc-limit);
3677 /* WRED (Weighted Random Early Discard) by hardware */
3678 wred = nr64(RED_DIS_CNT(rx_channel));
3679 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3680 nw64(RED_DIS_CNT(rx_channel), 0);
3681 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3683 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3684 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3686 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3687 "rx-%d: WRED drop=%u over=%u\n",
3688 rx_channel, wred, wred-limit);
3692 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3693 struct rx_ring_info *rp, int budget)
3695 int qlen, rcr_done = 0, work_done = 0;
3696 struct rxdma_mailbox *mbox = rp->mbox;
3700 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3701 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3703 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3704 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3706 mbox->rx_dma_ctl_stat = 0;
3707 mbox->rcrstat_a = 0;
3709 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3710 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3711 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3713 rcr_done = work_done = 0;
3714 qlen = min(qlen, budget);
3715 while (work_done < qlen) {
3716 rcr_done += niu_process_rx_pkt(napi, np, rp);
3720 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3723 for (i = 0; i < rp->rbr_refill_pending; i++)
3724 niu_rbr_refill(np, rp, GFP_ATOMIC);
3725 rp->rbr_refill_pending = 0;
3728 stat = (RX_DMA_CTL_STAT_MEX |
3729 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3730 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3732 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3734 /* Only sync discards stats when qlen indicate potential for drops */
3736 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3741 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3744 u32 tx_vec = (v0 >> 32);
3745 u32 rx_vec = (v0 & 0xffffffff);
3746 int i, work_done = 0;
3748 netif_printk(np, intr, KERN_DEBUG, np->dev,
3749 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3751 for (i = 0; i < np->num_tx_rings; i++) {
3752 struct tx_ring_info *rp = &np->tx_rings[i];
3753 if (tx_vec & (1 << rp->tx_channel))
3754 niu_tx_work(np, rp);
3755 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3758 for (i = 0; i < np->num_rx_rings; i++) {
3759 struct rx_ring_info *rp = &np->rx_rings[i];
3761 if (rx_vec & (1 << rp->rx_channel)) {
3764 this_work_done = niu_rx_work(&lp->napi, np, rp,
3767 budget -= this_work_done;
3768 work_done += this_work_done;
3770 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3776 static int niu_poll(struct napi_struct *napi, int budget)
3778 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3779 struct niu *np = lp->np;
3782 work_done = niu_poll_core(np, lp, budget);
3784 if (work_done < budget) {
3785 napi_complete(napi);
3786 niu_ldg_rearm(np, lp, 1);
3791 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3794 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3796 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3797 pr_cont("RBR_TMOUT ");
3798 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3799 pr_cont("RSP_CNT ");
3800 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3801 pr_cont("BYTE_EN_BUS ");
3802 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3803 pr_cont("RSP_DAT ");
3804 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3805 pr_cont("RCR_ACK ");
3806 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3807 pr_cont("RCR_SHA_PAR ");
3808 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3809 pr_cont("RBR_PRE_PAR ");
3810 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3812 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3813 pr_cont("RCRINCON ");
3814 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3815 pr_cont("RCRFULL ");
3816 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3817 pr_cont("RBRFULL ");
3818 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3819 pr_cont("RBRLOGPAGE ");
3820 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3821 pr_cont("CFIGLOGPAGE ");
3822 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3823 pr_cont("DC_FIDO ");
3828 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3830 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3834 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3835 RX_DMA_CTL_STAT_PORT_FATAL))
3839 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3841 (unsigned long long) stat);
3843 niu_log_rxchan_errors(np, rp, stat);
3846 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3847 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3852 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3855 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3857 if (cs & TX_CS_MBOX_ERR)
3859 if (cs & TX_CS_PKT_SIZE_ERR)
3860 pr_cont("PKT_SIZE ");
3861 if (cs & TX_CS_TX_RING_OFLOW)
3862 pr_cont("TX_RING_OFLOW ");
3863 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3864 pr_cont("PREF_BUF_PAR ");
3865 if (cs & TX_CS_NACK_PREF)
3866 pr_cont("NACK_PREF ");
3867 if (cs & TX_CS_NACK_PKT_RD)
3868 pr_cont("NACK_PKT_RD ");
3869 if (cs & TX_CS_CONF_PART_ERR)
3870 pr_cont("CONF_PART ");
3871 if (cs & TX_CS_PKT_PRT_ERR)
3872 pr_cont("PKT_PTR ");
3877 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3881 cs = nr64(TX_CS(rp->tx_channel));
3882 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3883 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3885 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3887 (unsigned long long)cs,
3888 (unsigned long long)logh,
3889 (unsigned long long)logl);
3891 niu_log_txchan_errors(np, rp, cs);
3896 static int niu_mif_interrupt(struct niu *np)
3898 u64 mif_status = nr64(MIF_STATUS);
3901 if (np->flags & NIU_FLAGS_XMAC) {
3902 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3904 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3908 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3909 (unsigned long long)mif_status, phy_mdint);
3914 static void niu_xmac_interrupt(struct niu *np)
3916 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3919 val = nr64_mac(XTXMAC_STATUS);
3920 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3921 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3922 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3923 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3924 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3925 mp->tx_fifo_errors++;
3926 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3927 mp->tx_overflow_errors++;
3928 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3929 mp->tx_max_pkt_size_errors++;
3930 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3931 mp->tx_underflow_errors++;
3933 val = nr64_mac(XRXMAC_STATUS);
3934 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3935 mp->rx_local_faults++;
3936 if (val & XRXMAC_STATUS_RFLT_DET)
3937 mp->rx_remote_faults++;
3938 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3939 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3940 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3941 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3942 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3943 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3944 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3945 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3946 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3947 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3948 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3949 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3950 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3951 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3952 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3953 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3954 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3955 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3956 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3957 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3958 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3959 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3960 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3961 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3962 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3963 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3964 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3965 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3966 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3967 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3968 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3969 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3970 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3971 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3972 if (val & XRXMAC_STATUS_RXUFLOW)
3973 mp->rx_underflows++;
3974 if (val & XRXMAC_STATUS_RXOFLOW)
3977 val = nr64_mac(XMAC_FC_STAT);
3978 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3979 mp->pause_off_state++;
3980 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3981 mp->pause_on_state++;
3982 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3983 mp->pause_received++;
3986 static void niu_bmac_interrupt(struct niu *np)
3988 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3991 val = nr64_mac(BTXMAC_STATUS);
3992 if (val & BTXMAC_STATUS_UNDERRUN)
3993 mp->tx_underflow_errors++;
3994 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3995 mp->tx_max_pkt_size_errors++;
3996 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3997 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3998 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
3999 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4001 val = nr64_mac(BRXMAC_STATUS);
4002 if (val & BRXMAC_STATUS_OVERFLOW)
4004 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4005 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4006 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4007 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4008 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4009 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4010 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4011 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4013 val = nr64_mac(BMAC_CTRL_STATUS);
4014 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4015 mp->pause_off_state++;
4016 if (val & BMAC_CTRL_STATUS_PAUSE)
4017 mp->pause_on_state++;
4018 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4019 mp->pause_received++;
4022 static int niu_mac_interrupt(struct niu *np)
4024 if (np->flags & NIU_FLAGS_XMAC)
4025 niu_xmac_interrupt(np);
4027 niu_bmac_interrupt(np);
4032 static void niu_log_device_error(struct niu *np, u64 stat)
4034 netdev_err(np->dev, "Core device errors ( ");
4036 if (stat & SYS_ERR_MASK_META2)
4038 if (stat & SYS_ERR_MASK_META1)
4040 if (stat & SYS_ERR_MASK_PEU)
4042 if (stat & SYS_ERR_MASK_TXC)
4044 if (stat & SYS_ERR_MASK_RDMC)
4046 if (stat & SYS_ERR_MASK_TDMC)
4048 if (stat & SYS_ERR_MASK_ZCP)
4050 if (stat & SYS_ERR_MASK_FFLP)
4052 if (stat & SYS_ERR_MASK_IPP)
4054 if (stat & SYS_ERR_MASK_MAC)
4056 if (stat & SYS_ERR_MASK_SMX)
4062 static int niu_device_error(struct niu *np)
4064 u64 stat = nr64(SYS_ERR_STAT);
4066 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4067 (unsigned long long)stat);
4069 niu_log_device_error(np, stat);
4074 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4075 u64 v0, u64 v1, u64 v2)
4084 if (v1 & 0x00000000ffffffffULL) {
4085 u32 rx_vec = (v1 & 0xffffffff);
4087 for (i = 0; i < np->num_rx_rings; i++) {
4088 struct rx_ring_info *rp = &np->rx_rings[i];
4090 if (rx_vec & (1 << rp->rx_channel)) {
4091 int r = niu_rx_error(np, rp);
4096 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4097 RX_DMA_CTL_STAT_MEX);
4102 if (v1 & 0x7fffffff00000000ULL) {
4103 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4105 for (i = 0; i < np->num_tx_rings; i++) {
4106 struct tx_ring_info *rp = &np->tx_rings[i];
4108 if (tx_vec & (1 << rp->tx_channel)) {
4109 int r = niu_tx_error(np, rp);
4115 if ((v0 | v1) & 0x8000000000000000ULL) {
4116 int r = niu_mif_interrupt(np);
4122 int r = niu_mac_interrupt(np);
4127 int r = niu_device_error(np);
4134 niu_enable_interrupts(np, 0);
4139 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4142 struct rxdma_mailbox *mbox = rp->mbox;
4143 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4145 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4146 RX_DMA_CTL_STAT_RCRTO);
4147 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4149 netif_printk(np, intr, KERN_DEBUG, np->dev,
4150 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4153 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4156 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4158 netif_printk(np, intr, KERN_DEBUG, np->dev,
4159 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4162 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4164 struct niu_parent *parent = np->parent;
4168 tx_vec = (v0 >> 32);
4169 rx_vec = (v0 & 0xffffffff);
4171 for (i = 0; i < np->num_rx_rings; i++) {
4172 struct rx_ring_info *rp = &np->rx_rings[i];
4173 int ldn = LDN_RXDMA(rp->rx_channel);
4175 if (parent->ldg_map[ldn] != ldg)
4178 nw64(LD_IM0(ldn), LD_IM0_MASK);
4179 if (rx_vec & (1 << rp->rx_channel))
4180 niu_rxchan_intr(np, rp, ldn);
4183 for (i = 0; i < np->num_tx_rings; i++) {
4184 struct tx_ring_info *rp = &np->tx_rings[i];
4185 int ldn = LDN_TXDMA(rp->tx_channel);
4187 if (parent->ldg_map[ldn] != ldg)
4190 nw64(LD_IM0(ldn), LD_IM0_MASK);
4191 if (tx_vec & (1 << rp->tx_channel))
4192 niu_txchan_intr(np, rp, ldn);
4196 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4197 u64 v0, u64 v1, u64 v2)
4199 if (likely(napi_schedule_prep(&lp->napi))) {
4203 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4204 __napi_schedule(&lp->napi);
4208 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4210 struct niu_ldg *lp = dev_id;
4211 struct niu *np = lp->np;
4212 int ldg = lp->ldg_num;
4213 unsigned long flags;
4216 if (netif_msg_intr(np))
4217 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4220 spin_lock_irqsave(&np->lock, flags);
4222 v0 = nr64(LDSV0(ldg));
4223 v1 = nr64(LDSV1(ldg));
4224 v2 = nr64(LDSV2(ldg));
4226 if (netif_msg_intr(np))
4227 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4228 (unsigned long long) v0,
4229 (unsigned long long) v1,
4230 (unsigned long long) v2);
4232 if (unlikely(!v0 && !v1 && !v2)) {
4233 spin_unlock_irqrestore(&np->lock, flags);
4237 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4238 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4242 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4243 niu_schedule_napi(np, lp, v0, v1, v2);
4245 niu_ldg_rearm(np, lp, 1);
4247 spin_unlock_irqrestore(&np->lock, flags);
4252 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4255 np->ops->free_coherent(np->device,
4256 sizeof(struct rxdma_mailbox),
4257 rp->mbox, rp->mbox_dma);
4261 np->ops->free_coherent(np->device,
4262 MAX_RCR_RING_SIZE * sizeof(__le64),
4263 rp->rcr, rp->rcr_dma);
4265 rp->rcr_table_size = 0;
4269 niu_rbr_free(np, rp);
4271 np->ops->free_coherent(np->device,
4272 MAX_RBR_RING_SIZE * sizeof(__le32),
4273 rp->rbr, rp->rbr_dma);
4275 rp->rbr_table_size = 0;
4282 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4285 np->ops->free_coherent(np->device,
4286 sizeof(struct txdma_mailbox),
4287 rp->mbox, rp->mbox_dma);
4293 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4294 if (rp->tx_buffs[i].skb)
4295 (void) release_tx_packet(np, rp, i);
4298 np->ops->free_coherent(np->device,
4299 MAX_TX_RING_SIZE * sizeof(__le64),
4300 rp->descr, rp->descr_dma);
4309 static void niu_free_channels(struct niu *np)
4314 for (i = 0; i < np->num_rx_rings; i++) {
4315 struct rx_ring_info *rp = &np->rx_rings[i];
4317 niu_free_rx_ring_info(np, rp);
4319 kfree(np->rx_rings);
4320 np->rx_rings = NULL;
4321 np->num_rx_rings = 0;
4325 for (i = 0; i < np->num_tx_rings; i++) {
4326 struct tx_ring_info *rp = &np->tx_rings[i];
4328 niu_free_tx_ring_info(np, rp);
4330 kfree(np->tx_rings);
4331 np->tx_rings = NULL;
4332 np->num_tx_rings = 0;
4336 static int niu_alloc_rx_ring_info(struct niu *np,
4337 struct rx_ring_info *rp)
4339 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4341 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4346 rp->mbox = np->ops->alloc_coherent(np->device,
4347 sizeof(struct rxdma_mailbox),
4348 &rp->mbox_dma, GFP_KERNEL);
4351 if ((unsigned long)rp->mbox & (64UL - 1)) {
4352 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4357 rp->rcr = np->ops->alloc_coherent(np->device,
4358 MAX_RCR_RING_SIZE * sizeof(__le64),
4359 &rp->rcr_dma, GFP_KERNEL);
4362 if ((unsigned long)rp->rcr & (64UL - 1)) {
4363 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4367 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4370 rp->rbr = np->ops->alloc_coherent(np->device,
4371 MAX_RBR_RING_SIZE * sizeof(__le32),
4372 &rp->rbr_dma, GFP_KERNEL);
4375 if ((unsigned long)rp->rbr & (64UL - 1)) {
4376 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4380 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4382 rp->rbr_pending = 0;
4387 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4389 int mtu = np->dev->mtu;
4391 /* These values are recommended by the HW designers for fair
4392 * utilization of DRR amongst the rings.
4394 rp->max_burst = mtu + 32;
4395 if (rp->max_burst > 4096)
4396 rp->max_burst = 4096;
4399 static int niu_alloc_tx_ring_info(struct niu *np,
4400 struct tx_ring_info *rp)
4402 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4404 rp->mbox = np->ops->alloc_coherent(np->device,
4405 sizeof(struct txdma_mailbox),
4406 &rp->mbox_dma, GFP_KERNEL);
4409 if ((unsigned long)rp->mbox & (64UL - 1)) {
4410 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4415 rp->descr = np->ops->alloc_coherent(np->device,
4416 MAX_TX_RING_SIZE * sizeof(__le64),
4417 &rp->descr_dma, GFP_KERNEL);
4420 if ((unsigned long)rp->descr & (64UL - 1)) {
4421 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4426 rp->pending = MAX_TX_RING_SIZE;
4431 /* XXX make these configurable... XXX */
4432 rp->mark_freq = rp->pending / 4;
4434 niu_set_max_burst(np, rp);
4439 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4443 bss = min(PAGE_SHIFT, 15);
4445 rp->rbr_block_size = 1 << bss;
4446 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4448 rp->rbr_sizes[0] = 256;
4449 rp->rbr_sizes[1] = 1024;
4450 if (np->dev->mtu > ETH_DATA_LEN) {
4451 switch (PAGE_SIZE) {
4453 rp->rbr_sizes[2] = 4096;
4457 rp->rbr_sizes[2] = 8192;
4461 rp->rbr_sizes[2] = 2048;
4463 rp->rbr_sizes[3] = rp->rbr_block_size;
4466 static int niu_alloc_channels(struct niu *np)
4468 struct niu_parent *parent = np->parent;
4469 int first_rx_channel, first_tx_channel;
4470 int num_rx_rings, num_tx_rings;
4471 struct rx_ring_info *rx_rings;
4472 struct tx_ring_info *tx_rings;
4476 first_rx_channel = first_tx_channel = 0;
4477 for (i = 0; i < port; i++) {
4478 first_rx_channel += parent->rxchan_per_port[i];
4479 first_tx_channel += parent->txchan_per_port[i];
4482 num_rx_rings = parent->rxchan_per_port[port];
4483 num_tx_rings = parent->txchan_per_port[port];
4485 rx_rings = kcalloc(num_rx_rings, sizeof(struct rx_ring_info),
4491 np->num_rx_rings = num_rx_rings;
4493 np->rx_rings = rx_rings;
4495 netif_set_real_num_rx_queues(np->dev, num_rx_rings);
4497 for (i = 0; i < np->num_rx_rings; i++) {
4498 struct rx_ring_info *rp = &np->rx_rings[i];
4501 rp->rx_channel = first_rx_channel + i;
4503 err = niu_alloc_rx_ring_info(np, rp);
4507 niu_size_rbr(np, rp);
4509 /* XXX better defaults, configurable, etc... XXX */
4510 rp->nonsyn_window = 64;
4511 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4512 rp->syn_window = 64;
4513 rp->syn_threshold = rp->rcr_table_size - 64;
4514 rp->rcr_pkt_threshold = 16;
4515 rp->rcr_timeout = 8;
4516 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4517 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4518 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4520 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4525 tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info),
4531 np->num_tx_rings = num_tx_rings;
4533 np->tx_rings = tx_rings;
4535 netif_set_real_num_tx_queues(np->dev, num_tx_rings);
4537 for (i = 0; i < np->num_tx_rings; i++) {
4538 struct tx_ring_info *rp = &np->tx_rings[i];
4541 rp->tx_channel = first_tx_channel + i;
4543 err = niu_alloc_tx_ring_info(np, rp);
4551 niu_free_channels(np);
4555 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4559 while (--limit > 0) {
4560 u64 val = nr64(TX_CS(channel));
4561 if (val & TX_CS_SNG_STATE)
4567 static int niu_tx_channel_stop(struct niu *np, int channel)
4569 u64 val = nr64(TX_CS(channel));
4571 val |= TX_CS_STOP_N_GO;
4572 nw64(TX_CS(channel), val);
4574 return niu_tx_cs_sng_poll(np, channel);
4577 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4581 while (--limit > 0) {
4582 u64 val = nr64(TX_CS(channel));
4583 if (!(val & TX_CS_RST))
4589 static int niu_tx_channel_reset(struct niu *np, int channel)
4591 u64 val = nr64(TX_CS(channel));
4595 nw64(TX_CS(channel), val);
4597 err = niu_tx_cs_reset_poll(np, channel);
4599 nw64(TX_RING_KICK(channel), 0);
4604 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4608 nw64(TX_LOG_MASK1(channel), 0);
4609 nw64(TX_LOG_VAL1(channel), 0);
4610 nw64(TX_LOG_MASK2(channel), 0);
4611 nw64(TX_LOG_VAL2(channel), 0);
4612 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4613 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4614 nw64(TX_LOG_PAGE_HDL(channel), 0);
4616 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4617 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4618 nw64(TX_LOG_PAGE_VLD(channel), val);
4620 /* XXX TXDMA 32bit mode? XXX */
4625 static void niu_txc_enable_port(struct niu *np, int on)
4627 unsigned long flags;
4630 niu_lock_parent(np, flags);
4631 val = nr64(TXC_CONTROL);
4632 mask = (u64)1 << np->port;
4634 val |= TXC_CONTROL_ENABLE | mask;
4637 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4638 val &= ~TXC_CONTROL_ENABLE;
4640 nw64(TXC_CONTROL, val);
4641 niu_unlock_parent(np, flags);
4644 static void niu_txc_set_imask(struct niu *np, u64 imask)
4646 unsigned long flags;
4649 niu_lock_parent(np, flags);
4650 val = nr64(TXC_INT_MASK);
4651 val &= ~TXC_INT_MASK_VAL(np->port);
4652 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4653 niu_unlock_parent(np, flags);
4656 static void niu_txc_port_dma_enable(struct niu *np, int on)
4663 for (i = 0; i < np->num_tx_rings; i++)
4664 val |= (1 << np->tx_rings[i].tx_channel);
4666 nw64(TXC_PORT_DMA(np->port), val);
4669 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4671 int err, channel = rp->tx_channel;
4674 err = niu_tx_channel_stop(np, channel);
4678 err = niu_tx_channel_reset(np, channel);
4682 err = niu_tx_channel_lpage_init(np, channel);
4686 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4687 nw64(TX_ENT_MSK(channel), 0);
4689 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4690 TX_RNG_CFIG_STADDR)) {
4691 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4692 channel, (unsigned long long)rp->descr_dma);
4696 /* The length field in TX_RNG_CFIG is measured in 64-byte
4697 * blocks. rp->pending is the number of TX descriptors in
4698 * our ring, 8 bytes each, thus we divide by 8 bytes more
4699 * to get the proper value the chip wants.
4701 ring_len = (rp->pending / 8);
4703 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4705 nw64(TX_RNG_CFIG(channel), val);
4707 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4708 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4709 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4710 channel, (unsigned long long)rp->mbox_dma);
4713 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4714 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4716 nw64(TX_CS(channel), 0);
4718 rp->last_pkt_cnt = 0;
4723 static void niu_init_rdc_groups(struct niu *np)
4725 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4726 int i, first_table_num = tp->first_table_num;
4728 for (i = 0; i < tp->num_tables; i++) {
4729 struct rdc_table *tbl = &tp->tables[i];
4730 int this_table = first_table_num + i;
4733 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4734 nw64(RDC_TBL(this_table, slot),
4735 tbl->rxdma_channel[slot]);
4738 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4741 static void niu_init_drr_weight(struct niu *np)
4743 int type = phy_decode(np->parent->port_phy, np->port);
4748 val = PT_DRR_WEIGHT_DEFAULT_10G;
4753 val = PT_DRR_WEIGHT_DEFAULT_1G;
4756 nw64(PT_DRR_WT(np->port), val);
4759 static int niu_init_hostinfo(struct niu *np)
4761 struct niu_parent *parent = np->parent;
4762 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4763 int i, err, num_alt = niu_num_alt_addr(np);
4764 int first_rdc_table = tp->first_table_num;
4766 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4770 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4774 for (i = 0; i < num_alt; i++) {
4775 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4783 static int niu_rx_channel_reset(struct niu *np, int channel)
4785 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4786 RXDMA_CFIG1_RST, 1000, 10,
4790 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4794 nw64(RX_LOG_MASK1(channel), 0);
4795 nw64(RX_LOG_VAL1(channel), 0);
4796 nw64(RX_LOG_MASK2(channel), 0);
4797 nw64(RX_LOG_VAL2(channel), 0);
4798 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4799 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4800 nw64(RX_LOG_PAGE_HDL(channel), 0);
4802 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4803 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4804 nw64(RX_LOG_PAGE_VLD(channel), val);
4809 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4813 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4814 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4815 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4816 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4817 nw64(RDC_RED_PARA(rp->rx_channel), val);
4820 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4825 switch (rp->rbr_block_size) {
4827 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4830 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4833 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4836 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4841 val |= RBR_CFIG_B_VLD2;
4842 switch (rp->rbr_sizes[2]) {
4844 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4847 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4850 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4853 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4859 val |= RBR_CFIG_B_VLD1;
4860 switch (rp->rbr_sizes[1]) {
4862 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4865 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4868 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4871 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4877 val |= RBR_CFIG_B_VLD0;
4878 switch (rp->rbr_sizes[0]) {
4880 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4883 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4886 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4889 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4900 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4902 u64 val = nr64(RXDMA_CFIG1(channel));
4906 val |= RXDMA_CFIG1_EN;
4908 val &= ~RXDMA_CFIG1_EN;
4909 nw64(RXDMA_CFIG1(channel), val);
4912 while (--limit > 0) {
4913 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4922 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4924 int err, channel = rp->rx_channel;
4927 err = niu_rx_channel_reset(np, channel);
4931 err = niu_rx_channel_lpage_init(np, channel);
4935 niu_rx_channel_wred_init(np, rp);
4937 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4938 nw64(RX_DMA_CTL_STAT(channel),
4939 (RX_DMA_CTL_STAT_MEX |
4940 RX_DMA_CTL_STAT_RCRTHRES |
4941 RX_DMA_CTL_STAT_RCRTO |
4942 RX_DMA_CTL_STAT_RBR_EMPTY));
4943 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4944 nw64(RXDMA_CFIG2(channel),
4945 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4946 RXDMA_CFIG2_FULL_HDR));
4947 nw64(RBR_CFIG_A(channel),
4948 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4949 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4950 err = niu_compute_rbr_cfig_b(rp, &val);
4953 nw64(RBR_CFIG_B(channel), val);
4954 nw64(RCRCFIG_A(channel),
4955 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4956 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4957 nw64(RCRCFIG_B(channel),
4958 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4960 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4962 err = niu_enable_rx_channel(np, channel, 1);
4966 nw64(RBR_KICK(channel), rp->rbr_index);
4968 val = nr64(RX_DMA_CTL_STAT(channel));
4969 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4970 nw64(RX_DMA_CTL_STAT(channel), val);
4975 static int niu_init_rx_channels(struct niu *np)
4977 unsigned long flags;
4978 u64 seed = jiffies_64;
4981 niu_lock_parent(np, flags);
4982 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4983 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4984 niu_unlock_parent(np, flags);
4986 /* XXX RXDMA 32bit mode? XXX */
4988 niu_init_rdc_groups(np);
4989 niu_init_drr_weight(np);
4991 err = niu_init_hostinfo(np);
4995 for (i = 0; i < np->num_rx_rings; i++) {
4996 struct rx_ring_info *rp = &np->rx_rings[i];
4998 err = niu_init_one_rx_channel(np, rp);
5006 static int niu_set_ip_frag_rule(struct niu *np)
5008 struct niu_parent *parent = np->parent;
5009 struct niu_classifier *cp = &np->clas;
5010 struct niu_tcam_entry *tp;
5013 index = cp->tcam_top;
5014 tp = &parent->tcam[index];
5016 /* Note that the noport bit is the same in both ipv4 and
5017 * ipv6 format TCAM entries.
5019 memset(tp, 0, sizeof(*tp));
5020 tp->key[1] = TCAM_V4KEY1_NOPORT;
5021 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5022 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5023 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5024 err = tcam_write(np, index, tp->key, tp->key_mask);
5027 err = tcam_assoc_write(np, index, tp->assoc_data);
5031 cp->tcam_valid_entries++;
5036 static int niu_init_classifier_hw(struct niu *np)
5038 struct niu_parent *parent = np->parent;
5039 struct niu_classifier *cp = &np->clas;
5042 nw64(H1POLY, cp->h1_init);
5043 nw64(H2POLY, cp->h2_init);
5045 err = niu_init_hostinfo(np);
5049 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5050 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5052 vlan_tbl_write(np, i, np->port,
5053 vp->vlan_pref, vp->rdc_num);
5056 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5057 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5059 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5060 ap->rdc_num, ap->mac_pref);
5065 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5066 int index = i - CLASS_CODE_USER_PROG1;
5068 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5071 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5076 err = niu_set_ip_frag_rule(np);
5085 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5087 nw64(ZCP_RAM_DATA0, data[0]);
5088 nw64(ZCP_RAM_DATA1, data[1]);
5089 nw64(ZCP_RAM_DATA2, data[2]);
5090 nw64(ZCP_RAM_DATA3, data[3]);
5091 nw64(ZCP_RAM_DATA4, data[4]);
5092 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5094 (ZCP_RAM_ACC_WRITE |
5095 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5096 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5098 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5102 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5106 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5109 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5110 (unsigned long long)nr64(ZCP_RAM_ACC));
5116 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5117 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5119 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5122 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5123 (unsigned long long)nr64(ZCP_RAM_ACC));
5127 data[0] = nr64(ZCP_RAM_DATA0);
5128 data[1] = nr64(ZCP_RAM_DATA1);
5129 data[2] = nr64(ZCP_RAM_DATA2);
5130 data[3] = nr64(ZCP_RAM_DATA3);
5131 data[4] = nr64(ZCP_RAM_DATA4);
5136 static void niu_zcp_cfifo_reset(struct niu *np)
5138 u64 val = nr64(RESET_CFIFO);
5140 val |= RESET_CFIFO_RST(np->port);
5141 nw64(RESET_CFIFO, val);
5144 val &= ~RESET_CFIFO_RST(np->port);
5145 nw64(RESET_CFIFO, val);
5148 static int niu_init_zcp(struct niu *np)
5150 u64 data[5], rbuf[5];
5153 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5154 if (np->port == 0 || np->port == 1)
5155 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5157 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5159 max = NIU_CFIFO_ENTRIES;
5167 for (i = 0; i < max; i++) {
5168 err = niu_zcp_write(np, i, data);
5171 err = niu_zcp_read(np, i, rbuf);
5176 niu_zcp_cfifo_reset(np);
5177 nw64(CFIFO_ECC(np->port), 0);
5178 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5179 (void) nr64(ZCP_INT_STAT);
5180 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5185 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5187 u64 val = nr64_ipp(IPP_CFIG);
5189 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5190 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5191 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5192 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5193 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5194 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5195 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5196 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5199 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5201 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5202 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5203 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5204 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5205 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5206 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5209 static int niu_ipp_reset(struct niu *np)
5211 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5212 1000, 100, "IPP_CFIG");
5215 static int niu_init_ipp(struct niu *np)
5217 u64 data[5], rbuf[5], val;
5220 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5221 if (np->port == 0 || np->port == 1)
5222 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5224 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5226 max = NIU_DFIFO_ENTRIES;
5234 for (i = 0; i < max; i++) {
5235 niu_ipp_write(np, i, data);
5236 niu_ipp_read(np, i, rbuf);
5239 (void) nr64_ipp(IPP_INT_STAT);
5240 (void) nr64_ipp(IPP_INT_STAT);
5242 err = niu_ipp_reset(np);
5246 (void) nr64_ipp(IPP_PKT_DIS);
5247 (void) nr64_ipp(IPP_BAD_CS_CNT);
5248 (void) nr64_ipp(IPP_ECC);
5250 (void) nr64_ipp(IPP_INT_STAT);
5252 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5254 val = nr64_ipp(IPP_CFIG);
5255 val &= ~IPP_CFIG_IP_MAX_PKT;
5256 val |= (IPP_CFIG_IPP_ENABLE |
5257 IPP_CFIG_DFIFO_ECC_EN |
5258 IPP_CFIG_DROP_BAD_CRC |
5260 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5261 nw64_ipp(IPP_CFIG, val);
5266 static void niu_handle_led(struct niu *np, int status)
5269 val = nr64_mac(XMAC_CONFIG);
5271 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5272 (np->flags & NIU_FLAGS_FIBER) != 0) {
5274 val |= XMAC_CONFIG_LED_POLARITY;
5275 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5277 val |= XMAC_CONFIG_FORCE_LED_ON;
5278 val &= ~XMAC_CONFIG_LED_POLARITY;
5282 nw64_mac(XMAC_CONFIG, val);
5285 static void niu_init_xif_xmac(struct niu *np)
5287 struct niu_link_config *lp = &np->link_config;
5290 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5291 val = nr64(MIF_CONFIG);
5292 val |= MIF_CONFIG_ATCA_GE;
5293 nw64(MIF_CONFIG, val);
5296 val = nr64_mac(XMAC_CONFIG);
5297 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5299 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5301 if (lp->loopback_mode == LOOPBACK_MAC) {
5302 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5303 val |= XMAC_CONFIG_LOOPBACK;
5305 val &= ~XMAC_CONFIG_LOOPBACK;
5308 if (np->flags & NIU_FLAGS_10G) {
5309 val &= ~XMAC_CONFIG_LFS_DISABLE;
5311 val |= XMAC_CONFIG_LFS_DISABLE;
5312 if (!(np->flags & NIU_FLAGS_FIBER) &&
5313 !(np->flags & NIU_FLAGS_XCVR_SERDES))
5314 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5316 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5319 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5321 if (lp->active_speed == SPEED_100)
5322 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5324 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5326 nw64_mac(XMAC_CONFIG, val);
5328 val = nr64_mac(XMAC_CONFIG);
5329 val &= ~XMAC_CONFIG_MODE_MASK;
5330 if (np->flags & NIU_FLAGS_10G) {
5331 val |= XMAC_CONFIG_MODE_XGMII;
5333 if (lp->active_speed == SPEED_1000)
5334 val |= XMAC_CONFIG_MODE_GMII;
5336 val |= XMAC_CONFIG_MODE_MII;
5339 nw64_mac(XMAC_CONFIG, val);
5342 static void niu_init_xif_bmac(struct niu *np)
5344 struct niu_link_config *lp = &np->link_config;
5347 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5349 if (lp->loopback_mode == LOOPBACK_MAC)
5350 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5352 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5354 if (lp->active_speed == SPEED_1000)
5355 val |= BMAC_XIF_CONFIG_GMII_MODE;
5357 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5359 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5360 BMAC_XIF_CONFIG_LED_POLARITY);
5362 if (!(np->flags & NIU_FLAGS_10G) &&
5363 !(np->flags & NIU_FLAGS_FIBER) &&
5364 lp->active_speed == SPEED_100)
5365 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5367 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5369 nw64_mac(BMAC_XIF_CONFIG, val);
5372 static void niu_init_xif(struct niu *np)
5374 if (np->flags & NIU_FLAGS_XMAC)
5375 niu_init_xif_xmac(np);
5377 niu_init_xif_bmac(np);
5380 static void niu_pcs_mii_reset(struct niu *np)
5383 u64 val = nr64_pcs(PCS_MII_CTL);
5384 val |= PCS_MII_CTL_RST;
5385 nw64_pcs(PCS_MII_CTL, val);
5386 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5388 val = nr64_pcs(PCS_MII_CTL);
5392 static void niu_xpcs_reset(struct niu *np)
5395 u64 val = nr64_xpcs(XPCS_CONTROL1);
5396 val |= XPCS_CONTROL1_RESET;
5397 nw64_xpcs(XPCS_CONTROL1, val);
5398 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5400 val = nr64_xpcs(XPCS_CONTROL1);
5404 static int niu_init_pcs(struct niu *np)
5406 struct niu_link_config *lp = &np->link_config;
5409 switch (np->flags & (NIU_FLAGS_10G |
5411 NIU_FLAGS_XCVR_SERDES)) {
5412 case NIU_FLAGS_FIBER:
5414 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5415 nw64_pcs(PCS_DPATH_MODE, 0);
5416 niu_pcs_mii_reset(np);
5420 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5421 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5423 if (!(np->flags & NIU_FLAGS_XMAC))
5426 /* 10G copper or fiber */
5427 val = nr64_mac(XMAC_CONFIG);
5428 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5429 nw64_mac(XMAC_CONFIG, val);
5433 val = nr64_xpcs(XPCS_CONTROL1);
5434 if (lp->loopback_mode == LOOPBACK_PHY)
5435 val |= XPCS_CONTROL1_LOOPBACK;
5437 val &= ~XPCS_CONTROL1_LOOPBACK;
5438 nw64_xpcs(XPCS_CONTROL1, val);
5440 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5441 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5442 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5446 case NIU_FLAGS_XCVR_SERDES:
5448 niu_pcs_mii_reset(np);
5449 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5450 nw64_pcs(PCS_DPATH_MODE, 0);
5455 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5456 /* 1G RGMII FIBER */
5457 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5458 niu_pcs_mii_reset(np);
5468 static int niu_reset_tx_xmac(struct niu *np)
5470 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5471 (XTXMAC_SW_RST_REG_RS |
5472 XTXMAC_SW_RST_SOFT_RST),
5473 1000, 100, "XTXMAC_SW_RST");
5476 static int niu_reset_tx_bmac(struct niu *np)
5480 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5482 while (--limit >= 0) {
5483 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5488 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5490 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5497 static int niu_reset_tx_mac(struct niu *np)
5499 if (np->flags & NIU_FLAGS_XMAC)
5500 return niu_reset_tx_xmac(np);
5502 return niu_reset_tx_bmac(np);
5505 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5509 val = nr64_mac(XMAC_MIN);
5510 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5511 XMAC_MIN_RX_MIN_PKT_SIZE);
5512 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5513 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5514 nw64_mac(XMAC_MIN, val);
5516 nw64_mac(XMAC_MAX, max);
5518 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5520 val = nr64_mac(XMAC_IPG);
5521 if (np->flags & NIU_FLAGS_10G) {
5522 val &= ~XMAC_IPG_IPG_XGMII;
5523 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5525 val &= ~XMAC_IPG_IPG_MII_GMII;
5526 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5528 nw64_mac(XMAC_IPG, val);
5530 val = nr64_mac(XMAC_CONFIG);
5531 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5532 XMAC_CONFIG_STRETCH_MODE |
5533 XMAC_CONFIG_VAR_MIN_IPG_EN |
5534 XMAC_CONFIG_TX_ENABLE);
5535 nw64_mac(XMAC_CONFIG, val);
5537 nw64_mac(TXMAC_FRM_CNT, 0);
5538 nw64_mac(TXMAC_BYTE_CNT, 0);
5541 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5545 nw64_mac(BMAC_MIN_FRAME, min);
5546 nw64_mac(BMAC_MAX_FRAME, max);
5548 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5549 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5550 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5552 val = nr64_mac(BTXMAC_CONFIG);
5553 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5554 BTXMAC_CONFIG_ENABLE);
5555 nw64_mac(BTXMAC_CONFIG, val);
5558 static void niu_init_tx_mac(struct niu *np)
5563 if (np->dev->mtu > ETH_DATA_LEN)
5568 /* The XMAC_MIN register only accepts values for TX min which
5569 * have the low 3 bits cleared.
5573 if (np->flags & NIU_FLAGS_XMAC)
5574 niu_init_tx_xmac(np, min, max);
5576 niu_init_tx_bmac(np, min, max);
5579 static int niu_reset_rx_xmac(struct niu *np)
5583 nw64_mac(XRXMAC_SW_RST,
5584 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5586 while (--limit >= 0) {
5587 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5588 XRXMAC_SW_RST_SOFT_RST)))
5593 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5595 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5602 static int niu_reset_rx_bmac(struct niu *np)
5606 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5608 while (--limit >= 0) {
5609 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5614 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5616 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5623 static int niu_reset_rx_mac(struct niu *np)
5625 if (np->flags & NIU_FLAGS_XMAC)
5626 return niu_reset_rx_xmac(np);
5628 return niu_reset_rx_bmac(np);
5631 static void niu_init_rx_xmac(struct niu *np)
5633 struct niu_parent *parent = np->parent;
5634 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5635 int first_rdc_table = tp->first_table_num;
5639 nw64_mac(XMAC_ADD_FILT0, 0);
5640 nw64_mac(XMAC_ADD_FILT1, 0);
5641 nw64_mac(XMAC_ADD_FILT2, 0);
5642 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5643 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5644 for (i = 0; i < MAC_NUM_HASH; i++)
5645 nw64_mac(XMAC_HASH_TBL(i), 0);
5646 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5647 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5648 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5650 val = nr64_mac(XMAC_CONFIG);
5651 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5652 XMAC_CONFIG_PROMISCUOUS |
5653 XMAC_CONFIG_PROMISC_GROUP |
5654 XMAC_CONFIG_ERR_CHK_DIS |
5655 XMAC_CONFIG_RX_CRC_CHK_DIS |
5656 XMAC_CONFIG_RESERVED_MULTICAST |
5657 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5658 XMAC_CONFIG_ADDR_FILTER_EN |
5659 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5660 XMAC_CONFIG_STRIP_CRC |
5661 XMAC_CONFIG_PASS_FLOW_CTRL |
5662 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5663 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5664 nw64_mac(XMAC_CONFIG, val);
5666 nw64_mac(RXMAC_BT_CNT, 0);
5667 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5668 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5669 nw64_mac(RXMAC_FRAG_CNT, 0);
5670 nw64_mac(RXMAC_HIST_CNT1, 0);
5671 nw64_mac(RXMAC_HIST_CNT2, 0);
5672 nw64_mac(RXMAC_HIST_CNT3, 0);
5673 nw64_mac(RXMAC_HIST_CNT4, 0);
5674 nw64_mac(RXMAC_HIST_CNT5, 0);
5675 nw64_mac(RXMAC_HIST_CNT6, 0);
5676 nw64_mac(RXMAC_HIST_CNT7, 0);
5677 nw64_mac(RXMAC_MPSZER_CNT, 0);
5678 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5679 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5680 nw64_mac(LINK_FAULT_CNT, 0);
5683 static void niu_init_rx_bmac(struct niu *np)
5685 struct niu_parent *parent = np->parent;
5686 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5687 int first_rdc_table = tp->first_table_num;
5691 nw64_mac(BMAC_ADD_FILT0, 0);
5692 nw64_mac(BMAC_ADD_FILT1, 0);
5693 nw64_mac(BMAC_ADD_FILT2, 0);
5694 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5695 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5696 for (i = 0; i < MAC_NUM_HASH; i++)
5697 nw64_mac(BMAC_HASH_TBL(i), 0);
5698 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5699 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5700 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5702 val = nr64_mac(BRXMAC_CONFIG);
5703 val &= ~(BRXMAC_CONFIG_ENABLE |
5704 BRXMAC_CONFIG_STRIP_PAD |
5705 BRXMAC_CONFIG_STRIP_FCS |
5706 BRXMAC_CONFIG_PROMISC |
5707 BRXMAC_CONFIG_PROMISC_GRP |
5708 BRXMAC_CONFIG_ADDR_FILT_EN |
5709 BRXMAC_CONFIG_DISCARD_DIS);
5710 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5711 nw64_mac(BRXMAC_CONFIG, val);
5713 val = nr64_mac(BMAC_ADDR_CMPEN);
5714 val |= BMAC_ADDR_CMPEN_EN0;
5715 nw64_mac(BMAC_ADDR_CMPEN, val);
5718 static void niu_init_rx_mac(struct niu *np)
5720 niu_set_primary_mac(np, np->dev->dev_addr);
5722 if (np->flags & NIU_FLAGS_XMAC)
5723 niu_init_rx_xmac(np);
5725 niu_init_rx_bmac(np);
5728 static void niu_enable_tx_xmac(struct niu *np, int on)
5730 u64 val = nr64_mac(XMAC_CONFIG);
5733 val |= XMAC_CONFIG_TX_ENABLE;
5735 val &= ~XMAC_CONFIG_TX_ENABLE;
5736 nw64_mac(XMAC_CONFIG, val);
5739 static void niu_enable_tx_bmac(struct niu *np, int on)
5741 u64 val = nr64_mac(BTXMAC_CONFIG);
5744 val |= BTXMAC_CONFIG_ENABLE;
5746 val &= ~BTXMAC_CONFIG_ENABLE;
5747 nw64_mac(BTXMAC_CONFIG, val);
5750 static void niu_enable_tx_mac(struct niu *np, int on)
5752 if (np->flags & NIU_FLAGS_XMAC)
5753 niu_enable_tx_xmac(np, on);
5755 niu_enable_tx_bmac(np, on);
5758 static void niu_enable_rx_xmac(struct niu *np, int on)
5760 u64 val = nr64_mac(XMAC_CONFIG);
5762 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5763 XMAC_CONFIG_PROMISCUOUS);
5765 if (np->flags & NIU_FLAGS_MCAST)
5766 val |= XMAC_CONFIG_HASH_FILTER_EN;
5767 if (np->flags & NIU_FLAGS_PROMISC)
5768 val |= XMAC_CONFIG_PROMISCUOUS;
5771 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5773 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5774 nw64_mac(XMAC_CONFIG, val);
5777 static void niu_enable_rx_bmac(struct niu *np, int on)
5779 u64 val = nr64_mac(BRXMAC_CONFIG);
5781 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5782 BRXMAC_CONFIG_PROMISC);
5784 if (np->flags & NIU_FLAGS_MCAST)
5785 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5786 if (np->flags & NIU_FLAGS_PROMISC)
5787 val |= BRXMAC_CONFIG_PROMISC;
5790 val |= BRXMAC_CONFIG_ENABLE;
5792 val &= ~BRXMAC_CONFIG_ENABLE;
5793 nw64_mac(BRXMAC_CONFIG, val);
5796 static void niu_enable_rx_mac(struct niu *np, int on)
5798 if (np->flags & NIU_FLAGS_XMAC)
5799 niu_enable_rx_xmac(np, on);
5801 niu_enable_rx_bmac(np, on);
5804 static int niu_init_mac(struct niu *np)
5809 err = niu_init_pcs(np);
5813 err = niu_reset_tx_mac(np);
5816 niu_init_tx_mac(np);
5817 err = niu_reset_rx_mac(np);
5820 niu_init_rx_mac(np);
5822 /* This looks hookey but the RX MAC reset we just did will
5823 * undo some of the state we setup in niu_init_tx_mac() so we
5824 * have to call it again. In particular, the RX MAC reset will
5825 * set the XMAC_MAX register back to it's default value.
5827 niu_init_tx_mac(np);
5828 niu_enable_tx_mac(np, 1);
5830 niu_enable_rx_mac(np, 1);
5835 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5837 (void) niu_tx_channel_stop(np, rp->tx_channel);
5840 static void niu_stop_tx_channels(struct niu *np)
5844 for (i = 0; i < np->num_tx_rings; i++) {
5845 struct tx_ring_info *rp = &np->tx_rings[i];
5847 niu_stop_one_tx_channel(np, rp);
5851 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5853 (void) niu_tx_channel_reset(np, rp->tx_channel);
5856 static void niu_reset_tx_channels(struct niu *np)
5860 for (i = 0; i < np->num_tx_rings; i++) {
5861 struct tx_ring_info *rp = &np->tx_rings[i];
5863 niu_reset_one_tx_channel(np, rp);
5867 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5869 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5872 static void niu_stop_rx_channels(struct niu *np)
5876 for (i = 0; i < np->num_rx_rings; i++) {
5877 struct rx_ring_info *rp = &np->rx_rings[i];
5879 niu_stop_one_rx_channel(np, rp);
5883 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5885 int channel = rp->rx_channel;
5887 (void) niu_rx_channel_reset(np, channel);
5888 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5889 nw64(RX_DMA_CTL_STAT(channel), 0);
5890 (void) niu_enable_rx_channel(np, channel, 0);
5893 static void niu_reset_rx_channels(struct niu *np)
5897 for (i = 0; i < np->num_rx_rings; i++) {
5898 struct rx_ring_info *rp = &np->rx_rings[i];
5900 niu_reset_one_rx_channel(np, rp);
5904 static void niu_disable_ipp(struct niu *np)
5909 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5910 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5912 while (--limit >= 0 && (rd != wr)) {
5913 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5914 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5917 (rd != 0 && wr != 1)) {
5918 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5919 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5920 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5923 val = nr64_ipp(IPP_CFIG);
5924 val &= ~(IPP_CFIG_IPP_ENABLE |
5925 IPP_CFIG_DFIFO_ECC_EN |
5926 IPP_CFIG_DROP_BAD_CRC |
5928 nw64_ipp(IPP_CFIG, val);
5930 (void) niu_ipp_reset(np);
5933 static int niu_init_hw(struct niu *np)
5937 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5938 niu_txc_enable_port(np, 1);
5939 niu_txc_port_dma_enable(np, 1);
5940 niu_txc_set_imask(np, 0);
5942 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5943 for (i = 0; i < np->num_tx_rings; i++) {
5944 struct tx_ring_info *rp = &np->tx_rings[i];
5946 err = niu_init_one_tx_channel(np, rp);
5951 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5952 err = niu_init_rx_channels(np);
5954 goto out_uninit_tx_channels;
5956 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5957 err = niu_init_classifier_hw(np);
5959 goto out_uninit_rx_channels;
5961 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5962 err = niu_init_zcp(np);
5964 goto out_uninit_rx_channels;
5966 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5967 err = niu_init_ipp(np);
5969 goto out_uninit_rx_channels;
5971 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5972 err = niu_init_mac(np);
5974 goto out_uninit_ipp;
5979 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5980 niu_disable_ipp(np);
5982 out_uninit_rx_channels:
5983 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5984 niu_stop_rx_channels(np);
5985 niu_reset_rx_channels(np);
5987 out_uninit_tx_channels:
5988 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
5989 niu_stop_tx_channels(np);
5990 niu_reset_tx_channels(np);
5995 static void niu_stop_hw(struct niu *np)
5997 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
5998 niu_enable_interrupts(np, 0);
6000 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
6001 niu_enable_rx_mac(np, 0);
6003 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
6004 niu_disable_ipp(np);
6006 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
6007 niu_stop_tx_channels(np);
6009 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
6010 niu_stop_rx_channels(np);
6012 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6013 niu_reset_tx_channels(np);
6015 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6016 niu_reset_rx_channels(np);
6019 static void niu_set_irq_name(struct niu *np)
6021 int port = np->port;
6024 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6027 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6028 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6032 for (i = 0; i < np->num_ldg - j; i++) {
6033 if (i < np->num_rx_rings)
6034 sprintf(np->irq_name[i+j], "%s-rx-%d",
6036 else if (i < np->num_tx_rings + np->num_rx_rings)
6037 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6038 i - np->num_rx_rings);
6042 static int niu_request_irq(struct niu *np)
6046 niu_set_irq_name(np);
6049 for (i = 0; i < np->num_ldg; i++) {
6050 struct niu_ldg *lp = &np->ldg[i];
6052 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED,
6053 np->irq_name[i], lp);
6062 for (j = 0; j < i; j++) {
6063 struct niu_ldg *lp = &np->ldg[j];
6065 free_irq(lp->irq, lp);
6070 static void niu_free_irq(struct niu *np)
6074 for (i = 0; i < np->num_ldg; i++) {
6075 struct niu_ldg *lp = &np->ldg[i];
6077 free_irq(lp->irq, lp);
6081 static void niu_enable_napi(struct niu *np)
6085 for (i = 0; i < np->num_ldg; i++)
6086 napi_enable(&np->ldg[i].napi);
6089 static void niu_disable_napi(struct niu *np)
6093 for (i = 0; i < np->num_ldg; i++)
6094 napi_disable(&np->ldg[i].napi);
6097 static int niu_open(struct net_device *dev)
6099 struct niu *np = netdev_priv(dev);
6102 netif_carrier_off(dev);
6104 err = niu_alloc_channels(np);
6108 err = niu_enable_interrupts(np, 0);
6110 goto out_free_channels;
6112 err = niu_request_irq(np);
6114 goto out_free_channels;
6116 niu_enable_napi(np);
6118 spin_lock_irq(&np->lock);
6120 err = niu_init_hw(np);
6122 init_timer(&np->timer);
6123 np->timer.expires = jiffies + HZ;
6124 np->timer.data = (unsigned long) np;
6125 np->timer.function = niu_timer;
6127 err = niu_enable_interrupts(np, 1);
6132 spin_unlock_irq(&np->lock);
6135 niu_disable_napi(np);
6139 netif_tx_start_all_queues(dev);
6141 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6142 netif_carrier_on(dev);
6144 add_timer(&np->timer);
6152 niu_free_channels(np);
6158 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6160 cancel_work_sync(&np->reset_task);
6162 niu_disable_napi(np);
6163 netif_tx_stop_all_queues(dev);
6165 del_timer_sync(&np->timer);
6167 spin_lock_irq(&np->lock);
6171 spin_unlock_irq(&np->lock);
6174 static int niu_close(struct net_device *dev)
6176 struct niu *np = netdev_priv(dev);
6178 niu_full_shutdown(np, dev);
6182 niu_free_channels(np);
6184 niu_handle_led(np, 0);
6189 static void niu_sync_xmac_stats(struct niu *np)
6191 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6193 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6194 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6196 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6197 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6198 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6199 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6200 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6201 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6202 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6203 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6204 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6205 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6206 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6207 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6208 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6209 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6210 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6211 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6214 static void niu_sync_bmac_stats(struct niu *np)
6216 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6218 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6219 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6221 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6222 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6223 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6224 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6227 static void niu_sync_mac_stats(struct niu *np)
6229 if (np->flags & NIU_FLAGS_XMAC)
6230 niu_sync_xmac_stats(np);
6232 niu_sync_bmac_stats(np);
6235 static void niu_get_rx_stats(struct niu *np,
6236 struct rtnl_link_stats64 *stats)
6238 u64 pkts, dropped, errors, bytes;
6239 struct rx_ring_info *rx_rings;
6242 pkts = dropped = errors = bytes = 0;
6244 rx_rings = ACCESS_ONCE(np->rx_rings);
6248 for (i = 0; i < np->num_rx_rings; i++) {
6249 struct rx_ring_info *rp = &rx_rings[i];
6251 niu_sync_rx_discard_stats(np, rp, 0);
6253 pkts += rp->rx_packets;
6254 bytes += rp->rx_bytes;
6255 dropped += rp->rx_dropped;
6256 errors += rp->rx_errors;
6260 stats->rx_packets = pkts;
6261 stats->rx_bytes = bytes;
6262 stats->rx_dropped = dropped;
6263 stats->rx_errors = errors;
6266 static void niu_get_tx_stats(struct niu *np,
6267 struct rtnl_link_stats64 *stats)
6269 u64 pkts, errors, bytes;
6270 struct tx_ring_info *tx_rings;
6273 pkts = errors = bytes = 0;
6275 tx_rings = ACCESS_ONCE(np->tx_rings);
6279 for (i = 0; i < np->num_tx_rings; i++) {
6280 struct tx_ring_info *rp = &tx_rings[i];
6282 pkts += rp->tx_packets;
6283 bytes += rp->tx_bytes;
6284 errors += rp->tx_errors;
6288 stats->tx_packets = pkts;
6289 stats->tx_bytes = bytes;
6290 stats->tx_errors = errors;
6293 static struct rtnl_link_stats64 *niu_get_stats(struct net_device *dev,
6294 struct rtnl_link_stats64 *stats)
6296 struct niu *np = netdev_priv(dev);
6298 if (netif_running(dev)) {
6299 niu_get_rx_stats(np, stats);
6300 niu_get_tx_stats(np, stats);
6306 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6310 for (i = 0; i < 16; i++)
6311 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6314 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6318 for (i = 0; i < 16; i++)
6319 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6322 static void niu_load_hash(struct niu *np, u16 *hash)
6324 if (np->flags & NIU_FLAGS_XMAC)
6325 niu_load_hash_xmac(np, hash);
6327 niu_load_hash_bmac(np, hash);
6330 static void niu_set_rx_mode(struct net_device *dev)
6332 struct niu *np = netdev_priv(dev);
6333 int i, alt_cnt, err;
6334 struct netdev_hw_addr *ha;
6335 unsigned long flags;
6336 u16 hash[16] = { 0, };
6338 spin_lock_irqsave(&np->lock, flags);
6339 niu_enable_rx_mac(np, 0);
6341 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6342 if (dev->flags & IFF_PROMISC)
6343 np->flags |= NIU_FLAGS_PROMISC;
6344 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6345 np->flags |= NIU_FLAGS_MCAST;
6347 alt_cnt = netdev_uc_count(dev);
6348 if (alt_cnt > niu_num_alt_addr(np)) {
6350 np->flags |= NIU_FLAGS_PROMISC;
6356 netdev_for_each_uc_addr(ha, dev) {
6357 err = niu_set_alt_mac(np, index, ha->addr);
6359 netdev_warn(dev, "Error %d adding alt mac %d\n",
6361 err = niu_enable_alt_mac(np, index, 1);
6363 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6370 if (np->flags & NIU_FLAGS_XMAC)
6374 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6375 err = niu_enable_alt_mac(np, i, 0);
6377 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6381 if (dev->flags & IFF_ALLMULTI) {
6382 for (i = 0; i < 16; i++)
6384 } else if (!netdev_mc_empty(dev)) {
6385 netdev_for_each_mc_addr(ha, dev) {
6386 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
6389 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6393 if (np->flags & NIU_FLAGS_MCAST)
6394 niu_load_hash(np, hash);
6396 niu_enable_rx_mac(np, 1);
6397 spin_unlock_irqrestore(&np->lock, flags);
6400 static int niu_set_mac_addr(struct net_device *dev, void *p)
6402 struct niu *np = netdev_priv(dev);
6403 struct sockaddr *addr = p;
6404 unsigned long flags;
6406 if (!is_valid_ether_addr(addr->sa_data))
6407 return -EADDRNOTAVAIL;
6409 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6411 if (!netif_running(dev))
6414 spin_lock_irqsave(&np->lock, flags);
6415 niu_enable_rx_mac(np, 0);
6416 niu_set_primary_mac(np, dev->dev_addr);
6417 niu_enable_rx_mac(np, 1);
6418 spin_unlock_irqrestore(&np->lock, flags);
6423 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6428 static void niu_netif_stop(struct niu *np)
6430 np->dev->trans_start = jiffies; /* prevent tx timeout */
6432 niu_disable_napi(np);
6434 netif_tx_disable(np->dev);
6437 static void niu_netif_start(struct niu *np)
6439 /* NOTE: unconditional netif_wake_queue is only appropriate
6440 * so long as all callers are assured to have free tx slots
6441 * (such as after niu_init_hw).
6443 netif_tx_wake_all_queues(np->dev);
6445 niu_enable_napi(np);
6447 niu_enable_interrupts(np, 1);
6450 static void niu_reset_buffers(struct niu *np)
6455 for (i = 0; i < np->num_rx_rings; i++) {
6456 struct rx_ring_info *rp = &np->rx_rings[i];
6458 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6461 page = rp->rxhash[j];
6464 (struct page *) page->mapping;
6465 u64 base = page->index;
6466 base = base >> RBR_DESCR_ADDR_SHIFT;
6467 rp->rbr[k++] = cpu_to_le32(base);
6471 for (; k < MAX_RBR_RING_SIZE; k++) {
6472 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6477 rp->rbr_index = rp->rbr_table_size - 1;
6479 rp->rbr_pending = 0;
6480 rp->rbr_refill_pending = 0;
6484 for (i = 0; i < np->num_tx_rings; i++) {
6485 struct tx_ring_info *rp = &np->tx_rings[i];
6487 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6488 if (rp->tx_buffs[j].skb)
6489 (void) release_tx_packet(np, rp, j);
6492 rp->pending = MAX_TX_RING_SIZE;
6500 static void niu_reset_task(struct work_struct *work)
6502 struct niu *np = container_of(work, struct niu, reset_task);
6503 unsigned long flags;
6506 spin_lock_irqsave(&np->lock, flags);
6507 if (!netif_running(np->dev)) {
6508 spin_unlock_irqrestore(&np->lock, flags);
6512 spin_unlock_irqrestore(&np->lock, flags);
6514 del_timer_sync(&np->timer);
6518 spin_lock_irqsave(&np->lock, flags);
6522 spin_unlock_irqrestore(&np->lock, flags);
6524 niu_reset_buffers(np);
6526 spin_lock_irqsave(&np->lock, flags);
6528 err = niu_init_hw(np);
6530 np->timer.expires = jiffies + HZ;
6531 add_timer(&np->timer);
6532 niu_netif_start(np);
6535 spin_unlock_irqrestore(&np->lock, flags);
6538 static void niu_tx_timeout(struct net_device *dev)
6540 struct niu *np = netdev_priv(dev);
6542 dev_err(np->device, "%s: Transmit timed out, resetting\n",
6545 schedule_work(&np->reset_task);
6548 static void niu_set_txd(struct tx_ring_info *rp, int index,
6549 u64 mapping, u64 len, u64 mark,
6552 __le64 *desc = &rp->descr[index];
6554 *desc = cpu_to_le64(mark |
6555 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6556 (len << TX_DESC_TR_LEN_SHIFT) |
6557 (mapping & TX_DESC_SAD));
6560 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6561 u64 pad_bytes, u64 len)
6563 u16 eth_proto, eth_proto_inner;
6564 u64 csum_bits, l3off, ihl, ret;
6568 eth_proto = be16_to_cpu(ehdr->h_proto);
6569 eth_proto_inner = eth_proto;
6570 if (eth_proto == ETH_P_8021Q) {
6571 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6572 __be16 val = vp->h_vlan_encapsulated_proto;
6574 eth_proto_inner = be16_to_cpu(val);
6578 switch (skb->protocol) {
6579 case cpu_to_be16(ETH_P_IP):
6580 ip_proto = ip_hdr(skb)->protocol;
6581 ihl = ip_hdr(skb)->ihl;
6583 case cpu_to_be16(ETH_P_IPV6):
6584 ip_proto = ipv6_hdr(skb)->nexthdr;
6593 csum_bits = TXHDR_CSUM_NONE;
6594 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6597 csum_bits = (ip_proto == IPPROTO_TCP ?
6599 (ip_proto == IPPROTO_UDP ?
6600 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6602 start = skb_checksum_start_offset(skb) -
6603 (pad_bytes + sizeof(struct tx_pkt_hdr));
6604 stuff = start + skb->csum_offset;
6606 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6607 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6610 l3off = skb_network_offset(skb) -
6611 (pad_bytes + sizeof(struct tx_pkt_hdr));
6613 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6614 (len << TXHDR_LEN_SHIFT) |
6615 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6616 (ihl << TXHDR_IHL_SHIFT) |
6617 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6618 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6619 (ipv6 ? TXHDR_IP_VER : 0) |
6625 static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6626 struct net_device *dev)
6628 struct niu *np = netdev_priv(dev);
6629 unsigned long align, headroom;
6630 struct netdev_queue *txq;
6631 struct tx_ring_info *rp;
6632 struct tx_pkt_hdr *tp;
6633 unsigned int len, nfg;
6634 struct ethhdr *ehdr;
6638 i = skb_get_queue_mapping(skb);
6639 rp = &np->tx_rings[i];
6640 txq = netdev_get_tx_queue(dev, i);
6642 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6643 netif_tx_stop_queue(txq);
6644 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
6646 return NETDEV_TX_BUSY;
6649 if (skb->len < ETH_ZLEN) {
6650 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6652 if (skb_pad(skb, pad_bytes))
6654 skb_put(skb, pad_bytes);
6657 len = sizeof(struct tx_pkt_hdr) + 15;
6658 if (skb_headroom(skb) < len) {
6659 struct sk_buff *skb_new;
6661 skb_new = skb_realloc_headroom(skb, len);
6671 align = ((unsigned long) skb->data & (16 - 1));
6672 headroom = align + sizeof(struct tx_pkt_hdr);
6674 ehdr = (struct ethhdr *) skb->data;
6675 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6677 len = skb->len - sizeof(struct tx_pkt_hdr);
6678 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6681 len = skb_headlen(skb);
6682 mapping = np->ops->map_single(np->device, skb->data,
6683 len, DMA_TO_DEVICE);
6687 rp->tx_buffs[prod].skb = skb;
6688 rp->tx_buffs[prod].mapping = mapping;
6691 if (++rp->mark_counter == rp->mark_freq) {
6692 rp->mark_counter = 0;
6693 mrk |= TX_DESC_MARK;
6698 nfg = skb_shinfo(skb)->nr_frags;
6700 tlen -= MAX_TX_DESC_LEN;
6705 unsigned int this_len = len;
6707 if (this_len > MAX_TX_DESC_LEN)
6708 this_len = MAX_TX_DESC_LEN;
6710 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6713 prod = NEXT_TX(rp, prod);
6714 mapping += this_len;
6718 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6719 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6721 len = skb_frag_size(frag);
6722 mapping = np->ops->map_page(np->device, skb_frag_page(frag),
6723 frag->page_offset, len,
6726 rp->tx_buffs[prod].skb = NULL;
6727 rp->tx_buffs[prod].mapping = mapping;
6729 niu_set_txd(rp, prod, mapping, len, 0, 0);
6731 prod = NEXT_TX(rp, prod);
6734 if (prod < rp->prod)
6735 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6738 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6740 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6741 netif_tx_stop_queue(txq);
6742 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6743 netif_tx_wake_queue(txq);
6747 return NETDEV_TX_OK;
6755 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6757 struct niu *np = netdev_priv(dev);
6758 int err, orig_jumbo, new_jumbo;
6760 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6763 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6764 new_jumbo = (new_mtu > ETH_DATA_LEN);
6768 if (!netif_running(dev) ||
6769 (orig_jumbo == new_jumbo))
6772 niu_full_shutdown(np, dev);
6774 niu_free_channels(np);
6776 niu_enable_napi(np);
6778 err = niu_alloc_channels(np);
6782 spin_lock_irq(&np->lock);
6784 err = niu_init_hw(np);
6786 init_timer(&np->timer);
6787 np->timer.expires = jiffies + HZ;
6788 np->timer.data = (unsigned long) np;
6789 np->timer.function = niu_timer;
6791 err = niu_enable_interrupts(np, 1);
6796 spin_unlock_irq(&np->lock);
6799 netif_tx_start_all_queues(dev);
6800 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6801 netif_carrier_on(dev);
6803 add_timer(&np->timer);
6809 static void niu_get_drvinfo(struct net_device *dev,
6810 struct ethtool_drvinfo *info)
6812 struct niu *np = netdev_priv(dev);
6813 struct niu_vpd *vpd = &np->vpd;
6815 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
6816 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
6817 snprintf(info->fw_version, sizeof(info->fw_version), "%d.%d",
6818 vpd->fcode_major, vpd->fcode_minor);
6819 if (np->parent->plat_type != PLAT_TYPE_NIU)
6820 strlcpy(info->bus_info, pci_name(np->pdev),
6821 sizeof(info->bus_info));
6824 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6826 struct niu *np = netdev_priv(dev);
6827 struct niu_link_config *lp;
6829 lp = &np->link_config;
6831 memset(cmd, 0, sizeof(*cmd));
6832 cmd->phy_address = np->phy_addr;
6833 cmd->supported = lp->supported;
6834 cmd->advertising = lp->active_advertising;
6835 cmd->autoneg = lp->active_autoneg;
6836 ethtool_cmd_speed_set(cmd, lp->active_speed);
6837 cmd->duplex = lp->active_duplex;
6838 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6839 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6840 XCVR_EXTERNAL : XCVR_INTERNAL;
6845 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6847 struct niu *np = netdev_priv(dev);
6848 struct niu_link_config *lp = &np->link_config;
6850 lp->advertising = cmd->advertising;
6851 lp->speed = ethtool_cmd_speed(cmd);
6852 lp->duplex = cmd->duplex;
6853 lp->autoneg = cmd->autoneg;
6854 return niu_init_link(np);
6857 static u32 niu_get_msglevel(struct net_device *dev)
6859 struct niu *np = netdev_priv(dev);
6860 return np->msg_enable;
6863 static void niu_set_msglevel(struct net_device *dev, u32 value)
6865 struct niu *np = netdev_priv(dev);
6866 np->msg_enable = value;
6869 static int niu_nway_reset(struct net_device *dev)
6871 struct niu *np = netdev_priv(dev);
6873 if (np->link_config.autoneg)
6874 return niu_init_link(np);
6879 static int niu_get_eeprom_len(struct net_device *dev)
6881 struct niu *np = netdev_priv(dev);
6883 return np->eeprom_len;
6886 static int niu_get_eeprom(struct net_device *dev,
6887 struct ethtool_eeprom *eeprom, u8 *data)
6889 struct niu *np = netdev_priv(dev);
6890 u32 offset, len, val;
6892 offset = eeprom->offset;
6895 if (offset + len < offset)
6897 if (offset >= np->eeprom_len)
6899 if (offset + len > np->eeprom_len)
6900 len = eeprom->len = np->eeprom_len - offset;
6903 u32 b_offset, b_count;
6905 b_offset = offset & 3;
6906 b_count = 4 - b_offset;
6910 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6911 memcpy(data, ((char *)&val) + b_offset, b_count);
6917 val = nr64(ESPC_NCR(offset / 4));
6918 memcpy(data, &val, 4);
6924 val = nr64(ESPC_NCR(offset / 4));
6925 memcpy(data, &val, len);
6930 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6932 switch (flow_type) {
6943 *pid = IPPROTO_SCTP;
6959 static int niu_class_to_ethflow(u64 class, int *flow_type)
6962 case CLASS_CODE_TCP_IPV4:
6963 *flow_type = TCP_V4_FLOW;
6965 case CLASS_CODE_UDP_IPV4:
6966 *flow_type = UDP_V4_FLOW;
6968 case CLASS_CODE_AH_ESP_IPV4:
6969 *flow_type = AH_V4_FLOW;
6971 case CLASS_CODE_SCTP_IPV4:
6972 *flow_type = SCTP_V4_FLOW;
6974 case CLASS_CODE_TCP_IPV6:
6975 *flow_type = TCP_V6_FLOW;
6977 case CLASS_CODE_UDP_IPV6:
6978 *flow_type = UDP_V6_FLOW;
6980 case CLASS_CODE_AH_ESP_IPV6:
6981 *flow_type = AH_V6_FLOW;
6983 case CLASS_CODE_SCTP_IPV6:
6984 *flow_type = SCTP_V6_FLOW;
6986 case CLASS_CODE_USER_PROG1:
6987 case CLASS_CODE_USER_PROG2:
6988 case CLASS_CODE_USER_PROG3:
6989 case CLASS_CODE_USER_PROG4:
6990 *flow_type = IP_USER_FLOW;
6999 static int niu_ethflow_to_class(int flow_type, u64 *class)
7001 switch (flow_type) {
7003 *class = CLASS_CODE_TCP_IPV4;
7006 *class = CLASS_CODE_UDP_IPV4;
7008 case AH_ESP_V4_FLOW:
7011 *class = CLASS_CODE_AH_ESP_IPV4;
7014 *class = CLASS_CODE_SCTP_IPV4;
7017 *class = CLASS_CODE_TCP_IPV6;
7020 *class = CLASS_CODE_UDP_IPV6;
7022 case AH_ESP_V6_FLOW:
7025 *class = CLASS_CODE_AH_ESP_IPV6;
7028 *class = CLASS_CODE_SCTP_IPV6;
7037 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7041 if (flow_key & FLOW_KEY_L2DA)
7042 ethflow |= RXH_L2DA;
7043 if (flow_key & FLOW_KEY_VLAN)
7044 ethflow |= RXH_VLAN;
7045 if (flow_key & FLOW_KEY_IPSA)
7046 ethflow |= RXH_IP_SRC;
7047 if (flow_key & FLOW_KEY_IPDA)
7048 ethflow |= RXH_IP_DST;
7049 if (flow_key & FLOW_KEY_PROTO)
7050 ethflow |= RXH_L3_PROTO;
7051 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7052 ethflow |= RXH_L4_B_0_1;
7053 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7054 ethflow |= RXH_L4_B_2_3;
7060 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7064 if (ethflow & RXH_L2DA)
7065 key |= FLOW_KEY_L2DA;
7066 if (ethflow & RXH_VLAN)
7067 key |= FLOW_KEY_VLAN;
7068 if (ethflow & RXH_IP_SRC)
7069 key |= FLOW_KEY_IPSA;
7070 if (ethflow & RXH_IP_DST)
7071 key |= FLOW_KEY_IPDA;
7072 if (ethflow & RXH_L3_PROTO)
7073 key |= FLOW_KEY_PROTO;
7074 if (ethflow & RXH_L4_B_0_1)
7075 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7076 if (ethflow & RXH_L4_B_2_3)
7077 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7085 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7091 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7094 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7096 nfc->data = RXH_DISCARD;
7098 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7099 CLASS_CODE_USER_PROG1]);
7103 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7104 struct ethtool_rx_flow_spec *fsp)
7109 tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7110 fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7112 tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7113 fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7115 tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7116 fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7118 tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7119 fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7121 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7122 TCAM_V4KEY2_TOS_SHIFT;
7123 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7124 TCAM_V4KEY2_TOS_SHIFT;
7126 switch (fsp->flow_type) {
7130 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7131 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7132 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7134 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7135 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7136 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7138 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7139 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7140 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7142 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7143 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7144 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7148 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7149 TCAM_V4KEY2_PORT_SPI_SHIFT;
7150 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7152 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7153 TCAM_V4KEY2_PORT_SPI_SHIFT;
7154 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7157 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7158 TCAM_V4KEY2_PORT_SPI_SHIFT;
7159 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7161 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7162 TCAM_V4KEY2_PORT_SPI_SHIFT;
7163 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7165 fsp->h_u.usr_ip4_spec.proto =
7166 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7167 TCAM_V4KEY2_PROTO_SHIFT;
7168 fsp->m_u.usr_ip4_spec.proto =
7169 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7170 TCAM_V4KEY2_PROTO_SHIFT;
7172 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7179 static int niu_get_ethtool_tcam_entry(struct niu *np,
7180 struct ethtool_rxnfc *nfc)
7182 struct niu_parent *parent = np->parent;
7183 struct niu_tcam_entry *tp;
7184 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7189 idx = tcam_get_index(np, (u16)nfc->fs.location);
7191 tp = &parent->tcam[idx];
7193 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7194 parent->index, (u16)nfc->fs.location, idx);
7198 /* fill the flow spec entry */
7199 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7200 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7201 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7204 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7210 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7211 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7212 TCAM_V4KEY2_PROTO_SHIFT;
7213 if (proto == IPPROTO_ESP) {
7214 if (fsp->flow_type == AH_V4_FLOW)
7215 fsp->flow_type = ESP_V4_FLOW;
7217 fsp->flow_type = ESP_V6_FLOW;
7221 switch (fsp->flow_type) {
7227 niu_get_ip4fs_from_tcam_key(tp, fsp);
7234 /* Not yet implemented */
7238 niu_get_ip4fs_from_tcam_key(tp, fsp);
7248 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7249 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7251 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7252 TCAM_ASSOCDATA_OFFSET_SHIFT;
7254 /* put the tcam size here */
7255 nfc->data = tcam_get_size(np);
7260 static int niu_get_ethtool_tcam_all(struct niu *np,
7261 struct ethtool_rxnfc *nfc,
7264 struct niu_parent *parent = np->parent;
7265 struct niu_tcam_entry *tp;
7267 unsigned long flags;
7270 /* put the tcam size here */
7271 nfc->data = tcam_get_size(np);
7273 niu_lock_parent(np, flags);
7274 for (cnt = 0, i = 0; i < nfc->data; i++) {
7275 idx = tcam_get_index(np, i);
7276 tp = &parent->tcam[idx];
7279 if (cnt == nfc->rule_cnt) {
7286 niu_unlock_parent(np, flags);
7288 nfc->rule_cnt = cnt;
7293 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7296 struct niu *np = netdev_priv(dev);
7301 ret = niu_get_hash_opts(np, cmd);
7303 case ETHTOOL_GRXRINGS:
7304 cmd->data = np->num_rx_rings;
7306 case ETHTOOL_GRXCLSRLCNT:
7307 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7309 case ETHTOOL_GRXCLSRULE:
7310 ret = niu_get_ethtool_tcam_entry(np, cmd);
7312 case ETHTOOL_GRXCLSRLALL:
7313 ret = niu_get_ethtool_tcam_all(np, cmd, rule_locs);
7323 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7327 unsigned long flags;
7329 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7332 if (class < CLASS_CODE_USER_PROG1 ||
7333 class > CLASS_CODE_SCTP_IPV6)
7336 if (nfc->data & RXH_DISCARD) {
7337 niu_lock_parent(np, flags);
7338 flow_key = np->parent->tcam_key[class -
7339 CLASS_CODE_USER_PROG1];
7340 flow_key |= TCAM_KEY_DISC;
7341 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7342 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7343 niu_unlock_parent(np, flags);
7346 /* Discard was set before, but is not set now */
7347 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7349 niu_lock_parent(np, flags);
7350 flow_key = np->parent->tcam_key[class -
7351 CLASS_CODE_USER_PROG1];
7352 flow_key &= ~TCAM_KEY_DISC;
7353 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7355 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7357 niu_unlock_parent(np, flags);
7361 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7364 niu_lock_parent(np, flags);
7365 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7366 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7367 niu_unlock_parent(np, flags);
7372 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7373 struct niu_tcam_entry *tp,
7374 int l2_rdc_tab, u64 class)
7377 u32 sip, dip, sipm, dipm, spi, spim;
7378 u16 sport, dport, spm, dpm;
7380 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7381 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7382 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7383 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7385 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7386 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7387 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7388 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7390 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7393 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7394 tp->key_mask[3] |= dipm;
7396 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7397 TCAM_V4KEY2_TOS_SHIFT);
7398 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7399 TCAM_V4KEY2_TOS_SHIFT);
7400 switch (fsp->flow_type) {
7404 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7405 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7406 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7407 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7409 tp->key[2] |= (((u64)sport << 16) | dport);
7410 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7411 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7415 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7416 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7419 tp->key_mask[2] |= spim;
7420 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7423 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7424 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7427 tp->key_mask[2] |= spim;
7428 pid = fsp->h_u.usr_ip4_spec.proto;
7434 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7436 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7440 static int niu_add_ethtool_tcam_entry(struct niu *np,
7441 struct ethtool_rxnfc *nfc)
7443 struct niu_parent *parent = np->parent;
7444 struct niu_tcam_entry *tp;
7445 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7446 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7447 int l2_rdc_table = rdc_table->first_table_num;
7450 unsigned long flags;
7455 idx = nfc->fs.location;
7456 if (idx >= tcam_get_size(np))
7459 if (fsp->flow_type == IP_USER_FLOW) {
7461 int add_usr_cls = 0;
7462 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7463 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7465 if (uspec->ip_ver != ETH_RX_NFC_IP4)
7468 niu_lock_parent(np, flags);
7470 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7471 if (parent->l3_cls[i]) {
7472 if (uspec->proto == parent->l3_cls_pid[i]) {
7473 class = parent->l3_cls[i];
7474 parent->l3_cls_refcnt[i]++;
7479 /* Program new user IP class */
7482 class = CLASS_CODE_USER_PROG1;
7485 class = CLASS_CODE_USER_PROG2;
7488 class = CLASS_CODE_USER_PROG3;
7491 class = CLASS_CODE_USER_PROG4;
7496 ret = tcam_user_ip_class_set(np, class, 0,
7503 ret = tcam_user_ip_class_enable(np, class, 1);
7506 parent->l3_cls[i] = class;
7507 parent->l3_cls_pid[i] = uspec->proto;
7508 parent->l3_cls_refcnt[i]++;
7514 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7515 parent->index, __func__, uspec->proto);
7519 niu_unlock_parent(np, flags);
7521 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7526 niu_lock_parent(np, flags);
7528 idx = tcam_get_index(np, idx);
7529 tp = &parent->tcam[idx];
7531 memset(tp, 0, sizeof(*tp));
7533 /* fill in the tcam key and mask */
7534 switch (fsp->flow_type) {
7540 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7547 /* Not yet implemented */
7548 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7549 parent->index, __func__, fsp->flow_type);
7553 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7556 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7557 parent->index, __func__, fsp->flow_type);
7562 /* fill in the assoc data */
7563 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7564 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7566 if (fsp->ring_cookie >= np->num_rx_rings) {
7567 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7568 parent->index, __func__,
7569 (long long)fsp->ring_cookie);
7573 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7574 (fsp->ring_cookie <<
7575 TCAM_ASSOCDATA_OFFSET_SHIFT));
7578 err = tcam_write(np, idx, tp->key, tp->key_mask);
7583 err = tcam_assoc_write(np, idx, tp->assoc_data);
7589 /* validate the entry */
7591 np->clas.tcam_valid_entries++;
7593 niu_unlock_parent(np, flags);
7598 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7600 struct niu_parent *parent = np->parent;
7601 struct niu_tcam_entry *tp;
7603 unsigned long flags;
7607 if (loc >= tcam_get_size(np))
7610 niu_lock_parent(np, flags);
7612 idx = tcam_get_index(np, loc);
7613 tp = &parent->tcam[idx];
7615 /* if the entry is of a user defined class, then update*/
7616 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7617 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7619 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7621 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7622 if (parent->l3_cls[i] == class) {
7623 parent->l3_cls_refcnt[i]--;
7624 if (!parent->l3_cls_refcnt[i]) {
7626 ret = tcam_user_ip_class_enable(np,
7631 parent->l3_cls[i] = 0;
7632 parent->l3_cls_pid[i] = 0;
7637 if (i == NIU_L3_PROG_CLS) {
7638 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7639 parent->index, __func__,
7640 (unsigned long long)class);
7646 ret = tcam_flush(np, idx);
7650 /* invalidate the entry */
7652 np->clas.tcam_valid_entries--;
7654 niu_unlock_parent(np, flags);
7659 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7661 struct niu *np = netdev_priv(dev);
7666 ret = niu_set_hash_opts(np, cmd);
7668 case ETHTOOL_SRXCLSRLINS:
7669 ret = niu_add_ethtool_tcam_entry(np, cmd);
7671 case ETHTOOL_SRXCLSRLDEL:
7672 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7682 static const struct {
7683 const char string[ETH_GSTRING_LEN];
7684 } niu_xmac_stat_keys[] = {
7687 { "tx_fifo_errors" },
7688 { "tx_overflow_errors" },
7689 { "tx_max_pkt_size_errors" },
7690 { "tx_underflow_errors" },
7691 { "rx_local_faults" },
7692 { "rx_remote_faults" },
7693 { "rx_link_faults" },
7694 { "rx_align_errors" },
7706 { "rx_code_violations" },
7707 { "rx_len_errors" },
7708 { "rx_crc_errors" },
7709 { "rx_underflows" },
7711 { "pause_off_state" },
7712 { "pause_on_state" },
7713 { "pause_received" },
7716 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7718 static const struct {
7719 const char string[ETH_GSTRING_LEN];
7720 } niu_bmac_stat_keys[] = {
7721 { "tx_underflow_errors" },
7722 { "tx_max_pkt_size_errors" },
7727 { "rx_align_errors" },
7728 { "rx_crc_errors" },
7729 { "rx_len_errors" },
7730 { "pause_off_state" },
7731 { "pause_on_state" },
7732 { "pause_received" },
7735 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7737 static const struct {
7738 const char string[ETH_GSTRING_LEN];
7739 } niu_rxchan_stat_keys[] = {
7747 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7749 static const struct {
7750 const char string[ETH_GSTRING_LEN];
7751 } niu_txchan_stat_keys[] = {
7758 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7760 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7762 struct niu *np = netdev_priv(dev);
7765 if (stringset != ETH_SS_STATS)
7768 if (np->flags & NIU_FLAGS_XMAC) {
7769 memcpy(data, niu_xmac_stat_keys,
7770 sizeof(niu_xmac_stat_keys));
7771 data += sizeof(niu_xmac_stat_keys);
7773 memcpy(data, niu_bmac_stat_keys,
7774 sizeof(niu_bmac_stat_keys));
7775 data += sizeof(niu_bmac_stat_keys);
7777 for (i = 0; i < np->num_rx_rings; i++) {
7778 memcpy(data, niu_rxchan_stat_keys,
7779 sizeof(niu_rxchan_stat_keys));
7780 data += sizeof(niu_rxchan_stat_keys);
7782 for (i = 0; i < np->num_tx_rings; i++) {
7783 memcpy(data, niu_txchan_stat_keys,
7784 sizeof(niu_txchan_stat_keys));
7785 data += sizeof(niu_txchan_stat_keys);
7789 static int niu_get_sset_count(struct net_device *dev, int stringset)
7791 struct niu *np = netdev_priv(dev);
7793 if (stringset != ETH_SS_STATS)
7796 return (np->flags & NIU_FLAGS_XMAC ?
7797 NUM_XMAC_STAT_KEYS :
7798 NUM_BMAC_STAT_KEYS) +
7799 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7800 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS);
7803 static void niu_get_ethtool_stats(struct net_device *dev,
7804 struct ethtool_stats *stats, u64 *data)
7806 struct niu *np = netdev_priv(dev);
7809 niu_sync_mac_stats(np);
7810 if (np->flags & NIU_FLAGS_XMAC) {
7811 memcpy(data, &np->mac_stats.xmac,
7812 sizeof(struct niu_xmac_stats));
7813 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7815 memcpy(data, &np->mac_stats.bmac,
7816 sizeof(struct niu_bmac_stats));
7817 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7819 for (i = 0; i < np->num_rx_rings; i++) {
7820 struct rx_ring_info *rp = &np->rx_rings[i];
7822 niu_sync_rx_discard_stats(np, rp, 0);
7824 data[0] = rp->rx_channel;
7825 data[1] = rp->rx_packets;
7826 data[2] = rp->rx_bytes;
7827 data[3] = rp->rx_dropped;
7828 data[4] = rp->rx_errors;
7831 for (i = 0; i < np->num_tx_rings; i++) {
7832 struct tx_ring_info *rp = &np->tx_rings[i];
7834 data[0] = rp->tx_channel;
7835 data[1] = rp->tx_packets;
7836 data[2] = rp->tx_bytes;
7837 data[3] = rp->tx_errors;
7842 static u64 niu_led_state_save(struct niu *np)
7844 if (np->flags & NIU_FLAGS_XMAC)
7845 return nr64_mac(XMAC_CONFIG);
7847 return nr64_mac(BMAC_XIF_CONFIG);
7850 static void niu_led_state_restore(struct niu *np, u64 val)
7852 if (np->flags & NIU_FLAGS_XMAC)
7853 nw64_mac(XMAC_CONFIG, val);
7855 nw64_mac(BMAC_XIF_CONFIG, val);
7858 static void niu_force_led(struct niu *np, int on)
7862 if (np->flags & NIU_FLAGS_XMAC) {
7864 bit = XMAC_CONFIG_FORCE_LED_ON;
7866 reg = BMAC_XIF_CONFIG;
7867 bit = BMAC_XIF_CONFIG_LINK_LED;
7870 val = nr64_mac(reg);
7878 static int niu_set_phys_id(struct net_device *dev,
7879 enum ethtool_phys_id_state state)
7882 struct niu *np = netdev_priv(dev);
7884 if (!netif_running(dev))
7888 case ETHTOOL_ID_ACTIVE:
7889 np->orig_led_state = niu_led_state_save(np);
7890 return 1; /* cycle on/off once per second */
7893 niu_force_led(np, 1);
7896 case ETHTOOL_ID_OFF:
7897 niu_force_led(np, 0);
7900 case ETHTOOL_ID_INACTIVE:
7901 niu_led_state_restore(np, np->orig_led_state);
7907 static const struct ethtool_ops niu_ethtool_ops = {
7908 .get_drvinfo = niu_get_drvinfo,
7909 .get_link = ethtool_op_get_link,
7910 .get_msglevel = niu_get_msglevel,
7911 .set_msglevel = niu_set_msglevel,
7912 .nway_reset = niu_nway_reset,
7913 .get_eeprom_len = niu_get_eeprom_len,
7914 .get_eeprom = niu_get_eeprom,
7915 .get_settings = niu_get_settings,
7916 .set_settings = niu_set_settings,
7917 .get_strings = niu_get_strings,
7918 .get_sset_count = niu_get_sset_count,
7919 .get_ethtool_stats = niu_get_ethtool_stats,
7920 .set_phys_id = niu_set_phys_id,
7921 .get_rxnfc = niu_get_nfc,
7922 .set_rxnfc = niu_set_nfc,
7925 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7928 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7930 if (ldn < 0 || ldn > LDN_MAX)
7933 parent->ldg_map[ldn] = ldg;
7935 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7936 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7937 * the firmware, and we're not supposed to change them.
7938 * Validate the mapping, because if it's wrong we probably
7939 * won't get any interrupts and that's painful to debug.
7941 if (nr64(LDG_NUM(ldn)) != ldg) {
7942 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7944 (unsigned long long) nr64(LDG_NUM(ldn)));
7948 nw64(LDG_NUM(ldn), ldg);
7953 static int niu_set_ldg_timer_res(struct niu *np, int res)
7955 if (res < 0 || res > LDG_TIMER_RES_VAL)
7959 nw64(LDG_TIMER_RES, res);
7964 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7966 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7967 (func < 0 || func > 3) ||
7968 (vector < 0 || vector > 0x1f))
7971 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7976 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7978 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7979 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7982 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7986 nw64(ESPC_PIO_STAT, frame);
7990 frame = nr64(ESPC_PIO_STAT);
7991 if (frame & ESPC_PIO_STAT_READ_END)
7994 if (!(frame & ESPC_PIO_STAT_READ_END)) {
7995 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
7996 (unsigned long long) frame);
8001 nw64(ESPC_PIO_STAT, frame);
8005 frame = nr64(ESPC_PIO_STAT);
8006 if (frame & ESPC_PIO_STAT_READ_END)
8009 if (!(frame & ESPC_PIO_STAT_READ_END)) {
8010 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8011 (unsigned long long) frame);
8015 frame = nr64(ESPC_PIO_STAT);
8016 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8019 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8021 int err = niu_pci_eeprom_read(np, off);
8027 err = niu_pci_eeprom_read(np, off + 1);
8030 val |= (err & 0xff);
8035 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8037 int err = niu_pci_eeprom_read(np, off);
8044 err = niu_pci_eeprom_read(np, off + 1);
8048 val |= (err & 0xff) << 8;
8053 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8060 for (i = 0; i < namebuf_len; i++) {
8061 int err = niu_pci_eeprom_read(np, off + i);
8068 if (i >= namebuf_len)
8074 static void __devinit niu_vpd_parse_version(struct niu *np)
8076 struct niu_vpd *vpd = &np->vpd;
8077 int len = strlen(vpd->version) + 1;
8078 const char *s = vpd->version;
8081 for (i = 0; i < len - 5; i++) {
8082 if (!strncmp(s + i, "FCode ", 6))
8089 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8091 netif_printk(np, probe, KERN_DEBUG, np->dev,
8092 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8093 vpd->fcode_major, vpd->fcode_minor);
8094 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8095 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8096 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8097 np->flags |= NIU_FLAGS_VPD_VALID;
8100 /* ESPC_PIO_EN_ENABLE must be set */
8101 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8104 unsigned int found_mask = 0;
8105 #define FOUND_MASK_MODEL 0x00000001
8106 #define FOUND_MASK_BMODEL 0x00000002
8107 #define FOUND_MASK_VERS 0x00000004
8108 #define FOUND_MASK_MAC 0x00000008
8109 #define FOUND_MASK_NMAC 0x00000010
8110 #define FOUND_MASK_PHY 0x00000020
8111 #define FOUND_MASK_ALL 0x0000003f
8113 netif_printk(np, probe, KERN_DEBUG, np->dev,
8114 "VPD_SCAN: start[%x] end[%x]\n", start, end);
8115 while (start < end) {
8116 int len, err, prop_len;
8121 if (found_mask == FOUND_MASK_ALL) {
8122 niu_vpd_parse_version(np);
8126 err = niu_pci_eeprom_read(np, start + 2);
8132 prop_len = niu_pci_eeprom_read(np, start + 4);
8133 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8139 if (!strcmp(namebuf, "model")) {
8140 prop_buf = np->vpd.model;
8141 max_len = NIU_VPD_MODEL_MAX;
8142 found_mask |= FOUND_MASK_MODEL;
8143 } else if (!strcmp(namebuf, "board-model")) {
8144 prop_buf = np->vpd.board_model;
8145 max_len = NIU_VPD_BD_MODEL_MAX;
8146 found_mask |= FOUND_MASK_BMODEL;
8147 } else if (!strcmp(namebuf, "version")) {
8148 prop_buf = np->vpd.version;
8149 max_len = NIU_VPD_VERSION_MAX;
8150 found_mask |= FOUND_MASK_VERS;
8151 } else if (!strcmp(namebuf, "local-mac-address")) {
8152 prop_buf = np->vpd.local_mac;
8154 found_mask |= FOUND_MASK_MAC;
8155 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8156 prop_buf = &np->vpd.mac_num;
8158 found_mask |= FOUND_MASK_NMAC;
8159 } else if (!strcmp(namebuf, "phy-type")) {
8160 prop_buf = np->vpd.phy_type;
8161 max_len = NIU_VPD_PHY_TYPE_MAX;
8162 found_mask |= FOUND_MASK_PHY;
8165 if (max_len && prop_len > max_len) {
8166 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
8171 u32 off = start + 5 + err;
8174 netif_printk(np, probe, KERN_DEBUG, np->dev,
8175 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8177 for (i = 0; i < prop_len; i++)
8178 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8187 /* ESPC_PIO_EN_ENABLE must be set */
8188 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8193 err = niu_pci_eeprom_read16_swp(np, start + 1);
8199 while (start + offset < ESPC_EEPROM_SIZE) {
8200 u32 here = start + offset;
8203 err = niu_pci_eeprom_read(np, here);
8207 err = niu_pci_eeprom_read16_swp(np, here + 1);
8211 here = start + offset + 3;
8212 end = start + offset + err;
8216 err = niu_pci_vpd_scan_props(np, here, end);
8217 if (err < 0 || err == 1)
8222 /* ESPC_PIO_EN_ENABLE must be set */
8223 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8225 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8228 while (start < end) {
8231 /* ROM header signature? */
8232 err = niu_pci_eeprom_read16(np, start + 0);
8236 /* Apply offset to PCI data structure. */
8237 err = niu_pci_eeprom_read16(np, start + 23);
8242 /* Check for "PCIR" signature. */
8243 err = niu_pci_eeprom_read16(np, start + 0);
8246 err = niu_pci_eeprom_read16(np, start + 2);
8250 /* Check for OBP image type. */
8251 err = niu_pci_eeprom_read(np, start + 20);
8255 err = niu_pci_eeprom_read(np, ret + 2);
8259 start = ret + (err * 512);
8263 err = niu_pci_eeprom_read16_swp(np, start + 8);
8268 err = niu_pci_eeprom_read(np, ret + 0);
8278 static int __devinit niu_phy_type_prop_decode(struct niu *np,
8279 const char *phy_prop)
8281 if (!strcmp(phy_prop, "mif")) {
8282 /* 1G copper, MII */
8283 np->flags &= ~(NIU_FLAGS_FIBER |
8285 np->mac_xcvr = MAC_XCVR_MII;
8286 } else if (!strcmp(phy_prop, "xgf")) {
8287 /* 10G fiber, XPCS */
8288 np->flags |= (NIU_FLAGS_10G |
8290 np->mac_xcvr = MAC_XCVR_XPCS;
8291 } else if (!strcmp(phy_prop, "pcs")) {
8293 np->flags &= ~NIU_FLAGS_10G;
8294 np->flags |= NIU_FLAGS_FIBER;
8295 np->mac_xcvr = MAC_XCVR_PCS;
8296 } else if (!strcmp(phy_prop, "xgc")) {
8297 /* 10G copper, XPCS */
8298 np->flags |= NIU_FLAGS_10G;
8299 np->flags &= ~NIU_FLAGS_FIBER;
8300 np->mac_xcvr = MAC_XCVR_XPCS;
8301 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8302 /* 10G Serdes or 1G Serdes, default to 10G */
8303 np->flags |= NIU_FLAGS_10G;
8304 np->flags &= ~NIU_FLAGS_FIBER;
8305 np->flags |= NIU_FLAGS_XCVR_SERDES;
8306 np->mac_xcvr = MAC_XCVR_XPCS;
8313 static int niu_pci_vpd_get_nports(struct niu *np)
8317 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8318 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8319 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8320 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8321 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8323 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8324 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8325 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8326 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8333 static void __devinit niu_pci_vpd_validate(struct niu *np)
8335 struct net_device *dev = np->dev;
8336 struct niu_vpd *vpd = &np->vpd;
8339 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8340 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
8342 np->flags &= ~NIU_FLAGS_VPD_VALID;
8346 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8347 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8348 np->flags |= NIU_FLAGS_10G;
8349 np->flags &= ~NIU_FLAGS_FIBER;
8350 np->flags |= NIU_FLAGS_XCVR_SERDES;
8351 np->mac_xcvr = MAC_XCVR_PCS;
8353 np->flags |= NIU_FLAGS_FIBER;
8354 np->flags &= ~NIU_FLAGS_10G;
8356 if (np->flags & NIU_FLAGS_10G)
8357 np->mac_xcvr = MAC_XCVR_XPCS;
8358 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8359 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8360 NIU_FLAGS_HOTPLUG_PHY);
8361 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8362 dev_err(np->device, "Illegal phy string [%s]\n",
8364 dev_err(np->device, "Falling back to SPROM\n");
8365 np->flags &= ~NIU_FLAGS_VPD_VALID;
8369 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8371 val8 = dev->perm_addr[5];
8372 dev->perm_addr[5] += np->port;
8373 if (dev->perm_addr[5] < val8)
8374 dev->perm_addr[4]++;
8376 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8379 static int __devinit niu_pci_probe_sprom(struct niu *np)
8381 struct net_device *dev = np->dev;
8386 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8387 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8390 np->eeprom_len = len;
8392 netif_printk(np, probe, KERN_DEBUG, np->dev,
8393 "SPROM: Image size %llu\n", (unsigned long long)val);
8396 for (i = 0; i < len; i++) {
8397 val = nr64(ESPC_NCR(i));
8398 sum += (val >> 0) & 0xff;
8399 sum += (val >> 8) & 0xff;
8400 sum += (val >> 16) & 0xff;
8401 sum += (val >> 24) & 0xff;
8403 netif_printk(np, probe, KERN_DEBUG, np->dev,
8404 "SPROM: Checksum %x\n", (int)(sum & 0xff));
8405 if ((sum & 0xff) != 0xab) {
8406 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
8410 val = nr64(ESPC_PHY_TYPE);
8413 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8414 ESPC_PHY_TYPE_PORT0_SHIFT;
8417 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8418 ESPC_PHY_TYPE_PORT1_SHIFT;
8421 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8422 ESPC_PHY_TYPE_PORT2_SHIFT;
8425 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8426 ESPC_PHY_TYPE_PORT3_SHIFT;
8429 dev_err(np->device, "Bogus port number %u\n",
8433 netif_printk(np, probe, KERN_DEBUG, np->dev,
8434 "SPROM: PHY type %x\n", val8);
8437 case ESPC_PHY_TYPE_1G_COPPER:
8438 /* 1G copper, MII */
8439 np->flags &= ~(NIU_FLAGS_FIBER |
8441 np->mac_xcvr = MAC_XCVR_MII;
8444 case ESPC_PHY_TYPE_1G_FIBER:
8446 np->flags &= ~NIU_FLAGS_10G;
8447 np->flags |= NIU_FLAGS_FIBER;
8448 np->mac_xcvr = MAC_XCVR_PCS;
8451 case ESPC_PHY_TYPE_10G_COPPER:
8452 /* 10G copper, XPCS */
8453 np->flags |= NIU_FLAGS_10G;
8454 np->flags &= ~NIU_FLAGS_FIBER;
8455 np->mac_xcvr = MAC_XCVR_XPCS;
8458 case ESPC_PHY_TYPE_10G_FIBER:
8459 /* 10G fiber, XPCS */
8460 np->flags |= (NIU_FLAGS_10G |
8462 np->mac_xcvr = MAC_XCVR_XPCS;
8466 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
8470 val = nr64(ESPC_MAC_ADDR0);
8471 netif_printk(np, probe, KERN_DEBUG, np->dev,
8472 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8473 dev->perm_addr[0] = (val >> 0) & 0xff;
8474 dev->perm_addr[1] = (val >> 8) & 0xff;
8475 dev->perm_addr[2] = (val >> 16) & 0xff;
8476 dev->perm_addr[3] = (val >> 24) & 0xff;
8478 val = nr64(ESPC_MAC_ADDR1);
8479 netif_printk(np, probe, KERN_DEBUG, np->dev,
8480 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8481 dev->perm_addr[4] = (val >> 0) & 0xff;
8482 dev->perm_addr[5] = (val >> 8) & 0xff;
8484 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8485 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8490 val8 = dev->perm_addr[5];
8491 dev->perm_addr[5] += np->port;
8492 if (dev->perm_addr[5] < val8)
8493 dev->perm_addr[4]++;
8495 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8497 val = nr64(ESPC_MOD_STR_LEN);
8498 netif_printk(np, probe, KERN_DEBUG, np->dev,
8499 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8503 for (i = 0; i < val; i += 4) {
8504 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8506 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8507 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8508 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8509 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8511 np->vpd.model[val] = '\0';
8513 val = nr64(ESPC_BD_MOD_STR_LEN);
8514 netif_printk(np, probe, KERN_DEBUG, np->dev,
8515 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8519 for (i = 0; i < val; i += 4) {
8520 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8522 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8523 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8524 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8525 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8527 np->vpd.board_model[val] = '\0';
8530 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8531 netif_printk(np, probe, KERN_DEBUG, np->dev,
8532 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
8537 static int __devinit niu_get_and_validate_port(struct niu *np)
8539 struct niu_parent *parent = np->parent;
8542 np->flags |= NIU_FLAGS_XMAC;
8544 if (!parent->num_ports) {
8545 if (parent->plat_type == PLAT_TYPE_NIU) {
8546 parent->num_ports = 2;
8548 parent->num_ports = niu_pci_vpd_get_nports(np);
8549 if (!parent->num_ports) {
8550 /* Fall back to SPROM as last resort.
8551 * This will fail on most cards.
8553 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8554 ESPC_NUM_PORTS_MACS_VAL;
8556 /* All of the current probing methods fail on
8557 * Maramba on-board parts.
8559 if (!parent->num_ports)
8560 parent->num_ports = 4;
8565 if (np->port >= parent->num_ports)
8571 static int __devinit phy_record(struct niu_parent *parent,
8572 struct phy_probe_info *p,
8573 int dev_id_1, int dev_id_2, u8 phy_port,
8576 u32 id = (dev_id_1 << 16) | dev_id_2;
8579 if (dev_id_1 < 0 || dev_id_2 < 0)
8581 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8582 /* Because of the NIU_PHY_ID_MASK being applied, the 8704
8583 * test covers the 8706 as well.
8585 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8586 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011))
8589 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8593 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8595 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8596 type == PHY_TYPE_PCS ? "PCS" : "MII",
8599 if (p->cur[type] >= NIU_MAX_PORTS) {
8600 pr_err("Too many PHY ports\n");
8604 p->phy_id[type][idx] = id;
8605 p->phy_port[type][idx] = phy_port;
8606 p->cur[type] = idx + 1;
8610 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8614 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8615 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8618 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8619 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8626 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8632 for (port = 8; port < 32; port++) {
8633 if (port_has_10g(p, port)) {
8643 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8646 if (p->cur[PHY_TYPE_MII])
8647 *lowest = p->phy_port[PHY_TYPE_MII][0];
8649 return p->cur[PHY_TYPE_MII];
8652 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8654 int num_ports = parent->num_ports;
8657 for (i = 0; i < num_ports; i++) {
8658 parent->rxchan_per_port[i] = (16 / num_ports);
8659 parent->txchan_per_port[i] = (16 / num_ports);
8661 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8663 parent->rxchan_per_port[i],
8664 parent->txchan_per_port[i]);
8668 static void __devinit niu_divide_channels(struct niu_parent *parent,
8669 int num_10g, int num_1g)
8671 int num_ports = parent->num_ports;
8672 int rx_chans_per_10g, rx_chans_per_1g;
8673 int tx_chans_per_10g, tx_chans_per_1g;
8674 int i, tot_rx, tot_tx;
8676 if (!num_10g || !num_1g) {
8677 rx_chans_per_10g = rx_chans_per_1g =
8678 (NIU_NUM_RXCHAN / num_ports);
8679 tx_chans_per_10g = tx_chans_per_1g =
8680 (NIU_NUM_TXCHAN / num_ports);
8682 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8683 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8684 (rx_chans_per_1g * num_1g)) /
8687 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8688 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8689 (tx_chans_per_1g * num_1g)) /
8693 tot_rx = tot_tx = 0;
8694 for (i = 0; i < num_ports; i++) {
8695 int type = phy_decode(parent->port_phy, i);
8697 if (type == PORT_TYPE_10G) {
8698 parent->rxchan_per_port[i] = rx_chans_per_10g;
8699 parent->txchan_per_port[i] = tx_chans_per_10g;
8701 parent->rxchan_per_port[i] = rx_chans_per_1g;
8702 parent->txchan_per_port[i] = tx_chans_per_1g;
8704 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8706 parent->rxchan_per_port[i],
8707 parent->txchan_per_port[i]);
8708 tot_rx += parent->rxchan_per_port[i];
8709 tot_tx += parent->txchan_per_port[i];
8712 if (tot_rx > NIU_NUM_RXCHAN) {
8713 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8714 parent->index, tot_rx);
8715 for (i = 0; i < num_ports; i++)
8716 parent->rxchan_per_port[i] = 1;
8718 if (tot_tx > NIU_NUM_TXCHAN) {
8719 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8720 parent->index, tot_tx);
8721 for (i = 0; i < num_ports; i++)
8722 parent->txchan_per_port[i] = 1;
8724 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8725 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8726 parent->index, tot_rx, tot_tx);
8730 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8731 int num_10g, int num_1g)
8733 int i, num_ports = parent->num_ports;
8734 int rdc_group, rdc_groups_per_port;
8735 int rdc_channel_base;
8738 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8740 rdc_channel_base = 0;
8742 for (i = 0; i < num_ports; i++) {
8743 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8744 int grp, num_channels = parent->rxchan_per_port[i];
8745 int this_channel_offset;
8747 tp->first_table_num = rdc_group;
8748 tp->num_tables = rdc_groups_per_port;
8749 this_channel_offset = 0;
8750 for (grp = 0; grp < tp->num_tables; grp++) {
8751 struct rdc_table *rt = &tp->tables[grp];
8754 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8755 parent->index, i, tp->first_table_num + grp);
8756 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8757 rt->rxdma_channel[slot] =
8758 rdc_channel_base + this_channel_offset;
8760 pr_cont("%d ", rt->rxdma_channel[slot]);
8762 if (++this_channel_offset == num_channels)
8763 this_channel_offset = 0;
8768 parent->rdc_default[i] = rdc_channel_base;
8770 rdc_channel_base += num_channels;
8771 rdc_group += rdc_groups_per_port;
8775 static int __devinit fill_phy_probe_info(struct niu *np,
8776 struct niu_parent *parent,
8777 struct phy_probe_info *info)
8779 unsigned long flags;
8782 memset(info, 0, sizeof(*info));
8784 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8785 niu_lock_parent(np, flags);
8787 for (port = 8; port < 32; port++) {
8788 int dev_id_1, dev_id_2;
8790 dev_id_1 = mdio_read(np, port,
8791 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8792 dev_id_2 = mdio_read(np, port,
8793 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8794 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8798 dev_id_1 = mdio_read(np, port,
8799 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8800 dev_id_2 = mdio_read(np, port,
8801 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8802 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8806 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8807 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8808 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8813 niu_unlock_parent(np, flags);
8818 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8820 struct phy_probe_info *info = &parent->phy_probe_info;
8821 int lowest_10g, lowest_1g;
8822 int num_10g, num_1g;
8826 num_10g = num_1g = 0;
8828 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8829 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8832 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8833 parent->num_ports = 4;
8834 val = (phy_encode(PORT_TYPE_1G, 0) |
8835 phy_encode(PORT_TYPE_1G, 1) |
8836 phy_encode(PORT_TYPE_1G, 2) |
8837 phy_encode(PORT_TYPE_1G, 3));
8838 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8841 parent->num_ports = 2;
8842 val = (phy_encode(PORT_TYPE_10G, 0) |
8843 phy_encode(PORT_TYPE_10G, 1));
8844 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8845 (parent->plat_type == PLAT_TYPE_NIU)) {
8846 /* this is the Monza case */
8847 if (np->flags & NIU_FLAGS_10G) {
8848 val = (phy_encode(PORT_TYPE_10G, 0) |
8849 phy_encode(PORT_TYPE_10G, 1));
8851 val = (phy_encode(PORT_TYPE_1G, 0) |
8852 phy_encode(PORT_TYPE_1G, 1));
8855 err = fill_phy_probe_info(np, parent, info);
8859 num_10g = count_10g_ports(info, &lowest_10g);
8860 num_1g = count_1g_ports(info, &lowest_1g);
8862 switch ((num_10g << 4) | num_1g) {
8864 if (lowest_1g == 10)
8865 parent->plat_type = PLAT_TYPE_VF_P0;
8866 else if (lowest_1g == 26)
8867 parent->plat_type = PLAT_TYPE_VF_P1;
8869 goto unknown_vg_1g_port;
8873 val = (phy_encode(PORT_TYPE_10G, 0) |
8874 phy_encode(PORT_TYPE_10G, 1) |
8875 phy_encode(PORT_TYPE_1G, 2) |
8876 phy_encode(PORT_TYPE_1G, 3));
8880 val = (phy_encode(PORT_TYPE_10G, 0) |
8881 phy_encode(PORT_TYPE_10G, 1));
8885 val = phy_encode(PORT_TYPE_10G, np->port);
8889 if (lowest_1g == 10)
8890 parent->plat_type = PLAT_TYPE_VF_P0;
8891 else if (lowest_1g == 26)
8892 parent->plat_type = PLAT_TYPE_VF_P1;
8894 goto unknown_vg_1g_port;
8898 if ((lowest_10g & 0x7) == 0)
8899 val = (phy_encode(PORT_TYPE_10G, 0) |
8900 phy_encode(PORT_TYPE_1G, 1) |
8901 phy_encode(PORT_TYPE_1G, 2) |
8902 phy_encode(PORT_TYPE_1G, 3));
8904 val = (phy_encode(PORT_TYPE_1G, 0) |
8905 phy_encode(PORT_TYPE_10G, 1) |
8906 phy_encode(PORT_TYPE_1G, 2) |
8907 phy_encode(PORT_TYPE_1G, 3));
8911 if (lowest_1g == 10)
8912 parent->plat_type = PLAT_TYPE_VF_P0;
8913 else if (lowest_1g == 26)
8914 parent->plat_type = PLAT_TYPE_VF_P1;
8916 goto unknown_vg_1g_port;
8918 val = (phy_encode(PORT_TYPE_1G, 0) |
8919 phy_encode(PORT_TYPE_1G, 1) |
8920 phy_encode(PORT_TYPE_1G, 2) |
8921 phy_encode(PORT_TYPE_1G, 3));
8925 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8931 parent->port_phy = val;
8933 if (parent->plat_type == PLAT_TYPE_NIU)
8934 niu_n2_divide_channels(parent);
8936 niu_divide_channels(parent, num_10g, num_1g);
8938 niu_divide_rdc_groups(parent, num_10g, num_1g);
8943 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
8947 static int __devinit niu_probe_ports(struct niu *np)
8949 struct niu_parent *parent = np->parent;
8952 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8953 err = walk_phys(np, parent);
8957 niu_set_ldg_timer_res(np, 2);
8958 for (i = 0; i <= LDN_MAX; i++)
8959 niu_ldn_irq_enable(np, i, 0);
8962 if (parent->port_phy == PORT_PHY_INVALID)
8968 static int __devinit niu_classifier_swstate_init(struct niu *np)
8970 struct niu_classifier *cp = &np->clas;
8972 cp->tcam_top = (u16) np->port;
8973 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
8974 cp->h1_init = 0xffffffff;
8975 cp->h2_init = 0xffff;
8977 return fflp_early_init(np);
8980 static void __devinit niu_link_config_init(struct niu *np)
8982 struct niu_link_config *lp = &np->link_config;
8984 lp->advertising = (ADVERTISED_10baseT_Half |
8985 ADVERTISED_10baseT_Full |
8986 ADVERTISED_100baseT_Half |
8987 ADVERTISED_100baseT_Full |
8988 ADVERTISED_1000baseT_Half |
8989 ADVERTISED_1000baseT_Full |
8990 ADVERTISED_10000baseT_Full |
8991 ADVERTISED_Autoneg);
8992 lp->speed = lp->active_speed = SPEED_INVALID;
8993 lp->duplex = DUPLEX_FULL;
8994 lp->active_duplex = DUPLEX_INVALID;
8997 lp->loopback_mode = LOOPBACK_MAC;
8998 lp->active_speed = SPEED_10000;
8999 lp->active_duplex = DUPLEX_FULL;
9001 lp->loopback_mode = LOOPBACK_DISABLED;
9005 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9009 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9010 np->ipp_off = 0x00000;
9011 np->pcs_off = 0x04000;
9012 np->xpcs_off = 0x02000;
9016 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9017 np->ipp_off = 0x08000;
9018 np->pcs_off = 0x0a000;
9019 np->xpcs_off = 0x08000;
9023 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9024 np->ipp_off = 0x04000;
9025 np->pcs_off = 0x0e000;
9026 np->xpcs_off = ~0UL;
9030 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9031 np->ipp_off = 0x0c000;
9032 np->pcs_off = 0x12000;
9033 np->xpcs_off = ~0UL;
9037 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9044 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9046 struct msix_entry msi_vec[NIU_NUM_LDG];
9047 struct niu_parent *parent = np->parent;
9048 struct pci_dev *pdev = np->pdev;
9049 int i, num_irqs, err;
9052 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9053 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9054 ldg_num_map[i] = first_ldg + i;
9056 num_irqs = (parent->rxchan_per_port[np->port] +
9057 parent->txchan_per_port[np->port] +
9058 (np->port == 0 ? 3 : 1));
9059 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9062 for (i = 0; i < num_irqs; i++) {
9063 msi_vec[i].vector = 0;
9064 msi_vec[i].entry = i;
9067 err = pci_enable_msix(pdev, msi_vec, num_irqs);
9069 np->flags &= ~NIU_FLAGS_MSIX;
9077 np->flags |= NIU_FLAGS_MSIX;
9078 for (i = 0; i < num_irqs; i++)
9079 np->ldg[i].irq = msi_vec[i].vector;
9080 np->num_ldg = num_irqs;
9083 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9085 #ifdef CONFIG_SPARC64
9086 struct platform_device *op = np->op;
9087 const u32 *int_prop;
9090 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
9094 for (i = 0; i < op->archdata.num_irqs; i++) {
9095 ldg_num_map[i] = int_prop[i];
9096 np->ldg[i].irq = op->archdata.irqs[i];
9099 np->num_ldg = op->archdata.num_irqs;
9107 static int __devinit niu_ldg_init(struct niu *np)
9109 struct niu_parent *parent = np->parent;
9110 u8 ldg_num_map[NIU_NUM_LDG];
9111 int first_chan, num_chan;
9112 int i, err, ldg_rotor;
9116 np->ldg[0].irq = np->dev->irq;
9117 if (parent->plat_type == PLAT_TYPE_NIU) {
9118 err = niu_n2_irq_init(np, ldg_num_map);
9122 niu_try_msix(np, ldg_num_map);
9125 for (i = 0; i < np->num_ldg; i++) {
9126 struct niu_ldg *lp = &np->ldg[i];
9128 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9131 lp->ldg_num = ldg_num_map[i];
9132 lp->timer = 2; /* XXX */
9134 /* On N2 NIU the firmware has setup the SID mappings so they go
9135 * to the correct values that will route the LDG to the proper
9136 * interrupt in the NCU interrupt table.
9138 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9139 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9145 /* We adopt the LDG assignment ordering used by the N2 NIU
9146 * 'interrupt' properties because that simplifies a lot of
9147 * things. This ordering is:
9150 * MIF (if port zero)
9151 * SYSERR (if port zero)
9158 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9164 if (ldg_rotor == np->num_ldg)
9168 err = niu_ldg_assign_ldn(np, parent,
9169 ldg_num_map[ldg_rotor],
9175 if (ldg_rotor == np->num_ldg)
9178 err = niu_ldg_assign_ldn(np, parent,
9179 ldg_num_map[ldg_rotor],
9185 if (ldg_rotor == np->num_ldg)
9191 for (i = 0; i < port; i++)
9192 first_chan += parent->rxchan_per_port[i];
9193 num_chan = parent->rxchan_per_port[port];
9195 for (i = first_chan; i < (first_chan + num_chan); i++) {
9196 err = niu_ldg_assign_ldn(np, parent,
9197 ldg_num_map[ldg_rotor],
9202 if (ldg_rotor == np->num_ldg)
9207 for (i = 0; i < port; i++)
9208 first_chan += parent->txchan_per_port[i];
9209 num_chan = parent->txchan_per_port[port];
9210 for (i = first_chan; i < (first_chan + num_chan); i++) {
9211 err = niu_ldg_assign_ldn(np, parent,
9212 ldg_num_map[ldg_rotor],
9217 if (ldg_rotor == np->num_ldg)
9224 static void __devexit niu_ldg_free(struct niu *np)
9226 if (np->flags & NIU_FLAGS_MSIX)
9227 pci_disable_msix(np->pdev);
9230 static int __devinit niu_get_of_props(struct niu *np)
9232 #ifdef CONFIG_SPARC64
9233 struct net_device *dev = np->dev;
9234 struct device_node *dp;
9235 const char *phy_type;
9240 if (np->parent->plat_type == PLAT_TYPE_NIU)
9241 dp = np->op->dev.of_node;
9243 dp = pci_device_to_OF_node(np->pdev);
9245 phy_type = of_get_property(dp, "phy-type", &prop_len);
9247 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9252 if (!strcmp(phy_type, "none"))
9255 strcpy(np->vpd.phy_type, phy_type);
9257 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9258 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9259 dp->full_name, np->vpd.phy_type);
9263 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9265 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9269 if (prop_len != dev->addr_len) {
9270 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9271 dp->full_name, prop_len);
9273 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9274 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
9275 netdev_err(dev, "%s: OF MAC address is invalid\n",
9277 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
9281 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
9283 model = of_get_property(dp, "model", &prop_len);
9286 strcpy(np->vpd.model, model);
9288 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9289 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9290 NIU_FLAGS_HOTPLUG_PHY);
9299 static int __devinit niu_get_invariants(struct niu *np)
9301 int err, have_props;
9304 err = niu_get_of_props(np);
9310 err = niu_init_mac_ipp_pcs_base(np);
9315 err = niu_get_and_validate_port(np);
9320 if (np->parent->plat_type == PLAT_TYPE_NIU)
9323 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9324 offset = niu_pci_vpd_offset(np);
9325 netif_printk(np, probe, KERN_DEBUG, np->dev,
9326 "%s() VPD offset [%08x]\n", __func__, offset);
9328 niu_pci_vpd_fetch(np, offset);
9329 nw64(ESPC_PIO_EN, 0);
9331 if (np->flags & NIU_FLAGS_VPD_VALID) {
9332 niu_pci_vpd_validate(np);
9333 err = niu_get_and_validate_port(np);
9338 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9339 err = niu_get_and_validate_port(np);
9342 err = niu_pci_probe_sprom(np);
9348 err = niu_probe_ports(np);
9354 niu_classifier_swstate_init(np);
9355 niu_link_config_init(np);
9357 err = niu_determine_phy_disposition(np);
9359 err = niu_init_link(np);
9364 static LIST_HEAD(niu_parent_list);
9365 static DEFINE_MUTEX(niu_parent_lock);
9366 static int niu_parent_index;
9368 static ssize_t show_port_phy(struct device *dev,
9369 struct device_attribute *attr, char *buf)
9371 struct platform_device *plat_dev = to_platform_device(dev);
9372 struct niu_parent *p = plat_dev->dev.platform_data;
9373 u32 port_phy = p->port_phy;
9374 char *orig_buf = buf;
9377 if (port_phy == PORT_PHY_UNKNOWN ||
9378 port_phy == PORT_PHY_INVALID)
9381 for (i = 0; i < p->num_ports; i++) {
9382 const char *type_str;
9385 type = phy_decode(port_phy, i);
9386 if (type == PORT_TYPE_10G)
9391 (i == 0) ? "%s" : " %s",
9394 buf += sprintf(buf, "\n");
9395 return buf - orig_buf;
9398 static ssize_t show_plat_type(struct device *dev,
9399 struct device_attribute *attr, char *buf)
9401 struct platform_device *plat_dev = to_platform_device(dev);
9402 struct niu_parent *p = plat_dev->dev.platform_data;
9403 const char *type_str;
9405 switch (p->plat_type) {
9406 case PLAT_TYPE_ATLAS:
9412 case PLAT_TYPE_VF_P0:
9415 case PLAT_TYPE_VF_P1:
9419 type_str = "unknown";
9423 return sprintf(buf, "%s\n", type_str);
9426 static ssize_t __show_chan_per_port(struct device *dev,
9427 struct device_attribute *attr, char *buf,
9430 struct platform_device *plat_dev = to_platform_device(dev);
9431 struct niu_parent *p = plat_dev->dev.platform_data;
9432 char *orig_buf = buf;
9436 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9438 for (i = 0; i < p->num_ports; i++) {
9440 (i == 0) ? "%d" : " %d",
9443 buf += sprintf(buf, "\n");
9445 return buf - orig_buf;
9448 static ssize_t show_rxchan_per_port(struct device *dev,
9449 struct device_attribute *attr, char *buf)
9451 return __show_chan_per_port(dev, attr, buf, 1);
9454 static ssize_t show_txchan_per_port(struct device *dev,
9455 struct device_attribute *attr, char *buf)
9457 return __show_chan_per_port(dev, attr, buf, 1);
9460 static ssize_t show_num_ports(struct device *dev,
9461 struct device_attribute *attr, char *buf)
9463 struct platform_device *plat_dev = to_platform_device(dev);
9464 struct niu_parent *p = plat_dev->dev.platform_data;
9466 return sprintf(buf, "%d\n", p->num_ports);
9469 static struct device_attribute niu_parent_attributes[] = {
9470 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9471 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9472 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9473 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9474 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9478 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9479 union niu_parent_id *id,
9482 struct platform_device *plat_dev;
9483 struct niu_parent *p;
9486 plat_dev = platform_device_register_simple("niu-board", niu_parent_index,
9488 if (IS_ERR(plat_dev))
9491 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9492 int err = device_create_file(&plat_dev->dev,
9493 &niu_parent_attributes[i]);
9495 goto fail_unregister;
9498 p = kzalloc(sizeof(*p), GFP_KERNEL);
9500 goto fail_unregister;
9502 p->index = niu_parent_index++;
9504 plat_dev->dev.platform_data = p;
9505 p->plat_dev = plat_dev;
9507 memcpy(&p->id, id, sizeof(*id));
9508 p->plat_type = ptype;
9509 INIT_LIST_HEAD(&p->list);
9510 atomic_set(&p->refcnt, 0);
9511 list_add(&p->list, &niu_parent_list);
9512 spin_lock_init(&p->lock);
9514 p->rxdma_clock_divider = 7500;
9516 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9517 if (p->plat_type == PLAT_TYPE_NIU)
9518 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9520 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9521 int index = i - CLASS_CODE_USER_PROG1;
9523 p->tcam_key[index] = TCAM_KEY_TSEL;
9524 p->flow_key[index] = (FLOW_KEY_IPSA |
9527 (FLOW_KEY_L4_BYTE12 <<
9528 FLOW_KEY_L4_0_SHIFT) |
9529 (FLOW_KEY_L4_BYTE12 <<
9530 FLOW_KEY_L4_1_SHIFT));
9533 for (i = 0; i < LDN_MAX + 1; i++)
9534 p->ldg_map[i] = LDG_INVALID;
9539 platform_device_unregister(plat_dev);
9543 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9544 union niu_parent_id *id,
9547 struct niu_parent *p, *tmp;
9548 int port = np->port;
9550 mutex_lock(&niu_parent_lock);
9552 list_for_each_entry(tmp, &niu_parent_list, list) {
9553 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9559 p = niu_new_parent(np, id, ptype);
9565 sprintf(port_name, "port%d", port);
9566 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9570 p->ports[port] = np;
9571 atomic_inc(&p->refcnt);
9574 mutex_unlock(&niu_parent_lock);
9579 static void niu_put_parent(struct niu *np)
9581 struct niu_parent *p = np->parent;
9585 BUG_ON(!p || p->ports[port] != np);
9587 netif_printk(np, probe, KERN_DEBUG, np->dev,
9588 "%s() port[%u]\n", __func__, port);
9590 sprintf(port_name, "port%d", port);
9592 mutex_lock(&niu_parent_lock);
9594 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9596 p->ports[port] = NULL;
9599 if (atomic_dec_and_test(&p->refcnt)) {
9601 platform_device_unregister(p->plat_dev);
9604 mutex_unlock(&niu_parent_lock);
9607 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9608 u64 *handle, gfp_t flag)
9613 ret = dma_alloc_coherent(dev, size, &dh, flag);
9619 static void niu_pci_free_coherent(struct device *dev, size_t size,
9620 void *cpu_addr, u64 handle)
9622 dma_free_coherent(dev, size, cpu_addr, handle);
9625 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9626 unsigned long offset, size_t size,
9627 enum dma_data_direction direction)
9629 return dma_map_page(dev, page, offset, size, direction);
9632 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9633 size_t size, enum dma_data_direction direction)
9635 dma_unmap_page(dev, dma_address, size, direction);
9638 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9640 enum dma_data_direction direction)
9642 return dma_map_single(dev, cpu_addr, size, direction);
9645 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9647 enum dma_data_direction direction)
9649 dma_unmap_single(dev, dma_address, size, direction);
9652 static const struct niu_ops niu_pci_ops = {
9653 .alloc_coherent = niu_pci_alloc_coherent,
9654 .free_coherent = niu_pci_free_coherent,
9655 .map_page = niu_pci_map_page,
9656 .unmap_page = niu_pci_unmap_page,
9657 .map_single = niu_pci_map_single,
9658 .unmap_single = niu_pci_unmap_single,
9661 static void __devinit niu_driver_version(void)
9663 static int niu_version_printed;
9665 if (niu_version_printed++ == 0)
9666 pr_info("%s", version);
9669 static struct net_device * __devinit niu_alloc_and_init(
9670 struct device *gen_dev, struct pci_dev *pdev,
9671 struct platform_device *op, const struct niu_ops *ops,
9674 struct net_device *dev;
9677 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9681 SET_NETDEV_DEV(dev, gen_dev);
9683 np = netdev_priv(dev);
9687 np->device = gen_dev;
9690 np->msg_enable = niu_debug;
9692 spin_lock_init(&np->lock);
9693 INIT_WORK(&np->reset_task, niu_reset_task);
9700 static const struct net_device_ops niu_netdev_ops = {
9701 .ndo_open = niu_open,
9702 .ndo_stop = niu_close,
9703 .ndo_start_xmit = niu_start_xmit,
9704 .ndo_get_stats64 = niu_get_stats,
9705 .ndo_set_rx_mode = niu_set_rx_mode,
9706 .ndo_validate_addr = eth_validate_addr,
9707 .ndo_set_mac_address = niu_set_mac_addr,
9708 .ndo_do_ioctl = niu_ioctl,
9709 .ndo_tx_timeout = niu_tx_timeout,
9710 .ndo_change_mtu = niu_change_mtu,
9713 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9715 dev->netdev_ops = &niu_netdev_ops;
9716 dev->ethtool_ops = &niu_ethtool_ops;
9717 dev->watchdog_timeo = NIU_TX_TIMEOUT;
9720 static void __devinit niu_device_announce(struct niu *np)
9722 struct net_device *dev = np->dev;
9724 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9726 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9727 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9729 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9730 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9731 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9732 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9733 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9736 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9738 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9739 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9740 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9741 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9743 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9744 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9749 static void __devinit niu_set_basic_features(struct net_device *dev)
9751 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH;
9752 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
9755 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9756 const struct pci_device_id *ent)
9758 union niu_parent_id parent_id;
9759 struct net_device *dev;
9765 niu_driver_version();
9767 err = pci_enable_device(pdev);
9769 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9773 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9774 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9775 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
9777 goto err_out_disable_pdev;
9780 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9782 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9783 goto err_out_disable_pdev;
9786 pos = pci_pcie_cap(pdev);
9788 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
9789 goto err_out_free_res;
9792 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9793 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9796 goto err_out_free_res;
9798 np = netdev_priv(dev);
9800 memset(&parent_id, 0, sizeof(parent_id));
9801 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9802 parent_id.pci.bus = pdev->bus->number;
9803 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9805 np->parent = niu_get_parent(np, &parent_id,
9809 goto err_out_free_dev;
9812 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9813 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9814 val16 |= (PCI_EXP_DEVCTL_CERE |
9815 PCI_EXP_DEVCTL_NFERE |
9816 PCI_EXP_DEVCTL_FERE |
9817 PCI_EXP_DEVCTL_URRE |
9818 PCI_EXP_DEVCTL_RELAX_EN);
9819 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9821 dma_mask = DMA_BIT_MASK(44);
9822 err = pci_set_dma_mask(pdev, dma_mask);
9824 dev->features |= NETIF_F_HIGHDMA;
9825 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9827 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9828 goto err_out_release_parent;
9832 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9834 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
9835 goto err_out_release_parent;
9839 niu_set_basic_features(dev);
9841 dev->priv_flags |= IFF_UNICAST_FLT;
9843 np->regs = pci_ioremap_bar(pdev, 0);
9845 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9847 goto err_out_release_parent;
9850 pci_set_master(pdev);
9851 pci_save_state(pdev);
9853 dev->irq = pdev->irq;
9855 niu_assign_netdev_ops(dev);
9857 err = niu_get_invariants(np);
9860 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
9861 goto err_out_iounmap;
9864 err = register_netdev(dev);
9866 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
9867 goto err_out_iounmap;
9870 pci_set_drvdata(pdev, dev);
9872 niu_device_announce(np);
9882 err_out_release_parent:
9889 pci_release_regions(pdev);
9891 err_out_disable_pdev:
9892 pci_disable_device(pdev);
9893 pci_set_drvdata(pdev, NULL);
9898 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9900 struct net_device *dev = pci_get_drvdata(pdev);
9903 struct niu *np = netdev_priv(dev);
9905 unregister_netdev(dev);
9916 pci_release_regions(pdev);
9917 pci_disable_device(pdev);
9918 pci_set_drvdata(pdev, NULL);
9922 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9924 struct net_device *dev = pci_get_drvdata(pdev);
9925 struct niu *np = netdev_priv(dev);
9926 unsigned long flags;
9928 if (!netif_running(dev))
9931 flush_work_sync(&np->reset_task);
9934 del_timer_sync(&np->timer);
9936 spin_lock_irqsave(&np->lock, flags);
9937 niu_enable_interrupts(np, 0);
9938 spin_unlock_irqrestore(&np->lock, flags);
9940 netif_device_detach(dev);
9942 spin_lock_irqsave(&np->lock, flags);
9944 spin_unlock_irqrestore(&np->lock, flags);
9946 pci_save_state(pdev);
9951 static int niu_resume(struct pci_dev *pdev)
9953 struct net_device *dev = pci_get_drvdata(pdev);
9954 struct niu *np = netdev_priv(dev);
9955 unsigned long flags;
9958 if (!netif_running(dev))
9961 pci_restore_state(pdev);
9963 netif_device_attach(dev);
9965 spin_lock_irqsave(&np->lock, flags);
9967 err = niu_init_hw(np);
9969 np->timer.expires = jiffies + HZ;
9970 add_timer(&np->timer);
9971 niu_netif_start(np);
9974 spin_unlock_irqrestore(&np->lock, flags);
9979 static struct pci_driver niu_pci_driver = {
9980 .name = DRV_MODULE_NAME,
9981 .id_table = niu_pci_tbl,
9982 .probe = niu_pci_init_one,
9983 .remove = __devexit_p(niu_pci_remove_one),
9984 .suspend = niu_suspend,
9985 .resume = niu_resume,
9988 #ifdef CONFIG_SPARC64
9989 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9990 u64 *dma_addr, gfp_t flag)
9992 unsigned long order = get_order(size);
9993 unsigned long page = __get_free_pages(flag, order);
9997 memset((char *)page, 0, PAGE_SIZE << order);
9998 *dma_addr = __pa(page);
10000 return (void *) page;
10003 static void niu_phys_free_coherent(struct device *dev, size_t size,
10004 void *cpu_addr, u64 handle)
10006 unsigned long order = get_order(size);
10008 free_pages((unsigned long) cpu_addr, order);
10011 static u64 niu_phys_map_page(struct device *dev, struct page *page,
10012 unsigned long offset, size_t size,
10013 enum dma_data_direction direction)
10015 return page_to_phys(page) + offset;
10018 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10019 size_t size, enum dma_data_direction direction)
10021 /* Nothing to do. */
10024 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10026 enum dma_data_direction direction)
10028 return __pa(cpu_addr);
10031 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10033 enum dma_data_direction direction)
10035 /* Nothing to do. */
10038 static const struct niu_ops niu_phys_ops = {
10039 .alloc_coherent = niu_phys_alloc_coherent,
10040 .free_coherent = niu_phys_free_coherent,
10041 .map_page = niu_phys_map_page,
10042 .unmap_page = niu_phys_unmap_page,
10043 .map_single = niu_phys_map_single,
10044 .unmap_single = niu_phys_unmap_single,
10047 static int __devinit niu_of_probe(struct platform_device *op)
10049 union niu_parent_id parent_id;
10050 struct net_device *dev;
10055 niu_driver_version();
10057 reg = of_get_property(op->dev.of_node, "reg", NULL);
10059 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
10060 op->dev.of_node->full_name);
10064 dev = niu_alloc_and_init(&op->dev, NULL, op,
10065 &niu_phys_ops, reg[0] & 0x1);
10070 np = netdev_priv(dev);
10072 memset(&parent_id, 0, sizeof(parent_id));
10073 parent_id.of = of_get_parent(op->dev.of_node);
10075 np->parent = niu_get_parent(np, &parent_id,
10079 goto err_out_free_dev;
10082 niu_set_basic_features(dev);
10084 np->regs = of_ioremap(&op->resource[1], 0,
10085 resource_size(&op->resource[1]),
10088 dev_err(&op->dev, "Cannot map device registers, aborting\n");
10090 goto err_out_release_parent;
10093 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10094 resource_size(&op->resource[2]),
10096 if (!np->vir_regs_1) {
10097 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
10099 goto err_out_iounmap;
10102 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10103 resource_size(&op->resource[3]),
10105 if (!np->vir_regs_2) {
10106 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
10108 goto err_out_iounmap;
10111 niu_assign_netdev_ops(dev);
10113 err = niu_get_invariants(np);
10115 if (err != -ENODEV)
10116 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
10117 goto err_out_iounmap;
10120 err = register_netdev(dev);
10122 dev_err(&op->dev, "Cannot register net device, aborting\n");
10123 goto err_out_iounmap;
10126 dev_set_drvdata(&op->dev, dev);
10128 niu_device_announce(np);
10133 if (np->vir_regs_1) {
10134 of_iounmap(&op->resource[2], np->vir_regs_1,
10135 resource_size(&op->resource[2]));
10136 np->vir_regs_1 = NULL;
10139 if (np->vir_regs_2) {
10140 of_iounmap(&op->resource[3], np->vir_regs_2,
10141 resource_size(&op->resource[3]));
10142 np->vir_regs_2 = NULL;
10146 of_iounmap(&op->resource[1], np->regs,
10147 resource_size(&op->resource[1]));
10151 err_out_release_parent:
10152 niu_put_parent(np);
10161 static int __devexit niu_of_remove(struct platform_device *op)
10163 struct net_device *dev = dev_get_drvdata(&op->dev);
10166 struct niu *np = netdev_priv(dev);
10168 unregister_netdev(dev);
10170 if (np->vir_regs_1) {
10171 of_iounmap(&op->resource[2], np->vir_regs_1,
10172 resource_size(&op->resource[2]));
10173 np->vir_regs_1 = NULL;
10176 if (np->vir_regs_2) {
10177 of_iounmap(&op->resource[3], np->vir_regs_2,
10178 resource_size(&op->resource[3]));
10179 np->vir_regs_2 = NULL;
10183 of_iounmap(&op->resource[1], np->regs,
10184 resource_size(&op->resource[1]));
10190 niu_put_parent(np);
10193 dev_set_drvdata(&op->dev, NULL);
10198 static const struct of_device_id niu_match[] = {
10201 .compatible = "SUNW,niusl",
10205 MODULE_DEVICE_TABLE(of, niu_match);
10207 static struct platform_driver niu_of_driver = {
10210 .owner = THIS_MODULE,
10211 .of_match_table = niu_match,
10213 .probe = niu_of_probe,
10214 .remove = __devexit_p(niu_of_remove),
10217 #endif /* CONFIG_SPARC64 */
10219 static int __init niu_init(void)
10223 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10225 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10227 #ifdef CONFIG_SPARC64
10228 err = platform_driver_register(&niu_of_driver);
10232 err = pci_register_driver(&niu_pci_driver);
10233 #ifdef CONFIG_SPARC64
10235 platform_driver_unregister(&niu_of_driver);
10242 static void __exit niu_exit(void)
10244 pci_unregister_driver(&niu_pci_driver);
10245 #ifdef CONFIG_SPARC64
10246 platform_driver_unregister(&niu_of_driver);
10250 module_init(niu_init);
10251 module_exit(niu_exit);