1 /*******************************************************************************
2 STMMAC Ethernet Driver -- MDIO bus implementation
3 Provides Bus interface for MII registers
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Carl Shaw <carl.shaw@st.com>
24 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 *******************************************************************************/
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/slab.h>
31 #include <linux/of_gpio.h>
37 #define MII_BUSY 0x00000001
38 #define MII_WRITE 0x00000002
40 static int stmmac_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_addr)
43 unsigned long finish = jiffies + 3 * HZ;
47 if (readl(ioaddr + mii_addr) & MII_BUSY)
51 } while (!time_after_eq(curr, finish));
58 * @bus: points to the mii_bus structure
59 * @phyaddr: MII addr reg bits 15-11
60 * @phyreg: MII addr reg bits 10-6
61 * Description: it reads data from the MII register from within the phy device.
62 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
63 * accessing the PHY registers.
64 * Fortunately, it seems this has no drawback for the 7109 MAC.
66 static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
68 struct net_device *ndev = bus->priv;
69 struct stmmac_priv *priv = netdev_priv(ndev);
70 unsigned int mii_address = priv->hw->mii.addr;
71 unsigned int mii_data = priv->hw->mii.data;
74 u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
75 ((phyreg << 6) & (0x000007C0)));
76 regValue |= MII_BUSY | ((priv->clk_csr & 0xF) << 2);
78 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
81 writel(regValue, priv->ioaddr + mii_address);
83 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
86 /* Read the data from the MII data register */
87 data = (int)readl(priv->ioaddr + mii_data);
94 * @bus: points to the mii_bus structure
95 * @phyaddr: MII addr reg bits 15-11
96 * @phyreg: MII addr reg bits 10-6
98 * Description: it writes the data into the MII register from within the device.
100 static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
103 struct net_device *ndev = bus->priv;
104 struct stmmac_priv *priv = netdev_priv(ndev);
105 unsigned int mii_address = priv->hw->mii.addr;
106 unsigned int mii_data = priv->hw->mii.data;
109 (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
112 value |= MII_BUSY | ((priv->clk_csr & 0xF) << 2);
114 /* Wait until any existing MII operation is complete */
115 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
118 /* Set the MII address register to write */
119 writel(phydata, priv->ioaddr + mii_data);
120 writel(value, priv->ioaddr + mii_address);
122 /* Wait until any existing MII operation is complete */
123 return stmmac_mdio_busy_wait(priv->ioaddr, mii_address);
128 * @bus: points to the mii_bus structure
129 * Description: reset the MII bus
131 static int stmmac_mdio_reset(struct mii_bus *bus)
133 #if defined(CONFIG_STMMAC_PLATFORM)
134 struct net_device *ndev = bus->priv;
135 struct stmmac_priv *priv = netdev_priv(ndev);
136 unsigned int mii_address = priv->hw->mii.addr;
137 struct stmmac_mdio_bus_data *data = priv->plat->mdio_bus_data;
140 if (priv->device->of_node) {
141 int reset_gpio, active_low;
143 if (data->reset_gpio < 0) {
144 struct device_node *np = priv->device->of_node;
148 data->reset_gpio = of_get_named_gpio(np,
149 "snps,reset-gpio", 0);
150 if (data->reset_gpio < 0)
153 data->active_low = of_property_read_bool(np,
154 "snps,reset-active-low");
155 of_property_read_u32_array(np,
156 "snps,reset-delays-us", data->delays, 3);
159 reset_gpio = data->reset_gpio;
160 active_low = data->active_low;
162 if (!gpio_request(reset_gpio, "mdio-reset")) {
163 gpio_direction_output(reset_gpio, active_low ? 1 : 0);
164 udelay(data->delays[0]);
165 gpio_set_value(reset_gpio, active_low ? 0 : 1);
166 udelay(data->delays[1]);
167 gpio_set_value(reset_gpio, active_low ? 1 : 0);
168 udelay(data->delays[2]);
169 gpio_free(reset_gpio);
174 if (data->phy_reset) {
175 pr_debug("stmmac_mdio_reset: calling phy_reset\n");
176 data->phy_reset(priv->plat->bsp_priv);
179 /* This is a workaround for problems with the STE101P PHY.
180 * It doesn't complete its reset until at least one clock cycle
181 * on MDC, so perform a dummy mdio read.
183 writel(0, priv->ioaddr + mii_address);
189 * stmmac_mdio_register
190 * @ndev: net device structure
191 * Description: it registers the MII bus
193 int stmmac_mdio_register(struct net_device *ndev)
196 struct mii_bus *new_bus;
198 struct stmmac_priv *priv = netdev_priv(ndev);
199 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
205 new_bus = mdiobus_alloc();
209 if (mdio_bus_data->irqs)
210 irqlist = mdio_bus_data->irqs;
212 irqlist = priv->mii_irq;
215 if (priv->device->of_node)
216 mdio_bus_data->reset_gpio = -1;
219 new_bus->name = "stmmac";
220 new_bus->read = &stmmac_mdio_read;
221 new_bus->write = &stmmac_mdio_write;
222 new_bus->reset = &stmmac_mdio_reset;
223 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
224 new_bus->name, priv->plat->bus_id);
225 new_bus->priv = ndev;
226 new_bus->irq = irqlist;
227 new_bus->phy_mask = mdio_bus_data->phy_mask;
228 new_bus->parent = priv->device;
229 err = mdiobus_register(new_bus);
231 pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
232 goto bus_register_fail;
236 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
237 struct phy_device *phydev = new_bus->phy_map[addr];
244 * If an IRQ was provided to be assigned after
245 * the bus probe, do it here.
247 if ((mdio_bus_data->irqs == NULL) &&
248 (mdio_bus_data->probed_phy_irq > 0)) {
249 irqlist[addr] = mdio_bus_data->probed_phy_irq;
250 phydev->irq = mdio_bus_data->probed_phy_irq;
254 * If we're going to bind the MAC to this PHY bus,
255 * and no PHY number was provided to the MAC,
256 * use the one probed here.
258 if (priv->plat->phy_addr == -1)
259 priv->plat->phy_addr = addr;
261 act = (priv->plat->phy_addr == addr);
262 switch (phydev->irq) {
266 case PHY_IGNORE_INTERRUPT:
270 sprintf(irq_num, "%d", phydev->irq);
274 pr_info("%s: PHY ID %08x at %d IRQ %s (%s)%s\n",
275 ndev->name, phydev->phy_id, addr,
276 irq_str, dev_name(&phydev->dev),
277 act ? " active" : "");
283 pr_warning("%s: No PHY found\n", ndev->name);
284 mdiobus_unregister(new_bus);
285 mdiobus_free(new_bus);
294 mdiobus_free(new_bus);
299 * stmmac_mdio_unregister
300 * @ndev: net device structure
301 * Description: it unregisters the MII bus
303 int stmmac_mdio_unregister(struct net_device *ndev)
305 struct stmmac_priv *priv = netdev_priv(ndev);
310 mdiobus_unregister(priv->mii);
311 priv->mii->priv = NULL;
312 mdiobus_free(priv->mii);