Pileus Git - ~andy/linux/blob - drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/pinctrl/consumer.h>
  47 #ifdef CONFIG_STMMAC_DEBUG_FS
  48 #include <linux/debugfs.h>
  49 #include <linux/seq_file.h>
  50 #endif /* CONFIG_STMMAC_DEBUG_FS */
  51 #include <linux/net_tstamp.h>
  52 #include "stmmac_ptp.h"
  53 #include "stmmac.h"
  54
  55 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  56 #define JUMBO_LEN       9000
  57
  58 /* Module parameters */
  59 #define TX_TIMEO        5000
  60 static int watchdog = TX_TIMEO;
  61 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  62 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  63
  64 static int debug = -1;
  65 module_param(debug, int, S_IRUGO | S_IWUSR);
  66 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  67
  68 static int phyaddr = -1;
  69 module_param(phyaddr, int, S_IRUGO);
  70 MODULE_PARM_DESC(phyaddr, "Physical device address");
  71
  72 #define DMA_TX_SIZE 256
  73 static int dma_txsize = DMA_TX_SIZE;
  74 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  75 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
  76
  77 #define DMA_RX_SIZE 256
  78 static int dma_rxsize = DMA_RX_SIZE;
  79 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
  80 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
  81
  82 static int flow_ctrl = FLOW_OFF;
  83 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
  84 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  85
  86 static int pause = PAUSE_TIME;
  87 module_param(pause, int, S_IRUGO | S_IWUSR);
  88 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  89
  90 #define TC_DEFAULT 64
  91 static int tc = TC_DEFAULT;
  92 module_param(tc, int, S_IRUGO | S_IWUSR);
  93 MODULE_PARM_DESC(tc, "DMA threshold control value");
  94
  95 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
  96 static int buf_sz = DMA_BUFFER_SIZE;
  97 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
  98 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  99
 100 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 101                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 102                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 103
 104 #define STMMAC_DEFAULT_LPI_TIMER        1000
 105 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 106 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 107 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 109
 110 /* By default the driver will use the ring mode to manage tx and rx descriptors
 111  * but passing this value so user can force to use the chain instead of the ring
 112  */
 113 static unsigned int chain_mode;
 114 module_param(chain_mode, int, S_IRUGO);
 115 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 116
 117 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 118
 119 #ifdef CONFIG_STMMAC_DEBUG_FS
 120 static int stmmac_init_fs(struct net_device *dev);
 121 static void stmmac_exit_fs(void);
 122 #endif
 123
 124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 125
 126 /**
 127  * stmmac_verify_args - verify the driver parameters.
 128  * Description: it verifies if some wrong parameter is passed to the driver.
 129  * Note that wrong parameters are replaced with the default values.
 130  */
 131 static void stmmac_verify_args(void)
 132 {
 133         if (unlikely(watchdog < 0))
 134                 watchdog = TX_TIMEO;
 135         if (unlikely(dma_rxsize < 0))
 136                 dma_rxsize = DMA_RX_SIZE;
 137         if (unlikely(dma_txsize < 0))
 138                 dma_txsize = DMA_TX_SIZE;
 139         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 140                 buf_sz = DMA_BUFFER_SIZE;
 141         if (unlikely(flow_ctrl > 1))
 142                 flow_ctrl = FLOW_AUTO;
 143         else if (likely(flow_ctrl < 0))
 144                 flow_ctrl = FLOW_OFF;
 145         if (unlikely((pause < 0) || (pause > 0xffff)))
 146                 pause = PAUSE_TIME;
 147         if (eee_timer < 0)
 148                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 149 }
 150
 151 /**
 152  * stmmac_clk_csr_set - dynamically set the MDC clock
 153  * @priv: driver private structure
 154  * Description: this is to dynamically set the MDC clock according to the csr
 155  * clock input.
 156  * Note:
 157  *      If a specific clk_csr value is passed from the platform
 158  *      this means that the CSR Clock Range selection cannot be
 159  *      changed at run-time and it is fixed (as reported in the driver
 160  *      documentation). Viceversa the driver will try to set the MDC
 161  *      clock dynamically according to the actual clock input.
 162  */
 163 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 164 {
 165         u32 clk_rate;
 166
 167         clk_rate = clk_get_rate(priv->stmmac_clk);
 168
 169         /* Platform provided default clk_csr would be assumed valid
 170          * for all other cases except for the below mentioned ones.
 171          * For values higher than the IEEE 802.3 specified frequency
 172          * we can not estimate the proper divider as it is not known
 173          * the frequency of clk_csr_i. So we do not change the default
 174          * divider.
 175          */
 176         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 177                 if (clk_rate < CSR_F_35M)
 178                         priv->clk_csr = STMMAC_CSR_20_35M;
 179                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 180                         priv->clk_csr = STMMAC_CSR_35_60M;
 181                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 182                         priv->clk_csr = STMMAC_CSR_60_100M;
 183                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 184                         priv->clk_csr = STMMAC_CSR_100_150M;
 185                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 186                         priv->clk_csr = STMMAC_CSR_150_250M;
 187                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 188                         priv->clk_csr = STMMAC_CSR_250_300M;
 189         }
 190 }
 191
 192 static void print_pkt(unsigned char *buf, int len)
 193 {
 194         int j;
 195         pr_debug("len = %d byte, buf addr: 0x%p", len, buf);
 196         for (j = 0; j < len; j++) {
 197                 if ((j % 16) == 0)
 198                         pr_debug("\n %03x:", j);
 199                 pr_debug(" %02x", buf[j]);
 200         }
 201         pr_debug("\n");
 202 }
 203
 204 /* minimum number of free TX descriptors required to wake up TX process */
 205 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 206
 207 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 208 {
 209         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 210 }
 211
 212 /**
 213  * stmmac_hw_fix_mac_speed: callback for speed selection
 214  * @priv: driver private structure
 215  * Description: on some platforms (e.g. ST), some HW system configuraton
 216  * registers have to be set according to the link speed negotiated.
 217  */
 218 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 219 {
 220         struct phy_device *phydev = priv->phydev;
 221
 222         if (likely(priv->plat->fix_mac_speed))
 223                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 224 }
 225
 226 /**
 227  * stmmac_enable_eee_mode: Check and enter in LPI mode
 228  * @priv: driver private structure
 229  * Description: this function is to verify and enter in LPI mode for EEE.
 230  */
 231 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 232 {
 233         /* Check and enter in LPI mode */
 234         if ((priv->dirty_tx == priv->cur_tx) &&
 235             (priv->tx_path_in_lpi_mode == false))
 236                 priv->hw->mac->set_eee_mode(priv->ioaddr);
 237 }
 238
 239 /**
 240  * stmmac_disable_eee_mode: disable/exit from EEE
 241  * @priv: driver private structure
 242  * Description: this function is to exit and disable EEE in case of
 243  * LPI state is true. This is called by the xmit.
 244  */
 245 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 246 {
 247         priv->hw->mac->reset_eee_mode(priv->ioaddr);
 248         del_timer_sync(&priv->eee_ctrl_timer);
 249         priv->tx_path_in_lpi_mode = false;
 250 }
 251
 252 /**
 253  * stmmac_eee_ctrl_timer: EEE TX SW timer.
 254  * @arg : data hook
 255  * Description:
 256  *  if there is no data transfer and if we are not in LPI state,
 257  *  then MAC Transmitter can be moved to LPI state.
 258  */
 259 static void stmmac_eee_ctrl_timer(unsigned long arg)
 260 {
 261         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 262
 263         stmmac_enable_eee_mode(priv);
 264         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 265 }
 266
 267 /**
 268  * stmmac_eee_init: init EEE
 269  * @priv: driver private structure
 270  * Description:
 271  *  If the EEE support has been enabled while configuring the driver,
 272  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 273  *  phy can also manage EEE, so enable the LPI state and start the timer
 274  *  to verify if the tx path can enter in LPI state.
 275  */
 276 bool stmmac_eee_init(struct stmmac_priv *priv)
 277 {
 278         bool ret = false;
 279
 280         /* Using PCS we cannot dial with the phy registers at this stage
 281          * so we do not support extra feature like EEE.
 282          */
 283         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
 284             (priv->pcs == STMMAC_PCS_RTBI))
 285                 goto out;
 286
 287         /* MAC core supports the EEE feature. */
 288         if (priv->dma_cap.eee) {
 289                 /* Check if the PHY supports EEE */
 290                 if (phy_init_eee(priv->phydev, 1))
 291                         goto out;
 292
 293                 if (!priv->eee_active) {
 294                         priv->eee_active = 1;
 295                         init_timer(&priv->eee_ctrl_timer);
 296                         priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
 297                         priv->eee_ctrl_timer.data = (unsigned long)priv;
 298                         priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
 299                         add_timer(&priv->eee_ctrl_timer);
 300
 301                         priv->hw->mac->set_eee_timer(priv->ioaddr,
 302                                                      STMMAC_DEFAULT_LIT_LS,
 303                                                      priv->tx_lpi_timer);
 304                 } else
 305                         /* Set HW EEE according to the speed */
 306                         priv->hw->mac->set_eee_pls(priv->ioaddr,
 307                                                    priv->phydev->link);
 308
 309                 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
 310
 311                 ret = true;
 312         }
 313 out:
 314         return ret;
 315 }
 316
 317 /* stmmac_get_tx_hwtstamp: get HW TX timestamps
 318  * @priv: driver private structure
 319  * @entry : descriptor index to be used.
 320  * @skb : the socket buffer
 321  * Description :
 322  * This function will read timestamp from the descriptor & pass it to stack.
 323  * and also perform some sanity checks.
 324  */
 325 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 326                                    unsigned int entry, struct sk_buff *skb)
 327 {
 328         struct skb_shared_hwtstamps shhwtstamp;
 329         u64 ns;
 330         void *desc = NULL;
 331
 332         if (!priv->hwts_tx_en)
 333                 return;
 334
 335         /* exit if skb doesn't support hw tstamp */
 336         if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 337                 return;
 338
 339         if (priv->adv_ts)
 340                 desc = (priv->dma_etx + entry);
 341         else
 342                 desc = (priv->dma_tx + entry);
 343
 344         /* check tx tstamp status */
 345         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 346                 return;
 347
 348         /* get the valid tstamp */
 349         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 350
 351         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 352         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 353         /* pass tstamp to stack */
 354         skb_tstamp_tx(skb, &shhwtstamp);
 355
 356         return;
 357 }
 358
 359 /* stmmac_get_rx_hwtstamp: get HW RX timestamps
 360  * @priv: driver private structure
 361  * @entry : descriptor index to be used.
 362  * @skb : the socket buffer
 363  * Description :
 364  * This function will read received packet's timestamp from the descriptor
 365  * and pass it to stack. It also perform some sanity checks.
 366  */
 367 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 368                                    unsigned int entry, struct sk_buff *skb)
 369 {
 370         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 371         u64 ns;
 372         void *desc = NULL;
 373
 374         if (!priv->hwts_rx_en)
 375                 return;
 376
 377         if (priv->adv_ts)
 378                 desc = (priv->dma_erx + entry);
 379         else
 380                 desc = (priv->dma_rx + entry);
 381
 382         /* exit if rx tstamp is not valid */
 383         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 384                 return;
 385
 386         /* get valid tstamp */
 387         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 388         shhwtstamp = skb_hwtstamps(skb);
 389         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 390         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 391 }
 392
 393 /**
 394  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 395  *  @dev: device pointer.
 396  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 397  *  a proprietary structure used to pass information to the driver.
 398  *  Description:
 399  *  This function configures the MAC to enable/disable both outgoing(TX)
 400  *  and incoming(RX) packets time stamping based on user input.
 401  *  Return Value:
 402  *  0 on success and an appropriate -ve integer on failure.
 403  */
 404 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 405 {
 406         struct stmmac_priv *priv = netdev_priv(dev);
 407         struct hwtstamp_config config;
 408         struct timespec now;
 409         u64 temp = 0;
 410         u32 ptp_v2 = 0;
 411         u32 tstamp_all = 0;
 412         u32 ptp_over_ipv4_udp = 0;
 413         u32 ptp_over_ipv6_udp = 0;
 414         u32 ptp_over_ethernet = 0;
 415         u32 snap_type_sel = 0;
 416         u32 ts_master_en = 0;
 417         u32 ts_event_en = 0;
 418         u32 value = 0;
 419
 420         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 421                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 422                 priv->hwts_tx_en = 0;
 423                 priv->hwts_rx_en = 0;
 424
 425                 return -EOPNOTSUPP;
 426         }
 427
 428         if (copy_from_user(&config, ifr->ifr_data,
 429                            sizeof(struct hwtstamp_config)))
 430                 return -EFAULT;
 431
 432         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 433                  __func__, config.flags, config.tx_type, config.rx_filter);
 434
 435         /* reserved for future extensions */
 436         if (config.flags)
 437                 return -EINVAL;
 438
 439         if (config.tx_type != HWTSTAMP_TX_OFF &&
 440             config.tx_type != HWTSTAMP_TX_ON)
 441                 return -ERANGE;
 442
 443         if (priv->adv_ts) {
 444                 switch (config.rx_filter) {
 445                 case HWTSTAMP_FILTER_NONE:
 446                         /* time stamp no incoming packet at all */
 447                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 448                         break;
 449
 450                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 451                         /* PTP v1, UDP, any kind of event packet */
 452                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 453                         /* take time stamp for all event messages */
 454                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 455
 456                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 457                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 458                         break;
 459
 460                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 461                         /* PTP v1, UDP, Sync packet */
 462                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 463                         /* take time stamp for SYNC messages only */
 464                         ts_event_en = PTP_TCR_TSEVNTENA;
 465
 466                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 467                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 468                         break;
 469
 470                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 471                         /* PTP v1, UDP, Delay_req packet */
 472                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 473                         /* take time stamp for Delay_Req messages only */
 474                         ts_master_en = PTP_TCR_TSMSTRENA;
 475                         ts_event_en = PTP_TCR_TSEVNTENA;
 476
 477                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 478                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 479                         break;
 480
 481                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 482                         /* PTP v2, UDP, any kind of event packet */
 483                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 484                         ptp_v2 = PTP_TCR_TSVER2ENA;
 485                         /* take time stamp for all event messages */
 486                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 487
 488                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 489                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 490                         break;
 491
 492                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 493                         /* PTP v2, UDP, Sync packet */
 494                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 495                         ptp_v2 = PTP_TCR_TSVER2ENA;
 496                         /* take time stamp for SYNC messages only */
 497                         ts_event_en = PTP_TCR_TSEVNTENA;
 498
 499                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 500                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 501                         break;
 502
 503                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 504                         /* PTP v2, UDP, Delay_req packet */
 505                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 506                         ptp_v2 = PTP_TCR_TSVER2ENA;
 507                         /* take time stamp for Delay_Req messages only */
 508                         ts_master_en = PTP_TCR_TSMSTRENA;
 509                         ts_event_en = PTP_TCR_TSEVNTENA;
 510
 511                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 512                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 513                         break;
 514
 515                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 516                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 517                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 518                         ptp_v2 = PTP_TCR_TSVER2ENA;
 519                         /* take time stamp for all event messages */
 520                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 521
 522                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 523                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 524                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 525                         break;
 526
 527                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 528                         /* PTP v2/802.AS1, any layer, Sync packet */
 529                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 530                         ptp_v2 = PTP_TCR_TSVER2ENA;
 531                         /* take time stamp for SYNC messages only */
 532                         ts_event_en = PTP_TCR_TSEVNTENA;
 533
 534                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 535                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 536                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 537                         break;
 538
 539                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 540                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 541                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 542                         ptp_v2 = PTP_TCR_TSVER2ENA;
 543                         /* take time stamp for Delay_Req messages only */
 544                         ts_master_en = PTP_TCR_TSMSTRENA;
 545                         ts_event_en = PTP_TCR_TSEVNTENA;
 546
 547                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 548                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 549                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 550                         break;
 551
 552                 case HWTSTAMP_FILTER_ALL:
 553                         /* time stamp any incoming packet */
 554                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 555                         tstamp_all = PTP_TCR_TSENALL;
 556                         break;
 557
 558                 default:
 559                         return -ERANGE;
 560                 }
 561         } else {
 562                 switch (config.rx_filter) {
 563                 case HWTSTAMP_FILTER_NONE:
 564                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 565                         break;
 566                 default:
 567                         /* PTP v1, UDP, any kind of event packet */
 568                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 569                         break;
 570                 }
 571         }
 572         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 573         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 574
 575         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 576                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 577         else {
 578                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 579                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 580                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 581                          ts_master_en | snap_type_sel);
 582
 583                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 584
 585                 /* program Sub Second Increment reg */
 586                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
 587
 588                 /* calculate default added value:
 589                  * formula is :
 590                  * addend = (2^32)/freq_div_ratio;
 591                  * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
 592                  * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
 593                  * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
 594                  *       achive 20ns accuracy.
 595                  *
 596                  * 2^x * y == (y << x), hence
 597                  * 2^32 * 50000000 ==> (50000000 << 32)
 598                  */
 599                 temp = (u64) (50000000ULL << 32);
 600                 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK);
 601                 priv->hw->ptp->config_addend(priv->ioaddr,
 602                                              priv->default_addend);
 603
 604                 /* initialize system time */
 605                 getnstimeofday(&now);
 606                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
 607                                             now.tv_nsec);
 608         }
 609
 610         return copy_to_user(ifr->ifr_data, &config,
 611                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 612 }
 613
 614 /**
 615  * stmmac_init_ptp: init PTP
 616  * @priv: driver private structure
 617  * Description: this is to verify if the HW supports the PTPv1 or v2.
 618  * This is done by looking at the HW cap. register.
 619  * Also it registers the ptp driver.
 620  */
 621 static int stmmac_init_ptp(struct stmmac_priv *priv)
 622 {
 623         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 624                 return -EOPNOTSUPP;
 625
 626         priv->adv_ts = 0;
 627         if (priv->dma_cap.atime_stamp && priv->extend_desc)
 628                 priv->adv_ts = 1;
 629
 630         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
 631                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 632
 633         if (netif_msg_hw(priv) && priv->adv_ts)
 634                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
 635
 636         priv->hw->ptp = &stmmac_ptp;
 637         priv->hwts_tx_en = 0;
 638         priv->hwts_rx_en = 0;
 639
 640         return stmmac_ptp_register(priv);
 641 }
 642
 643 static void stmmac_release_ptp(struct stmmac_priv *priv)
 644 {
 645         stmmac_ptp_unregister(priv);
 646 }
 647
 648 /**
 649  * stmmac_adjust_link
 650  * @dev: net device structure
 651  * Description: it adjusts the link parameters.
 652  */
 653 static void stmmac_adjust_link(struct net_device *dev)
 654 {
 655         struct stmmac_priv *priv = netdev_priv(dev);
 656         struct phy_device *phydev = priv->phydev;
 657         unsigned long flags;
 658         int new_state = 0;
 659         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 660
 661         if (phydev == NULL)
 662                 return;
 663
 664         spin_lock_irqsave(&priv->lock, flags);
 665
 666         if (phydev->link) {
 667                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 668
 669                 /* Now we make sure that we can be in full duplex mode.
 670                  * If not, we operate in half-duplex mode. */
 671                 if (phydev->duplex != priv->oldduplex) {
 672                         new_state = 1;
 673                         if (!(phydev->duplex))
 674                                 ctrl &= ~priv->hw->link.duplex;
 675                         else
 676                                 ctrl |= priv->hw->link.duplex;
 677                         priv->oldduplex = phydev->duplex;
 678                 }
 679                 /* Flow Control operation */
 680                 if (phydev->pause)
 681                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
 682                                                  fc, pause_time);
 683
 684                 if (phydev->speed != priv->speed) {
 685                         new_state = 1;
 686                         switch (phydev->speed) {
 687                         case 1000:
 688                                 if (likely(priv->plat->has_gmac))
 689                                         ctrl &= ~priv->hw->link.port;
 690                                 stmmac_hw_fix_mac_speed(priv);
 691                                 break;
 692                         case 100:
 693                         case 10:
 694                                 if (priv->plat->has_gmac) {
 695                                         ctrl |= priv->hw->link.port;
 696                                         if (phydev->speed == SPEED_100) {
 697                                                 ctrl |= priv->hw->link.speed;
 698                                         } else {
 699                                                 ctrl &= ~(priv->hw->link.speed);
 700                                         }
 701                                 } else {
 702                                         ctrl &= ~priv->hw->link.port;
 703                                 }
 704                                 stmmac_hw_fix_mac_speed(priv);
 705                                 break;
 706                         default:
 707                                 if (netif_msg_link(priv))
 708                                         pr_warn("%s: Speed (%d) not 10/100\n",
 709                                                 dev->name, phydev->speed);
 710                                 break;
 711                         }
 712
 713                         priv->speed = phydev->speed;
 714                 }
 715
 716                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 717
 718                 if (!priv->oldlink) {
 719                         new_state = 1;
 720                         priv->oldlink = 1;
 721                 }
 722         } else if (priv->oldlink) {
 723                 new_state = 1;
 724                 priv->oldlink = 0;
 725                 priv->speed = 0;
 726                 priv->oldduplex = -1;
 727         }
 728
 729         if (new_state && netif_msg_link(priv))
 730                 phy_print_status(phydev);
 731
 732         /* At this stage, it could be needed to setup the EEE or adjust some
 733          * MAC related HW registers.
 734          */
 735         priv->eee_enabled = stmmac_eee_init(priv);
 736
 737         spin_unlock_irqrestore(&priv->lock, flags);
 738 }
 739
 740 /**
 741  * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
 742  * @priv: driver private structure
 743  * Description: this is to verify if the HW supports the PCS.
 744  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 745  * configured for the TBI, RTBI, or SGMII PHY interface.
 746  */
 747 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 748 {
 749         int interface = priv->plat->interface;
 750
 751         if (priv->dma_cap.pcs) {
 752                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 753                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 754                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 755                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 756                         pr_debug("STMMAC: PCS RGMII support enable\n");
 757                         priv->pcs = STMMAC_PCS_RGMII;
 758                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 759                         pr_debug("STMMAC: PCS SGMII support enable\n");
 760                         priv->pcs = STMMAC_PCS_SGMII;
 761                 }
 762         }
 763 }
 764
 765 /**
 766  * stmmac_init_phy - PHY initialization
 767  * @dev: net device structure
 768  * Description: it initializes the driver's PHY state, and attaches the PHY
 769  * to the mac driver.
 770  *  Return value:
 771  *  0 on success
 772  */
 773 static int stmmac_init_phy(struct net_device *dev)
 774 {
 775         struct stmmac_priv *priv = netdev_priv(dev);
 776         struct phy_device *phydev;
 777         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 778         char bus_id[MII_BUS_ID_SIZE];
 779         int interface = priv->plat->interface;
 780         int max_speed = priv->plat->max_speed;
 781         priv->oldlink = 0;
 782         priv->speed = 0;
 783         priv->oldduplex = -1;
 784
 785         if (priv->plat->phy_bus_name)
 786                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 787                          priv->plat->phy_bus_name, priv->plat->bus_id);
 788         else
 789                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 790                          priv->plat->bus_id);
 791
 792         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 793                  priv->plat->phy_addr);
 794         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 795
 796         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 797
 798         if (IS_ERR(phydev)) {
 799                 pr_err("%s: Could not attach to PHY\n", dev->name);
 800                 return PTR_ERR(phydev);
 801         }
 802
 803         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 804         if ((interface == PHY_INTERFACE_MODE_MII) ||
 805             (interface == PHY_INTERFACE_MODE_RMII) ||
 806                 (max_speed < 1000 &&  max_speed > 0))
 807                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 808                                          SUPPORTED_1000baseT_Full);
 809
 810         /*
 811          * Broken HW is sometimes missing the pull-up resistor on the
 812          * MDIO line, which results in reads to non-existent devices returning
 813          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 814          * device as well.
 815          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 816          */
 817         if (phydev->phy_id == 0) {
 818                 phy_disconnect(phydev);
 819                 return -ENODEV;
 820         }
 821         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 822                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 823
 824         priv->phydev = phydev;
 825
 826         return 0;
 827 }
 828
 829 /**
 830  * stmmac_display_ring: display ring
 831  * @head: pointer to the head of the ring passed.
 832  * @size: size of the ring.
 833  * @extend_desc: to verify if extended descriptors are used.
 834  * Description: display the control/status and buffer descriptors.
 835  */
 836 static void stmmac_display_ring(void *head, int size, int extend_desc)
 837 {
 838         int i;
 839         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
 840         struct dma_desc *p = (struct dma_desc *)head;
 841
 842         for (i = 0; i < size; i++) {
 843                 u64 x;
 844                 if (extend_desc) {
 845                         x = *(u64 *) ep;
 846                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 847                                 i, (unsigned int)virt_to_phys(ep),
 848                                 (unsigned int)x, (unsigned int)(x >> 32),
 849                                 ep->basic.des2, ep->basic.des3);
 850                         ep++;
 851                 } else {
 852                         x = *(u64 *) p;
 853                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 854                                 i, (unsigned int)virt_to_phys(p),
 855                                 (unsigned int)x, (unsigned int)(x >> 32),
 856                                 p->des2, p->des3);
 857                         p++;
 858                 }
 859                 pr_info("\n");
 860         }
 861 }
 862
 863 static void stmmac_display_rings(struct stmmac_priv *priv)
 864 {
 865         unsigned int txsize = priv->dma_tx_size;
 866         unsigned int rxsize = priv->dma_rx_size;
 867
 868         if (priv->extend_desc) {
 869                 pr_info("Extended RX descriptor ring:\n");
 870                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
 871                 pr_info("Extended TX descriptor ring:\n");
 872                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
 873         } else {
 874                 pr_info("RX descriptor ring:\n");
 875                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
 876                 pr_info("TX descriptor ring:\n");
 877                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
 878         }
 879 }
 880
 881 static int stmmac_set_bfsize(int mtu, int bufsize)
 882 {
 883         int ret = bufsize;
 884
 885         if (mtu >= BUF_SIZE_4KiB)
 886                 ret = BUF_SIZE_8KiB;
 887         else if (mtu >= BUF_SIZE_2KiB)
 888                 ret = BUF_SIZE_4KiB;
 889         else if (mtu >= DMA_BUFFER_SIZE)
 890                 ret = BUF_SIZE_2KiB;
 891         else
 892                 ret = DMA_BUFFER_SIZE;
 893
 894         return ret;
 895 }
 896
 897 /**
 898  * stmmac_clear_descriptors: clear descriptors
 899  * @priv: driver private structure
 900  * Description: this function is called to clear the tx and rx descriptors
 901  * in case of both basic and extended descriptors are used.
 902  */
 903 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 904 {
 905         int i;
 906         unsigned int txsize = priv->dma_tx_size;
 907         unsigned int rxsize = priv->dma_rx_size;
 908
 909         /* Clear the Rx/Tx descriptors */
 910         for (i = 0; i < rxsize; i++)
 911                 if (priv->extend_desc)
 912                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 913                                                      priv->use_riwt, priv->mode,
 914                                                      (i == rxsize - 1));
 915                 else
 916                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 917                                                      priv->use_riwt, priv->mode,
 918                                                      (i == rxsize - 1));
 919         for (i = 0; i < txsize; i++)
 920                 if (priv->extend_desc)
 921                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 922                                                      priv->mode,
 923                                                      (i == txsize - 1));
 924                 else
 925                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 926                                                      priv->mode,
 927                                                      (i == txsize - 1));
 928 }
 929
 930 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 931                                   int i)
 932 {
 933         struct sk_buff *skb;
 934
 935         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
 936                                  GFP_KERNEL);
 937         if (!skb) {
 938                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 939                 return -ENOMEM;
 940         }
 941         skb_reserve(skb, NET_IP_ALIGN);
 942         priv->rx_skbuff[i] = skb;
 943         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 944                                                 priv->dma_buf_sz,
 945                                                 DMA_FROM_DEVICE);
 946         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
 947                 pr_err("%s: DMA mapping error\n", __func__);
 948                 dev_kfree_skb_any(skb);
 949                 return -EINVAL;
 950         }
 951
 952         p->des2 = priv->rx_skbuff_dma[i];
 953
 954         if ((priv->mode == STMMAC_RING_MODE) &&
 955             (priv->dma_buf_sz == BUF_SIZE_16KiB))
 956                 priv->hw->ring->init_desc3(p);
 957
 958         return 0;
 959 }
 960
 961 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
 962 {
 963         if (priv->rx_skbuff[i]) {
 964                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
 965                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
 966                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 967         }
 968         priv->rx_skbuff[i] = NULL;
 969 }
 970
 971 /**
 972  * init_dma_desc_rings - init the RX/TX descriptor rings
 973  * @dev: net device structure
 974  * Description:  this function initializes the DMA RX/TX descriptors
 975  * and allocates the socket buffers. It suppors the chained and ring
 976  * modes.
 977  */
 978 static int init_dma_desc_rings(struct net_device *dev)
 979 {
 980         int i;
 981         struct stmmac_priv *priv = netdev_priv(dev);
 982         unsigned int txsize = priv->dma_tx_size;
 983         unsigned int rxsize = priv->dma_rx_size;
 984         unsigned int bfsize = 0;
 985         int ret = -ENOMEM;
 986
 987         /* Set the max buffer size according to the DESC mode
 988          * and the MTU. Note that RING mode allows 16KiB bsize.
 989          */
 990         if (priv->mode == STMMAC_RING_MODE)
 991                 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
 992
 993         if (bfsize < BUF_SIZE_16KiB)
 994                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
 995
 996         if (netif_msg_probe(priv))
 997                 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
 998                          txsize, rxsize, bfsize);
 999
1000         if (netif_msg_probe(priv)) {
1001                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1002                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1003
1004                 /* RX INITIALIZATION */
1005                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1006         }
1007         for (i = 0; i < rxsize; i++) {
1008                 struct dma_desc *p;
1009                 if (priv->extend_desc)
1010                         p = &((priv->dma_erx + i)->basic);
1011                 else
1012                         p = priv->dma_rx + i;
1013
1014                 ret = stmmac_init_rx_buffers(priv, p, i);
1015                 if (ret)
1016                         goto err_init_rx_buffers;
1017
1018                 if (netif_msg_probe(priv))
1019                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1020                                  priv->rx_skbuff[i]->data,
1021                                  (unsigned int)priv->rx_skbuff_dma[i]);
1022         }
1023         priv->cur_rx = 0;
1024         priv->dirty_rx = (unsigned int)(i - rxsize);
1025         priv->dma_buf_sz = bfsize;
1026         buf_sz = bfsize;
1027
1028         /* Setup the chained descriptor addresses */
1029         if (priv->mode == STMMAC_CHAIN_MODE) {
1030                 if (priv->extend_desc) {
1031                         priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
1032                                               rxsize, 1);
1033                         priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
1034                                               txsize, 1);
1035                 } else {
1036                         priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
1037                                               rxsize, 0);
1038                         priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
1039                                               txsize, 0);
1040                 }
1041         }
1042
1043         /* TX INITIALIZATION */
1044         for (i = 0; i < txsize; i++) {
1045                 struct dma_desc *p;
1046                 if (priv->extend_desc)
1047                         p = &((priv->dma_etx + i)->basic);
1048                 else
1049                         p = priv->dma_tx + i;
1050                 p->des2 = 0;
1051                 priv->tx_skbuff_dma[i] = 0;
1052                 priv->tx_skbuff[i] = NULL;
1053         }
1054
1055         priv->dirty_tx = 0;
1056         priv->cur_tx = 0;
1057
1058         stmmac_clear_descriptors(priv);
1059
1060         if (netif_msg_hw(priv))
1061                 stmmac_display_rings(priv);
1062
1063         return 0;
1064 err_init_rx_buffers:
1065         while (--i >= 0)
1066                 stmmac_free_rx_buffers(priv, i);
1067         return ret;
1068 }
1069
1070 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1071 {
1072         int i;
1073
1074         for (i = 0; i < priv->dma_rx_size; i++)
1075                 stmmac_free_rx_buffers(priv, i);
1076 }
1077
1078 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1079 {
1080         int i;
1081
1082         for (i = 0; i < priv->dma_tx_size; i++) {
1083                 if (priv->tx_skbuff[i] != NULL) {
1084                         struct dma_desc *p;
1085                         if (priv->extend_desc)
1086                                 p = &((priv->dma_etx + i)->basic);
1087                         else
1088                                 p = priv->dma_tx + i;
1089
1090                         if (priv->tx_skbuff_dma[i])
1091                                 dma_unmap_single(priv->device,
1092                                                  priv->tx_skbuff_dma[i],
1093                                                  priv->hw->desc->get_tx_len(p),
1094                                                  DMA_TO_DEVICE);
1095                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1096                         priv->tx_skbuff[i] = NULL;
1097                         priv->tx_skbuff_dma[i] = 0;
1098                 }
1099         }
1100 }
1101
1102 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1103 {
1104         unsigned int txsize = priv->dma_tx_size;
1105         unsigned int rxsize = priv->dma_rx_size;
1106         int ret = -ENOMEM;
1107
1108         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1109                                             GFP_KERNEL);
1110         if (!priv->rx_skbuff_dma)
1111                 return -ENOMEM;
1112
1113         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1114                                         GFP_KERNEL);
1115         if (!priv->rx_skbuff)
1116                 goto err_rx_skbuff;
1117
1118         priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
1119                                             GFP_KERNEL);
1120         if (!priv->tx_skbuff_dma)
1121                 goto err_tx_skbuff_dma;
1122
1123         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1124                                         GFP_KERNEL);
1125         if (!priv->tx_skbuff)
1126                 goto err_tx_skbuff;
1127
1128         if (priv->extend_desc) {
1129                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1130                                                    sizeof(struct
1131                                                           dma_extended_desc),
1132                                                    &priv->dma_rx_phy,
1133                                                    GFP_KERNEL);
1134                 if (!priv->dma_erx)
1135                         goto err_dma;
1136
1137                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1138                                                    sizeof(struct
1139                                                           dma_extended_desc),
1140                                                    &priv->dma_tx_phy,
1141                                                    GFP_KERNEL);
1142                 if (!priv->dma_etx) {
1143                         dma_free_coherent(priv->device, priv->dma_rx_size *
1144                                         sizeof(struct dma_extended_desc),
1145                                         priv->dma_erx, priv->dma_rx_phy);
1146                         goto err_dma;
1147                 }
1148         } else {
1149                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1150                                                   sizeof(struct dma_desc),
1151                                                   &priv->dma_rx_phy,
1152                                                   GFP_KERNEL);
1153                 if (!priv->dma_rx)
1154                         goto err_dma;
1155
1156                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1157                                                   sizeof(struct dma_desc),
1158                                                   &priv->dma_tx_phy,
1159                                                   GFP_KERNEL);
1160                 if (!priv->dma_tx) {
1161                         dma_free_coherent(priv->device, priv->dma_rx_size *
1162                                         sizeof(struct dma_desc),
1163                                         priv->dma_rx, priv->dma_rx_phy);
1164                         goto err_dma;
1165                 }
1166         }
1167
1168         return 0;
1169
1170 err_dma:
1171         kfree(priv->tx_skbuff);
1172 err_tx_skbuff:
1173         kfree(priv->tx_skbuff_dma);
1174 err_tx_skbuff_dma:
1175         kfree(priv->rx_skbuff);
1176 err_rx_skbuff:
1177         kfree(priv->rx_skbuff_dma);
1178         return ret;
1179 }
1180
1181 static void free_dma_desc_resources(struct stmmac_priv *priv)
1182 {
1183         /* Release the DMA TX/RX socket buffers */
1184         dma_free_rx_skbufs(priv);
1185         dma_free_tx_skbufs(priv);
1186
1187         /* Free DMA regions of consistent memory previously allocated */
1188         if (!priv->extend_desc) {
1189                 dma_free_coherent(priv->device,
1190                                   priv->dma_tx_size * sizeof(struct dma_desc),
1191                                   priv->dma_tx, priv->dma_tx_phy);
1192                 dma_free_coherent(priv->device,
1193                                   priv->dma_rx_size * sizeof(struct dma_desc),
1194                                   priv->dma_rx, priv->dma_rx_phy);
1195         } else {
1196                 dma_free_coherent(priv->device, priv->dma_tx_size *
1197                                   sizeof(struct dma_extended_desc),
1198                                   priv->dma_etx, priv->dma_tx_phy);
1199                 dma_free_coherent(priv->device, priv->dma_rx_size *
1200                                   sizeof(struct dma_extended_desc),
1201                                   priv->dma_erx, priv->dma_rx_phy);
1202         }
1203         kfree(priv->rx_skbuff_dma);
1204         kfree(priv->rx_skbuff);
1205         kfree(priv->tx_skbuff_dma);
1206         kfree(priv->tx_skbuff);
1207 }
1208
1209 /**
1210  *  stmmac_dma_operation_mode - HW DMA operation mode
1211  *  @priv: driver private structure
1212  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
1213  *  or Store-And-Forward capability.
1214  */
1215 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1216 {
1217         if (priv->plat->force_thresh_dma_mode)
1218                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc);
1219         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1220                 /*
1221                  * In case of GMAC, SF mode can be enabled
1222                  * to perform the TX COE in HW. This depends on:
1223                  * 1) TX COE if actually supported
1224                  * 2) There is no bugged Jumbo frame support
1225                  *    that needs to not insert csum in the TDES.
1226                  */
1227                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
1228                 tc = SF_DMA_MODE;
1229         } else
1230                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1231 }
1232
1233 /**
1234  * stmmac_tx_clean:
1235  * @priv: driver private structure
1236  * Description: it reclaims resources after transmission completes.
1237  */
1238 static void stmmac_tx_clean(struct stmmac_priv *priv)
1239 {
1240         unsigned int txsize = priv->dma_tx_size;
1241
1242         spin_lock(&priv->tx_lock);
1243
1244         priv->xstats.tx_clean++;
1245
1246         while (priv->dirty_tx != priv->cur_tx) {
1247                 int last;
1248                 unsigned int entry = priv->dirty_tx % txsize;
1249                 struct sk_buff *skb = priv->tx_skbuff[entry];
1250                 struct dma_desc *p;
1251
1252                 if (priv->extend_desc)
1253                         p = (struct dma_desc *)(priv->dma_etx + entry);
1254                 else
1255                         p = priv->dma_tx + entry;
1256
1257                 /* Check if the descriptor is owned by the DMA. */
1258                 if (priv->hw->desc->get_tx_owner(p))
1259                         break;
1260
1261                 /* Verify tx error by looking at the last segment. */
1262                 last = priv->hw->desc->get_tx_ls(p);
1263                 if (likely(last)) {
1264                         int tx_error =
1265                             priv->hw->desc->tx_status(&priv->dev->stats,
1266                                                       &priv->xstats, p,
1267                                                       priv->ioaddr);
1268                         if (likely(tx_error == 0)) {
1269                                 priv->dev->stats.tx_packets++;
1270                                 priv->xstats.tx_pkt_n++;
1271                         } else
1272                                 priv->dev->stats.tx_errors++;
1273
1274                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1275                 }
1276                 if (netif_msg_tx_done(priv))
1277                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1278                                  priv->cur_tx, priv->dirty_tx);
1279
1280                 if (likely(priv->tx_skbuff_dma[entry])) {
1281                         dma_unmap_single(priv->device,
1282                                          priv->tx_skbuff_dma[entry],
1283                                          priv->hw->desc->get_tx_len(p),
1284                                          DMA_TO_DEVICE);
1285                         priv->tx_skbuff_dma[entry] = 0;
1286                 }
1287                 priv->hw->ring->clean_desc3(priv, p);
1288
1289                 if (likely(skb != NULL)) {
1290                         dev_kfree_skb(skb);
1291                         priv->tx_skbuff[entry] = NULL;
1292                 }
1293
1294                 priv->hw->desc->release_tx_desc(p, priv->mode);
1295
1296                 priv->dirty_tx++;
1297         }
1298         if (unlikely(netif_queue_stopped(priv->dev) &&
1299                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1300                 netif_tx_lock(priv->dev);
1301                 if (netif_queue_stopped(priv->dev) &&
1302                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1303                         if (netif_msg_tx_done(priv))
1304                                 pr_debug("%s: restart transmit\n", __func__);
1305                         netif_wake_queue(priv->dev);
1306                 }
1307                 netif_tx_unlock(priv->dev);
1308         }
1309
1310         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1311                 stmmac_enable_eee_mode(priv);
1312                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1313         }
1314         spin_unlock(&priv->tx_lock);
1315 }
1316
1317 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1318 {
1319         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1320 }
1321
1322 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1323 {
1324         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1325 }
1326
1327 /**
1328  * stmmac_tx_err: irq tx error mng function
1329  * @priv: driver private structure
1330  * Description: it cleans the descriptors and restarts the transmission
1331  * in case of errors.
1332  */
1333 static void stmmac_tx_err(struct stmmac_priv *priv)
1334 {
1335         int i;
1336         int txsize = priv->dma_tx_size;
1337         netif_stop_queue(priv->dev);
1338
1339         priv->hw->dma->stop_tx(priv->ioaddr);
1340         dma_free_tx_skbufs(priv);
1341         for (i = 0; i < txsize; i++)
1342                 if (priv->extend_desc)
1343                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1344                                                      priv->mode,
1345                                                      (i == txsize - 1));
1346                 else
1347                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1348                                                      priv->mode,
1349                                                      (i == txsize - 1));
1350         priv->dirty_tx = 0;
1351         priv->cur_tx = 0;
1352         priv->hw->dma->start_tx(priv->ioaddr);
1353
1354         priv->dev->stats.tx_errors++;
1355         netif_wake_queue(priv->dev);
1356 }
1357
1358 /**
1359  * stmmac_dma_interrupt: DMA ISR
1360  * @priv: driver private structure
1361  * Description: this is the DMA ISR. It is called by the main ISR.
1362  * It calls the dwmac dma routine to understand which type of interrupt
1363  * happened. In case of there is a Normal interrupt and either TX or RX
1364  * interrupt happened so the NAPI is scheduled.
1365  */
1366 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1367 {
1368         int status;
1369
1370         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1371         if (likely((status & handle_rx)) || (status & handle_tx)) {
1372                 if (likely(napi_schedule_prep(&priv->napi))) {
1373                         stmmac_disable_dma_irq(priv);
1374                         __napi_schedule(&priv->napi);
1375                 }
1376         }
1377         if (unlikely(status & tx_hard_error_bump_tc)) {
1378                 /* Try to bump up the dma threshold on this failure */
1379                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1380                         tc += 64;
1381                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1382                         priv->xstats.threshold = tc;
1383                 }
1384         } else if (unlikely(status == tx_hard_error))
1385                 stmmac_tx_err(priv);
1386 }
1387
1388 /**
1389  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1390  * @priv: driver private structure
1391  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1392  */
1393 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1394 {
1395         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1396             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1397
1398         dwmac_mmc_intr_all_mask(priv->ioaddr);
1399
1400         if (priv->dma_cap.rmon) {
1401                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1402                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1403         } else
1404                 pr_info(" No MAC Management Counters available\n");
1405 }
1406
1407 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1408 {
1409         u32 hwid = priv->hw->synopsys_uid;
1410
1411         /* Check Synopsys Id (not available on old chips) */
1412         if (likely(hwid)) {
1413                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1414                 u32 synid = (hwid & 0x000000ff);
1415
1416                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1417                         uid, synid);
1418
1419                 return synid;
1420         }
1421         return 0;
1422 }
1423
1424 /**
1425  * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1426  * @priv: driver private structure
1427  * Description: select the Enhanced/Alternate or Normal descriptors.
1428  * In case of Enhanced/Alternate, it looks at the extended descriptors are
1429  * supported by the HW cap. register.
1430  */
1431 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1432 {
1433         if (priv->plat->enh_desc) {
1434                 pr_info(" Enhanced/Alternate descriptors\n");
1435
1436                 /* GMAC older than 3.50 has no extended descriptors */
1437                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1438                         pr_info("\tEnabled extended descriptors\n");
1439                         priv->extend_desc = 1;
1440                 } else
1441                         pr_warn("Extended descriptors not supported\n");
1442
1443                 priv->hw->desc = &enh_desc_ops;
1444         } else {
1445                 pr_info(" Normal descriptors\n");
1446                 priv->hw->desc = &ndesc_ops;
1447         }
1448 }
1449
1450 /**
1451  * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1452  * @priv: driver private structure
1453  * Description:
1454  *  new GMAC chip generations have a new register to indicate the
1455  *  presence of the optional feature/functions.
1456  *  This can be also used to override the value passed through the
1457  *  platform and necessary for old MAC10/100 and GMAC chips.
1458  */
1459 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1460 {
1461         u32 hw_cap = 0;
1462
1463         if (priv->hw->dma->get_hw_feature) {
1464                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1465
1466                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1467                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1468                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1469                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1470                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1471                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1472                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1473                 priv->dma_cap.pmt_remote_wake_up =
1474                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1475                 priv->dma_cap.pmt_magic_frame =
1476                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1477                 /* MMC */
1478                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1479                 /* IEEE 1588-2002 */
1480                 priv->dma_cap.time_stamp =
1481                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1482                 /* IEEE 1588-2008 */
1483                 priv->dma_cap.atime_stamp =
1484                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1485                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1486                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1487                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1488                 /* TX and RX csum */
1489                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1490                 priv->dma_cap.rx_coe_type1 =
1491                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1492                 priv->dma_cap.rx_coe_type2 =
1493                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1494                 priv->dma_cap.rxfifo_over_2048 =
1495                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1496                 /* TX and RX number of channels */
1497                 priv->dma_cap.number_rx_channel =
1498                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1499                 priv->dma_cap.number_tx_channel =
1500                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1501                 /* Alternate (enhanced) DESC mode */
1502                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1503         }
1504
1505         return hw_cap;
1506 }
1507
1508 /**
1509  * stmmac_check_ether_addr: check if the MAC addr is valid
1510  * @priv: driver private structure
1511  * Description:
1512  * it is to verify if the MAC address is valid, in case of failures it
1513  * generates a random MAC address
1514  */
1515 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1516 {
1517         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1518                 priv->hw->mac->get_umac_addr((void __iomem *)
1519                                              priv->dev->base_addr,
1520                                              priv->dev->dev_addr, 0);
1521                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1522                         eth_hw_addr_random(priv->dev);
1523         }
1524         pr_warn("%s: device MAC address %pM\n", priv->dev->name,
1525                 priv->dev->dev_addr);
1526 }
1527
1528 /**
1529  * stmmac_init_dma_engine: DMA init.
1530  * @priv: driver private structure
1531  * Description:
1532  * It inits the DMA invoking the specific MAC/GMAC callback.
1533  * Some DMA parameters can be passed from the platform;
1534  * in case of these are not passed a default is kept for the MAC or GMAC.
1535  */
1536 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1537 {
1538         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1539         int mixed_burst = 0;
1540         int atds = 0;
1541
1542         if (priv->plat->dma_cfg) {
1543                 pbl = priv->plat->dma_cfg->pbl;
1544                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1545                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1546                 burst_len = priv->plat->dma_cfg->burst_len;
1547         }
1548
1549         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1550                 atds = 1;
1551
1552         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1553                                    burst_len, priv->dma_tx_phy,
1554                                    priv->dma_rx_phy, atds);
1555 }
1556
1557 /**
1558  * stmmac_tx_timer: mitigation sw timer for tx.
1559  * @data: data pointer
1560  * Description:
1561  * This is the timer handler to directly invoke the stmmac_tx_clean.
1562  */
1563 static void stmmac_tx_timer(unsigned long data)
1564 {
1565         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1566
1567         stmmac_tx_clean(priv);
1568 }
1569
1570 /**
1571  * stmmac_init_tx_coalesce: init tx mitigation options.
1572  * @priv: driver private structure
1573  * Description:
1574  * This inits the transmit coalesce parameters: i.e. timer rate,
1575  * timer handler and default threshold used for enabling the
1576  * interrupt on completion bit.
1577  */
1578 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1579 {
1580         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1581         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1582         init_timer(&priv->txtimer);
1583         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1584         priv->txtimer.data = (unsigned long)priv;
1585         priv->txtimer.function = stmmac_tx_timer;
1586         add_timer(&priv->txtimer);
1587 }
1588
1589 /**
1590  * stmmac_hw_setup: setup mac in a usable state.
1591  *  @dev : pointer to the device structure.
1592  *  Description:
1593  *  This function sets up the ip in a usable state.
1594  *  Return value:
1595  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1596  *  file on failure.
1597  */
1598 static int stmmac_hw_setup(struct net_device *dev)
1599 {
1600         struct stmmac_priv *priv = netdev_priv(dev);
1601         int ret;
1602
1603         ret = init_dma_desc_rings(dev);
1604         if (ret < 0) {
1605                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1606                 return ret;
1607         }
1608         /* DMA initialization and SW reset */
1609         ret = stmmac_init_dma_engine(priv);
1610         if (ret < 0) {
1611                 pr_err("%s: DMA engine initialization failed\n", __func__);
1612                 return ret;
1613         }
1614
1615         /* Copy the MAC addr into the HW  */
1616         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1617
1618         /* If required, perform hw setup of the bus. */
1619         if (priv->plat->bus_setup)
1620                 priv->plat->bus_setup(priv->ioaddr);
1621
1622         /* Initialize the MAC Core */
1623         priv->hw->mac->core_init(priv->ioaddr);
1624
1625         /* Enable the MAC Rx/Tx */
1626         stmmac_set_mac(priv->ioaddr, true);
1627
1628         /* Set the HW DMA mode and the COE */
1629         stmmac_dma_operation_mode(priv);
1630
1631         stmmac_mmc_setup(priv);
1632
1633         ret = stmmac_init_ptp(priv);
1634         if (ret)
1635                 pr_warn("%s: failed PTP initialisation\n", __func__);
1636
1637 #ifdef CONFIG_STMMAC_DEBUG_FS
1638         ret = stmmac_init_fs(dev);
1639         if (ret < 0)
1640                 pr_warn("%s: failed debugFS registration\n", __func__);
1641 #endif
1642         /* Start the ball rolling... */
1643         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1644         priv->hw->dma->start_tx(priv->ioaddr);
1645         priv->hw->dma->start_rx(priv->ioaddr);
1646
1647         /* Dump DMA/MAC registers */
1648         if (netif_msg_hw(priv)) {
1649                 priv->hw->mac->dump_regs(priv->ioaddr);
1650                 priv->hw->dma->dump_regs(priv->ioaddr);
1651         }
1652         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1653
1654         priv->eee_enabled = stmmac_eee_init(priv);
1655
1656         stmmac_init_tx_coalesce(priv);
1657
1658         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1659                 priv->rx_riwt = MAX_DMA_RIWT;
1660                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1661         }
1662
1663         if (priv->pcs && priv->hw->mac->ctrl_ane)
1664                 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1665
1666         return 0;
1667 }
1668
1669 /**
1670  *  stmmac_open - open entry point of the driver
1671  *  @dev : pointer to the device structure.
1672  *  Description:
1673  *  This function is the open entry point of the driver.
1674  *  Return value:
1675  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1676  *  file on failure.
1677  */
1678 static int stmmac_open(struct net_device *dev)
1679 {
1680         struct stmmac_priv *priv = netdev_priv(dev);
1681         int ret;
1682
1683         clk_prepare_enable(priv->stmmac_clk);
1684
1685         stmmac_check_ether_addr(priv);
1686
1687         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1688             priv->pcs != STMMAC_PCS_RTBI) {
1689                 ret = stmmac_init_phy(dev);
1690                 if (ret) {
1691                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1692                                __func__, ret);
1693                         goto phy_error;
1694                 }
1695         }
1696
1697         /* Extra statistics */
1698         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1699         priv->xstats.threshold = tc;
1700
1701         /* Create and initialize the TX/RX descriptors chains. */
1702         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1703         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1704         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1705
1706         alloc_dma_desc_resources(priv);
1707         if (ret < 0) {
1708                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1709                 goto dma_desc_error;
1710         }
1711
1712         ret = stmmac_hw_setup(dev);
1713         if (ret < 0) {
1714                 pr_err("%s: Hw setup failed\n", __func__);
1715                 goto init_error;
1716         }
1717
1718         if (priv->phydev)
1719                 phy_start(priv->phydev);
1720
1721         /* Request the IRQ lines */
1722         ret = request_irq(dev->irq, stmmac_interrupt,
1723                           IRQF_SHARED, dev->name, dev);
1724         if (unlikely(ret < 0)) {
1725                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1726                        __func__, dev->irq, ret);
1727                 goto init_error;
1728         }
1729
1730         /* Request the Wake IRQ in case of another line is used for WoL */
1731         if (priv->wol_irq != dev->irq) {
1732                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1733                                   IRQF_SHARED, dev->name, dev);
1734                 if (unlikely(ret < 0)) {
1735                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1736                                __func__, priv->wol_irq, ret);
1737                         goto wolirq_error;
1738                 }
1739         }
1740
1741         /* Request the IRQ lines */
1742         if (priv->lpi_irq != -ENXIO) {
1743                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1744                                   dev->name, dev);
1745                 if (unlikely(ret < 0)) {
1746                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1747                                __func__, priv->lpi_irq, ret);
1748                         goto lpiirq_error;
1749                 }
1750         }
1751
1752         napi_enable(&priv->napi);
1753         netif_start_queue(dev);
1754
1755         return 0;
1756
1757 lpiirq_error:
1758         if (priv->wol_irq != dev->irq)
1759                 free_irq(priv->wol_irq, dev);
1760 wolirq_error:
1761         free_irq(dev->irq, dev);
1762
1763 init_error:
1764         free_dma_desc_resources(priv);
1765 dma_desc_error:
1766         if (priv->phydev)
1767                 phy_disconnect(priv->phydev);
1768 phy_error:
1769         clk_disable_unprepare(priv->stmmac_clk);
1770
1771         return ret;
1772 }
1773
1774 /**
1775  *  stmmac_release - close entry point of the driver
1776  *  @dev : device pointer.
1777  *  Description:
1778  *  This is the stop entry point of the driver.
1779  */
1780 static int stmmac_release(struct net_device *dev)
1781 {
1782         struct stmmac_priv *priv = netdev_priv(dev);
1783
1784         if (priv->eee_enabled)
1785                 del_timer_sync(&priv->eee_ctrl_timer);
1786
1787         /* Stop and disconnect the PHY */
1788         if (priv->phydev) {
1789                 phy_stop(priv->phydev);
1790                 phy_disconnect(priv->phydev);
1791                 priv->phydev = NULL;
1792         }
1793
1794         netif_stop_queue(dev);
1795
1796         napi_disable(&priv->napi);
1797
1798         del_timer_sync(&priv->txtimer);
1799
1800         /* Free the IRQ lines */
1801         free_irq(dev->irq, dev);
1802         if (priv->wol_irq != dev->irq)
1803                 free_irq(priv->wol_irq, dev);
1804         if (priv->lpi_irq != -ENXIO)
1805                 free_irq(priv->lpi_irq, dev);
1806
1807         /* Stop TX/RX DMA and clear the descriptors */
1808         priv->hw->dma->stop_tx(priv->ioaddr);
1809         priv->hw->dma->stop_rx(priv->ioaddr);
1810
1811         /* Release and free the Rx/Tx resources */
1812         free_dma_desc_resources(priv);
1813
1814         /* Disable the MAC Rx/Tx */
1815         stmmac_set_mac(priv->ioaddr, false);
1816
1817         netif_carrier_off(dev);
1818
1819 #ifdef CONFIG_STMMAC_DEBUG_FS
1820         stmmac_exit_fs();
1821 #endif
1822         clk_disable_unprepare(priv->stmmac_clk);
1823
1824         stmmac_release_ptp(priv);
1825
1826         return 0;
1827 }
1828
1829 /**
1830  *  stmmac_xmit: Tx entry point of the driver
1831  *  @skb : the socket buffer
1832  *  @dev : device pointer
1833  *  Description : this is the tx entry point of the driver.
1834  *  It programs the chain or the ring and supports oversized frames
1835  *  and SG feature.
1836  */
1837 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1838 {
1839         struct stmmac_priv *priv = netdev_priv(dev);
1840         unsigned int txsize = priv->dma_tx_size;
1841         unsigned int entry;
1842         int i, csum_insertion = 0, is_jumbo = 0;
1843         int nfrags = skb_shinfo(skb)->nr_frags;
1844         struct dma_desc *desc, *first;
1845         unsigned int nopaged_len = skb_headlen(skb);
1846
1847         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1848                 if (!netif_queue_stopped(dev)) {
1849                         netif_stop_queue(dev);
1850                         /* This is a hard error, log it. */
1851                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1852                 }
1853                 return NETDEV_TX_BUSY;
1854         }
1855
1856         spin_lock(&priv->tx_lock);
1857
1858         if (priv->tx_path_in_lpi_mode)
1859                 stmmac_disable_eee_mode(priv);
1860
1861         entry = priv->cur_tx % txsize;
1862
1863         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1864
1865         if (priv->extend_desc)
1866                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1867         else
1868                 desc = priv->dma_tx + entry;
1869
1870         first = desc;
1871
1872         priv->tx_skbuff[entry] = skb;
1873
1874         /* To program the descriptors according to the size of the frame */
1875         if (priv->mode == STMMAC_RING_MODE) {
1876                 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1877                                                         priv->plat->enh_desc);
1878                 if (unlikely(is_jumbo))
1879                         entry = priv->hw->ring->jumbo_frm(priv, skb,
1880                                                           csum_insertion);
1881         } else {
1882                 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
1883                                                          priv->plat->enh_desc);
1884                 if (unlikely(is_jumbo))
1885                         entry = priv->hw->chain->jumbo_frm(priv, skb,
1886                                                            csum_insertion);
1887         }
1888         if (likely(!is_jumbo)) {
1889                 desc->des2 = dma_map_single(priv->device, skb->data,
1890                                             nopaged_len, DMA_TO_DEVICE);
1891                 priv->tx_skbuff_dma[entry] = desc->des2;
1892                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1893                                                 csum_insertion, priv->mode);
1894         } else
1895                 desc = first;
1896
1897         for (i = 0; i < nfrags; i++) {
1898                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1899                 int len = skb_frag_size(frag);
1900
1901                 entry = (++priv->cur_tx) % txsize;
1902                 if (priv->extend_desc)
1903                         desc = (struct dma_desc *)(priv->dma_etx + entry);
1904                 else
1905                         desc = priv->dma_tx + entry;
1906
1907                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1908                                               DMA_TO_DEVICE);
1909                 priv->tx_skbuff_dma[entry] = desc->des2;
1910                 priv->tx_skbuff[entry] = NULL;
1911                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1912                                                 priv->mode);
1913                 wmb();
1914                 priv->hw->desc->set_tx_owner(desc);
1915                 wmb();
1916         }
1917
1918         /* Finalize the latest segment. */
1919         priv->hw->desc->close_tx_desc(desc);
1920
1921         wmb();
1922         /* According to the coalesce parameter the IC bit for the latest
1923          * segment could be reset and the timer re-started to invoke the
1924          * stmmac_tx function. This approach takes care about the fragments.
1925          */
1926         priv->tx_count_frames += nfrags + 1;
1927         if (priv->tx_coal_frames > priv->tx_count_frames) {
1928                 priv->hw->desc->clear_tx_ic(desc);
1929                 priv->xstats.tx_reset_ic_bit++;
1930                 mod_timer(&priv->txtimer,
1931                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1932         } else
1933                 priv->tx_count_frames = 0;
1934
1935         /* To avoid raise condition */
1936         priv->hw->desc->set_tx_owner(first);
1937         wmb();
1938
1939         priv->cur_tx++;
1940
1941         if (netif_msg_pktdata(priv)) {
1942                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
1943                         __func__, (priv->cur_tx % txsize),
1944                         (priv->dirty_tx % txsize), entry, first, nfrags);
1945
1946                 if (priv->extend_desc)
1947                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1948                 else
1949                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1950
1951                 pr_debug(">>> frame to be transmitted: ");
1952                 print_pkt(skb->data, skb->len);
1953         }
1954         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1955                 if (netif_msg_hw(priv))
1956                         pr_debug("%s: stop transmitted packets\n", __func__);
1957                 netif_stop_queue(dev);
1958         }
1959
1960         dev->stats.tx_bytes += skb->len;
1961
1962         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1963                      priv->hwts_tx_en)) {
1964                 /* declare that device is doing timestamping */
1965                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1966                 priv->hw->desc->enable_tx_timestamp(first);
1967         }
1968
1969         if (!priv->hwts_tx_en)
1970                 skb_tx_timestamp(skb);
1971
1972         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1973
1974         spin_unlock(&priv->tx_lock);
1975
1976         return NETDEV_TX_OK;
1977 }
1978
1979 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
1980 {
1981         struct ethhdr *ehdr;
1982         u16 vlanid;
1983
1984         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
1985             NETIF_F_HW_VLAN_CTAG_RX &&
1986             !__vlan_get_tag(skb, &vlanid)) {
1987                 /* pop the vlan tag */
1988                 ehdr = (struct ethhdr *)skb->data;
1989                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
1990                 skb_pull(skb, VLAN_HLEN);
1991                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
1992         }
1993 }
1994
1995
1996 /**
1997  * stmmac_rx_refill: refill used skb preallocated buffers
1998  * @priv: driver private structure
1999  * Description : this is to reallocate the skb for the reception process
2000  * that is based on zero-copy.
2001  */
2002 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2003 {
2004         unsigned int rxsize = priv->dma_rx_size;
2005         int bfsize = priv->dma_buf_sz;
2006
2007         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2008                 unsigned int entry = priv->dirty_rx % rxsize;
2009                 struct dma_desc *p;
2010
2011                 if (priv->extend_desc)
2012                         p = (struct dma_desc *)(priv->dma_erx + entry);
2013                 else
2014                         p = priv->dma_rx + entry;
2015
2016                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2017                         struct sk_buff *skb;
2018
2019                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2020
2021                         if (unlikely(skb == NULL))
2022                                 break;
2023
2024                         priv->rx_skbuff[entry] = skb;
2025                         priv->rx_skbuff_dma[entry] =
2026                             dma_map_single(priv->device, skb->data, bfsize,
2027                                            DMA_FROM_DEVICE);
2028
2029                         p->des2 = priv->rx_skbuff_dma[entry];
2030
2031                         priv->hw->ring->refill_desc3(priv, p);
2032
2033                         if (netif_msg_rx_status(priv))
2034                                 pr_debug("\trefill entry #%d\n", entry);
2035                 }
2036                 wmb();
2037                 priv->hw->desc->set_rx_owner(p);
2038                 wmb();
2039         }
2040 }
2041
2042 /**
2043  * stmmac_rx_refill: refill used skb preallocated buffers
2044  * @priv: driver private structure
2045  * @limit: napi bugget.
2046  * Description :  this the function called by the napi poll method.
2047  * It gets all the frames inside the ring.
2048  */
2049 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2050 {
2051         unsigned int rxsize = priv->dma_rx_size;
2052         unsigned int entry = priv->cur_rx % rxsize;
2053         unsigned int next_entry;
2054         unsigned int count = 0;
2055         int coe = priv->plat->rx_coe;
2056
2057         if (netif_msg_rx_status(priv)) {
2058                 pr_debug("%s: descriptor ring:\n", __func__);
2059                 if (priv->extend_desc)
2060                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2061                 else
2062                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2063         }
2064         while (count < limit) {
2065                 int status;
2066                 struct dma_desc *p;
2067
2068                 if (priv->extend_desc)
2069                         p = (struct dma_desc *)(priv->dma_erx + entry);
2070                 else
2071                         p = priv->dma_rx + entry;
2072
2073                 if (priv->hw->desc->get_rx_owner(p))
2074                         break;
2075
2076                 count++;
2077
2078                 next_entry = (++priv->cur_rx) % rxsize;
2079                 if (priv->extend_desc)
2080                         prefetch(priv->dma_erx + next_entry);
2081                 else
2082                         prefetch(priv->dma_rx + next_entry);
2083
2084                 /* read the status of the incoming frame */
2085                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2086                                                    &priv->xstats, p);
2087                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2088                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2089                                                            &priv->xstats,
2090                                                            priv->dma_erx +
2091                                                            entry);
2092                 if (unlikely(status == discard_frame)) {
2093                         priv->dev->stats.rx_errors++;
2094                         if (priv->hwts_rx_en && !priv->extend_desc) {
2095                                 /* DESC2 & DESC3 will be overwitten by device
2096                                  * with timestamp value, hence reinitialize
2097                                  * them in stmmac_rx_refill() function so that
2098                                  * device can reuse it.
2099                                  */
2100                                 priv->rx_skbuff[entry] = NULL;
2101                                 dma_unmap_single(priv->device,
2102                                                  priv->rx_skbuff_dma[entry],
2103                                                  priv->dma_buf_sz,
2104                                                  DMA_FROM_DEVICE);
2105                         }
2106                 } else {
2107                         struct sk_buff *skb;
2108                         int frame_len;
2109
2110                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2111
2112                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2113                          * Type frames (LLC/LLC-SNAP)
2114                          */
2115                         if (unlikely(status != llc_snap))
2116                                 frame_len -= ETH_FCS_LEN;
2117
2118                         if (netif_msg_rx_status(priv)) {
2119                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2120                                          p, entry, p->des2);
2121                                 if (frame_len > ETH_FRAME_LEN)
2122                                         pr_debug("\tframe size %d, COE: %d\n",
2123                                                  frame_len, status);
2124                         }
2125                         skb = priv->rx_skbuff[entry];
2126                         if (unlikely(!skb)) {
2127                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2128                                        priv->dev->name);
2129                                 priv->dev->stats.rx_dropped++;
2130                                 break;
2131                         }
2132                         prefetch(skb->data - NET_IP_ALIGN);
2133                         priv->rx_skbuff[entry] = NULL;
2134
2135                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2136
2137                         skb_put(skb, frame_len);
2138                         dma_unmap_single(priv->device,
2139                                          priv->rx_skbuff_dma[entry],
2140                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2141
2142                         if (netif_msg_pktdata(priv)) {
2143                                 pr_debug("frame received (%dbytes)", frame_len);
2144                                 print_pkt(skb->data, frame_len);
2145                         }
2146
2147                         stmmac_rx_vlan(priv->dev, skb);
2148
2149                         skb->protocol = eth_type_trans(skb, priv->dev);
2150
2151                         if (unlikely(!coe))
2152                                 skb_checksum_none_assert(skb);
2153                         else
2154                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2155
2156                         napi_gro_receive(&priv->napi, skb);
2157
2158                         priv->dev->stats.rx_packets++;
2159                         priv->dev->stats.rx_bytes += frame_len;
2160                 }
2161                 entry = next_entry;
2162         }
2163
2164         stmmac_rx_refill(priv);
2165
2166         priv->xstats.rx_pkt_n += count;
2167
2168         return count;
2169 }
2170
2171 /**
2172  *  stmmac_poll - stmmac poll method (NAPI)
2173  *  @napi : pointer to the napi structure.
2174  *  @budget : maximum number of packets that the current CPU can receive from
2175  *            all interfaces.
2176  *  Description :
2177  *  To look at the incoming frames and clear the tx resources.
2178  */
2179 static int stmmac_poll(struct napi_struct *napi, int budget)
2180 {
2181         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2182         int work_done = 0;
2183
2184         priv->xstats.napi_poll++;
2185         stmmac_tx_clean(priv);
2186
2187         work_done = stmmac_rx(priv, budget);
2188         if (work_done < budget) {
2189                 napi_complete(napi);
2190                 stmmac_enable_dma_irq(priv);
2191         }
2192         return work_done;
2193 }
2194
2195 /**
2196  *  stmmac_tx_timeout
2197  *  @dev : Pointer to net device structure
2198  *  Description: this function is called when a packet transmission fails to
2199  *   complete within a reasonable time. The driver will mark the error in the
2200  *   netdev structure and arrange for the device to be reset to a sane state
2201  *   in order to transmit a new packet.
2202  */
2203 static void stmmac_tx_timeout(struct net_device *dev)
2204 {
2205         struct stmmac_priv *priv = netdev_priv(dev);
2206
2207         /* Clear Tx resources and restart transmitting again */
2208         stmmac_tx_err(priv);
2209 }
2210
2211 /* Configuration changes (passed on by ifconfig) */
2212 static int stmmac_config(struct net_device *dev, struct ifmap *map)
2213 {
2214         if (dev->flags & IFF_UP)        /* can't act on a running interface */
2215                 return -EBUSY;
2216
2217         /* Don't allow changing the I/O address */
2218         if (map->base_addr != dev->base_addr) {
2219                 pr_warn("%s: can't change I/O address\n", dev->name);
2220                 return -EOPNOTSUPP;
2221         }
2222
2223         /* Don't allow changing the IRQ */
2224         if (map->irq != dev->irq) {
2225                 pr_warn("%s: not change IRQ number %d\n", dev->name, dev->irq);
2226                 return -EOPNOTSUPP;
2227         }
2228
2229         return 0;
2230 }
2231
2232 /**
2233  *  stmmac_set_rx_mode - entry point for multicast addressing
2234  *  @dev : pointer to the device structure
2235  *  Description:
2236  *  This function is a driver entry point which gets called by the kernel
2237  *  whenever multicast addresses must be enabled/disabled.
2238  *  Return value:
2239  *  void.
2240  */
2241 static void stmmac_set_rx_mode(struct net_device *dev)
2242 {
2243         struct stmmac_priv *priv = netdev_priv(dev);
2244
2245         spin_lock(&priv->lock);
2246         priv->hw->mac->set_filter(dev, priv->synopsys_id);
2247         spin_unlock(&priv->lock);
2248 }
2249
2250 /**
2251  *  stmmac_change_mtu - entry point to change MTU size for the device.
2252  *  @dev : device pointer.
2253  *  @new_mtu : the new MTU size for the device.
2254  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2255  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2256  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2257  *  Return value:
2258  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2259  *  file on failure.
2260  */
2261 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2262 {
2263         struct stmmac_priv *priv = netdev_priv(dev);
2264         int max_mtu;
2265
2266         if (netif_running(dev)) {
2267                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2268                 return -EBUSY;
2269         }
2270
2271         if (priv->plat->enh_desc)
2272                 max_mtu = JUMBO_LEN;
2273         else
2274                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2275
2276         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2277                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2278                 return -EINVAL;
2279         }
2280
2281         dev->mtu = new_mtu;
2282         netdev_update_features(dev);
2283
2284         return 0;
2285 }
2286
2287 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2288                                              netdev_features_t features)
2289 {
2290         struct stmmac_priv *priv = netdev_priv(dev);
2291
2292         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2293                 features &= ~NETIF_F_RXCSUM;
2294         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
2295                 features &= ~NETIF_F_IPV6_CSUM;
2296         if (!priv->plat->tx_coe)
2297                 features &= ~NETIF_F_ALL_CSUM;
2298
2299         /* Some GMAC devices have a bugged Jumbo frame support that
2300          * needs to have the Tx COE disabled for oversized frames
2301          * (due to limited buffer sizes). In this case we disable
2302          * the TX csum insertionin the TDES and not use SF.
2303          */
2304         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2305                 features &= ~NETIF_F_ALL_CSUM;
2306
2307         return features;
2308 }
2309
2310 /**
2311  *  stmmac_interrupt - main ISR
2312  *  @irq: interrupt number.
2313  *  @dev_id: to pass the net device pointer.
2314  *  Description: this is the main driver interrupt service routine.
2315  *  It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2316  *  interrupts.
2317  */
2318 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2319 {
2320         struct net_device *dev = (struct net_device *)dev_id;
2321         struct stmmac_priv *priv = netdev_priv(dev);
2322
2323         if (priv->irq_wake)
2324                 pm_wakeup_event(priv->device, 0);
2325
2326         if (unlikely(!dev)) {
2327                 pr_err("%s: invalid dev pointer\n", __func__);
2328                 return IRQ_NONE;
2329         }
2330
2331         /* To handle GMAC own interrupts */
2332         if (priv->plat->has_gmac) {
2333                 int status = priv->hw->mac->host_irq_status((void __iomem *)
2334                                                             dev->base_addr,
2335                                                             &priv->xstats);
2336                 if (unlikely(status)) {
2337                         /* For LPI we need to save the tx status */
2338                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2339                                 priv->tx_path_in_lpi_mode = true;
2340                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2341                                 priv->tx_path_in_lpi_mode = false;
2342                 }
2343         }
2344
2345         /* To handle DMA interrupts */
2346         stmmac_dma_interrupt(priv);
2347
2348         return IRQ_HANDLED;
2349 }
2350
2351 #ifdef CONFIG_NET_POLL_CONTROLLER
2352 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2353  * to allow network I/O with interrupts disabled.
2354  */
2355 static void stmmac_poll_controller(struct net_device *dev)
2356 {
2357         disable_irq(dev->irq);
2358         stmmac_interrupt(dev->irq, dev);
2359         enable_irq(dev->irq);
2360 }
2361 #endif
2362
2363 /**
2364  *  stmmac_ioctl - Entry point for the Ioctl
2365  *  @dev: Device pointer.
2366  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2367  *  a proprietary structure used to pass information to the driver.
2368  *  @cmd: IOCTL command
2369  *  Description:
2370  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2371  */
2372 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2373 {
2374         struct stmmac_priv *priv = netdev_priv(dev);
2375         int ret = -EOPNOTSUPP;
2376
2377         if (!netif_running(dev))
2378                 return -EINVAL;
2379
2380         switch (cmd) {
2381         case SIOCGMIIPHY:
2382         case SIOCGMIIREG:
2383         case SIOCSMIIREG:
2384                 if (!priv->phydev)
2385                         return -EINVAL;
2386                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2387                 break;
2388         case SIOCSHWTSTAMP:
2389                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2390                 break;
2391         default:
2392                 break;
2393         }
2394
2395         return ret;
2396 }
2397
2398 #ifdef CONFIG_STMMAC_DEBUG_FS
2399 static struct dentry *stmmac_fs_dir;
2400 static struct dentry *stmmac_rings_status;
2401 static struct dentry *stmmac_dma_cap;
2402
2403 static void sysfs_display_ring(void *head, int size, int extend_desc,
2404                                struct seq_file *seq)
2405 {
2406         int i;
2407         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2408         struct dma_desc *p = (struct dma_desc *)head;
2409
2410         for (i = 0; i < size; i++) {
2411                 u64 x;
2412                 if (extend_desc) {
2413                         x = *(u64 *) ep;
2414                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2415                                    i, (unsigned int)virt_to_phys(ep),
2416                                    (unsigned int)x, (unsigned int)(x >> 32),
2417                                    ep->basic.des2, ep->basic.des3);
2418                         ep++;
2419                 } else {
2420                         x = *(u64 *) p;
2421                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2422                                    i, (unsigned int)virt_to_phys(ep),
2423                                    (unsigned int)x, (unsigned int)(x >> 32),
2424                                    p->des2, p->des3);
2425                         p++;
2426                 }
2427                 seq_printf(seq, "\n");
2428         }
2429 }
2430
2431 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2432 {
2433         struct net_device *dev = seq->private;
2434         struct stmmac_priv *priv = netdev_priv(dev);
2435         unsigned int txsize = priv->dma_tx_size;
2436         unsigned int rxsize = priv->dma_rx_size;
2437
2438         if (priv->extend_desc) {
2439                 seq_printf(seq, "Extended RX descriptor ring:\n");
2440                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2441                 seq_printf(seq, "Extended TX descriptor ring:\n");
2442                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2443         } else {
2444                 seq_printf(seq, "RX descriptor ring:\n");
2445                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2446                 seq_printf(seq, "TX descriptor ring:\n");
2447                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2448         }
2449
2450         return 0;
2451 }
2452
2453 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2454 {
2455         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2456 }
2457
2458 static const struct file_operations stmmac_rings_status_fops = {
2459         .owner = THIS_MODULE,
2460         .open = stmmac_sysfs_ring_open,
2461         .read = seq_read,
2462         .llseek = seq_lseek,
2463         .release = single_release,
2464 };
2465
2466 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2467 {
2468         struct net_device *dev = seq->private;
2469         struct stmmac_priv *priv = netdev_priv(dev);
2470
2471         if (!priv->hw_cap_support) {
2472                 seq_printf(seq, "DMA HW features not supported\n");
2473                 return 0;
2474         }
2475
2476         seq_printf(seq, "==============================\n");
2477         seq_printf(seq, "\tDMA HW features\n");
2478         seq_printf(seq, "==============================\n");
2479
2480         seq_printf(seq, "\t10/100 Mbps %s\n",
2481                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2482         seq_printf(seq, "\t1000 Mbps %s\n",
2483                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2484         seq_printf(seq, "\tHalf duple %s\n",
2485                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2486         seq_printf(seq, "\tHash Filter: %s\n",
2487                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2488         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2489                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2490         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2491                    (priv->dma_cap.pcs) ? "Y" : "N");
2492         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2493                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2494         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2495                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2496         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2497                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2498         seq_printf(seq, "\tRMON module: %s\n",
2499                    (priv->dma_cap.rmon) ? "Y" : "N");
2500         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2501                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2502         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2503                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2504         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2505                    (priv->dma_cap.eee) ? "Y" : "N");
2506         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2507         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2508                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2509         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2510                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2511         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2512                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2513         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2514                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2515         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2516                    priv->dma_cap.number_rx_channel);
2517         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2518                    priv->dma_cap.number_tx_channel);
2519         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2520                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2521
2522         return 0;
2523 }
2524
2525 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2526 {
2527         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2528 }
2529
2530 static const struct file_operations stmmac_dma_cap_fops = {
2531         .owner = THIS_MODULE,
2532         .open = stmmac_sysfs_dma_cap_open,
2533         .read = seq_read,
2534         .llseek = seq_lseek,
2535         .release = single_release,
2536 };
2537
2538 static int stmmac_init_fs(struct net_device *dev)
2539 {
2540         /* Create debugfs entries */
2541         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2542
2543         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2544                 pr_err("ERROR %s, debugfs create directory failed\n",
2545                        STMMAC_RESOURCE_NAME);
2546
2547                 return -ENOMEM;
2548         }
2549
2550         /* Entry to report DMA RX/TX rings */
2551         stmmac_rings_status = debugfs_create_file("descriptors_status",
2552                                                   S_IRUGO, stmmac_fs_dir, dev,
2553                                                   &stmmac_rings_status_fops);
2554
2555         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2556                 pr_info("ERROR creating stmmac ring debugfs file\n");
2557                 debugfs_remove(stmmac_fs_dir);
2558
2559                 return -ENOMEM;
2560         }
2561
2562         /* Entry to report the DMA HW features */
2563         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2564                                              dev, &stmmac_dma_cap_fops);
2565
2566         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2567                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2568                 debugfs_remove(stmmac_rings_status);
2569                 debugfs_remove(stmmac_fs_dir);
2570
2571                 return -ENOMEM;
2572         }
2573
2574         return 0;
2575 }
2576
2577 static void stmmac_exit_fs(void)
2578 {
2579         debugfs_remove(stmmac_rings_status);
2580         debugfs_remove(stmmac_dma_cap);
2581         debugfs_remove(stmmac_fs_dir);
2582 }
2583 #endif /* CONFIG_STMMAC_DEBUG_FS */
2584
2585 static const struct net_device_ops stmmac_netdev_ops = {
2586         .ndo_open = stmmac_open,
2587         .ndo_start_xmit = stmmac_xmit,
2588         .ndo_stop = stmmac_release,
2589         .ndo_change_mtu = stmmac_change_mtu,
2590         .ndo_fix_features = stmmac_fix_features,
2591         .ndo_set_rx_mode = stmmac_set_rx_mode,
2592         .ndo_tx_timeout = stmmac_tx_timeout,
2593         .ndo_do_ioctl = stmmac_ioctl,
2594         .ndo_set_config = stmmac_config,
2595 #ifdef CONFIG_NET_POLL_CONTROLLER
2596         .ndo_poll_controller = stmmac_poll_controller,
2597 #endif
2598         .ndo_set_mac_address = eth_mac_addr,
2599 };
2600
2601 /**
2602  *  stmmac_hw_init - Init the MAC device
2603  *  @priv: driver private structure
2604  *  Description: this function detects which MAC device
2605  *  (GMAC/MAC10-100) has to attached, checks the HW capability
2606  *  (if supported) and sets the driver's features (for example
2607  *  to use the ring or chaine mode or support the normal/enh
2608  *  descriptor structure).
2609  */
2610 static int stmmac_hw_init(struct stmmac_priv *priv)
2611 {
2612         int ret;
2613         struct mac_device_info *mac;
2614
2615         /* Identify the MAC HW device */
2616         if (priv->plat->has_gmac) {
2617                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2618                 mac = dwmac1000_setup(priv->ioaddr);
2619         } else {
2620                 mac = dwmac100_setup(priv->ioaddr);
2621         }
2622         if (!mac)
2623                 return -ENOMEM;
2624
2625         priv->hw = mac;
2626
2627         /* Get and dump the chip ID */
2628         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2629
2630         /* To use the chained or ring mode */
2631         if (chain_mode) {
2632                 priv->hw->chain = &chain_mode_ops;
2633                 pr_info(" Chain mode enabled\n");
2634                 priv->mode = STMMAC_CHAIN_MODE;
2635         } else {
2636                 priv->hw->ring = &ring_mode_ops;
2637                 pr_info(" Ring mode enabled\n");
2638                 priv->mode = STMMAC_RING_MODE;
2639         }
2640
2641         /* Get the HW capability (new GMAC newer than 3.50a) */
2642         priv->hw_cap_support = stmmac_get_hw_features(priv);
2643         if (priv->hw_cap_support) {
2644                 pr_info(" DMA HW capability register supported");
2645
2646                 /* We can override some gmac/dma configuration fields: e.g.
2647                  * enh_desc, tx_coe (e.g. that are passed through the
2648                  * platform) with the values from the HW capability
2649                  * register (if supported).
2650                  */
2651                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2652                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2653
2654                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2655
2656                 if (priv->dma_cap.rx_coe_type2)
2657                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2658                 else if (priv->dma_cap.rx_coe_type1)
2659                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2660
2661         } else
2662                 pr_info(" No HW DMA feature register supported");
2663
2664         /* To use alternate (extended) or normal descriptor structures */
2665         stmmac_selec_desc_mode(priv);
2666
2667         ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2668         if (!ret) {
2669                 pr_warn(" RX IPC Checksum Offload not configured.\n");
2670                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2671         }
2672
2673         if (priv->plat->rx_coe)
2674                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2675                         priv->plat->rx_coe);
2676         if (priv->plat->tx_coe)
2677                 pr_info(" TX Checksum insertion supported\n");
2678
2679         if (priv->plat->pmt) {
2680                 pr_info(" Wake-Up On Lan supported\n");
2681                 device_set_wakeup_capable(priv->device, 1);
2682         }
2683
2684         return 0;
2685 }
2686
2687 /**
2688  * stmmac_dvr_probe
2689  * @device: device pointer
2690  * @plat_dat: platform data pointer
2691  * @addr: iobase memory address
2692  * Description: this is the main probe function used to
2693  * call the alloc_etherdev, allocate the priv structure.
2694  */
2695 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2696                                      struct plat_stmmacenet_data *plat_dat,
2697                                      void __iomem *addr)
2698 {
2699         int ret = 0;
2700         struct net_device *ndev = NULL;
2701         struct stmmac_priv *priv;
2702
2703         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2704         if (!ndev)
2705                 return NULL;
2706
2707         SET_NETDEV_DEV(ndev, device);
2708
2709         priv = netdev_priv(ndev);
2710         priv->device = device;
2711         priv->dev = ndev;
2712
2713         ether_setup(ndev);
2714
2715         stmmac_set_ethtool_ops(ndev);
2716         priv->pause = pause;
2717         priv->plat = plat_dat;
2718         priv->ioaddr = addr;
2719         priv->dev->base_addr = (unsigned long)addr;
2720
2721         /* Verify driver arguments */
2722         stmmac_verify_args();
2723
2724         /* Override with kernel parameters if supplied XXX CRS XXX
2725          * this needs to have multiple instances
2726          */
2727         if ((phyaddr >= 0) && (phyaddr <= 31))
2728                 priv->plat->phy_addr = phyaddr;
2729
2730         /* Init MAC and get the capabilities */
2731         ret = stmmac_hw_init(priv);
2732         if (ret)
2733                 goto error_free_netdev;
2734
2735         ndev->netdev_ops = &stmmac_netdev_ops;
2736
2737         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2738                             NETIF_F_RXCSUM;
2739         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2740         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2741 #ifdef STMMAC_VLAN_TAG_USED
2742         /* Both mac100 and gmac support receive VLAN tag detection */
2743         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2744 #endif
2745         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2746
2747         if (flow_ctrl)
2748                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2749
2750         /* Rx Watchdog is available in the COREs newer than the 3.40.
2751          * In some case, for example on bugged HW this feature
2752          * has to be disable and this can be done by passing the
2753          * riwt_off field from the platform.
2754          */
2755         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2756                 priv->use_riwt = 1;
2757                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2758         }
2759
2760         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2761
2762         spin_lock_init(&priv->lock);
2763         spin_lock_init(&priv->tx_lock);
2764
2765         ret = register_netdev(ndev);
2766         if (ret) {
2767                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2768                 goto error_netdev_register;
2769         }
2770
2771         priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
2772         if (IS_ERR(priv->stmmac_clk)) {
2773                 pr_warn("%s: warning: cannot get CSR clock\n", __func__);
2774                 goto error_clk_get;
2775         }
2776
2777         /* If a specific clk_csr value is passed from the platform
2778          * this means that the CSR Clock Range selection cannot be
2779          * changed at run-time and it is fixed. Viceversa the driver'll try to
2780          * set the MDC clock dynamically according to the csr actual
2781          * clock input.
2782          */
2783         if (!priv->plat->clk_csr)
2784                 stmmac_clk_csr_set(priv);
2785         else
2786                 priv->clk_csr = priv->plat->clk_csr;
2787
2788         stmmac_check_pcs_mode(priv);
2789
2790         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2791             priv->pcs != STMMAC_PCS_RTBI) {
2792                 /* MDIO bus Registration */
2793                 ret = stmmac_mdio_register(ndev);
2794                 if (ret < 0) {
2795                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2796                                  __func__, priv->plat->bus_id);
2797                         goto error_mdio_register;
2798                 }
2799         }
2800
2801         return priv;
2802
2803 error_mdio_register:
2804         clk_put(priv->stmmac_clk);
2805 error_clk_get:
2806         unregister_netdev(ndev);
2807 error_netdev_register:
2808         netif_napi_del(&priv->napi);
2809 error_free_netdev:
2810         free_netdev(ndev);
2811
2812         return NULL;
2813 }
2814
2815 /**
2816  * stmmac_dvr_remove
2817  * @ndev: net device pointer
2818  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2819  * changes the link status, releases the DMA descriptor rings.
2820  */
2821 int stmmac_dvr_remove(struct net_device *ndev)
2822 {
2823         struct stmmac_priv *priv = netdev_priv(ndev);
2824
2825         pr_info("%s:\n\tremoving driver", __func__);
2826
2827         priv->hw->dma->stop_rx(priv->ioaddr);
2828         priv->hw->dma->stop_tx(priv->ioaddr);
2829
2830         stmmac_set_mac(priv->ioaddr, false);
2831         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2832             priv->pcs != STMMAC_PCS_RTBI)
2833                 stmmac_mdio_unregister(ndev);
2834         netif_carrier_off(ndev);
2835         unregister_netdev(ndev);
2836         free_netdev(ndev);
2837
2838         return 0;
2839 }
2840
2841 #ifdef CONFIG_PM
2842 int stmmac_suspend(struct net_device *ndev)
2843 {
2844         struct stmmac_priv *priv = netdev_priv(ndev);
2845         unsigned long flags;
2846
2847         if (!ndev || !netif_running(ndev))
2848                 return 0;
2849
2850         if (priv->phydev)
2851                 phy_stop(priv->phydev);
2852
2853         spin_lock_irqsave(&priv->lock, flags);
2854
2855         netif_device_detach(ndev);
2856         netif_stop_queue(ndev);
2857
2858         napi_disable(&priv->napi);
2859
2860         /* Stop TX/RX DMA */
2861         priv->hw->dma->stop_tx(priv->ioaddr);
2862         priv->hw->dma->stop_rx(priv->ioaddr);
2863
2864         stmmac_clear_descriptors(priv);
2865
2866         /* Enable Power down mode by programming the PMT regs */
2867         if (device_may_wakeup(priv->device)) {
2868                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2869                 priv->irq_wake = 1;
2870         } else {
2871                 stmmac_set_mac(priv->ioaddr, false);
2872                 pinctrl_pm_select_sleep_state(priv->device);
2873                 /* Disable clock in case of PWM is off */
2874                 clk_disable_unprepare(priv->stmmac_clk);
2875         }
2876         spin_unlock_irqrestore(&priv->lock, flags);
2877         return 0;
2878 }
2879
2880 int stmmac_resume(struct net_device *ndev)
2881 {
2882         struct stmmac_priv *priv = netdev_priv(ndev);
2883         unsigned long flags;
2884
2885         if (!netif_running(ndev))
2886                 return 0;
2887
2888         spin_lock_irqsave(&priv->lock, flags);
2889
2890         /* Power Down bit, into the PM register, is cleared
2891          * automatically as soon as a magic packet or a Wake-up frame
2892          * is received. Anyway, it's better to manually clear
2893          * this bit because it can generate problems while resuming
2894          * from another devices (e.g. serial console).
2895          */
2896         if (device_may_wakeup(priv->device)) {
2897                 priv->hw->mac->pmt(priv->ioaddr, 0);
2898                 priv->irq_wake = 0;
2899         } else {
2900                 pinctrl_pm_select_default_state(priv->device);
2901                 /* enable the clk prevously disabled */
2902                 clk_prepare_enable(priv->stmmac_clk);
2903                 /* reset the phy so that it's ready */
2904                 if (priv->mii)
2905                         stmmac_mdio_reset(priv->mii);
2906         }
2907
2908         netif_device_attach(ndev);
2909
2910         stmmac_hw_setup(ndev);
2911
2912         napi_enable(&priv->napi);
2913
2914         netif_start_queue(ndev);
2915
2916         spin_unlock_irqrestore(&priv->lock, flags);
2917
2918         if (priv->phydev)
2919                 phy_start(priv->phydev);
2920
2921         return 0;
2922 }
2923 #endif /* CONFIG_PM */
2924
2925 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2926  * depending on the configuration selected.
2927  */
2928 static int __init stmmac_init(void)
2929 {
2930         int ret;
2931
2932         ret = stmmac_register_platform();
2933         if (ret)
2934                 goto err;
2935         ret = stmmac_register_pci();
2936         if (ret)
2937                 goto err_pci;
2938         return 0;
2939 err_pci:
2940         stmmac_unregister_platform();
2941 err:
2942         pr_err("stmmac: driver registration failed\n");
2943         return ret;
2944 }
2945
2946 static void __exit stmmac_exit(void)
2947 {
2948         stmmac_unregister_platform();
2949         stmmac_unregister_pci();
2950 }
2951
2952 module_init(stmmac_init);
2953 module_exit(stmmac_exit);
2954
2955 #ifndef MODULE
2956 static int __init stmmac_cmdline_opt(char *str)
2957 {
2958         char *opt;
2959
2960         if (!str || !*str)
2961                 return -EINVAL;
2962         while ((opt = strsep(&str, ",")) != NULL) {
2963                 if (!strncmp(opt, "debug:", 6)) {
2964                         if (kstrtoint(opt + 6, 0, &debug))
2965                                 goto err;
2966                 } else if (!strncmp(opt, "phyaddr:", 8)) {
2967                         if (kstrtoint(opt + 8, 0, &phyaddr))
2968                                 goto err;
2969                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2970                         if (kstrtoint(opt + 11, 0, &dma_txsize))
2971                                 goto err;
2972                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2973                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
2974                                 goto err;
2975                 } else if (!strncmp(opt, "buf_sz:", 7)) {
2976                         if (kstrtoint(opt + 7, 0, &buf_sz))
2977                                 goto err;
2978                 } else if (!strncmp(opt, "tc:", 3)) {
2979                         if (kstrtoint(opt + 3, 0, &tc))
2980                                 goto err;
2981                 } else if (!strncmp(opt, "watchdog:", 9)) {
2982                         if (kstrtoint(opt + 9, 0, &watchdog))
2983                                 goto err;
2984                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2985                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
2986                                 goto err;
2987                 } else if (!strncmp(opt, "pause:", 6)) {
2988                         if (kstrtoint(opt + 6, 0, &pause))
2989                                 goto err;
2990                 } else if (!strncmp(opt, "eee_timer:", 10)) {
2991                         if (kstrtoint(opt + 10, 0, &eee_timer))
2992                                 goto err;
2993                 } else if (!strncmp(opt, "chain_mode:", 11)) {
2994                         if (kstrtoint(opt + 11, 0, &chain_mode))
2995                                 goto err;
2996                 }
2997         }
2998         return 0;
2999
3000 err:
3001         pr_err("%s: ERROR broken module parameter conversion", __func__);
3002         return -EINVAL;
3003 }
3004
3005 __setup("stmmaceth=", stmmac_cmdline_opt);
3006 #endif /* MODULE */
3007
3008 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3009 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3010 MODULE_LICENSE("GPL");