1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2010 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/random.h>
17 #include "net_driver.h"
25 #include "workarounds.h"
27 #include "mcdi_pcol.h"
30 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
32 static void siena_init_wol(struct efx_nic *efx);
33 static int siena_reset_hw(struct efx_nic *efx, enum reset_type method);
36 static void siena_push_irq_moderation(struct efx_channel *channel)
38 efx_dword_t timer_cmd;
40 if (channel->irq_moderation)
41 EFX_POPULATE_DWORD_2(timer_cmd,
43 FFE_CZ_TIMER_MODE_INT_HLDOFF,
45 channel->irq_moderation - 1);
47 EFX_POPULATE_DWORD_2(timer_cmd,
49 FFE_CZ_TIMER_MODE_DIS,
50 FRF_CZ_TC_TIMER_VAL, 0);
51 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
55 static int siena_mdio_write(struct net_device *net_dev,
56 int prtad, int devad, u16 addr, u16 value)
58 struct efx_nic *efx = netdev_priv(net_dev);
62 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
63 addr, value, &status);
66 if (status != MC_CMD_MDIO_STATUS_GOOD)
72 static int siena_mdio_read(struct net_device *net_dev,
73 int prtad, int devad, u16 addr)
75 struct efx_nic *efx = netdev_priv(net_dev);
80 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
81 addr, &value, &status);
84 if (status != MC_CMD_MDIO_STATUS_GOOD)
90 /* This call is responsible for hooking in the MAC and PHY operations */
91 static int siena_probe_port(struct efx_nic *efx)
95 /* Hook in PHY operations table */
96 efx->phy_op = &efx_mcdi_phy_ops;
98 /* Set up MDIO structure for PHY */
99 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
100 efx->mdio.mdio_read = siena_mdio_read;
101 efx->mdio.mdio_write = siena_mdio_write;
103 /* Fill out MDIO structure, loopback modes, and initial link state */
104 rc = efx->phy_op->probe(efx);
108 /* Allocate buffer for stats */
109 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
110 MC_CMD_MAC_NSTATS * sizeof(u64));
113 netif_dbg(efx, probe, efx->net_dev,
114 "stats buffer at %llx (virt %p phys %llx)\n",
115 (u64)efx->stats_buffer.dma_addr,
116 efx->stats_buffer.addr,
117 (u64)virt_to_phys(efx->stats_buffer.addr));
119 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
124 static void siena_remove_port(struct efx_nic *efx)
126 efx->phy_op->remove(efx);
127 efx_nic_free_buffer(efx, &efx->stats_buffer);
130 static const struct efx_nic_register_test siena_register_tests[] = {
132 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
134 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
136 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
138 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
140 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
141 { FR_AZ_SRM_TX_DC_CFG,
142 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
144 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
146 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
148 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
150 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
151 { FR_CZ_RX_RSS_IPV6_REG1,
152 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
153 { FR_CZ_RX_RSS_IPV6_REG2,
154 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
155 { FR_CZ_RX_RSS_IPV6_REG3,
156 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
159 static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
161 enum reset_type reset_method = reset_method;
164 efx_reset_down(efx, reset_method);
166 /* Reset the chip immediately so that it is completely
167 * quiescent regardless of what any VF driver does.
169 rc = siena_reset_hw(efx, reset_method);
174 efx_nic_test_registers(efx, siena_register_tests,
175 ARRAY_SIZE(siena_register_tests))
178 rc = siena_reset_hw(efx, reset_method);
180 rc2 = efx_reset_up(efx, reset_method, rc == 0);
181 return rc ? rc : rc2;
184 /**************************************************************************
188 **************************************************************************
191 static enum reset_type siena_map_reset_reason(enum reset_type reason)
193 return RESET_TYPE_ALL;
196 static int siena_map_reset_flags(u32 *flags)
199 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
200 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
202 SIENA_RESET_MC = (SIENA_RESET_PORT |
203 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
206 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
207 *flags &= ~SIENA_RESET_MC;
208 return RESET_TYPE_WORLD;
211 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
212 *flags &= ~SIENA_RESET_PORT;
213 return RESET_TYPE_ALL;
216 /* no invisible reset implemented */
221 static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
225 /* Recover from a failed assertion pre-reset */
226 rc = efx_mcdi_handle_assertion(efx);
230 if (method == RESET_TYPE_WORLD)
231 return efx_mcdi_reset_mc(efx);
233 return efx_mcdi_reset_port(efx);
236 static int siena_probe_nvconfig(struct efx_nic *efx)
241 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
243 efx->timer_quantum_ns =
244 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
245 3072 : 6144; /* 768 cycles */
249 static void siena_dimension_resources(struct efx_nic *efx)
251 /* Each port has a small block of internal SRAM dedicated to
252 * the buffer table and descriptor caches. In theory we can
253 * map both blocks to one port, but we don't.
255 efx_nic_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
258 static int siena_probe_nic(struct efx_nic *efx)
260 struct siena_nic_data *nic_data;
261 bool already_attached = false;
265 /* Allocate storage for hardware specific data */
266 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
269 efx->nic_data = nic_data;
271 if (efx_nic_fpga_ver(efx) != 0) {
272 netif_err(efx, probe, efx->net_dev,
273 "Siena FPGA not supported\n");
278 efx_reado(efx, ®, FR_AZ_CS_DEBUG);
279 efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
283 /* Recover from a failed assertion before probing */
284 rc = efx_mcdi_handle_assertion(efx);
288 /* Let the BMC know that the driver is now in charge of link and
289 * filter settings. We must do this before we reset the NIC */
290 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
292 netif_err(efx, probe, efx->net_dev,
293 "Unable to register driver with MCPU\n");
296 if (already_attached)
297 /* Not a fatal error */
298 netif_err(efx, probe, efx->net_dev,
299 "Host already registered with MCPU\n");
301 /* Now we can reset the NIC */
302 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
304 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
310 /* Allocate memory for INT_KER */
311 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
314 BUG_ON(efx->irq_status.dma_addr & 0x0f);
316 netif_dbg(efx, probe, efx->net_dev,
317 "INT_KER at %llx (virt %p phys %llx)\n",
318 (unsigned long long)efx->irq_status.dma_addr,
319 efx->irq_status.addr,
320 (unsigned long long)virt_to_phys(efx->irq_status.addr));
322 /* Read in the non-volatile configuration */
323 rc = siena_probe_nvconfig(efx);
325 netif_err(efx, probe, efx->net_dev,
326 "NVRAM is invalid therefore using defaults\n");
327 efx->phy_type = PHY_TYPE_NONE;
328 efx->mdio.prtad = MDIO_PRTAD_NONE;
333 rc = efx_mcdi_mon_probe(efx);
337 efx_sriov_probe(efx);
342 efx_nic_free_buffer(efx, &efx->irq_status);
345 efx_mcdi_drv_attach(efx, false, NULL);
348 kfree(efx->nic_data);
352 /* This call performs hardware-specific global initialisation, such as
353 * defining the descriptor cache sizes and number of RSS channels.
354 * It does not set up any buffers, descriptor rings or event queues.
356 static int siena_init_nic(struct efx_nic *efx)
361 /* Recover from a failed assertion post-reset */
362 rc = efx_mcdi_handle_assertion(efx);
366 /* Squash TX of packets of 16 bytes or less */
367 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
368 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
369 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
371 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
372 * descriptors (which is bad).
374 efx_reado(efx, &temp, FR_AZ_TX_CFG);
375 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
376 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
377 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
379 efx_reado(efx, &temp, FR_AZ_RX_CFG);
380 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
381 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
382 /* Enable hash insertion. This is broken for the 'Falcon' hash
383 * if IPv6 hashing is also enabled, so also select Toeplitz
384 * TCP/IPv4 and IPv4 hashes. */
385 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
386 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
387 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
388 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
390 /* Set hash key for IPv4 */
391 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
392 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
394 /* Enable IPv6 RSS */
395 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
396 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
397 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
398 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
399 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
400 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
401 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
402 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
403 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
404 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
405 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
406 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
408 /* Enable event logging */
409 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
413 /* Set destination of both TX and RX Flush events */
414 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
415 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
417 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
418 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
420 efx_nic_init_common(efx);
424 static void siena_remove_nic(struct efx_nic *efx)
426 efx_mcdi_mon_remove(efx);
428 efx_nic_free_buffer(efx, &efx->irq_status);
430 siena_reset_hw(efx, RESET_TYPE_ALL);
432 /* Relinquish the device back to the BMC */
433 efx_mcdi_drv_attach(efx, false, NULL);
435 /* Tear down the private nic state */
436 kfree(efx->nic_data);
437 efx->nic_data = NULL;
440 #define STATS_GENERATION_INVALID ((__force __le64)(-1))
442 static int siena_try_update_nic_stats(struct efx_nic *efx)
445 struct efx_mac_stats *mac_stats;
446 __le64 generation_start, generation_end;
448 mac_stats = &efx->mac_stats;
449 dma_stats = efx->stats_buffer.addr;
451 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
452 if (generation_end == STATS_GENERATION_INVALID)
456 #define MAC_STAT(M, D) \
457 mac_stats->M = le64_to_cpu(dma_stats[MC_CMD_MAC_ ## D])
459 MAC_STAT(tx_bytes, TX_BYTES);
460 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
461 efx_update_diff_stat(&mac_stats->tx_good_bytes,
462 mac_stats->tx_bytes - mac_stats->tx_bad_bytes);
463 MAC_STAT(tx_packets, TX_PKTS);
464 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
465 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
466 MAC_STAT(tx_control, TX_CONTROL_PKTS);
467 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
468 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
469 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
470 MAC_STAT(tx_lt64, TX_LT64_PKTS);
471 MAC_STAT(tx_64, TX_64_PKTS);
472 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
473 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
474 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
475 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
476 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
477 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
478 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
479 mac_stats->tx_collision = 0;
480 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
481 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
482 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
483 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
484 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
485 mac_stats->tx_collision = (mac_stats->tx_single_collision +
486 mac_stats->tx_multiple_collision +
487 mac_stats->tx_excessive_collision +
488 mac_stats->tx_late_collision);
489 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
490 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
491 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
492 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
493 MAC_STAT(rx_bytes, RX_BYTES);
494 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
495 efx_update_diff_stat(&mac_stats->rx_good_bytes,
496 mac_stats->rx_bytes - mac_stats->rx_bad_bytes);
497 MAC_STAT(rx_packets, RX_PKTS);
498 MAC_STAT(rx_good, RX_GOOD_PKTS);
499 MAC_STAT(rx_bad, RX_BAD_FCS_PKTS);
500 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
501 MAC_STAT(rx_control, RX_CONTROL_PKTS);
502 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
503 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
504 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
505 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
506 MAC_STAT(rx_64, RX_64_PKTS);
507 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
508 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
509 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
510 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
511 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
512 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
513 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
514 mac_stats->rx_bad_lt64 = 0;
515 mac_stats->rx_bad_64_to_15xx = 0;
516 mac_stats->rx_bad_15xx_to_jumbo = 0;
517 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
518 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
519 mac_stats->rx_missed = 0;
520 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
521 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
522 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
523 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
524 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
525 mac_stats->rx_good_lt64 = 0;
527 efx->n_rx_nodesc_drop_cnt =
528 le64_to_cpu(dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]);
533 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
534 if (generation_end != generation_start)
540 static void siena_update_nic_stats(struct efx_nic *efx)
544 /* If we're unlucky enough to read statistics wduring the DMA, wait
545 * up to 10ms for it to finish (typically takes <500us) */
546 for (retry = 0; retry < 100; ++retry) {
547 if (siena_try_update_nic_stats(efx) == 0)
552 /* Use the old values instead */
555 static void siena_start_nic_stats(struct efx_nic *efx)
557 __le64 *dma_stats = efx->stats_buffer.addr;
559 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
561 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
562 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
565 static void siena_stop_nic_stats(struct efx_nic *efx)
567 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
570 /**************************************************************************
574 **************************************************************************
577 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
579 struct siena_nic_data *nic_data = efx->nic_data;
581 wol->supported = WAKE_MAGIC;
582 if (nic_data->wol_filter_id != -1)
583 wol->wolopts = WAKE_MAGIC;
586 memset(&wol->sopass, 0, sizeof(wol->sopass));
590 static int siena_set_wol(struct efx_nic *efx, u32 type)
592 struct siena_nic_data *nic_data = efx->nic_data;
595 if (type & ~WAKE_MAGIC)
598 if (type & WAKE_MAGIC) {
599 if (nic_data->wol_filter_id != -1)
600 efx_mcdi_wol_filter_remove(efx,
601 nic_data->wol_filter_id);
602 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
603 &nic_data->wol_filter_id);
607 pci_wake_from_d3(efx->pci_dev, true);
609 rc = efx_mcdi_wol_filter_reset(efx);
610 nic_data->wol_filter_id = -1;
611 pci_wake_from_d3(efx->pci_dev, false);
618 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
624 static void siena_init_wol(struct efx_nic *efx)
626 struct siena_nic_data *nic_data = efx->nic_data;
629 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
632 /* If it failed, attempt to get into a synchronised
633 * state with MC by resetting any set WoL filters */
634 efx_mcdi_wol_filter_reset(efx);
635 nic_data->wol_filter_id = -1;
636 } else if (nic_data->wol_filter_id != -1) {
637 pci_wake_from_d3(efx->pci_dev, true);
642 /**************************************************************************
644 * Revision-dependent attributes used by efx.c and nic.c
646 **************************************************************************
649 const struct efx_nic_type siena_a0_nic_type = {
650 .probe = siena_probe_nic,
651 .remove = siena_remove_nic,
652 .init = siena_init_nic,
653 .dimension_resources = siena_dimension_resources,
654 .fini = efx_port_dummy_op_void,
656 .map_reset_reason = siena_map_reset_reason,
657 .map_reset_flags = siena_map_reset_flags,
658 .reset = siena_reset_hw,
659 .probe_port = siena_probe_port,
660 .remove_port = siena_remove_port,
661 .prepare_flush = efx_port_dummy_op_void,
662 .update_stats = siena_update_nic_stats,
663 .start_stats = siena_start_nic_stats,
664 .stop_stats = siena_stop_nic_stats,
665 .set_id_led = efx_mcdi_set_id_led,
666 .push_irq_moderation = siena_push_irq_moderation,
667 .reconfigure_mac = efx_mcdi_mac_reconfigure,
668 .check_mac_fault = efx_mcdi_mac_check_fault,
669 .reconfigure_port = efx_mcdi_phy_reconfigure,
670 .get_wol = siena_get_wol,
671 .set_wol = siena_set_wol,
672 .resume_wol = siena_init_wol,
673 .test_chip = siena_test_chip,
674 .test_nvram = efx_mcdi_nvram_test_all,
676 .revision = EFX_REV_SIENA_A0,
677 .mem_map_size = (FR_CZ_MC_TREG_SMEM +
678 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
679 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
680 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
681 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
682 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
683 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
684 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
685 .rx_buffer_hash_size = 0x10,
686 .rx_buffer_padding = 0,
687 .max_interrupt_mode = EFX_INT_MODE_MSIX,
688 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
689 * interrupt handler only supports 32
691 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
692 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
693 NETIF_F_RXHASH | NETIF_F_NTUPLE),