Pileus Git - ~andy/linux/blob - drivers/net/ethernet/renesas/sh_eth.c

   1 /*
   2  *  SuperH Ethernet device driver
   3  *
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2013 Renesas Solutions Corp.
   6  *  Copyright (C) 2013 Cogent Embedded, Inc.
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms and conditions of the GNU General Public License,
  10  *  version 2, as published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  *  more details.
  16  *  You should have received a copy of the GNU General Public License along with
  17  *  this program; if not, write to the Free Software Foundation, Inc.,
  18  *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  *  The full GNU General Public License is included in this distribution in
  21  *  the file called "COPYING".
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/delay.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/mdio-bitbang.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/phy.h>
  36 #include <linux/cache.h>
  37 #include <linux/io.h>
  38 #include <linux/pm_runtime.h>
  39 #include <linux/slab.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/clk.h>
  43 #include <linux/sh_eth.h>
  44
  45 #include "sh_eth.h"
  46
  47 #define SH_ETH_DEF_MSG_ENABLE \
  48                 (NETIF_MSG_LINK | \
  49                 NETIF_MSG_TIMER | \
  50                 NETIF_MSG_RX_ERR| \
  51                 NETIF_MSG_TX_ERR)
  52
  53 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  54         [EDSR]          = 0x0000,
  55         [EDMR]          = 0x0400,
  56         [EDTRR]         = 0x0408,
  57         [EDRRR]         = 0x0410,
  58         [EESR]          = 0x0428,
  59         [EESIPR]        = 0x0430,
  60         [TDLAR]         = 0x0010,
  61         [TDFAR]         = 0x0014,
  62         [TDFXR]         = 0x0018,
  63         [TDFFR]         = 0x001c,
  64         [RDLAR]         = 0x0030,
  65         [RDFAR]         = 0x0034,
  66         [RDFXR]         = 0x0038,
  67         [RDFFR]         = 0x003c,
  68         [TRSCER]        = 0x0438,
  69         [RMFCR]         = 0x0440,
  70         [TFTR]          = 0x0448,
  71         [FDR]           = 0x0450,
  72         [RMCR]          = 0x0458,
  73         [RPADIR]        = 0x0460,
  74         [FCFTR]         = 0x0468,
  75         [CSMR]          = 0x04E4,
  76
  77         [ECMR]          = 0x0500,
  78         [ECSR]          = 0x0510,
  79         [ECSIPR]        = 0x0518,
  80         [PIR]           = 0x0520,
  81         [PSR]           = 0x0528,
  82         [PIPR]          = 0x052c,
  83         [RFLR]          = 0x0508,
  84         [APR]           = 0x0554,
  85         [MPR]           = 0x0558,
  86         [PFTCR]         = 0x055c,
  87         [PFRCR]         = 0x0560,
  88         [TPAUSER]       = 0x0564,
  89         [GECMR]         = 0x05b0,
  90         [BCULR]         = 0x05b4,
  91         [MAHR]          = 0x05c0,
  92         [MALR]          = 0x05c8,
  93         [TROCR]         = 0x0700,
  94         [CDCR]          = 0x0708,
  95         [LCCR]          = 0x0710,
  96         [CEFCR]         = 0x0740,
  97         [FRECR]         = 0x0748,
  98         [TSFRCR]        = 0x0750,
  99         [TLFRCR]        = 0x0758,
 100         [RFCR]          = 0x0760,
 101         [CERCR]         = 0x0768,
 102         [CEECR]         = 0x0770,
 103         [MAFCR]         = 0x0778,
 104         [RMII_MII]      = 0x0790,
 105
 106         [ARSTR]         = 0x0000,
 107         [TSU_CTRST]     = 0x0004,
 108         [TSU_FWEN0]     = 0x0010,
 109         [TSU_FWEN1]     = 0x0014,
 110         [TSU_FCM]       = 0x0018,
 111         [TSU_BSYSL0]    = 0x0020,
 112         [TSU_BSYSL1]    = 0x0024,
 113         [TSU_PRISL0]    = 0x0028,
 114         [TSU_PRISL1]    = 0x002c,
 115         [TSU_FWSL0]     = 0x0030,
 116         [TSU_FWSL1]     = 0x0034,
 117         [TSU_FWSLC]     = 0x0038,
 118         [TSU_QTAG0]     = 0x0040,
 119         [TSU_QTAG1]     = 0x0044,
 120         [TSU_FWSR]      = 0x0050,
 121         [TSU_FWINMK]    = 0x0054,
 122         [TSU_ADQT0]     = 0x0048,
 123         [TSU_ADQT1]     = 0x004c,
 124         [TSU_VTAG0]     = 0x0058,
 125         [TSU_VTAG1]     = 0x005c,
 126         [TSU_ADSBSY]    = 0x0060,
 127         [TSU_TEN]       = 0x0064,
 128         [TSU_POST1]     = 0x0070,
 129         [TSU_POST2]     = 0x0074,
 130         [TSU_POST3]     = 0x0078,
 131         [TSU_POST4]     = 0x007c,
 132         [TSU_ADRH0]     = 0x0100,
 133         [TSU_ADRL0]     = 0x0104,
 134         [TSU_ADRH31]    = 0x01f8,
 135         [TSU_ADRL31]    = 0x01fc,
 136
 137         [TXNLCR0]       = 0x0080,
 138         [TXALCR0]       = 0x0084,
 139         [RXNLCR0]       = 0x0088,
 140         [RXALCR0]       = 0x008c,
 141         [FWNLCR0]       = 0x0090,
 142         [FWALCR0]       = 0x0094,
 143         [TXNLCR1]       = 0x00a0,
 144         [TXALCR1]       = 0x00a0,
 145         [RXNLCR1]       = 0x00a8,
 146         [RXALCR1]       = 0x00ac,
 147         [FWNLCR1]       = 0x00b0,
 148         [FWALCR1]       = 0x00b4,
 149 };
 150
 151 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 152         [ECMR]          = 0x0300,
 153         [RFLR]          = 0x0308,
 154         [ECSR]          = 0x0310,
 155         [ECSIPR]        = 0x0318,
 156         [PIR]           = 0x0320,
 157         [PSR]           = 0x0328,
 158         [RDMLR]         = 0x0340,
 159         [IPGR]          = 0x0350,
 160         [APR]           = 0x0354,
 161         [MPR]           = 0x0358,
 162         [RFCF]          = 0x0360,
 163         [TPAUSER]       = 0x0364,
 164         [TPAUSECR]      = 0x0368,
 165         [MAHR]          = 0x03c0,
 166         [MALR]          = 0x03c8,
 167         [TROCR]         = 0x03d0,
 168         [CDCR]          = 0x03d4,
 169         [LCCR]          = 0x03d8,
 170         [CNDCR]         = 0x03dc,
 171         [CEFCR]         = 0x03e4,
 172         [FRECR]         = 0x03e8,
 173         [TSFRCR]        = 0x03ec,
 174         [TLFRCR]        = 0x03f0,
 175         [RFCR]          = 0x03f4,
 176         [MAFCR]         = 0x03f8,
 177
 178         [EDMR]          = 0x0200,
 179         [EDTRR]         = 0x0208,
 180         [EDRRR]         = 0x0210,
 181         [TDLAR]         = 0x0218,
 182         [RDLAR]         = 0x0220,
 183         [EESR]          = 0x0228,
 184         [EESIPR]        = 0x0230,
 185         [TRSCER]        = 0x0238,
 186         [RMFCR]         = 0x0240,
 187         [TFTR]          = 0x0248,
 188         [FDR]           = 0x0250,
 189         [RMCR]          = 0x0258,
 190         [TFUCR]         = 0x0264,
 191         [RFOCR]         = 0x0268,
 192         [FCFTR]         = 0x0270,
 193         [TRIMD]         = 0x027c,
 194 };
 195
 196 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 197         [ECMR]          = 0x0100,
 198         [RFLR]          = 0x0108,
 199         [ECSR]          = 0x0110,
 200         [ECSIPR]        = 0x0118,
 201         [PIR]           = 0x0120,
 202         [PSR]           = 0x0128,
 203         [RDMLR]         = 0x0140,
 204         [IPGR]          = 0x0150,
 205         [APR]           = 0x0154,
 206         [MPR]           = 0x0158,
 207         [TPAUSER]       = 0x0164,
 208         [RFCF]          = 0x0160,
 209         [TPAUSECR]      = 0x0168,
 210         [BCFRR]         = 0x016c,
 211         [MAHR]          = 0x01c0,
 212         [MALR]          = 0x01c8,
 213         [TROCR]         = 0x01d0,
 214         [CDCR]          = 0x01d4,
 215         [LCCR]          = 0x01d8,
 216         [CNDCR]         = 0x01dc,
 217         [CEFCR]         = 0x01e4,
 218         [FRECR]         = 0x01e8,
 219         [TSFRCR]        = 0x01ec,
 220         [TLFRCR]        = 0x01f0,
 221         [RFCR]          = 0x01f4,
 222         [MAFCR]         = 0x01f8,
 223         [RTRATE]        = 0x01fc,
 224
 225         [EDMR]          = 0x0000,
 226         [EDTRR]         = 0x0008,
 227         [EDRRR]         = 0x0010,
 228         [TDLAR]         = 0x0018,
 229         [RDLAR]         = 0x0020,
 230         [EESR]          = 0x0028,
 231         [EESIPR]        = 0x0030,
 232         [TRSCER]        = 0x0038,
 233         [RMFCR]         = 0x0040,
 234         [TFTR]          = 0x0048,
 235         [FDR]           = 0x0050,
 236         [RMCR]          = 0x0058,
 237         [TFUCR]         = 0x0064,
 238         [RFOCR]         = 0x0068,
 239         [FCFTR]         = 0x0070,
 240         [RPADIR]        = 0x0078,
 241         [TRIMD]         = 0x007c,
 242         [RBWAR]         = 0x00c8,
 243         [RDFAR]         = 0x00cc,
 244         [TBRAR]         = 0x00d4,
 245         [TDFAR]         = 0x00d8,
 246 };
 247
 248 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 249         [ECMR]          = 0x0160,
 250         [ECSR]          = 0x0164,
 251         [ECSIPR]        = 0x0168,
 252         [PIR]           = 0x016c,
 253         [MAHR]          = 0x0170,
 254         [MALR]          = 0x0174,
 255         [RFLR]          = 0x0178,
 256         [PSR]           = 0x017c,
 257         [TROCR]         = 0x0180,
 258         [CDCR]          = 0x0184,
 259         [LCCR]          = 0x0188,
 260         [CNDCR]         = 0x018c,
 261         [CEFCR]         = 0x0194,
 262         [FRECR]         = 0x0198,
 263         [TSFRCR]        = 0x019c,
 264         [TLFRCR]        = 0x01a0,
 265         [RFCR]          = 0x01a4,
 266         [MAFCR]         = 0x01a8,
 267         [IPGR]          = 0x01b4,
 268         [APR]           = 0x01b8,
 269         [MPR]           = 0x01bc,
 270         [TPAUSER]       = 0x01c4,
 271         [BCFR]          = 0x01cc,
 272
 273         [ARSTR]         = 0x0000,
 274         [TSU_CTRST]     = 0x0004,
 275         [TSU_FWEN0]     = 0x0010,
 276         [TSU_FWEN1]     = 0x0014,
 277         [TSU_FCM]       = 0x0018,
 278         [TSU_BSYSL0]    = 0x0020,
 279         [TSU_BSYSL1]    = 0x0024,
 280         [TSU_PRISL0]    = 0x0028,
 281         [TSU_PRISL1]    = 0x002c,
 282         [TSU_FWSL0]     = 0x0030,
 283         [TSU_FWSL1]     = 0x0034,
 284         [TSU_FWSLC]     = 0x0038,
 285         [TSU_QTAGM0]    = 0x0040,
 286         [TSU_QTAGM1]    = 0x0044,
 287         [TSU_ADQT0]     = 0x0048,
 288         [TSU_ADQT1]     = 0x004c,
 289         [TSU_FWSR]      = 0x0050,
 290         [TSU_FWINMK]    = 0x0054,
 291         [TSU_ADSBSY]    = 0x0060,
 292         [TSU_TEN]       = 0x0064,
 293         [TSU_POST1]     = 0x0070,
 294         [TSU_POST2]     = 0x0074,
 295         [TSU_POST3]     = 0x0078,
 296         [TSU_POST4]     = 0x007c,
 297
 298         [TXNLCR0]       = 0x0080,
 299         [TXALCR0]       = 0x0084,
 300         [RXNLCR0]       = 0x0088,
 301         [RXALCR0]       = 0x008c,
 302         [FWNLCR0]       = 0x0090,
 303         [FWALCR0]       = 0x0094,
 304         [TXNLCR1]       = 0x00a0,
 305         [TXALCR1]       = 0x00a0,
 306         [RXNLCR1]       = 0x00a8,
 307         [RXALCR1]       = 0x00ac,
 308         [FWNLCR1]       = 0x00b0,
 309         [FWALCR1]       = 0x00b4,
 310
 311         [TSU_ADRH0]     = 0x0100,
 312         [TSU_ADRL0]     = 0x0104,
 313         [TSU_ADRL31]    = 0x01fc,
 314 };
 315
 316 static int sh_eth_is_gether(struct sh_eth_private *mdp)
 317 {
 318         if (mdp->reg_offset == sh_eth_offset_gigabit)
 319                 return 1;
 320         else
 321                 return 0;
 322 }
 323
 324 static void sh_eth_select_mii(struct net_device *ndev)
 325 {
 326         u32 value = 0x0;
 327         struct sh_eth_private *mdp = netdev_priv(ndev);
 328
 329         switch (mdp->phy_interface) {
 330         case PHY_INTERFACE_MODE_GMII:
 331                 value = 0x2;
 332                 break;
 333         case PHY_INTERFACE_MODE_MII:
 334                 value = 0x1;
 335                 break;
 336         case PHY_INTERFACE_MODE_RMII:
 337                 value = 0x0;
 338                 break;
 339         default:
 340                 pr_warn("PHY interface mode was not setup. Set to MII.\n");
 341                 value = 0x1;
 342                 break;
 343         }
 344
 345         sh_eth_write(ndev, value, RMII_MII);
 346 }
 347
 348 static void sh_eth_set_duplex(struct net_device *ndev)
 349 {
 350         struct sh_eth_private *mdp = netdev_priv(ndev);
 351
 352         if (mdp->duplex) /* Full */
 353                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 354         else            /* Half */
 355                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 356 }
 357
 358 /* There is CPU dependent code */
 359 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 360 {
 361         struct sh_eth_private *mdp = netdev_priv(ndev);
 362
 363         switch (mdp->speed) {
 364         case 10: /* 10BASE */
 365                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 366                 break;
 367         case 100:/* 100BASE */
 368                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 369                 break;
 370         default:
 371                 break;
 372         }
 373 }
 374
 375 /* R8A7778/9 */
 376 static struct sh_eth_cpu_data r8a777x_data = {
 377         .set_duplex     = sh_eth_set_duplex,
 378         .set_rate       = sh_eth_set_rate_r8a777x,
 379
 380         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 381         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 382         .eesipr_value   = 0x01ff009f,
 383
 384         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 385         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 386                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 387                           EESR_ECI,
 388
 389         .apr            = 1,
 390         .mpr            = 1,
 391         .tpauser        = 1,
 392         .hw_swap        = 1,
 393 };
 394
 395 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 396 {
 397         struct sh_eth_private *mdp = netdev_priv(ndev);
 398
 399         switch (mdp->speed) {
 400         case 10: /* 10BASE */
 401                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 402                 break;
 403         case 100:/* 100BASE */
 404                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 405                 break;
 406         default:
 407                 break;
 408         }
 409 }
 410
 411 /* SH7724 */
 412 static struct sh_eth_cpu_data sh7724_data = {
 413         .set_duplex     = sh_eth_set_duplex,
 414         .set_rate       = sh_eth_set_rate_sh7724,
 415
 416         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 417         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 418         .eesipr_value   = 0x01ff009f,
 419
 420         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 421         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 422                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 423                           EESR_ECI,
 424
 425         .apr            = 1,
 426         .mpr            = 1,
 427         .tpauser        = 1,
 428         .hw_swap        = 1,
 429         .rpadir         = 1,
 430         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 431 };
 432
 433 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 434 {
 435         struct sh_eth_private *mdp = netdev_priv(ndev);
 436
 437         switch (mdp->speed) {
 438         case 10: /* 10BASE */
 439                 sh_eth_write(ndev, 0, RTRATE);
 440                 break;
 441         case 100:/* 100BASE */
 442                 sh_eth_write(ndev, 1, RTRATE);
 443                 break;
 444         default:
 445                 break;
 446         }
 447 }
 448
 449 /* SH7757 */
 450 static struct sh_eth_cpu_data sh7757_data = {
 451         .set_duplex     = sh_eth_set_duplex,
 452         .set_rate       = sh_eth_set_rate_sh7757,
 453
 454         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 455         .rmcr_value     = 0x00000001,
 456
 457         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 458         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 459                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 460                           EESR_ECI,
 461
 462         .irq_flags      = IRQF_SHARED,
 463         .apr            = 1,
 464         .mpr            = 1,
 465         .tpauser        = 1,
 466         .hw_swap        = 1,
 467         .no_ade         = 1,
 468         .rpadir         = 1,
 469         .rpadir_value   = 2 << 16,
 470 };
 471
 472 #define SH_GIGA_ETH_BASE        0xfee00000UL
 473 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 474 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 475 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 476 {
 477         int i;
 478         unsigned long mahr[2], malr[2];
 479
 480         /* save MAHR and MALR */
 481         for (i = 0; i < 2; i++) {
 482                 malr[i] = ioread32((void *)GIGA_MALR(i));
 483                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 484         }
 485
 486         /* reset device */
 487         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 488         mdelay(1);
 489
 490         /* restore MAHR and MALR */
 491         for (i = 0; i < 2; i++) {
 492                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 493                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 494         }
 495 }
 496
 497 static void sh_eth_set_rate_giga(struct net_device *ndev)
 498 {
 499         struct sh_eth_private *mdp = netdev_priv(ndev);
 500
 501         switch (mdp->speed) {
 502         case 10: /* 10BASE */
 503                 sh_eth_write(ndev, 0x00000000, GECMR);
 504                 break;
 505         case 100:/* 100BASE */
 506                 sh_eth_write(ndev, 0x00000010, GECMR);
 507                 break;
 508         case 1000: /* 1000BASE */
 509                 sh_eth_write(ndev, 0x00000020, GECMR);
 510                 break;
 511         default:
 512                 break;
 513         }
 514 }
 515
 516 /* SH7757(GETHERC) */
 517 static struct sh_eth_cpu_data sh7757_data_giga = {
 518         .chip_reset     = sh_eth_chip_reset_giga,
 519         .set_duplex     = sh_eth_set_duplex,
 520         .set_rate       = sh_eth_set_rate_giga,
 521
 522         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 523         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 524         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 525
 526         .tx_check       = EESR_TC1 | EESR_FTC,
 527         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 528                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 529                           EESR_TDE | EESR_ECI,
 530         .fdr_value      = 0x0000072f,
 531         .rmcr_value     = 0x00000001,
 532
 533         .irq_flags      = IRQF_SHARED,
 534         .apr            = 1,
 535         .mpr            = 1,
 536         .tpauser        = 1,
 537         .bculr          = 1,
 538         .hw_swap        = 1,
 539         .rpadir         = 1,
 540         .rpadir_value   = 2 << 16,
 541         .no_trimd       = 1,
 542         .no_ade         = 1,
 543         .tsu            = 1,
 544 };
 545
 546 static void sh_eth_chip_reset(struct net_device *ndev)
 547 {
 548         struct sh_eth_private *mdp = netdev_priv(ndev);
 549
 550         /* reset device */
 551         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 552         mdelay(1);
 553 }
 554
 555 static void sh_eth_set_rate_gether(struct net_device *ndev)
 556 {
 557         struct sh_eth_private *mdp = netdev_priv(ndev);
 558
 559         switch (mdp->speed) {
 560         case 10: /* 10BASE */
 561                 sh_eth_write(ndev, GECMR_10, GECMR);
 562                 break;
 563         case 100:/* 100BASE */
 564                 sh_eth_write(ndev, GECMR_100, GECMR);
 565                 break;
 566         case 1000: /* 1000BASE */
 567                 sh_eth_write(ndev, GECMR_1000, GECMR);
 568                 break;
 569         default:
 570                 break;
 571         }
 572 }
 573
 574 /* SH7734 */
 575 static struct sh_eth_cpu_data sh7734_data = {
 576         .chip_reset     = sh_eth_chip_reset,
 577         .set_duplex     = sh_eth_set_duplex,
 578         .set_rate       = sh_eth_set_rate_gether,
 579
 580         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 581         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 582         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 583
 584         .tx_check       = EESR_TC1 | EESR_FTC,
 585         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 586                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 587                           EESR_TDE | EESR_ECI,
 588
 589         .apr            = 1,
 590         .mpr            = 1,
 591         .tpauser        = 1,
 592         .bculr          = 1,
 593         .hw_swap        = 1,
 594         .no_trimd       = 1,
 595         .no_ade         = 1,
 596         .tsu            = 1,
 597         .hw_crc         = 1,
 598         .select_mii     = 1,
 599 };
 600
 601 /* SH7763 */
 602 static struct sh_eth_cpu_data sh7763_data = {
 603         .chip_reset     = sh_eth_chip_reset,
 604         .set_duplex     = sh_eth_set_duplex,
 605         .set_rate       = sh_eth_set_rate_gether,
 606
 607         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 608         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 609         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 610
 611         .tx_check       = EESR_TC1 | EESR_FTC,
 612         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 613                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 614                           EESR_ECI,
 615
 616         .apr            = 1,
 617         .mpr            = 1,
 618         .tpauser        = 1,
 619         .bculr          = 1,
 620         .hw_swap        = 1,
 621         .no_trimd       = 1,
 622         .no_ade         = 1,
 623         .tsu            = 1,
 624         .irq_flags      = IRQF_SHARED,
 625 };
 626
 627 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 628 {
 629         struct sh_eth_private *mdp = netdev_priv(ndev);
 630
 631         /* reset device */
 632         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 633         mdelay(1);
 634
 635         sh_eth_select_mii(ndev);
 636 }
 637
 638 /* R8A7740 */
 639 static struct sh_eth_cpu_data r8a7740_data = {
 640         .chip_reset     = sh_eth_chip_reset_r8a7740,
 641         .set_duplex     = sh_eth_set_duplex,
 642         .set_rate       = sh_eth_set_rate_gether,
 643
 644         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 645         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 646         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 647
 648         .tx_check       = EESR_TC1 | EESR_FTC,
 649         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 650                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 651                           EESR_TDE | EESR_ECI,
 652
 653         .apr            = 1,
 654         .mpr            = 1,
 655         .tpauser        = 1,
 656         .bculr          = 1,
 657         .hw_swap        = 1,
 658         .no_trimd       = 1,
 659         .no_ade         = 1,
 660         .tsu            = 1,
 661         .select_mii     = 1,
 662         .shift_rd0      = 1,
 663 };
 664
 665 static struct sh_eth_cpu_data sh7619_data = {
 666         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 667
 668         .apr            = 1,
 669         .mpr            = 1,
 670         .tpauser        = 1,
 671         .hw_swap        = 1,
 672 };
 673
 674 static struct sh_eth_cpu_data sh771x_data = {
 675         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 676         .tsu            = 1,
 677 };
 678
 679 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 680 {
 681         if (!cd->ecsr_value)
 682                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 683
 684         if (!cd->ecsipr_value)
 685                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 686
 687         if (!cd->fcftr_value)
 688                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
 689                                   DEFAULT_FIFO_F_D_RFD;
 690
 691         if (!cd->fdr_value)
 692                 cd->fdr_value = DEFAULT_FDR_INIT;
 693
 694         if (!cd->rmcr_value)
 695                 cd->rmcr_value = DEFAULT_RMCR_VALUE;
 696
 697         if (!cd->tx_check)
 698                 cd->tx_check = DEFAULT_TX_CHECK;
 699
 700         if (!cd->eesr_err_check)
 701                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 702 }
 703
 704 static int sh_eth_check_reset(struct net_device *ndev)
 705 {
 706         int ret = 0;
 707         int cnt = 100;
 708
 709         while (cnt > 0) {
 710                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 711                         break;
 712                 mdelay(1);
 713                 cnt--;
 714         }
 715         if (cnt <= 0) {
 716                 pr_err("Device reset failed\n");
 717                 ret = -ETIMEDOUT;
 718         }
 719         return ret;
 720 }
 721
 722 static int sh_eth_reset(struct net_device *ndev)
 723 {
 724         struct sh_eth_private *mdp = netdev_priv(ndev);
 725         int ret = 0;
 726
 727         if (sh_eth_is_gether(mdp)) {
 728                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 729                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 730                              EDMR);
 731
 732                 ret = sh_eth_check_reset(ndev);
 733                 if (ret)
 734                         goto out;
 735
 736                 /* Table Init */
 737                 sh_eth_write(ndev, 0x0, TDLAR);
 738                 sh_eth_write(ndev, 0x0, TDFAR);
 739                 sh_eth_write(ndev, 0x0, TDFXR);
 740                 sh_eth_write(ndev, 0x0, TDFFR);
 741                 sh_eth_write(ndev, 0x0, RDLAR);
 742                 sh_eth_write(ndev, 0x0, RDFAR);
 743                 sh_eth_write(ndev, 0x0, RDFXR);
 744                 sh_eth_write(ndev, 0x0, RDFFR);
 745
 746                 /* Reset HW CRC register */
 747                 if (mdp->cd->hw_crc)
 748                         sh_eth_write(ndev, 0x0, CSMR);
 749
 750                 /* Select MII mode */
 751                 if (mdp->cd->select_mii)
 752                         sh_eth_select_mii(ndev);
 753         } else {
 754                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 755                              EDMR);
 756                 mdelay(3);
 757                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 758                              EDMR);
 759         }
 760
 761 out:
 762         return ret;
 763 }
 764
 765 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 766 static void sh_eth_set_receive_align(struct sk_buff *skb)
 767 {
 768         int reserve;
 769
 770         reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
 771         if (reserve)
 772                 skb_reserve(skb, reserve);
 773 }
 774 #else
 775 static void sh_eth_set_receive_align(struct sk_buff *skb)
 776 {
 777         skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
 778 }
 779 #endif
 780
 781
 782 /* CPU <-> EDMAC endian convert */
 783 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 784 {
 785         switch (mdp->edmac_endian) {
 786         case EDMAC_LITTLE_ENDIAN:
 787                 return cpu_to_le32(x);
 788         case EDMAC_BIG_ENDIAN:
 789                 return cpu_to_be32(x);
 790         }
 791         return x;
 792 }
 793
 794 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 795 {
 796         switch (mdp->edmac_endian) {
 797         case EDMAC_LITTLE_ENDIAN:
 798                 return le32_to_cpu(x);
 799         case EDMAC_BIG_ENDIAN:
 800                 return be32_to_cpu(x);
 801         }
 802         return x;
 803 }
 804
 805 /*
 806  * Program the hardware MAC address from dev->dev_addr.
 807  */
 808 static void update_mac_address(struct net_device *ndev)
 809 {
 810         sh_eth_write(ndev,
 811                 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 812                 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 813         sh_eth_write(ndev,
 814                 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 815 }
 816
 817 /*
 818  * Get MAC address from SuperH MAC address register
 819  *
 820  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 821  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 822  * When you want use this device, you must set MAC address in bootloader.
 823  *
 824  */
 825 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 826 {
 827         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 828                 memcpy(ndev->dev_addr, mac, 6);
 829         } else {
 830                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 831                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 832                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 833                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 834                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 835                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 836         }
 837 }
 838
 839 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 840 {
 841         if (sh_eth_is_gether(mdp))
 842                 return EDTRR_TRNS_GETHER;
 843         else
 844                 return EDTRR_TRNS_ETHER;
 845 }
 846
 847 struct bb_info {
 848         void (*set_gate)(void *addr);
 849         struct mdiobb_ctrl ctrl;
 850         void *addr;
 851         u32 mmd_msk;/* MMD */
 852         u32 mdo_msk;
 853         u32 mdi_msk;
 854         u32 mdc_msk;
 855 };
 856
 857 /* PHY bit set */
 858 static void bb_set(void *addr, u32 msk)
 859 {
 860         iowrite32(ioread32(addr) | msk, addr);
 861 }
 862
 863 /* PHY bit clear */
 864 static void bb_clr(void *addr, u32 msk)
 865 {
 866         iowrite32((ioread32(addr) & ~msk), addr);
 867 }
 868
 869 /* PHY bit read */
 870 static int bb_read(void *addr, u32 msk)
 871 {
 872         return (ioread32(addr) & msk) != 0;
 873 }
 874
 875 /* Data I/O pin control */
 876 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
 877 {
 878         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 879
 880         if (bitbang->set_gate)
 881                 bitbang->set_gate(bitbang->addr);
 882
 883         if (bit)
 884                 bb_set(bitbang->addr, bitbang->mmd_msk);
 885         else
 886                 bb_clr(bitbang->addr, bitbang->mmd_msk);
 887 }
 888
 889 /* Set bit data*/
 890 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
 891 {
 892         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 893
 894         if (bitbang->set_gate)
 895                 bitbang->set_gate(bitbang->addr);
 896
 897         if (bit)
 898                 bb_set(bitbang->addr, bitbang->mdo_msk);
 899         else
 900                 bb_clr(bitbang->addr, bitbang->mdo_msk);
 901 }
 902
 903 /* Get bit data*/
 904 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
 905 {
 906         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 907
 908         if (bitbang->set_gate)
 909                 bitbang->set_gate(bitbang->addr);
 910
 911         return bb_read(bitbang->addr, bitbang->mdi_msk);
 912 }
 913
 914 /* MDC pin control */
 915 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
 916 {
 917         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 918
 919         if (bitbang->set_gate)
 920                 bitbang->set_gate(bitbang->addr);
 921
 922         if (bit)
 923                 bb_set(bitbang->addr, bitbang->mdc_msk);
 924         else
 925                 bb_clr(bitbang->addr, bitbang->mdc_msk);
 926 }
 927
 928 /* mdio bus control struct */
 929 static struct mdiobb_ops bb_ops = {
 930         .owner = THIS_MODULE,
 931         .set_mdc = sh_mdc_ctrl,
 932         .set_mdio_dir = sh_mmd_ctrl,
 933         .set_mdio_data = sh_set_mdio,
 934         .get_mdio_data = sh_get_mdio,
 935 };
 936
 937 /* free skb and descriptor buffer */
 938 static void sh_eth_ring_free(struct net_device *ndev)
 939 {
 940         struct sh_eth_private *mdp = netdev_priv(ndev);
 941         int i;
 942
 943         /* Free Rx skb ringbuffer */
 944         if (mdp->rx_skbuff) {
 945                 for (i = 0; i < mdp->num_rx_ring; i++) {
 946                         if (mdp->rx_skbuff[i])
 947                                 dev_kfree_skb(mdp->rx_skbuff[i]);
 948                 }
 949         }
 950         kfree(mdp->rx_skbuff);
 951         mdp->rx_skbuff = NULL;
 952
 953         /* Free Tx skb ringbuffer */
 954         if (mdp->tx_skbuff) {
 955                 for (i = 0; i < mdp->num_tx_ring; i++) {
 956                         if (mdp->tx_skbuff[i])
 957                                 dev_kfree_skb(mdp->tx_skbuff[i]);
 958                 }
 959         }
 960         kfree(mdp->tx_skbuff);
 961         mdp->tx_skbuff = NULL;
 962 }
 963
 964 /* format skb and descriptor buffer */
 965 static void sh_eth_ring_format(struct net_device *ndev)
 966 {
 967         struct sh_eth_private *mdp = netdev_priv(ndev);
 968         int i;
 969         struct sk_buff *skb;
 970         struct sh_eth_rxdesc *rxdesc = NULL;
 971         struct sh_eth_txdesc *txdesc = NULL;
 972         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
 973         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
 974
 975         mdp->cur_rx = mdp->cur_tx = 0;
 976         mdp->dirty_rx = mdp->dirty_tx = 0;
 977
 978         memset(mdp->rx_ring, 0, rx_ringsize);
 979
 980         /* build Rx ring buffer */
 981         for (i = 0; i < mdp->num_rx_ring; i++) {
 982                 /* skb */
 983                 mdp->rx_skbuff[i] = NULL;
 984                 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
 985                 mdp->rx_skbuff[i] = skb;
 986                 if (skb == NULL)
 987                         break;
 988                 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
 989                                 DMA_FROM_DEVICE);
 990                 sh_eth_set_receive_align(skb);
 991
 992                 /* RX descriptor */
 993                 rxdesc = &mdp->rx_ring[i];
 994                 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
 995                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
 996
 997                 /* The size of the buffer is 16 byte boundary. */
 998                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
 999                 /* Rx descriptor address set */
1000                 if (i == 0) {
1001                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1002                         if (sh_eth_is_gether(mdp))
1003                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1004                 }
1005         }
1006
1007         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1008
1009         /* Mark the last entry as wrapping the ring. */
1010         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1011
1012         memset(mdp->tx_ring, 0, tx_ringsize);
1013
1014         /* build Tx ring buffer */
1015         for (i = 0; i < mdp->num_tx_ring; i++) {
1016                 mdp->tx_skbuff[i] = NULL;
1017                 txdesc = &mdp->tx_ring[i];
1018                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1019                 txdesc->buffer_length = 0;
1020                 if (i == 0) {
1021                         /* Tx descriptor address set */
1022                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1023                         if (sh_eth_is_gether(mdp))
1024                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1025                 }
1026         }
1027
1028         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1029 }
1030
1031 /* Get skb and descriptor buffer */
1032 static int sh_eth_ring_init(struct net_device *ndev)
1033 {
1034         struct sh_eth_private *mdp = netdev_priv(ndev);
1035         int rx_ringsize, tx_ringsize, ret = 0;
1036
1037         /*
1038          * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1039          * card needs room to do 8 byte alignment, +2 so we can reserve
1040          * the first 2 bytes, and +16 gets room for the status word from the
1041          * card.
1042          */
1043         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1044                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1045         if (mdp->cd->rpadir)
1046                 mdp->rx_buf_sz += NET_IP_ALIGN;
1047
1048         /* Allocate RX and TX skb rings */
1049         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1050                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1051         if (!mdp->rx_skbuff) {
1052                 ret = -ENOMEM;
1053                 return ret;
1054         }
1055
1056         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1057                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1058         if (!mdp->tx_skbuff) {
1059                 ret = -ENOMEM;
1060                 goto skb_ring_free;
1061         }
1062
1063         /* Allocate all Rx descriptors. */
1064         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1065         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1066                                           GFP_KERNEL);
1067         if (!mdp->rx_ring) {
1068                 ret = -ENOMEM;
1069                 goto desc_ring_free;
1070         }
1071
1072         mdp->dirty_rx = 0;
1073
1074         /* Allocate all Tx descriptors. */
1075         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1076         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1077                                           GFP_KERNEL);
1078         if (!mdp->tx_ring) {
1079                 ret = -ENOMEM;
1080                 goto desc_ring_free;
1081         }
1082         return ret;
1083
1084 desc_ring_free:
1085         /* free DMA buffer */
1086         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1087
1088 skb_ring_free:
1089         /* Free Rx and Tx skb ring buffer */
1090         sh_eth_ring_free(ndev);
1091         mdp->tx_ring = NULL;
1092         mdp->rx_ring = NULL;
1093
1094         return ret;
1095 }
1096
1097 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1098 {
1099         int ringsize;
1100
1101         if (mdp->rx_ring) {
1102                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1103                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1104                                   mdp->rx_desc_dma);
1105                 mdp->rx_ring = NULL;
1106         }
1107
1108         if (mdp->tx_ring) {
1109                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1110                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1111                                   mdp->tx_desc_dma);
1112                 mdp->tx_ring = NULL;
1113         }
1114 }
1115
1116 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1117 {
1118         int ret = 0;
1119         struct sh_eth_private *mdp = netdev_priv(ndev);
1120         u32 val;
1121
1122         /* Soft Reset */
1123         ret = sh_eth_reset(ndev);
1124         if (ret)
1125                 goto out;
1126
1127         /* Descriptor format */
1128         sh_eth_ring_format(ndev);
1129         if (mdp->cd->rpadir)
1130                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1131
1132         /* all sh_eth int mask */
1133         sh_eth_write(ndev, 0, EESIPR);
1134
1135 #if defined(__LITTLE_ENDIAN)
1136         if (mdp->cd->hw_swap)
1137                 sh_eth_write(ndev, EDMR_EL, EDMR);
1138         else
1139 #endif
1140                 sh_eth_write(ndev, 0, EDMR);
1141
1142         /* FIFO size set */
1143         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1144         sh_eth_write(ndev, 0, TFTR);
1145
1146         /* Frame recv control */
1147         sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
1148
1149         sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1150
1151         if (mdp->cd->bculr)
1152                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1153
1154         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1155
1156         if (!mdp->cd->no_trimd)
1157                 sh_eth_write(ndev, 0, TRIMD);
1158
1159         /* Recv frame limit set register */
1160         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1161                      RFLR);
1162
1163         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1164         if (start)
1165                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1166
1167         /* PAUSE Prohibition */
1168         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1169                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1170
1171         sh_eth_write(ndev, val, ECMR);
1172
1173         if (mdp->cd->set_rate)
1174                 mdp->cd->set_rate(ndev);
1175
1176         /* E-MAC Status Register clear */
1177         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1178
1179         /* E-MAC Interrupt Enable register */
1180         if (start)
1181                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1182
1183         /* Set MAC address */
1184         update_mac_address(ndev);
1185
1186         /* mask reset */
1187         if (mdp->cd->apr)
1188                 sh_eth_write(ndev, APR_AP, APR);
1189         if (mdp->cd->mpr)
1190                 sh_eth_write(ndev, MPR_MP, MPR);
1191         if (mdp->cd->tpauser)
1192                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1193
1194         if (start) {
1195                 /* Setting the Rx mode will start the Rx process. */
1196                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1197
1198                 netif_start_queue(ndev);
1199         }
1200
1201 out:
1202         return ret;
1203 }
1204
1205 /* free Tx skb function */
1206 static int sh_eth_txfree(struct net_device *ndev)
1207 {
1208         struct sh_eth_private *mdp = netdev_priv(ndev);
1209         struct sh_eth_txdesc *txdesc;
1210         int freeNum = 0;
1211         int entry = 0;
1212
1213         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1214                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1215                 txdesc = &mdp->tx_ring[entry];
1216                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1217                         break;
1218                 /* Free the original skb. */
1219                 if (mdp->tx_skbuff[entry]) {
1220                         dma_unmap_single(&ndev->dev, txdesc->addr,
1221                                          txdesc->buffer_length, DMA_TO_DEVICE);
1222                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1223                         mdp->tx_skbuff[entry] = NULL;
1224                         freeNum++;
1225                 }
1226                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1227                 if (entry >= mdp->num_tx_ring - 1)
1228                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1229
1230                 ndev->stats.tx_packets++;
1231                 ndev->stats.tx_bytes += txdesc->buffer_length;
1232         }
1233         return freeNum;
1234 }
1235
1236 /* Packet receive function */
1237 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1238 {
1239         struct sh_eth_private *mdp = netdev_priv(ndev);
1240         struct sh_eth_rxdesc *rxdesc;
1241
1242         int entry = mdp->cur_rx % mdp->num_rx_ring;
1243         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1244         struct sk_buff *skb;
1245         int exceeded = 0;
1246         u16 pkt_len = 0;
1247         u32 desc_status;
1248
1249         rxdesc = &mdp->rx_ring[entry];
1250         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1251                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1252                 pkt_len = rxdesc->frame_length;
1253
1254                 if (--boguscnt < 0)
1255                         break;
1256
1257                 if (*quota <= 0) {
1258                         exceeded = 1;
1259                         break;
1260                 }
1261                 (*quota)--;
1262
1263                 if (!(desc_status & RDFEND))
1264                         ndev->stats.rx_length_errors++;
1265
1266                 /*
1267                  * In case of almost all GETHER/ETHERs, the Receive Frame State
1268                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1269                  * bit 0. However, in case of the R8A7740's GETHER, the RFS
1270                  * bits are from bit 25 to bit 16. So, the driver needs right
1271                  * shifting by 16.
1272                  */
1273                 if (mdp->cd->shift_rd0)
1274                         desc_status >>= 16;
1275
1276                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1277                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1278                         ndev->stats.rx_errors++;
1279                         if (desc_status & RD_RFS1)
1280                                 ndev->stats.rx_crc_errors++;
1281                         if (desc_status & RD_RFS2)
1282                                 ndev->stats.rx_frame_errors++;
1283                         if (desc_status & RD_RFS3)
1284                                 ndev->stats.rx_length_errors++;
1285                         if (desc_status & RD_RFS4)
1286                                 ndev->stats.rx_length_errors++;
1287                         if (desc_status & RD_RFS6)
1288                                 ndev->stats.rx_missed_errors++;
1289                         if (desc_status & RD_RFS10)
1290                                 ndev->stats.rx_over_errors++;
1291                 } else {
1292                         if (!mdp->cd->hw_swap)
1293                                 sh_eth_soft_swap(
1294                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1295                                         pkt_len + 2);
1296                         skb = mdp->rx_skbuff[entry];
1297                         mdp->rx_skbuff[entry] = NULL;
1298                         if (mdp->cd->rpadir)
1299                                 skb_reserve(skb, NET_IP_ALIGN);
1300                         skb_put(skb, pkt_len);
1301                         skb->protocol = eth_type_trans(skb, ndev);
1302                         netif_rx(skb);
1303                         ndev->stats.rx_packets++;
1304                         ndev->stats.rx_bytes += pkt_len;
1305                 }
1306                 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1307                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1308                 rxdesc = &mdp->rx_ring[entry];
1309         }
1310
1311         /* Refill the Rx ring buffers. */
1312         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1313                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1314                 rxdesc = &mdp->rx_ring[entry];
1315                 /* The size of the buffer is 16 byte boundary. */
1316                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1317
1318                 if (mdp->rx_skbuff[entry] == NULL) {
1319                         skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1320                         mdp->rx_skbuff[entry] = skb;
1321                         if (skb == NULL)
1322                                 break;  /* Better luck next round. */
1323                         dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1324                                         DMA_FROM_DEVICE);
1325                         sh_eth_set_receive_align(skb);
1326
1327                         skb_checksum_none_assert(skb);
1328                         rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1329                 }
1330                 if (entry >= mdp->num_rx_ring - 1)
1331                         rxdesc->status |=
1332                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1333                 else
1334                         rxdesc->status |=
1335                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1336         }
1337
1338         /* Restart Rx engine if stopped. */
1339         /* If we don't need to check status, don't. -KDU */
1340         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1341                 /* fix the values for the next receiving if RDE is set */
1342                 if (intr_status & EESR_RDE)
1343                         mdp->cur_rx = mdp->dirty_rx =
1344                                 (sh_eth_read(ndev, RDFAR) -
1345                                  sh_eth_read(ndev, RDLAR)) >> 4;
1346                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1347         }
1348
1349         return exceeded;
1350 }
1351
1352 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1353 {
1354         /* disable tx and rx */
1355         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1356                 ~(ECMR_RE | ECMR_TE), ECMR);
1357 }
1358
1359 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1360 {
1361         /* enable tx and rx */
1362         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1363                 (ECMR_RE | ECMR_TE), ECMR);
1364 }
1365
1366 /* error control function */
1367 static void sh_eth_error(struct net_device *ndev, int intr_status)
1368 {
1369         struct sh_eth_private *mdp = netdev_priv(ndev);
1370         u32 felic_stat;
1371         u32 link_stat;
1372         u32 mask;
1373
1374         if (intr_status & EESR_ECI) {
1375                 felic_stat = sh_eth_read(ndev, ECSR);
1376                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1377                 if (felic_stat & ECSR_ICD)
1378                         ndev->stats.tx_carrier_errors++;
1379                 if (felic_stat & ECSR_LCHNG) {
1380                         /* Link Changed */
1381                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1382                                 goto ignore_link;
1383                         } else {
1384                                 link_stat = (sh_eth_read(ndev, PSR));
1385                                 if (mdp->ether_link_active_low)
1386                                         link_stat = ~link_stat;
1387                         }
1388                         if (!(link_stat & PHY_ST_LINK))
1389                                 sh_eth_rcv_snd_disable(ndev);
1390                         else {
1391                                 /* Link Up */
1392                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1393                                           ~DMAC_M_ECI, EESIPR);
1394                                 /*clear int */
1395                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1396                                           ECSR);
1397                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1398                                           DMAC_M_ECI, EESIPR);
1399                                 /* enable tx and rx */
1400                                 sh_eth_rcv_snd_enable(ndev);
1401                         }
1402                 }
1403         }
1404
1405 ignore_link:
1406         if (intr_status & EESR_TWB) {
1407                 /* Unused write back interrupt */
1408                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1409                         ndev->stats.tx_aborted_errors++;
1410                         if (netif_msg_tx_err(mdp))
1411                                 dev_err(&ndev->dev, "Transmit Abort\n");
1412                 }
1413         }
1414
1415         if (intr_status & EESR_RABT) {
1416                 /* Receive Abort int */
1417                 if (intr_status & EESR_RFRMER) {
1418                         /* Receive Frame Overflow int */
1419                         ndev->stats.rx_frame_errors++;
1420                         if (netif_msg_rx_err(mdp))
1421                                 dev_err(&ndev->dev, "Receive Abort\n");
1422                 }
1423         }
1424
1425         if (intr_status & EESR_TDE) {
1426                 /* Transmit Descriptor Empty int */
1427                 ndev->stats.tx_fifo_errors++;
1428                 if (netif_msg_tx_err(mdp))
1429                         dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1430         }
1431
1432         if (intr_status & EESR_TFE) {
1433                 /* FIFO under flow */
1434                 ndev->stats.tx_fifo_errors++;
1435                 if (netif_msg_tx_err(mdp))
1436                         dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1437         }
1438
1439         if (intr_status & EESR_RDE) {
1440                 /* Receive Descriptor Empty int */
1441                 ndev->stats.rx_over_errors++;
1442
1443                 if (netif_msg_rx_err(mdp))
1444                         dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1445         }
1446
1447         if (intr_status & EESR_RFE) {
1448                 /* Receive FIFO Overflow int */
1449                 ndev->stats.rx_fifo_errors++;
1450                 if (netif_msg_rx_err(mdp))
1451                         dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1452         }
1453
1454         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1455                 /* Address Error */
1456                 ndev->stats.tx_fifo_errors++;
1457                 if (netif_msg_tx_err(mdp))
1458                         dev_err(&ndev->dev, "Address Error\n");
1459         }
1460
1461         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1462         if (mdp->cd->no_ade)
1463                 mask &= ~EESR_ADE;
1464         if (intr_status & mask) {
1465                 /* Tx error */
1466                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1467                 /* dmesg */
1468                 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1469                                 intr_status, mdp->cur_tx);
1470                 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1471                                 mdp->dirty_tx, (u32) ndev->state, edtrr);
1472                 /* dirty buffer free */
1473                 sh_eth_txfree(ndev);
1474
1475                 /* SH7712 BUG */
1476                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1477                         /* tx dma start */
1478                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1479                 }
1480                 /* wakeup */
1481                 netif_wake_queue(ndev);
1482         }
1483 }
1484
1485 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1486 {
1487         struct net_device *ndev = netdev;
1488         struct sh_eth_private *mdp = netdev_priv(ndev);
1489         struct sh_eth_cpu_data *cd = mdp->cd;
1490         irqreturn_t ret = IRQ_NONE;
1491         unsigned long intr_status, intr_enable;
1492
1493         spin_lock(&mdp->lock);
1494
1495         /* Get interrupt status */
1496         intr_status = sh_eth_read(ndev, EESR);
1497         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1498          * enabled since it's the one that  comes thru regardless of the mask,
1499          * and we need to fully handle it in sh_eth_error() in order to quench
1500          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1501          */
1502         intr_enable = sh_eth_read(ndev, EESIPR);
1503         intr_status &= intr_enable | DMAC_M_ECI;
1504         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1505                 ret = IRQ_HANDLED;
1506         else
1507                 goto other_irq;
1508
1509         if (intr_status & EESR_RX_CHECK) {
1510                 if (napi_schedule_prep(&mdp->napi)) {
1511                         /* Mask Rx interrupts */
1512                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1513                                      EESIPR);
1514                         __napi_schedule(&mdp->napi);
1515                 } else {
1516                         dev_warn(&ndev->dev,
1517                                  "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1518                                  intr_status, intr_enable);
1519                 }
1520         }
1521
1522         /* Tx Check */
1523         if (intr_status & cd->tx_check) {
1524                 /* Clear Tx interrupts */
1525                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1526
1527                 sh_eth_txfree(ndev);
1528                 netif_wake_queue(ndev);
1529         }
1530
1531         if (intr_status & cd->eesr_err_check) {
1532                 /* Clear error interrupts */
1533                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1534
1535                 sh_eth_error(ndev, intr_status);
1536         }
1537
1538 other_irq:
1539         spin_unlock(&mdp->lock);
1540
1541         return ret;
1542 }
1543
1544 static int sh_eth_poll(struct napi_struct *napi, int budget)
1545 {
1546         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1547                                                   napi);
1548         struct net_device *ndev = napi->dev;
1549         int quota = budget;
1550         unsigned long intr_status;
1551
1552         for (;;) {
1553                 intr_status = sh_eth_read(ndev, EESR);
1554                 if (!(intr_status & EESR_RX_CHECK))
1555                         break;
1556                 /* Clear Rx interrupts */
1557                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1558
1559                 if (sh_eth_rx(ndev, intr_status, &quota))
1560                         goto out;
1561         }
1562
1563         napi_complete(napi);
1564
1565         /* Reenable Rx interrupts */
1566         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1567 out:
1568         return budget - quota;
1569 }
1570
1571 /* PHY state control function */
1572 static void sh_eth_adjust_link(struct net_device *ndev)
1573 {
1574         struct sh_eth_private *mdp = netdev_priv(ndev);
1575         struct phy_device *phydev = mdp->phydev;
1576         int new_state = 0;
1577
1578         if (phydev->link) {
1579                 if (phydev->duplex != mdp->duplex) {
1580                         new_state = 1;
1581                         mdp->duplex = phydev->duplex;
1582                         if (mdp->cd->set_duplex)
1583                                 mdp->cd->set_duplex(ndev);
1584                 }
1585
1586                 if (phydev->speed != mdp->speed) {
1587                         new_state = 1;
1588                         mdp->speed = phydev->speed;
1589                         if (mdp->cd->set_rate)
1590                                 mdp->cd->set_rate(ndev);
1591                 }
1592                 if (!mdp->link) {
1593                         sh_eth_write(ndev,
1594                                 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1595                         new_state = 1;
1596                         mdp->link = phydev->link;
1597                         if (mdp->cd->no_psr || mdp->no_ether_link)
1598                                 sh_eth_rcv_snd_enable(ndev);
1599                 }
1600         } else if (mdp->link) {
1601                 new_state = 1;
1602                 mdp->link = 0;
1603                 mdp->speed = 0;
1604                 mdp->duplex = -1;
1605                 if (mdp->cd->no_psr || mdp->no_ether_link)
1606                         sh_eth_rcv_snd_disable(ndev);
1607         }
1608
1609         if (new_state && netif_msg_link(mdp))
1610                 phy_print_status(phydev);
1611 }
1612
1613 /* PHY init function */
1614 static int sh_eth_phy_init(struct net_device *ndev)
1615 {
1616         struct sh_eth_private *mdp = netdev_priv(ndev);
1617         char phy_id[MII_BUS_ID_SIZE + 3];
1618         struct phy_device *phydev = NULL;
1619
1620         snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1621                 mdp->mii_bus->id , mdp->phy_id);
1622
1623         mdp->link = 0;
1624         mdp->speed = 0;
1625         mdp->duplex = -1;
1626
1627         /* Try connect to PHY */
1628         phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1629                              mdp->phy_interface);
1630         if (IS_ERR(phydev)) {
1631                 dev_err(&ndev->dev, "phy_connect failed\n");
1632                 return PTR_ERR(phydev);
1633         }
1634
1635         dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1636                 phydev->addr, phydev->drv->name);
1637
1638         mdp->phydev = phydev;
1639
1640         return 0;
1641 }
1642
1643 /* PHY control start function */
1644 static int sh_eth_phy_start(struct net_device *ndev)
1645 {
1646         struct sh_eth_private *mdp = netdev_priv(ndev);
1647         int ret;
1648
1649         ret = sh_eth_phy_init(ndev);
1650         if (ret)
1651                 return ret;
1652
1653         /* reset phy - this also wakes it from PDOWN */
1654         phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1655         phy_start(mdp->phydev);
1656
1657         return 0;
1658 }
1659
1660 static int sh_eth_get_settings(struct net_device *ndev,
1661                         struct ethtool_cmd *ecmd)
1662 {
1663         struct sh_eth_private *mdp = netdev_priv(ndev);
1664         unsigned long flags;
1665         int ret;
1666
1667         spin_lock_irqsave(&mdp->lock, flags);
1668         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1669         spin_unlock_irqrestore(&mdp->lock, flags);
1670
1671         return ret;
1672 }
1673
1674 static int sh_eth_set_settings(struct net_device *ndev,
1675                 struct ethtool_cmd *ecmd)
1676 {
1677         struct sh_eth_private *mdp = netdev_priv(ndev);
1678         unsigned long flags;
1679         int ret;
1680
1681         spin_lock_irqsave(&mdp->lock, flags);
1682
1683         /* disable tx and rx */
1684         sh_eth_rcv_snd_disable(ndev);
1685
1686         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1687         if (ret)
1688                 goto error_exit;
1689
1690         if (ecmd->duplex == DUPLEX_FULL)
1691                 mdp->duplex = 1;
1692         else
1693                 mdp->duplex = 0;
1694
1695         if (mdp->cd->set_duplex)
1696                 mdp->cd->set_duplex(ndev);
1697
1698 error_exit:
1699         mdelay(1);
1700
1701         /* enable tx and rx */
1702         sh_eth_rcv_snd_enable(ndev);
1703
1704         spin_unlock_irqrestore(&mdp->lock, flags);
1705
1706         return ret;
1707 }
1708
1709 static int sh_eth_nway_reset(struct net_device *ndev)
1710 {
1711         struct sh_eth_private *mdp = netdev_priv(ndev);
1712         unsigned long flags;
1713         int ret;
1714
1715         spin_lock_irqsave(&mdp->lock, flags);
1716         ret = phy_start_aneg(mdp->phydev);
1717         spin_unlock_irqrestore(&mdp->lock, flags);
1718
1719         return ret;
1720 }
1721
1722 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1723 {
1724         struct sh_eth_private *mdp = netdev_priv(ndev);
1725         return mdp->msg_enable;
1726 }
1727
1728 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1729 {
1730         struct sh_eth_private *mdp = netdev_priv(ndev);
1731         mdp->msg_enable = value;
1732 }
1733
1734 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1735         "rx_current", "tx_current",
1736         "rx_dirty", "tx_dirty",
1737 };
1738 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1739
1740 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1741 {
1742         switch (sset) {
1743         case ETH_SS_STATS:
1744                 return SH_ETH_STATS_LEN;
1745         default:
1746                 return -EOPNOTSUPP;
1747         }
1748 }
1749
1750 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1751                         struct ethtool_stats *stats, u64 *data)
1752 {
1753         struct sh_eth_private *mdp = netdev_priv(ndev);
1754         int i = 0;
1755
1756         /* device-specific stats */
1757         data[i++] = mdp->cur_rx;
1758         data[i++] = mdp->cur_tx;
1759         data[i++] = mdp->dirty_rx;
1760         data[i++] = mdp->dirty_tx;
1761 }
1762
1763 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1764 {
1765         switch (stringset) {
1766         case ETH_SS_STATS:
1767                 memcpy(data, *sh_eth_gstrings_stats,
1768                                         sizeof(sh_eth_gstrings_stats));
1769                 break;
1770         }
1771 }
1772
1773 static void sh_eth_get_ringparam(struct net_device *ndev,
1774                                  struct ethtool_ringparam *ring)
1775 {
1776         struct sh_eth_private *mdp = netdev_priv(ndev);
1777
1778         ring->rx_max_pending = RX_RING_MAX;
1779         ring->tx_max_pending = TX_RING_MAX;
1780         ring->rx_pending = mdp->num_rx_ring;
1781         ring->tx_pending = mdp->num_tx_ring;
1782 }
1783
1784 static int sh_eth_set_ringparam(struct net_device *ndev,
1785                                 struct ethtool_ringparam *ring)
1786 {
1787         struct sh_eth_private *mdp = netdev_priv(ndev);
1788         int ret;
1789
1790         if (ring->tx_pending > TX_RING_MAX ||
1791             ring->rx_pending > RX_RING_MAX ||
1792             ring->tx_pending < TX_RING_MIN ||
1793             ring->rx_pending < RX_RING_MIN)
1794                 return -EINVAL;
1795         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1796                 return -EINVAL;
1797
1798         if (netif_running(ndev)) {
1799                 netif_tx_disable(ndev);
1800                 /* Disable interrupts by clearing the interrupt mask. */
1801                 sh_eth_write(ndev, 0x0000, EESIPR);
1802                 /* Stop the chip's Tx and Rx processes. */
1803                 sh_eth_write(ndev, 0, EDTRR);
1804                 sh_eth_write(ndev, 0, EDRRR);
1805                 synchronize_irq(ndev->irq);
1806         }
1807
1808         /* Free all the skbuffs in the Rx queue. */
1809         sh_eth_ring_free(ndev);
1810         /* Free DMA buffer */
1811         sh_eth_free_dma_buffer(mdp);
1812
1813         /* Set new parameters */
1814         mdp->num_rx_ring = ring->rx_pending;
1815         mdp->num_tx_ring = ring->tx_pending;
1816
1817         ret = sh_eth_ring_init(ndev);
1818         if (ret < 0) {
1819                 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1820                 return ret;
1821         }
1822         ret = sh_eth_dev_init(ndev, false);
1823         if (ret < 0) {
1824                 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1825                 return ret;
1826         }
1827
1828         if (netif_running(ndev)) {
1829                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1830                 /* Setting the Rx mode will start the Rx process. */
1831                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1832                 netif_wake_queue(ndev);
1833         }
1834
1835         return 0;
1836 }
1837
1838 static const struct ethtool_ops sh_eth_ethtool_ops = {
1839         .get_settings   = sh_eth_get_settings,
1840         .set_settings   = sh_eth_set_settings,
1841         .nway_reset     = sh_eth_nway_reset,
1842         .get_msglevel   = sh_eth_get_msglevel,
1843         .set_msglevel   = sh_eth_set_msglevel,
1844         .get_link       = ethtool_op_get_link,
1845         .get_strings    = sh_eth_get_strings,
1846         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
1847         .get_sset_count     = sh_eth_get_sset_count,
1848         .get_ringparam  = sh_eth_get_ringparam,
1849         .set_ringparam  = sh_eth_set_ringparam,
1850 };
1851
1852 /* network device open function */
1853 static int sh_eth_open(struct net_device *ndev)
1854 {
1855         int ret = 0;
1856         struct sh_eth_private *mdp = netdev_priv(ndev);
1857
1858         pm_runtime_get_sync(&mdp->pdev->dev);
1859
1860         ret = request_irq(ndev->irq, sh_eth_interrupt,
1861                           mdp->cd->irq_flags, ndev->name, ndev);
1862         if (ret) {
1863                 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1864                 return ret;
1865         }
1866
1867         /* Descriptor set */
1868         ret = sh_eth_ring_init(ndev);
1869         if (ret)
1870                 goto out_free_irq;
1871
1872         /* device init */
1873         ret = sh_eth_dev_init(ndev, true);
1874         if (ret)
1875                 goto out_free_irq;
1876
1877         /* PHY control start*/
1878         ret = sh_eth_phy_start(ndev);
1879         if (ret)
1880                 goto out_free_irq;
1881
1882         napi_enable(&mdp->napi);
1883
1884         return ret;
1885
1886 out_free_irq:
1887         free_irq(ndev->irq, ndev);
1888         pm_runtime_put_sync(&mdp->pdev->dev);
1889         return ret;
1890 }
1891
1892 /* Timeout function */
1893 static void sh_eth_tx_timeout(struct net_device *ndev)
1894 {
1895         struct sh_eth_private *mdp = netdev_priv(ndev);
1896         struct sh_eth_rxdesc *rxdesc;
1897         int i;
1898
1899         netif_stop_queue(ndev);
1900
1901         if (netif_msg_timer(mdp))
1902                 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1903                " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1904
1905         /* tx_errors count up */
1906         ndev->stats.tx_errors++;
1907
1908         /* Free all the skbuffs in the Rx queue. */
1909         for (i = 0; i < mdp->num_rx_ring; i++) {
1910                 rxdesc = &mdp->rx_ring[i];
1911                 rxdesc->status = 0;
1912                 rxdesc->addr = 0xBADF00D0;
1913                 if (mdp->rx_skbuff[i])
1914                         dev_kfree_skb(mdp->rx_skbuff[i]);
1915                 mdp->rx_skbuff[i] = NULL;
1916         }
1917         for (i = 0; i < mdp->num_tx_ring; i++) {
1918                 if (mdp->tx_skbuff[i])
1919                         dev_kfree_skb(mdp->tx_skbuff[i]);
1920                 mdp->tx_skbuff[i] = NULL;
1921         }
1922
1923         /* device init */
1924         sh_eth_dev_init(ndev, true);
1925 }
1926
1927 /* Packet transmit function */
1928 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1929 {
1930         struct sh_eth_private *mdp = netdev_priv(ndev);
1931         struct sh_eth_txdesc *txdesc;
1932         u32 entry;
1933         unsigned long flags;
1934
1935         spin_lock_irqsave(&mdp->lock, flags);
1936         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1937                 if (!sh_eth_txfree(ndev)) {
1938                         if (netif_msg_tx_queued(mdp))
1939                                 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1940                         netif_stop_queue(ndev);
1941                         spin_unlock_irqrestore(&mdp->lock, flags);
1942                         return NETDEV_TX_BUSY;
1943                 }
1944         }
1945         spin_unlock_irqrestore(&mdp->lock, flags);
1946
1947         entry = mdp->cur_tx % mdp->num_tx_ring;
1948         mdp->tx_skbuff[entry] = skb;
1949         txdesc = &mdp->tx_ring[entry];
1950         /* soft swap. */
1951         if (!mdp->cd->hw_swap)
1952                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1953                                  skb->len + 2);
1954         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1955                                       DMA_TO_DEVICE);
1956         if (skb->len < ETHERSMALL)
1957                 txdesc->buffer_length = ETHERSMALL;
1958         else
1959                 txdesc->buffer_length = skb->len;
1960
1961         if (entry >= mdp->num_tx_ring - 1)
1962                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1963         else
1964                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1965
1966         mdp->cur_tx++;
1967
1968         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1969                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1970
1971         return NETDEV_TX_OK;
1972 }
1973
1974 /* device close function */
1975 static int sh_eth_close(struct net_device *ndev)
1976 {
1977         struct sh_eth_private *mdp = netdev_priv(ndev);
1978
1979         napi_disable(&mdp->napi);
1980
1981         netif_stop_queue(ndev);
1982
1983         /* Disable interrupts by clearing the interrupt mask. */
1984         sh_eth_write(ndev, 0x0000, EESIPR);
1985
1986         /* Stop the chip's Tx and Rx processes. */
1987         sh_eth_write(ndev, 0, EDTRR);
1988         sh_eth_write(ndev, 0, EDRRR);
1989
1990         /* PHY Disconnect */
1991         if (mdp->phydev) {
1992                 phy_stop(mdp->phydev);
1993                 phy_disconnect(mdp->phydev);
1994         }
1995
1996         free_irq(ndev->irq, ndev);
1997
1998         /* Free all the skbuffs in the Rx queue. */
1999         sh_eth_ring_free(ndev);
2000
2001         /* free DMA buffer */
2002         sh_eth_free_dma_buffer(mdp);
2003
2004         pm_runtime_put_sync(&mdp->pdev->dev);
2005
2006         return 0;
2007 }
2008
2009 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2010 {
2011         struct sh_eth_private *mdp = netdev_priv(ndev);
2012
2013         pm_runtime_get_sync(&mdp->pdev->dev);
2014
2015         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2016         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
2017         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2018         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
2019         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2020         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
2021         if (sh_eth_is_gether(mdp)) {
2022                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2023                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
2024                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2025                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
2026         } else {
2027                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2028                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
2029         }
2030         pm_runtime_put_sync(&mdp->pdev->dev);
2031
2032         return &ndev->stats;
2033 }
2034
2035 /* ioctl to device function */
2036 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
2037                                 int cmd)
2038 {
2039         struct sh_eth_private *mdp = netdev_priv(ndev);
2040         struct phy_device *phydev = mdp->phydev;
2041
2042         if (!netif_running(ndev))
2043                 return -EINVAL;
2044
2045         if (!phydev)
2046                 return -ENODEV;
2047
2048         return phy_mii_ioctl(phydev, rq, cmd);
2049 }
2050
2051 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2052 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2053                                             int entry)
2054 {
2055         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2056 }
2057
2058 static u32 sh_eth_tsu_get_post_mask(int entry)
2059 {
2060         return 0x0f << (28 - ((entry % 8) * 4));
2061 }
2062
2063 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2064 {
2065         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2066 }
2067
2068 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2069                                              int entry)
2070 {
2071         struct sh_eth_private *mdp = netdev_priv(ndev);
2072         u32 tmp;
2073         void *reg_offset;
2074
2075         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2076         tmp = ioread32(reg_offset);
2077         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2078 }
2079
2080 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2081                                               int entry)
2082 {
2083         struct sh_eth_private *mdp = netdev_priv(ndev);
2084         u32 post_mask, ref_mask, tmp;
2085         void *reg_offset;
2086
2087         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2088         post_mask = sh_eth_tsu_get_post_mask(entry);
2089         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2090
2091         tmp = ioread32(reg_offset);
2092         iowrite32(tmp & ~post_mask, reg_offset);
2093
2094         /* If other port enables, the function returns "true" */
2095         return tmp & ref_mask;
2096 }
2097
2098 static int sh_eth_tsu_busy(struct net_device *ndev)
2099 {
2100         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2101         struct sh_eth_private *mdp = netdev_priv(ndev);
2102
2103         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2104                 udelay(10);
2105                 timeout--;
2106                 if (timeout <= 0) {
2107                         dev_err(&ndev->dev, "%s: timeout\n", __func__);
2108                         return -ETIMEDOUT;
2109                 }
2110         }
2111
2112         return 0;
2113 }
2114
2115 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2116                                   const u8 *addr)
2117 {
2118         u32 val;
2119
2120         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2121         iowrite32(val, reg);
2122         if (sh_eth_tsu_busy(ndev) < 0)
2123                 return -EBUSY;
2124
2125         val = addr[4] << 8 | addr[5];
2126         iowrite32(val, reg + 4);
2127         if (sh_eth_tsu_busy(ndev) < 0)
2128                 return -EBUSY;
2129
2130         return 0;
2131 }
2132
2133 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2134 {
2135         u32 val;
2136
2137         val = ioread32(reg);
2138         addr[0] = (val >> 24) & 0xff;
2139         addr[1] = (val >> 16) & 0xff;
2140         addr[2] = (val >> 8) & 0xff;
2141         addr[3] = val & 0xff;
2142         val = ioread32(reg + 4);
2143         addr[4] = (val >> 8) & 0xff;
2144         addr[5] = val & 0xff;
2145 }
2146
2147
2148 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2149 {
2150         struct sh_eth_private *mdp = netdev_priv(ndev);
2151         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2152         int i;
2153         u8 c_addr[ETH_ALEN];
2154
2155         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2156                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2157                 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2158                         return i;
2159         }
2160
2161         return -ENOENT;
2162 }
2163
2164 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2165 {
2166         u8 blank[ETH_ALEN];
2167         int entry;
2168
2169         memset(blank, 0, sizeof(blank));
2170         entry = sh_eth_tsu_find_entry(ndev, blank);
2171         return (entry < 0) ? -ENOMEM : entry;
2172 }
2173
2174 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2175                                               int entry)
2176 {
2177         struct sh_eth_private *mdp = netdev_priv(ndev);
2178         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2179         int ret;
2180         u8 blank[ETH_ALEN];
2181
2182         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2183                          ~(1 << (31 - entry)), TSU_TEN);
2184
2185         memset(blank, 0, sizeof(blank));
2186         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2187         if (ret < 0)
2188                 return ret;
2189         return 0;
2190 }
2191
2192 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2193 {
2194         struct sh_eth_private *mdp = netdev_priv(ndev);
2195         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2196         int i, ret;
2197
2198         if (!mdp->cd->tsu)
2199                 return 0;
2200
2201         i = sh_eth_tsu_find_entry(ndev, addr);
2202         if (i < 0) {
2203                 /* No entry found, create one */
2204                 i = sh_eth_tsu_find_empty(ndev);
2205                 if (i < 0)
2206                         return -ENOMEM;
2207                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2208                 if (ret < 0)
2209                         return ret;
2210
2211                 /* Enable the entry */
2212                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2213                                  (1 << (31 - i)), TSU_TEN);
2214         }
2215
2216         /* Entry found or created, enable POST */
2217         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2218
2219         return 0;
2220 }
2221
2222 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2223 {
2224         struct sh_eth_private *mdp = netdev_priv(ndev);
2225         int i, ret;
2226
2227         if (!mdp->cd->tsu)
2228                 return 0;
2229
2230         i = sh_eth_tsu_find_entry(ndev, addr);
2231         if (i) {
2232                 /* Entry found */
2233                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2234                         goto done;
2235
2236                 /* Disable the entry if both ports was disabled */
2237                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2238                 if (ret < 0)
2239                         return ret;
2240         }
2241 done:
2242         return 0;
2243 }
2244
2245 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2246 {
2247         struct sh_eth_private *mdp = netdev_priv(ndev);
2248         int i, ret;
2249
2250         if (unlikely(!mdp->cd->tsu))
2251                 return 0;
2252
2253         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2254                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2255                         continue;
2256
2257                 /* Disable the entry if both ports was disabled */
2258                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2259                 if (ret < 0)
2260                         return ret;
2261         }
2262
2263         return 0;
2264 }
2265
2266 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2267 {
2268         struct sh_eth_private *mdp = netdev_priv(ndev);
2269         u8 addr[ETH_ALEN];
2270         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2271         int i;
2272
2273         if (unlikely(!mdp->cd->tsu))
2274                 return;
2275
2276         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2277                 sh_eth_tsu_read_entry(reg_offset, addr);
2278                 if (is_multicast_ether_addr(addr))
2279                         sh_eth_tsu_del_entry(ndev, addr);
2280         }
2281 }
2282
2283 /* Multicast reception directions set */
2284 static void sh_eth_set_multicast_list(struct net_device *ndev)
2285 {
2286         struct sh_eth_private *mdp = netdev_priv(ndev);
2287         u32 ecmr_bits;
2288         int mcast_all = 0;
2289         unsigned long flags;
2290
2291         spin_lock_irqsave(&mdp->lock, flags);
2292         /*
2293          * Initial condition is MCT = 1, PRM = 0.
2294          * Depending on ndev->flags, set PRM or clear MCT
2295          */
2296         ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2297
2298         if (!(ndev->flags & IFF_MULTICAST)) {
2299                 sh_eth_tsu_purge_mcast(ndev);
2300                 mcast_all = 1;
2301         }
2302         if (ndev->flags & IFF_ALLMULTI) {
2303                 sh_eth_tsu_purge_mcast(ndev);
2304                 ecmr_bits &= ~ECMR_MCT;
2305                 mcast_all = 1;
2306         }
2307
2308         if (ndev->flags & IFF_PROMISC) {
2309                 sh_eth_tsu_purge_all(ndev);
2310                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2311         } else if (mdp->cd->tsu) {
2312                 struct netdev_hw_addr *ha;
2313                 netdev_for_each_mc_addr(ha, ndev) {
2314                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2315                                 continue;
2316
2317                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2318                                 if (!mcast_all) {
2319                                         sh_eth_tsu_purge_mcast(ndev);
2320                                         ecmr_bits &= ~ECMR_MCT;
2321                                         mcast_all = 1;
2322                                 }
2323                         }
2324                 }
2325         } else {
2326                 /* Normal, unicast/broadcast-only mode. */
2327                 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2328         }
2329
2330         /* update the ethernet mode */
2331         sh_eth_write(ndev, ecmr_bits, ECMR);
2332
2333         spin_unlock_irqrestore(&mdp->lock, flags);
2334 }
2335
2336 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2337 {
2338         if (!mdp->port)
2339                 return TSU_VTAG0;
2340         else
2341                 return TSU_VTAG1;
2342 }
2343
2344 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2345                                   __be16 proto, u16 vid)
2346 {
2347         struct sh_eth_private *mdp = netdev_priv(ndev);
2348         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2349
2350         if (unlikely(!mdp->cd->tsu))
2351                 return -EPERM;
2352
2353         /* No filtering if vid = 0 */
2354         if (!vid)
2355                 return 0;
2356
2357         mdp->vlan_num_ids++;
2358
2359         /*
2360          * The controller has one VLAN tag HW filter. So, if the filter is
2361          * already enabled, the driver disables it and the filte
2362          */
2363         if (mdp->vlan_num_ids > 1) {
2364                 /* disable VLAN filter */
2365                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2366                 return 0;
2367         }
2368
2369         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2370                          vtag_reg_index);
2371
2372         return 0;
2373 }
2374
2375 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2376                                    __be16 proto, u16 vid)
2377 {
2378         struct sh_eth_private *mdp = netdev_priv(ndev);
2379         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2380
2381         if (unlikely(!mdp->cd->tsu))
2382                 return -EPERM;
2383
2384         /* No filtering if vid = 0 */
2385         if (!vid)
2386                 return 0;
2387
2388         mdp->vlan_num_ids--;
2389         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2390
2391         return 0;
2392 }
2393
2394 /* SuperH's TSU register init function */
2395 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2396 {
2397         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2398         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2399         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2400         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2401         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2402         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2403         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2404         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2405         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2406         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2407         if (sh_eth_is_gether(mdp)) {
2408                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2409                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2410         } else {
2411                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2412                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2413         }
2414         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2415         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2416         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2417         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2418         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2419         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2420         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2421 }
2422
2423 /* MDIO bus release function */
2424 static int sh_mdio_release(struct net_device *ndev)
2425 {
2426         struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2427
2428         /* unregister mdio bus */
2429         mdiobus_unregister(bus);
2430
2431         /* remove mdio bus info from net_device */
2432         dev_set_drvdata(&ndev->dev, NULL);
2433
2434         /* free bitbang info */
2435         free_mdio_bitbang(bus);
2436
2437         return 0;
2438 }
2439
2440 /* MDIO bus init function */
2441 static int sh_mdio_init(struct net_device *ndev, int id,
2442                         struct sh_eth_plat_data *pd)
2443 {
2444         int ret, i;
2445         struct bb_info *bitbang;
2446         struct sh_eth_private *mdp = netdev_priv(ndev);
2447
2448         /* create bit control struct for PHY */
2449         bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2450                                GFP_KERNEL);
2451         if (!bitbang) {
2452                 ret = -ENOMEM;
2453                 goto out;
2454         }
2455
2456         /* bitbang init */
2457         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2458         bitbang->set_gate = pd->set_mdio_gate;
2459         bitbang->mdi_msk = PIR_MDI;
2460         bitbang->mdo_msk = PIR_MDO;
2461         bitbang->mmd_msk = PIR_MMD;
2462         bitbang->mdc_msk = PIR_MDC;
2463         bitbang->ctrl.ops = &bb_ops;
2464
2465         /* MII controller setting */
2466         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2467         if (!mdp->mii_bus) {
2468                 ret = -ENOMEM;
2469                 goto out;
2470         }
2471
2472         /* Hook up MII support for ethtool */
2473         mdp->mii_bus->name = "sh_mii";
2474         mdp->mii_bus->parent = &ndev->dev;
2475         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2476                 mdp->pdev->name, id);
2477
2478         /* PHY IRQ */
2479         mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2480                                          sizeof(int) * PHY_MAX_ADDR,
2481                                          GFP_KERNEL);
2482         if (!mdp->mii_bus->irq) {
2483                 ret = -ENOMEM;
2484                 goto out_free_bus;
2485         }
2486
2487         for (i = 0; i < PHY_MAX_ADDR; i++)
2488                 mdp->mii_bus->irq[i] = PHY_POLL;
2489
2490         /* register mdio bus */
2491         ret = mdiobus_register(mdp->mii_bus);
2492         if (ret)
2493                 goto out_free_bus;
2494
2495         dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2496
2497         return 0;
2498
2499 out_free_bus:
2500         free_mdio_bitbang(mdp->mii_bus);
2501
2502 out:
2503         return ret;
2504 }
2505
2506 static const u16 *sh_eth_get_register_offset(int register_type)
2507 {
2508         const u16 *reg_offset = NULL;
2509
2510         switch (register_type) {
2511         case SH_ETH_REG_GIGABIT:
2512                 reg_offset = sh_eth_offset_gigabit;
2513                 break;
2514         case SH_ETH_REG_FAST_RCAR:
2515                 reg_offset = sh_eth_offset_fast_rcar;
2516                 break;
2517         case SH_ETH_REG_FAST_SH4:
2518                 reg_offset = sh_eth_offset_fast_sh4;
2519                 break;
2520         case SH_ETH_REG_FAST_SH3_SH2:
2521                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2522                 break;
2523         default:
2524                 pr_err("Unknown register type (%d)\n", register_type);
2525                 break;
2526         }
2527
2528         return reg_offset;
2529 }
2530
2531 static const struct net_device_ops sh_eth_netdev_ops = {
2532         .ndo_open               = sh_eth_open,
2533         .ndo_stop               = sh_eth_close,
2534         .ndo_start_xmit         = sh_eth_start_xmit,
2535         .ndo_get_stats          = sh_eth_get_stats,
2536         .ndo_tx_timeout         = sh_eth_tx_timeout,
2537         .ndo_do_ioctl           = sh_eth_do_ioctl,
2538         .ndo_validate_addr      = eth_validate_addr,
2539         .ndo_set_mac_address    = eth_mac_addr,
2540         .ndo_change_mtu         = eth_change_mtu,
2541 };
2542
2543 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2544         .ndo_open               = sh_eth_open,
2545         .ndo_stop               = sh_eth_close,
2546         .ndo_start_xmit         = sh_eth_start_xmit,
2547         .ndo_get_stats          = sh_eth_get_stats,
2548         .ndo_set_rx_mode        = sh_eth_set_multicast_list,
2549         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2550         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2551         .ndo_tx_timeout         = sh_eth_tx_timeout,
2552         .ndo_do_ioctl           = sh_eth_do_ioctl,
2553         .ndo_validate_addr      = eth_validate_addr,
2554         .ndo_set_mac_address    = eth_mac_addr,
2555         .ndo_change_mtu         = eth_change_mtu,
2556 };
2557
2558 static int sh_eth_drv_probe(struct platform_device *pdev)
2559 {
2560         int ret, devno = 0;
2561         struct resource *res;
2562         struct net_device *ndev = NULL;
2563         struct sh_eth_private *mdp = NULL;
2564         struct sh_eth_plat_data *pd = pdev->dev.platform_data;
2565         const struct platform_device_id *id = platform_get_device_id(pdev);
2566
2567         /* get base addr */
2568         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2569         if (unlikely(res == NULL)) {
2570                 dev_err(&pdev->dev, "invalid resource\n");
2571                 ret = -EINVAL;
2572                 goto out;
2573         }
2574
2575         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2576         if (!ndev) {
2577                 ret = -ENOMEM;
2578                 goto out;
2579         }
2580
2581         /* The sh Ether-specific entries in the device structure. */
2582         ndev->base_addr = res->start;
2583         devno = pdev->id;
2584         if (devno < 0)
2585                 devno = 0;
2586
2587         ndev->dma = -1;
2588         ret = platform_get_irq(pdev, 0);
2589         if (ret < 0) {
2590                 ret = -ENODEV;
2591                 goto out_release;
2592         }
2593         ndev->irq = ret;
2594
2595         SET_NETDEV_DEV(ndev, &pdev->dev);
2596
2597         /* Fill in the fields of the device structure with ethernet values. */
2598         ether_setup(ndev);
2599
2600         mdp = netdev_priv(ndev);
2601         mdp->num_tx_ring = TX_RING_SIZE;
2602         mdp->num_rx_ring = RX_RING_SIZE;
2603         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2604         if (IS_ERR(mdp->addr)) {
2605                 ret = PTR_ERR(mdp->addr);
2606                 goto out_release;
2607         }
2608
2609         spin_lock_init(&mdp->lock);
2610         mdp->pdev = pdev;
2611         pm_runtime_enable(&pdev->dev);
2612         pm_runtime_resume(&pdev->dev);
2613
2614         /* get PHY ID */
2615         mdp->phy_id = pd->phy;
2616         mdp->phy_interface = pd->phy_interface;
2617         /* EDMAC endian */
2618         mdp->edmac_endian = pd->edmac_endian;
2619         mdp->no_ether_link = pd->no_ether_link;
2620         mdp->ether_link_active_low = pd->ether_link_active_low;
2621         mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
2622
2623         /* set cpu data */
2624         mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2625         sh_eth_set_default_cpu_data(mdp->cd);
2626
2627         /* set function */
2628         if (mdp->cd->tsu)
2629                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2630         else
2631                 ndev->netdev_ops = &sh_eth_netdev_ops;
2632         SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2633         ndev->watchdog_timeo = TX_TIMEOUT;
2634
2635         /* debug message level */
2636         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2637
2638         /* read and set MAC address */
2639         read_mac_address(ndev, pd->mac_addr);
2640         if (!is_valid_ether_addr(ndev->dev_addr)) {
2641                 dev_warn(&pdev->dev,
2642                          "no valid MAC address supplied, using a random one.\n");
2643                 eth_hw_addr_random(ndev);
2644         }
2645
2646         /* ioremap the TSU registers */
2647         if (mdp->cd->tsu) {
2648                 struct resource *rtsu;
2649                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2650                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2651                 if (IS_ERR(mdp->tsu_addr)) {
2652                         ret = PTR_ERR(mdp->tsu_addr);
2653                         goto out_release;
2654                 }
2655                 mdp->port = devno % 2;
2656                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2657         }
2658
2659         /* initialize first or needed device */
2660         if (!devno || pd->needs_init) {
2661                 if (mdp->cd->chip_reset)
2662                         mdp->cd->chip_reset(ndev);
2663
2664                 if (mdp->cd->tsu) {
2665                         /* TSU init (Init only)*/
2666                         sh_eth_tsu_init(mdp);
2667                 }
2668         }
2669
2670         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2671
2672         /* network device register */
2673         ret = register_netdev(ndev);
2674         if (ret)
2675                 goto out_napi_del;
2676
2677         /* mdio bus init */
2678         ret = sh_mdio_init(ndev, pdev->id, pd);
2679         if (ret)
2680                 goto out_unregister;
2681
2682         /* print device information */
2683         pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2684                (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2685
2686         platform_set_drvdata(pdev, ndev);
2687
2688         return ret;
2689
2690 out_unregister:
2691         unregister_netdev(ndev);
2692
2693 out_napi_del:
2694         netif_napi_del(&mdp->napi);
2695
2696 out_release:
2697         /* net_dev free */
2698         if (ndev)
2699                 free_netdev(ndev);
2700
2701 out:
2702         return ret;
2703 }
2704
2705 static int sh_eth_drv_remove(struct platform_device *pdev)
2706 {
2707         struct net_device *ndev = platform_get_drvdata(pdev);
2708         struct sh_eth_private *mdp = netdev_priv(ndev);
2709
2710         sh_mdio_release(ndev);
2711         unregister_netdev(ndev);
2712         netif_napi_del(&mdp->napi);
2713         pm_runtime_disable(&pdev->dev);
2714         free_netdev(ndev);
2715
2716         return 0;
2717 }
2718
2719 #ifdef CONFIG_PM
2720 static int sh_eth_runtime_nop(struct device *dev)
2721 {
2722         /*
2723          * Runtime PM callback shared between ->runtime_suspend()
2724          * and ->runtime_resume(). Simply returns success.
2725          *
2726          * This driver re-initializes all registers after
2727          * pm_runtime_get_sync() anyway so there is no need
2728          * to save and restore registers here.
2729          */
2730         return 0;
2731 }
2732
2733 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2734         .runtime_suspend = sh_eth_runtime_nop,
2735         .runtime_resume = sh_eth_runtime_nop,
2736 };
2737 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2738 #else
2739 #define SH_ETH_PM_OPS NULL
2740 #endif
2741
2742 static struct platform_device_id sh_eth_id_table[] = {
2743         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2744         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2745         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2746         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2747         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2748         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2749         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2750         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2751         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
2752         { }
2753 };
2754 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2755
2756 static struct platform_driver sh_eth_driver = {
2757         .probe = sh_eth_drv_probe,
2758         .remove = sh_eth_drv_remove,
2759         .id_table = sh_eth_id_table,
2760         .driver = {
2761                    .name = CARDNAME,
2762                    .pm = SH_ETH_PM_OPS,
2763         },
2764 };
2765
2766 module_platform_driver(sh_eth_driver);
2767
2768 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2769 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2770 MODULE_LICENSE("GPL v2");