Pileus Git - ~andy/linux/blob - drivers/net/ethernet/renesas/sh_eth.c

   1 /*
   2  *  SuperH Ethernet device driver
   3  *
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2013 Renesas Solutions Corp.
   6  *  Copyright (C) 2013 Cogent Embedded, Inc.
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms and conditions of the GNU General Public License,
  10  *  version 2, as published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  *  more details.
  16  *  You should have received a copy of the GNU General Public License along with
  17  *  this program; if not, write to the Free Software Foundation, Inc.,
  18  *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  *  The full GNU General Public License is included in this distribution in
  21  *  the file called "COPYING".
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/delay.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/mdio-bitbang.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/phy.h>
  36 #include <linux/cache.h>
  37 #include <linux/io.h>
  38 #include <linux/pm_runtime.h>
  39 #include <linux/slab.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/clk.h>
  43 #include <linux/sh_eth.h>
  44
  45 #include "sh_eth.h"
  46
  47 #define SH_ETH_DEF_MSG_ENABLE \
  48                 (NETIF_MSG_LINK | \
  49                 NETIF_MSG_TIMER | \
  50                 NETIF_MSG_RX_ERR| \
  51                 NETIF_MSG_TX_ERR)
  52
  53 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  54         [EDSR]          = 0x0000,
  55         [EDMR]          = 0x0400,
  56         [EDTRR]         = 0x0408,
  57         [EDRRR]         = 0x0410,
  58         [EESR]          = 0x0428,
  59         [EESIPR]        = 0x0430,
  60         [TDLAR]         = 0x0010,
  61         [TDFAR]         = 0x0014,
  62         [TDFXR]         = 0x0018,
  63         [TDFFR]         = 0x001c,
  64         [RDLAR]         = 0x0030,
  65         [RDFAR]         = 0x0034,
  66         [RDFXR]         = 0x0038,
  67         [RDFFR]         = 0x003c,
  68         [TRSCER]        = 0x0438,
  69         [RMFCR]         = 0x0440,
  70         [TFTR]          = 0x0448,
  71         [FDR]           = 0x0450,
  72         [RMCR]          = 0x0458,
  73         [RPADIR]        = 0x0460,
  74         [FCFTR]         = 0x0468,
  75         [CSMR]          = 0x04E4,
  76
  77         [ECMR]          = 0x0500,
  78         [ECSR]          = 0x0510,
  79         [ECSIPR]        = 0x0518,
  80         [PIR]           = 0x0520,
  81         [PSR]           = 0x0528,
  82         [PIPR]          = 0x052c,
  83         [RFLR]          = 0x0508,
  84         [APR]           = 0x0554,
  85         [MPR]           = 0x0558,
  86         [PFTCR]         = 0x055c,
  87         [PFRCR]         = 0x0560,
  88         [TPAUSER]       = 0x0564,
  89         [GECMR]         = 0x05b0,
  90         [BCULR]         = 0x05b4,
  91         [MAHR]          = 0x05c0,
  92         [MALR]          = 0x05c8,
  93         [TROCR]         = 0x0700,
  94         [CDCR]          = 0x0708,
  95         [LCCR]          = 0x0710,
  96         [CEFCR]         = 0x0740,
  97         [FRECR]         = 0x0748,
  98         [TSFRCR]        = 0x0750,
  99         [TLFRCR]        = 0x0758,
 100         [RFCR]          = 0x0760,
 101         [CERCR]         = 0x0768,
 102         [CEECR]         = 0x0770,
 103         [MAFCR]         = 0x0778,
 104         [RMII_MII]      = 0x0790,
 105
 106         [ARSTR]         = 0x0000,
 107         [TSU_CTRST]     = 0x0004,
 108         [TSU_FWEN0]     = 0x0010,
 109         [TSU_FWEN1]     = 0x0014,
 110         [TSU_FCM]       = 0x0018,
 111         [TSU_BSYSL0]    = 0x0020,
 112         [TSU_BSYSL1]    = 0x0024,
 113         [TSU_PRISL0]    = 0x0028,
 114         [TSU_PRISL1]    = 0x002c,
 115         [TSU_FWSL0]     = 0x0030,
 116         [TSU_FWSL1]     = 0x0034,
 117         [TSU_FWSLC]     = 0x0038,
 118         [TSU_QTAG0]     = 0x0040,
 119         [TSU_QTAG1]     = 0x0044,
 120         [TSU_FWSR]      = 0x0050,
 121         [TSU_FWINMK]    = 0x0054,
 122         [TSU_ADQT0]     = 0x0048,
 123         [TSU_ADQT1]     = 0x004c,
 124         [TSU_VTAG0]     = 0x0058,
 125         [TSU_VTAG1]     = 0x005c,
 126         [TSU_ADSBSY]    = 0x0060,
 127         [TSU_TEN]       = 0x0064,
 128         [TSU_POST1]     = 0x0070,
 129         [TSU_POST2]     = 0x0074,
 130         [TSU_POST3]     = 0x0078,
 131         [TSU_POST4]     = 0x007c,
 132         [TSU_ADRH0]     = 0x0100,
 133         [TSU_ADRL0]     = 0x0104,
 134         [TSU_ADRH31]    = 0x01f8,
 135         [TSU_ADRL31]    = 0x01fc,
 136
 137         [TXNLCR0]       = 0x0080,
 138         [TXALCR0]       = 0x0084,
 139         [RXNLCR0]       = 0x0088,
 140         [RXALCR0]       = 0x008c,
 141         [FWNLCR0]       = 0x0090,
 142         [FWALCR0]       = 0x0094,
 143         [TXNLCR1]       = 0x00a0,
 144         [TXALCR1]       = 0x00a0,
 145         [RXNLCR1]       = 0x00a8,
 146         [RXALCR1]       = 0x00ac,
 147         [FWNLCR1]       = 0x00b0,
 148         [FWALCR1]       = 0x00b4,
 149 };
 150
 151 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 152         [ECMR]          = 0x0300,
 153         [RFLR]          = 0x0308,
 154         [ECSR]          = 0x0310,
 155         [ECSIPR]        = 0x0318,
 156         [PIR]           = 0x0320,
 157         [PSR]           = 0x0328,
 158         [RDMLR]         = 0x0340,
 159         [IPGR]          = 0x0350,
 160         [APR]           = 0x0354,
 161         [MPR]           = 0x0358,
 162         [RFCF]          = 0x0360,
 163         [TPAUSER]       = 0x0364,
 164         [TPAUSECR]      = 0x0368,
 165         [MAHR]          = 0x03c0,
 166         [MALR]          = 0x03c8,
 167         [TROCR]         = 0x03d0,
 168         [CDCR]          = 0x03d4,
 169         [LCCR]          = 0x03d8,
 170         [CNDCR]         = 0x03dc,
 171         [CEFCR]         = 0x03e4,
 172         [FRECR]         = 0x03e8,
 173         [TSFRCR]        = 0x03ec,
 174         [TLFRCR]        = 0x03f0,
 175         [RFCR]          = 0x03f4,
 176         [MAFCR]         = 0x03f8,
 177
 178         [EDMR]          = 0x0200,
 179         [EDTRR]         = 0x0208,
 180         [EDRRR]         = 0x0210,
 181         [TDLAR]         = 0x0218,
 182         [RDLAR]         = 0x0220,
 183         [EESR]          = 0x0228,
 184         [EESIPR]        = 0x0230,
 185         [TRSCER]        = 0x0238,
 186         [RMFCR]         = 0x0240,
 187         [TFTR]          = 0x0248,
 188         [FDR]           = 0x0250,
 189         [RMCR]          = 0x0258,
 190         [TFUCR]         = 0x0264,
 191         [RFOCR]         = 0x0268,
 192         [RMIIMODE]      = 0x026c,
 193         [FCFTR]         = 0x0270,
 194         [TRIMD]         = 0x027c,
 195 };
 196
 197 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 198         [ECMR]          = 0x0100,
 199         [RFLR]          = 0x0108,
 200         [ECSR]          = 0x0110,
 201         [ECSIPR]        = 0x0118,
 202         [PIR]           = 0x0120,
 203         [PSR]           = 0x0128,
 204         [RDMLR]         = 0x0140,
 205         [IPGR]          = 0x0150,
 206         [APR]           = 0x0154,
 207         [MPR]           = 0x0158,
 208         [TPAUSER]       = 0x0164,
 209         [RFCF]          = 0x0160,
 210         [TPAUSECR]      = 0x0168,
 211         [BCFRR]         = 0x016c,
 212         [MAHR]          = 0x01c0,
 213         [MALR]          = 0x01c8,
 214         [TROCR]         = 0x01d0,
 215         [CDCR]          = 0x01d4,
 216         [LCCR]          = 0x01d8,
 217         [CNDCR]         = 0x01dc,
 218         [CEFCR]         = 0x01e4,
 219         [FRECR]         = 0x01e8,
 220         [TSFRCR]        = 0x01ec,
 221         [TLFRCR]        = 0x01f0,
 222         [RFCR]          = 0x01f4,
 223         [MAFCR]         = 0x01f8,
 224         [RTRATE]        = 0x01fc,
 225
 226         [EDMR]          = 0x0000,
 227         [EDTRR]         = 0x0008,
 228         [EDRRR]         = 0x0010,
 229         [TDLAR]         = 0x0018,
 230         [RDLAR]         = 0x0020,
 231         [EESR]          = 0x0028,
 232         [EESIPR]        = 0x0030,
 233         [TRSCER]        = 0x0038,
 234         [RMFCR]         = 0x0040,
 235         [TFTR]          = 0x0048,
 236         [FDR]           = 0x0050,
 237         [RMCR]          = 0x0058,
 238         [TFUCR]         = 0x0064,
 239         [RFOCR]         = 0x0068,
 240         [FCFTR]         = 0x0070,
 241         [RPADIR]        = 0x0078,
 242         [TRIMD]         = 0x007c,
 243         [RBWAR]         = 0x00c8,
 244         [RDFAR]         = 0x00cc,
 245         [TBRAR]         = 0x00d4,
 246         [TDFAR]         = 0x00d8,
 247 };
 248
 249 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 250         [ECMR]          = 0x0160,
 251         [ECSR]          = 0x0164,
 252         [ECSIPR]        = 0x0168,
 253         [PIR]           = 0x016c,
 254         [MAHR]          = 0x0170,
 255         [MALR]          = 0x0174,
 256         [RFLR]          = 0x0178,
 257         [PSR]           = 0x017c,
 258         [TROCR]         = 0x0180,
 259         [CDCR]          = 0x0184,
 260         [LCCR]          = 0x0188,
 261         [CNDCR]         = 0x018c,
 262         [CEFCR]         = 0x0194,
 263         [FRECR]         = 0x0198,
 264         [TSFRCR]        = 0x019c,
 265         [TLFRCR]        = 0x01a0,
 266         [RFCR]          = 0x01a4,
 267         [MAFCR]         = 0x01a8,
 268         [IPGR]          = 0x01b4,
 269         [APR]           = 0x01b8,
 270         [MPR]           = 0x01bc,
 271         [TPAUSER]       = 0x01c4,
 272         [BCFR]          = 0x01cc,
 273
 274         [ARSTR]         = 0x0000,
 275         [TSU_CTRST]     = 0x0004,
 276         [TSU_FWEN0]     = 0x0010,
 277         [TSU_FWEN1]     = 0x0014,
 278         [TSU_FCM]       = 0x0018,
 279         [TSU_BSYSL0]    = 0x0020,
 280         [TSU_BSYSL1]    = 0x0024,
 281         [TSU_PRISL0]    = 0x0028,
 282         [TSU_PRISL1]    = 0x002c,
 283         [TSU_FWSL0]     = 0x0030,
 284         [TSU_FWSL1]     = 0x0034,
 285         [TSU_FWSLC]     = 0x0038,
 286         [TSU_QTAGM0]    = 0x0040,
 287         [TSU_QTAGM1]    = 0x0044,
 288         [TSU_ADQT0]     = 0x0048,
 289         [TSU_ADQT1]     = 0x004c,
 290         [TSU_FWSR]      = 0x0050,
 291         [TSU_FWINMK]    = 0x0054,
 292         [TSU_ADSBSY]    = 0x0060,
 293         [TSU_TEN]       = 0x0064,
 294         [TSU_POST1]     = 0x0070,
 295         [TSU_POST2]     = 0x0074,
 296         [TSU_POST3]     = 0x0078,
 297         [TSU_POST4]     = 0x007c,
 298
 299         [TXNLCR0]       = 0x0080,
 300         [TXALCR0]       = 0x0084,
 301         [RXNLCR0]       = 0x0088,
 302         [RXALCR0]       = 0x008c,
 303         [FWNLCR0]       = 0x0090,
 304         [FWALCR0]       = 0x0094,
 305         [TXNLCR1]       = 0x00a0,
 306         [TXALCR1]       = 0x00a0,
 307         [RXNLCR1]       = 0x00a8,
 308         [RXALCR1]       = 0x00ac,
 309         [FWNLCR1]       = 0x00b0,
 310         [FWALCR1]       = 0x00b4,
 311
 312         [TSU_ADRH0]     = 0x0100,
 313         [TSU_ADRL0]     = 0x0104,
 314         [TSU_ADRL31]    = 0x01fc,
 315 };
 316
 317 static int sh_eth_is_gether(struct sh_eth_private *mdp)
 318 {
 319         if (mdp->reg_offset == sh_eth_offset_gigabit)
 320                 return 1;
 321         else
 322                 return 0;
 323 }
 324
 325 static void sh_eth_select_mii(struct net_device *ndev)
 326 {
 327         u32 value = 0x0;
 328         struct sh_eth_private *mdp = netdev_priv(ndev);
 329
 330         switch (mdp->phy_interface) {
 331         case PHY_INTERFACE_MODE_GMII:
 332                 value = 0x2;
 333                 break;
 334         case PHY_INTERFACE_MODE_MII:
 335                 value = 0x1;
 336                 break;
 337         case PHY_INTERFACE_MODE_RMII:
 338                 value = 0x0;
 339                 break;
 340         default:
 341                 pr_warn("PHY interface mode was not setup. Set to MII.\n");
 342                 value = 0x1;
 343                 break;
 344         }
 345
 346         sh_eth_write(ndev, value, RMII_MII);
 347 }
 348
 349 static void sh_eth_set_duplex(struct net_device *ndev)
 350 {
 351         struct sh_eth_private *mdp = netdev_priv(ndev);
 352
 353         if (mdp->duplex) /* Full */
 354                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 355         else            /* Half */
 356                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 357 }
 358
 359 /* There is CPU dependent code */
 360 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 361 {
 362         struct sh_eth_private *mdp = netdev_priv(ndev);
 363
 364         switch (mdp->speed) {
 365         case 10: /* 10BASE */
 366                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 367                 break;
 368         case 100:/* 100BASE */
 369                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 370                 break;
 371         default:
 372                 break;
 373         }
 374 }
 375
 376 /* R8A7778/9 */
 377 static struct sh_eth_cpu_data r8a777x_data = {
 378         .set_duplex     = sh_eth_set_duplex,
 379         .set_rate       = sh_eth_set_rate_r8a777x,
 380
 381         .register_type  = SH_ETH_REG_FAST_RCAR,
 382
 383         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 384         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 385         .eesipr_value   = 0x01ff009f,
 386
 387         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 388         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 389                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 390                           EESR_ECI,
 391
 392         .apr            = 1,
 393         .mpr            = 1,
 394         .tpauser        = 1,
 395         .hw_swap        = 1,
 396 };
 397
 398 /* R8A7790/1 */
 399 static struct sh_eth_cpu_data r8a779x_data = {
 400         .set_duplex     = sh_eth_set_duplex,
 401         .set_rate       = sh_eth_set_rate_r8a777x,
 402
 403         .register_type  = SH_ETH_REG_FAST_RCAR,
 404
 405         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 406         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 407         .eesipr_value   = 0x01ff009f,
 408
 409         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 410         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 411                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 412                           EESR_ECI,
 413
 414         .apr            = 1,
 415         .mpr            = 1,
 416         .tpauser        = 1,
 417         .hw_swap        = 1,
 418         .rmiimode       = 1,
 419         .shift_rd0      = 1,
 420 };
 421
 422 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 423 {
 424         struct sh_eth_private *mdp = netdev_priv(ndev);
 425
 426         switch (mdp->speed) {
 427         case 10: /* 10BASE */
 428                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 429                 break;
 430         case 100:/* 100BASE */
 431                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 432                 break;
 433         default:
 434                 break;
 435         }
 436 }
 437
 438 /* SH7724 */
 439 static struct sh_eth_cpu_data sh7724_data = {
 440         .set_duplex     = sh_eth_set_duplex,
 441         .set_rate       = sh_eth_set_rate_sh7724,
 442
 443         .register_type  = SH_ETH_REG_FAST_SH4,
 444
 445         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 446         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 447         .eesipr_value   = 0x01ff009f,
 448
 449         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 450         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 451                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 452                           EESR_ECI,
 453
 454         .apr            = 1,
 455         .mpr            = 1,
 456         .tpauser        = 1,
 457         .hw_swap        = 1,
 458         .rpadir         = 1,
 459         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 460 };
 461
 462 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 463 {
 464         struct sh_eth_private *mdp = netdev_priv(ndev);
 465
 466         switch (mdp->speed) {
 467         case 10: /* 10BASE */
 468                 sh_eth_write(ndev, 0, RTRATE);
 469                 break;
 470         case 100:/* 100BASE */
 471                 sh_eth_write(ndev, 1, RTRATE);
 472                 break;
 473         default:
 474                 break;
 475         }
 476 }
 477
 478 /* SH7757 */
 479 static struct sh_eth_cpu_data sh7757_data = {
 480         .set_duplex     = sh_eth_set_duplex,
 481         .set_rate       = sh_eth_set_rate_sh7757,
 482
 483         .register_type  = SH_ETH_REG_FAST_SH4,
 484
 485         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 486         .rmcr_value     = RMCR_RNC,
 487
 488         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 489         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 490                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 491                           EESR_ECI,
 492
 493         .irq_flags      = IRQF_SHARED,
 494         .apr            = 1,
 495         .mpr            = 1,
 496         .tpauser        = 1,
 497         .hw_swap        = 1,
 498         .no_ade         = 1,
 499         .rpadir         = 1,
 500         .rpadir_value   = 2 << 16,
 501 };
 502
 503 #define SH_GIGA_ETH_BASE        0xfee00000UL
 504 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 505 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 506 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 507 {
 508         int i;
 509         unsigned long mahr[2], malr[2];
 510
 511         /* save MAHR and MALR */
 512         for (i = 0; i < 2; i++) {
 513                 malr[i] = ioread32((void *)GIGA_MALR(i));
 514                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 515         }
 516
 517         /* reset device */
 518         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 519         mdelay(1);
 520
 521         /* restore MAHR and MALR */
 522         for (i = 0; i < 2; i++) {
 523                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 524                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 525         }
 526 }
 527
 528 static void sh_eth_set_rate_giga(struct net_device *ndev)
 529 {
 530         struct sh_eth_private *mdp = netdev_priv(ndev);
 531
 532         switch (mdp->speed) {
 533         case 10: /* 10BASE */
 534                 sh_eth_write(ndev, 0x00000000, GECMR);
 535                 break;
 536         case 100:/* 100BASE */
 537                 sh_eth_write(ndev, 0x00000010, GECMR);
 538                 break;
 539         case 1000: /* 1000BASE */
 540                 sh_eth_write(ndev, 0x00000020, GECMR);
 541                 break;
 542         default:
 543                 break;
 544         }
 545 }
 546
 547 /* SH7757(GETHERC) */
 548 static struct sh_eth_cpu_data sh7757_data_giga = {
 549         .chip_reset     = sh_eth_chip_reset_giga,
 550         .set_duplex     = sh_eth_set_duplex,
 551         .set_rate       = sh_eth_set_rate_giga,
 552
 553         .register_type  = SH_ETH_REG_GIGABIT,
 554
 555         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 556         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 557         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 558
 559         .tx_check       = EESR_TC1 | EESR_FTC,
 560         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 561                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 562                           EESR_TDE | EESR_ECI,
 563         .fdr_value      = 0x0000072f,
 564         .rmcr_value     = RMCR_RNC,
 565
 566         .irq_flags      = IRQF_SHARED,
 567         .apr            = 1,
 568         .mpr            = 1,
 569         .tpauser        = 1,
 570         .bculr          = 1,
 571         .hw_swap        = 1,
 572         .rpadir         = 1,
 573         .rpadir_value   = 2 << 16,
 574         .no_trimd       = 1,
 575         .no_ade         = 1,
 576         .tsu            = 1,
 577 };
 578
 579 static void sh_eth_chip_reset(struct net_device *ndev)
 580 {
 581         struct sh_eth_private *mdp = netdev_priv(ndev);
 582
 583         /* reset device */
 584         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 585         mdelay(1);
 586 }
 587
 588 static void sh_eth_set_rate_gether(struct net_device *ndev)
 589 {
 590         struct sh_eth_private *mdp = netdev_priv(ndev);
 591
 592         switch (mdp->speed) {
 593         case 10: /* 10BASE */
 594                 sh_eth_write(ndev, GECMR_10, GECMR);
 595                 break;
 596         case 100:/* 100BASE */
 597                 sh_eth_write(ndev, GECMR_100, GECMR);
 598                 break;
 599         case 1000: /* 1000BASE */
 600                 sh_eth_write(ndev, GECMR_1000, GECMR);
 601                 break;
 602         default:
 603                 break;
 604         }
 605 }
 606
 607 /* SH7734 */
 608 static struct sh_eth_cpu_data sh7734_data = {
 609         .chip_reset     = sh_eth_chip_reset,
 610         .set_duplex     = sh_eth_set_duplex,
 611         .set_rate       = sh_eth_set_rate_gether,
 612
 613         .register_type  = SH_ETH_REG_GIGABIT,
 614
 615         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 616         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 617         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 618
 619         .tx_check       = EESR_TC1 | EESR_FTC,
 620         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 621                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 622                           EESR_TDE | EESR_ECI,
 623
 624         .apr            = 1,
 625         .mpr            = 1,
 626         .tpauser        = 1,
 627         .bculr          = 1,
 628         .hw_swap        = 1,
 629         .no_trimd       = 1,
 630         .no_ade         = 1,
 631         .tsu            = 1,
 632         .hw_crc         = 1,
 633         .select_mii     = 1,
 634 };
 635
 636 /* SH7763 */
 637 static struct sh_eth_cpu_data sh7763_data = {
 638         .chip_reset     = sh_eth_chip_reset,
 639         .set_duplex     = sh_eth_set_duplex,
 640         .set_rate       = sh_eth_set_rate_gether,
 641
 642         .register_type  = SH_ETH_REG_GIGABIT,
 643
 644         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 645         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 646         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 647
 648         .tx_check       = EESR_TC1 | EESR_FTC,
 649         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 650                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 651                           EESR_ECI,
 652
 653         .apr            = 1,
 654         .mpr            = 1,
 655         .tpauser        = 1,
 656         .bculr          = 1,
 657         .hw_swap        = 1,
 658         .no_trimd       = 1,
 659         .no_ade         = 1,
 660         .tsu            = 1,
 661         .irq_flags      = IRQF_SHARED,
 662 };
 663
 664 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 665 {
 666         struct sh_eth_private *mdp = netdev_priv(ndev);
 667
 668         /* reset device */
 669         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 670         mdelay(1);
 671
 672         sh_eth_select_mii(ndev);
 673 }
 674
 675 /* R8A7740 */
 676 static struct sh_eth_cpu_data r8a7740_data = {
 677         .chip_reset     = sh_eth_chip_reset_r8a7740,
 678         .set_duplex     = sh_eth_set_duplex,
 679         .set_rate       = sh_eth_set_rate_gether,
 680
 681         .register_type  = SH_ETH_REG_GIGABIT,
 682
 683         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 684         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 685         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 686
 687         .tx_check       = EESR_TC1 | EESR_FTC,
 688         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 689                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 690                           EESR_TDE | EESR_ECI,
 691         .fdr_value      = 0x0000070f,
 692         .rmcr_value     = RMCR_RNC,
 693
 694         .apr            = 1,
 695         .mpr            = 1,
 696         .tpauser        = 1,
 697         .bculr          = 1,
 698         .hw_swap        = 1,
 699         .rpadir         = 1,
 700         .rpadir_value   = 2 << 16,
 701         .no_trimd       = 1,
 702         .no_ade         = 1,
 703         .tsu            = 1,
 704         .select_mii     = 1,
 705         .shift_rd0      = 1,
 706 };
 707
 708 static struct sh_eth_cpu_data sh7619_data = {
 709         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 710
 711         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 712
 713         .apr            = 1,
 714         .mpr            = 1,
 715         .tpauser        = 1,
 716         .hw_swap        = 1,
 717 };
 718
 719 static struct sh_eth_cpu_data sh771x_data = {
 720         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 721
 722         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 723         .tsu            = 1,
 724 };
 725
 726 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 727 {
 728         if (!cd->ecsr_value)
 729                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 730
 731         if (!cd->ecsipr_value)
 732                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 733
 734         if (!cd->fcftr_value)
 735                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
 736                                   DEFAULT_FIFO_F_D_RFD;
 737
 738         if (!cd->fdr_value)
 739                 cd->fdr_value = DEFAULT_FDR_INIT;
 740
 741         if (!cd->rmcr_value)
 742                 cd->rmcr_value = DEFAULT_RMCR_VALUE;
 743
 744         if (!cd->tx_check)
 745                 cd->tx_check = DEFAULT_TX_CHECK;
 746
 747         if (!cd->eesr_err_check)
 748                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 749 }
 750
 751 static int sh_eth_check_reset(struct net_device *ndev)
 752 {
 753         int ret = 0;
 754         int cnt = 100;
 755
 756         while (cnt > 0) {
 757                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 758                         break;
 759                 mdelay(1);
 760                 cnt--;
 761         }
 762         if (cnt <= 0) {
 763                 pr_err("Device reset failed\n");
 764                 ret = -ETIMEDOUT;
 765         }
 766         return ret;
 767 }
 768
 769 static int sh_eth_reset(struct net_device *ndev)
 770 {
 771         struct sh_eth_private *mdp = netdev_priv(ndev);
 772         int ret = 0;
 773
 774         if (sh_eth_is_gether(mdp)) {
 775                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 776                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 777                              EDMR);
 778
 779                 ret = sh_eth_check_reset(ndev);
 780                 if (ret)
 781                         goto out;
 782
 783                 /* Table Init */
 784                 sh_eth_write(ndev, 0x0, TDLAR);
 785                 sh_eth_write(ndev, 0x0, TDFAR);
 786                 sh_eth_write(ndev, 0x0, TDFXR);
 787                 sh_eth_write(ndev, 0x0, TDFFR);
 788                 sh_eth_write(ndev, 0x0, RDLAR);
 789                 sh_eth_write(ndev, 0x0, RDFAR);
 790                 sh_eth_write(ndev, 0x0, RDFXR);
 791                 sh_eth_write(ndev, 0x0, RDFFR);
 792
 793                 /* Reset HW CRC register */
 794                 if (mdp->cd->hw_crc)
 795                         sh_eth_write(ndev, 0x0, CSMR);
 796
 797                 /* Select MII mode */
 798                 if (mdp->cd->select_mii)
 799                         sh_eth_select_mii(ndev);
 800         } else {
 801                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 802                              EDMR);
 803                 mdelay(3);
 804                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 805                              EDMR);
 806         }
 807
 808 out:
 809         return ret;
 810 }
 811
 812 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 813 static void sh_eth_set_receive_align(struct sk_buff *skb)
 814 {
 815         int reserve;
 816
 817         reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
 818         if (reserve)
 819                 skb_reserve(skb, reserve);
 820 }
 821 #else
 822 static void sh_eth_set_receive_align(struct sk_buff *skb)
 823 {
 824         skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
 825 }
 826 #endif
 827
 828
 829 /* CPU <-> EDMAC endian convert */
 830 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 831 {
 832         switch (mdp->edmac_endian) {
 833         case EDMAC_LITTLE_ENDIAN:
 834                 return cpu_to_le32(x);
 835         case EDMAC_BIG_ENDIAN:
 836                 return cpu_to_be32(x);
 837         }
 838         return x;
 839 }
 840
 841 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 842 {
 843         switch (mdp->edmac_endian) {
 844         case EDMAC_LITTLE_ENDIAN:
 845                 return le32_to_cpu(x);
 846         case EDMAC_BIG_ENDIAN:
 847                 return be32_to_cpu(x);
 848         }
 849         return x;
 850 }
 851
 852 /*
 853  * Program the hardware MAC address from dev->dev_addr.
 854  */
 855 static void update_mac_address(struct net_device *ndev)
 856 {
 857         sh_eth_write(ndev,
 858                 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 859                 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 860         sh_eth_write(ndev,
 861                 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 862 }
 863
 864 /*
 865  * Get MAC address from SuperH MAC address register
 866  *
 867  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 868  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 869  * When you want use this device, you must set MAC address in bootloader.
 870  *
 871  */
 872 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 873 {
 874         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 875                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 876         } else {
 877                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 878                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 879                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 880                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 881                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 882                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 883         }
 884 }
 885
 886 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 887 {
 888         if (sh_eth_is_gether(mdp))
 889                 return EDTRR_TRNS_GETHER;
 890         else
 891                 return EDTRR_TRNS_ETHER;
 892 }
 893
 894 struct bb_info {
 895         void (*set_gate)(void *addr);
 896         struct mdiobb_ctrl ctrl;
 897         void *addr;
 898         u32 mmd_msk;/* MMD */
 899         u32 mdo_msk;
 900         u32 mdi_msk;
 901         u32 mdc_msk;
 902 };
 903
 904 /* PHY bit set */
 905 static void bb_set(void *addr, u32 msk)
 906 {
 907         iowrite32(ioread32(addr) | msk, addr);
 908 }
 909
 910 /* PHY bit clear */
 911 static void bb_clr(void *addr, u32 msk)
 912 {
 913         iowrite32((ioread32(addr) & ~msk), addr);
 914 }
 915
 916 /* PHY bit read */
 917 static int bb_read(void *addr, u32 msk)
 918 {
 919         return (ioread32(addr) & msk) != 0;
 920 }
 921
 922 /* Data I/O pin control */
 923 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
 924 {
 925         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 926
 927         if (bitbang->set_gate)
 928                 bitbang->set_gate(bitbang->addr);
 929
 930         if (bit)
 931                 bb_set(bitbang->addr, bitbang->mmd_msk);
 932         else
 933                 bb_clr(bitbang->addr, bitbang->mmd_msk);
 934 }
 935
 936 /* Set bit data*/
 937 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
 938 {
 939         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 940
 941         if (bitbang->set_gate)
 942                 bitbang->set_gate(bitbang->addr);
 943
 944         if (bit)
 945                 bb_set(bitbang->addr, bitbang->mdo_msk);
 946         else
 947                 bb_clr(bitbang->addr, bitbang->mdo_msk);
 948 }
 949
 950 /* Get bit data*/
 951 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
 952 {
 953         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 954
 955         if (bitbang->set_gate)
 956                 bitbang->set_gate(bitbang->addr);
 957
 958         return bb_read(bitbang->addr, bitbang->mdi_msk);
 959 }
 960
 961 /* MDC pin control */
 962 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
 963 {
 964         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 965
 966         if (bitbang->set_gate)
 967                 bitbang->set_gate(bitbang->addr);
 968
 969         if (bit)
 970                 bb_set(bitbang->addr, bitbang->mdc_msk);
 971         else
 972                 bb_clr(bitbang->addr, bitbang->mdc_msk);
 973 }
 974
 975 /* mdio bus control struct */
 976 static struct mdiobb_ops bb_ops = {
 977         .owner = THIS_MODULE,
 978         .set_mdc = sh_mdc_ctrl,
 979         .set_mdio_dir = sh_mmd_ctrl,
 980         .set_mdio_data = sh_set_mdio,
 981         .get_mdio_data = sh_get_mdio,
 982 };
 983
 984 /* free skb and descriptor buffer */
 985 static void sh_eth_ring_free(struct net_device *ndev)
 986 {
 987         struct sh_eth_private *mdp = netdev_priv(ndev);
 988         int i;
 989
 990         /* Free Rx skb ringbuffer */
 991         if (mdp->rx_skbuff) {
 992                 for (i = 0; i < mdp->num_rx_ring; i++) {
 993                         if (mdp->rx_skbuff[i])
 994                                 dev_kfree_skb(mdp->rx_skbuff[i]);
 995                 }
 996         }
 997         kfree(mdp->rx_skbuff);
 998         mdp->rx_skbuff = NULL;
 999
1000         /* Free Tx skb ringbuffer */
1001         if (mdp->tx_skbuff) {
1002                 for (i = 0; i < mdp->num_tx_ring; i++) {
1003                         if (mdp->tx_skbuff[i])
1004                                 dev_kfree_skb(mdp->tx_skbuff[i]);
1005                 }
1006         }
1007         kfree(mdp->tx_skbuff);
1008         mdp->tx_skbuff = NULL;
1009 }
1010
1011 /* format skb and descriptor buffer */
1012 static void sh_eth_ring_format(struct net_device *ndev)
1013 {
1014         struct sh_eth_private *mdp = netdev_priv(ndev);
1015         int i;
1016         struct sk_buff *skb;
1017         struct sh_eth_rxdesc *rxdesc = NULL;
1018         struct sh_eth_txdesc *txdesc = NULL;
1019         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1020         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1021
1022         mdp->cur_rx = mdp->cur_tx = 0;
1023         mdp->dirty_rx = mdp->dirty_tx = 0;
1024
1025         memset(mdp->rx_ring, 0, rx_ringsize);
1026
1027         /* build Rx ring buffer */
1028         for (i = 0; i < mdp->num_rx_ring; i++) {
1029                 /* skb */
1030                 mdp->rx_skbuff[i] = NULL;
1031                 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1032                 mdp->rx_skbuff[i] = skb;
1033                 if (skb == NULL)
1034                         break;
1035                 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1036                                 DMA_FROM_DEVICE);
1037                 sh_eth_set_receive_align(skb);
1038
1039                 /* RX descriptor */
1040                 rxdesc = &mdp->rx_ring[i];
1041                 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1042                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1043
1044                 /* The size of the buffer is 16 byte boundary. */
1045                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1046                 /* Rx descriptor address set */
1047                 if (i == 0) {
1048                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1049                         if (sh_eth_is_gether(mdp))
1050                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1051                 }
1052         }
1053
1054         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1055
1056         /* Mark the last entry as wrapping the ring. */
1057         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1058
1059         memset(mdp->tx_ring, 0, tx_ringsize);
1060
1061         /* build Tx ring buffer */
1062         for (i = 0; i < mdp->num_tx_ring; i++) {
1063                 mdp->tx_skbuff[i] = NULL;
1064                 txdesc = &mdp->tx_ring[i];
1065                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1066                 txdesc->buffer_length = 0;
1067                 if (i == 0) {
1068                         /* Tx descriptor address set */
1069                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1070                         if (sh_eth_is_gether(mdp))
1071                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1072                 }
1073         }
1074
1075         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1076 }
1077
1078 /* Get skb and descriptor buffer */
1079 static int sh_eth_ring_init(struct net_device *ndev)
1080 {
1081         struct sh_eth_private *mdp = netdev_priv(ndev);
1082         int rx_ringsize, tx_ringsize, ret = 0;
1083
1084         /*
1085          * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1086          * card needs room to do 8 byte alignment, +2 so we can reserve
1087          * the first 2 bytes, and +16 gets room for the status word from the
1088          * card.
1089          */
1090         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1091                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1092         if (mdp->cd->rpadir)
1093                 mdp->rx_buf_sz += NET_IP_ALIGN;
1094
1095         /* Allocate RX and TX skb rings */
1096         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1097                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1098         if (!mdp->rx_skbuff) {
1099                 ret = -ENOMEM;
1100                 return ret;
1101         }
1102
1103         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1104                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1105         if (!mdp->tx_skbuff) {
1106                 ret = -ENOMEM;
1107                 goto skb_ring_free;
1108         }
1109
1110         /* Allocate all Rx descriptors. */
1111         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1112         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1113                                           GFP_KERNEL);
1114         if (!mdp->rx_ring) {
1115                 ret = -ENOMEM;
1116                 goto desc_ring_free;
1117         }
1118
1119         mdp->dirty_rx = 0;
1120
1121         /* Allocate all Tx descriptors. */
1122         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1123         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1124                                           GFP_KERNEL);
1125         if (!mdp->tx_ring) {
1126                 ret = -ENOMEM;
1127                 goto desc_ring_free;
1128         }
1129         return ret;
1130
1131 desc_ring_free:
1132         /* free DMA buffer */
1133         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1134
1135 skb_ring_free:
1136         /* Free Rx and Tx skb ring buffer */
1137         sh_eth_ring_free(ndev);
1138         mdp->tx_ring = NULL;
1139         mdp->rx_ring = NULL;
1140
1141         return ret;
1142 }
1143
1144 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1145 {
1146         int ringsize;
1147
1148         if (mdp->rx_ring) {
1149                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1150                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1151                                   mdp->rx_desc_dma);
1152                 mdp->rx_ring = NULL;
1153         }
1154
1155         if (mdp->tx_ring) {
1156                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1157                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1158                                   mdp->tx_desc_dma);
1159                 mdp->tx_ring = NULL;
1160         }
1161 }
1162
1163 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1164 {
1165         int ret = 0;
1166         struct sh_eth_private *mdp = netdev_priv(ndev);
1167         u32 val;
1168
1169         /* Soft Reset */
1170         ret = sh_eth_reset(ndev);
1171         if (ret)
1172                 goto out;
1173
1174         if (mdp->cd->rmiimode)
1175                 sh_eth_write(ndev, 0x1, RMIIMODE);
1176
1177         /* Descriptor format */
1178         sh_eth_ring_format(ndev);
1179         if (mdp->cd->rpadir)
1180                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1181
1182         /* all sh_eth int mask */
1183         sh_eth_write(ndev, 0, EESIPR);
1184
1185 #if defined(__LITTLE_ENDIAN)
1186         if (mdp->cd->hw_swap)
1187                 sh_eth_write(ndev, EDMR_EL, EDMR);
1188         else
1189 #endif
1190                 sh_eth_write(ndev, 0, EDMR);
1191
1192         /* FIFO size set */
1193         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1194         sh_eth_write(ndev, 0, TFTR);
1195
1196         /* Frame recv control */
1197         sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
1198
1199         sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1200
1201         if (mdp->cd->bculr)
1202                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1203
1204         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1205
1206         if (!mdp->cd->no_trimd)
1207                 sh_eth_write(ndev, 0, TRIMD);
1208
1209         /* Recv frame limit set register */
1210         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1211                      RFLR);
1212
1213         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1214         if (start)
1215                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1216
1217         /* PAUSE Prohibition */
1218         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1219                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1220
1221         sh_eth_write(ndev, val, ECMR);
1222
1223         if (mdp->cd->set_rate)
1224                 mdp->cd->set_rate(ndev);
1225
1226         /* E-MAC Status Register clear */
1227         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1228
1229         /* E-MAC Interrupt Enable register */
1230         if (start)
1231                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1232
1233         /* Set MAC address */
1234         update_mac_address(ndev);
1235
1236         /* mask reset */
1237         if (mdp->cd->apr)
1238                 sh_eth_write(ndev, APR_AP, APR);
1239         if (mdp->cd->mpr)
1240                 sh_eth_write(ndev, MPR_MP, MPR);
1241         if (mdp->cd->tpauser)
1242                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1243
1244         if (start) {
1245                 /* Setting the Rx mode will start the Rx process. */
1246                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1247
1248                 netif_start_queue(ndev);
1249         }
1250
1251 out:
1252         return ret;
1253 }
1254
1255 /* free Tx skb function */
1256 static int sh_eth_txfree(struct net_device *ndev)
1257 {
1258         struct sh_eth_private *mdp = netdev_priv(ndev);
1259         struct sh_eth_txdesc *txdesc;
1260         int freeNum = 0;
1261         int entry = 0;
1262
1263         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1264                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1265                 txdesc = &mdp->tx_ring[entry];
1266                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1267                         break;
1268                 /* Free the original skb. */
1269                 if (mdp->tx_skbuff[entry]) {
1270                         dma_unmap_single(&ndev->dev, txdesc->addr,
1271                                          txdesc->buffer_length, DMA_TO_DEVICE);
1272                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1273                         mdp->tx_skbuff[entry] = NULL;
1274                         freeNum++;
1275                 }
1276                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1277                 if (entry >= mdp->num_tx_ring - 1)
1278                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1279
1280                 ndev->stats.tx_packets++;
1281                 ndev->stats.tx_bytes += txdesc->buffer_length;
1282         }
1283         return freeNum;
1284 }
1285
1286 /* Packet receive function */
1287 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1288 {
1289         struct sh_eth_private *mdp = netdev_priv(ndev);
1290         struct sh_eth_rxdesc *rxdesc;
1291
1292         int entry = mdp->cur_rx % mdp->num_rx_ring;
1293         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1294         struct sk_buff *skb;
1295         int exceeded = 0;
1296         u16 pkt_len = 0;
1297         u32 desc_status;
1298
1299         rxdesc = &mdp->rx_ring[entry];
1300         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1301                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1302                 pkt_len = rxdesc->frame_length;
1303
1304                 if (--boguscnt < 0)
1305                         break;
1306
1307                 if (*quota <= 0) {
1308                         exceeded = 1;
1309                         break;
1310                 }
1311                 (*quota)--;
1312
1313                 if (!(desc_status & RDFEND))
1314                         ndev->stats.rx_length_errors++;
1315
1316                 /*
1317                  * In case of almost all GETHER/ETHERs, the Receive Frame State
1318                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1319                  * bit 0. However, in case of the R8A7740's GETHER, the RFS
1320                  * bits are from bit 25 to bit 16. So, the driver needs right
1321                  * shifting by 16.
1322                  */
1323                 if (mdp->cd->shift_rd0)
1324                         desc_status >>= 16;
1325
1326                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1327                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1328                         ndev->stats.rx_errors++;
1329                         if (desc_status & RD_RFS1)
1330                                 ndev->stats.rx_crc_errors++;
1331                         if (desc_status & RD_RFS2)
1332                                 ndev->stats.rx_frame_errors++;
1333                         if (desc_status & RD_RFS3)
1334                                 ndev->stats.rx_length_errors++;
1335                         if (desc_status & RD_RFS4)
1336                                 ndev->stats.rx_length_errors++;
1337                         if (desc_status & RD_RFS6)
1338                                 ndev->stats.rx_missed_errors++;
1339                         if (desc_status & RD_RFS10)
1340                                 ndev->stats.rx_over_errors++;
1341                 } else {
1342                         if (!mdp->cd->hw_swap)
1343                                 sh_eth_soft_swap(
1344                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1345                                         pkt_len + 2);
1346                         skb = mdp->rx_skbuff[entry];
1347                         mdp->rx_skbuff[entry] = NULL;
1348                         if (mdp->cd->rpadir)
1349                                 skb_reserve(skb, NET_IP_ALIGN);
1350                         dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1351                                                 mdp->rx_buf_sz,
1352                                                 DMA_FROM_DEVICE);
1353                         skb_put(skb, pkt_len);
1354                         skb->protocol = eth_type_trans(skb, ndev);
1355                         netif_receive_skb(skb);
1356                         ndev->stats.rx_packets++;
1357                         ndev->stats.rx_bytes += pkt_len;
1358                 }
1359                 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1360                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1361                 rxdesc = &mdp->rx_ring[entry];
1362         }
1363
1364         /* Refill the Rx ring buffers. */
1365         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1366                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1367                 rxdesc = &mdp->rx_ring[entry];
1368                 /* The size of the buffer is 16 byte boundary. */
1369                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1370
1371                 if (mdp->rx_skbuff[entry] == NULL) {
1372                         skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1373                         mdp->rx_skbuff[entry] = skb;
1374                         if (skb == NULL)
1375                                 break;  /* Better luck next round. */
1376                         dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1377                                         DMA_FROM_DEVICE);
1378                         sh_eth_set_receive_align(skb);
1379
1380                         skb_checksum_none_assert(skb);
1381                         rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1382                 }
1383                 if (entry >= mdp->num_rx_ring - 1)
1384                         rxdesc->status |=
1385                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1386                 else
1387                         rxdesc->status |=
1388                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1389         }
1390
1391         /* Restart Rx engine if stopped. */
1392         /* If we don't need to check status, don't. -KDU */
1393         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1394                 /* fix the values for the next receiving if RDE is set */
1395                 if (intr_status & EESR_RDE)
1396                         mdp->cur_rx = mdp->dirty_rx =
1397                                 (sh_eth_read(ndev, RDFAR) -
1398                                  sh_eth_read(ndev, RDLAR)) >> 4;
1399                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1400         }
1401
1402         return exceeded;
1403 }
1404
1405 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1406 {
1407         /* disable tx and rx */
1408         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1409                 ~(ECMR_RE | ECMR_TE), ECMR);
1410 }
1411
1412 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1413 {
1414         /* enable tx and rx */
1415         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1416                 (ECMR_RE | ECMR_TE), ECMR);
1417 }
1418
1419 /* error control function */
1420 static void sh_eth_error(struct net_device *ndev, int intr_status)
1421 {
1422         struct sh_eth_private *mdp = netdev_priv(ndev);
1423         u32 felic_stat;
1424         u32 link_stat;
1425         u32 mask;
1426
1427         if (intr_status & EESR_ECI) {
1428                 felic_stat = sh_eth_read(ndev, ECSR);
1429                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1430                 if (felic_stat & ECSR_ICD)
1431                         ndev->stats.tx_carrier_errors++;
1432                 if (felic_stat & ECSR_LCHNG) {
1433                         /* Link Changed */
1434                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1435                                 goto ignore_link;
1436                         } else {
1437                                 link_stat = (sh_eth_read(ndev, PSR));
1438                                 if (mdp->ether_link_active_low)
1439                                         link_stat = ~link_stat;
1440                         }
1441                         if (!(link_stat & PHY_ST_LINK))
1442                                 sh_eth_rcv_snd_disable(ndev);
1443                         else {
1444                                 /* Link Up */
1445                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1446                                           ~DMAC_M_ECI, EESIPR);
1447                                 /*clear int */
1448                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1449                                           ECSR);
1450                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1451                                           DMAC_M_ECI, EESIPR);
1452                                 /* enable tx and rx */
1453                                 sh_eth_rcv_snd_enable(ndev);
1454                         }
1455                 }
1456         }
1457
1458 ignore_link:
1459         if (intr_status & EESR_TWB) {
1460                 /* Unused write back interrupt */
1461                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1462                         ndev->stats.tx_aborted_errors++;
1463                         if (netif_msg_tx_err(mdp))
1464                                 dev_err(&ndev->dev, "Transmit Abort\n");
1465                 }
1466         }
1467
1468         if (intr_status & EESR_RABT) {
1469                 /* Receive Abort int */
1470                 if (intr_status & EESR_RFRMER) {
1471                         /* Receive Frame Overflow int */
1472                         ndev->stats.rx_frame_errors++;
1473                         if (netif_msg_rx_err(mdp))
1474                                 dev_err(&ndev->dev, "Receive Abort\n");
1475                 }
1476         }
1477
1478         if (intr_status & EESR_TDE) {
1479                 /* Transmit Descriptor Empty int */
1480                 ndev->stats.tx_fifo_errors++;
1481                 if (netif_msg_tx_err(mdp))
1482                         dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1483         }
1484
1485         if (intr_status & EESR_TFE) {
1486                 /* FIFO under flow */
1487                 ndev->stats.tx_fifo_errors++;
1488                 if (netif_msg_tx_err(mdp))
1489                         dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1490         }
1491
1492         if (intr_status & EESR_RDE) {
1493                 /* Receive Descriptor Empty int */
1494                 ndev->stats.rx_over_errors++;
1495
1496                 if (netif_msg_rx_err(mdp))
1497                         dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1498         }
1499
1500         if (intr_status & EESR_RFE) {
1501                 /* Receive FIFO Overflow int */
1502                 ndev->stats.rx_fifo_errors++;
1503                 if (netif_msg_rx_err(mdp))
1504                         dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1505         }
1506
1507         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1508                 /* Address Error */
1509                 ndev->stats.tx_fifo_errors++;
1510                 if (netif_msg_tx_err(mdp))
1511                         dev_err(&ndev->dev, "Address Error\n");
1512         }
1513
1514         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1515         if (mdp->cd->no_ade)
1516                 mask &= ~EESR_ADE;
1517         if (intr_status & mask) {
1518                 /* Tx error */
1519                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1520                 /* dmesg */
1521                 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1522                                 intr_status, mdp->cur_tx);
1523                 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1524                                 mdp->dirty_tx, (u32) ndev->state, edtrr);
1525                 /* dirty buffer free */
1526                 sh_eth_txfree(ndev);
1527
1528                 /* SH7712 BUG */
1529                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1530                         /* tx dma start */
1531                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1532                 }
1533                 /* wakeup */
1534                 netif_wake_queue(ndev);
1535         }
1536 }
1537
1538 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1539 {
1540         struct net_device *ndev = netdev;
1541         struct sh_eth_private *mdp = netdev_priv(ndev);
1542         struct sh_eth_cpu_data *cd = mdp->cd;
1543         irqreturn_t ret = IRQ_NONE;
1544         unsigned long intr_status, intr_enable;
1545
1546         spin_lock(&mdp->lock);
1547
1548         /* Get interrupt status */
1549         intr_status = sh_eth_read(ndev, EESR);
1550         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1551          * enabled since it's the one that  comes thru regardless of the mask,
1552          * and we need to fully handle it in sh_eth_error() in order to quench
1553          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1554          */
1555         intr_enable = sh_eth_read(ndev, EESIPR);
1556         intr_status &= intr_enable | DMAC_M_ECI;
1557         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1558                 ret = IRQ_HANDLED;
1559         else
1560                 goto other_irq;
1561
1562         if (intr_status & EESR_RX_CHECK) {
1563                 if (napi_schedule_prep(&mdp->napi)) {
1564                         /* Mask Rx interrupts */
1565                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1566                                      EESIPR);
1567                         __napi_schedule(&mdp->napi);
1568                 } else {
1569                         dev_warn(&ndev->dev,
1570                                  "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1571                                  intr_status, intr_enable);
1572                 }
1573         }
1574
1575         /* Tx Check */
1576         if (intr_status & cd->tx_check) {
1577                 /* Clear Tx interrupts */
1578                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1579
1580                 sh_eth_txfree(ndev);
1581                 netif_wake_queue(ndev);
1582         }
1583
1584         if (intr_status & cd->eesr_err_check) {
1585                 /* Clear error interrupts */
1586                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1587
1588                 sh_eth_error(ndev, intr_status);
1589         }
1590
1591 other_irq:
1592         spin_unlock(&mdp->lock);
1593
1594         return ret;
1595 }
1596
1597 static int sh_eth_poll(struct napi_struct *napi, int budget)
1598 {
1599         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1600                                                   napi);
1601         struct net_device *ndev = napi->dev;
1602         int quota = budget;
1603         unsigned long intr_status;
1604
1605         for (;;) {
1606                 intr_status = sh_eth_read(ndev, EESR);
1607                 if (!(intr_status & EESR_RX_CHECK))
1608                         break;
1609                 /* Clear Rx interrupts */
1610                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1611
1612                 if (sh_eth_rx(ndev, intr_status, &quota))
1613                         goto out;
1614         }
1615
1616         napi_complete(napi);
1617
1618         /* Reenable Rx interrupts */
1619         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1620 out:
1621         return budget - quota;
1622 }
1623
1624 /* PHY state control function */
1625 static void sh_eth_adjust_link(struct net_device *ndev)
1626 {
1627         struct sh_eth_private *mdp = netdev_priv(ndev);
1628         struct phy_device *phydev = mdp->phydev;
1629         int new_state = 0;
1630
1631         if (phydev->link) {
1632                 if (phydev->duplex != mdp->duplex) {
1633                         new_state = 1;
1634                         mdp->duplex = phydev->duplex;
1635                         if (mdp->cd->set_duplex)
1636                                 mdp->cd->set_duplex(ndev);
1637                 }
1638
1639                 if (phydev->speed != mdp->speed) {
1640                         new_state = 1;
1641                         mdp->speed = phydev->speed;
1642                         if (mdp->cd->set_rate)
1643                                 mdp->cd->set_rate(ndev);
1644                 }
1645                 if (!mdp->link) {
1646                         sh_eth_write(ndev,
1647                                 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1648                         new_state = 1;
1649                         mdp->link = phydev->link;
1650                         if (mdp->cd->no_psr || mdp->no_ether_link)
1651                                 sh_eth_rcv_snd_enable(ndev);
1652                 }
1653         } else if (mdp->link) {
1654                 new_state = 1;
1655                 mdp->link = 0;
1656                 mdp->speed = 0;
1657                 mdp->duplex = -1;
1658                 if (mdp->cd->no_psr || mdp->no_ether_link)
1659                         sh_eth_rcv_snd_disable(ndev);
1660         }
1661
1662         if (new_state && netif_msg_link(mdp))
1663                 phy_print_status(phydev);
1664 }
1665
1666 /* PHY init function */
1667 static int sh_eth_phy_init(struct net_device *ndev)
1668 {
1669         struct sh_eth_private *mdp = netdev_priv(ndev);
1670         char phy_id[MII_BUS_ID_SIZE + 3];
1671         struct phy_device *phydev = NULL;
1672
1673         snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1674                 mdp->mii_bus->id , mdp->phy_id);
1675
1676         mdp->link = 0;
1677         mdp->speed = 0;
1678         mdp->duplex = -1;
1679
1680         /* Try connect to PHY */
1681         phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1682                              mdp->phy_interface);
1683         if (IS_ERR(phydev)) {
1684                 dev_err(&ndev->dev, "phy_connect failed\n");
1685                 return PTR_ERR(phydev);
1686         }
1687
1688         dev_info(&ndev->dev, "attached PHY %d (IRQ %d) to driver %s\n",
1689                  phydev->addr, phydev->irq, phydev->drv->name);
1690
1691         mdp->phydev = phydev;
1692
1693         return 0;
1694 }
1695
1696 /* PHY control start function */
1697 static int sh_eth_phy_start(struct net_device *ndev)
1698 {
1699         struct sh_eth_private *mdp = netdev_priv(ndev);
1700         int ret;
1701
1702         ret = sh_eth_phy_init(ndev);
1703         if (ret)
1704                 return ret;
1705
1706         phy_start(mdp->phydev);
1707
1708         return 0;
1709 }
1710
1711 static int sh_eth_get_settings(struct net_device *ndev,
1712                         struct ethtool_cmd *ecmd)
1713 {
1714         struct sh_eth_private *mdp = netdev_priv(ndev);
1715         unsigned long flags;
1716         int ret;
1717
1718         spin_lock_irqsave(&mdp->lock, flags);
1719         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1720         spin_unlock_irqrestore(&mdp->lock, flags);
1721
1722         return ret;
1723 }
1724
1725 static int sh_eth_set_settings(struct net_device *ndev,
1726                 struct ethtool_cmd *ecmd)
1727 {
1728         struct sh_eth_private *mdp = netdev_priv(ndev);
1729         unsigned long flags;
1730         int ret;
1731
1732         spin_lock_irqsave(&mdp->lock, flags);
1733
1734         /* disable tx and rx */
1735         sh_eth_rcv_snd_disable(ndev);
1736
1737         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1738         if (ret)
1739                 goto error_exit;
1740
1741         if (ecmd->duplex == DUPLEX_FULL)
1742                 mdp->duplex = 1;
1743         else
1744                 mdp->duplex = 0;
1745
1746         if (mdp->cd->set_duplex)
1747                 mdp->cd->set_duplex(ndev);
1748
1749 error_exit:
1750         mdelay(1);
1751
1752         /* enable tx and rx */
1753         sh_eth_rcv_snd_enable(ndev);
1754
1755         spin_unlock_irqrestore(&mdp->lock, flags);
1756
1757         return ret;
1758 }
1759
1760 static int sh_eth_nway_reset(struct net_device *ndev)
1761 {
1762         struct sh_eth_private *mdp = netdev_priv(ndev);
1763         unsigned long flags;
1764         int ret;
1765
1766         spin_lock_irqsave(&mdp->lock, flags);
1767         ret = phy_start_aneg(mdp->phydev);
1768         spin_unlock_irqrestore(&mdp->lock, flags);
1769
1770         return ret;
1771 }
1772
1773 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1774 {
1775         struct sh_eth_private *mdp = netdev_priv(ndev);
1776         return mdp->msg_enable;
1777 }
1778
1779 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1780 {
1781         struct sh_eth_private *mdp = netdev_priv(ndev);
1782         mdp->msg_enable = value;
1783 }
1784
1785 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1786         "rx_current", "tx_current",
1787         "rx_dirty", "tx_dirty",
1788 };
1789 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1790
1791 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1792 {
1793         switch (sset) {
1794         case ETH_SS_STATS:
1795                 return SH_ETH_STATS_LEN;
1796         default:
1797                 return -EOPNOTSUPP;
1798         }
1799 }
1800
1801 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1802                         struct ethtool_stats *stats, u64 *data)
1803 {
1804         struct sh_eth_private *mdp = netdev_priv(ndev);
1805         int i = 0;
1806
1807         /* device-specific stats */
1808         data[i++] = mdp->cur_rx;
1809         data[i++] = mdp->cur_tx;
1810         data[i++] = mdp->dirty_rx;
1811         data[i++] = mdp->dirty_tx;
1812 }
1813
1814 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1815 {
1816         switch (stringset) {
1817         case ETH_SS_STATS:
1818                 memcpy(data, *sh_eth_gstrings_stats,
1819                                         sizeof(sh_eth_gstrings_stats));
1820                 break;
1821         }
1822 }
1823
1824 static void sh_eth_get_ringparam(struct net_device *ndev,
1825                                  struct ethtool_ringparam *ring)
1826 {
1827         struct sh_eth_private *mdp = netdev_priv(ndev);
1828
1829         ring->rx_max_pending = RX_RING_MAX;
1830         ring->tx_max_pending = TX_RING_MAX;
1831         ring->rx_pending = mdp->num_rx_ring;
1832         ring->tx_pending = mdp->num_tx_ring;
1833 }
1834
1835 static int sh_eth_set_ringparam(struct net_device *ndev,
1836                                 struct ethtool_ringparam *ring)
1837 {
1838         struct sh_eth_private *mdp = netdev_priv(ndev);
1839         int ret;
1840
1841         if (ring->tx_pending > TX_RING_MAX ||
1842             ring->rx_pending > RX_RING_MAX ||
1843             ring->tx_pending < TX_RING_MIN ||
1844             ring->rx_pending < RX_RING_MIN)
1845                 return -EINVAL;
1846         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1847                 return -EINVAL;
1848
1849         if (netif_running(ndev)) {
1850                 netif_tx_disable(ndev);
1851                 /* Disable interrupts by clearing the interrupt mask. */
1852                 sh_eth_write(ndev, 0x0000, EESIPR);
1853                 /* Stop the chip's Tx and Rx processes. */
1854                 sh_eth_write(ndev, 0, EDTRR);
1855                 sh_eth_write(ndev, 0, EDRRR);
1856                 synchronize_irq(ndev->irq);
1857         }
1858
1859         /* Free all the skbuffs in the Rx queue. */
1860         sh_eth_ring_free(ndev);
1861         /* Free DMA buffer */
1862         sh_eth_free_dma_buffer(mdp);
1863
1864         /* Set new parameters */
1865         mdp->num_rx_ring = ring->rx_pending;
1866         mdp->num_tx_ring = ring->tx_pending;
1867
1868         ret = sh_eth_ring_init(ndev);
1869         if (ret < 0) {
1870                 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1871                 return ret;
1872         }
1873         ret = sh_eth_dev_init(ndev, false);
1874         if (ret < 0) {
1875                 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1876                 return ret;
1877         }
1878
1879         if (netif_running(ndev)) {
1880                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1881                 /* Setting the Rx mode will start the Rx process. */
1882                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1883                 netif_wake_queue(ndev);
1884         }
1885
1886         return 0;
1887 }
1888
1889 static const struct ethtool_ops sh_eth_ethtool_ops = {
1890         .get_settings   = sh_eth_get_settings,
1891         .set_settings   = sh_eth_set_settings,
1892         .nway_reset     = sh_eth_nway_reset,
1893         .get_msglevel   = sh_eth_get_msglevel,
1894         .set_msglevel   = sh_eth_set_msglevel,
1895         .get_link       = ethtool_op_get_link,
1896         .get_strings    = sh_eth_get_strings,
1897         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
1898         .get_sset_count     = sh_eth_get_sset_count,
1899         .get_ringparam  = sh_eth_get_ringparam,
1900         .set_ringparam  = sh_eth_set_ringparam,
1901 };
1902
1903 /* network device open function */
1904 static int sh_eth_open(struct net_device *ndev)
1905 {
1906         int ret = 0;
1907         struct sh_eth_private *mdp = netdev_priv(ndev);
1908
1909         pm_runtime_get_sync(&mdp->pdev->dev);
1910
1911         napi_enable(&mdp->napi);
1912
1913         ret = request_irq(ndev->irq, sh_eth_interrupt,
1914                           mdp->cd->irq_flags, ndev->name, ndev);
1915         if (ret) {
1916                 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1917                 goto out_napi_off;
1918         }
1919
1920         /* Descriptor set */
1921         ret = sh_eth_ring_init(ndev);
1922         if (ret)
1923                 goto out_free_irq;
1924
1925         /* device init */
1926         ret = sh_eth_dev_init(ndev, true);
1927         if (ret)
1928                 goto out_free_irq;
1929
1930         /* PHY control start*/
1931         ret = sh_eth_phy_start(ndev);
1932         if (ret)
1933                 goto out_free_irq;
1934
1935         return ret;
1936
1937 out_free_irq:
1938         free_irq(ndev->irq, ndev);
1939 out_napi_off:
1940         napi_disable(&mdp->napi);
1941         pm_runtime_put_sync(&mdp->pdev->dev);
1942         return ret;
1943 }
1944
1945 /* Timeout function */
1946 static void sh_eth_tx_timeout(struct net_device *ndev)
1947 {
1948         struct sh_eth_private *mdp = netdev_priv(ndev);
1949         struct sh_eth_rxdesc *rxdesc;
1950         int i;
1951
1952         netif_stop_queue(ndev);
1953
1954         if (netif_msg_timer(mdp))
1955                 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1956                " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1957
1958         /* tx_errors count up */
1959         ndev->stats.tx_errors++;
1960
1961         /* Free all the skbuffs in the Rx queue. */
1962         for (i = 0; i < mdp->num_rx_ring; i++) {
1963                 rxdesc = &mdp->rx_ring[i];
1964                 rxdesc->status = 0;
1965                 rxdesc->addr = 0xBADF00D0;
1966                 if (mdp->rx_skbuff[i])
1967                         dev_kfree_skb(mdp->rx_skbuff[i]);
1968                 mdp->rx_skbuff[i] = NULL;
1969         }
1970         for (i = 0; i < mdp->num_tx_ring; i++) {
1971                 if (mdp->tx_skbuff[i])
1972                         dev_kfree_skb(mdp->tx_skbuff[i]);
1973                 mdp->tx_skbuff[i] = NULL;
1974         }
1975
1976         /* device init */
1977         sh_eth_dev_init(ndev, true);
1978 }
1979
1980 /* Packet transmit function */
1981 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1982 {
1983         struct sh_eth_private *mdp = netdev_priv(ndev);
1984         struct sh_eth_txdesc *txdesc;
1985         u32 entry;
1986         unsigned long flags;
1987
1988         spin_lock_irqsave(&mdp->lock, flags);
1989         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1990                 if (!sh_eth_txfree(ndev)) {
1991                         if (netif_msg_tx_queued(mdp))
1992                                 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1993                         netif_stop_queue(ndev);
1994                         spin_unlock_irqrestore(&mdp->lock, flags);
1995                         return NETDEV_TX_BUSY;
1996                 }
1997         }
1998         spin_unlock_irqrestore(&mdp->lock, flags);
1999
2000         entry = mdp->cur_tx % mdp->num_tx_ring;
2001         mdp->tx_skbuff[entry] = skb;
2002         txdesc = &mdp->tx_ring[entry];
2003         /* soft swap. */
2004         if (!mdp->cd->hw_swap)
2005                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2006                                  skb->len + 2);
2007         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2008                                       DMA_TO_DEVICE);
2009         if (skb->len < ETHERSMALL)
2010                 txdesc->buffer_length = ETHERSMALL;
2011         else
2012                 txdesc->buffer_length = skb->len;
2013
2014         if (entry >= mdp->num_tx_ring - 1)
2015                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2016         else
2017                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2018
2019         mdp->cur_tx++;
2020
2021         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2022                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2023
2024         return NETDEV_TX_OK;
2025 }
2026
2027 /* device close function */
2028 static int sh_eth_close(struct net_device *ndev)
2029 {
2030         struct sh_eth_private *mdp = netdev_priv(ndev);
2031
2032         netif_stop_queue(ndev);
2033
2034         /* Disable interrupts by clearing the interrupt mask. */
2035         sh_eth_write(ndev, 0x0000, EESIPR);
2036
2037         /* Stop the chip's Tx and Rx processes. */
2038         sh_eth_write(ndev, 0, EDTRR);
2039         sh_eth_write(ndev, 0, EDRRR);
2040
2041         /* PHY Disconnect */
2042         if (mdp->phydev) {
2043                 phy_stop(mdp->phydev);
2044                 phy_disconnect(mdp->phydev);
2045         }
2046
2047         free_irq(ndev->irq, ndev);
2048
2049         napi_disable(&mdp->napi);
2050
2051         /* Free all the skbuffs in the Rx queue. */
2052         sh_eth_ring_free(ndev);
2053
2054         /* free DMA buffer */
2055         sh_eth_free_dma_buffer(mdp);
2056
2057         pm_runtime_put_sync(&mdp->pdev->dev);
2058
2059         return 0;
2060 }
2061
2062 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2063 {
2064         struct sh_eth_private *mdp = netdev_priv(ndev);
2065
2066         pm_runtime_get_sync(&mdp->pdev->dev);
2067
2068         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2069         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
2070         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2071         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
2072         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2073         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
2074         if (sh_eth_is_gether(mdp)) {
2075                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2076                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
2077                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2078                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
2079         } else {
2080                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2081                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
2082         }
2083         pm_runtime_put_sync(&mdp->pdev->dev);
2084
2085         return &ndev->stats;
2086 }
2087
2088 /* ioctl to device function */
2089 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
2090                                 int cmd)
2091 {
2092         struct sh_eth_private *mdp = netdev_priv(ndev);
2093         struct phy_device *phydev = mdp->phydev;
2094
2095         if (!netif_running(ndev))
2096                 return -EINVAL;
2097
2098         if (!phydev)
2099                 return -ENODEV;
2100
2101         return phy_mii_ioctl(phydev, rq, cmd);
2102 }
2103
2104 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2105 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2106                                             int entry)
2107 {
2108         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2109 }
2110
2111 static u32 sh_eth_tsu_get_post_mask(int entry)
2112 {
2113         return 0x0f << (28 - ((entry % 8) * 4));
2114 }
2115
2116 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2117 {
2118         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2119 }
2120
2121 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2122                                              int entry)
2123 {
2124         struct sh_eth_private *mdp = netdev_priv(ndev);
2125         u32 tmp;
2126         void *reg_offset;
2127
2128         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2129         tmp = ioread32(reg_offset);
2130         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2131 }
2132
2133 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2134                                               int entry)
2135 {
2136         struct sh_eth_private *mdp = netdev_priv(ndev);
2137         u32 post_mask, ref_mask, tmp;
2138         void *reg_offset;
2139
2140         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2141         post_mask = sh_eth_tsu_get_post_mask(entry);
2142         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2143
2144         tmp = ioread32(reg_offset);
2145         iowrite32(tmp & ~post_mask, reg_offset);
2146
2147         /* If other port enables, the function returns "true" */
2148         return tmp & ref_mask;
2149 }
2150
2151 static int sh_eth_tsu_busy(struct net_device *ndev)
2152 {
2153         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2154         struct sh_eth_private *mdp = netdev_priv(ndev);
2155
2156         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2157                 udelay(10);
2158                 timeout--;
2159                 if (timeout <= 0) {
2160                         dev_err(&ndev->dev, "%s: timeout\n", __func__);
2161                         return -ETIMEDOUT;
2162                 }
2163         }
2164
2165         return 0;
2166 }
2167
2168 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2169                                   const u8 *addr)
2170 {
2171         u32 val;
2172
2173         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2174         iowrite32(val, reg);
2175         if (sh_eth_tsu_busy(ndev) < 0)
2176                 return -EBUSY;
2177
2178         val = addr[4] << 8 | addr[5];
2179         iowrite32(val, reg + 4);
2180         if (sh_eth_tsu_busy(ndev) < 0)
2181                 return -EBUSY;
2182
2183         return 0;
2184 }
2185
2186 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2187 {
2188         u32 val;
2189
2190         val = ioread32(reg);
2191         addr[0] = (val >> 24) & 0xff;
2192         addr[1] = (val >> 16) & 0xff;
2193         addr[2] = (val >> 8) & 0xff;
2194         addr[3] = val & 0xff;
2195         val = ioread32(reg + 4);
2196         addr[4] = (val >> 8) & 0xff;
2197         addr[5] = val & 0xff;
2198 }
2199
2200
2201 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2202 {
2203         struct sh_eth_private *mdp = netdev_priv(ndev);
2204         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2205         int i;
2206         u8 c_addr[ETH_ALEN];
2207
2208         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2209                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2210                 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2211                         return i;
2212         }
2213
2214         return -ENOENT;
2215 }
2216
2217 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2218 {
2219         u8 blank[ETH_ALEN];
2220         int entry;
2221
2222         memset(blank, 0, sizeof(blank));
2223         entry = sh_eth_tsu_find_entry(ndev, blank);
2224         return (entry < 0) ? -ENOMEM : entry;
2225 }
2226
2227 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2228                                               int entry)
2229 {
2230         struct sh_eth_private *mdp = netdev_priv(ndev);
2231         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2232         int ret;
2233         u8 blank[ETH_ALEN];
2234
2235         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2236                          ~(1 << (31 - entry)), TSU_TEN);
2237
2238         memset(blank, 0, sizeof(blank));
2239         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2240         if (ret < 0)
2241                 return ret;
2242         return 0;
2243 }
2244
2245 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2246 {
2247         struct sh_eth_private *mdp = netdev_priv(ndev);
2248         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2249         int i, ret;
2250
2251         if (!mdp->cd->tsu)
2252                 return 0;
2253
2254         i = sh_eth_tsu_find_entry(ndev, addr);
2255         if (i < 0) {
2256                 /* No entry found, create one */
2257                 i = sh_eth_tsu_find_empty(ndev);
2258                 if (i < 0)
2259                         return -ENOMEM;
2260                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2261                 if (ret < 0)
2262                         return ret;
2263
2264                 /* Enable the entry */
2265                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2266                                  (1 << (31 - i)), TSU_TEN);
2267         }
2268
2269         /* Entry found or created, enable POST */
2270         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2271
2272         return 0;
2273 }
2274
2275 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2276 {
2277         struct sh_eth_private *mdp = netdev_priv(ndev);
2278         int i, ret;
2279
2280         if (!mdp->cd->tsu)
2281                 return 0;
2282
2283         i = sh_eth_tsu_find_entry(ndev, addr);
2284         if (i) {
2285                 /* Entry found */
2286                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2287                         goto done;
2288
2289                 /* Disable the entry if both ports was disabled */
2290                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2291                 if (ret < 0)
2292                         return ret;
2293         }
2294 done:
2295         return 0;
2296 }
2297
2298 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2299 {
2300         struct sh_eth_private *mdp = netdev_priv(ndev);
2301         int i, ret;
2302
2303         if (unlikely(!mdp->cd->tsu))
2304                 return 0;
2305
2306         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2307                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2308                         continue;
2309
2310                 /* Disable the entry if both ports was disabled */
2311                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2312                 if (ret < 0)
2313                         return ret;
2314         }
2315
2316         return 0;
2317 }
2318
2319 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2320 {
2321         struct sh_eth_private *mdp = netdev_priv(ndev);
2322         u8 addr[ETH_ALEN];
2323         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2324         int i;
2325
2326         if (unlikely(!mdp->cd->tsu))
2327                 return;
2328
2329         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2330                 sh_eth_tsu_read_entry(reg_offset, addr);
2331                 if (is_multicast_ether_addr(addr))
2332                         sh_eth_tsu_del_entry(ndev, addr);
2333         }
2334 }
2335
2336 /* Multicast reception directions set */
2337 static void sh_eth_set_multicast_list(struct net_device *ndev)
2338 {
2339         struct sh_eth_private *mdp = netdev_priv(ndev);
2340         u32 ecmr_bits;
2341         int mcast_all = 0;
2342         unsigned long flags;
2343
2344         spin_lock_irqsave(&mdp->lock, flags);
2345         /*
2346          * Initial condition is MCT = 1, PRM = 0.
2347          * Depending on ndev->flags, set PRM or clear MCT
2348          */
2349         ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2350
2351         if (!(ndev->flags & IFF_MULTICAST)) {
2352                 sh_eth_tsu_purge_mcast(ndev);
2353                 mcast_all = 1;
2354         }
2355         if (ndev->flags & IFF_ALLMULTI) {
2356                 sh_eth_tsu_purge_mcast(ndev);
2357                 ecmr_bits &= ~ECMR_MCT;
2358                 mcast_all = 1;
2359         }
2360
2361         if (ndev->flags & IFF_PROMISC) {
2362                 sh_eth_tsu_purge_all(ndev);
2363                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2364         } else if (mdp->cd->tsu) {
2365                 struct netdev_hw_addr *ha;
2366                 netdev_for_each_mc_addr(ha, ndev) {
2367                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2368                                 continue;
2369
2370                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2371                                 if (!mcast_all) {
2372                                         sh_eth_tsu_purge_mcast(ndev);
2373                                         ecmr_bits &= ~ECMR_MCT;
2374                                         mcast_all = 1;
2375                                 }
2376                         }
2377                 }
2378         } else {
2379                 /* Normal, unicast/broadcast-only mode. */
2380                 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2381         }
2382
2383         /* update the ethernet mode */
2384         sh_eth_write(ndev, ecmr_bits, ECMR);
2385
2386         spin_unlock_irqrestore(&mdp->lock, flags);
2387 }
2388
2389 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2390 {
2391         if (!mdp->port)
2392                 return TSU_VTAG0;
2393         else
2394                 return TSU_VTAG1;
2395 }
2396
2397 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2398                                   __be16 proto, u16 vid)
2399 {
2400         struct sh_eth_private *mdp = netdev_priv(ndev);
2401         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2402
2403         if (unlikely(!mdp->cd->tsu))
2404                 return -EPERM;
2405
2406         /* No filtering if vid = 0 */
2407         if (!vid)
2408                 return 0;
2409
2410         mdp->vlan_num_ids++;
2411
2412         /*
2413          * The controller has one VLAN tag HW filter. So, if the filter is
2414          * already enabled, the driver disables it and the filte
2415          */
2416         if (mdp->vlan_num_ids > 1) {
2417                 /* disable VLAN filter */
2418                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2419                 return 0;
2420         }
2421
2422         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2423                          vtag_reg_index);
2424
2425         return 0;
2426 }
2427
2428 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2429                                    __be16 proto, u16 vid)
2430 {
2431         struct sh_eth_private *mdp = netdev_priv(ndev);
2432         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2433
2434         if (unlikely(!mdp->cd->tsu))
2435                 return -EPERM;
2436
2437         /* No filtering if vid = 0 */
2438         if (!vid)
2439                 return 0;
2440
2441         mdp->vlan_num_ids--;
2442         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2443
2444         return 0;
2445 }
2446
2447 /* SuperH's TSU register init function */
2448 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2449 {
2450         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2451         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2452         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2453         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2454         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2455         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2456         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2457         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2458         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2459         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2460         if (sh_eth_is_gether(mdp)) {
2461                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2462                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2463         } else {
2464                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2465                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2466         }
2467         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2468         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2469         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2470         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2471         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2472         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2473         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2474 }
2475
2476 /* MDIO bus release function */
2477 static int sh_mdio_release(struct net_device *ndev)
2478 {
2479         struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2480
2481         /* unregister mdio bus */
2482         mdiobus_unregister(bus);
2483
2484         /* remove mdio bus info from net_device */
2485         dev_set_drvdata(&ndev->dev, NULL);
2486
2487         /* free bitbang info */
2488         free_mdio_bitbang(bus);
2489
2490         return 0;
2491 }
2492
2493 /* MDIO bus init function */
2494 static int sh_mdio_init(struct net_device *ndev, int id,
2495                         struct sh_eth_plat_data *pd)
2496 {
2497         int ret, i;
2498         struct bb_info *bitbang;
2499         struct sh_eth_private *mdp = netdev_priv(ndev);
2500
2501         /* create bit control struct for PHY */
2502         bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2503                                GFP_KERNEL);
2504         if (!bitbang) {
2505                 ret = -ENOMEM;
2506                 goto out;
2507         }
2508
2509         /* bitbang init */
2510         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2511         bitbang->set_gate = pd->set_mdio_gate;
2512         bitbang->mdi_msk = PIR_MDI;
2513         bitbang->mdo_msk = PIR_MDO;
2514         bitbang->mmd_msk = PIR_MMD;
2515         bitbang->mdc_msk = PIR_MDC;
2516         bitbang->ctrl.ops = &bb_ops;
2517
2518         /* MII controller setting */
2519         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2520         if (!mdp->mii_bus) {
2521                 ret = -ENOMEM;
2522                 goto out;
2523         }
2524
2525         /* Hook up MII support for ethtool */
2526         mdp->mii_bus->name = "sh_mii";
2527         mdp->mii_bus->parent = &ndev->dev;
2528         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2529                 mdp->pdev->name, id);
2530
2531         /* PHY IRQ */
2532         mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2533                                          sizeof(int) * PHY_MAX_ADDR,
2534                                          GFP_KERNEL);
2535         if (!mdp->mii_bus->irq) {
2536                 ret = -ENOMEM;
2537                 goto out_free_bus;
2538         }
2539
2540         for (i = 0; i < PHY_MAX_ADDR; i++)
2541                 mdp->mii_bus->irq[i] = PHY_POLL;
2542         if (pd->phy_irq > 0)
2543                 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2544
2545         /* register mdio bus */
2546         ret = mdiobus_register(mdp->mii_bus);
2547         if (ret)
2548                 goto out_free_bus;
2549
2550         dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2551
2552         return 0;
2553
2554 out_free_bus:
2555         free_mdio_bitbang(mdp->mii_bus);
2556
2557 out:
2558         return ret;
2559 }
2560
2561 static const u16 *sh_eth_get_register_offset(int register_type)
2562 {
2563         const u16 *reg_offset = NULL;
2564
2565         switch (register_type) {
2566         case SH_ETH_REG_GIGABIT:
2567                 reg_offset = sh_eth_offset_gigabit;
2568                 break;
2569         case SH_ETH_REG_FAST_RCAR:
2570                 reg_offset = sh_eth_offset_fast_rcar;
2571                 break;
2572         case SH_ETH_REG_FAST_SH4:
2573                 reg_offset = sh_eth_offset_fast_sh4;
2574                 break;
2575         case SH_ETH_REG_FAST_SH3_SH2:
2576                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2577                 break;
2578         default:
2579                 pr_err("Unknown register type (%d)\n", register_type);
2580                 break;
2581         }
2582
2583         return reg_offset;
2584 }
2585
2586 static const struct net_device_ops sh_eth_netdev_ops = {
2587         .ndo_open               = sh_eth_open,
2588         .ndo_stop               = sh_eth_close,
2589         .ndo_start_xmit         = sh_eth_start_xmit,
2590         .ndo_get_stats          = sh_eth_get_stats,
2591         .ndo_tx_timeout         = sh_eth_tx_timeout,
2592         .ndo_do_ioctl           = sh_eth_do_ioctl,
2593         .ndo_validate_addr      = eth_validate_addr,
2594         .ndo_set_mac_address    = eth_mac_addr,
2595         .ndo_change_mtu         = eth_change_mtu,
2596 };
2597
2598 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2599         .ndo_open               = sh_eth_open,
2600         .ndo_stop               = sh_eth_close,
2601         .ndo_start_xmit         = sh_eth_start_xmit,
2602         .ndo_get_stats          = sh_eth_get_stats,
2603         .ndo_set_rx_mode        = sh_eth_set_multicast_list,
2604         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2605         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2606         .ndo_tx_timeout         = sh_eth_tx_timeout,
2607         .ndo_do_ioctl           = sh_eth_do_ioctl,
2608         .ndo_validate_addr      = eth_validate_addr,
2609         .ndo_set_mac_address    = eth_mac_addr,
2610         .ndo_change_mtu         = eth_change_mtu,
2611 };
2612
2613 static int sh_eth_drv_probe(struct platform_device *pdev)
2614 {
2615         int ret, devno = 0;
2616         struct resource *res;
2617         struct net_device *ndev = NULL;
2618         struct sh_eth_private *mdp = NULL;
2619         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2620         const struct platform_device_id *id = platform_get_device_id(pdev);
2621
2622         /* get base addr */
2623         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2624         if (unlikely(res == NULL)) {
2625                 dev_err(&pdev->dev, "invalid resource\n");
2626                 ret = -EINVAL;
2627                 goto out;
2628         }
2629
2630         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2631         if (!ndev) {
2632                 ret = -ENOMEM;
2633                 goto out;
2634         }
2635
2636         /* The sh Ether-specific entries in the device structure. */
2637         ndev->base_addr = res->start;
2638         devno = pdev->id;
2639         if (devno < 0)
2640                 devno = 0;
2641
2642         ndev->dma = -1;
2643         ret = platform_get_irq(pdev, 0);
2644         if (ret < 0) {
2645                 ret = -ENODEV;
2646                 goto out_release;
2647         }
2648         ndev->irq = ret;
2649
2650         SET_NETDEV_DEV(ndev, &pdev->dev);
2651
2652         mdp = netdev_priv(ndev);
2653         mdp->num_tx_ring = TX_RING_SIZE;
2654         mdp->num_rx_ring = RX_RING_SIZE;
2655         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2656         if (IS_ERR(mdp->addr)) {
2657                 ret = PTR_ERR(mdp->addr);
2658                 goto out_release;
2659         }
2660
2661         spin_lock_init(&mdp->lock);
2662         mdp->pdev = pdev;
2663         pm_runtime_enable(&pdev->dev);
2664         pm_runtime_resume(&pdev->dev);
2665
2666         if (!pd) {
2667                 dev_err(&pdev->dev, "no platform data\n");
2668                 ret = -EINVAL;
2669                 goto out_release;
2670         }
2671
2672         /* get PHY ID */
2673         mdp->phy_id = pd->phy;
2674         mdp->phy_interface = pd->phy_interface;
2675         /* EDMAC endian */
2676         mdp->edmac_endian = pd->edmac_endian;
2677         mdp->no_ether_link = pd->no_ether_link;
2678         mdp->ether_link_active_low = pd->ether_link_active_low;
2679
2680         /* set cpu data */
2681         mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2682         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2683         sh_eth_set_default_cpu_data(mdp->cd);
2684
2685         /* set function */
2686         if (mdp->cd->tsu)
2687                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2688         else
2689                 ndev->netdev_ops = &sh_eth_netdev_ops;
2690         SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2691         ndev->watchdog_timeo = TX_TIMEOUT;
2692
2693         /* debug message level */
2694         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2695
2696         /* read and set MAC address */
2697         read_mac_address(ndev, pd->mac_addr);
2698         if (!is_valid_ether_addr(ndev->dev_addr)) {
2699                 dev_warn(&pdev->dev,
2700                          "no valid MAC address supplied, using a random one.\n");
2701                 eth_hw_addr_random(ndev);
2702         }
2703
2704         /* ioremap the TSU registers */
2705         if (mdp->cd->tsu) {
2706                 struct resource *rtsu;
2707                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2708                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2709                 if (IS_ERR(mdp->tsu_addr)) {
2710                         ret = PTR_ERR(mdp->tsu_addr);
2711                         goto out_release;
2712                 }
2713                 mdp->port = devno % 2;
2714                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2715         }
2716
2717         /* initialize first or needed device */
2718         if (!devno || pd->needs_init) {
2719                 if (mdp->cd->chip_reset)
2720                         mdp->cd->chip_reset(ndev);
2721
2722                 if (mdp->cd->tsu) {
2723                         /* TSU init (Init only)*/
2724                         sh_eth_tsu_init(mdp);
2725                 }
2726         }
2727
2728         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2729
2730         /* network device register */
2731         ret = register_netdev(ndev);
2732         if (ret)
2733                 goto out_napi_del;
2734
2735         /* mdio bus init */
2736         ret = sh_mdio_init(ndev, pdev->id, pd);
2737         if (ret)
2738                 goto out_unregister;
2739
2740         /* print device information */
2741         pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2742                (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2743
2744         platform_set_drvdata(pdev, ndev);
2745
2746         return ret;
2747
2748 out_unregister:
2749         unregister_netdev(ndev);
2750
2751 out_napi_del:
2752         netif_napi_del(&mdp->napi);
2753
2754 out_release:
2755         /* net_dev free */
2756         if (ndev)
2757                 free_netdev(ndev);
2758
2759 out:
2760         return ret;
2761 }
2762
2763 static int sh_eth_drv_remove(struct platform_device *pdev)
2764 {
2765         struct net_device *ndev = platform_get_drvdata(pdev);
2766         struct sh_eth_private *mdp = netdev_priv(ndev);
2767
2768         sh_mdio_release(ndev);
2769         unregister_netdev(ndev);
2770         netif_napi_del(&mdp->napi);
2771         pm_runtime_disable(&pdev->dev);
2772         free_netdev(ndev);
2773
2774         return 0;
2775 }
2776
2777 #ifdef CONFIG_PM
2778 static int sh_eth_runtime_nop(struct device *dev)
2779 {
2780         /*
2781          * Runtime PM callback shared between ->runtime_suspend()
2782          * and ->runtime_resume(). Simply returns success.
2783          *
2784          * This driver re-initializes all registers after
2785          * pm_runtime_get_sync() anyway so there is no need
2786          * to save and restore registers here.
2787          */
2788         return 0;
2789 }
2790
2791 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2792         .runtime_suspend = sh_eth_runtime_nop,
2793         .runtime_resume = sh_eth_runtime_nop,
2794 };
2795 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2796 #else
2797 #define SH_ETH_PM_OPS NULL
2798 #endif
2799
2800 static struct platform_device_id sh_eth_id_table[] = {
2801         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2802         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2803         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2804         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2805         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2806         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2807         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2808         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2809         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
2810         { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
2811         { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
2812         { }
2813 };
2814 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2815
2816 static struct platform_driver sh_eth_driver = {
2817         .probe = sh_eth_drv_probe,
2818         .remove = sh_eth_drv_remove,
2819         .id_table = sh_eth_id_table,
2820         .driver = {
2821                    .name = CARDNAME,
2822                    .pm = SH_ETH_PM_OPS,
2823         },
2824 };
2825
2826 module_platform_driver(sh_eth_driver);
2827
2828 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2829 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2830 MODULE_LICENSE("GPL v2");