2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Cogent Embedded, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/spinlock.h>
28 #include <linux/interrupt.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/mdio-bitbang.h>
34 #include <linux/netdevice.h>
35 #include <linux/phy.h>
36 #include <linux/cache.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/slab.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42 #include <linux/clk.h>
43 #include <linux/sh_eth.h>
47 #define SH_ETH_DEF_MSG_ENABLE \
53 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
107 [TSU_CTRST] = 0x0004,
108 [TSU_FWEN0] = 0x0010,
109 [TSU_FWEN1] = 0x0014,
111 [TSU_BSYSL0] = 0x0020,
112 [TSU_BSYSL1] = 0x0024,
113 [TSU_PRISL0] = 0x0028,
114 [TSU_PRISL1] = 0x002c,
115 [TSU_FWSL0] = 0x0030,
116 [TSU_FWSL1] = 0x0034,
117 [TSU_FWSLC] = 0x0038,
118 [TSU_QTAG0] = 0x0040,
119 [TSU_QTAG1] = 0x0044,
121 [TSU_FWINMK] = 0x0054,
122 [TSU_ADQT0] = 0x0048,
123 [TSU_ADQT1] = 0x004c,
124 [TSU_VTAG0] = 0x0058,
125 [TSU_VTAG1] = 0x005c,
126 [TSU_ADSBSY] = 0x0060,
128 [TSU_POST1] = 0x0070,
129 [TSU_POST2] = 0x0074,
130 [TSU_POST3] = 0x0078,
131 [TSU_POST4] = 0x007c,
132 [TSU_ADRH0] = 0x0100,
133 [TSU_ADRL0] = 0x0104,
134 [TSU_ADRH31] = 0x01f8,
135 [TSU_ADRL31] = 0x01fc,
151 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
197 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
249 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
275 [TSU_CTRST] = 0x0004,
276 [TSU_FWEN0] = 0x0010,
277 [TSU_FWEN1] = 0x0014,
279 [TSU_BSYSL0] = 0x0020,
280 [TSU_BSYSL1] = 0x0024,
281 [TSU_PRISL0] = 0x0028,
282 [TSU_PRISL1] = 0x002c,
283 [TSU_FWSL0] = 0x0030,
284 [TSU_FWSL1] = 0x0034,
285 [TSU_FWSLC] = 0x0038,
286 [TSU_QTAGM0] = 0x0040,
287 [TSU_QTAGM1] = 0x0044,
288 [TSU_ADQT0] = 0x0048,
289 [TSU_ADQT1] = 0x004c,
291 [TSU_FWINMK] = 0x0054,
292 [TSU_ADSBSY] = 0x0060,
294 [TSU_POST1] = 0x0070,
295 [TSU_POST2] = 0x0074,
296 [TSU_POST3] = 0x0078,
297 [TSU_POST4] = 0x007c,
312 [TSU_ADRH0] = 0x0100,
313 [TSU_ADRL0] = 0x0104,
314 [TSU_ADRL31] = 0x01fc,
317 static int sh_eth_is_gether(struct sh_eth_private *mdp)
319 if (mdp->reg_offset == sh_eth_offset_gigabit)
325 static void sh_eth_select_mii(struct net_device *ndev)
328 struct sh_eth_private *mdp = netdev_priv(ndev);
330 switch (mdp->phy_interface) {
331 case PHY_INTERFACE_MODE_GMII:
334 case PHY_INTERFACE_MODE_MII:
337 case PHY_INTERFACE_MODE_RMII:
341 pr_warn("PHY interface mode was not setup. Set to MII.\n");
346 sh_eth_write(ndev, value, RMII_MII);
349 static void sh_eth_set_duplex(struct net_device *ndev)
351 struct sh_eth_private *mdp = netdev_priv(ndev);
353 if (mdp->duplex) /* Full */
354 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
356 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
359 /* There is CPU dependent code */
360 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
362 struct sh_eth_private *mdp = netdev_priv(ndev);
364 switch (mdp->speed) {
365 case 10: /* 10BASE */
366 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
368 case 100:/* 100BASE */
369 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
377 static struct sh_eth_cpu_data r8a777x_data = {
378 .set_duplex = sh_eth_set_duplex,
379 .set_rate = sh_eth_set_rate_r8a777x,
381 .register_type = SH_ETH_REG_FAST_RCAR,
383 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
384 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
385 .eesipr_value = 0x01ff009f,
387 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
388 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
389 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
399 static struct sh_eth_cpu_data r8a7790_data = {
400 .set_duplex = sh_eth_set_duplex,
401 .set_rate = sh_eth_set_rate_r8a777x,
403 .register_type = SH_ETH_REG_FAST_RCAR,
405 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
406 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
407 .eesipr_value = 0x01ff009f,
409 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
410 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
411 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
421 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
423 struct sh_eth_private *mdp = netdev_priv(ndev);
425 switch (mdp->speed) {
426 case 10: /* 10BASE */
427 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
429 case 100:/* 100BASE */
430 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
438 static struct sh_eth_cpu_data sh7724_data = {
439 .set_duplex = sh_eth_set_duplex,
440 .set_rate = sh_eth_set_rate_sh7724,
442 .register_type = SH_ETH_REG_FAST_SH4,
444 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
445 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
446 .eesipr_value = 0x01ff009f,
448 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
449 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
450 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
458 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
461 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
463 struct sh_eth_private *mdp = netdev_priv(ndev);
465 switch (mdp->speed) {
466 case 10: /* 10BASE */
467 sh_eth_write(ndev, 0, RTRATE);
469 case 100:/* 100BASE */
470 sh_eth_write(ndev, 1, RTRATE);
478 static struct sh_eth_cpu_data sh7757_data = {
479 .set_duplex = sh_eth_set_duplex,
480 .set_rate = sh_eth_set_rate_sh7757,
482 .register_type = SH_ETH_REG_FAST_SH4,
484 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
485 .rmcr_value = 0x00000001,
487 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
488 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
489 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
492 .irq_flags = IRQF_SHARED,
499 .rpadir_value = 2 << 16,
502 #define SH_GIGA_ETH_BASE 0xfee00000UL
503 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
504 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
505 static void sh_eth_chip_reset_giga(struct net_device *ndev)
508 unsigned long mahr[2], malr[2];
510 /* save MAHR and MALR */
511 for (i = 0; i < 2; i++) {
512 malr[i] = ioread32((void *)GIGA_MALR(i));
513 mahr[i] = ioread32((void *)GIGA_MAHR(i));
517 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
520 /* restore MAHR and MALR */
521 for (i = 0; i < 2; i++) {
522 iowrite32(malr[i], (void *)GIGA_MALR(i));
523 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
527 static void sh_eth_set_rate_giga(struct net_device *ndev)
529 struct sh_eth_private *mdp = netdev_priv(ndev);
531 switch (mdp->speed) {
532 case 10: /* 10BASE */
533 sh_eth_write(ndev, 0x00000000, GECMR);
535 case 100:/* 100BASE */
536 sh_eth_write(ndev, 0x00000010, GECMR);
538 case 1000: /* 1000BASE */
539 sh_eth_write(ndev, 0x00000020, GECMR);
546 /* SH7757(GETHERC) */
547 static struct sh_eth_cpu_data sh7757_data_giga = {
548 .chip_reset = sh_eth_chip_reset_giga,
549 .set_duplex = sh_eth_set_duplex,
550 .set_rate = sh_eth_set_rate_giga,
552 .register_type = SH_ETH_REG_GIGABIT,
554 .ecsr_value = ECSR_ICD | ECSR_MPD,
555 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
556 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
558 .tx_check = EESR_TC1 | EESR_FTC,
559 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
560 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
562 .fdr_value = 0x0000072f,
563 .rmcr_value = 0x00000001,
565 .irq_flags = IRQF_SHARED,
572 .rpadir_value = 2 << 16,
578 static void sh_eth_chip_reset(struct net_device *ndev)
580 struct sh_eth_private *mdp = netdev_priv(ndev);
583 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
587 static void sh_eth_set_rate_gether(struct net_device *ndev)
589 struct sh_eth_private *mdp = netdev_priv(ndev);
591 switch (mdp->speed) {
592 case 10: /* 10BASE */
593 sh_eth_write(ndev, GECMR_10, GECMR);
595 case 100:/* 100BASE */
596 sh_eth_write(ndev, GECMR_100, GECMR);
598 case 1000: /* 1000BASE */
599 sh_eth_write(ndev, GECMR_1000, GECMR);
607 static struct sh_eth_cpu_data sh7734_data = {
608 .chip_reset = sh_eth_chip_reset,
609 .set_duplex = sh_eth_set_duplex,
610 .set_rate = sh_eth_set_rate_gether,
612 .register_type = SH_ETH_REG_GIGABIT,
614 .ecsr_value = ECSR_ICD | ECSR_MPD,
615 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
616 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
618 .tx_check = EESR_TC1 | EESR_FTC,
619 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
620 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
636 static struct sh_eth_cpu_data sh7763_data = {
637 .chip_reset = sh_eth_chip_reset,
638 .set_duplex = sh_eth_set_duplex,
639 .set_rate = sh_eth_set_rate_gether,
641 .register_type = SH_ETH_REG_GIGABIT,
643 .ecsr_value = ECSR_ICD | ECSR_MPD,
644 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
645 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
647 .tx_check = EESR_TC1 | EESR_FTC,
648 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
649 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
660 .irq_flags = IRQF_SHARED,
663 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
665 struct sh_eth_private *mdp = netdev_priv(ndev);
668 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
671 sh_eth_select_mii(ndev);
675 static struct sh_eth_cpu_data r8a7740_data = {
676 .chip_reset = sh_eth_chip_reset_r8a7740,
677 .set_duplex = sh_eth_set_duplex,
678 .set_rate = sh_eth_set_rate_gether,
680 .register_type = SH_ETH_REG_GIGABIT,
682 .ecsr_value = ECSR_ICD | ECSR_MPD,
683 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
684 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
686 .tx_check = EESR_TC1 | EESR_FTC,
687 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
688 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
703 static struct sh_eth_cpu_data sh7619_data = {
704 .register_type = SH_ETH_REG_FAST_SH3_SH2,
706 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
714 static struct sh_eth_cpu_data sh771x_data = {
715 .register_type = SH_ETH_REG_FAST_SH3_SH2,
717 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
721 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
724 cd->ecsr_value = DEFAULT_ECSR_INIT;
726 if (!cd->ecsipr_value)
727 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
729 if (!cd->fcftr_value)
730 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
731 DEFAULT_FIFO_F_D_RFD;
734 cd->fdr_value = DEFAULT_FDR_INIT;
737 cd->rmcr_value = DEFAULT_RMCR_VALUE;
740 cd->tx_check = DEFAULT_TX_CHECK;
742 if (!cd->eesr_err_check)
743 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
746 static int sh_eth_check_reset(struct net_device *ndev)
752 if (!(sh_eth_read(ndev, EDMR) & 0x3))
758 pr_err("Device reset failed\n");
764 static int sh_eth_reset(struct net_device *ndev)
766 struct sh_eth_private *mdp = netdev_priv(ndev);
769 if (sh_eth_is_gether(mdp)) {
770 sh_eth_write(ndev, EDSR_ENALL, EDSR);
771 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
774 ret = sh_eth_check_reset(ndev);
779 sh_eth_write(ndev, 0x0, TDLAR);
780 sh_eth_write(ndev, 0x0, TDFAR);
781 sh_eth_write(ndev, 0x0, TDFXR);
782 sh_eth_write(ndev, 0x0, TDFFR);
783 sh_eth_write(ndev, 0x0, RDLAR);
784 sh_eth_write(ndev, 0x0, RDFAR);
785 sh_eth_write(ndev, 0x0, RDFXR);
786 sh_eth_write(ndev, 0x0, RDFFR);
788 /* Reset HW CRC register */
790 sh_eth_write(ndev, 0x0, CSMR);
792 /* Select MII mode */
793 if (mdp->cd->select_mii)
794 sh_eth_select_mii(ndev);
796 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
799 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
807 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
808 static void sh_eth_set_receive_align(struct sk_buff *skb)
812 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
814 skb_reserve(skb, reserve);
817 static void sh_eth_set_receive_align(struct sk_buff *skb)
819 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
824 /* CPU <-> EDMAC endian convert */
825 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
827 switch (mdp->edmac_endian) {
828 case EDMAC_LITTLE_ENDIAN:
829 return cpu_to_le32(x);
830 case EDMAC_BIG_ENDIAN:
831 return cpu_to_be32(x);
836 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
838 switch (mdp->edmac_endian) {
839 case EDMAC_LITTLE_ENDIAN:
840 return le32_to_cpu(x);
841 case EDMAC_BIG_ENDIAN:
842 return be32_to_cpu(x);
848 * Program the hardware MAC address from dev->dev_addr.
850 static void update_mac_address(struct net_device *ndev)
853 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
854 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
856 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
860 * Get MAC address from SuperH MAC address register
862 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
863 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
864 * When you want use this device, you must set MAC address in bootloader.
867 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
869 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
870 memcpy(ndev->dev_addr, mac, 6);
872 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
873 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
874 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
875 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
876 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
877 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
881 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
883 if (sh_eth_is_gether(mdp))
884 return EDTRR_TRNS_GETHER;
886 return EDTRR_TRNS_ETHER;
890 void (*set_gate)(void *addr);
891 struct mdiobb_ctrl ctrl;
893 u32 mmd_msk;/* MMD */
900 static void bb_set(void *addr, u32 msk)
902 iowrite32(ioread32(addr) | msk, addr);
906 static void bb_clr(void *addr, u32 msk)
908 iowrite32((ioread32(addr) & ~msk), addr);
912 static int bb_read(void *addr, u32 msk)
914 return (ioread32(addr) & msk) != 0;
917 /* Data I/O pin control */
918 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
920 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
922 if (bitbang->set_gate)
923 bitbang->set_gate(bitbang->addr);
926 bb_set(bitbang->addr, bitbang->mmd_msk);
928 bb_clr(bitbang->addr, bitbang->mmd_msk);
932 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
934 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
936 if (bitbang->set_gate)
937 bitbang->set_gate(bitbang->addr);
940 bb_set(bitbang->addr, bitbang->mdo_msk);
942 bb_clr(bitbang->addr, bitbang->mdo_msk);
946 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
948 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
950 if (bitbang->set_gate)
951 bitbang->set_gate(bitbang->addr);
953 return bb_read(bitbang->addr, bitbang->mdi_msk);
956 /* MDC pin control */
957 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
959 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
961 if (bitbang->set_gate)
962 bitbang->set_gate(bitbang->addr);
965 bb_set(bitbang->addr, bitbang->mdc_msk);
967 bb_clr(bitbang->addr, bitbang->mdc_msk);
970 /* mdio bus control struct */
971 static struct mdiobb_ops bb_ops = {
972 .owner = THIS_MODULE,
973 .set_mdc = sh_mdc_ctrl,
974 .set_mdio_dir = sh_mmd_ctrl,
975 .set_mdio_data = sh_set_mdio,
976 .get_mdio_data = sh_get_mdio,
979 /* free skb and descriptor buffer */
980 static void sh_eth_ring_free(struct net_device *ndev)
982 struct sh_eth_private *mdp = netdev_priv(ndev);
985 /* Free Rx skb ringbuffer */
986 if (mdp->rx_skbuff) {
987 for (i = 0; i < mdp->num_rx_ring; i++) {
988 if (mdp->rx_skbuff[i])
989 dev_kfree_skb(mdp->rx_skbuff[i]);
992 kfree(mdp->rx_skbuff);
993 mdp->rx_skbuff = NULL;
995 /* Free Tx skb ringbuffer */
996 if (mdp->tx_skbuff) {
997 for (i = 0; i < mdp->num_tx_ring; i++) {
998 if (mdp->tx_skbuff[i])
999 dev_kfree_skb(mdp->tx_skbuff[i]);
1002 kfree(mdp->tx_skbuff);
1003 mdp->tx_skbuff = NULL;
1006 /* format skb and descriptor buffer */
1007 static void sh_eth_ring_format(struct net_device *ndev)
1009 struct sh_eth_private *mdp = netdev_priv(ndev);
1011 struct sk_buff *skb;
1012 struct sh_eth_rxdesc *rxdesc = NULL;
1013 struct sh_eth_txdesc *txdesc = NULL;
1014 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1015 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1017 mdp->cur_rx = mdp->cur_tx = 0;
1018 mdp->dirty_rx = mdp->dirty_tx = 0;
1020 memset(mdp->rx_ring, 0, rx_ringsize);
1022 /* build Rx ring buffer */
1023 for (i = 0; i < mdp->num_rx_ring; i++) {
1025 mdp->rx_skbuff[i] = NULL;
1026 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1027 mdp->rx_skbuff[i] = skb;
1030 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1032 sh_eth_set_receive_align(skb);
1035 rxdesc = &mdp->rx_ring[i];
1036 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1037 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1039 /* The size of the buffer is 16 byte boundary. */
1040 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1041 /* Rx descriptor address set */
1043 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1044 if (sh_eth_is_gether(mdp))
1045 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1049 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1051 /* Mark the last entry as wrapping the ring. */
1052 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1054 memset(mdp->tx_ring, 0, tx_ringsize);
1056 /* build Tx ring buffer */
1057 for (i = 0; i < mdp->num_tx_ring; i++) {
1058 mdp->tx_skbuff[i] = NULL;
1059 txdesc = &mdp->tx_ring[i];
1060 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1061 txdesc->buffer_length = 0;
1063 /* Tx descriptor address set */
1064 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1065 if (sh_eth_is_gether(mdp))
1066 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1070 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1073 /* Get skb and descriptor buffer */
1074 static int sh_eth_ring_init(struct net_device *ndev)
1076 struct sh_eth_private *mdp = netdev_priv(ndev);
1077 int rx_ringsize, tx_ringsize, ret = 0;
1080 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1081 * card needs room to do 8 byte alignment, +2 so we can reserve
1082 * the first 2 bytes, and +16 gets room for the status word from the
1085 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1086 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1087 if (mdp->cd->rpadir)
1088 mdp->rx_buf_sz += NET_IP_ALIGN;
1090 /* Allocate RX and TX skb rings */
1091 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1092 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1093 if (!mdp->rx_skbuff) {
1098 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1099 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1100 if (!mdp->tx_skbuff) {
1105 /* Allocate all Rx descriptors. */
1106 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1107 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1109 if (!mdp->rx_ring) {
1111 goto desc_ring_free;
1116 /* Allocate all Tx descriptors. */
1117 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1118 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1120 if (!mdp->tx_ring) {
1122 goto desc_ring_free;
1127 /* free DMA buffer */
1128 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1131 /* Free Rx and Tx skb ring buffer */
1132 sh_eth_ring_free(ndev);
1133 mdp->tx_ring = NULL;
1134 mdp->rx_ring = NULL;
1139 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1144 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1145 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1147 mdp->rx_ring = NULL;
1151 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1152 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1154 mdp->tx_ring = NULL;
1158 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1161 struct sh_eth_private *mdp = netdev_priv(ndev);
1165 ret = sh_eth_reset(ndev);
1169 if (mdp->cd->rmiimode)
1170 sh_eth_write(ndev, 0x1, RMIIMODE);
1172 /* Descriptor format */
1173 sh_eth_ring_format(ndev);
1174 if (mdp->cd->rpadir)
1175 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1177 /* all sh_eth int mask */
1178 sh_eth_write(ndev, 0, EESIPR);
1180 #if defined(__LITTLE_ENDIAN)
1181 if (mdp->cd->hw_swap)
1182 sh_eth_write(ndev, EDMR_EL, EDMR);
1185 sh_eth_write(ndev, 0, EDMR);
1188 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1189 sh_eth_write(ndev, 0, TFTR);
1191 /* Frame recv control */
1192 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
1194 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1197 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1199 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1201 if (!mdp->cd->no_trimd)
1202 sh_eth_write(ndev, 0, TRIMD);
1204 /* Recv frame limit set register */
1205 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1208 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1210 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1212 /* PAUSE Prohibition */
1213 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1214 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1216 sh_eth_write(ndev, val, ECMR);
1218 if (mdp->cd->set_rate)
1219 mdp->cd->set_rate(ndev);
1221 /* E-MAC Status Register clear */
1222 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1224 /* E-MAC Interrupt Enable register */
1226 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1228 /* Set MAC address */
1229 update_mac_address(ndev);
1233 sh_eth_write(ndev, APR_AP, APR);
1235 sh_eth_write(ndev, MPR_MP, MPR);
1236 if (mdp->cd->tpauser)
1237 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1240 /* Setting the Rx mode will start the Rx process. */
1241 sh_eth_write(ndev, EDRRR_R, EDRRR);
1243 netif_start_queue(ndev);
1250 /* free Tx skb function */
1251 static int sh_eth_txfree(struct net_device *ndev)
1253 struct sh_eth_private *mdp = netdev_priv(ndev);
1254 struct sh_eth_txdesc *txdesc;
1258 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1259 entry = mdp->dirty_tx % mdp->num_tx_ring;
1260 txdesc = &mdp->tx_ring[entry];
1261 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1263 /* Free the original skb. */
1264 if (mdp->tx_skbuff[entry]) {
1265 dma_unmap_single(&ndev->dev, txdesc->addr,
1266 txdesc->buffer_length, DMA_TO_DEVICE);
1267 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1268 mdp->tx_skbuff[entry] = NULL;
1271 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1272 if (entry >= mdp->num_tx_ring - 1)
1273 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1275 ndev->stats.tx_packets++;
1276 ndev->stats.tx_bytes += txdesc->buffer_length;
1281 /* Packet receive function */
1282 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1284 struct sh_eth_private *mdp = netdev_priv(ndev);
1285 struct sh_eth_rxdesc *rxdesc;
1287 int entry = mdp->cur_rx % mdp->num_rx_ring;
1288 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1289 struct sk_buff *skb;
1294 rxdesc = &mdp->rx_ring[entry];
1295 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1296 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1297 pkt_len = rxdesc->frame_length;
1308 if (!(desc_status & RDFEND))
1309 ndev->stats.rx_length_errors++;
1312 * In case of almost all GETHER/ETHERs, the Receive Frame State
1313 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1314 * bit 0. However, in case of the R8A7740's GETHER, the RFS
1315 * bits are from bit 25 to bit 16. So, the driver needs right
1318 if (mdp->cd->shift_rd0)
1321 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1322 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1323 ndev->stats.rx_errors++;
1324 if (desc_status & RD_RFS1)
1325 ndev->stats.rx_crc_errors++;
1326 if (desc_status & RD_RFS2)
1327 ndev->stats.rx_frame_errors++;
1328 if (desc_status & RD_RFS3)
1329 ndev->stats.rx_length_errors++;
1330 if (desc_status & RD_RFS4)
1331 ndev->stats.rx_length_errors++;
1332 if (desc_status & RD_RFS6)
1333 ndev->stats.rx_missed_errors++;
1334 if (desc_status & RD_RFS10)
1335 ndev->stats.rx_over_errors++;
1337 if (!mdp->cd->hw_swap)
1339 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1341 skb = mdp->rx_skbuff[entry];
1342 mdp->rx_skbuff[entry] = NULL;
1343 if (mdp->cd->rpadir)
1344 skb_reserve(skb, NET_IP_ALIGN);
1345 skb_put(skb, pkt_len);
1346 skb->protocol = eth_type_trans(skb, ndev);
1348 ndev->stats.rx_packets++;
1349 ndev->stats.rx_bytes += pkt_len;
1351 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1352 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1353 rxdesc = &mdp->rx_ring[entry];
1356 /* Refill the Rx ring buffers. */
1357 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1358 entry = mdp->dirty_rx % mdp->num_rx_ring;
1359 rxdesc = &mdp->rx_ring[entry];
1360 /* The size of the buffer is 16 byte boundary. */
1361 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1363 if (mdp->rx_skbuff[entry] == NULL) {
1364 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1365 mdp->rx_skbuff[entry] = skb;
1367 break; /* Better luck next round. */
1368 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1370 sh_eth_set_receive_align(skb);
1372 skb_checksum_none_assert(skb);
1373 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1375 if (entry >= mdp->num_rx_ring - 1)
1377 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1380 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1383 /* Restart Rx engine if stopped. */
1384 /* If we don't need to check status, don't. -KDU */
1385 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1386 /* fix the values for the next receiving if RDE is set */
1387 if (intr_status & EESR_RDE)
1388 mdp->cur_rx = mdp->dirty_rx =
1389 (sh_eth_read(ndev, RDFAR) -
1390 sh_eth_read(ndev, RDLAR)) >> 4;
1391 sh_eth_write(ndev, EDRRR_R, EDRRR);
1397 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1399 /* disable tx and rx */
1400 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1401 ~(ECMR_RE | ECMR_TE), ECMR);
1404 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1406 /* enable tx and rx */
1407 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1408 (ECMR_RE | ECMR_TE), ECMR);
1411 /* error control function */
1412 static void sh_eth_error(struct net_device *ndev, int intr_status)
1414 struct sh_eth_private *mdp = netdev_priv(ndev);
1419 if (intr_status & EESR_ECI) {
1420 felic_stat = sh_eth_read(ndev, ECSR);
1421 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1422 if (felic_stat & ECSR_ICD)
1423 ndev->stats.tx_carrier_errors++;
1424 if (felic_stat & ECSR_LCHNG) {
1426 if (mdp->cd->no_psr || mdp->no_ether_link) {
1429 link_stat = (sh_eth_read(ndev, PSR));
1430 if (mdp->ether_link_active_low)
1431 link_stat = ~link_stat;
1433 if (!(link_stat & PHY_ST_LINK))
1434 sh_eth_rcv_snd_disable(ndev);
1437 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1438 ~DMAC_M_ECI, EESIPR);
1440 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1442 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1443 DMAC_M_ECI, EESIPR);
1444 /* enable tx and rx */
1445 sh_eth_rcv_snd_enable(ndev);
1451 if (intr_status & EESR_TWB) {
1452 /* Unused write back interrupt */
1453 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1454 ndev->stats.tx_aborted_errors++;
1455 if (netif_msg_tx_err(mdp))
1456 dev_err(&ndev->dev, "Transmit Abort\n");
1460 if (intr_status & EESR_RABT) {
1461 /* Receive Abort int */
1462 if (intr_status & EESR_RFRMER) {
1463 /* Receive Frame Overflow int */
1464 ndev->stats.rx_frame_errors++;
1465 if (netif_msg_rx_err(mdp))
1466 dev_err(&ndev->dev, "Receive Abort\n");
1470 if (intr_status & EESR_TDE) {
1471 /* Transmit Descriptor Empty int */
1472 ndev->stats.tx_fifo_errors++;
1473 if (netif_msg_tx_err(mdp))
1474 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1477 if (intr_status & EESR_TFE) {
1478 /* FIFO under flow */
1479 ndev->stats.tx_fifo_errors++;
1480 if (netif_msg_tx_err(mdp))
1481 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1484 if (intr_status & EESR_RDE) {
1485 /* Receive Descriptor Empty int */
1486 ndev->stats.rx_over_errors++;
1488 if (netif_msg_rx_err(mdp))
1489 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1492 if (intr_status & EESR_RFE) {
1493 /* Receive FIFO Overflow int */
1494 ndev->stats.rx_fifo_errors++;
1495 if (netif_msg_rx_err(mdp))
1496 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1499 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1501 ndev->stats.tx_fifo_errors++;
1502 if (netif_msg_tx_err(mdp))
1503 dev_err(&ndev->dev, "Address Error\n");
1506 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1507 if (mdp->cd->no_ade)
1509 if (intr_status & mask) {
1511 u32 edtrr = sh_eth_read(ndev, EDTRR);
1513 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1514 intr_status, mdp->cur_tx);
1515 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1516 mdp->dirty_tx, (u32) ndev->state, edtrr);
1517 /* dirty buffer free */
1518 sh_eth_txfree(ndev);
1521 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1523 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1526 netif_wake_queue(ndev);
1530 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1532 struct net_device *ndev = netdev;
1533 struct sh_eth_private *mdp = netdev_priv(ndev);
1534 struct sh_eth_cpu_data *cd = mdp->cd;
1535 irqreturn_t ret = IRQ_NONE;
1536 unsigned long intr_status, intr_enable;
1538 spin_lock(&mdp->lock);
1540 /* Get interrupt status */
1541 intr_status = sh_eth_read(ndev, EESR);
1542 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1543 * enabled since it's the one that comes thru regardless of the mask,
1544 * and we need to fully handle it in sh_eth_error() in order to quench
1545 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1547 intr_enable = sh_eth_read(ndev, EESIPR);
1548 intr_status &= intr_enable | DMAC_M_ECI;
1549 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1554 if (intr_status & EESR_RX_CHECK) {
1555 if (napi_schedule_prep(&mdp->napi)) {
1556 /* Mask Rx interrupts */
1557 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1559 __napi_schedule(&mdp->napi);
1561 dev_warn(&ndev->dev,
1562 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1563 intr_status, intr_enable);
1568 if (intr_status & cd->tx_check) {
1569 /* Clear Tx interrupts */
1570 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1572 sh_eth_txfree(ndev);
1573 netif_wake_queue(ndev);
1576 if (intr_status & cd->eesr_err_check) {
1577 /* Clear error interrupts */
1578 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1580 sh_eth_error(ndev, intr_status);
1584 spin_unlock(&mdp->lock);
1589 static int sh_eth_poll(struct napi_struct *napi, int budget)
1591 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1593 struct net_device *ndev = napi->dev;
1595 unsigned long intr_status;
1598 intr_status = sh_eth_read(ndev, EESR);
1599 if (!(intr_status & EESR_RX_CHECK))
1601 /* Clear Rx interrupts */
1602 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1604 if (sh_eth_rx(ndev, intr_status, "a))
1608 napi_complete(napi);
1610 /* Reenable Rx interrupts */
1611 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1613 return budget - quota;
1616 /* PHY state control function */
1617 static void sh_eth_adjust_link(struct net_device *ndev)
1619 struct sh_eth_private *mdp = netdev_priv(ndev);
1620 struct phy_device *phydev = mdp->phydev;
1624 if (phydev->duplex != mdp->duplex) {
1626 mdp->duplex = phydev->duplex;
1627 if (mdp->cd->set_duplex)
1628 mdp->cd->set_duplex(ndev);
1631 if (phydev->speed != mdp->speed) {
1633 mdp->speed = phydev->speed;
1634 if (mdp->cd->set_rate)
1635 mdp->cd->set_rate(ndev);
1639 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1641 mdp->link = phydev->link;
1642 if (mdp->cd->no_psr || mdp->no_ether_link)
1643 sh_eth_rcv_snd_enable(ndev);
1645 } else if (mdp->link) {
1650 if (mdp->cd->no_psr || mdp->no_ether_link)
1651 sh_eth_rcv_snd_disable(ndev);
1654 if (new_state && netif_msg_link(mdp))
1655 phy_print_status(phydev);
1658 /* PHY init function */
1659 static int sh_eth_phy_init(struct net_device *ndev)
1661 struct sh_eth_private *mdp = netdev_priv(ndev);
1662 char phy_id[MII_BUS_ID_SIZE + 3];
1663 struct phy_device *phydev = NULL;
1665 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1666 mdp->mii_bus->id , mdp->phy_id);
1672 /* Try connect to PHY */
1673 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1674 mdp->phy_interface);
1675 if (IS_ERR(phydev)) {
1676 dev_err(&ndev->dev, "phy_connect failed\n");
1677 return PTR_ERR(phydev);
1680 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1681 phydev->addr, phydev->drv->name);
1683 mdp->phydev = phydev;
1688 /* PHY control start function */
1689 static int sh_eth_phy_start(struct net_device *ndev)
1691 struct sh_eth_private *mdp = netdev_priv(ndev);
1694 ret = sh_eth_phy_init(ndev);
1698 /* reset phy - this also wakes it from PDOWN */
1699 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1700 phy_start(mdp->phydev);
1705 static int sh_eth_get_settings(struct net_device *ndev,
1706 struct ethtool_cmd *ecmd)
1708 struct sh_eth_private *mdp = netdev_priv(ndev);
1709 unsigned long flags;
1712 spin_lock_irqsave(&mdp->lock, flags);
1713 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1714 spin_unlock_irqrestore(&mdp->lock, flags);
1719 static int sh_eth_set_settings(struct net_device *ndev,
1720 struct ethtool_cmd *ecmd)
1722 struct sh_eth_private *mdp = netdev_priv(ndev);
1723 unsigned long flags;
1726 spin_lock_irqsave(&mdp->lock, flags);
1728 /* disable tx and rx */
1729 sh_eth_rcv_snd_disable(ndev);
1731 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1735 if (ecmd->duplex == DUPLEX_FULL)
1740 if (mdp->cd->set_duplex)
1741 mdp->cd->set_duplex(ndev);
1746 /* enable tx and rx */
1747 sh_eth_rcv_snd_enable(ndev);
1749 spin_unlock_irqrestore(&mdp->lock, flags);
1754 static int sh_eth_nway_reset(struct net_device *ndev)
1756 struct sh_eth_private *mdp = netdev_priv(ndev);
1757 unsigned long flags;
1760 spin_lock_irqsave(&mdp->lock, flags);
1761 ret = phy_start_aneg(mdp->phydev);
1762 spin_unlock_irqrestore(&mdp->lock, flags);
1767 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1769 struct sh_eth_private *mdp = netdev_priv(ndev);
1770 return mdp->msg_enable;
1773 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1775 struct sh_eth_private *mdp = netdev_priv(ndev);
1776 mdp->msg_enable = value;
1779 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1780 "rx_current", "tx_current",
1781 "rx_dirty", "tx_dirty",
1783 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1785 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1789 return SH_ETH_STATS_LEN;
1795 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1796 struct ethtool_stats *stats, u64 *data)
1798 struct sh_eth_private *mdp = netdev_priv(ndev);
1801 /* device-specific stats */
1802 data[i++] = mdp->cur_rx;
1803 data[i++] = mdp->cur_tx;
1804 data[i++] = mdp->dirty_rx;
1805 data[i++] = mdp->dirty_tx;
1808 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1810 switch (stringset) {
1812 memcpy(data, *sh_eth_gstrings_stats,
1813 sizeof(sh_eth_gstrings_stats));
1818 static void sh_eth_get_ringparam(struct net_device *ndev,
1819 struct ethtool_ringparam *ring)
1821 struct sh_eth_private *mdp = netdev_priv(ndev);
1823 ring->rx_max_pending = RX_RING_MAX;
1824 ring->tx_max_pending = TX_RING_MAX;
1825 ring->rx_pending = mdp->num_rx_ring;
1826 ring->tx_pending = mdp->num_tx_ring;
1829 static int sh_eth_set_ringparam(struct net_device *ndev,
1830 struct ethtool_ringparam *ring)
1832 struct sh_eth_private *mdp = netdev_priv(ndev);
1835 if (ring->tx_pending > TX_RING_MAX ||
1836 ring->rx_pending > RX_RING_MAX ||
1837 ring->tx_pending < TX_RING_MIN ||
1838 ring->rx_pending < RX_RING_MIN)
1840 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1843 if (netif_running(ndev)) {
1844 netif_tx_disable(ndev);
1845 /* Disable interrupts by clearing the interrupt mask. */
1846 sh_eth_write(ndev, 0x0000, EESIPR);
1847 /* Stop the chip's Tx and Rx processes. */
1848 sh_eth_write(ndev, 0, EDTRR);
1849 sh_eth_write(ndev, 0, EDRRR);
1850 synchronize_irq(ndev->irq);
1853 /* Free all the skbuffs in the Rx queue. */
1854 sh_eth_ring_free(ndev);
1855 /* Free DMA buffer */
1856 sh_eth_free_dma_buffer(mdp);
1858 /* Set new parameters */
1859 mdp->num_rx_ring = ring->rx_pending;
1860 mdp->num_tx_ring = ring->tx_pending;
1862 ret = sh_eth_ring_init(ndev);
1864 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1867 ret = sh_eth_dev_init(ndev, false);
1869 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1873 if (netif_running(ndev)) {
1874 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1875 /* Setting the Rx mode will start the Rx process. */
1876 sh_eth_write(ndev, EDRRR_R, EDRRR);
1877 netif_wake_queue(ndev);
1883 static const struct ethtool_ops sh_eth_ethtool_ops = {
1884 .get_settings = sh_eth_get_settings,
1885 .set_settings = sh_eth_set_settings,
1886 .nway_reset = sh_eth_nway_reset,
1887 .get_msglevel = sh_eth_get_msglevel,
1888 .set_msglevel = sh_eth_set_msglevel,
1889 .get_link = ethtool_op_get_link,
1890 .get_strings = sh_eth_get_strings,
1891 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1892 .get_sset_count = sh_eth_get_sset_count,
1893 .get_ringparam = sh_eth_get_ringparam,
1894 .set_ringparam = sh_eth_set_ringparam,
1897 /* network device open function */
1898 static int sh_eth_open(struct net_device *ndev)
1901 struct sh_eth_private *mdp = netdev_priv(ndev);
1903 pm_runtime_get_sync(&mdp->pdev->dev);
1905 ret = request_irq(ndev->irq, sh_eth_interrupt,
1906 mdp->cd->irq_flags, ndev->name, ndev);
1908 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1912 /* Descriptor set */
1913 ret = sh_eth_ring_init(ndev);
1918 ret = sh_eth_dev_init(ndev, true);
1922 /* PHY control start*/
1923 ret = sh_eth_phy_start(ndev);
1927 napi_enable(&mdp->napi);
1932 free_irq(ndev->irq, ndev);
1933 pm_runtime_put_sync(&mdp->pdev->dev);
1937 /* Timeout function */
1938 static void sh_eth_tx_timeout(struct net_device *ndev)
1940 struct sh_eth_private *mdp = netdev_priv(ndev);
1941 struct sh_eth_rxdesc *rxdesc;
1944 netif_stop_queue(ndev);
1946 if (netif_msg_timer(mdp))
1947 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1948 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1950 /* tx_errors count up */
1951 ndev->stats.tx_errors++;
1953 /* Free all the skbuffs in the Rx queue. */
1954 for (i = 0; i < mdp->num_rx_ring; i++) {
1955 rxdesc = &mdp->rx_ring[i];
1957 rxdesc->addr = 0xBADF00D0;
1958 if (mdp->rx_skbuff[i])
1959 dev_kfree_skb(mdp->rx_skbuff[i]);
1960 mdp->rx_skbuff[i] = NULL;
1962 for (i = 0; i < mdp->num_tx_ring; i++) {
1963 if (mdp->tx_skbuff[i])
1964 dev_kfree_skb(mdp->tx_skbuff[i]);
1965 mdp->tx_skbuff[i] = NULL;
1969 sh_eth_dev_init(ndev, true);
1972 /* Packet transmit function */
1973 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1975 struct sh_eth_private *mdp = netdev_priv(ndev);
1976 struct sh_eth_txdesc *txdesc;
1978 unsigned long flags;
1980 spin_lock_irqsave(&mdp->lock, flags);
1981 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1982 if (!sh_eth_txfree(ndev)) {
1983 if (netif_msg_tx_queued(mdp))
1984 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1985 netif_stop_queue(ndev);
1986 spin_unlock_irqrestore(&mdp->lock, flags);
1987 return NETDEV_TX_BUSY;
1990 spin_unlock_irqrestore(&mdp->lock, flags);
1992 entry = mdp->cur_tx % mdp->num_tx_ring;
1993 mdp->tx_skbuff[entry] = skb;
1994 txdesc = &mdp->tx_ring[entry];
1996 if (!mdp->cd->hw_swap)
1997 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1999 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2001 if (skb->len < ETHERSMALL)
2002 txdesc->buffer_length = ETHERSMALL;
2004 txdesc->buffer_length = skb->len;
2006 if (entry >= mdp->num_tx_ring - 1)
2007 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2009 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2013 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2014 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2016 return NETDEV_TX_OK;
2019 /* device close function */
2020 static int sh_eth_close(struct net_device *ndev)
2022 struct sh_eth_private *mdp = netdev_priv(ndev);
2024 napi_disable(&mdp->napi);
2026 netif_stop_queue(ndev);
2028 /* Disable interrupts by clearing the interrupt mask. */
2029 sh_eth_write(ndev, 0x0000, EESIPR);
2031 /* Stop the chip's Tx and Rx processes. */
2032 sh_eth_write(ndev, 0, EDTRR);
2033 sh_eth_write(ndev, 0, EDRRR);
2035 /* PHY Disconnect */
2037 phy_stop(mdp->phydev);
2038 phy_disconnect(mdp->phydev);
2041 free_irq(ndev->irq, ndev);
2043 /* Free all the skbuffs in the Rx queue. */
2044 sh_eth_ring_free(ndev);
2046 /* free DMA buffer */
2047 sh_eth_free_dma_buffer(mdp);
2049 pm_runtime_put_sync(&mdp->pdev->dev);
2054 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2056 struct sh_eth_private *mdp = netdev_priv(ndev);
2058 pm_runtime_get_sync(&mdp->pdev->dev);
2060 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2061 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
2062 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2063 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
2064 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2065 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
2066 if (sh_eth_is_gether(mdp)) {
2067 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2068 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
2069 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2070 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2072 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2073 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2075 pm_runtime_put_sync(&mdp->pdev->dev);
2077 return &ndev->stats;
2080 /* ioctl to device function */
2081 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
2084 struct sh_eth_private *mdp = netdev_priv(ndev);
2085 struct phy_device *phydev = mdp->phydev;
2087 if (!netif_running(ndev))
2093 return phy_mii_ioctl(phydev, rq, cmd);
2096 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2097 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2100 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2103 static u32 sh_eth_tsu_get_post_mask(int entry)
2105 return 0x0f << (28 - ((entry % 8) * 4));
2108 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2110 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2113 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2116 struct sh_eth_private *mdp = netdev_priv(ndev);
2120 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2121 tmp = ioread32(reg_offset);
2122 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2125 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2128 struct sh_eth_private *mdp = netdev_priv(ndev);
2129 u32 post_mask, ref_mask, tmp;
2132 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2133 post_mask = sh_eth_tsu_get_post_mask(entry);
2134 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2136 tmp = ioread32(reg_offset);
2137 iowrite32(tmp & ~post_mask, reg_offset);
2139 /* If other port enables, the function returns "true" */
2140 return tmp & ref_mask;
2143 static int sh_eth_tsu_busy(struct net_device *ndev)
2145 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2146 struct sh_eth_private *mdp = netdev_priv(ndev);
2148 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2152 dev_err(&ndev->dev, "%s: timeout\n", __func__);
2160 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2165 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2166 iowrite32(val, reg);
2167 if (sh_eth_tsu_busy(ndev) < 0)
2170 val = addr[4] << 8 | addr[5];
2171 iowrite32(val, reg + 4);
2172 if (sh_eth_tsu_busy(ndev) < 0)
2178 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2182 val = ioread32(reg);
2183 addr[0] = (val >> 24) & 0xff;
2184 addr[1] = (val >> 16) & 0xff;
2185 addr[2] = (val >> 8) & 0xff;
2186 addr[3] = val & 0xff;
2187 val = ioread32(reg + 4);
2188 addr[4] = (val >> 8) & 0xff;
2189 addr[5] = val & 0xff;
2193 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2195 struct sh_eth_private *mdp = netdev_priv(ndev);
2196 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2198 u8 c_addr[ETH_ALEN];
2200 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2201 sh_eth_tsu_read_entry(reg_offset, c_addr);
2202 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2209 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2214 memset(blank, 0, sizeof(blank));
2215 entry = sh_eth_tsu_find_entry(ndev, blank);
2216 return (entry < 0) ? -ENOMEM : entry;
2219 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2222 struct sh_eth_private *mdp = netdev_priv(ndev);
2223 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2227 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2228 ~(1 << (31 - entry)), TSU_TEN);
2230 memset(blank, 0, sizeof(blank));
2231 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2237 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2239 struct sh_eth_private *mdp = netdev_priv(ndev);
2240 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2246 i = sh_eth_tsu_find_entry(ndev, addr);
2248 /* No entry found, create one */
2249 i = sh_eth_tsu_find_empty(ndev);
2252 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2256 /* Enable the entry */
2257 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2258 (1 << (31 - i)), TSU_TEN);
2261 /* Entry found or created, enable POST */
2262 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2267 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2269 struct sh_eth_private *mdp = netdev_priv(ndev);
2275 i = sh_eth_tsu_find_entry(ndev, addr);
2278 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2281 /* Disable the entry if both ports was disabled */
2282 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2290 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2292 struct sh_eth_private *mdp = netdev_priv(ndev);
2295 if (unlikely(!mdp->cd->tsu))
2298 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2299 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2302 /* Disable the entry if both ports was disabled */
2303 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2311 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2313 struct sh_eth_private *mdp = netdev_priv(ndev);
2315 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2318 if (unlikely(!mdp->cd->tsu))
2321 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2322 sh_eth_tsu_read_entry(reg_offset, addr);
2323 if (is_multicast_ether_addr(addr))
2324 sh_eth_tsu_del_entry(ndev, addr);
2328 /* Multicast reception directions set */
2329 static void sh_eth_set_multicast_list(struct net_device *ndev)
2331 struct sh_eth_private *mdp = netdev_priv(ndev);
2334 unsigned long flags;
2336 spin_lock_irqsave(&mdp->lock, flags);
2338 * Initial condition is MCT = 1, PRM = 0.
2339 * Depending on ndev->flags, set PRM or clear MCT
2341 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2343 if (!(ndev->flags & IFF_MULTICAST)) {
2344 sh_eth_tsu_purge_mcast(ndev);
2347 if (ndev->flags & IFF_ALLMULTI) {
2348 sh_eth_tsu_purge_mcast(ndev);
2349 ecmr_bits &= ~ECMR_MCT;
2353 if (ndev->flags & IFF_PROMISC) {
2354 sh_eth_tsu_purge_all(ndev);
2355 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2356 } else if (mdp->cd->tsu) {
2357 struct netdev_hw_addr *ha;
2358 netdev_for_each_mc_addr(ha, ndev) {
2359 if (mcast_all && is_multicast_ether_addr(ha->addr))
2362 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2364 sh_eth_tsu_purge_mcast(ndev);
2365 ecmr_bits &= ~ECMR_MCT;
2371 /* Normal, unicast/broadcast-only mode. */
2372 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2375 /* update the ethernet mode */
2376 sh_eth_write(ndev, ecmr_bits, ECMR);
2378 spin_unlock_irqrestore(&mdp->lock, flags);
2381 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2389 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2390 __be16 proto, u16 vid)
2392 struct sh_eth_private *mdp = netdev_priv(ndev);
2393 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2395 if (unlikely(!mdp->cd->tsu))
2398 /* No filtering if vid = 0 */
2402 mdp->vlan_num_ids++;
2405 * The controller has one VLAN tag HW filter. So, if the filter is
2406 * already enabled, the driver disables it and the filte
2408 if (mdp->vlan_num_ids > 1) {
2409 /* disable VLAN filter */
2410 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2414 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2420 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2421 __be16 proto, u16 vid)
2423 struct sh_eth_private *mdp = netdev_priv(ndev);
2424 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2426 if (unlikely(!mdp->cd->tsu))
2429 /* No filtering if vid = 0 */
2433 mdp->vlan_num_ids--;
2434 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2439 /* SuperH's TSU register init function */
2440 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2442 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2443 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2444 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2445 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2446 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2447 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2448 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2449 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2450 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2451 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2452 if (sh_eth_is_gether(mdp)) {
2453 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2454 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2456 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2457 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2459 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2460 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2461 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2462 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2463 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2464 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2465 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2468 /* MDIO bus release function */
2469 static int sh_mdio_release(struct net_device *ndev)
2471 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2473 /* unregister mdio bus */
2474 mdiobus_unregister(bus);
2476 /* remove mdio bus info from net_device */
2477 dev_set_drvdata(&ndev->dev, NULL);
2479 /* free bitbang info */
2480 free_mdio_bitbang(bus);
2485 /* MDIO bus init function */
2486 static int sh_mdio_init(struct net_device *ndev, int id,
2487 struct sh_eth_plat_data *pd)
2490 struct bb_info *bitbang;
2491 struct sh_eth_private *mdp = netdev_priv(ndev);
2493 /* create bit control struct for PHY */
2494 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2502 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2503 bitbang->set_gate = pd->set_mdio_gate;
2504 bitbang->mdi_msk = PIR_MDI;
2505 bitbang->mdo_msk = PIR_MDO;
2506 bitbang->mmd_msk = PIR_MMD;
2507 bitbang->mdc_msk = PIR_MDC;
2508 bitbang->ctrl.ops = &bb_ops;
2510 /* MII controller setting */
2511 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2512 if (!mdp->mii_bus) {
2517 /* Hook up MII support for ethtool */
2518 mdp->mii_bus->name = "sh_mii";
2519 mdp->mii_bus->parent = &ndev->dev;
2520 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2521 mdp->pdev->name, id);
2524 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2525 sizeof(int) * PHY_MAX_ADDR,
2527 if (!mdp->mii_bus->irq) {
2532 for (i = 0; i < PHY_MAX_ADDR; i++)
2533 mdp->mii_bus->irq[i] = PHY_POLL;
2535 /* register mdio bus */
2536 ret = mdiobus_register(mdp->mii_bus);
2540 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2545 free_mdio_bitbang(mdp->mii_bus);
2551 static const u16 *sh_eth_get_register_offset(int register_type)
2553 const u16 *reg_offset = NULL;
2555 switch (register_type) {
2556 case SH_ETH_REG_GIGABIT:
2557 reg_offset = sh_eth_offset_gigabit;
2559 case SH_ETH_REG_FAST_RCAR:
2560 reg_offset = sh_eth_offset_fast_rcar;
2562 case SH_ETH_REG_FAST_SH4:
2563 reg_offset = sh_eth_offset_fast_sh4;
2565 case SH_ETH_REG_FAST_SH3_SH2:
2566 reg_offset = sh_eth_offset_fast_sh3_sh2;
2569 pr_err("Unknown register type (%d)\n", register_type);
2576 static const struct net_device_ops sh_eth_netdev_ops = {
2577 .ndo_open = sh_eth_open,
2578 .ndo_stop = sh_eth_close,
2579 .ndo_start_xmit = sh_eth_start_xmit,
2580 .ndo_get_stats = sh_eth_get_stats,
2581 .ndo_tx_timeout = sh_eth_tx_timeout,
2582 .ndo_do_ioctl = sh_eth_do_ioctl,
2583 .ndo_validate_addr = eth_validate_addr,
2584 .ndo_set_mac_address = eth_mac_addr,
2585 .ndo_change_mtu = eth_change_mtu,
2588 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2589 .ndo_open = sh_eth_open,
2590 .ndo_stop = sh_eth_close,
2591 .ndo_start_xmit = sh_eth_start_xmit,
2592 .ndo_get_stats = sh_eth_get_stats,
2593 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2594 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2595 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2596 .ndo_tx_timeout = sh_eth_tx_timeout,
2597 .ndo_do_ioctl = sh_eth_do_ioctl,
2598 .ndo_validate_addr = eth_validate_addr,
2599 .ndo_set_mac_address = eth_mac_addr,
2600 .ndo_change_mtu = eth_change_mtu,
2603 static int sh_eth_drv_probe(struct platform_device *pdev)
2606 struct resource *res;
2607 struct net_device *ndev = NULL;
2608 struct sh_eth_private *mdp = NULL;
2609 struct sh_eth_plat_data *pd = pdev->dev.platform_data;
2610 const struct platform_device_id *id = platform_get_device_id(pdev);
2613 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2614 if (unlikely(res == NULL)) {
2615 dev_err(&pdev->dev, "invalid resource\n");
2620 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2626 /* The sh Ether-specific entries in the device structure. */
2627 ndev->base_addr = res->start;
2633 ret = platform_get_irq(pdev, 0);
2640 SET_NETDEV_DEV(ndev, &pdev->dev);
2642 mdp = netdev_priv(ndev);
2643 mdp->num_tx_ring = TX_RING_SIZE;
2644 mdp->num_rx_ring = RX_RING_SIZE;
2645 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2646 if (IS_ERR(mdp->addr)) {
2647 ret = PTR_ERR(mdp->addr);
2651 spin_lock_init(&mdp->lock);
2653 pm_runtime_enable(&pdev->dev);
2654 pm_runtime_resume(&pdev->dev);
2657 mdp->phy_id = pd->phy;
2658 mdp->phy_interface = pd->phy_interface;
2660 mdp->edmac_endian = pd->edmac_endian;
2661 mdp->no_ether_link = pd->no_ether_link;
2662 mdp->ether_link_active_low = pd->ether_link_active_low;
2665 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2666 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2667 sh_eth_set_default_cpu_data(mdp->cd);
2671 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2673 ndev->netdev_ops = &sh_eth_netdev_ops;
2674 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2675 ndev->watchdog_timeo = TX_TIMEOUT;
2677 /* debug message level */
2678 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2680 /* read and set MAC address */
2681 read_mac_address(ndev, pd->mac_addr);
2682 if (!is_valid_ether_addr(ndev->dev_addr)) {
2683 dev_warn(&pdev->dev,
2684 "no valid MAC address supplied, using a random one.\n");
2685 eth_hw_addr_random(ndev);
2688 /* ioremap the TSU registers */
2690 struct resource *rtsu;
2691 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2692 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2693 if (IS_ERR(mdp->tsu_addr)) {
2694 ret = PTR_ERR(mdp->tsu_addr);
2697 mdp->port = devno % 2;
2698 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2701 /* initialize first or needed device */
2702 if (!devno || pd->needs_init) {
2703 if (mdp->cd->chip_reset)
2704 mdp->cd->chip_reset(ndev);
2707 /* TSU init (Init only)*/
2708 sh_eth_tsu_init(mdp);
2712 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2714 /* network device register */
2715 ret = register_netdev(ndev);
2720 ret = sh_mdio_init(ndev, pdev->id, pd);
2722 goto out_unregister;
2724 /* print device information */
2725 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2726 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2728 platform_set_drvdata(pdev, ndev);
2733 unregister_netdev(ndev);
2736 netif_napi_del(&mdp->napi);
2747 static int sh_eth_drv_remove(struct platform_device *pdev)
2749 struct net_device *ndev = platform_get_drvdata(pdev);
2750 struct sh_eth_private *mdp = netdev_priv(ndev);
2752 sh_mdio_release(ndev);
2753 unregister_netdev(ndev);
2754 netif_napi_del(&mdp->napi);
2755 pm_runtime_disable(&pdev->dev);
2762 static int sh_eth_runtime_nop(struct device *dev)
2765 * Runtime PM callback shared between ->runtime_suspend()
2766 * and ->runtime_resume(). Simply returns success.
2768 * This driver re-initializes all registers after
2769 * pm_runtime_get_sync() anyway so there is no need
2770 * to save and restore registers here.
2775 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2776 .runtime_suspend = sh_eth_runtime_nop,
2777 .runtime_resume = sh_eth_runtime_nop,
2779 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2781 #define SH_ETH_PM_OPS NULL
2784 static struct platform_device_id sh_eth_id_table[] = {
2785 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2786 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2787 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2788 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2789 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2790 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2791 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2792 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2793 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
2794 { "r8a7790-ether", (kernel_ulong_t)&r8a7790_data },
2797 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2799 static struct platform_driver sh_eth_driver = {
2800 .probe = sh_eth_drv_probe,
2801 .remove = sh_eth_drv_remove,
2802 .id_table = sh_eth_id_table,
2805 .pm = SH_ETH_PM_OPS,
2809 module_platform_driver(sh_eth_driver);
2811 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2812 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2813 MODULE_LICENSE("GPL v2");