Pileus Git - ~andy/linux/blob - drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   4  *  Copyright (C) 2008-2013 Renesas Solutions Corp.
   5  *  Copyright (C) 2013 Cogent Embedded, Inc.
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms and conditions of the GNU General Public License,
   9  *  version 2, as published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  *  more details.
  15  *
  16  *  The full GNU General Public License is included in this distribution in
  17  *  the file called "COPYING".
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/delay.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/mdio-bitbang.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/phy.h>
  31 #include <linux/cache.h>
  32 #include <linux/io.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/slab.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/clk.h>
  38 #include <linux/sh_eth.h>
  39
  40 #include "sh_eth.h"
  41
  42 #define SH_ETH_DEF_MSG_ENABLE \
  43                 (NETIF_MSG_LINK | \
  44                 NETIF_MSG_TIMER | \
  45                 NETIF_MSG_RX_ERR| \
  46                 NETIF_MSG_TX_ERR)
  47
  48 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  49         [EDSR]          = 0x0000,
  50         [EDMR]          = 0x0400,
  51         [EDTRR]         = 0x0408,
  52         [EDRRR]         = 0x0410,
  53         [EESR]          = 0x0428,
  54         [EESIPR]        = 0x0430,
  55         [TDLAR]         = 0x0010,
  56         [TDFAR]         = 0x0014,
  57         [TDFXR]         = 0x0018,
  58         [TDFFR]         = 0x001c,
  59         [RDLAR]         = 0x0030,
  60         [RDFAR]         = 0x0034,
  61         [RDFXR]         = 0x0038,
  62         [RDFFR]         = 0x003c,
  63         [TRSCER]        = 0x0438,
  64         [RMFCR]         = 0x0440,
  65         [TFTR]          = 0x0448,
  66         [FDR]           = 0x0450,
  67         [RMCR]          = 0x0458,
  68         [RPADIR]        = 0x0460,
  69         [FCFTR]         = 0x0468,
  70         [CSMR]          = 0x04E4,
  71
  72         [ECMR]          = 0x0500,
  73         [ECSR]          = 0x0510,
  74         [ECSIPR]        = 0x0518,
  75         [PIR]           = 0x0520,
  76         [PSR]           = 0x0528,
  77         [PIPR]          = 0x052c,
  78         [RFLR]          = 0x0508,
  79         [APR]           = 0x0554,
  80         [MPR]           = 0x0558,
  81         [PFTCR]         = 0x055c,
  82         [PFRCR]         = 0x0560,
  83         [TPAUSER]       = 0x0564,
  84         [GECMR]         = 0x05b0,
  85         [BCULR]         = 0x05b4,
  86         [MAHR]          = 0x05c0,
  87         [MALR]          = 0x05c8,
  88         [TROCR]         = 0x0700,
  89         [CDCR]          = 0x0708,
  90         [LCCR]          = 0x0710,
  91         [CEFCR]         = 0x0740,
  92         [FRECR]         = 0x0748,
  93         [TSFRCR]        = 0x0750,
  94         [TLFRCR]        = 0x0758,
  95         [RFCR]          = 0x0760,
  96         [CERCR]         = 0x0768,
  97         [CEECR]         = 0x0770,
  98         [MAFCR]         = 0x0778,
  99         [RMII_MII]      = 0x0790,
 100
 101         [ARSTR]         = 0x0000,
 102         [TSU_CTRST]     = 0x0004,
 103         [TSU_FWEN0]     = 0x0010,
 104         [TSU_FWEN1]     = 0x0014,
 105         [TSU_FCM]       = 0x0018,
 106         [TSU_BSYSL0]    = 0x0020,
 107         [TSU_BSYSL1]    = 0x0024,
 108         [TSU_PRISL0]    = 0x0028,
 109         [TSU_PRISL1]    = 0x002c,
 110         [TSU_FWSL0]     = 0x0030,
 111         [TSU_FWSL1]     = 0x0034,
 112         [TSU_FWSLC]     = 0x0038,
 113         [TSU_QTAG0]     = 0x0040,
 114         [TSU_QTAG1]     = 0x0044,
 115         [TSU_FWSR]      = 0x0050,
 116         [TSU_FWINMK]    = 0x0054,
 117         [TSU_ADQT0]     = 0x0048,
 118         [TSU_ADQT1]     = 0x004c,
 119         [TSU_VTAG0]     = 0x0058,
 120         [TSU_VTAG1]     = 0x005c,
 121         [TSU_ADSBSY]    = 0x0060,
 122         [TSU_TEN]       = 0x0064,
 123         [TSU_POST1]     = 0x0070,
 124         [TSU_POST2]     = 0x0074,
 125         [TSU_POST3]     = 0x0078,
 126         [TSU_POST4]     = 0x007c,
 127         [TSU_ADRH0]     = 0x0100,
 128         [TSU_ADRL0]     = 0x0104,
 129         [TSU_ADRH31]    = 0x01f8,
 130         [TSU_ADRL31]    = 0x01fc,
 131
 132         [TXNLCR0]       = 0x0080,
 133         [TXALCR0]       = 0x0084,
 134         [RXNLCR0]       = 0x0088,
 135         [RXALCR0]       = 0x008c,
 136         [FWNLCR0]       = 0x0090,
 137         [FWALCR0]       = 0x0094,
 138         [TXNLCR1]       = 0x00a0,
 139         [TXALCR1]       = 0x00a0,
 140         [RXNLCR1]       = 0x00a8,
 141         [RXALCR1]       = 0x00ac,
 142         [FWNLCR1]       = 0x00b0,
 143         [FWALCR1]       = 0x00b4,
 144 };
 145
 146 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 147         [ECMR]          = 0x0300,
 148         [RFLR]          = 0x0308,
 149         [ECSR]          = 0x0310,
 150         [ECSIPR]        = 0x0318,
 151         [PIR]           = 0x0320,
 152         [PSR]           = 0x0328,
 153         [RDMLR]         = 0x0340,
 154         [IPGR]          = 0x0350,
 155         [APR]           = 0x0354,
 156         [MPR]           = 0x0358,
 157         [RFCF]          = 0x0360,
 158         [TPAUSER]       = 0x0364,
 159         [TPAUSECR]      = 0x0368,
 160         [MAHR]          = 0x03c0,
 161         [MALR]          = 0x03c8,
 162         [TROCR]         = 0x03d0,
 163         [CDCR]          = 0x03d4,
 164         [LCCR]          = 0x03d8,
 165         [CNDCR]         = 0x03dc,
 166         [CEFCR]         = 0x03e4,
 167         [FRECR]         = 0x03e8,
 168         [TSFRCR]        = 0x03ec,
 169         [TLFRCR]        = 0x03f0,
 170         [RFCR]          = 0x03f4,
 171         [MAFCR]         = 0x03f8,
 172
 173         [EDMR]          = 0x0200,
 174         [EDTRR]         = 0x0208,
 175         [EDRRR]         = 0x0210,
 176         [TDLAR]         = 0x0218,
 177         [RDLAR]         = 0x0220,
 178         [EESR]          = 0x0228,
 179         [EESIPR]        = 0x0230,
 180         [TRSCER]        = 0x0238,
 181         [RMFCR]         = 0x0240,
 182         [TFTR]          = 0x0248,
 183         [FDR]           = 0x0250,
 184         [RMCR]          = 0x0258,
 185         [TFUCR]         = 0x0264,
 186         [RFOCR]         = 0x0268,
 187         [RMIIMODE]      = 0x026c,
 188         [FCFTR]         = 0x0270,
 189         [TRIMD]         = 0x027c,
 190 };
 191
 192 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 193         [ECMR]          = 0x0100,
 194         [RFLR]          = 0x0108,
 195         [ECSR]          = 0x0110,
 196         [ECSIPR]        = 0x0118,
 197         [PIR]           = 0x0120,
 198         [PSR]           = 0x0128,
 199         [RDMLR]         = 0x0140,
 200         [IPGR]          = 0x0150,
 201         [APR]           = 0x0154,
 202         [MPR]           = 0x0158,
 203         [TPAUSER]       = 0x0164,
 204         [RFCF]          = 0x0160,
 205         [TPAUSECR]      = 0x0168,
 206         [BCFRR]         = 0x016c,
 207         [MAHR]          = 0x01c0,
 208         [MALR]          = 0x01c8,
 209         [TROCR]         = 0x01d0,
 210         [CDCR]          = 0x01d4,
 211         [LCCR]          = 0x01d8,
 212         [CNDCR]         = 0x01dc,
 213         [CEFCR]         = 0x01e4,
 214         [FRECR]         = 0x01e8,
 215         [TSFRCR]        = 0x01ec,
 216         [TLFRCR]        = 0x01f0,
 217         [RFCR]          = 0x01f4,
 218         [MAFCR]         = 0x01f8,
 219         [RTRATE]        = 0x01fc,
 220
 221         [EDMR]          = 0x0000,
 222         [EDTRR]         = 0x0008,
 223         [EDRRR]         = 0x0010,
 224         [TDLAR]         = 0x0018,
 225         [RDLAR]         = 0x0020,
 226         [EESR]          = 0x0028,
 227         [EESIPR]        = 0x0030,
 228         [TRSCER]        = 0x0038,
 229         [RMFCR]         = 0x0040,
 230         [TFTR]          = 0x0048,
 231         [FDR]           = 0x0050,
 232         [RMCR]          = 0x0058,
 233         [TFUCR]         = 0x0064,
 234         [RFOCR]         = 0x0068,
 235         [FCFTR]         = 0x0070,
 236         [RPADIR]        = 0x0078,
 237         [TRIMD]         = 0x007c,
 238         [RBWAR]         = 0x00c8,
 239         [RDFAR]         = 0x00cc,
 240         [TBRAR]         = 0x00d4,
 241         [TDFAR]         = 0x00d8,
 242 };
 243
 244 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 245         [ECMR]          = 0x0160,
 246         [ECSR]          = 0x0164,
 247         [ECSIPR]        = 0x0168,
 248         [PIR]           = 0x016c,
 249         [MAHR]          = 0x0170,
 250         [MALR]          = 0x0174,
 251         [RFLR]          = 0x0178,
 252         [PSR]           = 0x017c,
 253         [TROCR]         = 0x0180,
 254         [CDCR]          = 0x0184,
 255         [LCCR]          = 0x0188,
 256         [CNDCR]         = 0x018c,
 257         [CEFCR]         = 0x0194,
 258         [FRECR]         = 0x0198,
 259         [TSFRCR]        = 0x019c,
 260         [TLFRCR]        = 0x01a0,
 261         [RFCR]          = 0x01a4,
 262         [MAFCR]         = 0x01a8,
 263         [IPGR]          = 0x01b4,
 264         [APR]           = 0x01b8,
 265         [MPR]           = 0x01bc,
 266         [TPAUSER]       = 0x01c4,
 267         [BCFR]          = 0x01cc,
 268
 269         [ARSTR]         = 0x0000,
 270         [TSU_CTRST]     = 0x0004,
 271         [TSU_FWEN0]     = 0x0010,
 272         [TSU_FWEN1]     = 0x0014,
 273         [TSU_FCM]       = 0x0018,
 274         [TSU_BSYSL0]    = 0x0020,
 275         [TSU_BSYSL1]    = 0x0024,
 276         [TSU_PRISL0]    = 0x0028,
 277         [TSU_PRISL1]    = 0x002c,
 278         [TSU_FWSL0]     = 0x0030,
 279         [TSU_FWSL1]     = 0x0034,
 280         [TSU_FWSLC]     = 0x0038,
 281         [TSU_QTAGM0]    = 0x0040,
 282         [TSU_QTAGM1]    = 0x0044,
 283         [TSU_ADQT0]     = 0x0048,
 284         [TSU_ADQT1]     = 0x004c,
 285         [TSU_FWSR]      = 0x0050,
 286         [TSU_FWINMK]    = 0x0054,
 287         [TSU_ADSBSY]    = 0x0060,
 288         [TSU_TEN]       = 0x0064,
 289         [TSU_POST1]     = 0x0070,
 290         [TSU_POST2]     = 0x0074,
 291         [TSU_POST3]     = 0x0078,
 292         [TSU_POST4]     = 0x007c,
 293
 294         [TXNLCR0]       = 0x0080,
 295         [TXALCR0]       = 0x0084,
 296         [RXNLCR0]       = 0x0088,
 297         [RXALCR0]       = 0x008c,
 298         [FWNLCR0]       = 0x0090,
 299         [FWALCR0]       = 0x0094,
 300         [TXNLCR1]       = 0x00a0,
 301         [TXALCR1]       = 0x00a0,
 302         [RXNLCR1]       = 0x00a8,
 303         [RXALCR1]       = 0x00ac,
 304         [FWNLCR1]       = 0x00b0,
 305         [FWALCR1]       = 0x00b4,
 306
 307         [TSU_ADRH0]     = 0x0100,
 308         [TSU_ADRL0]     = 0x0104,
 309         [TSU_ADRL31]    = 0x01fc,
 310 };
 311
 312 static int sh_eth_is_gether(struct sh_eth_private *mdp)
 313 {
 314         if (mdp->reg_offset == sh_eth_offset_gigabit)
 315                 return 1;
 316         else
 317                 return 0;
 318 }
 319
 320 static void sh_eth_select_mii(struct net_device *ndev)
 321 {
 322         u32 value = 0x0;
 323         struct sh_eth_private *mdp = netdev_priv(ndev);
 324
 325         switch (mdp->phy_interface) {
 326         case PHY_INTERFACE_MODE_GMII:
 327                 value = 0x2;
 328                 break;
 329         case PHY_INTERFACE_MODE_MII:
 330                 value = 0x1;
 331                 break;
 332         case PHY_INTERFACE_MODE_RMII:
 333                 value = 0x0;
 334                 break;
 335         default:
 336                 pr_warn("PHY interface mode was not setup. Set to MII.\n");
 337                 value = 0x1;
 338                 break;
 339         }
 340
 341         sh_eth_write(ndev, value, RMII_MII);
 342 }
 343
 344 static void sh_eth_set_duplex(struct net_device *ndev)
 345 {
 346         struct sh_eth_private *mdp = netdev_priv(ndev);
 347
 348         if (mdp->duplex) /* Full */
 349                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 350         else            /* Half */
 351                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 352 }
 353
 354 /* There is CPU dependent code */
 355 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 356 {
 357         struct sh_eth_private *mdp = netdev_priv(ndev);
 358
 359         switch (mdp->speed) {
 360         case 10: /* 10BASE */
 361                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 362                 break;
 363         case 100:/* 100BASE */
 364                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 365                 break;
 366         default:
 367                 break;
 368         }
 369 }
 370
 371 /* R8A7778/9 */
 372 static struct sh_eth_cpu_data r8a777x_data = {
 373         .set_duplex     = sh_eth_set_duplex,
 374         .set_rate       = sh_eth_set_rate_r8a777x,
 375
 376         .register_type  = SH_ETH_REG_FAST_RCAR,
 377
 378         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 379         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 380         .eesipr_value   = 0x01ff009f,
 381
 382         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 383         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 384                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 385                           EESR_ECI,
 386
 387         .apr            = 1,
 388         .mpr            = 1,
 389         .tpauser        = 1,
 390         .hw_swap        = 1,
 391 };
 392
 393 /* R8A7790/1 */
 394 static struct sh_eth_cpu_data r8a779x_data = {
 395         .set_duplex     = sh_eth_set_duplex,
 396         .set_rate       = sh_eth_set_rate_r8a777x,
 397
 398         .register_type  = SH_ETH_REG_FAST_RCAR,
 399
 400         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 401         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 402         .eesipr_value   = 0x01ff009f,
 403
 404         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 405         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 406                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 407                           EESR_ECI,
 408
 409         .apr            = 1,
 410         .mpr            = 1,
 411         .tpauser        = 1,
 412         .hw_swap        = 1,
 413         .rmiimode       = 1,
 414         .shift_rd0      = 1,
 415 };
 416
 417 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 418 {
 419         struct sh_eth_private *mdp = netdev_priv(ndev);
 420
 421         switch (mdp->speed) {
 422         case 10: /* 10BASE */
 423                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 424                 break;
 425         case 100:/* 100BASE */
 426                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 427                 break;
 428         default:
 429                 break;
 430         }
 431 }
 432
 433 /* SH7724 */
 434 static struct sh_eth_cpu_data sh7724_data = {
 435         .set_duplex     = sh_eth_set_duplex,
 436         .set_rate       = sh_eth_set_rate_sh7724,
 437
 438         .register_type  = SH_ETH_REG_FAST_SH4,
 439
 440         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 441         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 442         .eesipr_value   = 0x01ff009f,
 443
 444         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 445         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 446                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 447                           EESR_ECI,
 448
 449         .apr            = 1,
 450         .mpr            = 1,
 451         .tpauser        = 1,
 452         .hw_swap        = 1,
 453         .rpadir         = 1,
 454         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 455 };
 456
 457 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 458 {
 459         struct sh_eth_private *mdp = netdev_priv(ndev);
 460
 461         switch (mdp->speed) {
 462         case 10: /* 10BASE */
 463                 sh_eth_write(ndev, 0, RTRATE);
 464                 break;
 465         case 100:/* 100BASE */
 466                 sh_eth_write(ndev, 1, RTRATE);
 467                 break;
 468         default:
 469                 break;
 470         }
 471 }
 472
 473 /* SH7757 */
 474 static struct sh_eth_cpu_data sh7757_data = {
 475         .set_duplex     = sh_eth_set_duplex,
 476         .set_rate       = sh_eth_set_rate_sh7757,
 477
 478         .register_type  = SH_ETH_REG_FAST_SH4,
 479
 480         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 481         .rmcr_value     = RMCR_RNC,
 482
 483         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 484         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 485                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 486                           EESR_ECI,
 487
 488         .irq_flags      = IRQF_SHARED,
 489         .apr            = 1,
 490         .mpr            = 1,
 491         .tpauser        = 1,
 492         .hw_swap        = 1,
 493         .no_ade         = 1,
 494         .rpadir         = 1,
 495         .rpadir_value   = 2 << 16,
 496 };
 497
 498 #define SH_GIGA_ETH_BASE        0xfee00000UL
 499 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 500 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 501 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 502 {
 503         int i;
 504         unsigned long mahr[2], malr[2];
 505
 506         /* save MAHR and MALR */
 507         for (i = 0; i < 2; i++) {
 508                 malr[i] = ioread32((void *)GIGA_MALR(i));
 509                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 510         }
 511
 512         /* reset device */
 513         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 514         mdelay(1);
 515
 516         /* restore MAHR and MALR */
 517         for (i = 0; i < 2; i++) {
 518                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 519                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 520         }
 521 }
 522
 523 static void sh_eth_set_rate_giga(struct net_device *ndev)
 524 {
 525         struct sh_eth_private *mdp = netdev_priv(ndev);
 526
 527         switch (mdp->speed) {
 528         case 10: /* 10BASE */
 529                 sh_eth_write(ndev, 0x00000000, GECMR);
 530                 break;
 531         case 100:/* 100BASE */
 532                 sh_eth_write(ndev, 0x00000010, GECMR);
 533                 break;
 534         case 1000: /* 1000BASE */
 535                 sh_eth_write(ndev, 0x00000020, GECMR);
 536                 break;
 537         default:
 538                 break;
 539         }
 540 }
 541
 542 /* SH7757(GETHERC) */
 543 static struct sh_eth_cpu_data sh7757_data_giga = {
 544         .chip_reset     = sh_eth_chip_reset_giga,
 545         .set_duplex     = sh_eth_set_duplex,
 546         .set_rate       = sh_eth_set_rate_giga,
 547
 548         .register_type  = SH_ETH_REG_GIGABIT,
 549
 550         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 551         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 552         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 553
 554         .tx_check       = EESR_TC1 | EESR_FTC,
 555         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 556                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 557                           EESR_TDE | EESR_ECI,
 558         .fdr_value      = 0x0000072f,
 559         .rmcr_value     = RMCR_RNC,
 560
 561         .irq_flags      = IRQF_SHARED,
 562         .apr            = 1,
 563         .mpr            = 1,
 564         .tpauser        = 1,
 565         .bculr          = 1,
 566         .hw_swap        = 1,
 567         .rpadir         = 1,
 568         .rpadir_value   = 2 << 16,
 569         .no_trimd       = 1,
 570         .no_ade         = 1,
 571         .tsu            = 1,
 572 };
 573
 574 static void sh_eth_chip_reset(struct net_device *ndev)
 575 {
 576         struct sh_eth_private *mdp = netdev_priv(ndev);
 577
 578         /* reset device */
 579         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 580         mdelay(1);
 581 }
 582
 583 static void sh_eth_set_rate_gether(struct net_device *ndev)
 584 {
 585         struct sh_eth_private *mdp = netdev_priv(ndev);
 586
 587         switch (mdp->speed) {
 588         case 10: /* 10BASE */
 589                 sh_eth_write(ndev, GECMR_10, GECMR);
 590                 break;
 591         case 100:/* 100BASE */
 592                 sh_eth_write(ndev, GECMR_100, GECMR);
 593                 break;
 594         case 1000: /* 1000BASE */
 595                 sh_eth_write(ndev, GECMR_1000, GECMR);
 596                 break;
 597         default:
 598                 break;
 599         }
 600 }
 601
 602 /* SH7734 */
 603 static struct sh_eth_cpu_data sh7734_data = {
 604         .chip_reset     = sh_eth_chip_reset,
 605         .set_duplex     = sh_eth_set_duplex,
 606         .set_rate       = sh_eth_set_rate_gether,
 607
 608         .register_type  = SH_ETH_REG_GIGABIT,
 609
 610         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 611         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 612         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 613
 614         .tx_check       = EESR_TC1 | EESR_FTC,
 615         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 616                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 617                           EESR_TDE | EESR_ECI,
 618
 619         .apr            = 1,
 620         .mpr            = 1,
 621         .tpauser        = 1,
 622         .bculr          = 1,
 623         .hw_swap        = 1,
 624         .no_trimd       = 1,
 625         .no_ade         = 1,
 626         .tsu            = 1,
 627         .hw_crc         = 1,
 628         .select_mii     = 1,
 629 };
 630
 631 /* SH7763 */
 632 static struct sh_eth_cpu_data sh7763_data = {
 633         .chip_reset     = sh_eth_chip_reset,
 634         .set_duplex     = sh_eth_set_duplex,
 635         .set_rate       = sh_eth_set_rate_gether,
 636
 637         .register_type  = SH_ETH_REG_GIGABIT,
 638
 639         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 640         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 641         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 642
 643         .tx_check       = EESR_TC1 | EESR_FTC,
 644         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 645                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 646                           EESR_ECI,
 647
 648         .apr            = 1,
 649         .mpr            = 1,
 650         .tpauser        = 1,
 651         .bculr          = 1,
 652         .hw_swap        = 1,
 653         .no_trimd       = 1,
 654         .no_ade         = 1,
 655         .tsu            = 1,
 656         .irq_flags      = IRQF_SHARED,
 657 };
 658
 659 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 660 {
 661         struct sh_eth_private *mdp = netdev_priv(ndev);
 662
 663         /* reset device */
 664         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 665         mdelay(1);
 666
 667         sh_eth_select_mii(ndev);
 668 }
 669
 670 /* R8A7740 */
 671 static struct sh_eth_cpu_data r8a7740_data = {
 672         .chip_reset     = sh_eth_chip_reset_r8a7740,
 673         .set_duplex     = sh_eth_set_duplex,
 674         .set_rate       = sh_eth_set_rate_gether,
 675
 676         .register_type  = SH_ETH_REG_GIGABIT,
 677
 678         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 679         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 680         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 681
 682         .tx_check       = EESR_TC1 | EESR_FTC,
 683         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 684                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 685                           EESR_TDE | EESR_ECI,
 686         .fdr_value      = 0x0000070f,
 687         .rmcr_value     = RMCR_RNC,
 688
 689         .apr            = 1,
 690         .mpr            = 1,
 691         .tpauser        = 1,
 692         .bculr          = 1,
 693         .hw_swap        = 1,
 694         .rpadir         = 1,
 695         .rpadir_value   = 2 << 16,
 696         .no_trimd       = 1,
 697         .no_ade         = 1,
 698         .tsu            = 1,
 699         .select_mii     = 1,
 700         .shift_rd0      = 1,
 701 };
 702
 703 static struct sh_eth_cpu_data sh7619_data = {
 704         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 705
 706         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 707
 708         .apr            = 1,
 709         .mpr            = 1,
 710         .tpauser        = 1,
 711         .hw_swap        = 1,
 712 };
 713
 714 static struct sh_eth_cpu_data sh771x_data = {
 715         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 716
 717         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 718         .tsu            = 1,
 719 };
 720
 721 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 722 {
 723         if (!cd->ecsr_value)
 724                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 725
 726         if (!cd->ecsipr_value)
 727                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 728
 729         if (!cd->fcftr_value)
 730                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 731                                   DEFAULT_FIFO_F_D_RFD;
 732
 733         if (!cd->fdr_value)
 734                 cd->fdr_value = DEFAULT_FDR_INIT;
 735
 736         if (!cd->rmcr_value)
 737                 cd->rmcr_value = DEFAULT_RMCR_VALUE;
 738
 739         if (!cd->tx_check)
 740                 cd->tx_check = DEFAULT_TX_CHECK;
 741
 742         if (!cd->eesr_err_check)
 743                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 744 }
 745
 746 static int sh_eth_check_reset(struct net_device *ndev)
 747 {
 748         int ret = 0;
 749         int cnt = 100;
 750
 751         while (cnt > 0) {
 752                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 753                         break;
 754                 mdelay(1);
 755                 cnt--;
 756         }
 757         if (cnt <= 0) {
 758                 pr_err("Device reset failed\n");
 759                 ret = -ETIMEDOUT;
 760         }
 761         return ret;
 762 }
 763
 764 static int sh_eth_reset(struct net_device *ndev)
 765 {
 766         struct sh_eth_private *mdp = netdev_priv(ndev);
 767         int ret = 0;
 768
 769         if (sh_eth_is_gether(mdp)) {
 770                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 771                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 772                              EDMR);
 773
 774                 ret = sh_eth_check_reset(ndev);
 775                 if (ret)
 776                         goto out;
 777
 778                 /* Table Init */
 779                 sh_eth_write(ndev, 0x0, TDLAR);
 780                 sh_eth_write(ndev, 0x0, TDFAR);
 781                 sh_eth_write(ndev, 0x0, TDFXR);
 782                 sh_eth_write(ndev, 0x0, TDFFR);
 783                 sh_eth_write(ndev, 0x0, RDLAR);
 784                 sh_eth_write(ndev, 0x0, RDFAR);
 785                 sh_eth_write(ndev, 0x0, RDFXR);
 786                 sh_eth_write(ndev, 0x0, RDFFR);
 787
 788                 /* Reset HW CRC register */
 789                 if (mdp->cd->hw_crc)
 790                         sh_eth_write(ndev, 0x0, CSMR);
 791
 792                 /* Select MII mode */
 793                 if (mdp->cd->select_mii)
 794                         sh_eth_select_mii(ndev);
 795         } else {
 796                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 797                              EDMR);
 798                 mdelay(3);
 799                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 800                              EDMR);
 801         }
 802
 803 out:
 804         return ret;
 805 }
 806
 807 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 808 static void sh_eth_set_receive_align(struct sk_buff *skb)
 809 {
 810         int reserve;
 811
 812         reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
 813         if (reserve)
 814                 skb_reserve(skb, reserve);
 815 }
 816 #else
 817 static void sh_eth_set_receive_align(struct sk_buff *skb)
 818 {
 819         skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
 820 }
 821 #endif
 822
 823
 824 /* CPU <-> EDMAC endian convert */
 825 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 826 {
 827         switch (mdp->edmac_endian) {
 828         case EDMAC_LITTLE_ENDIAN:
 829                 return cpu_to_le32(x);
 830         case EDMAC_BIG_ENDIAN:
 831                 return cpu_to_be32(x);
 832         }
 833         return x;
 834 }
 835
 836 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 837 {
 838         switch (mdp->edmac_endian) {
 839         case EDMAC_LITTLE_ENDIAN:
 840                 return le32_to_cpu(x);
 841         case EDMAC_BIG_ENDIAN:
 842                 return be32_to_cpu(x);
 843         }
 844         return x;
 845 }
 846
 847 /* Program the hardware MAC address from dev->dev_addr. */
 848 static void update_mac_address(struct net_device *ndev)
 849 {
 850         sh_eth_write(ndev,
 851                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 852                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 853         sh_eth_write(ndev,
 854                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 855 }
 856
 857 /* Get MAC address from SuperH MAC address register
 858  *
 859  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 860  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 861  * When you want use this device, you must set MAC address in bootloader.
 862  *
 863  */
 864 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 865 {
 866         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 867                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 868         } else {
 869                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 870                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 871                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 872                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 873                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 874                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 875         }
 876 }
 877
 878 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 879 {
 880         if (sh_eth_is_gether(mdp))
 881                 return EDTRR_TRNS_GETHER;
 882         else
 883                 return EDTRR_TRNS_ETHER;
 884 }
 885
 886 struct bb_info {
 887         void (*set_gate)(void *addr);
 888         struct mdiobb_ctrl ctrl;
 889         void *addr;
 890         u32 mmd_msk;/* MMD */
 891         u32 mdo_msk;
 892         u32 mdi_msk;
 893         u32 mdc_msk;
 894 };
 895
 896 /* PHY bit set */
 897 static void bb_set(void *addr, u32 msk)
 898 {
 899         iowrite32(ioread32(addr) | msk, addr);
 900 }
 901
 902 /* PHY bit clear */
 903 static void bb_clr(void *addr, u32 msk)
 904 {
 905         iowrite32((ioread32(addr) & ~msk), addr);
 906 }
 907
 908 /* PHY bit read */
 909 static int bb_read(void *addr, u32 msk)
 910 {
 911         return (ioread32(addr) & msk) != 0;
 912 }
 913
 914 /* Data I/O pin control */
 915 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
 916 {
 917         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 918
 919         if (bitbang->set_gate)
 920                 bitbang->set_gate(bitbang->addr);
 921
 922         if (bit)
 923                 bb_set(bitbang->addr, bitbang->mmd_msk);
 924         else
 925                 bb_clr(bitbang->addr, bitbang->mmd_msk);
 926 }
 927
 928 /* Set bit data*/
 929 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
 930 {
 931         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 932
 933         if (bitbang->set_gate)
 934                 bitbang->set_gate(bitbang->addr);
 935
 936         if (bit)
 937                 bb_set(bitbang->addr, bitbang->mdo_msk);
 938         else
 939                 bb_clr(bitbang->addr, bitbang->mdo_msk);
 940 }
 941
 942 /* Get bit data*/
 943 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
 944 {
 945         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 946
 947         if (bitbang->set_gate)
 948                 bitbang->set_gate(bitbang->addr);
 949
 950         return bb_read(bitbang->addr, bitbang->mdi_msk);
 951 }
 952
 953 /* MDC pin control */
 954 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
 955 {
 956         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 957
 958         if (bitbang->set_gate)
 959                 bitbang->set_gate(bitbang->addr);
 960
 961         if (bit)
 962                 bb_set(bitbang->addr, bitbang->mdc_msk);
 963         else
 964                 bb_clr(bitbang->addr, bitbang->mdc_msk);
 965 }
 966
 967 /* mdio bus control struct */
 968 static struct mdiobb_ops bb_ops = {
 969         .owner = THIS_MODULE,
 970         .set_mdc = sh_mdc_ctrl,
 971         .set_mdio_dir = sh_mmd_ctrl,
 972         .set_mdio_data = sh_set_mdio,
 973         .get_mdio_data = sh_get_mdio,
 974 };
 975
 976 /* free skb and descriptor buffer */
 977 static void sh_eth_ring_free(struct net_device *ndev)
 978 {
 979         struct sh_eth_private *mdp = netdev_priv(ndev);
 980         int i;
 981
 982         /* Free Rx skb ringbuffer */
 983         if (mdp->rx_skbuff) {
 984                 for (i = 0; i < mdp->num_rx_ring; i++) {
 985                         if (mdp->rx_skbuff[i])
 986                                 dev_kfree_skb(mdp->rx_skbuff[i]);
 987                 }
 988         }
 989         kfree(mdp->rx_skbuff);
 990         mdp->rx_skbuff = NULL;
 991
 992         /* Free Tx skb ringbuffer */
 993         if (mdp->tx_skbuff) {
 994                 for (i = 0; i < mdp->num_tx_ring; i++) {
 995                         if (mdp->tx_skbuff[i])
 996                                 dev_kfree_skb(mdp->tx_skbuff[i]);
 997                 }
 998         }
 999         kfree(mdp->tx_skbuff);
1000         mdp->tx_skbuff = NULL;
1001 }
1002
1003 /* format skb and descriptor buffer */
1004 static void sh_eth_ring_format(struct net_device *ndev)
1005 {
1006         struct sh_eth_private *mdp = netdev_priv(ndev);
1007         int i;
1008         struct sk_buff *skb;
1009         struct sh_eth_rxdesc *rxdesc = NULL;
1010         struct sh_eth_txdesc *txdesc = NULL;
1011         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1012         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1013
1014         mdp->cur_rx = 0;
1015         mdp->cur_tx = 0;
1016         mdp->dirty_rx = 0;
1017         mdp->dirty_tx = 0;
1018
1019         memset(mdp->rx_ring, 0, rx_ringsize);
1020
1021         /* build Rx ring buffer */
1022         for (i = 0; i < mdp->num_rx_ring; i++) {
1023                 /* skb */
1024                 mdp->rx_skbuff[i] = NULL;
1025                 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1026                 mdp->rx_skbuff[i] = skb;
1027                 if (skb == NULL)
1028                         break;
1029                 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1030                                DMA_FROM_DEVICE);
1031                 sh_eth_set_receive_align(skb);
1032
1033                 /* RX descriptor */
1034                 rxdesc = &mdp->rx_ring[i];
1035                 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1036                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1037
1038                 /* The size of the buffer is 16 byte boundary. */
1039                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1040                 /* Rx descriptor address set */
1041                 if (i == 0) {
1042                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1043                         if (sh_eth_is_gether(mdp))
1044                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1045                 }
1046         }
1047
1048         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1049
1050         /* Mark the last entry as wrapping the ring. */
1051         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1052
1053         memset(mdp->tx_ring, 0, tx_ringsize);
1054
1055         /* build Tx ring buffer */
1056         for (i = 0; i < mdp->num_tx_ring; i++) {
1057                 mdp->tx_skbuff[i] = NULL;
1058                 txdesc = &mdp->tx_ring[i];
1059                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1060                 txdesc->buffer_length = 0;
1061                 if (i == 0) {
1062                         /* Tx descriptor address set */
1063                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1064                         if (sh_eth_is_gether(mdp))
1065                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1066                 }
1067         }
1068
1069         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1070 }
1071
1072 /* Get skb and descriptor buffer */
1073 static int sh_eth_ring_init(struct net_device *ndev)
1074 {
1075         struct sh_eth_private *mdp = netdev_priv(ndev);
1076         int rx_ringsize, tx_ringsize, ret = 0;
1077
1078         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1079          * card needs room to do 8 byte alignment, +2 so we can reserve
1080          * the first 2 bytes, and +16 gets room for the status word from the
1081          * card.
1082          */
1083         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1084                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1085         if (mdp->cd->rpadir)
1086                 mdp->rx_buf_sz += NET_IP_ALIGN;
1087
1088         /* Allocate RX and TX skb rings */
1089         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1090                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1091         if (!mdp->rx_skbuff) {
1092                 ret = -ENOMEM;
1093                 return ret;
1094         }
1095
1096         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1097                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1098         if (!mdp->tx_skbuff) {
1099                 ret = -ENOMEM;
1100                 goto skb_ring_free;
1101         }
1102
1103         /* Allocate all Rx descriptors. */
1104         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1105         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1106                                           GFP_KERNEL);
1107         if (!mdp->rx_ring) {
1108                 ret = -ENOMEM;
1109                 goto desc_ring_free;
1110         }
1111
1112         mdp->dirty_rx = 0;
1113
1114         /* Allocate all Tx descriptors. */
1115         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1116         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1117                                           GFP_KERNEL);
1118         if (!mdp->tx_ring) {
1119                 ret = -ENOMEM;
1120                 goto desc_ring_free;
1121         }
1122         return ret;
1123
1124 desc_ring_free:
1125         /* free DMA buffer */
1126         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1127
1128 skb_ring_free:
1129         /* Free Rx and Tx skb ring buffer */
1130         sh_eth_ring_free(ndev);
1131         mdp->tx_ring = NULL;
1132         mdp->rx_ring = NULL;
1133
1134         return ret;
1135 }
1136
1137 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1138 {
1139         int ringsize;
1140
1141         if (mdp->rx_ring) {
1142                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1143                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1144                                   mdp->rx_desc_dma);
1145                 mdp->rx_ring = NULL;
1146         }
1147
1148         if (mdp->tx_ring) {
1149                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1150                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1151                                   mdp->tx_desc_dma);
1152                 mdp->tx_ring = NULL;
1153         }
1154 }
1155
1156 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1157 {
1158         int ret = 0;
1159         struct sh_eth_private *mdp = netdev_priv(ndev);
1160         u32 val;
1161
1162         /* Soft Reset */
1163         ret = sh_eth_reset(ndev);
1164         if (ret)
1165                 goto out;
1166
1167         if (mdp->cd->rmiimode)
1168                 sh_eth_write(ndev, 0x1, RMIIMODE);
1169
1170         /* Descriptor format */
1171         sh_eth_ring_format(ndev);
1172         if (mdp->cd->rpadir)
1173                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1174
1175         /* all sh_eth int mask */
1176         sh_eth_write(ndev, 0, EESIPR);
1177
1178 #if defined(__LITTLE_ENDIAN)
1179         if (mdp->cd->hw_swap)
1180                 sh_eth_write(ndev, EDMR_EL, EDMR);
1181         else
1182 #endif
1183                 sh_eth_write(ndev, 0, EDMR);
1184
1185         /* FIFO size set */
1186         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1187         sh_eth_write(ndev, 0, TFTR);
1188
1189         /* Frame recv control */
1190         sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
1191
1192         sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1193
1194         if (mdp->cd->bculr)
1195                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1196
1197         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1198
1199         if (!mdp->cd->no_trimd)
1200                 sh_eth_write(ndev, 0, TRIMD);
1201
1202         /* Recv frame limit set register */
1203         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1204                      RFLR);
1205
1206         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1207         if (start)
1208                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1209
1210         /* PAUSE Prohibition */
1211         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1212                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1213
1214         sh_eth_write(ndev, val, ECMR);
1215
1216         if (mdp->cd->set_rate)
1217                 mdp->cd->set_rate(ndev);
1218
1219         /* E-MAC Status Register clear */
1220         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1221
1222         /* E-MAC Interrupt Enable register */
1223         if (start)
1224                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1225
1226         /* Set MAC address */
1227         update_mac_address(ndev);
1228
1229         /* mask reset */
1230         if (mdp->cd->apr)
1231                 sh_eth_write(ndev, APR_AP, APR);
1232         if (mdp->cd->mpr)
1233                 sh_eth_write(ndev, MPR_MP, MPR);
1234         if (mdp->cd->tpauser)
1235                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1236
1237         if (start) {
1238                 /* Setting the Rx mode will start the Rx process. */
1239                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1240
1241                 netif_start_queue(ndev);
1242         }
1243
1244 out:
1245         return ret;
1246 }
1247
1248 /* free Tx skb function */
1249 static int sh_eth_txfree(struct net_device *ndev)
1250 {
1251         struct sh_eth_private *mdp = netdev_priv(ndev);
1252         struct sh_eth_txdesc *txdesc;
1253         int free_num = 0;
1254         int entry = 0;
1255
1256         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1257                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1258                 txdesc = &mdp->tx_ring[entry];
1259                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1260                         break;
1261                 /* Free the original skb. */
1262                 if (mdp->tx_skbuff[entry]) {
1263                         dma_unmap_single(&ndev->dev, txdesc->addr,
1264                                          txdesc->buffer_length, DMA_TO_DEVICE);
1265                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1266                         mdp->tx_skbuff[entry] = NULL;
1267                         free_num++;
1268                 }
1269                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1270                 if (entry >= mdp->num_tx_ring - 1)
1271                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1272
1273                 ndev->stats.tx_packets++;
1274                 ndev->stats.tx_bytes += txdesc->buffer_length;
1275         }
1276         return free_num;
1277 }
1278
1279 /* Packet receive function */
1280 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1281 {
1282         struct sh_eth_private *mdp = netdev_priv(ndev);
1283         struct sh_eth_rxdesc *rxdesc;
1284
1285         int entry = mdp->cur_rx % mdp->num_rx_ring;
1286         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1287         struct sk_buff *skb;
1288         int exceeded = 0;
1289         u16 pkt_len = 0;
1290         u32 desc_status;
1291
1292         rxdesc = &mdp->rx_ring[entry];
1293         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1294                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1295                 pkt_len = rxdesc->frame_length;
1296
1297                 if (--boguscnt < 0)
1298                         break;
1299
1300                 if (*quota <= 0) {
1301                         exceeded = 1;
1302                         break;
1303                 }
1304                 (*quota)--;
1305
1306                 if (!(desc_status & RDFEND))
1307                         ndev->stats.rx_length_errors++;
1308
1309                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1310                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1311                  * bit 0. However, in case of the R8A7740's GETHER, the RFS
1312                  * bits are from bit 25 to bit 16. So, the driver needs right
1313                  * shifting by 16.
1314                  */
1315                 if (mdp->cd->shift_rd0)
1316                         desc_status >>= 16;
1317
1318                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1319                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1320                         ndev->stats.rx_errors++;
1321                         if (desc_status & RD_RFS1)
1322                                 ndev->stats.rx_crc_errors++;
1323                         if (desc_status & RD_RFS2)
1324                                 ndev->stats.rx_frame_errors++;
1325                         if (desc_status & RD_RFS3)
1326                                 ndev->stats.rx_length_errors++;
1327                         if (desc_status & RD_RFS4)
1328                                 ndev->stats.rx_length_errors++;
1329                         if (desc_status & RD_RFS6)
1330                                 ndev->stats.rx_missed_errors++;
1331                         if (desc_status & RD_RFS10)
1332                                 ndev->stats.rx_over_errors++;
1333                 } else {
1334                         if (!mdp->cd->hw_swap)
1335                                 sh_eth_soft_swap(
1336                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1337                                         pkt_len + 2);
1338                         skb = mdp->rx_skbuff[entry];
1339                         mdp->rx_skbuff[entry] = NULL;
1340                         if (mdp->cd->rpadir)
1341                                 skb_reserve(skb, NET_IP_ALIGN);
1342                         dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1343                                                 mdp->rx_buf_sz,
1344                                                 DMA_FROM_DEVICE);
1345                         skb_put(skb, pkt_len);
1346                         skb->protocol = eth_type_trans(skb, ndev);
1347                         netif_receive_skb(skb);
1348                         ndev->stats.rx_packets++;
1349                         ndev->stats.rx_bytes += pkt_len;
1350                 }
1351                 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1352                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1353                 rxdesc = &mdp->rx_ring[entry];
1354         }
1355
1356         /* Refill the Rx ring buffers. */
1357         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1358                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1359                 rxdesc = &mdp->rx_ring[entry];
1360                 /* The size of the buffer is 16 byte boundary. */
1361                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1362
1363                 if (mdp->rx_skbuff[entry] == NULL) {
1364                         skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1365                         mdp->rx_skbuff[entry] = skb;
1366                         if (skb == NULL)
1367                                 break;  /* Better luck next round. */
1368                         dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1369                                        DMA_FROM_DEVICE);
1370                         sh_eth_set_receive_align(skb);
1371
1372                         skb_checksum_none_assert(skb);
1373                         rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1374                 }
1375                 if (entry >= mdp->num_rx_ring - 1)
1376                         rxdesc->status |=
1377                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1378                 else
1379                         rxdesc->status |=
1380                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1381         }
1382
1383         /* Restart Rx engine if stopped. */
1384         /* If we don't need to check status, don't. -KDU */
1385         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1386                 /* fix the values for the next receiving if RDE is set */
1387                 if (intr_status & EESR_RDE) {
1388                         u32 count = (sh_eth_read(ndev, RDFAR) -
1389                                      sh_eth_read(ndev, RDLAR)) >> 4;
1390
1391                         mdp->cur_rx = count;
1392                         mdp->dirty_rx = count;
1393                 }
1394                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1395         }
1396
1397         return exceeded;
1398 }
1399
1400 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1401 {
1402         /* disable tx and rx */
1403         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1404                 ~(ECMR_RE | ECMR_TE), ECMR);
1405 }
1406
1407 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1408 {
1409         /* enable tx and rx */
1410         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1411                 (ECMR_RE | ECMR_TE), ECMR);
1412 }
1413
1414 /* error control function */
1415 static void sh_eth_error(struct net_device *ndev, int intr_status)
1416 {
1417         struct sh_eth_private *mdp = netdev_priv(ndev);
1418         u32 felic_stat;
1419         u32 link_stat;
1420         u32 mask;
1421
1422         if (intr_status & EESR_ECI) {
1423                 felic_stat = sh_eth_read(ndev, ECSR);
1424                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1425                 if (felic_stat & ECSR_ICD)
1426                         ndev->stats.tx_carrier_errors++;
1427                 if (felic_stat & ECSR_LCHNG) {
1428                         /* Link Changed */
1429                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1430                                 goto ignore_link;
1431                         } else {
1432                                 link_stat = (sh_eth_read(ndev, PSR));
1433                                 if (mdp->ether_link_active_low)
1434                                         link_stat = ~link_stat;
1435                         }
1436                         if (!(link_stat & PHY_ST_LINK)) {
1437                                 sh_eth_rcv_snd_disable(ndev);
1438                         } else {
1439                                 /* Link Up */
1440                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1441                                                    ~DMAC_M_ECI, EESIPR);
1442                                 /* clear int */
1443                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1444                                              ECSR);
1445                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1446                                                    DMAC_M_ECI, EESIPR);
1447                                 /* enable tx and rx */
1448                                 sh_eth_rcv_snd_enable(ndev);
1449                         }
1450                 }
1451         }
1452
1453 ignore_link:
1454         if (intr_status & EESR_TWB) {
1455                 /* Unused write back interrupt */
1456                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1457                         ndev->stats.tx_aborted_errors++;
1458                         if (netif_msg_tx_err(mdp))
1459                                 dev_err(&ndev->dev, "Transmit Abort\n");
1460                 }
1461         }
1462
1463         if (intr_status & EESR_RABT) {
1464                 /* Receive Abort int */
1465                 if (intr_status & EESR_RFRMER) {
1466                         /* Receive Frame Overflow int */
1467                         ndev->stats.rx_frame_errors++;
1468                         if (netif_msg_rx_err(mdp))
1469                                 dev_err(&ndev->dev, "Receive Abort\n");
1470                 }
1471         }
1472
1473         if (intr_status & EESR_TDE) {
1474                 /* Transmit Descriptor Empty int */
1475                 ndev->stats.tx_fifo_errors++;
1476                 if (netif_msg_tx_err(mdp))
1477                         dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1478         }
1479
1480         if (intr_status & EESR_TFE) {
1481                 /* FIFO under flow */
1482                 ndev->stats.tx_fifo_errors++;
1483                 if (netif_msg_tx_err(mdp))
1484                         dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1485         }
1486
1487         if (intr_status & EESR_RDE) {
1488                 /* Receive Descriptor Empty int */
1489                 ndev->stats.rx_over_errors++;
1490
1491                 if (netif_msg_rx_err(mdp))
1492                         dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1493         }
1494
1495         if (intr_status & EESR_RFE) {
1496                 /* Receive FIFO Overflow int */
1497                 ndev->stats.rx_fifo_errors++;
1498                 if (netif_msg_rx_err(mdp))
1499                         dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1500         }
1501
1502         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1503                 /* Address Error */
1504                 ndev->stats.tx_fifo_errors++;
1505                 if (netif_msg_tx_err(mdp))
1506                         dev_err(&ndev->dev, "Address Error\n");
1507         }
1508
1509         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1510         if (mdp->cd->no_ade)
1511                 mask &= ~EESR_ADE;
1512         if (intr_status & mask) {
1513                 /* Tx error */
1514                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1515
1516                 /* dmesg */
1517                 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1518                         intr_status, mdp->cur_tx, mdp->dirty_tx,
1519                         (u32)ndev->state, edtrr);
1520                 /* dirty buffer free */
1521                 sh_eth_txfree(ndev);
1522
1523                 /* SH7712 BUG */
1524                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1525                         /* tx dma start */
1526                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1527                 }
1528                 /* wakeup */
1529                 netif_wake_queue(ndev);
1530         }
1531 }
1532
1533 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1534 {
1535         struct net_device *ndev = netdev;
1536         struct sh_eth_private *mdp = netdev_priv(ndev);
1537         struct sh_eth_cpu_data *cd = mdp->cd;
1538         irqreturn_t ret = IRQ_NONE;
1539         unsigned long intr_status, intr_enable;
1540
1541         spin_lock(&mdp->lock);
1542
1543         /* Get interrupt status */
1544         intr_status = sh_eth_read(ndev, EESR);
1545         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1546          * enabled since it's the one that  comes thru regardless of the mask,
1547          * and we need to fully handle it in sh_eth_error() in order to quench
1548          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1549          */
1550         intr_enable = sh_eth_read(ndev, EESIPR);
1551         intr_status &= intr_enable | DMAC_M_ECI;
1552         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1553                 ret = IRQ_HANDLED;
1554         else
1555                 goto other_irq;
1556
1557         if (intr_status & EESR_RX_CHECK) {
1558                 if (napi_schedule_prep(&mdp->napi)) {
1559                         /* Mask Rx interrupts */
1560                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1561                                      EESIPR);
1562                         __napi_schedule(&mdp->napi);
1563                 } else {
1564                         dev_warn(&ndev->dev,
1565                                  "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1566                                  intr_status, intr_enable);
1567                 }
1568         }
1569
1570         /* Tx Check */
1571         if (intr_status & cd->tx_check) {
1572                 /* Clear Tx interrupts */
1573                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1574
1575                 sh_eth_txfree(ndev);
1576                 netif_wake_queue(ndev);
1577         }
1578
1579         if (intr_status & cd->eesr_err_check) {
1580                 /* Clear error interrupts */
1581                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1582
1583                 sh_eth_error(ndev, intr_status);
1584         }
1585
1586 other_irq:
1587         spin_unlock(&mdp->lock);
1588
1589         return ret;
1590 }
1591
1592 static int sh_eth_poll(struct napi_struct *napi, int budget)
1593 {
1594         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1595                                                   napi);
1596         struct net_device *ndev = napi->dev;
1597         int quota = budget;
1598         unsigned long intr_status;
1599
1600         for (;;) {
1601                 intr_status = sh_eth_read(ndev, EESR);
1602                 if (!(intr_status & EESR_RX_CHECK))
1603                         break;
1604                 /* Clear Rx interrupts */
1605                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1606
1607                 if (sh_eth_rx(ndev, intr_status, &quota))
1608                         goto out;
1609         }
1610
1611         napi_complete(napi);
1612
1613         /* Reenable Rx interrupts */
1614         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1615 out:
1616         return budget - quota;
1617 }
1618
1619 /* PHY state control function */
1620 static void sh_eth_adjust_link(struct net_device *ndev)
1621 {
1622         struct sh_eth_private *mdp = netdev_priv(ndev);
1623         struct phy_device *phydev = mdp->phydev;
1624         int new_state = 0;
1625
1626         if (phydev->link) {
1627                 if (phydev->duplex != mdp->duplex) {
1628                         new_state = 1;
1629                         mdp->duplex = phydev->duplex;
1630                         if (mdp->cd->set_duplex)
1631                                 mdp->cd->set_duplex(ndev);
1632                 }
1633
1634                 if (phydev->speed != mdp->speed) {
1635                         new_state = 1;
1636                         mdp->speed = phydev->speed;
1637                         if (mdp->cd->set_rate)
1638                                 mdp->cd->set_rate(ndev);
1639                 }
1640                 if (!mdp->link) {
1641                         sh_eth_write(ndev,
1642                                      sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1643                                      ECMR);
1644                         new_state = 1;
1645                         mdp->link = phydev->link;
1646                         if (mdp->cd->no_psr || mdp->no_ether_link)
1647                                 sh_eth_rcv_snd_enable(ndev);
1648                 }
1649         } else if (mdp->link) {
1650                 new_state = 1;
1651                 mdp->link = 0;
1652                 mdp->speed = 0;
1653                 mdp->duplex = -1;
1654                 if (mdp->cd->no_psr || mdp->no_ether_link)
1655                         sh_eth_rcv_snd_disable(ndev);
1656         }
1657
1658         if (new_state && netif_msg_link(mdp))
1659                 phy_print_status(phydev);
1660 }
1661
1662 /* PHY init function */
1663 static int sh_eth_phy_init(struct net_device *ndev)
1664 {
1665         struct sh_eth_private *mdp = netdev_priv(ndev);
1666         char phy_id[MII_BUS_ID_SIZE + 3];
1667         struct phy_device *phydev = NULL;
1668
1669         snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1670                  mdp->mii_bus->id, mdp->phy_id);
1671
1672         mdp->link = 0;
1673         mdp->speed = 0;
1674         mdp->duplex = -1;
1675
1676         /* Try connect to PHY */
1677         phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1678                              mdp->phy_interface);
1679         if (IS_ERR(phydev)) {
1680                 dev_err(&ndev->dev, "phy_connect failed\n");
1681                 return PTR_ERR(phydev);
1682         }
1683
1684         dev_info(&ndev->dev, "attached PHY %d (IRQ %d) to driver %s\n",
1685                  phydev->addr, phydev->irq, phydev->drv->name);
1686
1687         mdp->phydev = phydev;
1688
1689         return 0;
1690 }
1691
1692 /* PHY control start function */
1693 static int sh_eth_phy_start(struct net_device *ndev)
1694 {
1695         struct sh_eth_private *mdp = netdev_priv(ndev);
1696         int ret;
1697
1698         ret = sh_eth_phy_init(ndev);
1699         if (ret)
1700                 return ret;
1701
1702         phy_start(mdp->phydev);
1703
1704         return 0;
1705 }
1706
1707 static int sh_eth_get_settings(struct net_device *ndev,
1708                                struct ethtool_cmd *ecmd)
1709 {
1710         struct sh_eth_private *mdp = netdev_priv(ndev);
1711         unsigned long flags;
1712         int ret;
1713
1714         spin_lock_irqsave(&mdp->lock, flags);
1715         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1716         spin_unlock_irqrestore(&mdp->lock, flags);
1717
1718         return ret;
1719 }
1720
1721 static int sh_eth_set_settings(struct net_device *ndev,
1722                                struct ethtool_cmd *ecmd)
1723 {
1724         struct sh_eth_private *mdp = netdev_priv(ndev);
1725         unsigned long flags;
1726         int ret;
1727
1728         spin_lock_irqsave(&mdp->lock, flags);
1729
1730         /* disable tx and rx */
1731         sh_eth_rcv_snd_disable(ndev);
1732
1733         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1734         if (ret)
1735                 goto error_exit;
1736
1737         if (ecmd->duplex == DUPLEX_FULL)
1738                 mdp->duplex = 1;
1739         else
1740                 mdp->duplex = 0;
1741
1742         if (mdp->cd->set_duplex)
1743                 mdp->cd->set_duplex(ndev);
1744
1745 error_exit:
1746         mdelay(1);
1747
1748         /* enable tx and rx */
1749         sh_eth_rcv_snd_enable(ndev);
1750
1751         spin_unlock_irqrestore(&mdp->lock, flags);
1752
1753         return ret;
1754 }
1755
1756 static int sh_eth_nway_reset(struct net_device *ndev)
1757 {
1758         struct sh_eth_private *mdp = netdev_priv(ndev);
1759         unsigned long flags;
1760         int ret;
1761
1762         spin_lock_irqsave(&mdp->lock, flags);
1763         ret = phy_start_aneg(mdp->phydev);
1764         spin_unlock_irqrestore(&mdp->lock, flags);
1765
1766         return ret;
1767 }
1768
1769 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1770 {
1771         struct sh_eth_private *mdp = netdev_priv(ndev);
1772         return mdp->msg_enable;
1773 }
1774
1775 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1776 {
1777         struct sh_eth_private *mdp = netdev_priv(ndev);
1778         mdp->msg_enable = value;
1779 }
1780
1781 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1782         "rx_current", "tx_current",
1783         "rx_dirty", "tx_dirty",
1784 };
1785 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1786
1787 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1788 {
1789         switch (sset) {
1790         case ETH_SS_STATS:
1791                 return SH_ETH_STATS_LEN;
1792         default:
1793                 return -EOPNOTSUPP;
1794         }
1795 }
1796
1797 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1798                                      struct ethtool_stats *stats, u64 *data)
1799 {
1800         struct sh_eth_private *mdp = netdev_priv(ndev);
1801         int i = 0;
1802
1803         /* device-specific stats */
1804         data[i++] = mdp->cur_rx;
1805         data[i++] = mdp->cur_tx;
1806         data[i++] = mdp->dirty_rx;
1807         data[i++] = mdp->dirty_tx;
1808 }
1809
1810 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1811 {
1812         switch (stringset) {
1813         case ETH_SS_STATS:
1814                 memcpy(data, *sh_eth_gstrings_stats,
1815                        sizeof(sh_eth_gstrings_stats));
1816                 break;
1817         }
1818 }
1819
1820 static void sh_eth_get_ringparam(struct net_device *ndev,
1821                                  struct ethtool_ringparam *ring)
1822 {
1823         struct sh_eth_private *mdp = netdev_priv(ndev);
1824
1825         ring->rx_max_pending = RX_RING_MAX;
1826         ring->tx_max_pending = TX_RING_MAX;
1827         ring->rx_pending = mdp->num_rx_ring;
1828         ring->tx_pending = mdp->num_tx_ring;
1829 }
1830
1831 static int sh_eth_set_ringparam(struct net_device *ndev,
1832                                 struct ethtool_ringparam *ring)
1833 {
1834         struct sh_eth_private *mdp = netdev_priv(ndev);
1835         int ret;
1836
1837         if (ring->tx_pending > TX_RING_MAX ||
1838             ring->rx_pending > RX_RING_MAX ||
1839             ring->tx_pending < TX_RING_MIN ||
1840             ring->rx_pending < RX_RING_MIN)
1841                 return -EINVAL;
1842         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1843                 return -EINVAL;
1844
1845         if (netif_running(ndev)) {
1846                 netif_tx_disable(ndev);
1847                 /* Disable interrupts by clearing the interrupt mask. */
1848                 sh_eth_write(ndev, 0x0000, EESIPR);
1849                 /* Stop the chip's Tx and Rx processes. */
1850                 sh_eth_write(ndev, 0, EDTRR);
1851                 sh_eth_write(ndev, 0, EDRRR);
1852                 synchronize_irq(ndev->irq);
1853         }
1854
1855         /* Free all the skbuffs in the Rx queue. */
1856         sh_eth_ring_free(ndev);
1857         /* Free DMA buffer */
1858         sh_eth_free_dma_buffer(mdp);
1859
1860         /* Set new parameters */
1861         mdp->num_rx_ring = ring->rx_pending;
1862         mdp->num_tx_ring = ring->tx_pending;
1863
1864         ret = sh_eth_ring_init(ndev);
1865         if (ret < 0) {
1866                 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1867                 return ret;
1868         }
1869         ret = sh_eth_dev_init(ndev, false);
1870         if (ret < 0) {
1871                 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1872                 return ret;
1873         }
1874
1875         if (netif_running(ndev)) {
1876                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1877                 /* Setting the Rx mode will start the Rx process. */
1878                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1879                 netif_wake_queue(ndev);
1880         }
1881
1882         return 0;
1883 }
1884
1885 static const struct ethtool_ops sh_eth_ethtool_ops = {
1886         .get_settings   = sh_eth_get_settings,
1887         .set_settings   = sh_eth_set_settings,
1888         .nway_reset     = sh_eth_nway_reset,
1889         .get_msglevel   = sh_eth_get_msglevel,
1890         .set_msglevel   = sh_eth_set_msglevel,
1891         .get_link       = ethtool_op_get_link,
1892         .get_strings    = sh_eth_get_strings,
1893         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
1894         .get_sset_count     = sh_eth_get_sset_count,
1895         .get_ringparam  = sh_eth_get_ringparam,
1896         .set_ringparam  = sh_eth_set_ringparam,
1897 };
1898
1899 /* network device open function */
1900 static int sh_eth_open(struct net_device *ndev)
1901 {
1902         int ret = 0;
1903         struct sh_eth_private *mdp = netdev_priv(ndev);
1904
1905         pm_runtime_get_sync(&mdp->pdev->dev);
1906
1907         napi_enable(&mdp->napi);
1908
1909         ret = request_irq(ndev->irq, sh_eth_interrupt,
1910                           mdp->cd->irq_flags, ndev->name, ndev);
1911         if (ret) {
1912                 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1913                 goto out_napi_off;
1914         }
1915
1916         /* Descriptor set */
1917         ret = sh_eth_ring_init(ndev);
1918         if (ret)
1919                 goto out_free_irq;
1920
1921         /* device init */
1922         ret = sh_eth_dev_init(ndev, true);
1923         if (ret)
1924                 goto out_free_irq;
1925
1926         /* PHY control start*/
1927         ret = sh_eth_phy_start(ndev);
1928         if (ret)
1929                 goto out_free_irq;
1930
1931         return ret;
1932
1933 out_free_irq:
1934         free_irq(ndev->irq, ndev);
1935 out_napi_off:
1936         napi_disable(&mdp->napi);
1937         pm_runtime_put_sync(&mdp->pdev->dev);
1938         return ret;
1939 }
1940
1941 /* Timeout function */
1942 static void sh_eth_tx_timeout(struct net_device *ndev)
1943 {
1944         struct sh_eth_private *mdp = netdev_priv(ndev);
1945         struct sh_eth_rxdesc *rxdesc;
1946         int i;
1947
1948         netif_stop_queue(ndev);
1949
1950         if (netif_msg_timer(mdp)) {
1951                 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x, resetting...\n",
1952                         ndev->name, (int)sh_eth_read(ndev, EESR));
1953         }
1954
1955         /* tx_errors count up */
1956         ndev->stats.tx_errors++;
1957
1958         /* Free all the skbuffs in the Rx queue. */
1959         for (i = 0; i < mdp->num_rx_ring; i++) {
1960                 rxdesc = &mdp->rx_ring[i];
1961                 rxdesc->status = 0;
1962                 rxdesc->addr = 0xBADF00D0;
1963                 if (mdp->rx_skbuff[i])
1964                         dev_kfree_skb(mdp->rx_skbuff[i]);
1965                 mdp->rx_skbuff[i] = NULL;
1966         }
1967         for (i = 0; i < mdp->num_tx_ring; i++) {
1968                 if (mdp->tx_skbuff[i])
1969                         dev_kfree_skb(mdp->tx_skbuff[i]);
1970                 mdp->tx_skbuff[i] = NULL;
1971         }
1972
1973         /* device init */
1974         sh_eth_dev_init(ndev, true);
1975 }
1976
1977 /* Packet transmit function */
1978 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1979 {
1980         struct sh_eth_private *mdp = netdev_priv(ndev);
1981         struct sh_eth_txdesc *txdesc;
1982         u32 entry;
1983         unsigned long flags;
1984
1985         spin_lock_irqsave(&mdp->lock, flags);
1986         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1987                 if (!sh_eth_txfree(ndev)) {
1988                         if (netif_msg_tx_queued(mdp))
1989                                 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1990                         netif_stop_queue(ndev);
1991                         spin_unlock_irqrestore(&mdp->lock, flags);
1992                         return NETDEV_TX_BUSY;
1993                 }
1994         }
1995         spin_unlock_irqrestore(&mdp->lock, flags);
1996
1997         entry = mdp->cur_tx % mdp->num_tx_ring;
1998         mdp->tx_skbuff[entry] = skb;
1999         txdesc = &mdp->tx_ring[entry];
2000         /* soft swap. */
2001         if (!mdp->cd->hw_swap)
2002                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2003                                  skb->len + 2);
2004         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2005                                       DMA_TO_DEVICE);
2006         if (skb->len < ETHERSMALL)
2007                 txdesc->buffer_length = ETHERSMALL;
2008         else
2009                 txdesc->buffer_length = skb->len;
2010
2011         if (entry >= mdp->num_tx_ring - 1)
2012                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2013         else
2014                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2015
2016         mdp->cur_tx++;
2017
2018         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2019                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2020
2021         return NETDEV_TX_OK;
2022 }
2023
2024 /* device close function */
2025 static int sh_eth_close(struct net_device *ndev)
2026 {
2027         struct sh_eth_private *mdp = netdev_priv(ndev);
2028
2029         netif_stop_queue(ndev);
2030
2031         /* Disable interrupts by clearing the interrupt mask. */
2032         sh_eth_write(ndev, 0x0000, EESIPR);
2033
2034         /* Stop the chip's Tx and Rx processes. */
2035         sh_eth_write(ndev, 0, EDTRR);
2036         sh_eth_write(ndev, 0, EDRRR);
2037
2038         /* PHY Disconnect */
2039         if (mdp->phydev) {
2040                 phy_stop(mdp->phydev);
2041                 phy_disconnect(mdp->phydev);
2042         }
2043
2044         free_irq(ndev->irq, ndev);
2045
2046         napi_disable(&mdp->napi);
2047
2048         /* Free all the skbuffs in the Rx queue. */
2049         sh_eth_ring_free(ndev);
2050
2051         /* free DMA buffer */
2052         sh_eth_free_dma_buffer(mdp);
2053
2054         pm_runtime_put_sync(&mdp->pdev->dev);
2055
2056         return 0;
2057 }
2058
2059 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2060 {
2061         struct sh_eth_private *mdp = netdev_priv(ndev);
2062
2063         pm_runtime_get_sync(&mdp->pdev->dev);
2064
2065         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2066         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
2067         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2068         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
2069         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2070         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
2071         if (sh_eth_is_gether(mdp)) {
2072                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2073                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
2074                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2075                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
2076         } else {
2077                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2078                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
2079         }
2080         pm_runtime_put_sync(&mdp->pdev->dev);
2081
2082         return &ndev->stats;
2083 }
2084
2085 /* ioctl to device function */
2086 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2087 {
2088         struct sh_eth_private *mdp = netdev_priv(ndev);
2089         struct phy_device *phydev = mdp->phydev;
2090
2091         if (!netif_running(ndev))
2092                 return -EINVAL;
2093
2094         if (!phydev)
2095                 return -ENODEV;
2096
2097         return phy_mii_ioctl(phydev, rq, cmd);
2098 }
2099
2100 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2101 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2102                                             int entry)
2103 {
2104         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2105 }
2106
2107 static u32 sh_eth_tsu_get_post_mask(int entry)
2108 {
2109         return 0x0f << (28 - ((entry % 8) * 4));
2110 }
2111
2112 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2113 {
2114         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2115 }
2116
2117 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2118                                              int entry)
2119 {
2120         struct sh_eth_private *mdp = netdev_priv(ndev);
2121         u32 tmp;
2122         void *reg_offset;
2123
2124         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2125         tmp = ioread32(reg_offset);
2126         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2127 }
2128
2129 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2130                                               int entry)
2131 {
2132         struct sh_eth_private *mdp = netdev_priv(ndev);
2133         u32 post_mask, ref_mask, tmp;
2134         void *reg_offset;
2135
2136         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2137         post_mask = sh_eth_tsu_get_post_mask(entry);
2138         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2139
2140         tmp = ioread32(reg_offset);
2141         iowrite32(tmp & ~post_mask, reg_offset);
2142
2143         /* If other port enables, the function returns "true" */
2144         return tmp & ref_mask;
2145 }
2146
2147 static int sh_eth_tsu_busy(struct net_device *ndev)
2148 {
2149         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2150         struct sh_eth_private *mdp = netdev_priv(ndev);
2151
2152         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2153                 udelay(10);
2154                 timeout--;
2155                 if (timeout <= 0) {
2156                         dev_err(&ndev->dev, "%s: timeout\n", __func__);
2157                         return -ETIMEDOUT;
2158                 }
2159         }
2160
2161         return 0;
2162 }
2163
2164 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2165                                   const u8 *addr)
2166 {
2167         u32 val;
2168
2169         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2170         iowrite32(val, reg);
2171         if (sh_eth_tsu_busy(ndev) < 0)
2172                 return -EBUSY;
2173
2174         val = addr[4] << 8 | addr[5];
2175         iowrite32(val, reg + 4);
2176         if (sh_eth_tsu_busy(ndev) < 0)
2177                 return -EBUSY;
2178
2179         return 0;
2180 }
2181
2182 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2183 {
2184         u32 val;
2185
2186         val = ioread32(reg);
2187         addr[0] = (val >> 24) & 0xff;
2188         addr[1] = (val >> 16) & 0xff;
2189         addr[2] = (val >> 8) & 0xff;
2190         addr[3] = val & 0xff;
2191         val = ioread32(reg + 4);
2192         addr[4] = (val >> 8) & 0xff;
2193         addr[5] = val & 0xff;
2194 }
2195
2196
2197 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2198 {
2199         struct sh_eth_private *mdp = netdev_priv(ndev);
2200         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2201         int i;
2202         u8 c_addr[ETH_ALEN];
2203
2204         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2205                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2206                 if (ether_addr_equal(addr, c_addr))
2207                         return i;
2208         }
2209
2210         return -ENOENT;
2211 }
2212
2213 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2214 {
2215         u8 blank[ETH_ALEN];
2216         int entry;
2217
2218         memset(blank, 0, sizeof(blank));
2219         entry = sh_eth_tsu_find_entry(ndev, blank);
2220         return (entry < 0) ? -ENOMEM : entry;
2221 }
2222
2223 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2224                                               int entry)
2225 {
2226         struct sh_eth_private *mdp = netdev_priv(ndev);
2227         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2228         int ret;
2229         u8 blank[ETH_ALEN];
2230
2231         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2232                          ~(1 << (31 - entry)), TSU_TEN);
2233
2234         memset(blank, 0, sizeof(blank));
2235         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2236         if (ret < 0)
2237                 return ret;
2238         return 0;
2239 }
2240
2241 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2242 {
2243         struct sh_eth_private *mdp = netdev_priv(ndev);
2244         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2245         int i, ret;
2246
2247         if (!mdp->cd->tsu)
2248                 return 0;
2249
2250         i = sh_eth_tsu_find_entry(ndev, addr);
2251         if (i < 0) {
2252                 /* No entry found, create one */
2253                 i = sh_eth_tsu_find_empty(ndev);
2254                 if (i < 0)
2255                         return -ENOMEM;
2256                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2257                 if (ret < 0)
2258                         return ret;
2259
2260                 /* Enable the entry */
2261                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2262                                  (1 << (31 - i)), TSU_TEN);
2263         }
2264
2265         /* Entry found or created, enable POST */
2266         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2267
2268         return 0;
2269 }
2270
2271 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2272 {
2273         struct sh_eth_private *mdp = netdev_priv(ndev);
2274         int i, ret;
2275
2276         if (!mdp->cd->tsu)
2277                 return 0;
2278
2279         i = sh_eth_tsu_find_entry(ndev, addr);
2280         if (i) {
2281                 /* Entry found */
2282                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2283                         goto done;
2284
2285                 /* Disable the entry if both ports was disabled */
2286                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2287                 if (ret < 0)
2288                         return ret;
2289         }
2290 done:
2291         return 0;
2292 }
2293
2294 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2295 {
2296         struct sh_eth_private *mdp = netdev_priv(ndev);
2297         int i, ret;
2298
2299         if (unlikely(!mdp->cd->tsu))
2300                 return 0;
2301
2302         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2303                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2304                         continue;
2305
2306                 /* Disable the entry if both ports was disabled */
2307                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2308                 if (ret < 0)
2309                         return ret;
2310         }
2311
2312         return 0;
2313 }
2314
2315 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2316 {
2317         struct sh_eth_private *mdp = netdev_priv(ndev);
2318         u8 addr[ETH_ALEN];
2319         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2320         int i;
2321
2322         if (unlikely(!mdp->cd->tsu))
2323                 return;
2324
2325         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2326                 sh_eth_tsu_read_entry(reg_offset, addr);
2327                 if (is_multicast_ether_addr(addr))
2328                         sh_eth_tsu_del_entry(ndev, addr);
2329         }
2330 }
2331
2332 /* Multicast reception directions set */
2333 static void sh_eth_set_multicast_list(struct net_device *ndev)
2334 {
2335         struct sh_eth_private *mdp = netdev_priv(ndev);
2336         u32 ecmr_bits;
2337         int mcast_all = 0;
2338         unsigned long flags;
2339
2340         spin_lock_irqsave(&mdp->lock, flags);
2341         /* Initial condition is MCT = 1, PRM = 0.
2342          * Depending on ndev->flags, set PRM or clear MCT
2343          */
2344         ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2345
2346         if (!(ndev->flags & IFF_MULTICAST)) {
2347                 sh_eth_tsu_purge_mcast(ndev);
2348                 mcast_all = 1;
2349         }
2350         if (ndev->flags & IFF_ALLMULTI) {
2351                 sh_eth_tsu_purge_mcast(ndev);
2352                 ecmr_bits &= ~ECMR_MCT;
2353                 mcast_all = 1;
2354         }
2355
2356         if (ndev->flags & IFF_PROMISC) {
2357                 sh_eth_tsu_purge_all(ndev);
2358                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2359         } else if (mdp->cd->tsu) {
2360                 struct netdev_hw_addr *ha;
2361                 netdev_for_each_mc_addr(ha, ndev) {
2362                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2363                                 continue;
2364
2365                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2366                                 if (!mcast_all) {
2367                                         sh_eth_tsu_purge_mcast(ndev);
2368                                         ecmr_bits &= ~ECMR_MCT;
2369                                         mcast_all = 1;
2370                                 }
2371                         }
2372                 }
2373         } else {
2374                 /* Normal, unicast/broadcast-only mode. */
2375                 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2376         }
2377
2378         /* update the ethernet mode */
2379         sh_eth_write(ndev, ecmr_bits, ECMR);
2380
2381         spin_unlock_irqrestore(&mdp->lock, flags);
2382 }
2383
2384 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2385 {
2386         if (!mdp->port)
2387                 return TSU_VTAG0;
2388         else
2389                 return TSU_VTAG1;
2390 }
2391
2392 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2393                                   __be16 proto, u16 vid)
2394 {
2395         struct sh_eth_private *mdp = netdev_priv(ndev);
2396         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2397
2398         if (unlikely(!mdp->cd->tsu))
2399                 return -EPERM;
2400
2401         /* No filtering if vid = 0 */
2402         if (!vid)
2403                 return 0;
2404
2405         mdp->vlan_num_ids++;
2406
2407         /* The controller has one VLAN tag HW filter. So, if the filter is
2408          * already enabled, the driver disables it and the filte
2409          */
2410         if (mdp->vlan_num_ids > 1) {
2411                 /* disable VLAN filter */
2412                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2413                 return 0;
2414         }
2415
2416         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2417                          vtag_reg_index);
2418
2419         return 0;
2420 }
2421
2422 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2423                                    __be16 proto, u16 vid)
2424 {
2425         struct sh_eth_private *mdp = netdev_priv(ndev);
2426         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2427
2428         if (unlikely(!mdp->cd->tsu))
2429                 return -EPERM;
2430
2431         /* No filtering if vid = 0 */
2432         if (!vid)
2433                 return 0;
2434
2435         mdp->vlan_num_ids--;
2436         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2437
2438         return 0;
2439 }
2440
2441 /* SuperH's TSU register init function */
2442 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2443 {
2444         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2445         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2446         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2447         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2448         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2449         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2450         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2451         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2452         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2453         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2454         if (sh_eth_is_gether(mdp)) {
2455                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2456                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2457         } else {
2458                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2459                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2460         }
2461         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2462         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2463         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2464         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2465         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2466         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2467         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2468 }
2469
2470 /* MDIO bus release function */
2471 static int sh_mdio_release(struct net_device *ndev)
2472 {
2473         struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2474
2475         /* unregister mdio bus */
2476         mdiobus_unregister(bus);
2477
2478         /* remove mdio bus info from net_device */
2479         dev_set_drvdata(&ndev->dev, NULL);
2480
2481         /* free bitbang info */
2482         free_mdio_bitbang(bus);
2483
2484         return 0;
2485 }
2486
2487 /* MDIO bus init function */
2488 static int sh_mdio_init(struct net_device *ndev, int id,
2489                         struct sh_eth_plat_data *pd)
2490 {
2491         int ret, i;
2492         struct bb_info *bitbang;
2493         struct sh_eth_private *mdp = netdev_priv(ndev);
2494
2495         /* create bit control struct for PHY */
2496         bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2497                                GFP_KERNEL);
2498         if (!bitbang) {
2499                 ret = -ENOMEM;
2500                 goto out;
2501         }
2502
2503         /* bitbang init */
2504         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2505         bitbang->set_gate = pd->set_mdio_gate;
2506         bitbang->mdi_msk = PIR_MDI;
2507         bitbang->mdo_msk = PIR_MDO;
2508         bitbang->mmd_msk = PIR_MMD;
2509         bitbang->mdc_msk = PIR_MDC;
2510         bitbang->ctrl.ops = &bb_ops;
2511
2512         /* MII controller setting */
2513         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2514         if (!mdp->mii_bus) {
2515                 ret = -ENOMEM;
2516                 goto out;
2517         }
2518
2519         /* Hook up MII support for ethtool */
2520         mdp->mii_bus->name = "sh_mii";
2521         mdp->mii_bus->parent = &ndev->dev;
2522         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2523                  mdp->pdev->name, id);
2524
2525         /* PHY IRQ */
2526         mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2527                                          sizeof(int) * PHY_MAX_ADDR,
2528                                          GFP_KERNEL);
2529         if (!mdp->mii_bus->irq) {
2530                 ret = -ENOMEM;
2531                 goto out_free_bus;
2532         }
2533
2534         for (i = 0; i < PHY_MAX_ADDR; i++)
2535                 mdp->mii_bus->irq[i] = PHY_POLL;
2536         if (pd->phy_irq > 0)
2537                 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2538
2539         /* register mdio bus */
2540         ret = mdiobus_register(mdp->mii_bus);
2541         if (ret)
2542                 goto out_free_bus;
2543
2544         dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2545
2546         return 0;
2547
2548 out_free_bus:
2549         free_mdio_bitbang(mdp->mii_bus);
2550
2551 out:
2552         return ret;
2553 }
2554
2555 static const u16 *sh_eth_get_register_offset(int register_type)
2556 {
2557         const u16 *reg_offset = NULL;
2558
2559         switch (register_type) {
2560         case SH_ETH_REG_GIGABIT:
2561                 reg_offset = sh_eth_offset_gigabit;
2562                 break;
2563         case SH_ETH_REG_FAST_RCAR:
2564                 reg_offset = sh_eth_offset_fast_rcar;
2565                 break;
2566         case SH_ETH_REG_FAST_SH4:
2567                 reg_offset = sh_eth_offset_fast_sh4;
2568                 break;
2569         case SH_ETH_REG_FAST_SH3_SH2:
2570                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2571                 break;
2572         default:
2573                 pr_err("Unknown register type (%d)\n", register_type);
2574                 break;
2575         }
2576
2577         return reg_offset;
2578 }
2579
2580 static const struct net_device_ops sh_eth_netdev_ops = {
2581         .ndo_open               = sh_eth_open,
2582         .ndo_stop               = sh_eth_close,
2583         .ndo_start_xmit         = sh_eth_start_xmit,
2584         .ndo_get_stats          = sh_eth_get_stats,
2585         .ndo_tx_timeout         = sh_eth_tx_timeout,
2586         .ndo_do_ioctl           = sh_eth_do_ioctl,
2587         .ndo_validate_addr      = eth_validate_addr,
2588         .ndo_set_mac_address    = eth_mac_addr,
2589         .ndo_change_mtu         = eth_change_mtu,
2590 };
2591
2592 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2593         .ndo_open               = sh_eth_open,
2594         .ndo_stop               = sh_eth_close,
2595         .ndo_start_xmit         = sh_eth_start_xmit,
2596         .ndo_get_stats          = sh_eth_get_stats,
2597         .ndo_set_rx_mode        = sh_eth_set_multicast_list,
2598         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2599         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2600         .ndo_tx_timeout         = sh_eth_tx_timeout,
2601         .ndo_do_ioctl           = sh_eth_do_ioctl,
2602         .ndo_validate_addr      = eth_validate_addr,
2603         .ndo_set_mac_address    = eth_mac_addr,
2604         .ndo_change_mtu         = eth_change_mtu,
2605 };
2606
2607 static int sh_eth_drv_probe(struct platform_device *pdev)
2608 {
2609         int ret, devno = 0;
2610         struct resource *res;
2611         struct net_device *ndev = NULL;
2612         struct sh_eth_private *mdp = NULL;
2613         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2614         const struct platform_device_id *id = platform_get_device_id(pdev);
2615
2616         /* get base addr */
2617         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2618         if (unlikely(res == NULL)) {
2619                 dev_err(&pdev->dev, "invalid resource\n");
2620                 ret = -EINVAL;
2621                 goto out;
2622         }
2623
2624         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2625         if (!ndev) {
2626                 ret = -ENOMEM;
2627                 goto out;
2628         }
2629
2630         /* The sh Ether-specific entries in the device structure. */
2631         ndev->base_addr = res->start;
2632         devno = pdev->id;
2633         if (devno < 0)
2634                 devno = 0;
2635
2636         ndev->dma = -1;
2637         ret = platform_get_irq(pdev, 0);
2638         if (ret < 0) {
2639                 ret = -ENODEV;
2640                 goto out_release;
2641         }
2642         ndev->irq = ret;
2643
2644         SET_NETDEV_DEV(ndev, &pdev->dev);
2645
2646         mdp = netdev_priv(ndev);
2647         mdp->num_tx_ring = TX_RING_SIZE;
2648         mdp->num_rx_ring = RX_RING_SIZE;
2649         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2650         if (IS_ERR(mdp->addr)) {
2651                 ret = PTR_ERR(mdp->addr);
2652                 goto out_release;
2653         }
2654
2655         spin_lock_init(&mdp->lock);
2656         mdp->pdev = pdev;
2657         pm_runtime_enable(&pdev->dev);
2658         pm_runtime_resume(&pdev->dev);
2659
2660         if (!pd) {
2661                 dev_err(&pdev->dev, "no platform data\n");
2662                 ret = -EINVAL;
2663                 goto out_release;
2664         }
2665
2666         /* get PHY ID */
2667         mdp->phy_id = pd->phy;
2668         mdp->phy_interface = pd->phy_interface;
2669         /* EDMAC endian */
2670         mdp->edmac_endian = pd->edmac_endian;
2671         mdp->no_ether_link = pd->no_ether_link;
2672         mdp->ether_link_active_low = pd->ether_link_active_low;
2673
2674         /* set cpu data */
2675         mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2676         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2677         sh_eth_set_default_cpu_data(mdp->cd);
2678
2679         /* set function */
2680         if (mdp->cd->tsu)
2681                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2682         else
2683                 ndev->netdev_ops = &sh_eth_netdev_ops;
2684         SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2685         ndev->watchdog_timeo = TX_TIMEOUT;
2686
2687         /* debug message level */
2688         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2689
2690         /* read and set MAC address */
2691         read_mac_address(ndev, pd->mac_addr);
2692         if (!is_valid_ether_addr(ndev->dev_addr)) {
2693                 dev_warn(&pdev->dev,
2694                          "no valid MAC address supplied, using a random one.\n");
2695                 eth_hw_addr_random(ndev);
2696         }
2697
2698         /* ioremap the TSU registers */
2699         if (mdp->cd->tsu) {
2700                 struct resource *rtsu;
2701                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2702                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2703                 if (IS_ERR(mdp->tsu_addr)) {
2704                         ret = PTR_ERR(mdp->tsu_addr);
2705                         goto out_release;
2706                 }
2707                 mdp->port = devno % 2;
2708                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2709         }
2710
2711         /* initialize first or needed device */
2712         if (!devno || pd->needs_init) {
2713                 if (mdp->cd->chip_reset)
2714                         mdp->cd->chip_reset(ndev);
2715
2716                 if (mdp->cd->tsu) {
2717                         /* TSU init (Init only)*/
2718                         sh_eth_tsu_init(mdp);
2719                 }
2720         }
2721
2722         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2723
2724         /* network device register */
2725         ret = register_netdev(ndev);
2726         if (ret)
2727                 goto out_napi_del;
2728
2729         /* mdio bus init */
2730         ret = sh_mdio_init(ndev, pdev->id, pd);
2731         if (ret)
2732                 goto out_unregister;
2733
2734         /* print device information */
2735         pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2736                 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2737
2738         platform_set_drvdata(pdev, ndev);
2739
2740         return ret;
2741
2742 out_unregister:
2743         unregister_netdev(ndev);
2744
2745 out_napi_del:
2746         netif_napi_del(&mdp->napi);
2747
2748 out_release:
2749         /* net_dev free */
2750         if (ndev)
2751                 free_netdev(ndev);
2752
2753 out:
2754         return ret;
2755 }
2756
2757 static int sh_eth_drv_remove(struct platform_device *pdev)
2758 {
2759         struct net_device *ndev = platform_get_drvdata(pdev);
2760         struct sh_eth_private *mdp = netdev_priv(ndev);
2761
2762         sh_mdio_release(ndev);
2763         unregister_netdev(ndev);
2764         netif_napi_del(&mdp->napi);
2765         pm_runtime_disable(&pdev->dev);
2766         free_netdev(ndev);
2767
2768         return 0;
2769 }
2770
2771 #ifdef CONFIG_PM
2772 static int sh_eth_runtime_nop(struct device *dev)
2773 {
2774         /* Runtime PM callback shared between ->runtime_suspend()
2775          * and ->runtime_resume(). Simply returns success.
2776          *
2777          * This driver re-initializes all registers after
2778          * pm_runtime_get_sync() anyway so there is no need
2779          * to save and restore registers here.
2780          */
2781         return 0;
2782 }
2783
2784 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2785         .runtime_suspend = sh_eth_runtime_nop,
2786         .runtime_resume = sh_eth_runtime_nop,
2787 };
2788 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2789 #else
2790 #define SH_ETH_PM_OPS NULL
2791 #endif
2792
2793 static struct platform_device_id sh_eth_id_table[] = {
2794         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2795         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2796         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2797         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2798         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2799         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2800         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2801         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2802         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
2803         { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
2804         { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
2805         { }
2806 };
2807 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2808
2809 static struct platform_driver sh_eth_driver = {
2810         .probe = sh_eth_drv_probe,
2811         .remove = sh_eth_drv_remove,
2812         .id_table = sh_eth_id_table,
2813         .driver = {
2814                    .name = CARDNAME,
2815                    .pm = SH_ETH_PM_OPS,
2816         },
2817 };
2818
2819 module_platform_driver(sh_eth_driver);
2820
2821 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2822 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2823 MODULE_LICENSE("GPL v2");