Pileus Git - ~andy/linux/blob - drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49
  50 #ifdef RTL8169_DEBUG
  51 #define assert(expr) \
  52         if (!(expr)) {                                  \
  53                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  54                 #expr,__FILE__,__func__,__LINE__);              \
  55         }
  56 #define dprintk(fmt, args...) \
  57         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  58 #else
  59 #define assert(expr) do {} while (0)
  60 #define dprintk(fmt, args...)   do {} while (0)
  61 #endif /* RTL8169_DEBUG */
  62
  63 #define R8169_MSG_DEFAULT \
  64         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  65
  66 #define TX_SLOTS_AVAIL(tp) \
  67         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  68
  69 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  70 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  71         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  72
  73 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  74    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  75 static const int multicast_filter_limit = 32;
  76
  77 #define MAX_READ_REQUEST_SHIFT  12
  78 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  79 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  80 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  81
  82 #define R8169_REGS_SIZE         256
  83 #define R8169_NAPI_WEIGHT       64
  84 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  85 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  86 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  87 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  88 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  89
  90 #define RTL8169_TX_TIMEOUT      (6*HZ)
  91 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  92
  93 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  94 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  95 #define RTL_EEPROM_SIG_ADDR     0x0000
  96
  97 /* write/read MMIO register */
  98 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  99 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 100 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 101 #define RTL_R8(reg)             readb (ioaddr + (reg))
 102 #define RTL_R16(reg)            readw (ioaddr + (reg))
 103 #define RTL_R32(reg)            readl (ioaddr + (reg))
 104
 105 enum mac_version {
 106         RTL_GIGA_MAC_VER_01 = 0,
 107         RTL_GIGA_MAC_VER_02,
 108         RTL_GIGA_MAC_VER_03,
 109         RTL_GIGA_MAC_VER_04,
 110         RTL_GIGA_MAC_VER_05,
 111         RTL_GIGA_MAC_VER_06,
 112         RTL_GIGA_MAC_VER_07,
 113         RTL_GIGA_MAC_VER_08,
 114         RTL_GIGA_MAC_VER_09,
 115         RTL_GIGA_MAC_VER_10,
 116         RTL_GIGA_MAC_VER_11,
 117         RTL_GIGA_MAC_VER_12,
 118         RTL_GIGA_MAC_VER_13,
 119         RTL_GIGA_MAC_VER_14,
 120         RTL_GIGA_MAC_VER_15,
 121         RTL_GIGA_MAC_VER_16,
 122         RTL_GIGA_MAC_VER_17,
 123         RTL_GIGA_MAC_VER_18,
 124         RTL_GIGA_MAC_VER_19,
 125         RTL_GIGA_MAC_VER_20,
 126         RTL_GIGA_MAC_VER_21,
 127         RTL_GIGA_MAC_VER_22,
 128         RTL_GIGA_MAC_VER_23,
 129         RTL_GIGA_MAC_VER_24,
 130         RTL_GIGA_MAC_VER_25,
 131         RTL_GIGA_MAC_VER_26,
 132         RTL_GIGA_MAC_VER_27,
 133         RTL_GIGA_MAC_VER_28,
 134         RTL_GIGA_MAC_VER_29,
 135         RTL_GIGA_MAC_VER_30,
 136         RTL_GIGA_MAC_VER_31,
 137         RTL_GIGA_MAC_VER_32,
 138         RTL_GIGA_MAC_VER_33,
 139         RTL_GIGA_MAC_VER_34,
 140         RTL_GIGA_MAC_VER_35,
 141         RTL_GIGA_MAC_VER_36,
 142         RTL_GIGA_MAC_VER_37,
 143         RTL_GIGA_MAC_VER_38,
 144         RTL_GIGA_MAC_NONE   = 0xff,
 145 };
 146
 147 enum rtl_tx_desc_version {
 148         RTL_TD_0        = 0,
 149         RTL_TD_1        = 1,
 150 };
 151
 152 #define JUMBO_1K        ETH_DATA_LEN
 153 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 154 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 155 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 156 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 157
 158 #define _R(NAME,TD,FW,SZ,B) {   \
 159         .name = NAME,           \
 160         .txd_version = TD,      \
 161         .fw_name = FW,          \
 162         .jumbo_max = SZ,        \
 163         .jumbo_tx_csum = B      \
 164 }
 165
 166 static const struct {
 167         const char *name;
 168         enum rtl_tx_desc_version txd_version;
 169         const char *fw_name;
 170         u16 jumbo_max;
 171         bool jumbo_tx_csum;
 172 } rtl_chip_infos[] = {
 173         /* PCI devices. */
 174         [RTL_GIGA_MAC_VER_01] =
 175                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 176         [RTL_GIGA_MAC_VER_02] =
 177                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 178         [RTL_GIGA_MAC_VER_03] =
 179                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 180         [RTL_GIGA_MAC_VER_04] =
 181                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 182         [RTL_GIGA_MAC_VER_05] =
 183                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 184         [RTL_GIGA_MAC_VER_06] =
 185                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 186         /* PCI-E devices. */
 187         [RTL_GIGA_MAC_VER_07] =
 188                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 189         [RTL_GIGA_MAC_VER_08] =
 190                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 191         [RTL_GIGA_MAC_VER_09] =
 192                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 193         [RTL_GIGA_MAC_VER_10] =
 194                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 195         [RTL_GIGA_MAC_VER_11] =
 196                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 197         [RTL_GIGA_MAC_VER_12] =
 198                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 199         [RTL_GIGA_MAC_VER_13] =
 200                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 201         [RTL_GIGA_MAC_VER_14] =
 202                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 203         [RTL_GIGA_MAC_VER_15] =
 204                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 205         [RTL_GIGA_MAC_VER_16] =
 206                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 207         [RTL_GIGA_MAC_VER_17] =
 208                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 209         [RTL_GIGA_MAC_VER_18] =
 210                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 211         [RTL_GIGA_MAC_VER_19] =
 212                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 213         [RTL_GIGA_MAC_VER_20] =
 214                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 215         [RTL_GIGA_MAC_VER_21] =
 216                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 217         [RTL_GIGA_MAC_VER_22] =
 218                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 219         [RTL_GIGA_MAC_VER_23] =
 220                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 221         [RTL_GIGA_MAC_VER_24] =
 222                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 223         [RTL_GIGA_MAC_VER_25] =
 224                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 225                                                         JUMBO_9K, false),
 226         [RTL_GIGA_MAC_VER_26] =
 227                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 228                                                         JUMBO_9K, false),
 229         [RTL_GIGA_MAC_VER_27] =
 230                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 231         [RTL_GIGA_MAC_VER_28] =
 232                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 233         [RTL_GIGA_MAC_VER_29] =
 234                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 235                                                         JUMBO_1K, true),
 236         [RTL_GIGA_MAC_VER_30] =
 237                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 238                                                         JUMBO_1K, true),
 239         [RTL_GIGA_MAC_VER_31] =
 240                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 241         [RTL_GIGA_MAC_VER_32] =
 242                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 243                                                         JUMBO_9K, false),
 244         [RTL_GIGA_MAC_VER_33] =
 245                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 246                                                         JUMBO_9K, false),
 247         [RTL_GIGA_MAC_VER_34] =
 248                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 249                                                         JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_35] =
 251                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 252                                                         JUMBO_9K, false),
 253         [RTL_GIGA_MAC_VER_36] =
 254                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 255                                                         JUMBO_9K, false),
 256         [RTL_GIGA_MAC_VER_37] =
 257                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 258                                                         JUMBO_1K, true),
 259         [RTL_GIGA_MAC_VER_38] =
 260                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 261                                                         JUMBO_9K, false),
 262 };
 263 #undef _R
 264
 265 enum cfg_version {
 266         RTL_CFG_0 = 0x00,
 267         RTL_CFG_1,
 268         RTL_CFG_2
 269 };
 270
 271 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 272         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 273         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 274         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 275         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 276         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 277         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 278         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 279         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 280         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 281         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 282                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 283         { 0x0001,                               0x8168,
 284                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 285         {0,},
 286 };
 287
 288 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 289
 290 static int rx_buf_sz = 16383;
 291 static int use_dac;
 292 static struct {
 293         u32 msg_enable;
 294 } debug = { -1 };
 295
 296 enum rtl_registers {
 297         MAC0            = 0,    /* Ethernet hardware address. */
 298         MAC4            = 4,
 299         MAR0            = 8,    /* Multicast filter. */
 300         CounterAddrLow          = 0x10,
 301         CounterAddrHigh         = 0x14,
 302         TxDescStartAddrLow      = 0x20,
 303         TxDescStartAddrHigh     = 0x24,
 304         TxHDescStartAddrLow     = 0x28,
 305         TxHDescStartAddrHigh    = 0x2c,
 306         FLASH           = 0x30,
 307         ERSR            = 0x36,
 308         ChipCmd         = 0x37,
 309         TxPoll          = 0x38,
 310         IntrMask        = 0x3c,
 311         IntrStatus      = 0x3e,
 312
 313         TxConfig        = 0x40,
 314 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 315 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 316
 317         RxConfig        = 0x44,
 318 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 319 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 320 #define RXCFG_FIFO_SHIFT                13
 321                                         /* No threshold before first PCI xfer */
 322 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 323 #define RXCFG_DMA_SHIFT                 8
 324                                         /* Unlimited maximum PCI burst. */
 325 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 326
 327         RxMissed        = 0x4c,
 328         Cfg9346         = 0x50,
 329         Config0         = 0x51,
 330         Config1         = 0x52,
 331         Config2         = 0x53,
 332 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 333
 334         Config3         = 0x54,
 335         Config4         = 0x55,
 336         Config5         = 0x56,
 337         MultiIntr       = 0x5c,
 338         PHYAR           = 0x60,
 339         PHYstatus       = 0x6c,
 340         RxMaxSize       = 0xda,
 341         CPlusCmd        = 0xe0,
 342         IntrMitigate    = 0xe2,
 343         RxDescAddrLow   = 0xe4,
 344         RxDescAddrHigh  = 0xe8,
 345         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 346
 347 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 348
 349         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 350
 351 #define TxPacketMax     (8064 >> 7)
 352 #define EarlySize       0x27
 353
 354         FuncEvent       = 0xf0,
 355         FuncEventMask   = 0xf4,
 356         FuncPresetState = 0xf8,
 357         FuncForceEvent  = 0xfc,
 358 };
 359
 360 enum rtl8110_registers {
 361         TBICSR                  = 0x64,
 362         TBI_ANAR                = 0x68,
 363         TBI_LPAR                = 0x6a,
 364 };
 365
 366 enum rtl8168_8101_registers {
 367         CSIDR                   = 0x64,
 368         CSIAR                   = 0x68,
 369 #define CSIAR_FLAG                      0x80000000
 370 #define CSIAR_WRITE_CMD                 0x80000000
 371 #define CSIAR_BYTE_ENABLE               0x0f
 372 #define CSIAR_BYTE_ENABLE_SHIFT         12
 373 #define CSIAR_ADDR_MASK                 0x0fff
 374 #define CSIAR_FUNC_CARD                 0x00000000
 375 #define CSIAR_FUNC_SDIO                 0x00010000
 376 #define CSIAR_FUNC_NIC                  0x00020000
 377         PMCH                    = 0x6f,
 378         EPHYAR                  = 0x80,
 379 #define EPHYAR_FLAG                     0x80000000
 380 #define EPHYAR_WRITE_CMD                0x80000000
 381 #define EPHYAR_REG_MASK                 0x1f
 382 #define EPHYAR_REG_SHIFT                16
 383 #define EPHYAR_DATA_MASK                0xffff
 384         DLLPR                   = 0xd0,
 385 #define PFM_EN                          (1 << 6)
 386         DBG_REG                 = 0xd1,
 387 #define FIX_NAK_1                       (1 << 4)
 388 #define FIX_NAK_2                       (1 << 3)
 389         TWSI                    = 0xd2,
 390         MCU                     = 0xd3,
 391 #define NOW_IS_OOB                      (1 << 7)
 392 #define EN_NDP                          (1 << 3)
 393 #define EN_OOB_RESET                    (1 << 2)
 394         EFUSEAR                 = 0xdc,
 395 #define EFUSEAR_FLAG                    0x80000000
 396 #define EFUSEAR_WRITE_CMD               0x80000000
 397 #define EFUSEAR_READ_CMD                0x00000000
 398 #define EFUSEAR_REG_MASK                0x03ff
 399 #define EFUSEAR_REG_SHIFT               8
 400 #define EFUSEAR_DATA_MASK               0xff
 401 };
 402
 403 enum rtl8168_registers {
 404         LED_FREQ                = 0x1a,
 405         EEE_LED                 = 0x1b,
 406         ERIDR                   = 0x70,
 407         ERIAR                   = 0x74,
 408 #define ERIAR_FLAG                      0x80000000
 409 #define ERIAR_WRITE_CMD                 0x80000000
 410 #define ERIAR_READ_CMD                  0x00000000
 411 #define ERIAR_ADDR_BYTE_ALIGN           4
 412 #define ERIAR_TYPE_SHIFT                16
 413 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 414 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 415 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 416 #define ERIAR_MASK_SHIFT                12
 417 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 418 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 419 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 420         EPHY_RXER_NUM           = 0x7c,
 421         OCPDR                   = 0xb0, /* OCP GPHY access */
 422 #define OCPDR_WRITE_CMD                 0x80000000
 423 #define OCPDR_READ_CMD                  0x00000000
 424 #define OCPDR_REG_MASK                  0x7f
 425 #define OCPDR_GPHY_REG_SHIFT            16
 426 #define OCPDR_DATA_MASK                 0xffff
 427         OCPAR                   = 0xb4,
 428 #define OCPAR_FLAG                      0x80000000
 429 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 430 #define OCPAR_GPHY_READ_CMD             0x0000f060
 431         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 432         MISC                    = 0xf0, /* 8168e only. */
 433 #define TXPLA_RST                       (1 << 29)
 434 #define PWM_EN                          (1 << 22)
 435 };
 436
 437 enum rtl_register_content {
 438         /* InterruptStatusBits */
 439         SYSErr          = 0x8000,
 440         PCSTimeout      = 0x4000,
 441         SWInt           = 0x0100,
 442         TxDescUnavail   = 0x0080,
 443         RxFIFOOver      = 0x0040,
 444         LinkChg         = 0x0020,
 445         RxOverflow      = 0x0010,
 446         TxErr           = 0x0008,
 447         TxOK            = 0x0004,
 448         RxErr           = 0x0002,
 449         RxOK            = 0x0001,
 450
 451         /* RxStatusDesc */
 452         RxBOVF  = (1 << 24),
 453         RxFOVF  = (1 << 23),
 454         RxRWT   = (1 << 22),
 455         RxRES   = (1 << 21),
 456         RxRUNT  = (1 << 20),
 457         RxCRC   = (1 << 19),
 458
 459         /* ChipCmdBits */
 460         StopReq         = 0x80,
 461         CmdReset        = 0x10,
 462         CmdRxEnb        = 0x08,
 463         CmdTxEnb        = 0x04,
 464         RxBufEmpty      = 0x01,
 465
 466         /* TXPoll register p.5 */
 467         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 468         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 469         FSWInt          = 0x01,         /* Forced software interrupt */
 470
 471         /* Cfg9346Bits */
 472         Cfg9346_Lock    = 0x00,
 473         Cfg9346_Unlock  = 0xc0,
 474
 475         /* rx_mode_bits */
 476         AcceptErr       = 0x20,
 477         AcceptRunt      = 0x10,
 478         AcceptBroadcast = 0x08,
 479         AcceptMulticast = 0x04,
 480         AcceptMyPhys    = 0x02,
 481         AcceptAllPhys   = 0x01,
 482 #define RX_CONFIG_ACCEPT_MASK           0x3f
 483
 484         /* TxConfigBits */
 485         TxInterFrameGapShift = 24,
 486         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 487
 488         /* Config1 register p.24 */
 489         LEDS1           = (1 << 7),
 490         LEDS0           = (1 << 6),
 491         Speed_down      = (1 << 4),
 492         MEMMAP          = (1 << 3),
 493         IOMAP           = (1 << 2),
 494         VPD             = (1 << 1),
 495         PMEnable        = (1 << 0),     /* Power Management Enable */
 496
 497         /* Config2 register p. 25 */
 498         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 499         PCI_Clock_66MHz = 0x01,
 500         PCI_Clock_33MHz = 0x00,
 501
 502         /* Config3 register p.25 */
 503         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 504         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 505         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 506         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 507
 508         /* Config4 register */
 509         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 510
 511         /* Config5 register p.27 */
 512         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 513         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 514         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 515         Spi_en          = (1 << 3),
 516         LanWake         = (1 << 1),     /* LanWake enable/disable */
 517         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 518
 519         /* TBICSR p.28 */
 520         TBIReset        = 0x80000000,
 521         TBILoopback     = 0x40000000,
 522         TBINwEnable     = 0x20000000,
 523         TBINwRestart    = 0x10000000,
 524         TBILinkOk       = 0x02000000,
 525         TBINwComplete   = 0x01000000,
 526
 527         /* CPlusCmd p.31 */
 528         EnableBist      = (1 << 15),    // 8168 8101
 529         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 530         Normal_mode     = (1 << 13),    // unused
 531         Force_half_dup  = (1 << 12),    // 8168 8101
 532         Force_rxflow_en = (1 << 11),    // 8168 8101
 533         Force_txflow_en = (1 << 10),    // 8168 8101
 534         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 535         ASF             = (1 << 8),     // 8168 8101
 536         PktCntrDisable  = (1 << 7),     // 8168 8101
 537         Mac_dbgo_sel    = 0x001c,       // 8168
 538         RxVlan          = (1 << 6),
 539         RxChkSum        = (1 << 5),
 540         PCIDAC          = (1 << 4),
 541         PCIMulRW        = (1 << 3),
 542         INTT_0          = 0x0000,       // 8168
 543         INTT_1          = 0x0001,       // 8168
 544         INTT_2          = 0x0002,       // 8168
 545         INTT_3          = 0x0003,       // 8168
 546
 547         /* rtl8169_PHYstatus */
 548         TBI_Enable      = 0x80,
 549         TxFlowCtrl      = 0x40,
 550         RxFlowCtrl      = 0x20,
 551         _1000bpsF       = 0x10,
 552         _100bps         = 0x08,
 553         _10bps          = 0x04,
 554         LinkStatus      = 0x02,
 555         FullDup         = 0x01,
 556
 557         /* _TBICSRBit */
 558         TBILinkOK       = 0x02000000,
 559
 560         /* DumpCounterCommand */
 561         CounterDump     = 0x8,
 562 };
 563
 564 enum rtl_desc_bit {
 565         /* First doubleword. */
 566         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 567         RingEnd         = (1 << 30), /* End of descriptor ring */
 568         FirstFrag       = (1 << 29), /* First segment of a packet */
 569         LastFrag        = (1 << 28), /* Final segment of a packet */
 570 };
 571
 572 /* Generic case. */
 573 enum rtl_tx_desc_bit {
 574         /* First doubleword. */
 575         TD_LSO          = (1 << 27),            /* Large Send Offload */
 576 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 577
 578         /* Second doubleword. */
 579         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 580 };
 581
 582 /* 8169, 8168b and 810x except 8102e. */
 583 enum rtl_tx_desc_bit_0 {
 584         /* First doubleword. */
 585 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 586         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 587         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 588         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 589 };
 590
 591 /* 8102e, 8168c and beyond. */
 592 enum rtl_tx_desc_bit_1 {
 593         /* Second doubleword. */
 594 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 595         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 596         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 597         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 598 };
 599
 600 static const struct rtl_tx_desc_info {
 601         struct {
 602                 u32 udp;
 603                 u32 tcp;
 604         } checksum;
 605         u16 mss_shift;
 606         u16 opts_offset;
 607 } tx_desc_info [] = {
 608         [RTL_TD_0] = {
 609                 .checksum = {
 610                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 611                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 612                 },
 613                 .mss_shift      = TD0_MSS_SHIFT,
 614                 .opts_offset    = 0
 615         },
 616         [RTL_TD_1] = {
 617                 .checksum = {
 618                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 619                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 620                 },
 621                 .mss_shift      = TD1_MSS_SHIFT,
 622                 .opts_offset    = 1
 623         }
 624 };
 625
 626 enum rtl_rx_desc_bit {
 627         /* Rx private */
 628         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 629         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 630
 631 #define RxProtoUDP      (PID1)
 632 #define RxProtoTCP      (PID0)
 633 #define RxProtoIP       (PID1 | PID0)
 634 #define RxProtoMask     RxProtoIP
 635
 636         IPFail          = (1 << 16), /* IP checksum failed */
 637         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 638         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 639         RxVlanTag       = (1 << 16), /* VLAN tag available */
 640 };
 641
 642 #define RsvdMask        0x3fffc000
 643
 644 struct TxDesc {
 645         __le32 opts1;
 646         __le32 opts2;
 647         __le64 addr;
 648 };
 649
 650 struct RxDesc {
 651         __le32 opts1;
 652         __le32 opts2;
 653         __le64 addr;
 654 };
 655
 656 struct ring_info {
 657         struct sk_buff  *skb;
 658         u32             len;
 659         u8              __pad[sizeof(void *) - sizeof(u32)];
 660 };
 661
 662 enum features {
 663         RTL_FEATURE_WOL         = (1 << 0),
 664         RTL_FEATURE_MSI         = (1 << 1),
 665         RTL_FEATURE_GMII        = (1 << 2),
 666 };
 667
 668 struct rtl8169_counters {
 669         __le64  tx_packets;
 670         __le64  rx_packets;
 671         __le64  tx_errors;
 672         __le32  rx_errors;
 673         __le16  rx_missed;
 674         __le16  align_errors;
 675         __le32  tx_one_collision;
 676         __le32  tx_multi_collision;
 677         __le64  rx_unicast;
 678         __le64  rx_broadcast;
 679         __le32  rx_multicast;
 680         __le16  tx_aborted;
 681         __le16  tx_underun;
 682 };
 683
 684 enum rtl_flag {
 685         RTL_FLAG_TASK_ENABLED,
 686         RTL_FLAG_TASK_SLOW_PENDING,
 687         RTL_FLAG_TASK_RESET_PENDING,
 688         RTL_FLAG_TASK_PHY_PENDING,
 689         RTL_FLAG_MAX
 690 };
 691
 692 struct rtl8169_stats {
 693         u64                     packets;
 694         u64                     bytes;
 695         struct u64_stats_sync   syncp;
 696 };
 697
 698 struct rtl8169_private {
 699         void __iomem *mmio_addr;        /* memory map physical address */
 700         struct pci_dev *pci_dev;
 701         struct net_device *dev;
 702         struct napi_struct napi;
 703         u32 msg_enable;
 704         u16 txd_version;
 705         u16 mac_version;
 706         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 707         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 708         u32 dirty_rx;
 709         u32 dirty_tx;
 710         struct rtl8169_stats rx_stats;
 711         struct rtl8169_stats tx_stats;
 712         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 713         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 714         dma_addr_t TxPhyAddr;
 715         dma_addr_t RxPhyAddr;
 716         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 717         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 718         struct timer_list timer;
 719         u16 cp_cmd;
 720
 721         u16 event_slow;
 722
 723         struct mdio_ops {
 724                 void (*write)(void __iomem *, int, int);
 725                 int (*read)(void __iomem *, int);
 726         } mdio_ops;
 727
 728         struct pll_power_ops {
 729                 void (*down)(struct rtl8169_private *);
 730                 void (*up)(struct rtl8169_private *);
 731         } pll_power_ops;
 732
 733         struct jumbo_ops {
 734                 void (*enable)(struct rtl8169_private *);
 735                 void (*disable)(struct rtl8169_private *);
 736         } jumbo_ops;
 737
 738         struct csi_ops {
 739                 void (*write)(void __iomem *, int, int);
 740                 u32 (*read)(void __iomem *, int);
 741         } csi_ops;
 742
 743         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 744         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 745         void (*phy_reset_enable)(struct rtl8169_private *tp);
 746         void (*hw_start)(struct net_device *);
 747         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 748         unsigned int (*link_ok)(void __iomem *);
 749         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 750
 751         struct {
 752                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 753                 struct mutex mutex;
 754                 struct work_struct work;
 755         } wk;
 756
 757         unsigned features;
 758
 759         struct mii_if_info mii;
 760         struct rtl8169_counters counters;
 761         u32 saved_wolopts;
 762         u32 opts1_mask;
 763
 764         struct rtl_fw {
 765                 const struct firmware *fw;
 766
 767 #define RTL_VER_SIZE            32
 768
 769                 char version[RTL_VER_SIZE];
 770
 771                 struct rtl_fw_phy_action {
 772                         __le32 *code;
 773                         size_t size;
 774                 } phy_action;
 775         } *rtl_fw;
 776 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 777 };
 778
 779 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 780 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 781 module_param(use_dac, int, 0);
 782 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 783 module_param_named(debug, debug.msg_enable, int, 0);
 784 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 785 MODULE_LICENSE("GPL");
 786 MODULE_VERSION(RTL8169_VERSION);
 787 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 788 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 789 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 790 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 791 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 792 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 793 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 794 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 795 MODULE_FIRMWARE(FIRMWARE_8402_1);
 796 MODULE_FIRMWARE(FIRMWARE_8411_1);
 797
 798 static void rtl_lock_work(struct rtl8169_private *tp)
 799 {
 800         mutex_lock(&tp->wk.mutex);
 801 }
 802
 803 static void rtl_unlock_work(struct rtl8169_private *tp)
 804 {
 805         mutex_unlock(&tp->wk.mutex);
 806 }
 807
 808 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 809 {
 810         int cap = pci_pcie_cap(pdev);
 811
 812         if (cap) {
 813                 u16 ctl;
 814
 815                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 816                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 817                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 818         }
 819 }
 820
 821 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 822 {
 823         void __iomem *ioaddr = tp->mmio_addr;
 824         int i;
 825
 826         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 827         for (i = 0; i < 20; i++) {
 828                 udelay(100);
 829                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 830                         break;
 831         }
 832         return RTL_R32(OCPDR);
 833 }
 834
 835 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 836 {
 837         void __iomem *ioaddr = tp->mmio_addr;
 838         int i;
 839
 840         RTL_W32(OCPDR, data);
 841         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 842         for (i = 0; i < 20; i++) {
 843                 udelay(100);
 844                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 845                         break;
 846         }
 847 }
 848
 849 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 850 {
 851         void __iomem *ioaddr = tp->mmio_addr;
 852         int i;
 853
 854         RTL_W8(ERIDR, cmd);
 855         RTL_W32(ERIAR, 0x800010e8);
 856         msleep(2);
 857         for (i = 0; i < 5; i++) {
 858                 udelay(100);
 859                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 860                         break;
 861         }
 862
 863         ocp_write(tp, 0x1, 0x30, 0x00000001);
 864 }
 865
 866 #define OOB_CMD_RESET           0x00
 867 #define OOB_CMD_DRIVER_START    0x05
 868 #define OOB_CMD_DRIVER_STOP     0x06
 869
 870 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 871 {
 872         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 873 }
 874
 875 static void rtl8168_driver_start(struct rtl8169_private *tp)
 876 {
 877         u16 reg;
 878         int i;
 879
 880         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 881
 882         reg = rtl8168_get_ocp_reg(tp);
 883
 884         for (i = 0; i < 10; i++) {
 885                 msleep(10);
 886                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 887                         break;
 888         }
 889 }
 890
 891 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 892 {
 893         u16 reg;
 894         int i;
 895
 896         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 897
 898         reg = rtl8168_get_ocp_reg(tp);
 899
 900         for (i = 0; i < 10; i++) {
 901                 msleep(10);
 902                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 903                         break;
 904         }
 905 }
 906
 907 static int r8168dp_check_dash(struct rtl8169_private *tp)
 908 {
 909         u16 reg = rtl8168_get_ocp_reg(tp);
 910
 911         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 912 }
 913
 914 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 915 {
 916         int i;
 917
 918         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 919
 920         for (i = 20; i > 0; i--) {
 921                 /*
 922                  * Check if the RTL8169 has completed writing to the specified
 923                  * MII register.
 924                  */
 925                 if (!(RTL_R32(PHYAR) & 0x80000000))
 926                         break;
 927                 udelay(25);
 928         }
 929         /*
 930          * According to hardware specs a 20us delay is required after write
 931          * complete indication, but before sending next command.
 932          */
 933         udelay(20);
 934 }
 935
 936 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 937 {
 938         int i, value = -1;
 939
 940         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 941
 942         for (i = 20; i > 0; i--) {
 943                 /*
 944                  * Check if the RTL8169 has completed retrieving data from
 945                  * the specified MII register.
 946                  */
 947                 if (RTL_R32(PHYAR) & 0x80000000) {
 948                         value = RTL_R32(PHYAR) & 0xffff;
 949                         break;
 950                 }
 951                 udelay(25);
 952         }
 953         /*
 954          * According to hardware specs a 20us delay is required after read
 955          * complete indication, but before sending next command.
 956          */
 957         udelay(20);
 958
 959         return value;
 960 }
 961
 962 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 963 {
 964         int i;
 965
 966         RTL_W32(OCPDR, data |
 967                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 968         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 969         RTL_W32(EPHY_RXER_NUM, 0);
 970
 971         for (i = 0; i < 100; i++) {
 972                 mdelay(1);
 973                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 974                         break;
 975         }
 976 }
 977
 978 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 979 {
 980         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 981                 (value & OCPDR_DATA_MASK));
 982 }
 983
 984 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 985 {
 986         int i;
 987
 988         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 989
 990         mdelay(1);
 991         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 992         RTL_W32(EPHY_RXER_NUM, 0);
 993
 994         for (i = 0; i < 100; i++) {
 995                 mdelay(1);
 996                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 997                         break;
 998         }
 999
1000         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
1001 }
1002
1003 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1004
1005 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1006 {
1007         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1008 }
1009
1010 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1011 {
1012         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1013 }
1014
1015 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1016 {
1017         r8168dp_2_mdio_start(ioaddr);
1018
1019         r8169_mdio_write(ioaddr, reg_addr, value);
1020
1021         r8168dp_2_mdio_stop(ioaddr);
1022 }
1023
1024 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1025 {
1026         int value;
1027
1028         r8168dp_2_mdio_start(ioaddr);
1029
1030         value = r8169_mdio_read(ioaddr, reg_addr);
1031
1032         r8168dp_2_mdio_stop(ioaddr);
1033
1034         return value;
1035 }
1036
1037 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1038 {
1039         tp->mdio_ops.write(tp->mmio_addr, location, val);
1040 }
1041
1042 static int rtl_readphy(struct rtl8169_private *tp, int location)
1043 {
1044         return tp->mdio_ops.read(tp->mmio_addr, location);
1045 }
1046
1047 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1048 {
1049         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1050 }
1051
1052 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1053 {
1054         int val;
1055
1056         val = rtl_readphy(tp, reg_addr);
1057         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1058 }
1059
1060 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1061                            int val)
1062 {
1063         struct rtl8169_private *tp = netdev_priv(dev);
1064
1065         rtl_writephy(tp, location, val);
1066 }
1067
1068 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1069 {
1070         struct rtl8169_private *tp = netdev_priv(dev);
1071
1072         return rtl_readphy(tp, location);
1073 }
1074
1075 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1076 {
1077         unsigned int i;
1078
1079         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1080                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1081
1082         for (i = 0; i < 100; i++) {
1083                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1084                         break;
1085                 udelay(10);
1086         }
1087 }
1088
1089 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1090 {
1091         u16 value = 0xffff;
1092         unsigned int i;
1093
1094         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1095
1096         for (i = 0; i < 100; i++) {
1097                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1098                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1099                         break;
1100                 }
1101                 udelay(10);
1102         }
1103
1104         return value;
1105 }
1106
1107 static
1108 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1109 {
1110         unsigned int i;
1111
1112         BUG_ON((addr & 3) || (mask == 0));
1113         RTL_W32(ERIDR, val);
1114         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1115
1116         for (i = 0; i < 100; i++) {
1117                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1118                         break;
1119                 udelay(100);
1120         }
1121 }
1122
1123 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1124 {
1125         u32 value = ~0x00;
1126         unsigned int i;
1127
1128         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1129
1130         for (i = 0; i < 100; i++) {
1131                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1132                         value = RTL_R32(ERIDR);
1133                         break;
1134                 }
1135                 udelay(100);
1136         }
1137
1138         return value;
1139 }
1140
1141 static void
1142 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1143 {
1144         u32 val;
1145
1146         val = rtl_eri_read(ioaddr, addr, type);
1147         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1148 }
1149
1150 struct exgmac_reg {
1151         u16 addr;
1152         u16 mask;
1153         u32 val;
1154 };
1155
1156 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1157                                    const struct exgmac_reg *r, int len)
1158 {
1159         while (len-- > 0) {
1160                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1161                 r++;
1162         }
1163 }
1164
1165 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1166 {
1167         u8 value = 0xff;
1168         unsigned int i;
1169
1170         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1171
1172         for (i = 0; i < 300; i++) {
1173                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1174                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1175                         break;
1176                 }
1177                 udelay(100);
1178         }
1179
1180         return value;
1181 }
1182
1183 static u16 rtl_get_events(struct rtl8169_private *tp)
1184 {
1185         void __iomem *ioaddr = tp->mmio_addr;
1186
1187         return RTL_R16(IntrStatus);
1188 }
1189
1190 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1191 {
1192         void __iomem *ioaddr = tp->mmio_addr;
1193
1194         RTL_W16(IntrStatus, bits);
1195         mmiowb();
1196 }
1197
1198 static void rtl_irq_disable(struct rtl8169_private *tp)
1199 {
1200         void __iomem *ioaddr = tp->mmio_addr;
1201
1202         RTL_W16(IntrMask, 0);
1203         mmiowb();
1204 }
1205
1206 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1207 {
1208         void __iomem *ioaddr = tp->mmio_addr;
1209
1210         RTL_W16(IntrMask, bits);
1211 }
1212
1213 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1214 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1215 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1216
1217 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1218 {
1219         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1220 }
1221
1222 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1223 {
1224         void __iomem *ioaddr = tp->mmio_addr;
1225
1226         rtl_irq_disable(tp);
1227         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1228         RTL_R8(ChipCmd);
1229 }
1230
1231 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1232 {
1233         void __iomem *ioaddr = tp->mmio_addr;
1234
1235         return RTL_R32(TBICSR) & TBIReset;
1236 }
1237
1238 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1239 {
1240         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1241 }
1242
1243 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1244 {
1245         return RTL_R32(TBICSR) & TBILinkOk;
1246 }
1247
1248 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1249 {
1250         return RTL_R8(PHYstatus) & LinkStatus;
1251 }
1252
1253 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1254 {
1255         void __iomem *ioaddr = tp->mmio_addr;
1256
1257         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1258 }
1259
1260 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1261 {
1262         unsigned int val;
1263
1264         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1265         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1266 }
1267
1268 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1269 {
1270         void __iomem *ioaddr = tp->mmio_addr;
1271         struct net_device *dev = tp->dev;
1272
1273         if (!netif_running(dev))
1274                 return;
1275
1276         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1277             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1278                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1279                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1280                                       0x00000011, ERIAR_EXGMAC);
1281                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1282                                       0x00000005, ERIAR_EXGMAC);
1283                 } else if (RTL_R8(PHYstatus) & _100bps) {
1284                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1285                                       0x0000001f, ERIAR_EXGMAC);
1286                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1287                                       0x00000005, ERIAR_EXGMAC);
1288                 } else {
1289                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1290                                       0x0000001f, ERIAR_EXGMAC);
1291                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1292                                       0x0000003f, ERIAR_EXGMAC);
1293                 }
1294                 /* Reset packet filter */
1295                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1296                              ERIAR_EXGMAC);
1297                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1298                              ERIAR_EXGMAC);
1299         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1300                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1301                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1302                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1303                                       0x00000011, ERIAR_EXGMAC);
1304                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1305                                       0x00000005, ERIAR_EXGMAC);
1306                 } else {
1307                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1308                                       0x0000001f, ERIAR_EXGMAC);
1309                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1310                                       0x0000003f, ERIAR_EXGMAC);
1311                 }
1312         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1313                 if (RTL_R8(PHYstatus) & _10bps) {
1314                         rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011,
1315                                       0x4d02, ERIAR_EXGMAC);
1316                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_0011,
1317                                       0x0060, ERIAR_EXGMAC);
1318                 } else {
1319                         rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011,
1320                                       0x0000, ERIAR_EXGMAC);
1321                 }
1322         }
1323 }
1324
1325 static void __rtl8169_check_link_status(struct net_device *dev,
1326                                         struct rtl8169_private *tp,
1327                                         void __iomem *ioaddr, bool pm)
1328 {
1329         if (tp->link_ok(ioaddr)) {
1330                 rtl_link_chg_patch(tp);
1331                 /* This is to cancel a scheduled suspend if there's one. */
1332                 if (pm)
1333                         pm_request_resume(&tp->pci_dev->dev);
1334                 netif_carrier_on(dev);
1335                 if (net_ratelimit())
1336                         netif_info(tp, ifup, dev, "link up\n");
1337         } else {
1338                 netif_carrier_off(dev);
1339                 netif_info(tp, ifdown, dev, "link down\n");
1340                 if (pm)
1341                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1342         }
1343 }
1344
1345 static void rtl8169_check_link_status(struct net_device *dev,
1346                                       struct rtl8169_private *tp,
1347                                       void __iomem *ioaddr)
1348 {
1349         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1350 }
1351
1352 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1353
1354 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1355 {
1356         void __iomem *ioaddr = tp->mmio_addr;
1357         u8 options;
1358         u32 wolopts = 0;
1359
1360         options = RTL_R8(Config1);
1361         if (!(options & PMEnable))
1362                 return 0;
1363
1364         options = RTL_R8(Config3);
1365         if (options & LinkUp)
1366                 wolopts |= WAKE_PHY;
1367         if (options & MagicPacket)
1368                 wolopts |= WAKE_MAGIC;
1369
1370         options = RTL_R8(Config5);
1371         if (options & UWF)
1372                 wolopts |= WAKE_UCAST;
1373         if (options & BWF)
1374                 wolopts |= WAKE_BCAST;
1375         if (options & MWF)
1376                 wolopts |= WAKE_MCAST;
1377
1378         return wolopts;
1379 }
1380
1381 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1382 {
1383         struct rtl8169_private *tp = netdev_priv(dev);
1384
1385         rtl_lock_work(tp);
1386
1387         wol->supported = WAKE_ANY;
1388         wol->wolopts = __rtl8169_get_wol(tp);
1389
1390         rtl_unlock_work(tp);
1391 }
1392
1393 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1394 {
1395         void __iomem *ioaddr = tp->mmio_addr;
1396         unsigned int i;
1397         static const struct {
1398                 u32 opt;
1399                 u16 reg;
1400                 u8  mask;
1401         } cfg[] = {
1402                 { WAKE_PHY,   Config3, LinkUp },
1403                 { WAKE_MAGIC, Config3, MagicPacket },
1404                 { WAKE_UCAST, Config5, UWF },
1405                 { WAKE_BCAST, Config5, BWF },
1406                 { WAKE_MCAST, Config5, MWF },
1407                 { WAKE_ANY,   Config5, LanWake }
1408         };
1409         u8 options;
1410
1411         RTL_W8(Cfg9346, Cfg9346_Unlock);
1412
1413         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1414                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1415                 if (wolopts & cfg[i].opt)
1416                         options |= cfg[i].mask;
1417                 RTL_W8(cfg[i].reg, options);
1418         }
1419
1420         switch (tp->mac_version) {
1421         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1422                 options = RTL_R8(Config1) & ~PMEnable;
1423                 if (wolopts)
1424                         options |= PMEnable;
1425                 RTL_W8(Config1, options);
1426                 break;
1427         default:
1428                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1429                 if (wolopts)
1430                         options |= PME_SIGNAL;
1431                 RTL_W8(Config2, options);
1432                 break;
1433         }
1434
1435         RTL_W8(Cfg9346, Cfg9346_Lock);
1436 }
1437
1438 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1439 {
1440         struct rtl8169_private *tp = netdev_priv(dev);
1441
1442         rtl_lock_work(tp);
1443
1444         if (wol->wolopts)
1445                 tp->features |= RTL_FEATURE_WOL;
1446         else
1447                 tp->features &= ~RTL_FEATURE_WOL;
1448         __rtl8169_set_wol(tp, wol->wolopts);
1449
1450         rtl_unlock_work(tp);
1451
1452         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1453
1454         return 0;
1455 }
1456
1457 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1458 {
1459         return rtl_chip_infos[tp->mac_version].fw_name;
1460 }
1461
1462 static void rtl8169_get_drvinfo(struct net_device *dev,
1463                                 struct ethtool_drvinfo *info)
1464 {
1465         struct rtl8169_private *tp = netdev_priv(dev);
1466         struct rtl_fw *rtl_fw = tp->rtl_fw;
1467
1468         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1469         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1470         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1471         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1472         if (!IS_ERR_OR_NULL(rtl_fw))
1473                 strlcpy(info->fw_version, rtl_fw->version,
1474                         sizeof(info->fw_version));
1475 }
1476
1477 static int rtl8169_get_regs_len(struct net_device *dev)
1478 {
1479         return R8169_REGS_SIZE;
1480 }
1481
1482 static int rtl8169_set_speed_tbi(struct net_device *dev,
1483                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1484 {
1485         struct rtl8169_private *tp = netdev_priv(dev);
1486         void __iomem *ioaddr = tp->mmio_addr;
1487         int ret = 0;
1488         u32 reg;
1489
1490         reg = RTL_R32(TBICSR);
1491         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1492             (duplex == DUPLEX_FULL)) {
1493                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1494         } else if (autoneg == AUTONEG_ENABLE)
1495                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1496         else {
1497                 netif_warn(tp, link, dev,
1498                            "incorrect speed setting refused in TBI mode\n");
1499                 ret = -EOPNOTSUPP;
1500         }
1501
1502         return ret;
1503 }
1504
1505 static int rtl8169_set_speed_xmii(struct net_device *dev,
1506                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1507 {
1508         struct rtl8169_private *tp = netdev_priv(dev);
1509         int giga_ctrl, bmcr;
1510         int rc = -EINVAL;
1511
1512         rtl_writephy(tp, 0x1f, 0x0000);
1513
1514         if (autoneg == AUTONEG_ENABLE) {
1515                 int auto_nego;
1516
1517                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1518                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1519                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1520
1521                 if (adv & ADVERTISED_10baseT_Half)
1522                         auto_nego |= ADVERTISE_10HALF;
1523                 if (adv & ADVERTISED_10baseT_Full)
1524                         auto_nego |= ADVERTISE_10FULL;
1525                 if (adv & ADVERTISED_100baseT_Half)
1526                         auto_nego |= ADVERTISE_100HALF;
1527                 if (adv & ADVERTISED_100baseT_Full)
1528                         auto_nego |= ADVERTISE_100FULL;
1529
1530                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1531
1532                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1533                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1534
1535                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1536                 if (tp->mii.supports_gmii) {
1537                         if (adv & ADVERTISED_1000baseT_Half)
1538                                 giga_ctrl |= ADVERTISE_1000HALF;
1539                         if (adv & ADVERTISED_1000baseT_Full)
1540                                 giga_ctrl |= ADVERTISE_1000FULL;
1541                 } else if (adv & (ADVERTISED_1000baseT_Half |
1542                                   ADVERTISED_1000baseT_Full)) {
1543                         netif_info(tp, link, dev,
1544                                    "PHY does not support 1000Mbps\n");
1545                         goto out;
1546                 }
1547
1548                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1549
1550                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1551                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1552         } else {
1553                 giga_ctrl = 0;
1554
1555                 if (speed == SPEED_10)
1556                         bmcr = 0;
1557                 else if (speed == SPEED_100)
1558                         bmcr = BMCR_SPEED100;
1559                 else
1560                         goto out;
1561
1562                 if (duplex == DUPLEX_FULL)
1563                         bmcr |= BMCR_FULLDPLX;
1564         }
1565
1566         rtl_writephy(tp, MII_BMCR, bmcr);
1567
1568         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1569             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1570                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1571                         rtl_writephy(tp, 0x17, 0x2138);
1572                         rtl_writephy(tp, 0x0e, 0x0260);
1573                 } else {
1574                         rtl_writephy(tp, 0x17, 0x2108);
1575                         rtl_writephy(tp, 0x0e, 0x0000);
1576                 }
1577         }
1578
1579         rc = 0;
1580 out:
1581         return rc;
1582 }
1583
1584 static int rtl8169_set_speed(struct net_device *dev,
1585                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1586 {
1587         struct rtl8169_private *tp = netdev_priv(dev);
1588         int ret;
1589
1590         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1591         if (ret < 0)
1592                 goto out;
1593
1594         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1595             (advertising & ADVERTISED_1000baseT_Full)) {
1596                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1597         }
1598 out:
1599         return ret;
1600 }
1601
1602 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1603 {
1604         struct rtl8169_private *tp = netdev_priv(dev);
1605         int ret;
1606
1607         del_timer_sync(&tp->timer);
1608
1609         rtl_lock_work(tp);
1610         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1611                                 cmd->duplex, cmd->advertising);
1612         rtl_unlock_work(tp);
1613
1614         return ret;
1615 }
1616
1617 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1618         netdev_features_t features)
1619 {
1620         struct rtl8169_private *tp = netdev_priv(dev);
1621
1622         if (dev->mtu > TD_MSS_MAX)
1623                 features &= ~NETIF_F_ALL_TSO;
1624
1625         if (dev->mtu > JUMBO_1K &&
1626             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1627                 features &= ~NETIF_F_IP_CSUM;
1628
1629         return features;
1630 }
1631
1632 static void __rtl8169_set_features(struct net_device *dev,
1633                                    netdev_features_t features)
1634 {
1635         struct rtl8169_private *tp = netdev_priv(dev);
1636         netdev_features_t changed = features ^ dev->features;
1637         void __iomem *ioaddr = tp->mmio_addr;
1638
1639         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1640                 return;
1641
1642         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1643                 if (features & NETIF_F_RXCSUM)
1644                         tp->cp_cmd |= RxChkSum;
1645                 else
1646                         tp->cp_cmd &= ~RxChkSum;
1647
1648                 if (dev->features & NETIF_F_HW_VLAN_RX)
1649                         tp->cp_cmd |= RxVlan;
1650                 else
1651                         tp->cp_cmd &= ~RxVlan;
1652
1653                 RTL_W16(CPlusCmd, tp->cp_cmd);
1654                 RTL_R16(CPlusCmd);
1655         }
1656         if (changed & NETIF_F_RXALL) {
1657                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1658                 if (features & NETIF_F_RXALL)
1659                         tmp |= (AcceptErr | AcceptRunt);
1660                 RTL_W32(RxConfig, tmp);
1661         }
1662 }
1663
1664 static int rtl8169_set_features(struct net_device *dev,
1665                                 netdev_features_t features)
1666 {
1667         struct rtl8169_private *tp = netdev_priv(dev);
1668
1669         rtl_lock_work(tp);
1670         __rtl8169_set_features(dev, features);
1671         rtl_unlock_work(tp);
1672
1673         return 0;
1674 }
1675
1676
1677 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1678                                       struct sk_buff *skb)
1679 {
1680         return (vlan_tx_tag_present(skb)) ?
1681                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1682 }
1683
1684 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1685 {
1686         u32 opts2 = le32_to_cpu(desc->opts2);
1687
1688         if (opts2 & RxVlanTag)
1689                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1690
1691         desc->opts2 = 0;
1692 }
1693
1694 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1695 {
1696         struct rtl8169_private *tp = netdev_priv(dev);
1697         void __iomem *ioaddr = tp->mmio_addr;
1698         u32 status;
1699
1700         cmd->supported =
1701                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1702         cmd->port = PORT_FIBRE;
1703         cmd->transceiver = XCVR_INTERNAL;
1704
1705         status = RTL_R32(TBICSR);
1706         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1707         cmd->autoneg = !!(status & TBINwEnable);
1708
1709         ethtool_cmd_speed_set(cmd, SPEED_1000);
1710         cmd->duplex = DUPLEX_FULL; /* Always set */
1711
1712         return 0;
1713 }
1714
1715 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1716 {
1717         struct rtl8169_private *tp = netdev_priv(dev);
1718
1719         return mii_ethtool_gset(&tp->mii, cmd);
1720 }
1721
1722 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1723 {
1724         struct rtl8169_private *tp = netdev_priv(dev);
1725         int rc;
1726
1727         rtl_lock_work(tp);
1728         rc = tp->get_settings(dev, cmd);
1729         rtl_unlock_work(tp);
1730
1731         return rc;
1732 }
1733
1734 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1735                              void *p)
1736 {
1737         struct rtl8169_private *tp = netdev_priv(dev);
1738
1739         if (regs->len > R8169_REGS_SIZE)
1740                 regs->len = R8169_REGS_SIZE;
1741
1742         rtl_lock_work(tp);
1743         memcpy_fromio(p, tp->mmio_addr, regs->len);
1744         rtl_unlock_work(tp);
1745 }
1746
1747 static u32 rtl8169_get_msglevel(struct net_device *dev)
1748 {
1749         struct rtl8169_private *tp = netdev_priv(dev);
1750
1751         return tp->msg_enable;
1752 }
1753
1754 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1755 {
1756         struct rtl8169_private *tp = netdev_priv(dev);
1757
1758         tp->msg_enable = value;
1759 }
1760
1761 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1762         "tx_packets",
1763         "rx_packets",
1764         "tx_errors",
1765         "rx_errors",
1766         "rx_missed",
1767         "align_errors",
1768         "tx_single_collisions",
1769         "tx_multi_collisions",
1770         "unicast",
1771         "broadcast",
1772         "multicast",
1773         "tx_aborted",
1774         "tx_underrun",
1775 };
1776
1777 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1778 {
1779         switch (sset) {
1780         case ETH_SS_STATS:
1781                 return ARRAY_SIZE(rtl8169_gstrings);
1782         default:
1783                 return -EOPNOTSUPP;
1784         }
1785 }
1786
1787 static void rtl8169_update_counters(struct net_device *dev)
1788 {
1789         struct rtl8169_private *tp = netdev_priv(dev);
1790         void __iomem *ioaddr = tp->mmio_addr;
1791         struct device *d = &tp->pci_dev->dev;
1792         struct rtl8169_counters *counters;
1793         dma_addr_t paddr;
1794         u32 cmd;
1795         int wait = 1000;
1796
1797         /*
1798          * Some chips are unable to dump tally counters when the receiver
1799          * is disabled.
1800          */
1801         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1802                 return;
1803
1804         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1805         if (!counters)
1806                 return;
1807
1808         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1809         cmd = (u64)paddr & DMA_BIT_MASK(32);
1810         RTL_W32(CounterAddrLow, cmd);
1811         RTL_W32(CounterAddrLow, cmd | CounterDump);
1812
1813         while (wait--) {
1814                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1815                         memcpy(&tp->counters, counters, sizeof(*counters));
1816                         break;
1817                 }
1818                 udelay(10);
1819         }
1820
1821         RTL_W32(CounterAddrLow, 0);
1822         RTL_W32(CounterAddrHigh, 0);
1823
1824         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1825 }
1826
1827 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1828                                       struct ethtool_stats *stats, u64 *data)
1829 {
1830         struct rtl8169_private *tp = netdev_priv(dev);
1831
1832         ASSERT_RTNL();
1833
1834         rtl8169_update_counters(dev);
1835
1836         data[0] = le64_to_cpu(tp->counters.tx_packets);
1837         data[1] = le64_to_cpu(tp->counters.rx_packets);
1838         data[2] = le64_to_cpu(tp->counters.tx_errors);
1839         data[3] = le32_to_cpu(tp->counters.rx_errors);
1840         data[4] = le16_to_cpu(tp->counters.rx_missed);
1841         data[5] = le16_to_cpu(tp->counters.align_errors);
1842         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1843         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1844         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1845         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1846         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1847         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1848         data[12] = le16_to_cpu(tp->counters.tx_underun);
1849 }
1850
1851 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1852 {
1853         switch(stringset) {
1854         case ETH_SS_STATS:
1855                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1856                 break;
1857         }
1858 }
1859
1860 static const struct ethtool_ops rtl8169_ethtool_ops = {
1861         .get_drvinfo            = rtl8169_get_drvinfo,
1862         .get_regs_len           = rtl8169_get_regs_len,
1863         .get_link               = ethtool_op_get_link,
1864         .get_settings           = rtl8169_get_settings,
1865         .set_settings           = rtl8169_set_settings,
1866         .get_msglevel           = rtl8169_get_msglevel,
1867         .set_msglevel           = rtl8169_set_msglevel,
1868         .get_regs               = rtl8169_get_regs,
1869         .get_wol                = rtl8169_get_wol,
1870         .set_wol                = rtl8169_set_wol,
1871         .get_strings            = rtl8169_get_strings,
1872         .get_sset_count         = rtl8169_get_sset_count,
1873         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1874         .get_ts_info            = ethtool_op_get_ts_info,
1875 };
1876
1877 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1878                                     struct net_device *dev, u8 default_version)
1879 {
1880         void __iomem *ioaddr = tp->mmio_addr;
1881         /*
1882          * The driver currently handles the 8168Bf and the 8168Be identically
1883          * but they can be identified more specifically through the test below
1884          * if needed:
1885          *
1886          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1887          *
1888          * Same thing for the 8101Eb and the 8101Ec:
1889          *
1890          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1891          */
1892         static const struct rtl_mac_info {
1893                 u32 mask;
1894                 u32 val;
1895                 int mac_version;
1896         } mac_info[] = {
1897                 /* 8168F family. */
1898                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
1899                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1900                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1901
1902                 /* 8168E family. */
1903                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1904                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1905                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1906                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1907
1908                 /* 8168D family. */
1909                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1910                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1911                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1912
1913                 /* 8168DP family. */
1914                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1915                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1916                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1917
1918                 /* 8168C family. */
1919                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1920                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1921                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1922                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1923                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1924                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1925                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1926                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1927                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1928
1929                 /* 8168B family. */
1930                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1931                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1932                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1933                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1934
1935                 /* 8101 family. */
1936                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
1937                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1938                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1939                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1940                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1941                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1942                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1943                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1944                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1945                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1946                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1947                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1948                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1949                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1950                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1951                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1952                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1953                 /* FIXME: where did these entries come from ? -- FR */
1954                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1955                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1956
1957                 /* 8110 family. */
1958                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1959                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1960                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1961                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1962                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1963                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1964
1965                 /* Catch-all */
1966                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1967         };
1968         const struct rtl_mac_info *p = mac_info;
1969         u32 reg;
1970
1971         reg = RTL_R32(TxConfig);
1972         while ((reg & p->mask) != p->val)
1973                 p++;
1974         tp->mac_version = p->mac_version;
1975
1976         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1977                 netif_notice(tp, probe, dev,
1978                              "unknown MAC, using family default\n");
1979                 tp->mac_version = default_version;
1980         }
1981 }
1982
1983 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1984 {
1985         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1986 }
1987
1988 struct phy_reg {
1989         u16 reg;
1990         u16 val;
1991 };
1992
1993 static void rtl_writephy_batch(struct rtl8169_private *tp,
1994                                const struct phy_reg *regs, int len)
1995 {
1996         while (len-- > 0) {
1997                 rtl_writephy(tp, regs->reg, regs->val);
1998                 regs++;
1999         }
2000 }
2001
2002 #define PHY_READ                0x00000000
2003 #define PHY_DATA_OR             0x10000000
2004 #define PHY_DATA_AND            0x20000000
2005 #define PHY_BJMPN               0x30000000
2006 #define PHY_READ_EFUSE          0x40000000
2007 #define PHY_READ_MAC_BYTE       0x50000000
2008 #define PHY_WRITE_MAC_BYTE      0x60000000
2009 #define PHY_CLEAR_READCOUNT     0x70000000
2010 #define PHY_WRITE               0x80000000
2011 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2012 #define PHY_COMP_EQ_SKIPN       0xa0000000
2013 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2014 #define PHY_WRITE_PREVIOUS      0xc0000000
2015 #define PHY_SKIPN               0xd0000000
2016 #define PHY_DELAY_MS            0xe0000000
2017 #define PHY_WRITE_ERI_WORD      0xf0000000
2018
2019 struct fw_info {
2020         u32     magic;
2021         char    version[RTL_VER_SIZE];
2022         __le32  fw_start;
2023         __le32  fw_len;
2024         u8      chksum;
2025 } __packed;
2026
2027 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2028
2029 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2030 {
2031         const struct firmware *fw = rtl_fw->fw;
2032         struct fw_info *fw_info = (struct fw_info *)fw->data;
2033         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2034         char *version = rtl_fw->version;
2035         bool rc = false;
2036
2037         if (fw->size < FW_OPCODE_SIZE)
2038                 goto out;
2039
2040         if (!fw_info->magic) {
2041                 size_t i, size, start;
2042                 u8 checksum = 0;
2043
2044                 if (fw->size < sizeof(*fw_info))
2045                         goto out;
2046
2047                 for (i = 0; i < fw->size; i++)
2048                         checksum += fw->data[i];
2049                 if (checksum != 0)
2050                         goto out;
2051
2052                 start = le32_to_cpu(fw_info->fw_start);
2053                 if (start > fw->size)
2054                         goto out;
2055
2056                 size = le32_to_cpu(fw_info->fw_len);
2057                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2058                         goto out;
2059
2060                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2061
2062                 pa->code = (__le32 *)(fw->data + start);
2063                 pa->size = size;
2064         } else {
2065                 if (fw->size % FW_OPCODE_SIZE)
2066                         goto out;
2067
2068                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2069
2070                 pa->code = (__le32 *)fw->data;
2071                 pa->size = fw->size / FW_OPCODE_SIZE;
2072         }
2073         version[RTL_VER_SIZE - 1] = 0;
2074
2075         rc = true;
2076 out:
2077         return rc;
2078 }
2079
2080 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2081                            struct rtl_fw_phy_action *pa)
2082 {
2083         bool rc = false;
2084         size_t index;
2085
2086         for (index = 0; index < pa->size; index++) {
2087                 u32 action = le32_to_cpu(pa->code[index]);
2088                 u32 regno = (action & 0x0fff0000) >> 16;
2089
2090                 switch(action & 0xf0000000) {
2091                 case PHY_READ:
2092                 case PHY_DATA_OR:
2093                 case PHY_DATA_AND:
2094                 case PHY_READ_EFUSE:
2095                 case PHY_CLEAR_READCOUNT:
2096                 case PHY_WRITE:
2097                 case PHY_WRITE_PREVIOUS:
2098                 case PHY_DELAY_MS:
2099                         break;
2100
2101                 case PHY_BJMPN:
2102                         if (regno > index) {
2103                                 netif_err(tp, ifup, tp->dev,
2104                                           "Out of range of firmware\n");
2105                                 goto out;
2106                         }
2107                         break;
2108                 case PHY_READCOUNT_EQ_SKIP:
2109                         if (index + 2 >= pa->size) {
2110                                 netif_err(tp, ifup, tp->dev,
2111                                           "Out of range of firmware\n");
2112                                 goto out;
2113                         }
2114                         break;
2115                 case PHY_COMP_EQ_SKIPN:
2116                 case PHY_COMP_NEQ_SKIPN:
2117                 case PHY_SKIPN:
2118                         if (index + 1 + regno >= pa->size) {
2119                                 netif_err(tp, ifup, tp->dev,
2120                                           "Out of range of firmware\n");
2121                                 goto out;
2122                         }
2123                         break;
2124
2125                 case PHY_READ_MAC_BYTE:
2126                 case PHY_WRITE_MAC_BYTE:
2127                 case PHY_WRITE_ERI_WORD:
2128                 default:
2129                         netif_err(tp, ifup, tp->dev,
2130                                   "Invalid action 0x%08x\n", action);
2131                         goto out;
2132                 }
2133         }
2134         rc = true;
2135 out:
2136         return rc;
2137 }
2138
2139 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2140 {
2141         struct net_device *dev = tp->dev;
2142         int rc = -EINVAL;
2143
2144         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2145                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2146                 goto out;
2147         }
2148
2149         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2150                 rc = 0;
2151 out:
2152         return rc;
2153 }
2154
2155 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2156 {
2157         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2158         u32 predata, count;
2159         size_t index;
2160
2161         predata = count = 0;
2162
2163         for (index = 0; index < pa->size; ) {
2164                 u32 action = le32_to_cpu(pa->code[index]);
2165                 u32 data = action & 0x0000ffff;
2166                 u32 regno = (action & 0x0fff0000) >> 16;
2167
2168                 if (!action)
2169                         break;
2170
2171                 switch(action & 0xf0000000) {
2172                 case PHY_READ:
2173                         predata = rtl_readphy(tp, regno);
2174                         count++;
2175                         index++;
2176                         break;
2177                 case PHY_DATA_OR:
2178                         predata |= data;
2179                         index++;
2180                         break;
2181                 case PHY_DATA_AND:
2182                         predata &= data;
2183                         index++;
2184                         break;
2185                 case PHY_BJMPN:
2186                         index -= regno;
2187                         break;
2188                 case PHY_READ_EFUSE:
2189                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2190                         index++;
2191                         break;
2192                 case PHY_CLEAR_READCOUNT:
2193                         count = 0;
2194                         index++;
2195                         break;
2196                 case PHY_WRITE:
2197                         rtl_writephy(tp, regno, data);
2198                         index++;
2199                         break;
2200                 case PHY_READCOUNT_EQ_SKIP:
2201                         index += (count == data) ? 2 : 1;
2202                         break;
2203                 case PHY_COMP_EQ_SKIPN:
2204                         if (predata == data)
2205                                 index += regno;
2206                         index++;
2207                         break;
2208                 case PHY_COMP_NEQ_SKIPN:
2209                         if (predata != data)
2210                                 index += regno;
2211                         index++;
2212                         break;
2213                 case PHY_WRITE_PREVIOUS:
2214                         rtl_writephy(tp, regno, predata);
2215                         index++;
2216                         break;
2217                 case PHY_SKIPN:
2218                         index += regno + 1;
2219                         break;
2220                 case PHY_DELAY_MS:
2221                         mdelay(data);
2222                         index++;
2223                         break;
2224
2225                 case PHY_READ_MAC_BYTE:
2226                 case PHY_WRITE_MAC_BYTE:
2227                 case PHY_WRITE_ERI_WORD:
2228                 default:
2229                         BUG();
2230                 }
2231         }
2232 }
2233
2234 static void rtl_release_firmware(struct rtl8169_private *tp)
2235 {
2236         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2237                 release_firmware(tp->rtl_fw->fw);
2238                 kfree(tp->rtl_fw);
2239         }
2240         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2241 }
2242
2243 static void rtl_apply_firmware(struct rtl8169_private *tp)
2244 {
2245         struct rtl_fw *rtl_fw = tp->rtl_fw;
2246
2247         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2248         if (!IS_ERR_OR_NULL(rtl_fw))
2249                 rtl_phy_write_fw(tp, rtl_fw);
2250 }
2251
2252 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2253 {
2254         if (rtl_readphy(tp, reg) != val)
2255                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2256         else
2257                 rtl_apply_firmware(tp);
2258 }
2259
2260 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2261 {
2262         static const struct phy_reg phy_reg_init[] = {
2263                 { 0x1f, 0x0001 },
2264                 { 0x06, 0x006e },
2265                 { 0x08, 0x0708 },
2266                 { 0x15, 0x4000 },
2267                 { 0x18, 0x65c7 },
2268
2269                 { 0x1f, 0x0001 },
2270                 { 0x03, 0x00a1 },
2271                 { 0x02, 0x0008 },
2272                 { 0x01, 0x0120 },
2273                 { 0x00, 0x1000 },
2274                 { 0x04, 0x0800 },
2275                 { 0x04, 0x0000 },
2276
2277                 { 0x03, 0xff41 },
2278                 { 0x02, 0xdf60 },
2279                 { 0x01, 0x0140 },
2280                 { 0x00, 0x0077 },
2281                 { 0x04, 0x7800 },
2282                 { 0x04, 0x7000 },
2283
2284                 { 0x03, 0x802f },
2285                 { 0x02, 0x4f02 },
2286                 { 0x01, 0x0409 },
2287                 { 0x00, 0xf0f9 },
2288                 { 0x04, 0x9800 },
2289                 { 0x04, 0x9000 },
2290
2291                 { 0x03, 0xdf01 },
2292                 { 0x02, 0xdf20 },
2293                 { 0x01, 0xff95 },
2294                 { 0x00, 0xba00 },
2295                 { 0x04, 0xa800 },
2296                 { 0x04, 0xa000 },
2297
2298                 { 0x03, 0xff41 },
2299                 { 0x02, 0xdf20 },
2300                 { 0x01, 0x0140 },
2301                 { 0x00, 0x00bb },
2302                 { 0x04, 0xb800 },
2303                 { 0x04, 0xb000 },
2304
2305                 { 0x03, 0xdf41 },
2306                 { 0x02, 0xdc60 },
2307                 { 0x01, 0x6340 },
2308                 { 0x00, 0x007d },
2309                 { 0x04, 0xd800 },
2310                 { 0x04, 0xd000 },
2311
2312                 { 0x03, 0xdf01 },
2313                 { 0x02, 0xdf20 },
2314                 { 0x01, 0x100a },
2315                 { 0x00, 0xa0ff },
2316                 { 0x04, 0xf800 },
2317                 { 0x04, 0xf000 },
2318
2319                 { 0x1f, 0x0000 },
2320                 { 0x0b, 0x0000 },
2321                 { 0x00, 0x9200 }
2322         };
2323
2324         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2325 }
2326
2327 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2328 {
2329         static const struct phy_reg phy_reg_init[] = {
2330                 { 0x1f, 0x0002 },
2331                 { 0x01, 0x90d0 },
2332                 { 0x1f, 0x0000 }
2333         };
2334
2335         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2336 }
2337
2338 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2339 {
2340         struct pci_dev *pdev = tp->pci_dev;
2341
2342         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2343             (pdev->subsystem_device != 0xe000))
2344                 return;
2345
2346         rtl_writephy(tp, 0x1f, 0x0001);
2347         rtl_writephy(tp, 0x10, 0xf01b);
2348         rtl_writephy(tp, 0x1f, 0x0000);
2349 }
2350
2351 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2352 {
2353         static const struct phy_reg phy_reg_init[] = {
2354                 { 0x1f, 0x0001 },
2355                 { 0x04, 0x0000 },
2356                 { 0x03, 0x00a1 },
2357                 { 0x02, 0x0008 },
2358                 { 0x01, 0x0120 },
2359                 { 0x00, 0x1000 },
2360                 { 0x04, 0x0800 },
2361                 { 0x04, 0x9000 },
2362                 { 0x03, 0x802f },
2363                 { 0x02, 0x4f02 },
2364                 { 0x01, 0x0409 },
2365                 { 0x00, 0xf099 },
2366                 { 0x04, 0x9800 },
2367                 { 0x04, 0xa000 },
2368                 { 0x03, 0xdf01 },
2369                 { 0x02, 0xdf20 },
2370                 { 0x01, 0xff95 },
2371                 { 0x00, 0xba00 },
2372                 { 0x04, 0xa800 },
2373                 { 0x04, 0xf000 },
2374                 { 0x03, 0xdf01 },
2375                 { 0x02, 0xdf20 },
2376                 { 0x01, 0x101a },
2377                 { 0x00, 0xa0ff },
2378                 { 0x04, 0xf800 },
2379                 { 0x04, 0x0000 },
2380                 { 0x1f, 0x0000 },
2381
2382                 { 0x1f, 0x0001 },
2383                 { 0x10, 0xf41b },
2384                 { 0x14, 0xfb54 },
2385                 { 0x18, 0xf5c7 },
2386                 { 0x1f, 0x0000 },
2387
2388                 { 0x1f, 0x0001 },
2389                 { 0x17, 0x0cc0 },
2390                 { 0x1f, 0x0000 }
2391         };
2392
2393         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2394
2395         rtl8169scd_hw_phy_config_quirk(tp);
2396 }
2397
2398 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2399 {
2400         static const struct phy_reg phy_reg_init[] = {
2401                 { 0x1f, 0x0001 },
2402                 { 0x04, 0x0000 },
2403                 { 0x03, 0x00a1 },
2404                 { 0x02, 0x0008 },
2405                 { 0x01, 0x0120 },
2406                 { 0x00, 0x1000 },
2407                 { 0x04, 0x0800 },
2408                 { 0x04, 0x9000 },
2409                 { 0x03, 0x802f },
2410                 { 0x02, 0x4f02 },
2411                 { 0x01, 0x0409 },
2412                 { 0x00, 0xf099 },
2413                 { 0x04, 0x9800 },
2414                 { 0x04, 0xa000 },
2415                 { 0x03, 0xdf01 },
2416                 { 0x02, 0xdf20 },
2417                 { 0x01, 0xff95 },
2418                 { 0x00, 0xba00 },
2419                 { 0x04, 0xa800 },
2420                 { 0x04, 0xf000 },
2421                 { 0x03, 0xdf01 },
2422                 { 0x02, 0xdf20 },
2423                 { 0x01, 0x101a },
2424                 { 0x00, 0xa0ff },
2425                 { 0x04, 0xf800 },
2426                 { 0x04, 0x0000 },
2427                 { 0x1f, 0x0000 },
2428
2429                 { 0x1f, 0x0001 },
2430                 { 0x0b, 0x8480 },
2431                 { 0x1f, 0x0000 },
2432
2433                 { 0x1f, 0x0001 },
2434                 { 0x18, 0x67c7 },
2435                 { 0x04, 0x2000 },
2436                 { 0x03, 0x002f },
2437                 { 0x02, 0x4360 },
2438                 { 0x01, 0x0109 },
2439                 { 0x00, 0x3022 },
2440                 { 0x04, 0x2800 },
2441                 { 0x1f, 0x0000 },
2442
2443                 { 0x1f, 0x0001 },
2444                 { 0x17, 0x0cc0 },
2445                 { 0x1f, 0x0000 }
2446         };
2447
2448         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2449 }
2450
2451 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2452 {
2453         static const struct phy_reg phy_reg_init[] = {
2454                 { 0x10, 0xf41b },
2455                 { 0x1f, 0x0000 }
2456         };
2457
2458         rtl_writephy(tp, 0x1f, 0x0001);
2459         rtl_patchphy(tp, 0x16, 1 << 0);
2460
2461         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2462 }
2463
2464 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2465 {
2466         static const struct phy_reg phy_reg_init[] = {
2467                 { 0x1f, 0x0001 },
2468                 { 0x10, 0xf41b },
2469                 { 0x1f, 0x0000 }
2470         };
2471
2472         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2473 }
2474
2475 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2476 {
2477         static const struct phy_reg phy_reg_init[] = {
2478                 { 0x1f, 0x0000 },
2479                 { 0x1d, 0x0f00 },
2480                 { 0x1f, 0x0002 },
2481                 { 0x0c, 0x1ec8 },
2482                 { 0x1f, 0x0000 }
2483         };
2484
2485         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2486 }
2487
2488 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2489 {
2490         static const struct phy_reg phy_reg_init[] = {
2491                 { 0x1f, 0x0001 },
2492                 { 0x1d, 0x3d98 },
2493                 { 0x1f, 0x0000 }
2494         };
2495
2496         rtl_writephy(tp, 0x1f, 0x0000);
2497         rtl_patchphy(tp, 0x14, 1 << 5);
2498         rtl_patchphy(tp, 0x0d, 1 << 5);
2499
2500         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2501 }
2502
2503 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2504 {
2505         static const struct phy_reg phy_reg_init[] = {
2506                 { 0x1f, 0x0001 },
2507                 { 0x12, 0x2300 },
2508                 { 0x1f, 0x0002 },
2509                 { 0x00, 0x88d4 },
2510                 { 0x01, 0x82b1 },
2511                 { 0x03, 0x7002 },
2512                 { 0x08, 0x9e30 },
2513                 { 0x09, 0x01f0 },
2514                 { 0x0a, 0x5500 },
2515                 { 0x0c, 0x00c8 },
2516                 { 0x1f, 0x0003 },
2517                 { 0x12, 0xc096 },
2518                 { 0x16, 0x000a },
2519                 { 0x1f, 0x0000 },
2520                 { 0x1f, 0x0000 },
2521                 { 0x09, 0x2000 },
2522                 { 0x09, 0x0000 }
2523         };
2524
2525         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2526
2527         rtl_patchphy(tp, 0x14, 1 << 5);
2528         rtl_patchphy(tp, 0x0d, 1 << 5);
2529         rtl_writephy(tp, 0x1f, 0x0000);
2530 }
2531
2532 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2533 {
2534         static const struct phy_reg phy_reg_init[] = {
2535                 { 0x1f, 0x0001 },
2536                 { 0x12, 0x2300 },
2537                 { 0x03, 0x802f },
2538                 { 0x02, 0x4f02 },
2539                 { 0x01, 0x0409 },
2540                 { 0x00, 0xf099 },
2541                 { 0x04, 0x9800 },
2542                 { 0x04, 0x9000 },
2543                 { 0x1d, 0x3d98 },
2544                 { 0x1f, 0x0002 },
2545                 { 0x0c, 0x7eb8 },
2546                 { 0x06, 0x0761 },
2547                 { 0x1f, 0x0003 },
2548                 { 0x16, 0x0f0a },
2549                 { 0x1f, 0x0000 }
2550         };
2551
2552         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2553
2554         rtl_patchphy(tp, 0x16, 1 << 0);
2555         rtl_patchphy(tp, 0x14, 1 << 5);
2556         rtl_patchphy(tp, 0x0d, 1 << 5);
2557         rtl_writephy(tp, 0x1f, 0x0000);
2558 }
2559
2560 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2561 {
2562         static const struct phy_reg phy_reg_init[] = {
2563                 { 0x1f, 0x0001 },
2564                 { 0x12, 0x2300 },
2565                 { 0x1d, 0x3d98 },
2566                 { 0x1f, 0x0002 },
2567                 { 0x0c, 0x7eb8 },
2568                 { 0x06, 0x5461 },
2569                 { 0x1f, 0x0003 },
2570                 { 0x16, 0x0f0a },
2571                 { 0x1f, 0x0000 }
2572         };
2573
2574         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2575
2576         rtl_patchphy(tp, 0x16, 1 << 0);
2577         rtl_patchphy(tp, 0x14, 1 << 5);
2578         rtl_patchphy(tp, 0x0d, 1 << 5);
2579         rtl_writephy(tp, 0x1f, 0x0000);
2580 }
2581
2582 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2583 {
2584         rtl8168c_3_hw_phy_config(tp);
2585 }
2586
2587 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2588 {
2589         static const struct phy_reg phy_reg_init_0[] = {
2590                 /* Channel Estimation */
2591                 { 0x1f, 0x0001 },
2592                 { 0x06, 0x4064 },
2593                 { 0x07, 0x2863 },
2594                 { 0x08, 0x059c },
2595                 { 0x09, 0x26b4 },
2596                 { 0x0a, 0x6a19 },
2597                 { 0x0b, 0xdcc8 },
2598                 { 0x10, 0xf06d },
2599                 { 0x14, 0x7f68 },
2600                 { 0x18, 0x7fd9 },
2601                 { 0x1c, 0xf0ff },
2602                 { 0x1d, 0x3d9c },
2603                 { 0x1f, 0x0003 },
2604                 { 0x12, 0xf49f },
2605                 { 0x13, 0x070b },
2606                 { 0x1a, 0x05ad },
2607                 { 0x14, 0x94c0 },
2608
2609                 /*
2610                  * Tx Error Issue
2611                  * Enhance line driver power
2612                  */
2613                 { 0x1f, 0x0002 },
2614                 { 0x06, 0x5561 },
2615                 { 0x1f, 0x0005 },
2616                 { 0x05, 0x8332 },
2617                 { 0x06, 0x5561 },
2618
2619                 /*
2620                  * Can not link to 1Gbps with bad cable
2621                  * Decrease SNR threshold form 21.07dB to 19.04dB
2622                  */
2623                 { 0x1f, 0x0001 },
2624                 { 0x17, 0x0cc0 },
2625
2626                 { 0x1f, 0x0000 },
2627                 { 0x0d, 0xf880 }
2628         };
2629         void __iomem *ioaddr = tp->mmio_addr;
2630
2631         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2632
2633         /*
2634          * Rx Error Issue
2635          * Fine Tune Switching regulator parameter
2636          */
2637         rtl_writephy(tp, 0x1f, 0x0002);
2638         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2639         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2640
2641         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2642                 static const struct phy_reg phy_reg_init[] = {
2643                         { 0x1f, 0x0002 },
2644                         { 0x05, 0x669a },
2645                         { 0x1f, 0x0005 },
2646                         { 0x05, 0x8330 },
2647                         { 0x06, 0x669a },
2648                         { 0x1f, 0x0002 }
2649                 };
2650                 int val;
2651
2652                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2653
2654                 val = rtl_readphy(tp, 0x0d);
2655
2656                 if ((val & 0x00ff) != 0x006c) {
2657                         static const u32 set[] = {
2658                                 0x0065, 0x0066, 0x0067, 0x0068,
2659                                 0x0069, 0x006a, 0x006b, 0x006c
2660                         };
2661                         int i;
2662
2663                         rtl_writephy(tp, 0x1f, 0x0002);
2664
2665                         val &= 0xff00;
2666                         for (i = 0; i < ARRAY_SIZE(set); i++)
2667                                 rtl_writephy(tp, 0x0d, val | set[i]);
2668                 }
2669         } else {
2670                 static const struct phy_reg phy_reg_init[] = {
2671                         { 0x1f, 0x0002 },
2672                         { 0x05, 0x6662 },
2673                         { 0x1f, 0x0005 },
2674                         { 0x05, 0x8330 },
2675                         { 0x06, 0x6662 }
2676                 };
2677
2678                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2679         }
2680
2681         /* RSET couple improve */
2682         rtl_writephy(tp, 0x1f, 0x0002);
2683         rtl_patchphy(tp, 0x0d, 0x0300);
2684         rtl_patchphy(tp, 0x0f, 0x0010);
2685
2686         /* Fine tune PLL performance */
2687         rtl_writephy(tp, 0x1f, 0x0002);
2688         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2689         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2690
2691         rtl_writephy(tp, 0x1f, 0x0005);
2692         rtl_writephy(tp, 0x05, 0x001b);
2693
2694         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2695
2696         rtl_writephy(tp, 0x1f, 0x0000);
2697 }
2698
2699 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2700 {
2701         static const struct phy_reg phy_reg_init_0[] = {
2702                 /* Channel Estimation */
2703                 { 0x1f, 0x0001 },
2704                 { 0x06, 0x4064 },
2705                 { 0x07, 0x2863 },
2706                 { 0x08, 0x059c },
2707                 { 0x09, 0x26b4 },
2708                 { 0x0a, 0x6a19 },
2709                 { 0x0b, 0xdcc8 },
2710                 { 0x10, 0xf06d },
2711                 { 0x14, 0x7f68 },
2712                 { 0x18, 0x7fd9 },
2713                 { 0x1c, 0xf0ff },
2714                 { 0x1d, 0x3d9c },
2715                 { 0x1f, 0x0003 },
2716                 { 0x12, 0xf49f },
2717                 { 0x13, 0x070b },
2718                 { 0x1a, 0x05ad },
2719                 { 0x14, 0x94c0 },
2720
2721                 /*
2722                  * Tx Error Issue
2723                  * Enhance line driver power
2724                  */
2725                 { 0x1f, 0x0002 },
2726                 { 0x06, 0x5561 },
2727                 { 0x1f, 0x0005 },
2728                 { 0x05, 0x8332 },
2729                 { 0x06, 0x5561 },
2730
2731                 /*
2732                  * Can not link to 1Gbps with bad cable
2733                  * Decrease SNR threshold form 21.07dB to 19.04dB
2734                  */
2735                 { 0x1f, 0x0001 },
2736                 { 0x17, 0x0cc0 },
2737
2738                 { 0x1f, 0x0000 },
2739                 { 0x0d, 0xf880 }
2740         };
2741         void __iomem *ioaddr = tp->mmio_addr;
2742
2743         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2744
2745         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2746                 static const struct phy_reg phy_reg_init[] = {
2747                         { 0x1f, 0x0002 },
2748                         { 0x05, 0x669a },
2749                         { 0x1f, 0x0005 },
2750                         { 0x05, 0x8330 },
2751                         { 0x06, 0x669a },
2752
2753                         { 0x1f, 0x0002 }
2754                 };
2755                 int val;
2756
2757                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2758
2759                 val = rtl_readphy(tp, 0x0d);
2760                 if ((val & 0x00ff) != 0x006c) {
2761                         static const u32 set[] = {
2762                                 0x0065, 0x0066, 0x0067, 0x0068,
2763                                 0x0069, 0x006a, 0x006b, 0x006c
2764                         };
2765                         int i;
2766
2767                         rtl_writephy(tp, 0x1f, 0x0002);
2768
2769                         val &= 0xff00;
2770                         for (i = 0; i < ARRAY_SIZE(set); i++)
2771                                 rtl_writephy(tp, 0x0d, val | set[i]);
2772                 }
2773         } else {
2774                 static const struct phy_reg phy_reg_init[] = {
2775                         { 0x1f, 0x0002 },
2776                         { 0x05, 0x2642 },
2777                         { 0x1f, 0x0005 },
2778                         { 0x05, 0x8330 },
2779                         { 0x06, 0x2642 }
2780                 };
2781
2782                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2783         }
2784
2785         /* Fine tune PLL performance */
2786         rtl_writephy(tp, 0x1f, 0x0002);
2787         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2788         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2789
2790         /* Switching regulator Slew rate */
2791         rtl_writephy(tp, 0x1f, 0x0002);
2792         rtl_patchphy(tp, 0x0f, 0x0017);
2793
2794         rtl_writephy(tp, 0x1f, 0x0005);
2795         rtl_writephy(tp, 0x05, 0x001b);
2796
2797         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2798
2799         rtl_writephy(tp, 0x1f, 0x0000);
2800 }
2801
2802 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2803 {
2804         static const struct phy_reg phy_reg_init[] = {
2805                 { 0x1f, 0x0002 },
2806                 { 0x10, 0x0008 },
2807                 { 0x0d, 0x006c },
2808
2809                 { 0x1f, 0x0000 },
2810                 { 0x0d, 0xf880 },
2811
2812                 { 0x1f, 0x0001 },
2813                 { 0x17, 0x0cc0 },
2814
2815                 { 0x1f, 0x0001 },
2816                 { 0x0b, 0xa4d8 },
2817                 { 0x09, 0x281c },
2818                 { 0x07, 0x2883 },
2819                 { 0x0a, 0x6b35 },
2820                 { 0x1d, 0x3da4 },
2821                 { 0x1c, 0xeffd },
2822                 { 0x14, 0x7f52 },
2823                 { 0x18, 0x7fc6 },
2824                 { 0x08, 0x0601 },
2825                 { 0x06, 0x4063 },
2826                 { 0x10, 0xf074 },
2827                 { 0x1f, 0x0003 },
2828                 { 0x13, 0x0789 },
2829                 { 0x12, 0xf4bd },
2830                 { 0x1a, 0x04fd },
2831                 { 0x14, 0x84b0 },
2832                 { 0x1f, 0x0000 },
2833                 { 0x00, 0x9200 },
2834
2835                 { 0x1f, 0x0005 },
2836                 { 0x01, 0x0340 },
2837                 { 0x1f, 0x0001 },
2838                 { 0x04, 0x4000 },
2839                 { 0x03, 0x1d21 },
2840                 { 0x02, 0x0c32 },
2841                 { 0x01, 0x0200 },
2842                 { 0x00, 0x5554 },
2843                 { 0x04, 0x4800 },
2844                 { 0x04, 0x4000 },
2845                 { 0x04, 0xf000 },
2846                 { 0x03, 0xdf01 },
2847                 { 0x02, 0xdf20 },
2848                 { 0x01, 0x101a },
2849                 { 0x00, 0xa0ff },
2850                 { 0x04, 0xf800 },
2851                 { 0x04, 0xf000 },
2852                 { 0x1f, 0x0000 },
2853
2854                 { 0x1f, 0x0007 },
2855                 { 0x1e, 0x0023 },
2856                 { 0x16, 0x0000 },
2857                 { 0x1f, 0x0000 }
2858         };
2859
2860         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2861 }
2862
2863 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2864 {
2865         static const struct phy_reg phy_reg_init[] = {
2866                 { 0x1f, 0x0001 },
2867                 { 0x17, 0x0cc0 },
2868
2869                 { 0x1f, 0x0007 },
2870                 { 0x1e, 0x002d },
2871                 { 0x18, 0x0040 },
2872                 { 0x1f, 0x0000 }
2873         };
2874
2875         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2876         rtl_patchphy(tp, 0x0d, 1 << 5);
2877 }
2878
2879 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2880 {
2881         static const struct phy_reg phy_reg_init[] = {
2882                 /* Enable Delay cap */
2883                 { 0x1f, 0x0005 },
2884                 { 0x05, 0x8b80 },
2885                 { 0x06, 0xc896 },
2886                 { 0x1f, 0x0000 },
2887
2888                 /* Channel estimation fine tune */
2889                 { 0x1f, 0x0001 },
2890                 { 0x0b, 0x6c20 },
2891                 { 0x07, 0x2872 },
2892                 { 0x1c, 0xefff },
2893                 { 0x1f, 0x0003 },
2894                 { 0x14, 0x6420 },
2895                 { 0x1f, 0x0000 },
2896
2897                 /* Update PFM & 10M TX idle timer */
2898                 { 0x1f, 0x0007 },
2899                 { 0x1e, 0x002f },
2900                 { 0x15, 0x1919 },
2901                 { 0x1f, 0x0000 },
2902
2903                 { 0x1f, 0x0007 },
2904                 { 0x1e, 0x00ac },
2905                 { 0x18, 0x0006 },
2906                 { 0x1f, 0x0000 }
2907         };
2908
2909         rtl_apply_firmware(tp);
2910
2911         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2912
2913         /* DCO enable for 10M IDLE Power */
2914         rtl_writephy(tp, 0x1f, 0x0007);
2915         rtl_writephy(tp, 0x1e, 0x0023);
2916         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2917         rtl_writephy(tp, 0x1f, 0x0000);
2918
2919         /* For impedance matching */
2920         rtl_writephy(tp, 0x1f, 0x0002);
2921         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2922         rtl_writephy(tp, 0x1f, 0x0000);
2923
2924         /* PHY auto speed down */
2925         rtl_writephy(tp, 0x1f, 0x0007);
2926         rtl_writephy(tp, 0x1e, 0x002d);
2927         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2928         rtl_writephy(tp, 0x1f, 0x0000);
2929         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2930
2931         rtl_writephy(tp, 0x1f, 0x0005);
2932         rtl_writephy(tp, 0x05, 0x8b86);
2933         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2934         rtl_writephy(tp, 0x1f, 0x0000);
2935
2936         rtl_writephy(tp, 0x1f, 0x0005);
2937         rtl_writephy(tp, 0x05, 0x8b85);
2938         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2939         rtl_writephy(tp, 0x1f, 0x0007);
2940         rtl_writephy(tp, 0x1e, 0x0020);
2941         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2942         rtl_writephy(tp, 0x1f, 0x0006);
2943         rtl_writephy(tp, 0x00, 0x5a00);
2944         rtl_writephy(tp, 0x1f, 0x0000);
2945         rtl_writephy(tp, 0x0d, 0x0007);
2946         rtl_writephy(tp, 0x0e, 0x003c);
2947         rtl_writephy(tp, 0x0d, 0x4007);
2948         rtl_writephy(tp, 0x0e, 0x0000);
2949         rtl_writephy(tp, 0x0d, 0x0000);
2950 }
2951
2952 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2953 {
2954         static const struct phy_reg phy_reg_init[] = {
2955                 /* Enable Delay cap */
2956                 { 0x1f, 0x0004 },
2957                 { 0x1f, 0x0007 },
2958                 { 0x1e, 0x00ac },
2959                 { 0x18, 0x0006 },
2960                 { 0x1f, 0x0002 },
2961                 { 0x1f, 0x0000 },
2962                 { 0x1f, 0x0000 },
2963
2964                 /* Channel estimation fine tune */
2965                 { 0x1f, 0x0003 },
2966                 { 0x09, 0xa20f },
2967                 { 0x1f, 0x0000 },
2968                 { 0x1f, 0x0000 },
2969
2970                 /* Green Setting */
2971                 { 0x1f, 0x0005 },
2972                 { 0x05, 0x8b5b },
2973                 { 0x06, 0x9222 },
2974                 { 0x05, 0x8b6d },
2975                 { 0x06, 0x8000 },
2976                 { 0x05, 0x8b76 },
2977                 { 0x06, 0x8000 },
2978                 { 0x1f, 0x0000 }
2979         };
2980
2981         rtl_apply_firmware(tp);
2982
2983         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2984
2985         /* For 4-corner performance improve */
2986         rtl_writephy(tp, 0x1f, 0x0005);
2987         rtl_writephy(tp, 0x05, 0x8b80);
2988         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2989         rtl_writephy(tp, 0x1f, 0x0000);
2990
2991         /* PHY auto speed down */
2992         rtl_writephy(tp, 0x1f, 0x0004);
2993         rtl_writephy(tp, 0x1f, 0x0007);
2994         rtl_writephy(tp, 0x1e, 0x002d);
2995         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2996         rtl_writephy(tp, 0x1f, 0x0002);
2997         rtl_writephy(tp, 0x1f, 0x0000);
2998         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2999
3000         /* improve 10M EEE waveform */
3001         rtl_writephy(tp, 0x1f, 0x0005);
3002         rtl_writephy(tp, 0x05, 0x8b86);
3003         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3004         rtl_writephy(tp, 0x1f, 0x0000);
3005
3006         /* Improve 2-pair detection performance */
3007         rtl_writephy(tp, 0x1f, 0x0005);
3008         rtl_writephy(tp, 0x05, 0x8b85);
3009         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3010         rtl_writephy(tp, 0x1f, 0x0000);
3011
3012         /* EEE setting */
3013         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3014                      ERIAR_EXGMAC);
3015         rtl_writephy(tp, 0x1f, 0x0005);
3016         rtl_writephy(tp, 0x05, 0x8b85);
3017         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3018         rtl_writephy(tp, 0x1f, 0x0004);
3019         rtl_writephy(tp, 0x1f, 0x0007);
3020         rtl_writephy(tp, 0x1e, 0x0020);
3021         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3022         rtl_writephy(tp, 0x1f, 0x0002);
3023         rtl_writephy(tp, 0x1f, 0x0000);
3024         rtl_writephy(tp, 0x0d, 0x0007);
3025         rtl_writephy(tp, 0x0e, 0x003c);
3026         rtl_writephy(tp, 0x0d, 0x4007);
3027         rtl_writephy(tp, 0x0e, 0x0000);
3028         rtl_writephy(tp, 0x0d, 0x0000);
3029
3030         /* Green feature */
3031         rtl_writephy(tp, 0x1f, 0x0003);
3032         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3033         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3034         rtl_writephy(tp, 0x1f, 0x0000);
3035 }
3036
3037 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3038 {
3039         /* For 4-corner performance improve */
3040         rtl_writephy(tp, 0x1f, 0x0005);
3041         rtl_writephy(tp, 0x05, 0x8b80);
3042         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3043         rtl_writephy(tp, 0x1f, 0x0000);
3044
3045         /* PHY auto speed down */
3046         rtl_writephy(tp, 0x1f, 0x0007);
3047         rtl_writephy(tp, 0x1e, 0x002d);
3048         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3049         rtl_writephy(tp, 0x1f, 0x0000);
3050         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3051
3052         /* Improve 10M EEE waveform */
3053         rtl_writephy(tp, 0x1f, 0x0005);
3054         rtl_writephy(tp, 0x05, 0x8b86);
3055         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3056         rtl_writephy(tp, 0x1f, 0x0000);
3057 }
3058
3059 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3060 {
3061         static const struct phy_reg phy_reg_init[] = {
3062                 /* Channel estimation fine tune */
3063                 { 0x1f, 0x0003 },
3064                 { 0x09, 0xa20f },
3065                 { 0x1f, 0x0000 },
3066
3067                 /* Modify green table for giga & fnet */
3068                 { 0x1f, 0x0005 },
3069                 { 0x05, 0x8b55 },
3070                 { 0x06, 0x0000 },
3071                 { 0x05, 0x8b5e },
3072                 { 0x06, 0x0000 },
3073                 { 0x05, 0x8b67 },
3074                 { 0x06, 0x0000 },
3075                 { 0x05, 0x8b70 },
3076                 { 0x06, 0x0000 },
3077                 { 0x1f, 0x0000 },
3078                 { 0x1f, 0x0007 },
3079                 { 0x1e, 0x0078 },
3080                 { 0x17, 0x0000 },
3081                 { 0x19, 0x00fb },
3082                 { 0x1f, 0x0000 },
3083
3084                 /* Modify green table for 10M */
3085                 { 0x1f, 0x0005 },
3086                 { 0x05, 0x8b79 },
3087                 { 0x06, 0xaa00 },
3088                 { 0x1f, 0x0000 },
3089
3090                 /* Disable hiimpedance detection (RTCT) */
3091                 { 0x1f, 0x0003 },
3092                 { 0x01, 0x328a },
3093                 { 0x1f, 0x0000 }
3094         };
3095
3096         rtl_apply_firmware(tp);
3097
3098         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3099
3100         rtl8168f_hw_phy_config(tp);
3101
3102         /* Improve 2-pair detection performance */
3103         rtl_writephy(tp, 0x1f, 0x0005);
3104         rtl_writephy(tp, 0x05, 0x8b85);
3105         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3106         rtl_writephy(tp, 0x1f, 0x0000);
3107 }
3108
3109 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3110 {
3111         rtl_apply_firmware(tp);
3112
3113         rtl8168f_hw_phy_config(tp);
3114 }
3115
3116 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3117 {
3118         void __iomem *ioaddr = tp->mmio_addr;
3119         static const struct phy_reg phy_reg_init[] = {
3120                 /* Channel estimation fine tune */
3121                 { 0x1f, 0x0003 },
3122                 { 0x09, 0xa20f },
3123                 { 0x1f, 0x0000 },
3124
3125                 /* Modify green table for giga & fnet */
3126                 { 0x1f, 0x0005 },
3127                 { 0x05, 0x8b55 },
3128                 { 0x06, 0x0000 },
3129                 { 0x05, 0x8b5e },
3130                 { 0x06, 0x0000 },
3131                 { 0x05, 0x8b67 },
3132                 { 0x06, 0x0000 },
3133                 { 0x05, 0x8b70 },
3134                 { 0x06, 0x0000 },
3135                 { 0x1f, 0x0000 },
3136                 { 0x1f, 0x0007 },
3137                 { 0x1e, 0x0078 },
3138                 { 0x17, 0x0000 },
3139                 { 0x19, 0x00aa },
3140                 { 0x1f, 0x0000 },
3141
3142                 /* Modify green table for 10M */
3143                 { 0x1f, 0x0005 },
3144                 { 0x05, 0x8b79 },
3145                 { 0x06, 0xaa00 },
3146                 { 0x1f, 0x0000 },
3147
3148                 /* Disable hiimpedance detection (RTCT) */
3149                 { 0x1f, 0x0003 },
3150                 { 0x01, 0x328a },
3151                 { 0x1f, 0x0000 }
3152         };
3153
3154
3155         rtl_apply_firmware(tp);
3156
3157         rtl8168f_hw_phy_config(tp);
3158
3159         /* Improve 2-pair detection performance */
3160         rtl_writephy(tp, 0x1f, 0x0005);
3161         rtl_writephy(tp, 0x05, 0x8b85);
3162         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3163         rtl_writephy(tp, 0x1f, 0x0000);
3164
3165         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3166
3167         /* Modify green table for giga */
3168         rtl_writephy(tp, 0x1f, 0x0005);
3169         rtl_writephy(tp, 0x05, 0x8b54);
3170         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3171         rtl_writephy(tp, 0x05, 0x8b5d);
3172         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3173         rtl_writephy(tp, 0x05, 0x8a7c);
3174         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3175         rtl_writephy(tp, 0x05, 0x8a7f);
3176         rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3177         rtl_writephy(tp, 0x05, 0x8a82);
3178         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3179         rtl_writephy(tp, 0x05, 0x8a85);
3180         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3181         rtl_writephy(tp, 0x05, 0x8a88);
3182         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3183         rtl_writephy(tp, 0x1f, 0x0000);
3184
3185         /* uc same-seed solution */
3186         rtl_writephy(tp, 0x1f, 0x0005);
3187         rtl_writephy(tp, 0x05, 0x8b85);
3188         rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3189         rtl_writephy(tp, 0x1f, 0x0000);
3190
3191         /* eee setting */
3192         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3193         rtl_writephy(tp, 0x1f, 0x0005);
3194         rtl_writephy(tp, 0x05, 0x8b85);
3195         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3196         rtl_writephy(tp, 0x1f, 0x0004);
3197         rtl_writephy(tp, 0x1f, 0x0007);
3198         rtl_writephy(tp, 0x1e, 0x0020);
3199         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3200         rtl_writephy(tp, 0x1f, 0x0000);
3201         rtl_writephy(tp, 0x0d, 0x0007);
3202         rtl_writephy(tp, 0x0e, 0x003c);
3203         rtl_writephy(tp, 0x0d, 0x4007);
3204         rtl_writephy(tp, 0x0e, 0x0000);
3205         rtl_writephy(tp, 0x0d, 0x0000);
3206
3207         /* Green feature */
3208         rtl_writephy(tp, 0x1f, 0x0003);
3209         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3210         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3211         rtl_writephy(tp, 0x1f, 0x0000);
3212 }
3213
3214 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3215 {
3216         static const struct phy_reg phy_reg_init[] = {
3217                 { 0x1f, 0x0003 },
3218                 { 0x08, 0x441d },
3219                 { 0x01, 0x9100 },
3220                 { 0x1f, 0x0000 }
3221         };
3222
3223         rtl_writephy(tp, 0x1f, 0x0000);
3224         rtl_patchphy(tp, 0x11, 1 << 12);
3225         rtl_patchphy(tp, 0x19, 1 << 13);
3226         rtl_patchphy(tp, 0x10, 1 << 15);
3227
3228         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3229 }
3230
3231 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3232 {
3233         static const struct phy_reg phy_reg_init[] = {
3234                 { 0x1f, 0x0005 },
3235                 { 0x1a, 0x0000 },
3236                 { 0x1f, 0x0000 },
3237
3238                 { 0x1f, 0x0004 },
3239                 { 0x1c, 0x0000 },
3240                 { 0x1f, 0x0000 },
3241
3242                 { 0x1f, 0x0001 },
3243                 { 0x15, 0x7701 },
3244                 { 0x1f, 0x0000 }
3245         };
3246
3247         /* Disable ALDPS before ram code */
3248         rtl_writephy(tp, 0x1f, 0x0000);
3249         rtl_writephy(tp, 0x18, 0x0310);
3250         msleep(100);
3251
3252         rtl_apply_firmware(tp);
3253
3254         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3255 }
3256
3257 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3258 {
3259         void __iomem *ioaddr = tp->mmio_addr;
3260
3261         /* Disable ALDPS before setting firmware */
3262         rtl_writephy(tp, 0x1f, 0x0000);
3263         rtl_writephy(tp, 0x18, 0x0310);
3264         msleep(20);
3265
3266         rtl_apply_firmware(tp);
3267
3268         /* EEE setting */
3269         rtl_eri_write(ioaddr, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3270         rtl_writephy(tp, 0x1f, 0x0004);
3271         rtl_writephy(tp, 0x10, 0x401f);
3272         rtl_writephy(tp, 0x19, 0x7030);
3273         rtl_writephy(tp, 0x1f, 0x0000);
3274 }
3275
3276 static void rtl_hw_phy_config(struct net_device *dev)
3277 {
3278         struct rtl8169_private *tp = netdev_priv(dev);
3279
3280         rtl8169_print_mac_version(tp);
3281
3282         switch (tp->mac_version) {
3283         case RTL_GIGA_MAC_VER_01:
3284                 break;
3285         case RTL_GIGA_MAC_VER_02:
3286         case RTL_GIGA_MAC_VER_03:
3287                 rtl8169s_hw_phy_config(tp);
3288                 break;
3289         case RTL_GIGA_MAC_VER_04:
3290                 rtl8169sb_hw_phy_config(tp);
3291                 break;
3292         case RTL_GIGA_MAC_VER_05:
3293                 rtl8169scd_hw_phy_config(tp);
3294                 break;
3295         case RTL_GIGA_MAC_VER_06:
3296                 rtl8169sce_hw_phy_config(tp);
3297                 break;
3298         case RTL_GIGA_MAC_VER_07:
3299         case RTL_GIGA_MAC_VER_08:
3300         case RTL_GIGA_MAC_VER_09:
3301                 rtl8102e_hw_phy_config(tp);
3302                 break;
3303         case RTL_GIGA_MAC_VER_11:
3304                 rtl8168bb_hw_phy_config(tp);
3305                 break;
3306         case RTL_GIGA_MAC_VER_12:
3307                 rtl8168bef_hw_phy_config(tp);
3308                 break;
3309         case RTL_GIGA_MAC_VER_17:
3310                 rtl8168bef_hw_phy_config(tp);
3311                 break;
3312         case RTL_GIGA_MAC_VER_18:
3313                 rtl8168cp_1_hw_phy_config(tp);
3314                 break;
3315         case RTL_GIGA_MAC_VER_19:
3316                 rtl8168c_1_hw_phy_config(tp);
3317                 break;
3318         case RTL_GIGA_MAC_VER_20:
3319                 rtl8168c_2_hw_phy_config(tp);
3320                 break;
3321         case RTL_GIGA_MAC_VER_21:
3322                 rtl8168c_3_hw_phy_config(tp);
3323                 break;
3324         case RTL_GIGA_MAC_VER_22:
3325                 rtl8168c_4_hw_phy_config(tp);
3326                 break;
3327         case RTL_GIGA_MAC_VER_23:
3328         case RTL_GIGA_MAC_VER_24:
3329                 rtl8168cp_2_hw_phy_config(tp);
3330                 break;
3331         case RTL_GIGA_MAC_VER_25:
3332                 rtl8168d_1_hw_phy_config(tp);
3333                 break;
3334         case RTL_GIGA_MAC_VER_26:
3335                 rtl8168d_2_hw_phy_config(tp);
3336                 break;
3337         case RTL_GIGA_MAC_VER_27:
3338                 rtl8168d_3_hw_phy_config(tp);
3339                 break;
3340         case RTL_GIGA_MAC_VER_28:
3341                 rtl8168d_4_hw_phy_config(tp);
3342                 break;
3343         case RTL_GIGA_MAC_VER_29:
3344         case RTL_GIGA_MAC_VER_30:
3345                 rtl8105e_hw_phy_config(tp);
3346                 break;
3347         case RTL_GIGA_MAC_VER_31:
3348                 /* None. */
3349                 break;
3350         case RTL_GIGA_MAC_VER_32:
3351         case RTL_GIGA_MAC_VER_33:
3352                 rtl8168e_1_hw_phy_config(tp);
3353                 break;
3354         case RTL_GIGA_MAC_VER_34:
3355                 rtl8168e_2_hw_phy_config(tp);
3356                 break;
3357         case RTL_GIGA_MAC_VER_35:
3358                 rtl8168f_1_hw_phy_config(tp);
3359                 break;
3360         case RTL_GIGA_MAC_VER_36:
3361                 rtl8168f_2_hw_phy_config(tp);
3362                 break;
3363
3364         case RTL_GIGA_MAC_VER_37:
3365                 rtl8402_hw_phy_config(tp);
3366                 break;
3367
3368         case RTL_GIGA_MAC_VER_38:
3369                 rtl8411_hw_phy_config(tp);
3370                 break;
3371
3372         default:
3373                 break;
3374         }
3375 }
3376
3377 static void rtl_phy_work(struct rtl8169_private *tp)
3378 {
3379         struct timer_list *timer = &tp->timer;
3380         void __iomem *ioaddr = tp->mmio_addr;
3381         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3382
3383         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3384
3385         if (tp->phy_reset_pending(tp)) {
3386                 /*
3387                  * A busy loop could burn quite a few cycles on nowadays CPU.
3388                  * Let's delay the execution of the timer for a few ticks.
3389                  */
3390                 timeout = HZ/10;
3391                 goto out_mod_timer;
3392         }
3393
3394         if (tp->link_ok(ioaddr))
3395                 return;
3396
3397         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3398
3399         tp->phy_reset_enable(tp);
3400
3401 out_mod_timer:
3402         mod_timer(timer, jiffies + timeout);
3403 }
3404
3405 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3406 {
3407         if (!test_and_set_bit(flag, tp->wk.flags))
3408                 schedule_work(&tp->wk.work);
3409 }
3410
3411 static void rtl8169_phy_timer(unsigned long __opaque)
3412 {
3413         struct net_device *dev = (struct net_device *)__opaque;
3414         struct rtl8169_private *tp = netdev_priv(dev);
3415
3416         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3417 }
3418
3419 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3420                                   void __iomem *ioaddr)
3421 {
3422         iounmap(ioaddr);
3423         pci_release_regions(pdev);
3424         pci_clear_mwi(pdev);
3425         pci_disable_device(pdev);
3426         free_netdev(dev);
3427 }
3428
3429 static void rtl8169_phy_reset(struct net_device *dev,
3430                               struct rtl8169_private *tp)
3431 {
3432         unsigned int i;
3433
3434         tp->phy_reset_enable(tp);
3435         for (i = 0; i < 100; i++) {
3436                 if (!tp->phy_reset_pending(tp))
3437                         return;
3438                 msleep(1);
3439         }
3440         netif_err(tp, link, dev, "PHY reset failed\n");
3441 }
3442
3443 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3444 {
3445         void __iomem *ioaddr = tp->mmio_addr;
3446
3447         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3448             (RTL_R8(PHYstatus) & TBI_Enable);
3449 }
3450
3451 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3452 {
3453         void __iomem *ioaddr = tp->mmio_addr;
3454
3455         rtl_hw_phy_config(dev);
3456
3457         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3458                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3459                 RTL_W8(0x82, 0x01);
3460         }
3461
3462         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3463
3464         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3465                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3466
3467         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3468                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3469                 RTL_W8(0x82, 0x01);
3470                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3471                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3472         }
3473
3474         rtl8169_phy_reset(dev, tp);
3475
3476         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3477                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3478                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3479                           (tp->mii.supports_gmii ?
3480                            ADVERTISED_1000baseT_Half |
3481                            ADVERTISED_1000baseT_Full : 0));
3482
3483         if (rtl_tbi_enabled(tp))
3484                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3485 }
3486
3487 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3488 {
3489         void __iomem *ioaddr = tp->mmio_addr;
3490         u32 high;
3491         u32 low;
3492
3493         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3494         high = addr[4] | (addr[5] << 8);
3495
3496         rtl_lock_work(tp);
3497
3498         RTL_W8(Cfg9346, Cfg9346_Unlock);
3499
3500         RTL_W32(MAC4, high);
3501         RTL_R32(MAC4);
3502
3503         RTL_W32(MAC0, low);
3504         RTL_R32(MAC0);
3505
3506         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3507                 const struct exgmac_reg e[] = {
3508                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3509                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3510                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3511                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3512                                                                 low  >> 16 },
3513                 };
3514
3515                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3516         }
3517
3518         RTL_W8(Cfg9346, Cfg9346_Lock);
3519
3520         rtl_unlock_work(tp);
3521 }
3522
3523 static int rtl_set_mac_address(struct net_device *dev, void *p)
3524 {
3525         struct rtl8169_private *tp = netdev_priv(dev);
3526         struct sockaddr *addr = p;
3527
3528         if (!is_valid_ether_addr(addr->sa_data))
3529                 return -EADDRNOTAVAIL;
3530
3531         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3532
3533         rtl_rar_set(tp, dev->dev_addr);
3534
3535         return 0;
3536 }
3537
3538 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3539 {
3540         struct rtl8169_private *tp = netdev_priv(dev);
3541         struct mii_ioctl_data *data = if_mii(ifr);
3542
3543         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3544 }
3545
3546 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3547                           struct mii_ioctl_data *data, int cmd)
3548 {
3549         switch (cmd) {
3550         case SIOCGMIIPHY:
3551                 data->phy_id = 32; /* Internal PHY */
3552                 return 0;
3553
3554         case SIOCGMIIREG:
3555                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3556                 return 0;
3557
3558         case SIOCSMIIREG:
3559                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3560                 return 0;
3561         }
3562         return -EOPNOTSUPP;
3563 }
3564
3565 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3566 {
3567         return -EOPNOTSUPP;
3568 }
3569
3570 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3571 {
3572         if (tp->features & RTL_FEATURE_MSI) {
3573                 pci_disable_msi(pdev);
3574                 tp->features &= ~RTL_FEATURE_MSI;
3575         }
3576 }
3577
3578 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3579 {
3580         struct mdio_ops *ops = &tp->mdio_ops;
3581
3582         switch (tp->mac_version) {
3583         case RTL_GIGA_MAC_VER_27:
3584                 ops->write      = r8168dp_1_mdio_write;
3585                 ops->read       = r8168dp_1_mdio_read;
3586                 break;
3587         case RTL_GIGA_MAC_VER_28:
3588         case RTL_GIGA_MAC_VER_31:
3589                 ops->write      = r8168dp_2_mdio_write;
3590                 ops->read       = r8168dp_2_mdio_read;
3591                 break;
3592         default:
3593                 ops->write      = r8169_mdio_write;
3594                 ops->read       = r8169_mdio_read;
3595                 break;
3596         }
3597 }
3598
3599 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3600 {
3601         void __iomem *ioaddr = tp->mmio_addr;
3602
3603         switch (tp->mac_version) {
3604         case RTL_GIGA_MAC_VER_29:
3605         case RTL_GIGA_MAC_VER_30:
3606         case RTL_GIGA_MAC_VER_32:
3607         case RTL_GIGA_MAC_VER_33:
3608         case RTL_GIGA_MAC_VER_34:
3609         case RTL_GIGA_MAC_VER_37:
3610         case RTL_GIGA_MAC_VER_38:
3611                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3612                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3613                 break;
3614         default:
3615                 break;
3616         }
3617 }
3618
3619 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3620 {
3621         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3622                 return false;
3623
3624         rtl_writephy(tp, 0x1f, 0x0000);
3625         rtl_writephy(tp, MII_BMCR, 0x0000);
3626
3627         rtl_wol_suspend_quirk(tp);
3628
3629         return true;
3630 }
3631
3632 static void r810x_phy_power_down(struct rtl8169_private *tp)
3633 {
3634         rtl_writephy(tp, 0x1f, 0x0000);
3635         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3636 }
3637
3638 static void r810x_phy_power_up(struct rtl8169_private *tp)
3639 {
3640         rtl_writephy(tp, 0x1f, 0x0000);
3641         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3642 }
3643
3644 static void r810x_pll_power_down(struct rtl8169_private *tp)
3645 {
3646         void __iomem *ioaddr = tp->mmio_addr;
3647
3648         if (rtl_wol_pll_power_down(tp))
3649                 return;
3650
3651         r810x_phy_power_down(tp);
3652
3653         switch (tp->mac_version) {
3654         case RTL_GIGA_MAC_VER_07:
3655         case RTL_GIGA_MAC_VER_08:
3656         case RTL_GIGA_MAC_VER_09:
3657         case RTL_GIGA_MAC_VER_10:
3658         case RTL_GIGA_MAC_VER_13:
3659         case RTL_GIGA_MAC_VER_16:
3660                 break;
3661         default:
3662                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3663                 break;
3664         }
3665 }
3666
3667 static void r810x_pll_power_up(struct rtl8169_private *tp)
3668 {
3669         void __iomem *ioaddr = tp->mmio_addr;
3670
3671         r810x_phy_power_up(tp);
3672
3673         switch (tp->mac_version) {
3674         case RTL_GIGA_MAC_VER_07:
3675         case RTL_GIGA_MAC_VER_08:
3676         case RTL_GIGA_MAC_VER_09:
3677         case RTL_GIGA_MAC_VER_10:
3678         case RTL_GIGA_MAC_VER_13:
3679         case RTL_GIGA_MAC_VER_16:
3680                 break;
3681         default:
3682                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3683                 break;
3684         }
3685 }
3686
3687 static void r8168_phy_power_up(struct rtl8169_private *tp)
3688 {
3689         rtl_writephy(tp, 0x1f, 0x0000);
3690         switch (tp->mac_version) {
3691         case RTL_GIGA_MAC_VER_11:
3692         case RTL_GIGA_MAC_VER_12:
3693         case RTL_GIGA_MAC_VER_17:
3694         case RTL_GIGA_MAC_VER_18:
3695         case RTL_GIGA_MAC_VER_19:
3696         case RTL_GIGA_MAC_VER_20:
3697         case RTL_GIGA_MAC_VER_21:
3698         case RTL_GIGA_MAC_VER_22:
3699         case RTL_GIGA_MAC_VER_23:
3700         case RTL_GIGA_MAC_VER_24:
3701         case RTL_GIGA_MAC_VER_25:
3702         case RTL_GIGA_MAC_VER_26:
3703         case RTL_GIGA_MAC_VER_27:
3704         case RTL_GIGA_MAC_VER_28:
3705         case RTL_GIGA_MAC_VER_31:
3706                 rtl_writephy(tp, 0x0e, 0x0000);
3707                 break;
3708         default:
3709                 break;
3710         }
3711         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3712 }
3713
3714 static void r8168_phy_power_down(struct rtl8169_private *tp)
3715 {
3716         rtl_writephy(tp, 0x1f, 0x0000);
3717         switch (tp->mac_version) {
3718         case RTL_GIGA_MAC_VER_32:
3719         case RTL_GIGA_MAC_VER_33:
3720                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3721                 break;
3722
3723         case RTL_GIGA_MAC_VER_11:
3724         case RTL_GIGA_MAC_VER_12:
3725         case RTL_GIGA_MAC_VER_17:
3726         case RTL_GIGA_MAC_VER_18:
3727         case RTL_GIGA_MAC_VER_19:
3728         case RTL_GIGA_MAC_VER_20:
3729         case RTL_GIGA_MAC_VER_21:
3730         case RTL_GIGA_MAC_VER_22:
3731         case RTL_GIGA_MAC_VER_23:
3732         case RTL_GIGA_MAC_VER_24:
3733         case RTL_GIGA_MAC_VER_25:
3734         case RTL_GIGA_MAC_VER_26:
3735         case RTL_GIGA_MAC_VER_27:
3736         case RTL_GIGA_MAC_VER_28:
3737         case RTL_GIGA_MAC_VER_31:
3738                 rtl_writephy(tp, 0x0e, 0x0200);
3739         default:
3740                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3741                 break;
3742         }
3743 }
3744
3745 static void r8168_pll_power_down(struct rtl8169_private *tp)
3746 {
3747         void __iomem *ioaddr = tp->mmio_addr;
3748
3749         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3750              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3751              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3752             r8168dp_check_dash(tp)) {
3753                 return;
3754         }
3755
3756         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3757              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3758             (RTL_R16(CPlusCmd) & ASF)) {
3759                 return;
3760         }
3761
3762         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3763             tp->mac_version == RTL_GIGA_MAC_VER_33)
3764                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3765
3766         if (rtl_wol_pll_power_down(tp))
3767                 return;
3768
3769         r8168_phy_power_down(tp);
3770
3771         switch (tp->mac_version) {
3772         case RTL_GIGA_MAC_VER_25:
3773         case RTL_GIGA_MAC_VER_26:
3774         case RTL_GIGA_MAC_VER_27:
3775         case RTL_GIGA_MAC_VER_28:
3776         case RTL_GIGA_MAC_VER_31:
3777         case RTL_GIGA_MAC_VER_32:
3778         case RTL_GIGA_MAC_VER_33:
3779                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3780                 break;
3781         }
3782 }
3783
3784 static void r8168_pll_power_up(struct rtl8169_private *tp)
3785 {
3786         void __iomem *ioaddr = tp->mmio_addr;
3787
3788         switch (tp->mac_version) {
3789         case RTL_GIGA_MAC_VER_25:
3790         case RTL_GIGA_MAC_VER_26:
3791         case RTL_GIGA_MAC_VER_27:
3792         case RTL_GIGA_MAC_VER_28:
3793         case RTL_GIGA_MAC_VER_31:
3794         case RTL_GIGA_MAC_VER_32:
3795         case RTL_GIGA_MAC_VER_33:
3796                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3797                 break;
3798         }
3799
3800         r8168_phy_power_up(tp);
3801 }
3802
3803 static void rtl_generic_op(struct rtl8169_private *tp,
3804                            void (*op)(struct rtl8169_private *))
3805 {
3806         if (op)
3807                 op(tp);
3808 }
3809
3810 static void rtl_pll_power_down(struct rtl8169_private *tp)
3811 {
3812         rtl_generic_op(tp, tp->pll_power_ops.down);
3813 }
3814
3815 static void rtl_pll_power_up(struct rtl8169_private *tp)
3816 {
3817         rtl_generic_op(tp, tp->pll_power_ops.up);
3818 }
3819
3820 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3821 {
3822         struct pll_power_ops *ops = &tp->pll_power_ops;
3823
3824         switch (tp->mac_version) {
3825         case RTL_GIGA_MAC_VER_07:
3826         case RTL_GIGA_MAC_VER_08:
3827         case RTL_GIGA_MAC_VER_09:
3828         case RTL_GIGA_MAC_VER_10:
3829         case RTL_GIGA_MAC_VER_16:
3830         case RTL_GIGA_MAC_VER_29:
3831         case RTL_GIGA_MAC_VER_30:
3832         case RTL_GIGA_MAC_VER_37:
3833                 ops->down       = r810x_pll_power_down;
3834                 ops->up         = r810x_pll_power_up;
3835                 break;
3836
3837         case RTL_GIGA_MAC_VER_11:
3838         case RTL_GIGA_MAC_VER_12:
3839         case RTL_GIGA_MAC_VER_17:
3840         case RTL_GIGA_MAC_VER_18:
3841         case RTL_GIGA_MAC_VER_19:
3842         case RTL_GIGA_MAC_VER_20:
3843         case RTL_GIGA_MAC_VER_21:
3844         case RTL_GIGA_MAC_VER_22:
3845         case RTL_GIGA_MAC_VER_23:
3846         case RTL_GIGA_MAC_VER_24:
3847         case RTL_GIGA_MAC_VER_25:
3848         case RTL_GIGA_MAC_VER_26:
3849         case RTL_GIGA_MAC_VER_27:
3850         case RTL_GIGA_MAC_VER_28:
3851         case RTL_GIGA_MAC_VER_31:
3852         case RTL_GIGA_MAC_VER_32:
3853         case RTL_GIGA_MAC_VER_33:
3854         case RTL_GIGA_MAC_VER_34:
3855         case RTL_GIGA_MAC_VER_35:
3856         case RTL_GIGA_MAC_VER_36:
3857         case RTL_GIGA_MAC_VER_38:
3858                 ops->down       = r8168_pll_power_down;
3859                 ops->up         = r8168_pll_power_up;
3860                 break;
3861
3862         default:
3863                 ops->down       = NULL;
3864                 ops->up         = NULL;
3865                 break;
3866         }
3867 }
3868
3869 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3870 {
3871         void __iomem *ioaddr = tp->mmio_addr;
3872
3873         switch (tp->mac_version) {
3874         case RTL_GIGA_MAC_VER_01:
3875         case RTL_GIGA_MAC_VER_02:
3876         case RTL_GIGA_MAC_VER_03:
3877         case RTL_GIGA_MAC_VER_04:
3878         case RTL_GIGA_MAC_VER_05:
3879         case RTL_GIGA_MAC_VER_06:
3880         case RTL_GIGA_MAC_VER_10:
3881         case RTL_GIGA_MAC_VER_11:
3882         case RTL_GIGA_MAC_VER_12:
3883         case RTL_GIGA_MAC_VER_13:
3884         case RTL_GIGA_MAC_VER_14:
3885         case RTL_GIGA_MAC_VER_15:
3886         case RTL_GIGA_MAC_VER_16:
3887         case RTL_GIGA_MAC_VER_17:
3888                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3889                 break;
3890         case RTL_GIGA_MAC_VER_18:
3891         case RTL_GIGA_MAC_VER_19:
3892         case RTL_GIGA_MAC_VER_20:
3893         case RTL_GIGA_MAC_VER_21:
3894         case RTL_GIGA_MAC_VER_22:
3895         case RTL_GIGA_MAC_VER_23:
3896         case RTL_GIGA_MAC_VER_24:
3897         case RTL_GIGA_MAC_VER_34:
3898                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3899                 break;
3900         default:
3901                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3902                 break;
3903         }
3904 }
3905
3906 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3907 {
3908         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3909 }
3910
3911 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3912 {
3913         void __iomem *ioaddr = tp->mmio_addr;
3914
3915         RTL_W8(Cfg9346, Cfg9346_Unlock);
3916         rtl_generic_op(tp, tp->jumbo_ops.enable);
3917         RTL_W8(Cfg9346, Cfg9346_Lock);
3918 }
3919
3920 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3921 {
3922         void __iomem *ioaddr = tp->mmio_addr;
3923
3924         RTL_W8(Cfg9346, Cfg9346_Unlock);
3925         rtl_generic_op(tp, tp->jumbo_ops.disable);
3926         RTL_W8(Cfg9346, Cfg9346_Lock);
3927 }
3928
3929 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3930 {
3931         void __iomem *ioaddr = tp->mmio_addr;
3932
3933         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3934         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3935         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3936 }
3937
3938 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3939 {
3940         void __iomem *ioaddr = tp->mmio_addr;
3941
3942         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3943         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3944         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3945 }
3946
3947 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3948 {
3949         void __iomem *ioaddr = tp->mmio_addr;
3950
3951         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3952 }
3953
3954 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3955 {
3956         void __iomem *ioaddr = tp->mmio_addr;
3957
3958         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3959 }
3960
3961 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3962 {
3963         void __iomem *ioaddr = tp->mmio_addr;
3964
3965         RTL_W8(MaxTxPacketSize, 0x3f);
3966         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3967         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3968         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3969 }
3970
3971 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3972 {
3973         void __iomem *ioaddr = tp->mmio_addr;
3974
3975         RTL_W8(MaxTxPacketSize, 0x0c);
3976         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3977         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3978         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3979 }
3980
3981 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3982 {
3983         rtl_tx_performance_tweak(tp->pci_dev,
3984                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3985 }
3986
3987 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3988 {
3989         rtl_tx_performance_tweak(tp->pci_dev,
3990                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3991 }
3992
3993 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3994 {
3995         void __iomem *ioaddr = tp->mmio_addr;
3996
3997         r8168b_0_hw_jumbo_enable(tp);
3998
3999         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4000 }
4001
4002 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4003 {
4004         void __iomem *ioaddr = tp->mmio_addr;
4005
4006         r8168b_0_hw_jumbo_disable(tp);
4007
4008         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4009 }
4010
4011 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
4012 {
4013         struct jumbo_ops *ops = &tp->jumbo_ops;
4014
4015         switch (tp->mac_version) {
4016         case RTL_GIGA_MAC_VER_11:
4017                 ops->disable    = r8168b_0_hw_jumbo_disable;
4018                 ops->enable     = r8168b_0_hw_jumbo_enable;
4019                 break;
4020         case RTL_GIGA_MAC_VER_12:
4021         case RTL_GIGA_MAC_VER_17:
4022                 ops->disable    = r8168b_1_hw_jumbo_disable;
4023                 ops->enable     = r8168b_1_hw_jumbo_enable;
4024                 break;
4025         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4026         case RTL_GIGA_MAC_VER_19:
4027         case RTL_GIGA_MAC_VER_20:
4028         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4029         case RTL_GIGA_MAC_VER_22:
4030         case RTL_GIGA_MAC_VER_23:
4031         case RTL_GIGA_MAC_VER_24:
4032         case RTL_GIGA_MAC_VER_25:
4033         case RTL_GIGA_MAC_VER_26:
4034                 ops->disable    = r8168c_hw_jumbo_disable;
4035                 ops->enable     = r8168c_hw_jumbo_enable;
4036                 break;
4037         case RTL_GIGA_MAC_VER_27:
4038         case RTL_GIGA_MAC_VER_28:
4039                 ops->disable    = r8168dp_hw_jumbo_disable;
4040                 ops->enable     = r8168dp_hw_jumbo_enable;
4041                 break;
4042         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4043         case RTL_GIGA_MAC_VER_32:
4044         case RTL_GIGA_MAC_VER_33:
4045         case RTL_GIGA_MAC_VER_34:
4046                 ops->disable    = r8168e_hw_jumbo_disable;
4047                 ops->enable     = r8168e_hw_jumbo_enable;
4048                 break;
4049
4050         /*
4051          * No action needed for jumbo frames with 8169.
4052          * No jumbo for 810x at all.
4053          */
4054         default:
4055                 ops->disable    = NULL;
4056                 ops->enable     = NULL;
4057                 break;
4058         }
4059 }
4060
4061 static void rtl_hw_reset(struct rtl8169_private *tp)
4062 {
4063         void __iomem *ioaddr = tp->mmio_addr;
4064         int i;
4065
4066         /* Soft reset the chip. */
4067         RTL_W8(ChipCmd, CmdReset);
4068
4069         /* Check that the chip has finished the reset. */
4070         for (i = 0; i < 100; i++) {
4071                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
4072                         break;
4073                 udelay(100);
4074         }
4075 }
4076
4077 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4078 {
4079         struct rtl_fw *rtl_fw;
4080         const char *name;
4081         int rc = -ENOMEM;
4082
4083         name = rtl_lookup_firmware_name(tp);
4084         if (!name)
4085                 goto out_no_firmware;
4086
4087         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4088         if (!rtl_fw)
4089                 goto err_warn;
4090
4091         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4092         if (rc < 0)
4093                 goto err_free;
4094
4095         rc = rtl_check_firmware(tp, rtl_fw);
4096         if (rc < 0)
4097                 goto err_release_firmware;
4098
4099         tp->rtl_fw = rtl_fw;
4100 out:
4101         return;
4102
4103 err_release_firmware:
4104         release_firmware(rtl_fw->fw);
4105 err_free:
4106         kfree(rtl_fw);
4107 err_warn:
4108         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4109                    name, rc);
4110 out_no_firmware:
4111         tp->rtl_fw = NULL;
4112         goto out;
4113 }
4114
4115 static void rtl_request_firmware(struct rtl8169_private *tp)
4116 {
4117         if (IS_ERR(tp->rtl_fw))
4118                 rtl_request_uncached_firmware(tp);
4119 }
4120
4121 static void rtl_rx_close(struct rtl8169_private *tp)
4122 {
4123         void __iomem *ioaddr = tp->mmio_addr;
4124
4125         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4126 }
4127
4128 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4129 {
4130         void __iomem *ioaddr = tp->mmio_addr;
4131
4132         /* Disable interrupts */
4133         rtl8169_irq_mask_and_ack(tp);
4134
4135         rtl_rx_close(tp);
4136
4137         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4138             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4139             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4140                 while (RTL_R8(TxPoll) & NPQ)
4141                         udelay(20);
4142         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4143                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4144                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4145                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4146                    tp->mac_version == RTL_GIGA_MAC_VER_38) {
4147                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4148                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4149                         udelay(100);
4150         } else {
4151                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4152                 udelay(100);
4153         }
4154
4155         rtl_hw_reset(tp);
4156 }
4157
4158 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4159 {
4160         void __iomem *ioaddr = tp->mmio_addr;
4161
4162         /* Set DMA burst size and Interframe Gap Time */
4163         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4164                 (InterFrameGap << TxInterFrameGapShift));
4165 }
4166
4167 static void rtl_hw_start(struct net_device *dev)
4168 {
4169         struct rtl8169_private *tp = netdev_priv(dev);
4170
4171         tp->hw_start(dev);
4172
4173         rtl_irq_enable_all(tp);
4174 }
4175
4176 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4177                                          void __iomem *ioaddr)
4178 {
4179         /*
4180          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4181          * register to be written before TxDescAddrLow to work.
4182          * Switching from MMIO to I/O access fixes the issue as well.
4183          */
4184         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4185         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4186         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4187         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4188 }
4189
4190 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4191 {
4192         u16 cmd;
4193
4194         cmd = RTL_R16(CPlusCmd);
4195         RTL_W16(CPlusCmd, cmd);
4196         return cmd;
4197 }
4198
4199 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4200 {
4201         /* Low hurts. Let's disable the filtering. */
4202         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4203 }
4204
4205 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4206 {
4207         static const struct rtl_cfg2_info {
4208                 u32 mac_version;
4209                 u32 clk;
4210                 u32 val;
4211         } cfg2_info [] = {
4212                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4213                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4214                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4215                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4216         };
4217         const struct rtl_cfg2_info *p = cfg2_info;
4218         unsigned int i;
4219         u32 clk;
4220
4221         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4222         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4223                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4224                         RTL_W32(0x7c, p->val);
4225                         break;
4226                 }
4227         }
4228 }
4229
4230 static void rtl_set_rx_mode(struct net_device *dev)
4231 {
4232         struct rtl8169_private *tp = netdev_priv(dev);
4233         void __iomem *ioaddr = tp->mmio_addr;
4234         u32 mc_filter[2];       /* Multicast hash filter */
4235         int rx_mode;
4236         u32 tmp = 0;
4237
4238         if (dev->flags & IFF_PROMISC) {
4239                 /* Unconditionally log net taps. */
4240                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4241                 rx_mode =
4242                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4243                     AcceptAllPhys;
4244                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4245         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4246                    (dev->flags & IFF_ALLMULTI)) {
4247                 /* Too many to filter perfectly -- accept all multicasts. */
4248                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4249                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4250         } else {
4251                 struct netdev_hw_addr *ha;
4252
4253                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4254                 mc_filter[1] = mc_filter[0] = 0;
4255                 netdev_for_each_mc_addr(ha, dev) {
4256                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4257                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4258                         rx_mode |= AcceptMulticast;
4259                 }
4260         }
4261
4262         if (dev->features & NETIF_F_RXALL)
4263                 rx_mode |= (AcceptErr | AcceptRunt);
4264
4265         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4266
4267         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4268                 u32 data = mc_filter[0];
4269
4270                 mc_filter[0] = swab32(mc_filter[1]);
4271                 mc_filter[1] = swab32(data);
4272         }
4273
4274         RTL_W32(MAR0 + 4, mc_filter[1]);
4275         RTL_W32(MAR0 + 0, mc_filter[0]);
4276
4277         RTL_W32(RxConfig, tmp);
4278 }
4279
4280 static void rtl_hw_start_8169(struct net_device *dev)
4281 {
4282         struct rtl8169_private *tp = netdev_priv(dev);
4283         void __iomem *ioaddr = tp->mmio_addr;
4284         struct pci_dev *pdev = tp->pci_dev;
4285
4286         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4287                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4288                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4289         }
4290
4291         RTL_W8(Cfg9346, Cfg9346_Unlock);
4292         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4293             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4294             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4295             tp->mac_version == RTL_GIGA_MAC_VER_04)
4296                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4297
4298         rtl_init_rxcfg(tp);
4299
4300         RTL_W8(EarlyTxThres, NoEarlyTx);
4301
4302         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4303
4304         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4305             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4306             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4307             tp->mac_version == RTL_GIGA_MAC_VER_04)
4308                 rtl_set_rx_tx_config_registers(tp);
4309
4310         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4311
4312         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4313             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4314                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4315                         "Bit-3 and bit-14 MUST be 1\n");
4316                 tp->cp_cmd |= (1 << 14);
4317         }
4318
4319         RTL_W16(CPlusCmd, tp->cp_cmd);
4320
4321         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4322
4323         /*
4324          * Undocumented corner. Supposedly:
4325          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4326          */
4327         RTL_W16(IntrMitigate, 0x0000);
4328
4329         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4330
4331         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4332             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4333             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4334             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4335                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4336                 rtl_set_rx_tx_config_registers(tp);
4337         }
4338
4339         RTL_W8(Cfg9346, Cfg9346_Lock);
4340
4341         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4342         RTL_R8(IntrMask);
4343
4344         RTL_W32(RxMissed, 0);
4345
4346         rtl_set_rx_mode(dev);
4347
4348         /* no early-rx interrupts */
4349         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4350 }
4351
4352 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4353 {
4354         if (tp->csi_ops.write)
4355                 tp->csi_ops.write(tp->mmio_addr, addr, value);
4356 }
4357
4358 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4359 {
4360         if (tp->csi_ops.read)
4361                 return tp->csi_ops.read(tp->mmio_addr, addr);
4362         else
4363                 return ~0;
4364 }
4365
4366 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4367 {
4368         u32 csi;
4369
4370         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4371         rtl_csi_write(tp, 0x070c, csi | bits);
4372 }
4373
4374 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4375 {
4376         rtl_csi_access_enable(tp, 0x17000000);
4377 }
4378
4379 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4380 {
4381         rtl_csi_access_enable(tp, 0x27000000);
4382 }
4383
4384 static void r8169_csi_write(void __iomem *ioaddr, int addr, int value)
4385 {
4386         unsigned int i;
4387
4388         RTL_W32(CSIDR, value);
4389         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4390                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4391
4392         for (i = 0; i < 100; i++) {
4393                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
4394                         break;
4395                 udelay(10);
4396         }
4397 }
4398
4399 static u32 r8169_csi_read(void __iomem *ioaddr, int addr)
4400 {
4401         u32 value = ~0x00;
4402         unsigned int i;
4403
4404         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4405                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4406
4407         for (i = 0; i < 100; i++) {
4408                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
4409                         value = RTL_R32(CSIDR);
4410                         break;
4411                 }
4412                 udelay(10);
4413         }
4414
4415         return value;
4416 }
4417
4418 static void r8402_csi_write(void __iomem *ioaddr, int addr, int value)
4419 {
4420         unsigned int i;
4421
4422         RTL_W32(CSIDR, value);
4423         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4424                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4425                 CSIAR_FUNC_NIC);
4426
4427         for (i = 0; i < 100; i++) {
4428                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
4429                         break;
4430                 udelay(10);
4431         }
4432 }
4433
4434 static u32 r8402_csi_read(void __iomem *ioaddr, int addr)
4435 {
4436         u32 value = ~0x00;
4437         unsigned int i;
4438
4439         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4440                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4441
4442         for (i = 0; i < 100; i++) {
4443                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
4444                         value = RTL_R32(CSIDR);
4445                         break;
4446                 }
4447                 udelay(10);
4448         }
4449
4450         return value;
4451 }
4452
4453 static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
4454 {
4455         struct csi_ops *ops = &tp->csi_ops;
4456
4457         switch (tp->mac_version) {
4458         case RTL_GIGA_MAC_VER_01:
4459         case RTL_GIGA_MAC_VER_02:
4460         case RTL_GIGA_MAC_VER_03:
4461         case RTL_GIGA_MAC_VER_04:
4462         case RTL_GIGA_MAC_VER_05:
4463         case RTL_GIGA_MAC_VER_06:
4464         case RTL_GIGA_MAC_VER_10:
4465         case RTL_GIGA_MAC_VER_11:
4466         case RTL_GIGA_MAC_VER_12:
4467         case RTL_GIGA_MAC_VER_13:
4468         case RTL_GIGA_MAC_VER_14:
4469         case RTL_GIGA_MAC_VER_15:
4470         case RTL_GIGA_MAC_VER_16:
4471         case RTL_GIGA_MAC_VER_17:
4472                 ops->write      = NULL;
4473                 ops->read       = NULL;
4474                 break;
4475
4476         case RTL_GIGA_MAC_VER_37:
4477         case RTL_GIGA_MAC_VER_38:
4478                 ops->write      = r8402_csi_write;
4479                 ops->read       = r8402_csi_read;
4480                 break;
4481
4482         default:
4483                 ops->write      = r8169_csi_write;
4484                 ops->read       = r8169_csi_read;
4485                 break;
4486         }
4487 }
4488
4489 struct ephy_info {
4490         unsigned int offset;
4491         u16 mask;
4492         u16 bits;
4493 };
4494
4495 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4496 {
4497         u16 w;
4498
4499         while (len-- > 0) {
4500                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4501                 rtl_ephy_write(ioaddr, e->offset, w);
4502                 e++;
4503         }
4504 }
4505
4506 static void rtl_disable_clock_request(struct pci_dev *pdev)
4507 {
4508         int cap = pci_pcie_cap(pdev);
4509
4510         if (cap) {
4511                 u16 ctl;
4512
4513                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4514                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4515                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4516         }
4517 }
4518
4519 static void rtl_enable_clock_request(struct pci_dev *pdev)
4520 {
4521         int cap = pci_pcie_cap(pdev);
4522
4523         if (cap) {
4524                 u16 ctl;
4525
4526                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4527                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4528                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4529         }
4530 }
4531
4532 #define R8168_CPCMD_QUIRK_MASK (\
4533         EnableBist | \
4534         Mac_dbgo_oe | \
4535         Force_half_dup | \
4536         Force_rxflow_en | \
4537         Force_txflow_en | \
4538         Cxpl_dbg_sel | \
4539         ASF | \
4540         PktCntrDisable | \
4541         Mac_dbgo_sel)
4542
4543 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4544 {
4545         void __iomem *ioaddr = tp->mmio_addr;
4546         struct pci_dev *pdev = tp->pci_dev;
4547
4548         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4549
4550         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4551
4552         rtl_tx_performance_tweak(pdev,
4553                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4554 }
4555
4556 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4557 {
4558         void __iomem *ioaddr = tp->mmio_addr;
4559
4560         rtl_hw_start_8168bb(tp);
4561
4562         RTL_W8(MaxTxPacketSize, TxPacketMax);
4563
4564         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4565 }
4566
4567 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4568 {
4569         void __iomem *ioaddr = tp->mmio_addr;
4570         struct pci_dev *pdev = tp->pci_dev;
4571
4572         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4573
4574         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4575
4576         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4577
4578         rtl_disable_clock_request(pdev);
4579
4580         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4581 }
4582
4583 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4584 {
4585         void __iomem *ioaddr = tp->mmio_addr;
4586         static const struct ephy_info e_info_8168cp[] = {
4587                 { 0x01, 0,      0x0001 },
4588                 { 0x02, 0x0800, 0x1000 },
4589                 { 0x03, 0,      0x0042 },
4590                 { 0x06, 0x0080, 0x0000 },
4591                 { 0x07, 0,      0x2000 }
4592         };
4593
4594         rtl_csi_access_enable_2(tp);
4595
4596         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4597
4598         __rtl_hw_start_8168cp(tp);
4599 }
4600
4601 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4602 {
4603         void __iomem *ioaddr = tp->mmio_addr;
4604         struct pci_dev *pdev = tp->pci_dev;
4605
4606         rtl_csi_access_enable_2(tp);
4607
4608         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4609
4610         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4611
4612         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4613 }
4614
4615 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4616 {
4617         void __iomem *ioaddr = tp->mmio_addr;
4618         struct pci_dev *pdev = tp->pci_dev;
4619
4620         rtl_csi_access_enable_2(tp);
4621
4622         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4623
4624         /* Magic. */
4625         RTL_W8(DBG_REG, 0x20);
4626
4627         RTL_W8(MaxTxPacketSize, TxPacketMax);
4628
4629         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4630
4631         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4632 }
4633
4634 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4635 {
4636         void __iomem *ioaddr = tp->mmio_addr;
4637         static const struct ephy_info e_info_8168c_1[] = {
4638                 { 0x02, 0x0800, 0x1000 },
4639                 { 0x03, 0,      0x0002 },
4640                 { 0x06, 0x0080, 0x0000 }
4641         };
4642
4643         rtl_csi_access_enable_2(tp);
4644
4645         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4646
4647         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4648
4649         __rtl_hw_start_8168cp(tp);
4650 }
4651
4652 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4653 {
4654         void __iomem *ioaddr = tp->mmio_addr;
4655         static const struct ephy_info e_info_8168c_2[] = {
4656                 { 0x01, 0,      0x0001 },
4657                 { 0x03, 0x0400, 0x0220 }
4658         };
4659
4660         rtl_csi_access_enable_2(tp);
4661
4662         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4663
4664         __rtl_hw_start_8168cp(tp);
4665 }
4666
4667 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4668 {
4669         rtl_hw_start_8168c_2(tp);
4670 }
4671
4672 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4673 {
4674         rtl_csi_access_enable_2(tp);
4675
4676         __rtl_hw_start_8168cp(tp);
4677 }
4678
4679 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4680 {
4681         void __iomem *ioaddr = tp->mmio_addr;
4682         struct pci_dev *pdev = tp->pci_dev;
4683
4684         rtl_csi_access_enable_2(tp);
4685
4686         rtl_disable_clock_request(pdev);
4687
4688         RTL_W8(MaxTxPacketSize, TxPacketMax);
4689
4690         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4691
4692         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4693 }
4694
4695 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4696 {
4697         void __iomem *ioaddr = tp->mmio_addr;
4698         struct pci_dev *pdev = tp->pci_dev;
4699
4700         rtl_csi_access_enable_1(tp);
4701
4702         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4703
4704         RTL_W8(MaxTxPacketSize, TxPacketMax);
4705
4706         rtl_disable_clock_request(pdev);
4707 }
4708
4709 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4710 {
4711         void __iomem *ioaddr = tp->mmio_addr;
4712         struct pci_dev *pdev = tp->pci_dev;
4713         static const struct ephy_info e_info_8168d_4[] = {
4714                 { 0x0b, ~0,     0x48 },
4715                 { 0x19, 0x20,   0x50 },
4716                 { 0x0c, ~0,     0x20 }
4717         };
4718         int i;
4719
4720         rtl_csi_access_enable_1(tp);
4721
4722         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4723
4724         RTL_W8(MaxTxPacketSize, TxPacketMax);
4725
4726         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4727                 const struct ephy_info *e = e_info_8168d_4 + i;
4728                 u16 w;
4729
4730                 w = rtl_ephy_read(ioaddr, e->offset);
4731                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4732         }
4733
4734         rtl_enable_clock_request(pdev);
4735 }
4736
4737 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4738 {
4739         void __iomem *ioaddr = tp->mmio_addr;
4740         struct pci_dev *pdev = tp->pci_dev;
4741         static const struct ephy_info e_info_8168e_1[] = {
4742                 { 0x00, 0x0200, 0x0100 },
4743                 { 0x00, 0x0000, 0x0004 },
4744                 { 0x06, 0x0002, 0x0001 },
4745                 { 0x06, 0x0000, 0x0030 },
4746                 { 0x07, 0x0000, 0x2000 },
4747                 { 0x00, 0x0000, 0x0020 },
4748                 { 0x03, 0x5800, 0x2000 },
4749                 { 0x03, 0x0000, 0x0001 },
4750                 { 0x01, 0x0800, 0x1000 },
4751                 { 0x07, 0x0000, 0x4000 },
4752                 { 0x1e, 0x0000, 0x2000 },
4753                 { 0x19, 0xffff, 0xfe6c },
4754                 { 0x0a, 0x0000, 0x0040 }
4755         };
4756
4757         rtl_csi_access_enable_2(tp);
4758
4759         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4760
4761         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4762
4763         RTL_W8(MaxTxPacketSize, TxPacketMax);
4764
4765         rtl_disable_clock_request(pdev);
4766
4767         /* Reset tx FIFO pointer */
4768         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4769         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4770
4771         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4772 }
4773
4774 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4775 {
4776         void __iomem *ioaddr = tp->mmio_addr;
4777         struct pci_dev *pdev = tp->pci_dev;
4778         static const struct ephy_info e_info_8168e_2[] = {
4779                 { 0x09, 0x0000, 0x0080 },
4780                 { 0x19, 0x0000, 0x0224 }
4781         };
4782
4783         rtl_csi_access_enable_1(tp);
4784
4785         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4786
4787         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4788
4789         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4790         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4791         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4792         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4793         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4794         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4795         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4796         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4797                      ERIAR_EXGMAC);
4798
4799         RTL_W8(MaxTxPacketSize, EarlySize);
4800
4801         rtl_disable_clock_request(pdev);
4802
4803         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4804         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4805
4806         /* Adjust EEE LED frequency */
4807         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4808
4809         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4810         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4811         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4812 }
4813
4814 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4815 {
4816         void __iomem *ioaddr = tp->mmio_addr;
4817         struct pci_dev *pdev = tp->pci_dev;
4818
4819         rtl_csi_access_enable_2(tp);
4820
4821         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4822
4823         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4824         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4825         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4826         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4827         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4828         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4829         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4830         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4831         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4832         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4833
4834         RTL_W8(MaxTxPacketSize, EarlySize);
4835
4836         rtl_disable_clock_request(pdev);
4837
4838         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4839         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4840         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4841         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4842         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4843 }
4844
4845 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4846 {
4847         void __iomem *ioaddr = tp->mmio_addr;
4848         static const struct ephy_info e_info_8168f_1[] = {
4849                 { 0x06, 0x00c0, 0x0020 },
4850                 { 0x08, 0x0001, 0x0002 },
4851                 { 0x09, 0x0000, 0x0080 },
4852                 { 0x19, 0x0000, 0x0224 }
4853         };
4854
4855         rtl_hw_start_8168f(tp);
4856
4857         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4858
4859         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4860                      ERIAR_EXGMAC);
4861
4862         /* Adjust EEE LED frequency */
4863         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4864 }
4865
4866 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4867 {
4868         void __iomem *ioaddr = tp->mmio_addr;
4869         static const struct ephy_info e_info_8168f_1[] = {
4870                 { 0x06, 0x00c0, 0x0020 },
4871                 { 0x0f, 0xffff, 0x5200 },
4872                 { 0x1e, 0x0000, 0x4000 },
4873                 { 0x19, 0x0000, 0x0224 }
4874         };
4875
4876         rtl_hw_start_8168f(tp);
4877
4878         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4879
4880         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000,
4881                      ERIAR_EXGMAC);
4882 }
4883
4884 static void rtl_hw_start_8168(struct net_device *dev)
4885 {
4886         struct rtl8169_private *tp = netdev_priv(dev);
4887         void __iomem *ioaddr = tp->mmio_addr;
4888
4889         RTL_W8(Cfg9346, Cfg9346_Unlock);
4890
4891         RTL_W8(MaxTxPacketSize, TxPacketMax);
4892
4893         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4894
4895         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4896
4897         RTL_W16(CPlusCmd, tp->cp_cmd);
4898
4899         RTL_W16(IntrMitigate, 0x5151);
4900
4901         /* Work around for RxFIFO overflow. */
4902         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4903                 tp->event_slow |= RxFIFOOver | PCSTimeout;
4904                 tp->event_slow &= ~RxOverflow;
4905         }
4906
4907         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4908
4909         rtl_set_rx_mode(dev);
4910
4911         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4912                 (InterFrameGap << TxInterFrameGapShift));
4913
4914         RTL_R8(IntrMask);
4915
4916         switch (tp->mac_version) {
4917         case RTL_GIGA_MAC_VER_11:
4918                 rtl_hw_start_8168bb(tp);
4919                 break;
4920
4921         case RTL_GIGA_MAC_VER_12:
4922         case RTL_GIGA_MAC_VER_17:
4923                 rtl_hw_start_8168bef(tp);
4924                 break;
4925
4926         case RTL_GIGA_MAC_VER_18:
4927                 rtl_hw_start_8168cp_1(tp);
4928                 break;
4929
4930         case RTL_GIGA_MAC_VER_19:
4931                 rtl_hw_start_8168c_1(tp);
4932                 break;
4933
4934         case RTL_GIGA_MAC_VER_20:
4935                 rtl_hw_start_8168c_2(tp);
4936                 break;
4937
4938         case RTL_GIGA_MAC_VER_21:
4939                 rtl_hw_start_8168c_3(tp);
4940                 break;
4941
4942         case RTL_GIGA_MAC_VER_22:
4943                 rtl_hw_start_8168c_4(tp);
4944                 break;
4945
4946         case RTL_GIGA_MAC_VER_23:
4947                 rtl_hw_start_8168cp_2(tp);
4948                 break;
4949
4950         case RTL_GIGA_MAC_VER_24:
4951                 rtl_hw_start_8168cp_3(tp);
4952                 break;
4953
4954         case RTL_GIGA_MAC_VER_25:
4955         case RTL_GIGA_MAC_VER_26:
4956         case RTL_GIGA_MAC_VER_27:
4957                 rtl_hw_start_8168d(tp);
4958                 break;
4959
4960         case RTL_GIGA_MAC_VER_28:
4961                 rtl_hw_start_8168d_4(tp);
4962                 break;
4963
4964         case RTL_GIGA_MAC_VER_31:
4965                 rtl_hw_start_8168dp(tp);
4966                 break;
4967
4968         case RTL_GIGA_MAC_VER_32:
4969         case RTL_GIGA_MAC_VER_33:
4970                 rtl_hw_start_8168e_1(tp);
4971                 break;
4972         case RTL_GIGA_MAC_VER_34:
4973                 rtl_hw_start_8168e_2(tp);
4974                 break;
4975
4976         case RTL_GIGA_MAC_VER_35:
4977         case RTL_GIGA_MAC_VER_36:
4978                 rtl_hw_start_8168f_1(tp);
4979                 break;
4980
4981         case RTL_GIGA_MAC_VER_38:
4982                 rtl_hw_start_8411(tp);
4983                 break;
4984
4985         default:
4986                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4987                         dev->name, tp->mac_version);
4988                 break;
4989         }
4990
4991         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4992
4993         RTL_W8(Cfg9346, Cfg9346_Lock);
4994
4995         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4996 }
4997
4998 #define R810X_CPCMD_QUIRK_MASK (\
4999         EnableBist | \
5000         Mac_dbgo_oe | \
5001         Force_half_dup | \
5002         Force_rxflow_en | \
5003         Force_txflow_en | \
5004         Cxpl_dbg_sel | \
5005         ASF | \
5006         PktCntrDisable | \
5007         Mac_dbgo_sel)
5008
5009 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5010 {
5011         void __iomem *ioaddr = tp->mmio_addr;
5012         struct pci_dev *pdev = tp->pci_dev;
5013         static const struct ephy_info e_info_8102e_1[] = {
5014                 { 0x01, 0, 0x6e65 },
5015                 { 0x02, 0, 0x091f },
5016                 { 0x03, 0, 0xc2f9 },
5017                 { 0x06, 0, 0xafb5 },
5018                 { 0x07, 0, 0x0e00 },
5019                 { 0x19, 0, 0xec80 },
5020                 { 0x01, 0, 0x2e65 },
5021                 { 0x01, 0, 0x6e65 }
5022         };
5023         u8 cfg1;
5024
5025         rtl_csi_access_enable_2(tp);
5026
5027         RTL_W8(DBG_REG, FIX_NAK_1);
5028
5029         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5030
5031         RTL_W8(Config1,
5032                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5033         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5034
5035         cfg1 = RTL_R8(Config1);
5036         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5037                 RTL_W8(Config1, cfg1 & ~LEDS0);
5038
5039         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5040 }
5041
5042 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5043 {
5044         void __iomem *ioaddr = tp->mmio_addr;
5045         struct pci_dev *pdev = tp->pci_dev;
5046
5047         rtl_csi_access_enable_2(tp);
5048
5049         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5050
5051         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5052         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5053 }
5054
5055 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5056 {
5057         rtl_hw_start_8102e_2(tp);
5058
5059         rtl_ephy_write(tp->mmio_addr, 0x03, 0xc2f9);
5060 }
5061
5062 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5063 {
5064         void __iomem *ioaddr = tp->mmio_addr;
5065         static const struct ephy_info e_info_8105e_1[] = {
5066                 { 0x07, 0, 0x4000 },
5067                 { 0x19, 0, 0x0200 },
5068                 { 0x19, 0, 0x0020 },
5069                 { 0x1e, 0, 0x2000 },
5070                 { 0x03, 0, 0x0001 },
5071                 { 0x19, 0, 0x0100 },
5072                 { 0x19, 0, 0x0004 },
5073                 { 0x0a, 0, 0x0020 }
5074         };
5075
5076         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5077         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5078
5079         /* Disable Early Tally Counter */
5080         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5081
5082         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5083         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5084
5085         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5086 }
5087
5088 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5089 {
5090         void __iomem *ioaddr = tp->mmio_addr;
5091
5092         rtl_hw_start_8105e_1(tp);
5093         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5094 }
5095
5096 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5097 {
5098         void __iomem *ioaddr = tp->mmio_addr;
5099         static const struct ephy_info e_info_8402[] = {
5100                 { 0x19, 0xffff, 0xff64 },
5101                 { 0x1e, 0, 0x4000 }
5102         };
5103
5104         rtl_csi_access_enable_2(tp);
5105
5106         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5107         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5108
5109         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5110         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5111
5112         rtl_ephy_init(ioaddr, e_info_8402, ARRAY_SIZE(e_info_8402));
5113
5114         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5115
5116         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5117         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5118         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5119         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5120         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5121         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5122         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00,
5123                      ERIAR_EXGMAC);
5124 }
5125
5126 static void rtl_hw_start_8101(struct net_device *dev)
5127 {
5128         struct rtl8169_private *tp = netdev_priv(dev);
5129         void __iomem *ioaddr = tp->mmio_addr;
5130         struct pci_dev *pdev = tp->pci_dev;
5131
5132         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5133                 tp->event_slow &= ~RxFIFOOver;
5134
5135         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5136             tp->mac_version == RTL_GIGA_MAC_VER_16) {
5137                 int cap = pci_pcie_cap(pdev);
5138
5139                 if (cap) {
5140                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5141                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
5142                 }
5143         }
5144
5145         RTL_W8(Cfg9346, Cfg9346_Unlock);
5146
5147         switch (tp->mac_version) {
5148         case RTL_GIGA_MAC_VER_07:
5149                 rtl_hw_start_8102e_1(tp);
5150                 break;
5151
5152         case RTL_GIGA_MAC_VER_08:
5153                 rtl_hw_start_8102e_3(tp);
5154                 break;
5155
5156         case RTL_GIGA_MAC_VER_09:
5157                 rtl_hw_start_8102e_2(tp);
5158                 break;
5159
5160         case RTL_GIGA_MAC_VER_29:
5161                 rtl_hw_start_8105e_1(tp);
5162                 break;
5163         case RTL_GIGA_MAC_VER_30:
5164                 rtl_hw_start_8105e_2(tp);
5165                 break;
5166
5167         case RTL_GIGA_MAC_VER_37:
5168                 rtl_hw_start_8402(tp);
5169                 break;
5170         }
5171
5172         RTL_W8(Cfg9346, Cfg9346_Lock);
5173
5174         RTL_W8(MaxTxPacketSize, TxPacketMax);
5175
5176         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5177
5178         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5179         RTL_W16(CPlusCmd, tp->cp_cmd);
5180
5181         RTL_W16(IntrMitigate, 0x0000);
5182
5183         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5184
5185         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5186         rtl_set_rx_tx_config_registers(tp);
5187
5188         RTL_R8(IntrMask);
5189
5190         rtl_set_rx_mode(dev);
5191
5192         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5193 }
5194
5195 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5196 {
5197         struct rtl8169_private *tp = netdev_priv(dev);
5198
5199         if (new_mtu < ETH_ZLEN ||
5200             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5201                 return -EINVAL;
5202
5203         if (new_mtu > ETH_DATA_LEN)
5204                 rtl_hw_jumbo_enable(tp);
5205         else
5206                 rtl_hw_jumbo_disable(tp);
5207
5208         dev->mtu = new_mtu;
5209         netdev_update_features(dev);
5210
5211         return 0;
5212 }
5213
5214 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5215 {
5216         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5217         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5218 }
5219
5220 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5221                                      void **data_buff, struct RxDesc *desc)
5222 {
5223         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5224                          DMA_FROM_DEVICE);
5225
5226         kfree(*data_buff);
5227         *data_buff = NULL;
5228         rtl8169_make_unusable_by_asic(desc);
5229 }
5230
5231 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5232 {
5233         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5234
5235         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5236 }
5237
5238 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5239                                        u32 rx_buf_sz)
5240 {
5241         desc->addr = cpu_to_le64(mapping);
5242         wmb();
5243         rtl8169_mark_to_asic(desc, rx_buf_sz);
5244 }
5245
5246 static inline void *rtl8169_align(void *data)
5247 {
5248         return (void *)ALIGN((long)data, 16);
5249 }
5250
5251 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5252                                              struct RxDesc *desc)
5253 {
5254         void *data;
5255         dma_addr_t mapping;
5256         struct device *d = &tp->pci_dev->dev;
5257         struct net_device *dev = tp->dev;
5258         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5259
5260         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5261         if (!data)
5262                 return NULL;
5263
5264         if (rtl8169_align(data) != data) {
5265                 kfree(data);
5266                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5267                 if (!data)
5268                         return NULL;
5269         }
5270
5271         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5272                                  DMA_FROM_DEVICE);
5273         if (unlikely(dma_mapping_error(d, mapping))) {
5274                 if (net_ratelimit())
5275                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5276                 goto err_out;
5277         }
5278
5279         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5280         return data;
5281
5282 err_out:
5283         kfree(data);
5284         return NULL;
5285 }
5286
5287 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5288 {
5289         unsigned int i;
5290
5291         for (i = 0; i < NUM_RX_DESC; i++) {
5292                 if (tp->Rx_databuff[i]) {
5293                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5294                                             tp->RxDescArray + i);
5295                 }
5296         }
5297 }
5298
5299 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5300 {
5301         desc->opts1 |= cpu_to_le32(RingEnd);
5302 }
5303
5304 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5305 {
5306         unsigned int i;
5307
5308         for (i = 0; i < NUM_RX_DESC; i++) {
5309                 void *data;
5310
5311                 if (tp->Rx_databuff[i])
5312                         continue;
5313
5314                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5315                 if (!data) {
5316                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5317                         goto err_out;
5318                 }
5319                 tp->Rx_databuff[i] = data;
5320         }
5321
5322         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5323         return 0;
5324
5325 err_out:
5326         rtl8169_rx_clear(tp);
5327         return -ENOMEM;
5328 }
5329
5330 static int rtl8169_init_ring(struct net_device *dev)
5331 {
5332         struct rtl8169_private *tp = netdev_priv(dev);
5333
5334         rtl8169_init_ring_indexes(tp);
5335
5336         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5337         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5338
5339         return rtl8169_rx_fill(tp);
5340 }
5341
5342 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5343                                  struct TxDesc *desc)
5344 {
5345         unsigned int len = tx_skb->len;
5346
5347         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5348
5349         desc->opts1 = 0x00;
5350         desc->opts2 = 0x00;
5351         desc->addr = 0x00;
5352         tx_skb->len = 0;
5353 }
5354
5355 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5356                                    unsigned int n)
5357 {
5358         unsigned int i;
5359
5360         for (i = 0; i < n; i++) {
5361                 unsigned int entry = (start + i) % NUM_TX_DESC;
5362                 struct ring_info *tx_skb = tp->tx_skb + entry;
5363                 unsigned int len = tx_skb->len;
5364
5365                 if (len) {
5366                         struct sk_buff *skb = tx_skb->skb;
5367
5368                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5369                                              tp->TxDescArray + entry);
5370                         if (skb) {
5371                                 tp->dev->stats.tx_dropped++;
5372                                 dev_kfree_skb(skb);
5373                                 tx_skb->skb = NULL;
5374                         }
5375                 }
5376         }
5377 }
5378
5379 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5380 {
5381         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5382         tp->cur_tx = tp->dirty_tx = 0;
5383         netdev_reset_queue(tp->dev);
5384 }
5385
5386 static void rtl_reset_work(struct rtl8169_private *tp)
5387 {
5388         struct net_device *dev = tp->dev;
5389         int i;
5390
5391         napi_disable(&tp->napi);
5392         netif_stop_queue(dev);
5393         synchronize_sched();
5394
5395         rtl8169_hw_reset(tp);
5396
5397         for (i = 0; i < NUM_RX_DESC; i++)
5398                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5399
5400         rtl8169_tx_clear(tp);
5401         rtl8169_init_ring_indexes(tp);
5402
5403         napi_enable(&tp->napi);
5404         rtl_hw_start(dev);
5405         netif_wake_queue(dev);
5406         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5407 }
5408
5409 static void rtl8169_tx_timeout(struct net_device *dev)
5410 {
5411         struct rtl8169_private *tp = netdev_priv(dev);
5412
5413         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5414 }
5415
5416 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5417                               u32 *opts)
5418 {
5419         struct skb_shared_info *info = skb_shinfo(skb);
5420         unsigned int cur_frag, entry;
5421         struct TxDesc * uninitialized_var(txd);
5422         struct device *d = &tp->pci_dev->dev;
5423
5424         entry = tp->cur_tx;
5425         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5426                 const skb_frag_t *frag = info->frags + cur_frag;
5427                 dma_addr_t mapping;
5428                 u32 status, len;
5429                 void *addr;
5430
5431                 entry = (entry + 1) % NUM_TX_DESC;
5432
5433                 txd = tp->TxDescArray + entry;
5434                 len = skb_frag_size(frag);
5435                 addr = skb_frag_address(frag);
5436                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5437                 if (unlikely(dma_mapping_error(d, mapping))) {
5438                         if (net_ratelimit())
5439                                 netif_err(tp, drv, tp->dev,
5440                                           "Failed to map TX fragments DMA!\n");
5441                         goto err_out;
5442                 }
5443
5444                 /* Anti gcc 2.95.3 bugware (sic) */
5445                 status = opts[0] | len |
5446                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5447
5448                 txd->opts1 = cpu_to_le32(status);
5449                 txd->opts2 = cpu_to_le32(opts[1]);
5450                 txd->addr = cpu_to_le64(mapping);
5451
5452                 tp->tx_skb[entry].len = len;
5453         }
5454
5455         if (cur_frag) {
5456                 tp->tx_skb[entry].skb = skb;
5457                 txd->opts1 |= cpu_to_le32(LastFrag);
5458         }
5459
5460         return cur_frag;
5461
5462 err_out:
5463         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5464         return -EIO;
5465 }
5466
5467 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5468                                     struct sk_buff *skb, u32 *opts)
5469 {
5470         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5471         u32 mss = skb_shinfo(skb)->gso_size;
5472         int offset = info->opts_offset;
5473
5474         if (mss) {
5475                 opts[0] |= TD_LSO;
5476                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5477         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5478                 const struct iphdr *ip = ip_hdr(skb);
5479
5480                 if (ip->protocol == IPPROTO_TCP)
5481                         opts[offset] |= info->checksum.tcp;
5482                 else if (ip->protocol == IPPROTO_UDP)
5483                         opts[offset] |= info->checksum.udp;
5484                 else
5485                         WARN_ON_ONCE(1);
5486         }
5487 }
5488
5489 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5490                                       struct net_device *dev)
5491 {
5492         struct rtl8169_private *tp = netdev_priv(dev);
5493         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5494         struct TxDesc *txd = tp->TxDescArray + entry;
5495         void __iomem *ioaddr = tp->mmio_addr;
5496         struct device *d = &tp->pci_dev->dev;
5497         dma_addr_t mapping;
5498         u32 status, len;
5499         u32 opts[2];
5500         int frags;
5501
5502         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5503                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5504                 goto err_stop_0;
5505         }
5506
5507         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5508                 goto err_stop_0;
5509
5510         len = skb_headlen(skb);
5511         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5512         if (unlikely(dma_mapping_error(d, mapping))) {
5513                 if (net_ratelimit())
5514                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5515                 goto err_dma_0;
5516         }
5517
5518         tp->tx_skb[entry].len = len;
5519         txd->addr = cpu_to_le64(mapping);
5520
5521         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5522         opts[0] = DescOwn;
5523
5524         rtl8169_tso_csum(tp, skb, opts);
5525
5526         frags = rtl8169_xmit_frags(tp, skb, opts);
5527         if (frags < 0)
5528                 goto err_dma_1;
5529         else if (frags)
5530                 opts[0] |= FirstFrag;
5531         else {
5532                 opts[0] |= FirstFrag | LastFrag;
5533                 tp->tx_skb[entry].skb = skb;
5534         }
5535
5536         txd->opts2 = cpu_to_le32(opts[1]);
5537
5538         netdev_sent_queue(dev, skb->len);
5539
5540         skb_tx_timestamp(skb);
5541
5542         wmb();
5543
5544         /* Anti gcc 2.95.3 bugware (sic) */
5545         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5546         txd->opts1 = cpu_to_le32(status);
5547
5548         tp->cur_tx += frags + 1;
5549
5550         wmb();
5551
5552         RTL_W8(TxPoll, NPQ);
5553
5554         mmiowb();
5555
5556         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5557                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5558                  * not miss a ring update when it notices a stopped queue.
5559                  */
5560                 smp_wmb();
5561                 netif_stop_queue(dev);
5562                 /* Sync with rtl_tx:
5563                  * - publish queue status and cur_tx ring index (write barrier)
5564                  * - refresh dirty_tx ring index (read barrier).
5565                  * May the current thread have a pessimistic view of the ring
5566                  * status and forget to wake up queue, a racing rtl_tx thread
5567                  * can't.
5568                  */
5569                 smp_mb();
5570                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5571                         netif_wake_queue(dev);
5572         }
5573
5574         return NETDEV_TX_OK;
5575
5576 err_dma_1:
5577         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5578 err_dma_0:
5579         dev_kfree_skb(skb);
5580         dev->stats.tx_dropped++;
5581         return NETDEV_TX_OK;
5582
5583 err_stop_0:
5584         netif_stop_queue(dev);
5585         dev->stats.tx_dropped++;
5586         return NETDEV_TX_BUSY;
5587 }
5588
5589 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5590 {
5591         struct rtl8169_private *tp = netdev_priv(dev);
5592         struct pci_dev *pdev = tp->pci_dev;
5593         u16 pci_status, pci_cmd;
5594
5595         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5596         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5597
5598         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5599                   pci_cmd, pci_status);
5600
5601         /*
5602          * The recovery sequence below admits a very elaborated explanation:
5603          * - it seems to work;
5604          * - I did not see what else could be done;
5605          * - it makes iop3xx happy.
5606          *
5607          * Feel free to adjust to your needs.
5608          */
5609         if (pdev->broken_parity_status)
5610                 pci_cmd &= ~PCI_COMMAND_PARITY;
5611         else
5612                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5613
5614         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5615
5616         pci_write_config_word(pdev, PCI_STATUS,
5617                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5618                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5619                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5620
5621         /* The infamous DAC f*ckup only happens at boot time */
5622         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5623                 void __iomem *ioaddr = tp->mmio_addr;
5624
5625                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5626                 tp->cp_cmd &= ~PCIDAC;
5627                 RTL_W16(CPlusCmd, tp->cp_cmd);
5628                 dev->features &= ~NETIF_F_HIGHDMA;
5629         }
5630
5631         rtl8169_hw_reset(tp);
5632
5633         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5634 }
5635
5636 struct rtl_txc {
5637         int packets;
5638         int bytes;
5639 };
5640
5641 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5642 {
5643         struct rtl8169_stats *tx_stats = &tp->tx_stats;
5644         unsigned int dirty_tx, tx_left;
5645         struct rtl_txc txc = { 0, 0 };
5646
5647         dirty_tx = tp->dirty_tx;
5648         smp_rmb();
5649         tx_left = tp->cur_tx - dirty_tx;
5650
5651         while (tx_left > 0) {
5652                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5653                 struct ring_info *tx_skb = tp->tx_skb + entry;
5654                 u32 status;
5655
5656                 rmb();
5657                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5658                 if (status & DescOwn)
5659                         break;
5660
5661                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5662                                      tp->TxDescArray + entry);
5663                 if (status & LastFrag) {
5664                         struct sk_buff *skb = tx_skb->skb;
5665
5666                         txc.packets++;
5667                         txc.bytes += skb->len;
5668                         dev_kfree_skb(skb);
5669                         tx_skb->skb = NULL;
5670                 }
5671                 dirty_tx++;
5672                 tx_left--;
5673         }
5674
5675         u64_stats_update_begin(&tx_stats->syncp);
5676         tx_stats->packets += txc.packets;
5677         tx_stats->bytes += txc.bytes;
5678         u64_stats_update_end(&tx_stats->syncp);
5679
5680         netdev_completed_queue(dev, txc.packets, txc.bytes);
5681
5682         if (tp->dirty_tx != dirty_tx) {
5683                 tp->dirty_tx = dirty_tx;
5684                 /* Sync with rtl8169_start_xmit:
5685                  * - publish dirty_tx ring index (write barrier)
5686                  * - refresh cur_tx ring index and queue status (read barrier)
5687                  * May the current thread miss the stopped queue condition,
5688                  * a racing xmit thread can only have a right view of the
5689                  * ring status.
5690                  */
5691                 smp_mb();
5692                 if (netif_queue_stopped(dev) &&
5693                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5694                         netif_wake_queue(dev);
5695                 }
5696                 /*
5697                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5698                  * too close. Let's kick an extra TxPoll request when a burst
5699                  * of start_xmit activity is detected (if it is not detected,
5700                  * it is slow enough). -- FR
5701                  */
5702                 if (tp->cur_tx != dirty_tx) {
5703                         void __iomem *ioaddr = tp->mmio_addr;
5704
5705                         RTL_W8(TxPoll, NPQ);
5706                 }
5707         }
5708 }
5709
5710 static inline int rtl8169_fragmented_frame(u32 status)
5711 {
5712         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5713 }
5714
5715 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5716 {
5717         u32 status = opts1 & RxProtoMask;
5718
5719         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5720             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5721                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5722         else
5723                 skb_checksum_none_assert(skb);
5724 }
5725
5726 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5727                                            struct rtl8169_private *tp,
5728                                            int pkt_size,
5729                                            dma_addr_t addr)
5730 {
5731         struct sk_buff *skb;
5732         struct device *d = &tp->pci_dev->dev;
5733
5734         data = rtl8169_align(data);
5735         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5736         prefetch(data);
5737         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5738         if (skb)
5739                 memcpy(skb->data, data, pkt_size);
5740         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5741
5742         return skb;
5743 }
5744
5745 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5746 {
5747         unsigned int cur_rx, rx_left;
5748         unsigned int count;
5749
5750         cur_rx = tp->cur_rx;
5751         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5752         rx_left = min(rx_left, budget);
5753
5754         for (; rx_left > 0; rx_left--, cur_rx++) {
5755                 unsigned int entry = cur_rx % NUM_RX_DESC;
5756                 struct RxDesc *desc = tp->RxDescArray + entry;
5757                 u32 status;
5758
5759                 rmb();
5760                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5761
5762                 if (status & DescOwn)
5763                         break;
5764                 if (unlikely(status & RxRES)) {
5765                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5766                                    status);
5767                         dev->stats.rx_errors++;
5768                         if (status & (RxRWT | RxRUNT))
5769                                 dev->stats.rx_length_errors++;
5770                         if (status & RxCRC)
5771                                 dev->stats.rx_crc_errors++;
5772                         if (status & RxFOVF) {
5773                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5774                                 dev->stats.rx_fifo_errors++;
5775                         }
5776                         if ((status & (RxRUNT | RxCRC)) &&
5777                             !(status & (RxRWT | RxFOVF)) &&
5778                             (dev->features & NETIF_F_RXALL))
5779                                 goto process_pkt;
5780
5781                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5782                 } else {
5783                         struct sk_buff *skb;
5784                         dma_addr_t addr;
5785                         int pkt_size;
5786
5787 process_pkt:
5788                         addr = le64_to_cpu(desc->addr);
5789                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5790                                 pkt_size = (status & 0x00003fff) - 4;
5791                         else
5792                                 pkt_size = status & 0x00003fff;
5793
5794                         /*
5795                          * The driver does not support incoming fragmented
5796                          * frames. They are seen as a symptom of over-mtu
5797                          * sized frames.
5798                          */
5799                         if (unlikely(rtl8169_fragmented_frame(status))) {
5800                                 dev->stats.rx_dropped++;
5801                                 dev->stats.rx_length_errors++;
5802                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5803                                 continue;
5804                         }
5805
5806                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5807                                                   tp, pkt_size, addr);
5808                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5809                         if (!skb) {
5810                                 dev->stats.rx_dropped++;
5811                                 continue;
5812                         }
5813
5814                         rtl8169_rx_csum(skb, status);
5815                         skb_put(skb, pkt_size);
5816                         skb->protocol = eth_type_trans(skb, dev);
5817
5818                         rtl8169_rx_vlan_tag(desc, skb);
5819
5820                         napi_gro_receive(&tp->napi, skb);
5821
5822                         u64_stats_update_begin(&tp->rx_stats.syncp);
5823                         tp->rx_stats.packets++;
5824                         tp->rx_stats.bytes += pkt_size;
5825                         u64_stats_update_end(&tp->rx_stats.syncp);
5826                 }
5827
5828                 /* Work around for AMD plateform. */
5829                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5830                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5831                         desc->opts2 = 0;
5832                         cur_rx++;
5833                 }
5834         }
5835
5836         count = cur_rx - tp->cur_rx;
5837         tp->cur_rx = cur_rx;
5838
5839         tp->dirty_rx += count;
5840
5841         return count;
5842 }
5843
5844 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5845 {
5846         struct net_device *dev = dev_instance;
5847         struct rtl8169_private *tp = netdev_priv(dev);
5848         int handled = 0;
5849         u16 status;
5850
5851         status = rtl_get_events(tp);
5852         if (status && status != 0xffff) {
5853                 status &= RTL_EVENT_NAPI | tp->event_slow;
5854                 if (status) {
5855                         handled = 1;
5856
5857                         rtl_irq_disable(tp);
5858                         napi_schedule(&tp->napi);
5859                 }
5860         }
5861         return IRQ_RETVAL(handled);
5862 }
5863
5864 /*
5865  * Workqueue context.
5866  */
5867 static void rtl_slow_event_work(struct rtl8169_private *tp)
5868 {
5869         struct net_device *dev = tp->dev;
5870         u16 status;
5871
5872         status = rtl_get_events(tp) & tp->event_slow;
5873         rtl_ack_events(tp, status);
5874
5875         if (unlikely(status & RxFIFOOver)) {
5876                 switch (tp->mac_version) {
5877                 /* Work around for rx fifo overflow */
5878                 case RTL_GIGA_MAC_VER_11:
5879                         netif_stop_queue(dev);
5880                         /* XXX - Hack alert. See rtl_task(). */
5881                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5882                 default:
5883                         break;
5884                 }
5885         }
5886
5887         if (unlikely(status & SYSErr))
5888                 rtl8169_pcierr_interrupt(dev);
5889
5890         if (status & LinkChg)
5891                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5892
5893         rtl_irq_enable_all(tp);
5894 }
5895
5896 static void rtl_task(struct work_struct *work)
5897 {
5898         static const struct {
5899                 int bitnr;
5900                 void (*action)(struct rtl8169_private *);
5901         } rtl_work[] = {
5902                 /* XXX - keep rtl_slow_event_work() as first element. */
5903                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
5904                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
5905                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
5906         };
5907         struct rtl8169_private *tp =
5908                 container_of(work, struct rtl8169_private, wk.work);
5909         struct net_device *dev = tp->dev;
5910         int i;
5911
5912         rtl_lock_work(tp);
5913
5914         if (!netif_running(dev) ||
5915             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5916                 goto out_unlock;
5917
5918         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5919                 bool pending;
5920
5921                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5922                 if (pending)
5923                         rtl_work[i].action(tp);
5924         }
5925
5926 out_unlock:
5927         rtl_unlock_work(tp);
5928 }
5929
5930 static int rtl8169_poll(struct napi_struct *napi, int budget)
5931 {
5932         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5933         struct net_device *dev = tp->dev;
5934         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5935         int work_done= 0;
5936         u16 status;
5937
5938         status = rtl_get_events(tp);
5939         rtl_ack_events(tp, status & ~tp->event_slow);
5940
5941         if (status & RTL_EVENT_NAPI_RX)
5942                 work_done = rtl_rx(dev, tp, (u32) budget);
5943
5944         if (status & RTL_EVENT_NAPI_TX)
5945                 rtl_tx(dev, tp);
5946
5947         if (status & tp->event_slow) {
5948                 enable_mask &= ~tp->event_slow;
5949
5950                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5951         }
5952
5953         if (work_done < budget) {
5954                 napi_complete(napi);
5955
5956                 rtl_irq_enable(tp, enable_mask);
5957                 mmiowb();
5958         }
5959
5960         return work_done;
5961 }
5962
5963 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5964 {
5965         struct rtl8169_private *tp = netdev_priv(dev);
5966
5967         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5968                 return;
5969
5970         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5971         RTL_W32(RxMissed, 0);
5972 }
5973
5974 static void rtl8169_down(struct net_device *dev)
5975 {
5976         struct rtl8169_private *tp = netdev_priv(dev);
5977         void __iomem *ioaddr = tp->mmio_addr;
5978
5979         del_timer_sync(&tp->timer);
5980
5981         napi_disable(&tp->napi);
5982         netif_stop_queue(dev);
5983
5984         rtl8169_hw_reset(tp);
5985         /*
5986          * At this point device interrupts can not be enabled in any function,
5987          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5988          * and napi is disabled (rtl8169_poll).
5989          */
5990         rtl8169_rx_missed(dev, ioaddr);
5991
5992         /* Give a racing hard_start_xmit a few cycles to complete. */
5993         synchronize_sched();
5994
5995         rtl8169_tx_clear(tp);
5996
5997         rtl8169_rx_clear(tp);
5998
5999         rtl_pll_power_down(tp);
6000 }
6001
6002 static int rtl8169_close(struct net_device *dev)
6003 {
6004         struct rtl8169_private *tp = netdev_priv(dev);
6005         struct pci_dev *pdev = tp->pci_dev;
6006
6007         pm_runtime_get_sync(&pdev->dev);
6008
6009         /* Update counters before going down */
6010         rtl8169_update_counters(dev);
6011
6012         rtl_lock_work(tp);
6013         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6014
6015         rtl8169_down(dev);
6016         rtl_unlock_work(tp);
6017
6018         free_irq(pdev->irq, dev);
6019
6020         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6021                           tp->RxPhyAddr);
6022         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6023                           tp->TxPhyAddr);
6024         tp->TxDescArray = NULL;
6025         tp->RxDescArray = NULL;
6026
6027         pm_runtime_put_sync(&pdev->dev);
6028
6029         return 0;
6030 }
6031
6032 #ifdef CONFIG_NET_POLL_CONTROLLER
6033 static void rtl8169_netpoll(struct net_device *dev)
6034 {
6035         struct rtl8169_private *tp = netdev_priv(dev);
6036
6037         rtl8169_interrupt(tp->pci_dev->irq, dev);
6038 }
6039 #endif
6040
6041 static int rtl_open(struct net_device *dev)
6042 {
6043         struct rtl8169_private *tp = netdev_priv(dev);
6044         void __iomem *ioaddr = tp->mmio_addr;
6045         struct pci_dev *pdev = tp->pci_dev;
6046         int retval = -ENOMEM;
6047
6048         pm_runtime_get_sync(&pdev->dev);
6049
6050         /*
6051          * Rx and Tx descriptors needs 256 bytes alignment.
6052          * dma_alloc_coherent provides more.
6053          */
6054         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6055                                              &tp->TxPhyAddr, GFP_KERNEL);
6056         if (!tp->TxDescArray)
6057                 goto err_pm_runtime_put;
6058
6059         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6060                                              &tp->RxPhyAddr, GFP_KERNEL);
6061         if (!tp->RxDescArray)
6062                 goto err_free_tx_0;
6063
6064         retval = rtl8169_init_ring(dev);
6065         if (retval < 0)
6066                 goto err_free_rx_1;
6067
6068         INIT_WORK(&tp->wk.work, rtl_task);
6069
6070         smp_mb();
6071
6072         rtl_request_firmware(tp);
6073
6074         retval = request_irq(pdev->irq, rtl8169_interrupt,
6075                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6076                              dev->name, dev);
6077         if (retval < 0)
6078                 goto err_release_fw_2;
6079
6080         rtl_lock_work(tp);
6081
6082         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6083
6084         napi_enable(&tp->napi);
6085
6086         rtl8169_init_phy(dev, tp);
6087
6088         __rtl8169_set_features(dev, dev->features);
6089
6090         rtl_pll_power_up(tp);
6091
6092         rtl_hw_start(dev);
6093
6094         netif_start_queue(dev);
6095
6096         rtl_unlock_work(tp);
6097
6098         tp->saved_wolopts = 0;
6099         pm_runtime_put_noidle(&pdev->dev);
6100
6101         rtl8169_check_link_status(dev, tp, ioaddr);
6102 out:
6103         return retval;
6104
6105 err_release_fw_2:
6106         rtl_release_firmware(tp);
6107         rtl8169_rx_clear(tp);
6108 err_free_rx_1:
6109         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6110                           tp->RxPhyAddr);
6111         tp->RxDescArray = NULL;
6112 err_free_tx_0:
6113         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6114                           tp->TxPhyAddr);
6115         tp->TxDescArray = NULL;
6116 err_pm_runtime_put:
6117         pm_runtime_put_noidle(&pdev->dev);
6118         goto out;
6119 }
6120
6121 static struct rtnl_link_stats64 *
6122 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6123 {
6124         struct rtl8169_private *tp = netdev_priv(dev);
6125         void __iomem *ioaddr = tp->mmio_addr;
6126         unsigned int start;
6127
6128         if (netif_running(dev))
6129                 rtl8169_rx_missed(dev, ioaddr);
6130
6131         do {
6132                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6133                 stats->rx_packets = tp->rx_stats.packets;
6134                 stats->rx_bytes = tp->rx_stats.bytes;
6135         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6136
6137
6138         do {
6139                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6140                 stats->tx_packets = tp->tx_stats.packets;
6141                 stats->tx_bytes = tp->tx_stats.bytes;
6142         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6143
6144         stats->rx_dropped       = dev->stats.rx_dropped;
6145         stats->tx_dropped       = dev->stats.tx_dropped;
6146         stats->rx_length_errors = dev->stats.rx_length_errors;
6147         stats->rx_errors        = dev->stats.rx_errors;
6148         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6149         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6150         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6151
6152         return stats;
6153 }
6154
6155 static void rtl8169_net_suspend(struct net_device *dev)
6156 {
6157         struct rtl8169_private *tp = netdev_priv(dev);
6158
6159         if (!netif_running(dev))
6160                 return;
6161
6162         netif_device_detach(dev);
6163         netif_stop_queue(dev);
6164
6165         rtl_lock_work(tp);
6166         napi_disable(&tp->napi);
6167         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6168         rtl_unlock_work(tp);
6169
6170         rtl_pll_power_down(tp);
6171 }
6172
6173 #ifdef CONFIG_PM
6174
6175 static int rtl8169_suspend(struct device *device)
6176 {
6177         struct pci_dev *pdev = to_pci_dev(device);
6178         struct net_device *dev = pci_get_drvdata(pdev);
6179
6180         rtl8169_net_suspend(dev);
6181
6182         return 0;
6183 }
6184
6185 static void __rtl8169_resume(struct net_device *dev)
6186 {
6187         struct rtl8169_private *tp = netdev_priv(dev);
6188
6189         netif_device_attach(dev);
6190
6191         rtl_pll_power_up(tp);
6192
6193         rtl_lock_work(tp);
6194         napi_enable(&tp->napi);
6195         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6196         rtl_unlock_work(tp);
6197
6198         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6199 }
6200
6201 static int rtl8169_resume(struct device *device)
6202 {
6203         struct pci_dev *pdev = to_pci_dev(device);
6204         struct net_device *dev = pci_get_drvdata(pdev);
6205         struct rtl8169_private *tp = netdev_priv(dev);
6206
6207         rtl8169_init_phy(dev, tp);
6208
6209         if (netif_running(dev))
6210                 __rtl8169_resume(dev);
6211
6212         return 0;
6213 }
6214
6215 static int rtl8169_runtime_suspend(struct device *device)
6216 {
6217         struct pci_dev *pdev = to_pci_dev(device);
6218         struct net_device *dev = pci_get_drvdata(pdev);
6219         struct rtl8169_private *tp = netdev_priv(dev);
6220
6221         if (!tp->TxDescArray)
6222                 return 0;
6223
6224         rtl_lock_work(tp);
6225         tp->saved_wolopts = __rtl8169_get_wol(tp);
6226         __rtl8169_set_wol(tp, WAKE_ANY);
6227         rtl_unlock_work(tp);
6228
6229         rtl8169_net_suspend(dev);
6230
6231         return 0;
6232 }
6233
6234 static int rtl8169_runtime_resume(struct device *device)
6235 {
6236         struct pci_dev *pdev = to_pci_dev(device);
6237         struct net_device *dev = pci_get_drvdata(pdev);
6238         struct rtl8169_private *tp = netdev_priv(dev);
6239
6240         if (!tp->TxDescArray)
6241                 return 0;
6242
6243         rtl_lock_work(tp);
6244         __rtl8169_set_wol(tp, tp->saved_wolopts);
6245         tp->saved_wolopts = 0;
6246         rtl_unlock_work(tp);
6247
6248         rtl8169_init_phy(dev, tp);
6249
6250         __rtl8169_resume(dev);
6251
6252         return 0;
6253 }
6254
6255 static int rtl8169_runtime_idle(struct device *device)
6256 {
6257         struct pci_dev *pdev = to_pci_dev(device);
6258         struct net_device *dev = pci_get_drvdata(pdev);
6259         struct rtl8169_private *tp = netdev_priv(dev);
6260
6261         return tp->TxDescArray ? -EBUSY : 0;
6262 }
6263
6264 static const struct dev_pm_ops rtl8169_pm_ops = {
6265         .suspend                = rtl8169_suspend,
6266         .resume                 = rtl8169_resume,
6267         .freeze                 = rtl8169_suspend,
6268         .thaw                   = rtl8169_resume,
6269         .poweroff               = rtl8169_suspend,
6270         .restore                = rtl8169_resume,
6271         .runtime_suspend        = rtl8169_runtime_suspend,
6272         .runtime_resume         = rtl8169_runtime_resume,
6273         .runtime_idle           = rtl8169_runtime_idle,
6274 };
6275
6276 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6277
6278 #else /* !CONFIG_PM */
6279
6280 #define RTL8169_PM_OPS  NULL
6281
6282 #endif /* !CONFIG_PM */
6283
6284 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6285 {
6286         void __iomem *ioaddr = tp->mmio_addr;
6287
6288         /* WoL fails with 8168b when the receiver is disabled. */
6289         switch (tp->mac_version) {
6290         case RTL_GIGA_MAC_VER_11:
6291         case RTL_GIGA_MAC_VER_12:
6292         case RTL_GIGA_MAC_VER_17:
6293                 pci_clear_master(tp->pci_dev);
6294
6295                 RTL_W8(ChipCmd, CmdRxEnb);
6296                 /* PCI commit */
6297                 RTL_R8(ChipCmd);
6298                 break;
6299         default:
6300                 break;
6301         }
6302 }
6303
6304 static void rtl_shutdown(struct pci_dev *pdev)
6305 {
6306         struct net_device *dev = pci_get_drvdata(pdev);
6307         struct rtl8169_private *tp = netdev_priv(dev);
6308         struct device *d = &pdev->dev;
6309
6310         pm_runtime_get_sync(d);
6311
6312         rtl8169_net_suspend(dev);
6313
6314         /* Restore original MAC address */
6315         rtl_rar_set(tp, dev->perm_addr);
6316
6317         rtl8169_hw_reset(tp);
6318
6319         if (system_state == SYSTEM_POWER_OFF) {
6320                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6321                         rtl_wol_suspend_quirk(tp);
6322                         rtl_wol_shutdown_quirk(tp);
6323                 }
6324
6325                 pci_wake_from_d3(pdev, true);
6326                 pci_set_power_state(pdev, PCI_D3hot);
6327         }
6328
6329         pm_runtime_put_noidle(d);
6330 }
6331
6332 static void __devexit rtl_remove_one(struct pci_dev *pdev)
6333 {
6334         struct net_device *dev = pci_get_drvdata(pdev);
6335         struct rtl8169_private *tp = netdev_priv(dev);
6336
6337         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6338             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6339             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6340                 rtl8168_driver_stop(tp);
6341         }
6342
6343         cancel_work_sync(&tp->wk.work);
6344
6345         netif_napi_del(&tp->napi);
6346
6347         unregister_netdev(dev);
6348
6349         rtl_release_firmware(tp);
6350
6351         if (pci_dev_run_wake(pdev))
6352                 pm_runtime_get_noresume(&pdev->dev);
6353
6354         /* restore original MAC address */
6355         rtl_rar_set(tp, dev->perm_addr);
6356
6357         rtl_disable_msi(pdev, tp);
6358         rtl8169_release_board(pdev, dev, tp->mmio_addr);
6359         pci_set_drvdata(pdev, NULL);
6360 }
6361
6362 static const struct net_device_ops rtl_netdev_ops = {
6363         .ndo_open               = rtl_open,
6364         .ndo_stop               = rtl8169_close,
6365         .ndo_get_stats64        = rtl8169_get_stats64,
6366         .ndo_start_xmit         = rtl8169_start_xmit,
6367         .ndo_tx_timeout         = rtl8169_tx_timeout,
6368         .ndo_validate_addr      = eth_validate_addr,
6369         .ndo_change_mtu         = rtl8169_change_mtu,
6370         .ndo_fix_features       = rtl8169_fix_features,
6371         .ndo_set_features       = rtl8169_set_features,
6372         .ndo_set_mac_address    = rtl_set_mac_address,
6373         .ndo_do_ioctl           = rtl8169_ioctl,
6374         .ndo_set_rx_mode        = rtl_set_rx_mode,
6375 #ifdef CONFIG_NET_POLL_CONTROLLER
6376         .ndo_poll_controller    = rtl8169_netpoll,
6377 #endif
6378
6379 };
6380
6381 static const struct rtl_cfg_info {
6382         void (*hw_start)(struct net_device *);
6383         unsigned int region;
6384         unsigned int align;
6385         u16 event_slow;
6386         unsigned features;
6387         u8 default_ver;
6388 } rtl_cfg_infos [] = {
6389         [RTL_CFG_0] = {
6390                 .hw_start       = rtl_hw_start_8169,
6391                 .region         = 1,
6392                 .align          = 0,
6393                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6394                 .features       = RTL_FEATURE_GMII,
6395                 .default_ver    = RTL_GIGA_MAC_VER_01,
6396         },
6397         [RTL_CFG_1] = {
6398                 .hw_start       = rtl_hw_start_8168,
6399                 .region         = 2,
6400                 .align          = 8,
6401                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6402                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6403                 .default_ver    = RTL_GIGA_MAC_VER_11,
6404         },
6405         [RTL_CFG_2] = {
6406                 .hw_start       = rtl_hw_start_8101,
6407                 .region         = 2,
6408                 .align          = 8,
6409                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6410                                   PCSTimeout,
6411                 .features       = RTL_FEATURE_MSI,
6412                 .default_ver    = RTL_GIGA_MAC_VER_13,
6413         }
6414 };
6415
6416 /* Cfg9346_Unlock assumed. */
6417 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6418                             const struct rtl_cfg_info *cfg)
6419 {
6420         void __iomem *ioaddr = tp->mmio_addr;
6421         unsigned msi = 0;
6422         u8 cfg2;
6423
6424         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6425         if (cfg->features & RTL_FEATURE_MSI) {
6426                 if (pci_enable_msi(tp->pci_dev)) {
6427                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6428                 } else {
6429                         cfg2 |= MSIEnable;
6430                         msi = RTL_FEATURE_MSI;
6431                 }
6432         }
6433         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6434                 RTL_W8(Config2, cfg2);
6435         return msi;
6436 }
6437
6438 static int __devinit
6439 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6440 {
6441         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6442         const unsigned int region = cfg->region;
6443         struct rtl8169_private *tp;
6444         struct mii_if_info *mii;
6445         struct net_device *dev;
6446         void __iomem *ioaddr;
6447         int chipset, i;
6448         int rc;
6449
6450         if (netif_msg_drv(&debug)) {
6451                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6452                        MODULENAME, RTL8169_VERSION);
6453         }
6454
6455         dev = alloc_etherdev(sizeof (*tp));
6456         if (!dev) {
6457                 rc = -ENOMEM;
6458                 goto out;
6459         }
6460
6461         SET_NETDEV_DEV(dev, &pdev->dev);
6462         dev->netdev_ops = &rtl_netdev_ops;
6463         tp = netdev_priv(dev);
6464         tp->dev = dev;
6465         tp->pci_dev = pdev;
6466         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6467
6468         mii = &tp->mii;
6469         mii->dev = dev;
6470         mii->mdio_read = rtl_mdio_read;
6471         mii->mdio_write = rtl_mdio_write;
6472         mii->phy_id_mask = 0x1f;
6473         mii->reg_num_mask = 0x1f;
6474         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6475
6476         /* disable ASPM completely as that cause random device stop working
6477          * problems as well as full system hangs for some PCIe devices users */
6478         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6479                                      PCIE_LINK_STATE_CLKPM);
6480
6481         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6482         rc = pci_enable_device(pdev);
6483         if (rc < 0) {
6484                 netif_err(tp, probe, dev, "enable failure\n");
6485                 goto err_out_free_dev_1;
6486         }
6487
6488         if (pci_set_mwi(pdev) < 0)
6489                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6490
6491         /* make sure PCI base addr 1 is MMIO */
6492         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6493                 netif_err(tp, probe, dev,
6494                           "region #%d not an MMIO resource, aborting\n",
6495                           region);
6496                 rc = -ENODEV;
6497                 goto err_out_mwi_2;
6498         }
6499
6500         /* check for weird/broken PCI region reporting */
6501         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6502                 netif_err(tp, probe, dev,
6503                           "Invalid PCI region size(s), aborting\n");
6504                 rc = -ENODEV;
6505                 goto err_out_mwi_2;
6506         }
6507
6508         rc = pci_request_regions(pdev, MODULENAME);
6509         if (rc < 0) {
6510                 netif_err(tp, probe, dev, "could not request regions\n");
6511                 goto err_out_mwi_2;
6512         }
6513
6514         tp->cp_cmd = RxChkSum;
6515
6516         if ((sizeof(dma_addr_t) > 4) &&
6517             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6518                 tp->cp_cmd |= PCIDAC;
6519                 dev->features |= NETIF_F_HIGHDMA;
6520         } else {
6521                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6522                 if (rc < 0) {
6523                         netif_err(tp, probe, dev, "DMA configuration failed\n");
6524                         goto err_out_free_res_3;
6525                 }
6526         }
6527
6528         /* ioremap MMIO region */
6529         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6530         if (!ioaddr) {
6531                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6532                 rc = -EIO;
6533                 goto err_out_free_res_3;
6534         }
6535         tp->mmio_addr = ioaddr;
6536
6537         if (!pci_is_pcie(pdev))
6538                 netif_info(tp, probe, dev, "not PCI Express\n");
6539
6540         /* Identify chip attached to board */
6541         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6542
6543         rtl_init_rxcfg(tp);
6544
6545         rtl_irq_disable(tp);
6546
6547         rtl_hw_reset(tp);
6548
6549         rtl_ack_events(tp, 0xffff);
6550
6551         pci_set_master(pdev);
6552
6553         /*
6554          * Pretend we are using VLANs; This bypasses a nasty bug where
6555          * Interrupts stop flowing on high load on 8110SCd controllers.
6556          */
6557         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6558                 tp->cp_cmd |= RxVlan;
6559
6560         rtl_init_mdio_ops(tp);
6561         rtl_init_pll_power_ops(tp);
6562         rtl_init_jumbo_ops(tp);
6563         rtl_init_csi_ops(tp);
6564
6565         rtl8169_print_mac_version(tp);
6566
6567         chipset = tp->mac_version;
6568         tp->txd_version = rtl_chip_infos[chipset].txd_version;
6569
6570         RTL_W8(Cfg9346, Cfg9346_Unlock);
6571         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6572         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6573         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6574                 tp->features |= RTL_FEATURE_WOL;
6575         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6576                 tp->features |= RTL_FEATURE_WOL;
6577         tp->features |= rtl_try_msi(tp, cfg);
6578         RTL_W8(Cfg9346, Cfg9346_Lock);
6579
6580         if (rtl_tbi_enabled(tp)) {
6581                 tp->set_speed = rtl8169_set_speed_tbi;
6582                 tp->get_settings = rtl8169_gset_tbi;
6583                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6584                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6585                 tp->link_ok = rtl8169_tbi_link_ok;
6586                 tp->do_ioctl = rtl_tbi_ioctl;
6587         } else {
6588                 tp->set_speed = rtl8169_set_speed_xmii;
6589                 tp->get_settings = rtl8169_gset_xmii;
6590                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6591                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6592                 tp->link_ok = rtl8169_xmii_link_ok;
6593                 tp->do_ioctl = rtl_xmii_ioctl;
6594         }
6595
6596         mutex_init(&tp->wk.mutex);
6597
6598         /* Get MAC address */
6599         for (i = 0; i < ETH_ALEN; i++)
6600                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6601         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6602
6603         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6604         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6605
6606         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6607
6608         /* don't enable SG, IP_CSUM and TSO by default - it might not work
6609          * properly for all devices */
6610         dev->features |= NETIF_F_RXCSUM |
6611                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6612
6613         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6614                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6615         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6616                 NETIF_F_HIGHDMA;
6617
6618         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6619                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6620                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6621
6622         dev->hw_features |= NETIF_F_RXALL;
6623         dev->hw_features |= NETIF_F_RXFCS;
6624
6625         tp->hw_start = cfg->hw_start;
6626         tp->event_slow = cfg->event_slow;
6627
6628         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6629                 ~(RxBOVF | RxFOVF) : ~0;
6630
6631         init_timer(&tp->timer);
6632         tp->timer.data = (unsigned long) dev;
6633         tp->timer.function = rtl8169_phy_timer;
6634
6635         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6636
6637         rc = register_netdev(dev);
6638         if (rc < 0)
6639                 goto err_out_msi_4;
6640
6641         pci_set_drvdata(pdev, dev);
6642
6643         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6644                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6645                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6646         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6647                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6648                            "tx checksumming: %s]\n",
6649                            rtl_chip_infos[chipset].jumbo_max,
6650                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6651         }
6652
6653         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6654             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6655             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6656                 rtl8168_driver_start(tp);
6657         }
6658
6659         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6660
6661         if (pci_dev_run_wake(pdev))
6662                 pm_runtime_put_noidle(&pdev->dev);
6663
6664         netif_carrier_off(dev);
6665
6666 out:
6667         return rc;
6668
6669 err_out_msi_4:
6670         netif_napi_del(&tp->napi);
6671         rtl_disable_msi(pdev, tp);
6672         iounmap(ioaddr);
6673 err_out_free_res_3:
6674         pci_release_regions(pdev);
6675 err_out_mwi_2:
6676         pci_clear_mwi(pdev);
6677         pci_disable_device(pdev);
6678 err_out_free_dev_1:
6679         free_netdev(dev);
6680         goto out;
6681 }
6682
6683 static struct pci_driver rtl8169_pci_driver = {
6684         .name           = MODULENAME,
6685         .id_table       = rtl8169_pci_tbl,
6686         .probe          = rtl_init_one,
6687         .remove         = __devexit_p(rtl_remove_one),
6688         .shutdown       = rtl_shutdown,
6689         .driver.pm      = RTL8169_PM_OPS,
6690 };
6691
6692 static int __init rtl8169_init_module(void)
6693 {
6694         return pci_register_driver(&rtl8169_pci_driver);
6695 }
6696
6697 static void __exit rtl8169_cleanup_module(void)
6698 {
6699         pci_unregister_driver(&rtl8169_pci_driver);
6700 }
6701
6702 module_init(rtl8169_init_module);
6703 module_exit(rtl8169_cleanup_module);