Pileus Git - ~andy/linux/blob - drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48
  49 #ifdef RTL8169_DEBUG
  50 #define assert(expr) \
  51         if (!(expr)) {                                  \
  52                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  53                 #expr,__FILE__,__func__,__LINE__);              \
  54         }
  55 #define dprintk(fmt, args...) \
  56         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  57 #else
  58 #define assert(expr) do {} while (0)
  59 #define dprintk(fmt, args...)   do {} while (0)
  60 #endif /* RTL8169_DEBUG */
  61
  62 #define R8169_MSG_DEFAULT \
  63         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  64
  65 #define TX_BUFFS_AVAIL(tp) \
  66         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  67
  68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  69    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  70 static const int multicast_filter_limit = 32;
  71
  72 #define MAX_READ_REQUEST_SHIFT  12
  73 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  74 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  75 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  76
  77 #define R8169_REGS_SIZE         256
  78 #define R8169_NAPI_WEIGHT       64
  79 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  80 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  81 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  82 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  83 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  84
  85 #define RTL8169_TX_TIMEOUT      (6*HZ)
  86 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  87
  88 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  89 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  90 #define RTL_EEPROM_SIG_ADDR     0x0000
  91
  92 /* write/read MMIO register */
  93 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  94 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  95 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  96 #define RTL_R8(reg)             readb (ioaddr + (reg))
  97 #define RTL_R16(reg)            readw (ioaddr + (reg))
  98 #define RTL_R32(reg)            readl (ioaddr + (reg))
  99
 100 enum mac_version {
 101         RTL_GIGA_MAC_VER_01 = 0,
 102         RTL_GIGA_MAC_VER_02,
 103         RTL_GIGA_MAC_VER_03,
 104         RTL_GIGA_MAC_VER_04,
 105         RTL_GIGA_MAC_VER_05,
 106         RTL_GIGA_MAC_VER_06,
 107         RTL_GIGA_MAC_VER_07,
 108         RTL_GIGA_MAC_VER_08,
 109         RTL_GIGA_MAC_VER_09,
 110         RTL_GIGA_MAC_VER_10,
 111         RTL_GIGA_MAC_VER_11,
 112         RTL_GIGA_MAC_VER_12,
 113         RTL_GIGA_MAC_VER_13,
 114         RTL_GIGA_MAC_VER_14,
 115         RTL_GIGA_MAC_VER_15,
 116         RTL_GIGA_MAC_VER_16,
 117         RTL_GIGA_MAC_VER_17,
 118         RTL_GIGA_MAC_VER_18,
 119         RTL_GIGA_MAC_VER_19,
 120         RTL_GIGA_MAC_VER_20,
 121         RTL_GIGA_MAC_VER_21,
 122         RTL_GIGA_MAC_VER_22,
 123         RTL_GIGA_MAC_VER_23,
 124         RTL_GIGA_MAC_VER_24,
 125         RTL_GIGA_MAC_VER_25,
 126         RTL_GIGA_MAC_VER_26,
 127         RTL_GIGA_MAC_VER_27,
 128         RTL_GIGA_MAC_VER_28,
 129         RTL_GIGA_MAC_VER_29,
 130         RTL_GIGA_MAC_VER_30,
 131         RTL_GIGA_MAC_VER_31,
 132         RTL_GIGA_MAC_VER_32,
 133         RTL_GIGA_MAC_VER_33,
 134         RTL_GIGA_MAC_VER_34,
 135         RTL_GIGA_MAC_VER_35,
 136         RTL_GIGA_MAC_VER_36,
 137         RTL_GIGA_MAC_NONE   = 0xff,
 138 };
 139
 140 enum rtl_tx_desc_version {
 141         RTL_TD_0        = 0,
 142         RTL_TD_1        = 1,
 143 };
 144
 145 #define JUMBO_1K        ETH_DATA_LEN
 146 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 147 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 148 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 149 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 150
 151 #define _R(NAME,TD,FW,SZ,B) {   \
 152         .name = NAME,           \
 153         .txd_version = TD,      \
 154         .fw_name = FW,          \
 155         .jumbo_max = SZ,        \
 156         .jumbo_tx_csum = B      \
 157 }
 158
 159 static const struct {
 160         const char *name;
 161         enum rtl_tx_desc_version txd_version;
 162         const char *fw_name;
 163         u16 jumbo_max;
 164         bool jumbo_tx_csum;
 165 } rtl_chip_infos[] = {
 166         /* PCI devices. */
 167         [RTL_GIGA_MAC_VER_01] =
 168                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 169         [RTL_GIGA_MAC_VER_02] =
 170                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 171         [RTL_GIGA_MAC_VER_03] =
 172                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 173         [RTL_GIGA_MAC_VER_04] =
 174                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 175         [RTL_GIGA_MAC_VER_05] =
 176                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 177         [RTL_GIGA_MAC_VER_06] =
 178                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 179         /* PCI-E devices. */
 180         [RTL_GIGA_MAC_VER_07] =
 181                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 182         [RTL_GIGA_MAC_VER_08] =
 183                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 184         [RTL_GIGA_MAC_VER_09] =
 185                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 186         [RTL_GIGA_MAC_VER_10] =
 187                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 188         [RTL_GIGA_MAC_VER_11] =
 189                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 190         [RTL_GIGA_MAC_VER_12] =
 191                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 192         [RTL_GIGA_MAC_VER_13] =
 193                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 194         [RTL_GIGA_MAC_VER_14] =
 195                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 196         [RTL_GIGA_MAC_VER_15] =
 197                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 198         [RTL_GIGA_MAC_VER_16] =
 199                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 200         [RTL_GIGA_MAC_VER_17] =
 201                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 202         [RTL_GIGA_MAC_VER_18] =
 203                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 204         [RTL_GIGA_MAC_VER_19] =
 205                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 206         [RTL_GIGA_MAC_VER_20] =
 207                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 208         [RTL_GIGA_MAC_VER_21] =
 209                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 210         [RTL_GIGA_MAC_VER_22] =
 211                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 212         [RTL_GIGA_MAC_VER_23] =
 213                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 214         [RTL_GIGA_MAC_VER_24] =
 215                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 216         [RTL_GIGA_MAC_VER_25] =
 217                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 218                                                         JUMBO_9K, false),
 219         [RTL_GIGA_MAC_VER_26] =
 220                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 221                                                         JUMBO_9K, false),
 222         [RTL_GIGA_MAC_VER_27] =
 223                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 224         [RTL_GIGA_MAC_VER_28] =
 225                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 226         [RTL_GIGA_MAC_VER_29] =
 227                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 228                                                         JUMBO_1K, true),
 229         [RTL_GIGA_MAC_VER_30] =
 230                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 231                                                         JUMBO_1K, true),
 232         [RTL_GIGA_MAC_VER_31] =
 233                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 234         [RTL_GIGA_MAC_VER_32] =
 235                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 236                                                         JUMBO_9K, false),
 237         [RTL_GIGA_MAC_VER_33] =
 238                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 239                                                         JUMBO_9K, false),
 240         [RTL_GIGA_MAC_VER_34] =
 241                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_35] =
 244                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_36] =
 247                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 248                                                         JUMBO_9K, false),
 249 };
 250 #undef _R
 251
 252 enum cfg_version {
 253         RTL_CFG_0 = 0x00,
 254         RTL_CFG_1,
 255         RTL_CFG_2
 256 };
 257
 258 static void rtl_hw_start_8169(struct net_device *);
 259 static void rtl_hw_start_8168(struct net_device *);
 260 static void rtl_hw_start_8101(struct net_device *);
 261
 262 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 263         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 264         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 265         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 266         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 267         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 268         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 269         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 270         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 271         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 272         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 273                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 274         { 0x0001,                               0x8168,
 275                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 276         {0,},
 277 };
 278
 279 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 280
 281 static int rx_buf_sz = 16383;
 282 static int use_dac;
 283 static struct {
 284         u32 msg_enable;
 285 } debug = { -1 };
 286
 287 enum rtl_registers {
 288         MAC0            = 0,    /* Ethernet hardware address. */
 289         MAC4            = 4,
 290         MAR0            = 8,    /* Multicast filter. */
 291         CounterAddrLow          = 0x10,
 292         CounterAddrHigh         = 0x14,
 293         TxDescStartAddrLow      = 0x20,
 294         TxDescStartAddrHigh     = 0x24,
 295         TxHDescStartAddrLow     = 0x28,
 296         TxHDescStartAddrHigh    = 0x2c,
 297         FLASH           = 0x30,
 298         ERSR            = 0x36,
 299         ChipCmd         = 0x37,
 300         TxPoll          = 0x38,
 301         IntrMask        = 0x3c,
 302         IntrStatus      = 0x3e,
 303
 304         TxConfig        = 0x40,
 305 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 306 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 307
 308         RxConfig        = 0x44,
 309 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 310 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 311 #define RXCFG_FIFO_SHIFT                13
 312                                         /* No threshold before first PCI xfer */
 313 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 314 #define RXCFG_DMA_SHIFT                 8
 315                                         /* Unlimited maximum PCI burst. */
 316 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 317
 318         RxMissed        = 0x4c,
 319         Cfg9346         = 0x50,
 320         Config0         = 0x51,
 321         Config1         = 0x52,
 322         Config2         = 0x53,
 323         Config3         = 0x54,
 324         Config4         = 0x55,
 325         Config5         = 0x56,
 326         MultiIntr       = 0x5c,
 327         PHYAR           = 0x60,
 328         PHYstatus       = 0x6c,
 329         RxMaxSize       = 0xda,
 330         CPlusCmd        = 0xe0,
 331         IntrMitigate    = 0xe2,
 332         RxDescAddrLow   = 0xe4,
 333         RxDescAddrHigh  = 0xe8,
 334         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 335
 336 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 337
 338         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 339
 340 #define TxPacketMax     (8064 >> 7)
 341 #define EarlySize       0x27
 342
 343         FuncEvent       = 0xf0,
 344         FuncEventMask   = 0xf4,
 345         FuncPresetState = 0xf8,
 346         FuncForceEvent  = 0xfc,
 347 };
 348
 349 enum rtl8110_registers {
 350         TBICSR                  = 0x64,
 351         TBI_ANAR                = 0x68,
 352         TBI_LPAR                = 0x6a,
 353 };
 354
 355 enum rtl8168_8101_registers {
 356         CSIDR                   = 0x64,
 357         CSIAR                   = 0x68,
 358 #define CSIAR_FLAG                      0x80000000
 359 #define CSIAR_WRITE_CMD                 0x80000000
 360 #define CSIAR_BYTE_ENABLE               0x0f
 361 #define CSIAR_BYTE_ENABLE_SHIFT         12
 362 #define CSIAR_ADDR_MASK                 0x0fff
 363         PMCH                    = 0x6f,
 364         EPHYAR                  = 0x80,
 365 #define EPHYAR_FLAG                     0x80000000
 366 #define EPHYAR_WRITE_CMD                0x80000000
 367 #define EPHYAR_REG_MASK                 0x1f
 368 #define EPHYAR_REG_SHIFT                16
 369 #define EPHYAR_DATA_MASK                0xffff
 370         DLLPR                   = 0xd0,
 371 #define PFM_EN                          (1 << 6)
 372         DBG_REG                 = 0xd1,
 373 #define FIX_NAK_1                       (1 << 4)
 374 #define FIX_NAK_2                       (1 << 3)
 375         TWSI                    = 0xd2,
 376         MCU                     = 0xd3,
 377 #define NOW_IS_OOB                      (1 << 7)
 378 #define EN_NDP                          (1 << 3)
 379 #define EN_OOB_RESET                    (1 << 2)
 380         EFUSEAR                 = 0xdc,
 381 #define EFUSEAR_FLAG                    0x80000000
 382 #define EFUSEAR_WRITE_CMD               0x80000000
 383 #define EFUSEAR_READ_CMD                0x00000000
 384 #define EFUSEAR_REG_MASK                0x03ff
 385 #define EFUSEAR_REG_SHIFT               8
 386 #define EFUSEAR_DATA_MASK               0xff
 387 };
 388
 389 enum rtl8168_registers {
 390         LED_FREQ                = 0x1a,
 391         EEE_LED                 = 0x1b,
 392         ERIDR                   = 0x70,
 393         ERIAR                   = 0x74,
 394 #define ERIAR_FLAG                      0x80000000
 395 #define ERIAR_WRITE_CMD                 0x80000000
 396 #define ERIAR_READ_CMD                  0x00000000
 397 #define ERIAR_ADDR_BYTE_ALIGN           4
 398 #define ERIAR_TYPE_SHIFT                16
 399 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 400 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 401 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 402 #define ERIAR_MASK_SHIFT                12
 403 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 404 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 405 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 406         EPHY_RXER_NUM           = 0x7c,
 407         OCPDR                   = 0xb0, /* OCP GPHY access */
 408 #define OCPDR_WRITE_CMD                 0x80000000
 409 #define OCPDR_READ_CMD                  0x00000000
 410 #define OCPDR_REG_MASK                  0x7f
 411 #define OCPDR_GPHY_REG_SHIFT            16
 412 #define OCPDR_DATA_MASK                 0xffff
 413         OCPAR                   = 0xb4,
 414 #define OCPAR_FLAG                      0x80000000
 415 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 416 #define OCPAR_GPHY_READ_CMD             0x0000f060
 417         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 418         MISC                    = 0xf0, /* 8168e only. */
 419 #define TXPLA_RST                       (1 << 29)
 420 #define PWM_EN                          (1 << 22)
 421 };
 422
 423 enum rtl_register_content {
 424         /* InterruptStatusBits */
 425         SYSErr          = 0x8000,
 426         PCSTimeout      = 0x4000,
 427         SWInt           = 0x0100,
 428         TxDescUnavail   = 0x0080,
 429         RxFIFOOver      = 0x0040,
 430         LinkChg         = 0x0020,
 431         RxOverflow      = 0x0010,
 432         TxErr           = 0x0008,
 433         TxOK            = 0x0004,
 434         RxErr           = 0x0002,
 435         RxOK            = 0x0001,
 436
 437         /* RxStatusDesc */
 438         RxBOVF  = (1 << 24),
 439         RxFOVF  = (1 << 23),
 440         RxRWT   = (1 << 22),
 441         RxRES   = (1 << 21),
 442         RxRUNT  = (1 << 20),
 443         RxCRC   = (1 << 19),
 444
 445         /* ChipCmdBits */
 446         StopReq         = 0x80,
 447         CmdReset        = 0x10,
 448         CmdRxEnb        = 0x08,
 449         CmdTxEnb        = 0x04,
 450         RxBufEmpty      = 0x01,
 451
 452         /* TXPoll register p.5 */
 453         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 454         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 455         FSWInt          = 0x01,         /* Forced software interrupt */
 456
 457         /* Cfg9346Bits */
 458         Cfg9346_Lock    = 0x00,
 459         Cfg9346_Unlock  = 0xc0,
 460
 461         /* rx_mode_bits */
 462         AcceptErr       = 0x20,
 463         AcceptRunt      = 0x10,
 464         AcceptBroadcast = 0x08,
 465         AcceptMulticast = 0x04,
 466         AcceptMyPhys    = 0x02,
 467         AcceptAllPhys   = 0x01,
 468 #define RX_CONFIG_ACCEPT_MASK           0x3f
 469
 470         /* TxConfigBits */
 471         TxInterFrameGapShift = 24,
 472         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 473
 474         /* Config1 register p.24 */
 475         LEDS1           = (1 << 7),
 476         LEDS0           = (1 << 6),
 477         Speed_down      = (1 << 4),
 478         MEMMAP          = (1 << 3),
 479         IOMAP           = (1 << 2),
 480         VPD             = (1 << 1),
 481         PMEnable        = (1 << 0),     /* Power Management Enable */
 482
 483         /* Config2 register p. 25 */
 484         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 485         PCI_Clock_66MHz = 0x01,
 486         PCI_Clock_33MHz = 0x00,
 487
 488         /* Config3 register p.25 */
 489         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 490         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 491         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 492         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 493
 494         /* Config4 register */
 495         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 496
 497         /* Config5 register p.27 */
 498         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 499         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 500         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 501         Spi_en          = (1 << 3),
 502         LanWake         = (1 << 1),     /* LanWake enable/disable */
 503         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 504
 505         /* TBICSR p.28 */
 506         TBIReset        = 0x80000000,
 507         TBILoopback     = 0x40000000,
 508         TBINwEnable     = 0x20000000,
 509         TBINwRestart    = 0x10000000,
 510         TBILinkOk       = 0x02000000,
 511         TBINwComplete   = 0x01000000,
 512
 513         /* CPlusCmd p.31 */
 514         EnableBist      = (1 << 15),    // 8168 8101
 515         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 516         Normal_mode     = (1 << 13),    // unused
 517         Force_half_dup  = (1 << 12),    // 8168 8101
 518         Force_rxflow_en = (1 << 11),    // 8168 8101
 519         Force_txflow_en = (1 << 10),    // 8168 8101
 520         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 521         ASF             = (1 << 8),     // 8168 8101
 522         PktCntrDisable  = (1 << 7),     // 8168 8101
 523         Mac_dbgo_sel    = 0x001c,       // 8168
 524         RxVlan          = (1 << 6),
 525         RxChkSum        = (1 << 5),
 526         PCIDAC          = (1 << 4),
 527         PCIMulRW        = (1 << 3),
 528         INTT_0          = 0x0000,       // 8168
 529         INTT_1          = 0x0001,       // 8168
 530         INTT_2          = 0x0002,       // 8168
 531         INTT_3          = 0x0003,       // 8168
 532
 533         /* rtl8169_PHYstatus */
 534         TBI_Enable      = 0x80,
 535         TxFlowCtrl      = 0x40,
 536         RxFlowCtrl      = 0x20,
 537         _1000bpsF       = 0x10,
 538         _100bps         = 0x08,
 539         _10bps          = 0x04,
 540         LinkStatus      = 0x02,
 541         FullDup         = 0x01,
 542
 543         /* _TBICSRBit */
 544         TBILinkOK       = 0x02000000,
 545
 546         /* DumpCounterCommand */
 547         CounterDump     = 0x8,
 548 };
 549
 550 enum rtl_desc_bit {
 551         /* First doubleword. */
 552         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 553         RingEnd         = (1 << 30), /* End of descriptor ring */
 554         FirstFrag       = (1 << 29), /* First segment of a packet */
 555         LastFrag        = (1 << 28), /* Final segment of a packet */
 556 };
 557
 558 /* Generic case. */
 559 enum rtl_tx_desc_bit {
 560         /* First doubleword. */
 561         TD_LSO          = (1 << 27),            /* Large Send Offload */
 562 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 563
 564         /* Second doubleword. */
 565         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 566 };
 567
 568 /* 8169, 8168b and 810x except 8102e. */
 569 enum rtl_tx_desc_bit_0 {
 570         /* First doubleword. */
 571 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 572         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 573         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 574         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 575 };
 576
 577 /* 8102e, 8168c and beyond. */
 578 enum rtl_tx_desc_bit_1 {
 579         /* Second doubleword. */
 580 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 581         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 582         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 583         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 584 };
 585
 586 static const struct rtl_tx_desc_info {
 587         struct {
 588                 u32 udp;
 589                 u32 tcp;
 590         } checksum;
 591         u16 mss_shift;
 592         u16 opts_offset;
 593 } tx_desc_info [] = {
 594         [RTL_TD_0] = {
 595                 .checksum = {
 596                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 597                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 598                 },
 599                 .mss_shift      = TD0_MSS_SHIFT,
 600                 .opts_offset    = 0
 601         },
 602         [RTL_TD_1] = {
 603                 .checksum = {
 604                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 605                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 606                 },
 607                 .mss_shift      = TD1_MSS_SHIFT,
 608                 .opts_offset    = 1
 609         }
 610 };
 611
 612 enum rtl_rx_desc_bit {
 613         /* Rx private */
 614         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 615         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 616
 617 #define RxProtoUDP      (PID1)
 618 #define RxProtoTCP      (PID0)
 619 #define RxProtoIP       (PID1 | PID0)
 620 #define RxProtoMask     RxProtoIP
 621
 622         IPFail          = (1 << 16), /* IP checksum failed */
 623         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 624         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 625         RxVlanTag       = (1 << 16), /* VLAN tag available */
 626 };
 627
 628 #define RsvdMask        0x3fffc000
 629
 630 struct TxDesc {
 631         __le32 opts1;
 632         __le32 opts2;
 633         __le64 addr;
 634 };
 635
 636 struct RxDesc {
 637         __le32 opts1;
 638         __le32 opts2;
 639         __le64 addr;
 640 };
 641
 642 struct ring_info {
 643         struct sk_buff  *skb;
 644         u32             len;
 645         u8              __pad[sizeof(void *) - sizeof(u32)];
 646 };
 647
 648 enum features {
 649         RTL_FEATURE_WOL         = (1 << 0),
 650         RTL_FEATURE_MSI         = (1 << 1),
 651         RTL_FEATURE_GMII        = (1 << 2),
 652 };
 653
 654 struct rtl8169_counters {
 655         __le64  tx_packets;
 656         __le64  rx_packets;
 657         __le64  tx_errors;
 658         __le32  rx_errors;
 659         __le16  rx_missed;
 660         __le16  align_errors;
 661         __le32  tx_one_collision;
 662         __le32  tx_multi_collision;
 663         __le64  rx_unicast;
 664         __le64  rx_broadcast;
 665         __le32  rx_multicast;
 666         __le16  tx_aborted;
 667         __le16  tx_underun;
 668 };
 669
 670 enum rtl_flag {
 671         RTL_FLAG_TASK_ENABLED,
 672         RTL_FLAG_TASK_SLOW_PENDING,
 673         RTL_FLAG_TASK_RESET_PENDING,
 674         RTL_FLAG_TASK_PHY_PENDING,
 675         RTL_FLAG_MAX
 676 };
 677
 678 struct rtl8169_stats {
 679         u64                     packets;
 680         u64                     bytes;
 681         struct u64_stats_sync   syncp;
 682 };
 683
 684 struct rtl8169_private {
 685         void __iomem *mmio_addr;        /* memory map physical address */
 686         struct pci_dev *pci_dev;
 687         struct net_device *dev;
 688         struct napi_struct napi;
 689         u32 msg_enable;
 690         u16 txd_version;
 691         u16 mac_version;
 692         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 693         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 694         u32 dirty_rx;
 695         u32 dirty_tx;
 696         struct rtl8169_stats rx_stats;
 697         struct rtl8169_stats tx_stats;
 698         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 699         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 700         dma_addr_t TxPhyAddr;
 701         dma_addr_t RxPhyAddr;
 702         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 703         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 704         struct timer_list timer;
 705         u16 cp_cmd;
 706
 707         u16 event_slow;
 708
 709         struct mdio_ops {
 710                 void (*write)(void __iomem *, int, int);
 711                 int (*read)(void __iomem *, int);
 712         } mdio_ops;
 713
 714         struct pll_power_ops {
 715                 void (*down)(struct rtl8169_private *);
 716                 void (*up)(struct rtl8169_private *);
 717         } pll_power_ops;
 718
 719         struct jumbo_ops {
 720                 void (*enable)(struct rtl8169_private *);
 721                 void (*disable)(struct rtl8169_private *);
 722         } jumbo_ops;
 723
 724         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 725         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 726         void (*phy_reset_enable)(struct rtl8169_private *tp);
 727         void (*hw_start)(struct net_device *);
 728         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 729         unsigned int (*link_ok)(void __iomem *);
 730         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 731
 732         struct {
 733                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 734                 struct mutex mutex;
 735                 struct work_struct work;
 736         } wk;
 737
 738         unsigned features;
 739
 740         struct mii_if_info mii;
 741         struct rtl8169_counters counters;
 742         u32 saved_wolopts;
 743         u32 opts1_mask;
 744
 745         struct rtl_fw {
 746                 const struct firmware *fw;
 747
 748 #define RTL_VER_SIZE            32
 749
 750                 char version[RTL_VER_SIZE];
 751
 752                 struct rtl_fw_phy_action {
 753                         __le32 *code;
 754                         size_t size;
 755                 } phy_action;
 756         } *rtl_fw;
 757 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 758 };
 759
 760 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 761 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 762 module_param(use_dac, int, 0);
 763 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 764 module_param_named(debug, debug.msg_enable, int, 0);
 765 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 766 MODULE_LICENSE("GPL");
 767 MODULE_VERSION(RTL8169_VERSION);
 768 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 769 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 770 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 771 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 772 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 773 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 774 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 775 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 776
 777 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 778 static int rtl8169_init_ring(struct net_device *dev);
 779 static void rtl_hw_start(struct net_device *dev);
 780 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 781 static int rtl8169_poll(struct napi_struct *napi, int budget);
 782
 783 static void rtl_lock_work(struct rtl8169_private *tp)
 784 {
 785         mutex_lock(&tp->wk.mutex);
 786 }
 787
 788 static void rtl_unlock_work(struct rtl8169_private *tp)
 789 {
 790         mutex_unlock(&tp->wk.mutex);
 791 }
 792
 793 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 794 {
 795         int cap = pci_pcie_cap(pdev);
 796
 797         if (cap) {
 798                 u16 ctl;
 799
 800                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 801                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 802                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 803         }
 804 }
 805
 806 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 807 {
 808         void __iomem *ioaddr = tp->mmio_addr;
 809         int i;
 810
 811         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 812         for (i = 0; i < 20; i++) {
 813                 udelay(100);
 814                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 815                         break;
 816         }
 817         return RTL_R32(OCPDR);
 818 }
 819
 820 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 821 {
 822         void __iomem *ioaddr = tp->mmio_addr;
 823         int i;
 824
 825         RTL_W32(OCPDR, data);
 826         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 827         for (i = 0; i < 20; i++) {
 828                 udelay(100);
 829                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 830                         break;
 831         }
 832 }
 833
 834 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 835 {
 836         void __iomem *ioaddr = tp->mmio_addr;
 837         int i;
 838
 839         RTL_W8(ERIDR, cmd);
 840         RTL_W32(ERIAR, 0x800010e8);
 841         msleep(2);
 842         for (i = 0; i < 5; i++) {
 843                 udelay(100);
 844                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 845                         break;
 846         }
 847
 848         ocp_write(tp, 0x1, 0x30, 0x00000001);
 849 }
 850
 851 #define OOB_CMD_RESET           0x00
 852 #define OOB_CMD_DRIVER_START    0x05
 853 #define OOB_CMD_DRIVER_STOP     0x06
 854
 855 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 856 {
 857         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 858 }
 859
 860 static void rtl8168_driver_start(struct rtl8169_private *tp)
 861 {
 862         u16 reg;
 863         int i;
 864
 865         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 866
 867         reg = rtl8168_get_ocp_reg(tp);
 868
 869         for (i = 0; i < 10; i++) {
 870                 msleep(10);
 871                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 872                         break;
 873         }
 874 }
 875
 876 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 877 {
 878         u16 reg;
 879         int i;
 880
 881         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 882
 883         reg = rtl8168_get_ocp_reg(tp);
 884
 885         for (i = 0; i < 10; i++) {
 886                 msleep(10);
 887                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 888                         break;
 889         }
 890 }
 891
 892 static int r8168dp_check_dash(struct rtl8169_private *tp)
 893 {
 894         u16 reg = rtl8168_get_ocp_reg(tp);
 895
 896         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 897 }
 898
 899 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 900 {
 901         int i;
 902
 903         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 904
 905         for (i = 20; i > 0; i--) {
 906                 /*
 907                  * Check if the RTL8169 has completed writing to the specified
 908                  * MII register.
 909                  */
 910                 if (!(RTL_R32(PHYAR) & 0x80000000))
 911                         break;
 912                 udelay(25);
 913         }
 914         /*
 915          * According to hardware specs a 20us delay is required after write
 916          * complete indication, but before sending next command.
 917          */
 918         udelay(20);
 919 }
 920
 921 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 922 {
 923         int i, value = -1;
 924
 925         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 926
 927         for (i = 20; i > 0; i--) {
 928                 /*
 929                  * Check if the RTL8169 has completed retrieving data from
 930                  * the specified MII register.
 931                  */
 932                 if (RTL_R32(PHYAR) & 0x80000000) {
 933                         value = RTL_R32(PHYAR) & 0xffff;
 934                         break;
 935                 }
 936                 udelay(25);
 937         }
 938         /*
 939          * According to hardware specs a 20us delay is required after read
 940          * complete indication, but before sending next command.
 941          */
 942         udelay(20);
 943
 944         return value;
 945 }
 946
 947 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 948 {
 949         int i;
 950
 951         RTL_W32(OCPDR, data |
 952                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 953         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 954         RTL_W32(EPHY_RXER_NUM, 0);
 955
 956         for (i = 0; i < 100; i++) {
 957                 mdelay(1);
 958                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 959                         break;
 960         }
 961 }
 962
 963 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 964 {
 965         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 966                 (value & OCPDR_DATA_MASK));
 967 }
 968
 969 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 970 {
 971         int i;
 972
 973         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 974
 975         mdelay(1);
 976         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 977         RTL_W32(EPHY_RXER_NUM, 0);
 978
 979         for (i = 0; i < 100; i++) {
 980                 mdelay(1);
 981                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 982                         break;
 983         }
 984
 985         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 986 }
 987
 988 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 989
 990 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 991 {
 992         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 993 }
 994
 995 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 996 {
 997         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 998 }
 999
1000 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1001 {
1002         r8168dp_2_mdio_start(ioaddr);
1003
1004         r8169_mdio_write(ioaddr, reg_addr, value);
1005
1006         r8168dp_2_mdio_stop(ioaddr);
1007 }
1008
1009 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1010 {
1011         int value;
1012
1013         r8168dp_2_mdio_start(ioaddr);
1014
1015         value = r8169_mdio_read(ioaddr, reg_addr);
1016
1017         r8168dp_2_mdio_stop(ioaddr);
1018
1019         return value;
1020 }
1021
1022 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1023 {
1024         tp->mdio_ops.write(tp->mmio_addr, location, val);
1025 }
1026
1027 static int rtl_readphy(struct rtl8169_private *tp, int location)
1028 {
1029         return tp->mdio_ops.read(tp->mmio_addr, location);
1030 }
1031
1032 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1033 {
1034         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1035 }
1036
1037 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1038 {
1039         int val;
1040
1041         val = rtl_readphy(tp, reg_addr);
1042         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1043 }
1044
1045 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1046                            int val)
1047 {
1048         struct rtl8169_private *tp = netdev_priv(dev);
1049
1050         rtl_writephy(tp, location, val);
1051 }
1052
1053 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1054 {
1055         struct rtl8169_private *tp = netdev_priv(dev);
1056
1057         return rtl_readphy(tp, location);
1058 }
1059
1060 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1061 {
1062         unsigned int i;
1063
1064         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1065                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1066
1067         for (i = 0; i < 100; i++) {
1068                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1069                         break;
1070                 udelay(10);
1071         }
1072 }
1073
1074 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1075 {
1076         u16 value = 0xffff;
1077         unsigned int i;
1078
1079         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1080
1081         for (i = 0; i < 100; i++) {
1082                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1083                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1084                         break;
1085                 }
1086                 udelay(10);
1087         }
1088
1089         return value;
1090 }
1091
1092 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1093 {
1094         unsigned int i;
1095
1096         RTL_W32(CSIDR, value);
1097         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1098                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1099
1100         for (i = 0; i < 100; i++) {
1101                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1102                         break;
1103                 udelay(10);
1104         }
1105 }
1106
1107 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1108 {
1109         u32 value = ~0x00;
1110         unsigned int i;
1111
1112         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1113                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1114
1115         for (i = 0; i < 100; i++) {
1116                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1117                         value = RTL_R32(CSIDR);
1118                         break;
1119                 }
1120                 udelay(10);
1121         }
1122
1123         return value;
1124 }
1125
1126 static
1127 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1128 {
1129         unsigned int i;
1130
1131         BUG_ON((addr & 3) || (mask == 0));
1132         RTL_W32(ERIDR, val);
1133         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1134
1135         for (i = 0; i < 100; i++) {
1136                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1137                         break;
1138                 udelay(100);
1139         }
1140 }
1141
1142 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1143 {
1144         u32 value = ~0x00;
1145         unsigned int i;
1146
1147         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1148
1149         for (i = 0; i < 100; i++) {
1150                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1151                         value = RTL_R32(ERIDR);
1152                         break;
1153                 }
1154                 udelay(100);
1155         }
1156
1157         return value;
1158 }
1159
1160 static void
1161 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1162 {
1163         u32 val;
1164
1165         val = rtl_eri_read(ioaddr, addr, type);
1166         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1167 }
1168
1169 struct exgmac_reg {
1170         u16 addr;
1171         u16 mask;
1172         u32 val;
1173 };
1174
1175 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1176                                    const struct exgmac_reg *r, int len)
1177 {
1178         while (len-- > 0) {
1179                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1180                 r++;
1181         }
1182 }
1183
1184 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1185 {
1186         u8 value = 0xff;
1187         unsigned int i;
1188
1189         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1190
1191         for (i = 0; i < 300; i++) {
1192                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1193                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1194                         break;
1195                 }
1196                 udelay(100);
1197         }
1198
1199         return value;
1200 }
1201
1202 static u16 rtl_get_events(struct rtl8169_private *tp)
1203 {
1204         void __iomem *ioaddr = tp->mmio_addr;
1205
1206         return RTL_R16(IntrStatus);
1207 }
1208
1209 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1210 {
1211         void __iomem *ioaddr = tp->mmio_addr;
1212
1213         RTL_W16(IntrStatus, bits);
1214         mmiowb();
1215 }
1216
1217 static void rtl_irq_disable(struct rtl8169_private *tp)
1218 {
1219         void __iomem *ioaddr = tp->mmio_addr;
1220
1221         RTL_W16(IntrMask, 0);
1222         mmiowb();
1223 }
1224
1225 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1226 {
1227         void __iomem *ioaddr = tp->mmio_addr;
1228
1229         RTL_W16(IntrMask, bits);
1230 }
1231
1232 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1233 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1234 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1235
1236 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1237 {
1238         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1239 }
1240
1241 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1242 {
1243         void __iomem *ioaddr = tp->mmio_addr;
1244
1245         rtl_irq_disable(tp);
1246         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1247         RTL_R8(ChipCmd);
1248 }
1249
1250 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1251 {
1252         void __iomem *ioaddr = tp->mmio_addr;
1253
1254         return RTL_R32(TBICSR) & TBIReset;
1255 }
1256
1257 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1258 {
1259         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1260 }
1261
1262 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1263 {
1264         return RTL_R32(TBICSR) & TBILinkOk;
1265 }
1266
1267 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1268 {
1269         return RTL_R8(PHYstatus) & LinkStatus;
1270 }
1271
1272 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1273 {
1274         void __iomem *ioaddr = tp->mmio_addr;
1275
1276         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1277 }
1278
1279 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1280 {
1281         unsigned int val;
1282
1283         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1284         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1285 }
1286
1287 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1288 {
1289         void __iomem *ioaddr = tp->mmio_addr;
1290         struct net_device *dev = tp->dev;
1291
1292         if (!netif_running(dev))
1293                 return;
1294
1295         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1296                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1297                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1298                                       0x00000011, ERIAR_EXGMAC);
1299                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1300                                       0x00000005, ERIAR_EXGMAC);
1301                 } else if (RTL_R8(PHYstatus) & _100bps) {
1302                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1303                                       0x0000001f, ERIAR_EXGMAC);
1304                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1305                                       0x00000005, ERIAR_EXGMAC);
1306                 } else {
1307                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1308                                       0x0000001f, ERIAR_EXGMAC);
1309                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1310                                       0x0000003f, ERIAR_EXGMAC);
1311                 }
1312                 /* Reset packet filter */
1313                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1314                              ERIAR_EXGMAC);
1315                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1316                              ERIAR_EXGMAC);
1317         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1318                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1319                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1320                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1321                                       0x00000011, ERIAR_EXGMAC);
1322                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1323                                       0x00000005, ERIAR_EXGMAC);
1324                 } else {
1325                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1326                                       0x0000001f, ERIAR_EXGMAC);
1327                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1328                                       0x0000003f, ERIAR_EXGMAC);
1329                 }
1330         }
1331 }
1332
1333 static void __rtl8169_check_link_status(struct net_device *dev,
1334                                         struct rtl8169_private *tp,
1335                                         void __iomem *ioaddr, bool pm)
1336 {
1337         if (tp->link_ok(ioaddr)) {
1338                 rtl_link_chg_patch(tp);
1339                 /* This is to cancel a scheduled suspend if there's one. */
1340                 if (pm)
1341                         pm_request_resume(&tp->pci_dev->dev);
1342                 netif_carrier_on(dev);
1343                 if (net_ratelimit())
1344                         netif_info(tp, ifup, dev, "link up\n");
1345         } else {
1346                 netif_carrier_off(dev);
1347                 netif_info(tp, ifdown, dev, "link down\n");
1348                 if (pm)
1349                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1350         }
1351 }
1352
1353 static void rtl8169_check_link_status(struct net_device *dev,
1354                                       struct rtl8169_private *tp,
1355                                       void __iomem *ioaddr)
1356 {
1357         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1358 }
1359
1360 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1361
1362 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1363 {
1364         void __iomem *ioaddr = tp->mmio_addr;
1365         u8 options;
1366         u32 wolopts = 0;
1367
1368         options = RTL_R8(Config1);
1369         if (!(options & PMEnable))
1370                 return 0;
1371
1372         options = RTL_R8(Config3);
1373         if (options & LinkUp)
1374                 wolopts |= WAKE_PHY;
1375         if (options & MagicPacket)
1376                 wolopts |= WAKE_MAGIC;
1377
1378         options = RTL_R8(Config5);
1379         if (options & UWF)
1380                 wolopts |= WAKE_UCAST;
1381         if (options & BWF)
1382                 wolopts |= WAKE_BCAST;
1383         if (options & MWF)
1384                 wolopts |= WAKE_MCAST;
1385
1386         return wolopts;
1387 }
1388
1389 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1390 {
1391         struct rtl8169_private *tp = netdev_priv(dev);
1392
1393         rtl_lock_work(tp);
1394
1395         wol->supported = WAKE_ANY;
1396         wol->wolopts = __rtl8169_get_wol(tp);
1397
1398         rtl_unlock_work(tp);
1399 }
1400
1401 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1402 {
1403         void __iomem *ioaddr = tp->mmio_addr;
1404         unsigned int i;
1405         static const struct {
1406                 u32 opt;
1407                 u16 reg;
1408                 u8  mask;
1409         } cfg[] = {
1410                 { WAKE_ANY,   Config1, PMEnable },
1411                 { WAKE_PHY,   Config3, LinkUp },
1412                 { WAKE_MAGIC, Config3, MagicPacket },
1413                 { WAKE_UCAST, Config5, UWF },
1414                 { WAKE_BCAST, Config5, BWF },
1415                 { WAKE_MCAST, Config5, MWF },
1416                 { WAKE_ANY,   Config5, LanWake }
1417         };
1418
1419         RTL_W8(Cfg9346, Cfg9346_Unlock);
1420
1421         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1422                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1423                 if (wolopts & cfg[i].opt)
1424                         options |= cfg[i].mask;
1425                 RTL_W8(cfg[i].reg, options);
1426         }
1427
1428         RTL_W8(Cfg9346, Cfg9346_Lock);
1429 }
1430
1431 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1432 {
1433         struct rtl8169_private *tp = netdev_priv(dev);
1434
1435         rtl_lock_work(tp);
1436
1437         if (wol->wolopts)
1438                 tp->features |= RTL_FEATURE_WOL;
1439         else
1440                 tp->features &= ~RTL_FEATURE_WOL;
1441         __rtl8169_set_wol(tp, wol->wolopts);
1442
1443         rtl_unlock_work(tp);
1444
1445         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1446
1447         return 0;
1448 }
1449
1450 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1451 {
1452         return rtl_chip_infos[tp->mac_version].fw_name;
1453 }
1454
1455 static void rtl8169_get_drvinfo(struct net_device *dev,
1456                                 struct ethtool_drvinfo *info)
1457 {
1458         struct rtl8169_private *tp = netdev_priv(dev);
1459         struct rtl_fw *rtl_fw = tp->rtl_fw;
1460
1461         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1462         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1463         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1464         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1465         if (!IS_ERR_OR_NULL(rtl_fw))
1466                 strlcpy(info->fw_version, rtl_fw->version,
1467                         sizeof(info->fw_version));
1468 }
1469
1470 static int rtl8169_get_regs_len(struct net_device *dev)
1471 {
1472         return R8169_REGS_SIZE;
1473 }
1474
1475 static int rtl8169_set_speed_tbi(struct net_device *dev,
1476                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1477 {
1478         struct rtl8169_private *tp = netdev_priv(dev);
1479         void __iomem *ioaddr = tp->mmio_addr;
1480         int ret = 0;
1481         u32 reg;
1482
1483         reg = RTL_R32(TBICSR);
1484         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1485             (duplex == DUPLEX_FULL)) {
1486                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1487         } else if (autoneg == AUTONEG_ENABLE)
1488                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1489         else {
1490                 netif_warn(tp, link, dev,
1491                            "incorrect speed setting refused in TBI mode\n");
1492                 ret = -EOPNOTSUPP;
1493         }
1494
1495         return ret;
1496 }
1497
1498 static int rtl8169_set_speed_xmii(struct net_device *dev,
1499                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1500 {
1501         struct rtl8169_private *tp = netdev_priv(dev);
1502         int giga_ctrl, bmcr;
1503         int rc = -EINVAL;
1504
1505         rtl_writephy(tp, 0x1f, 0x0000);
1506
1507         if (autoneg == AUTONEG_ENABLE) {
1508                 int auto_nego;
1509
1510                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1511                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1512                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1513
1514                 if (adv & ADVERTISED_10baseT_Half)
1515                         auto_nego |= ADVERTISE_10HALF;
1516                 if (adv & ADVERTISED_10baseT_Full)
1517                         auto_nego |= ADVERTISE_10FULL;
1518                 if (adv & ADVERTISED_100baseT_Half)
1519                         auto_nego |= ADVERTISE_100HALF;
1520                 if (adv & ADVERTISED_100baseT_Full)
1521                         auto_nego |= ADVERTISE_100FULL;
1522
1523                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1524
1525                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1526                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1527
1528                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1529                 if (tp->mii.supports_gmii) {
1530                         if (adv & ADVERTISED_1000baseT_Half)
1531                                 giga_ctrl |= ADVERTISE_1000HALF;
1532                         if (adv & ADVERTISED_1000baseT_Full)
1533                                 giga_ctrl |= ADVERTISE_1000FULL;
1534                 } else if (adv & (ADVERTISED_1000baseT_Half |
1535                                   ADVERTISED_1000baseT_Full)) {
1536                         netif_info(tp, link, dev,
1537                                    "PHY does not support 1000Mbps\n");
1538                         goto out;
1539                 }
1540
1541                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1542
1543                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1544                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1545         } else {
1546                 giga_ctrl = 0;
1547
1548                 if (speed == SPEED_10)
1549                         bmcr = 0;
1550                 else if (speed == SPEED_100)
1551                         bmcr = BMCR_SPEED100;
1552                 else
1553                         goto out;
1554
1555                 if (duplex == DUPLEX_FULL)
1556                         bmcr |= BMCR_FULLDPLX;
1557         }
1558
1559         rtl_writephy(tp, MII_BMCR, bmcr);
1560
1561         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1562             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1563                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1564                         rtl_writephy(tp, 0x17, 0x2138);
1565                         rtl_writephy(tp, 0x0e, 0x0260);
1566                 } else {
1567                         rtl_writephy(tp, 0x17, 0x2108);
1568                         rtl_writephy(tp, 0x0e, 0x0000);
1569                 }
1570         }
1571
1572         rc = 0;
1573 out:
1574         return rc;
1575 }
1576
1577 static int rtl8169_set_speed(struct net_device *dev,
1578                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1579 {
1580         struct rtl8169_private *tp = netdev_priv(dev);
1581         int ret;
1582
1583         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1584         if (ret < 0)
1585                 goto out;
1586
1587         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1588             (advertising & ADVERTISED_1000baseT_Full)) {
1589                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1590         }
1591 out:
1592         return ret;
1593 }
1594
1595 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1596 {
1597         struct rtl8169_private *tp = netdev_priv(dev);
1598         int ret;
1599
1600         del_timer_sync(&tp->timer);
1601
1602         rtl_lock_work(tp);
1603         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1604                                 cmd->duplex, cmd->advertising);
1605         rtl_unlock_work(tp);
1606
1607         return ret;
1608 }
1609
1610 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1611         netdev_features_t features)
1612 {
1613         struct rtl8169_private *tp = netdev_priv(dev);
1614
1615         if (dev->mtu > TD_MSS_MAX)
1616                 features &= ~NETIF_F_ALL_TSO;
1617
1618         if (dev->mtu > JUMBO_1K &&
1619             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1620                 features &= ~NETIF_F_IP_CSUM;
1621
1622         return features;
1623 }
1624
1625 static void __rtl8169_set_features(struct net_device *dev,
1626                                    netdev_features_t features)
1627 {
1628         struct rtl8169_private *tp = netdev_priv(dev);
1629         netdev_features_t changed = features ^ dev->features;
1630         void __iomem *ioaddr = tp->mmio_addr;
1631
1632         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1633                 return;
1634
1635         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1636                 if (features & NETIF_F_RXCSUM)
1637                         tp->cp_cmd |= RxChkSum;
1638                 else
1639                         tp->cp_cmd &= ~RxChkSum;
1640
1641                 if (dev->features & NETIF_F_HW_VLAN_RX)
1642                         tp->cp_cmd |= RxVlan;
1643                 else
1644                         tp->cp_cmd &= ~RxVlan;
1645
1646                 RTL_W16(CPlusCmd, tp->cp_cmd);
1647                 RTL_R16(CPlusCmd);
1648         }
1649         if (changed & NETIF_F_RXALL) {
1650                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1651                 if (features & NETIF_F_RXALL)
1652                         tmp |= (AcceptErr | AcceptRunt);
1653                 RTL_W32(RxConfig, tmp);
1654         }
1655 }
1656
1657 static int rtl8169_set_features(struct net_device *dev,
1658                                 netdev_features_t features)
1659 {
1660         struct rtl8169_private *tp = netdev_priv(dev);
1661
1662         rtl_lock_work(tp);
1663         __rtl8169_set_features(dev, features);
1664         rtl_unlock_work(tp);
1665
1666         return 0;
1667 }
1668
1669
1670 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1671                                       struct sk_buff *skb)
1672 {
1673         return (vlan_tx_tag_present(skb)) ?
1674                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1675 }
1676
1677 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1678 {
1679         u32 opts2 = le32_to_cpu(desc->opts2);
1680
1681         if (opts2 & RxVlanTag)
1682                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1683
1684         desc->opts2 = 0;
1685 }
1686
1687 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1688 {
1689         struct rtl8169_private *tp = netdev_priv(dev);
1690         void __iomem *ioaddr = tp->mmio_addr;
1691         u32 status;
1692
1693         cmd->supported =
1694                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1695         cmd->port = PORT_FIBRE;
1696         cmd->transceiver = XCVR_INTERNAL;
1697
1698         status = RTL_R32(TBICSR);
1699         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1700         cmd->autoneg = !!(status & TBINwEnable);
1701
1702         ethtool_cmd_speed_set(cmd, SPEED_1000);
1703         cmd->duplex = DUPLEX_FULL; /* Always set */
1704
1705         return 0;
1706 }
1707
1708 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1709 {
1710         struct rtl8169_private *tp = netdev_priv(dev);
1711
1712         return mii_ethtool_gset(&tp->mii, cmd);
1713 }
1714
1715 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1716 {
1717         struct rtl8169_private *tp = netdev_priv(dev);
1718         int rc;
1719
1720         rtl_lock_work(tp);
1721         rc = tp->get_settings(dev, cmd);
1722         rtl_unlock_work(tp);
1723
1724         return rc;
1725 }
1726
1727 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1728                              void *p)
1729 {
1730         struct rtl8169_private *tp = netdev_priv(dev);
1731
1732         if (regs->len > R8169_REGS_SIZE)
1733                 regs->len = R8169_REGS_SIZE;
1734
1735         rtl_lock_work(tp);
1736         memcpy_fromio(p, tp->mmio_addr, regs->len);
1737         rtl_unlock_work(tp);
1738 }
1739
1740 static u32 rtl8169_get_msglevel(struct net_device *dev)
1741 {
1742         struct rtl8169_private *tp = netdev_priv(dev);
1743
1744         return tp->msg_enable;
1745 }
1746
1747 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1748 {
1749         struct rtl8169_private *tp = netdev_priv(dev);
1750
1751         tp->msg_enable = value;
1752 }
1753
1754 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1755         "tx_packets",
1756         "rx_packets",
1757         "tx_errors",
1758         "rx_errors",
1759         "rx_missed",
1760         "align_errors",
1761         "tx_single_collisions",
1762         "tx_multi_collisions",
1763         "unicast",
1764         "broadcast",
1765         "multicast",
1766         "tx_aborted",
1767         "tx_underrun",
1768 };
1769
1770 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1771 {
1772         switch (sset) {
1773         case ETH_SS_STATS:
1774                 return ARRAY_SIZE(rtl8169_gstrings);
1775         default:
1776                 return -EOPNOTSUPP;
1777         }
1778 }
1779
1780 static void rtl8169_update_counters(struct net_device *dev)
1781 {
1782         struct rtl8169_private *tp = netdev_priv(dev);
1783         void __iomem *ioaddr = tp->mmio_addr;
1784         struct device *d = &tp->pci_dev->dev;
1785         struct rtl8169_counters *counters;
1786         dma_addr_t paddr;
1787         u32 cmd;
1788         int wait = 1000;
1789
1790         /*
1791          * Some chips are unable to dump tally counters when the receiver
1792          * is disabled.
1793          */
1794         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1795                 return;
1796
1797         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1798         if (!counters)
1799                 return;
1800
1801         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1802         cmd = (u64)paddr & DMA_BIT_MASK(32);
1803         RTL_W32(CounterAddrLow, cmd);
1804         RTL_W32(CounterAddrLow, cmd | CounterDump);
1805
1806         while (wait--) {
1807                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1808                         memcpy(&tp->counters, counters, sizeof(*counters));
1809                         break;
1810                 }
1811                 udelay(10);
1812         }
1813
1814         RTL_W32(CounterAddrLow, 0);
1815         RTL_W32(CounterAddrHigh, 0);
1816
1817         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1818 }
1819
1820 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1821                                       struct ethtool_stats *stats, u64 *data)
1822 {
1823         struct rtl8169_private *tp = netdev_priv(dev);
1824
1825         ASSERT_RTNL();
1826
1827         rtl8169_update_counters(dev);
1828
1829         data[0] = le64_to_cpu(tp->counters.tx_packets);
1830         data[1] = le64_to_cpu(tp->counters.rx_packets);
1831         data[2] = le64_to_cpu(tp->counters.tx_errors);
1832         data[3] = le32_to_cpu(tp->counters.rx_errors);
1833         data[4] = le16_to_cpu(tp->counters.rx_missed);
1834         data[5] = le16_to_cpu(tp->counters.align_errors);
1835         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1836         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1837         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1838         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1839         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1840         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1841         data[12] = le16_to_cpu(tp->counters.tx_underun);
1842 }
1843
1844 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1845 {
1846         switch(stringset) {
1847         case ETH_SS_STATS:
1848                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1849                 break;
1850         }
1851 }
1852
1853 static const struct ethtool_ops rtl8169_ethtool_ops = {
1854         .get_drvinfo            = rtl8169_get_drvinfo,
1855         .get_regs_len           = rtl8169_get_regs_len,
1856         .get_link               = ethtool_op_get_link,
1857         .get_settings           = rtl8169_get_settings,
1858         .set_settings           = rtl8169_set_settings,
1859         .get_msglevel           = rtl8169_get_msglevel,
1860         .set_msglevel           = rtl8169_set_msglevel,
1861         .get_regs               = rtl8169_get_regs,
1862         .get_wol                = rtl8169_get_wol,
1863         .set_wol                = rtl8169_set_wol,
1864         .get_strings            = rtl8169_get_strings,
1865         .get_sset_count         = rtl8169_get_sset_count,
1866         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1867 };
1868
1869 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1870                                     struct net_device *dev, u8 default_version)
1871 {
1872         void __iomem *ioaddr = tp->mmio_addr;
1873         /*
1874          * The driver currently handles the 8168Bf and the 8168Be identically
1875          * but they can be identified more specifically through the test below
1876          * if needed:
1877          *
1878          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1879          *
1880          * Same thing for the 8101Eb and the 8101Ec:
1881          *
1882          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1883          */
1884         static const struct rtl_mac_info {
1885                 u32 mask;
1886                 u32 val;
1887                 int mac_version;
1888         } mac_info[] = {
1889                 /* 8168F family. */
1890                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1891                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1892
1893                 /* 8168E family. */
1894                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1895                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1896                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1897                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1898
1899                 /* 8168D family. */
1900                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1901                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1902                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1903
1904                 /* 8168DP family. */
1905                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1906                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1907                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1908
1909                 /* 8168C family. */
1910                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1911                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1912                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1913                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1914                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1915                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1916                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1917                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1918                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1919
1920                 /* 8168B family. */
1921                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1922                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1923                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1924                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1925
1926                 /* 8101 family. */
1927                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1928                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1929                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1930                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1931                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1932                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1933                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1934                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1935                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1936                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1937                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1938                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1939                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1940                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1941                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1942                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1943                 /* FIXME: where did these entries come from ? -- FR */
1944                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1945                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1946
1947                 /* 8110 family. */
1948                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1949                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1950                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1951                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1952                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1953                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1954
1955                 /* Catch-all */
1956                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1957         };
1958         const struct rtl_mac_info *p = mac_info;
1959         u32 reg;
1960
1961         reg = RTL_R32(TxConfig);
1962         while ((reg & p->mask) != p->val)
1963                 p++;
1964         tp->mac_version = p->mac_version;
1965
1966         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1967                 netif_notice(tp, probe, dev,
1968                              "unknown MAC, using family default\n");
1969                 tp->mac_version = default_version;
1970         }
1971 }
1972
1973 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1974 {
1975         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1976 }
1977
1978 struct phy_reg {
1979         u16 reg;
1980         u16 val;
1981 };
1982
1983 static void rtl_writephy_batch(struct rtl8169_private *tp,
1984                                const struct phy_reg *regs, int len)
1985 {
1986         while (len-- > 0) {
1987                 rtl_writephy(tp, regs->reg, regs->val);
1988                 regs++;
1989         }
1990 }
1991
1992 #define PHY_READ                0x00000000
1993 #define PHY_DATA_OR             0x10000000
1994 #define PHY_DATA_AND            0x20000000
1995 #define PHY_BJMPN               0x30000000
1996 #define PHY_READ_EFUSE          0x40000000
1997 #define PHY_READ_MAC_BYTE       0x50000000
1998 #define PHY_WRITE_MAC_BYTE      0x60000000
1999 #define PHY_CLEAR_READCOUNT     0x70000000
2000 #define PHY_WRITE               0x80000000
2001 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2002 #define PHY_COMP_EQ_SKIPN       0xa0000000
2003 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2004 #define PHY_WRITE_PREVIOUS      0xc0000000
2005 #define PHY_SKIPN               0xd0000000
2006 #define PHY_DELAY_MS            0xe0000000
2007 #define PHY_WRITE_ERI_WORD      0xf0000000
2008
2009 struct fw_info {
2010         u32     magic;
2011         char    version[RTL_VER_SIZE];
2012         __le32  fw_start;
2013         __le32  fw_len;
2014         u8      chksum;
2015 } __packed;
2016
2017 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2018
2019 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2020 {
2021         const struct firmware *fw = rtl_fw->fw;
2022         struct fw_info *fw_info = (struct fw_info *)fw->data;
2023         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2024         char *version = rtl_fw->version;
2025         bool rc = false;
2026
2027         if (fw->size < FW_OPCODE_SIZE)
2028                 goto out;
2029
2030         if (!fw_info->magic) {
2031                 size_t i, size, start;
2032                 u8 checksum = 0;
2033
2034                 if (fw->size < sizeof(*fw_info))
2035                         goto out;
2036
2037                 for (i = 0; i < fw->size; i++)
2038                         checksum += fw->data[i];
2039                 if (checksum != 0)
2040                         goto out;
2041
2042                 start = le32_to_cpu(fw_info->fw_start);
2043                 if (start > fw->size)
2044                         goto out;
2045
2046                 size = le32_to_cpu(fw_info->fw_len);
2047                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2048                         goto out;
2049
2050                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2051
2052                 pa->code = (__le32 *)(fw->data + start);
2053                 pa->size = size;
2054         } else {
2055                 if (fw->size % FW_OPCODE_SIZE)
2056                         goto out;
2057
2058                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2059
2060                 pa->code = (__le32 *)fw->data;
2061                 pa->size = fw->size / FW_OPCODE_SIZE;
2062         }
2063         version[RTL_VER_SIZE - 1] = 0;
2064
2065         rc = true;
2066 out:
2067         return rc;
2068 }
2069
2070 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2071                            struct rtl_fw_phy_action *pa)
2072 {
2073         bool rc = false;
2074         size_t index;
2075
2076         for (index = 0; index < pa->size; index++) {
2077                 u32 action = le32_to_cpu(pa->code[index]);
2078                 u32 regno = (action & 0x0fff0000) >> 16;
2079
2080                 switch(action & 0xf0000000) {
2081                 case PHY_READ:
2082                 case PHY_DATA_OR:
2083                 case PHY_DATA_AND:
2084                 case PHY_READ_EFUSE:
2085                 case PHY_CLEAR_READCOUNT:
2086                 case PHY_WRITE:
2087                 case PHY_WRITE_PREVIOUS:
2088                 case PHY_DELAY_MS:
2089                         break;
2090
2091                 case PHY_BJMPN:
2092                         if (regno > index) {
2093                                 netif_err(tp, ifup, tp->dev,
2094                                           "Out of range of firmware\n");
2095                                 goto out;
2096                         }
2097                         break;
2098                 case PHY_READCOUNT_EQ_SKIP:
2099                         if (index + 2 >= pa->size) {
2100                                 netif_err(tp, ifup, tp->dev,
2101                                           "Out of range of firmware\n");
2102                                 goto out;
2103                         }
2104                         break;
2105                 case PHY_COMP_EQ_SKIPN:
2106                 case PHY_COMP_NEQ_SKIPN:
2107                 case PHY_SKIPN:
2108                         if (index + 1 + regno >= pa->size) {
2109                                 netif_err(tp, ifup, tp->dev,
2110                                           "Out of range of firmware\n");
2111                                 goto out;
2112                         }
2113                         break;
2114
2115                 case PHY_READ_MAC_BYTE:
2116                 case PHY_WRITE_MAC_BYTE:
2117                 case PHY_WRITE_ERI_WORD:
2118                 default:
2119                         netif_err(tp, ifup, tp->dev,
2120                                   "Invalid action 0x%08x\n", action);
2121                         goto out;
2122                 }
2123         }
2124         rc = true;
2125 out:
2126         return rc;
2127 }
2128
2129 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2130 {
2131         struct net_device *dev = tp->dev;
2132         int rc = -EINVAL;
2133
2134         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2135                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2136                 goto out;
2137         }
2138
2139         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2140                 rc = 0;
2141 out:
2142         return rc;
2143 }
2144
2145 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2146 {
2147         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2148         u32 predata, count;
2149         size_t index;
2150
2151         predata = count = 0;
2152
2153         for (index = 0; index < pa->size; ) {
2154                 u32 action = le32_to_cpu(pa->code[index]);
2155                 u32 data = action & 0x0000ffff;
2156                 u32 regno = (action & 0x0fff0000) >> 16;
2157
2158                 if (!action)
2159                         break;
2160
2161                 switch(action & 0xf0000000) {
2162                 case PHY_READ:
2163                         predata = rtl_readphy(tp, regno);
2164                         count++;
2165                         index++;
2166                         break;
2167                 case PHY_DATA_OR:
2168                         predata |= data;
2169                         index++;
2170                         break;
2171                 case PHY_DATA_AND:
2172                         predata &= data;
2173                         index++;
2174                         break;
2175                 case PHY_BJMPN:
2176                         index -= regno;
2177                         break;
2178                 case PHY_READ_EFUSE:
2179                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2180                         index++;
2181                         break;
2182                 case PHY_CLEAR_READCOUNT:
2183                         count = 0;
2184                         index++;
2185                         break;
2186                 case PHY_WRITE:
2187                         rtl_writephy(tp, regno, data);
2188                         index++;
2189                         break;
2190                 case PHY_READCOUNT_EQ_SKIP:
2191                         index += (count == data) ? 2 : 1;
2192                         break;
2193                 case PHY_COMP_EQ_SKIPN:
2194                         if (predata == data)
2195                                 index += regno;
2196                         index++;
2197                         break;
2198                 case PHY_COMP_NEQ_SKIPN:
2199                         if (predata != data)
2200                                 index += regno;
2201                         index++;
2202                         break;
2203                 case PHY_WRITE_PREVIOUS:
2204                         rtl_writephy(tp, regno, predata);
2205                         index++;
2206                         break;
2207                 case PHY_SKIPN:
2208                         index += regno + 1;
2209                         break;
2210                 case PHY_DELAY_MS:
2211                         mdelay(data);
2212                         index++;
2213                         break;
2214
2215                 case PHY_READ_MAC_BYTE:
2216                 case PHY_WRITE_MAC_BYTE:
2217                 case PHY_WRITE_ERI_WORD:
2218                 default:
2219                         BUG();
2220                 }
2221         }
2222 }
2223
2224 static void rtl_release_firmware(struct rtl8169_private *tp)
2225 {
2226         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2227                 release_firmware(tp->rtl_fw->fw);
2228                 kfree(tp->rtl_fw);
2229         }
2230         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2231 }
2232
2233 static void rtl_apply_firmware(struct rtl8169_private *tp)
2234 {
2235         struct rtl_fw *rtl_fw = tp->rtl_fw;
2236
2237         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2238         if (!IS_ERR_OR_NULL(rtl_fw))
2239                 rtl_phy_write_fw(tp, rtl_fw);
2240 }
2241
2242 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2243 {
2244         if (rtl_readphy(tp, reg) != val)
2245                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2246         else
2247                 rtl_apply_firmware(tp);
2248 }
2249
2250 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2251 {
2252         static const struct phy_reg phy_reg_init[] = {
2253                 { 0x1f, 0x0001 },
2254                 { 0x06, 0x006e },
2255                 { 0x08, 0x0708 },
2256                 { 0x15, 0x4000 },
2257                 { 0x18, 0x65c7 },
2258
2259                 { 0x1f, 0x0001 },
2260                 { 0x03, 0x00a1 },
2261                 { 0x02, 0x0008 },
2262                 { 0x01, 0x0120 },
2263                 { 0x00, 0x1000 },
2264                 { 0x04, 0x0800 },
2265                 { 0x04, 0x0000 },
2266
2267                 { 0x03, 0xff41 },
2268                 { 0x02, 0xdf60 },
2269                 { 0x01, 0x0140 },
2270                 { 0x00, 0x0077 },
2271                 { 0x04, 0x7800 },
2272                 { 0x04, 0x7000 },
2273
2274                 { 0x03, 0x802f },
2275                 { 0x02, 0x4f02 },
2276                 { 0x01, 0x0409 },
2277                 { 0x00, 0xf0f9 },
2278                 { 0x04, 0x9800 },
2279                 { 0x04, 0x9000 },
2280
2281                 { 0x03, 0xdf01 },
2282                 { 0x02, 0xdf20 },
2283                 { 0x01, 0xff95 },
2284                 { 0x00, 0xba00 },
2285                 { 0x04, 0xa800 },
2286                 { 0x04, 0xa000 },
2287
2288                 { 0x03, 0xff41 },
2289                 { 0x02, 0xdf20 },
2290                 { 0x01, 0x0140 },
2291                 { 0x00, 0x00bb },
2292                 { 0x04, 0xb800 },
2293                 { 0x04, 0xb000 },
2294
2295                 { 0x03, 0xdf41 },
2296                 { 0x02, 0xdc60 },
2297                 { 0x01, 0x6340 },
2298                 { 0x00, 0x007d },
2299                 { 0x04, 0xd800 },
2300                 { 0x04, 0xd000 },
2301
2302                 { 0x03, 0xdf01 },
2303                 { 0x02, 0xdf20 },
2304                 { 0x01, 0x100a },
2305                 { 0x00, 0xa0ff },
2306                 { 0x04, 0xf800 },
2307                 { 0x04, 0xf000 },
2308
2309                 { 0x1f, 0x0000 },
2310                 { 0x0b, 0x0000 },
2311                 { 0x00, 0x9200 }
2312         };
2313
2314         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2315 }
2316
2317 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2318 {
2319         static const struct phy_reg phy_reg_init[] = {
2320                 { 0x1f, 0x0002 },
2321                 { 0x01, 0x90d0 },
2322                 { 0x1f, 0x0000 }
2323         };
2324
2325         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2326 }
2327
2328 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2329 {
2330         struct pci_dev *pdev = tp->pci_dev;
2331
2332         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2333             (pdev->subsystem_device != 0xe000))
2334                 return;
2335
2336         rtl_writephy(tp, 0x1f, 0x0001);
2337         rtl_writephy(tp, 0x10, 0xf01b);
2338         rtl_writephy(tp, 0x1f, 0x0000);
2339 }
2340
2341 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2342 {
2343         static const struct phy_reg phy_reg_init[] = {
2344                 { 0x1f, 0x0001 },
2345                 { 0x04, 0x0000 },
2346                 { 0x03, 0x00a1 },
2347                 { 0x02, 0x0008 },
2348                 { 0x01, 0x0120 },
2349                 { 0x00, 0x1000 },
2350                 { 0x04, 0x0800 },
2351                 { 0x04, 0x9000 },
2352                 { 0x03, 0x802f },
2353                 { 0x02, 0x4f02 },
2354                 { 0x01, 0x0409 },
2355                 { 0x00, 0xf099 },
2356                 { 0x04, 0x9800 },
2357                 { 0x04, 0xa000 },
2358                 { 0x03, 0xdf01 },
2359                 { 0x02, 0xdf20 },
2360                 { 0x01, 0xff95 },
2361                 { 0x00, 0xba00 },
2362                 { 0x04, 0xa800 },
2363                 { 0x04, 0xf000 },
2364                 { 0x03, 0xdf01 },
2365                 { 0x02, 0xdf20 },
2366                 { 0x01, 0x101a },
2367                 { 0x00, 0xa0ff },
2368                 { 0x04, 0xf800 },
2369                 { 0x04, 0x0000 },
2370                 { 0x1f, 0x0000 },
2371
2372                 { 0x1f, 0x0001 },
2373                 { 0x10, 0xf41b },
2374                 { 0x14, 0xfb54 },
2375                 { 0x18, 0xf5c7 },
2376                 { 0x1f, 0x0000 },
2377
2378                 { 0x1f, 0x0001 },
2379                 { 0x17, 0x0cc0 },
2380                 { 0x1f, 0x0000 }
2381         };
2382
2383         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2384
2385         rtl8169scd_hw_phy_config_quirk(tp);
2386 }
2387
2388 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2389 {
2390         static const struct phy_reg phy_reg_init[] = {
2391                 { 0x1f, 0x0001 },
2392                 { 0x04, 0x0000 },
2393                 { 0x03, 0x00a1 },
2394                 { 0x02, 0x0008 },
2395                 { 0x01, 0x0120 },
2396                 { 0x00, 0x1000 },
2397                 { 0x04, 0x0800 },
2398                 { 0x04, 0x9000 },
2399                 { 0x03, 0x802f },
2400                 { 0x02, 0x4f02 },
2401                 { 0x01, 0x0409 },
2402                 { 0x00, 0xf099 },
2403                 { 0x04, 0x9800 },
2404                 { 0x04, 0xa000 },
2405                 { 0x03, 0xdf01 },
2406                 { 0x02, 0xdf20 },
2407                 { 0x01, 0xff95 },
2408                 { 0x00, 0xba00 },
2409                 { 0x04, 0xa800 },
2410                 { 0x04, 0xf000 },
2411                 { 0x03, 0xdf01 },
2412                 { 0x02, 0xdf20 },
2413                 { 0x01, 0x101a },
2414                 { 0x00, 0xa0ff },
2415                 { 0x04, 0xf800 },
2416                 { 0x04, 0x0000 },
2417                 { 0x1f, 0x0000 },
2418
2419                 { 0x1f, 0x0001 },
2420                 { 0x0b, 0x8480 },
2421                 { 0x1f, 0x0000 },
2422
2423                 { 0x1f, 0x0001 },
2424                 { 0x18, 0x67c7 },
2425                 { 0x04, 0x2000 },
2426                 { 0x03, 0x002f },
2427                 { 0x02, 0x4360 },
2428                 { 0x01, 0x0109 },
2429                 { 0x00, 0x3022 },
2430                 { 0x04, 0x2800 },
2431                 { 0x1f, 0x0000 },
2432
2433                 { 0x1f, 0x0001 },
2434                 { 0x17, 0x0cc0 },
2435                 { 0x1f, 0x0000 }
2436         };
2437
2438         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2439 }
2440
2441 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2442 {
2443         static const struct phy_reg phy_reg_init[] = {
2444                 { 0x10, 0xf41b },
2445                 { 0x1f, 0x0000 }
2446         };
2447
2448         rtl_writephy(tp, 0x1f, 0x0001);
2449         rtl_patchphy(tp, 0x16, 1 << 0);
2450
2451         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2452 }
2453
2454 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2455 {
2456         static const struct phy_reg phy_reg_init[] = {
2457                 { 0x1f, 0x0001 },
2458                 { 0x10, 0xf41b },
2459                 { 0x1f, 0x0000 }
2460         };
2461
2462         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2463 }
2464
2465 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2466 {
2467         static const struct phy_reg phy_reg_init[] = {
2468                 { 0x1f, 0x0000 },
2469                 { 0x1d, 0x0f00 },
2470                 { 0x1f, 0x0002 },
2471                 { 0x0c, 0x1ec8 },
2472                 { 0x1f, 0x0000 }
2473         };
2474
2475         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2476 }
2477
2478 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2479 {
2480         static const struct phy_reg phy_reg_init[] = {
2481                 { 0x1f, 0x0001 },
2482                 { 0x1d, 0x3d98 },
2483                 { 0x1f, 0x0000 }
2484         };
2485
2486         rtl_writephy(tp, 0x1f, 0x0000);
2487         rtl_patchphy(tp, 0x14, 1 << 5);
2488         rtl_patchphy(tp, 0x0d, 1 << 5);
2489
2490         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2491 }
2492
2493 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2494 {
2495         static const struct phy_reg phy_reg_init[] = {
2496                 { 0x1f, 0x0001 },
2497                 { 0x12, 0x2300 },
2498                 { 0x1f, 0x0002 },
2499                 { 0x00, 0x88d4 },
2500                 { 0x01, 0x82b1 },
2501                 { 0x03, 0x7002 },
2502                 { 0x08, 0x9e30 },
2503                 { 0x09, 0x01f0 },
2504                 { 0x0a, 0x5500 },
2505                 { 0x0c, 0x00c8 },
2506                 { 0x1f, 0x0003 },
2507                 { 0x12, 0xc096 },
2508                 { 0x16, 0x000a },
2509                 { 0x1f, 0x0000 },
2510                 { 0x1f, 0x0000 },
2511                 { 0x09, 0x2000 },
2512                 { 0x09, 0x0000 }
2513         };
2514
2515         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2516
2517         rtl_patchphy(tp, 0x14, 1 << 5);
2518         rtl_patchphy(tp, 0x0d, 1 << 5);
2519         rtl_writephy(tp, 0x1f, 0x0000);
2520 }
2521
2522 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2523 {
2524         static const struct phy_reg phy_reg_init[] = {
2525                 { 0x1f, 0x0001 },
2526                 { 0x12, 0x2300 },
2527                 { 0x03, 0x802f },
2528                 { 0x02, 0x4f02 },
2529                 { 0x01, 0x0409 },
2530                 { 0x00, 0xf099 },
2531                 { 0x04, 0x9800 },
2532                 { 0x04, 0x9000 },
2533                 { 0x1d, 0x3d98 },
2534                 { 0x1f, 0x0002 },
2535                 { 0x0c, 0x7eb8 },
2536                 { 0x06, 0x0761 },
2537                 { 0x1f, 0x0003 },
2538                 { 0x16, 0x0f0a },
2539                 { 0x1f, 0x0000 }
2540         };
2541
2542         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2543
2544         rtl_patchphy(tp, 0x16, 1 << 0);
2545         rtl_patchphy(tp, 0x14, 1 << 5);
2546         rtl_patchphy(tp, 0x0d, 1 << 5);
2547         rtl_writephy(tp, 0x1f, 0x0000);
2548 }
2549
2550 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2551 {
2552         static const struct phy_reg phy_reg_init[] = {
2553                 { 0x1f, 0x0001 },
2554                 { 0x12, 0x2300 },
2555                 { 0x1d, 0x3d98 },
2556                 { 0x1f, 0x0002 },
2557                 { 0x0c, 0x7eb8 },
2558                 { 0x06, 0x5461 },
2559                 { 0x1f, 0x0003 },
2560                 { 0x16, 0x0f0a },
2561                 { 0x1f, 0x0000 }
2562         };
2563
2564         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2565
2566         rtl_patchphy(tp, 0x16, 1 << 0);
2567         rtl_patchphy(tp, 0x14, 1 << 5);
2568         rtl_patchphy(tp, 0x0d, 1 << 5);
2569         rtl_writephy(tp, 0x1f, 0x0000);
2570 }
2571
2572 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2573 {
2574         rtl8168c_3_hw_phy_config(tp);
2575 }
2576
2577 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2578 {
2579         static const struct phy_reg phy_reg_init_0[] = {
2580                 /* Channel Estimation */
2581                 { 0x1f, 0x0001 },
2582                 { 0x06, 0x4064 },
2583                 { 0x07, 0x2863 },
2584                 { 0x08, 0x059c },
2585                 { 0x09, 0x26b4 },
2586                 { 0x0a, 0x6a19 },
2587                 { 0x0b, 0xdcc8 },
2588                 { 0x10, 0xf06d },
2589                 { 0x14, 0x7f68 },
2590                 { 0x18, 0x7fd9 },
2591                 { 0x1c, 0xf0ff },
2592                 { 0x1d, 0x3d9c },
2593                 { 0x1f, 0x0003 },
2594                 { 0x12, 0xf49f },
2595                 { 0x13, 0x070b },
2596                 { 0x1a, 0x05ad },
2597                 { 0x14, 0x94c0 },
2598
2599                 /*
2600                  * Tx Error Issue
2601                  * Enhance line driver power
2602                  */
2603                 { 0x1f, 0x0002 },
2604                 { 0x06, 0x5561 },
2605                 { 0x1f, 0x0005 },
2606                 { 0x05, 0x8332 },
2607                 { 0x06, 0x5561 },
2608
2609                 /*
2610                  * Can not link to 1Gbps with bad cable
2611                  * Decrease SNR threshold form 21.07dB to 19.04dB
2612                  */
2613                 { 0x1f, 0x0001 },
2614                 { 0x17, 0x0cc0 },
2615
2616                 { 0x1f, 0x0000 },
2617                 { 0x0d, 0xf880 }
2618         };
2619         void __iomem *ioaddr = tp->mmio_addr;
2620
2621         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2622
2623         /*
2624          * Rx Error Issue
2625          * Fine Tune Switching regulator parameter
2626          */
2627         rtl_writephy(tp, 0x1f, 0x0002);
2628         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2629         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2630
2631         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2632                 static const struct phy_reg phy_reg_init[] = {
2633                         { 0x1f, 0x0002 },
2634                         { 0x05, 0x669a },
2635                         { 0x1f, 0x0005 },
2636                         { 0x05, 0x8330 },
2637                         { 0x06, 0x669a },
2638                         { 0x1f, 0x0002 }
2639                 };
2640                 int val;
2641
2642                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2643
2644                 val = rtl_readphy(tp, 0x0d);
2645
2646                 if ((val & 0x00ff) != 0x006c) {
2647                         static const u32 set[] = {
2648                                 0x0065, 0x0066, 0x0067, 0x0068,
2649                                 0x0069, 0x006a, 0x006b, 0x006c
2650                         };
2651                         int i;
2652
2653                         rtl_writephy(tp, 0x1f, 0x0002);
2654
2655                         val &= 0xff00;
2656                         for (i = 0; i < ARRAY_SIZE(set); i++)
2657                                 rtl_writephy(tp, 0x0d, val | set[i]);
2658                 }
2659         } else {
2660                 static const struct phy_reg phy_reg_init[] = {
2661                         { 0x1f, 0x0002 },
2662                         { 0x05, 0x6662 },
2663                         { 0x1f, 0x0005 },
2664                         { 0x05, 0x8330 },
2665                         { 0x06, 0x6662 }
2666                 };
2667
2668                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2669         }
2670
2671         /* RSET couple improve */
2672         rtl_writephy(tp, 0x1f, 0x0002);
2673         rtl_patchphy(tp, 0x0d, 0x0300);
2674         rtl_patchphy(tp, 0x0f, 0x0010);
2675
2676         /* Fine tune PLL performance */
2677         rtl_writephy(tp, 0x1f, 0x0002);
2678         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2679         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2680
2681         rtl_writephy(tp, 0x1f, 0x0005);
2682         rtl_writephy(tp, 0x05, 0x001b);
2683
2684         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2685
2686         rtl_writephy(tp, 0x1f, 0x0000);
2687 }
2688
2689 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2690 {
2691         static const struct phy_reg phy_reg_init_0[] = {
2692                 /* Channel Estimation */
2693                 { 0x1f, 0x0001 },
2694                 { 0x06, 0x4064 },
2695                 { 0x07, 0x2863 },
2696                 { 0x08, 0x059c },
2697                 { 0x09, 0x26b4 },
2698                 { 0x0a, 0x6a19 },
2699                 { 0x0b, 0xdcc8 },
2700                 { 0x10, 0xf06d },
2701                 { 0x14, 0x7f68 },
2702                 { 0x18, 0x7fd9 },
2703                 { 0x1c, 0xf0ff },
2704                 { 0x1d, 0x3d9c },
2705                 { 0x1f, 0x0003 },
2706                 { 0x12, 0xf49f },
2707                 { 0x13, 0x070b },
2708                 { 0x1a, 0x05ad },
2709                 { 0x14, 0x94c0 },
2710
2711                 /*
2712                  * Tx Error Issue
2713                  * Enhance line driver power
2714                  */
2715                 { 0x1f, 0x0002 },
2716                 { 0x06, 0x5561 },
2717                 { 0x1f, 0x0005 },
2718                 { 0x05, 0x8332 },
2719                 { 0x06, 0x5561 },
2720
2721                 /*
2722                  * Can not link to 1Gbps with bad cable
2723                  * Decrease SNR threshold form 21.07dB to 19.04dB
2724                  */
2725                 { 0x1f, 0x0001 },
2726                 { 0x17, 0x0cc0 },
2727
2728                 { 0x1f, 0x0000 },
2729                 { 0x0d, 0xf880 }
2730         };
2731         void __iomem *ioaddr = tp->mmio_addr;
2732
2733         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2734
2735         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2736                 static const struct phy_reg phy_reg_init[] = {
2737                         { 0x1f, 0x0002 },
2738                         { 0x05, 0x669a },
2739                         { 0x1f, 0x0005 },
2740                         { 0x05, 0x8330 },
2741                         { 0x06, 0x669a },
2742
2743                         { 0x1f, 0x0002 }
2744                 };
2745                 int val;
2746
2747                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2748
2749                 val = rtl_readphy(tp, 0x0d);
2750                 if ((val & 0x00ff) != 0x006c) {
2751                         static const u32 set[] = {
2752                                 0x0065, 0x0066, 0x0067, 0x0068,
2753                                 0x0069, 0x006a, 0x006b, 0x006c
2754                         };
2755                         int i;
2756
2757                         rtl_writephy(tp, 0x1f, 0x0002);
2758
2759                         val &= 0xff00;
2760                         for (i = 0; i < ARRAY_SIZE(set); i++)
2761                                 rtl_writephy(tp, 0x0d, val | set[i]);
2762                 }
2763         } else {
2764                 static const struct phy_reg phy_reg_init[] = {
2765                         { 0x1f, 0x0002 },
2766                         { 0x05, 0x2642 },
2767                         { 0x1f, 0x0005 },
2768                         { 0x05, 0x8330 },
2769                         { 0x06, 0x2642 }
2770                 };
2771
2772                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2773         }
2774
2775         /* Fine tune PLL performance */
2776         rtl_writephy(tp, 0x1f, 0x0002);
2777         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2778         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2779
2780         /* Switching regulator Slew rate */
2781         rtl_writephy(tp, 0x1f, 0x0002);
2782         rtl_patchphy(tp, 0x0f, 0x0017);
2783
2784         rtl_writephy(tp, 0x1f, 0x0005);
2785         rtl_writephy(tp, 0x05, 0x001b);
2786
2787         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2788
2789         rtl_writephy(tp, 0x1f, 0x0000);
2790 }
2791
2792 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2793 {
2794         static const struct phy_reg phy_reg_init[] = {
2795                 { 0x1f, 0x0002 },
2796                 { 0x10, 0x0008 },
2797                 { 0x0d, 0x006c },
2798
2799                 { 0x1f, 0x0000 },
2800                 { 0x0d, 0xf880 },
2801
2802                 { 0x1f, 0x0001 },
2803                 { 0x17, 0x0cc0 },
2804
2805                 { 0x1f, 0x0001 },
2806                 { 0x0b, 0xa4d8 },
2807                 { 0x09, 0x281c },
2808                 { 0x07, 0x2883 },
2809                 { 0x0a, 0x6b35 },
2810                 { 0x1d, 0x3da4 },
2811                 { 0x1c, 0xeffd },
2812                 { 0x14, 0x7f52 },
2813                 { 0x18, 0x7fc6 },
2814                 { 0x08, 0x0601 },
2815                 { 0x06, 0x4063 },
2816                 { 0x10, 0xf074 },
2817                 { 0x1f, 0x0003 },
2818                 { 0x13, 0x0789 },
2819                 { 0x12, 0xf4bd },
2820                 { 0x1a, 0x04fd },
2821                 { 0x14, 0x84b0 },
2822                 { 0x1f, 0x0000 },
2823                 { 0x00, 0x9200 },
2824
2825                 { 0x1f, 0x0005 },
2826                 { 0x01, 0x0340 },
2827                 { 0x1f, 0x0001 },
2828                 { 0x04, 0x4000 },
2829                 { 0x03, 0x1d21 },
2830                 { 0x02, 0x0c32 },
2831                 { 0x01, 0x0200 },
2832                 { 0x00, 0x5554 },
2833                 { 0x04, 0x4800 },
2834                 { 0x04, 0x4000 },
2835                 { 0x04, 0xf000 },
2836                 { 0x03, 0xdf01 },
2837                 { 0x02, 0xdf20 },
2838                 { 0x01, 0x101a },
2839                 { 0x00, 0xa0ff },
2840                 { 0x04, 0xf800 },
2841                 { 0x04, 0xf000 },
2842                 { 0x1f, 0x0000 },
2843
2844                 { 0x1f, 0x0007 },
2845                 { 0x1e, 0x0023 },
2846                 { 0x16, 0x0000 },
2847                 { 0x1f, 0x0000 }
2848         };
2849
2850         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2851 }
2852
2853 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2854 {
2855         static const struct phy_reg phy_reg_init[] = {
2856                 { 0x1f, 0x0001 },
2857                 { 0x17, 0x0cc0 },
2858
2859                 { 0x1f, 0x0007 },
2860                 { 0x1e, 0x002d },
2861                 { 0x18, 0x0040 },
2862                 { 0x1f, 0x0000 }
2863         };
2864
2865         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2866         rtl_patchphy(tp, 0x0d, 1 << 5);
2867 }
2868
2869 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2870 {
2871         static const struct phy_reg phy_reg_init[] = {
2872                 /* Enable Delay cap */
2873                 { 0x1f, 0x0005 },
2874                 { 0x05, 0x8b80 },
2875                 { 0x06, 0xc896 },
2876                 { 0x1f, 0x0000 },
2877
2878                 /* Channel estimation fine tune */
2879                 { 0x1f, 0x0001 },
2880                 { 0x0b, 0x6c20 },
2881                 { 0x07, 0x2872 },
2882                 { 0x1c, 0xefff },
2883                 { 0x1f, 0x0003 },
2884                 { 0x14, 0x6420 },
2885                 { 0x1f, 0x0000 },
2886
2887                 /* Update PFM & 10M TX idle timer */
2888                 { 0x1f, 0x0007 },
2889                 { 0x1e, 0x002f },
2890                 { 0x15, 0x1919 },
2891                 { 0x1f, 0x0000 },
2892
2893                 { 0x1f, 0x0007 },
2894                 { 0x1e, 0x00ac },
2895                 { 0x18, 0x0006 },
2896                 { 0x1f, 0x0000 }
2897         };
2898
2899         rtl_apply_firmware(tp);
2900
2901         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2902
2903         /* DCO enable for 10M IDLE Power */
2904         rtl_writephy(tp, 0x1f, 0x0007);
2905         rtl_writephy(tp, 0x1e, 0x0023);
2906         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2907         rtl_writephy(tp, 0x1f, 0x0000);
2908
2909         /* For impedance matching */
2910         rtl_writephy(tp, 0x1f, 0x0002);
2911         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2912         rtl_writephy(tp, 0x1f, 0x0000);
2913
2914         /* PHY auto speed down */
2915         rtl_writephy(tp, 0x1f, 0x0007);
2916         rtl_writephy(tp, 0x1e, 0x002d);
2917         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2918         rtl_writephy(tp, 0x1f, 0x0000);
2919         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2920
2921         rtl_writephy(tp, 0x1f, 0x0005);
2922         rtl_writephy(tp, 0x05, 0x8b86);
2923         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2924         rtl_writephy(tp, 0x1f, 0x0000);
2925
2926         rtl_writephy(tp, 0x1f, 0x0005);
2927         rtl_writephy(tp, 0x05, 0x8b85);
2928         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2929         rtl_writephy(tp, 0x1f, 0x0007);
2930         rtl_writephy(tp, 0x1e, 0x0020);
2931         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2932         rtl_writephy(tp, 0x1f, 0x0006);
2933         rtl_writephy(tp, 0x00, 0x5a00);
2934         rtl_writephy(tp, 0x1f, 0x0000);
2935         rtl_writephy(tp, 0x0d, 0x0007);
2936         rtl_writephy(tp, 0x0e, 0x003c);
2937         rtl_writephy(tp, 0x0d, 0x4007);
2938         rtl_writephy(tp, 0x0e, 0x0000);
2939         rtl_writephy(tp, 0x0d, 0x0000);
2940 }
2941
2942 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2943 {
2944         static const struct phy_reg phy_reg_init[] = {
2945                 /* Enable Delay cap */
2946                 { 0x1f, 0x0004 },
2947                 { 0x1f, 0x0007 },
2948                 { 0x1e, 0x00ac },
2949                 { 0x18, 0x0006 },
2950                 { 0x1f, 0x0002 },
2951                 { 0x1f, 0x0000 },
2952                 { 0x1f, 0x0000 },
2953
2954                 /* Channel estimation fine tune */
2955                 { 0x1f, 0x0003 },
2956                 { 0x09, 0xa20f },
2957                 { 0x1f, 0x0000 },
2958                 { 0x1f, 0x0000 },
2959
2960                 /* Green Setting */
2961                 { 0x1f, 0x0005 },
2962                 { 0x05, 0x8b5b },
2963                 { 0x06, 0x9222 },
2964                 { 0x05, 0x8b6d },
2965                 { 0x06, 0x8000 },
2966                 { 0x05, 0x8b76 },
2967                 { 0x06, 0x8000 },
2968                 { 0x1f, 0x0000 }
2969         };
2970
2971         rtl_apply_firmware(tp);
2972
2973         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2974
2975         /* For 4-corner performance improve */
2976         rtl_writephy(tp, 0x1f, 0x0005);
2977         rtl_writephy(tp, 0x05, 0x8b80);
2978         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2979         rtl_writephy(tp, 0x1f, 0x0000);
2980
2981         /* PHY auto speed down */
2982         rtl_writephy(tp, 0x1f, 0x0004);
2983         rtl_writephy(tp, 0x1f, 0x0007);
2984         rtl_writephy(tp, 0x1e, 0x002d);
2985         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2986         rtl_writephy(tp, 0x1f, 0x0002);
2987         rtl_writephy(tp, 0x1f, 0x0000);
2988         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2989
2990         /* improve 10M EEE waveform */
2991         rtl_writephy(tp, 0x1f, 0x0005);
2992         rtl_writephy(tp, 0x05, 0x8b86);
2993         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2994         rtl_writephy(tp, 0x1f, 0x0000);
2995
2996         /* Improve 2-pair detection performance */
2997         rtl_writephy(tp, 0x1f, 0x0005);
2998         rtl_writephy(tp, 0x05, 0x8b85);
2999         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3000         rtl_writephy(tp, 0x1f, 0x0000);
3001
3002         /* EEE setting */
3003         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3004                      ERIAR_EXGMAC);
3005         rtl_writephy(tp, 0x1f, 0x0005);
3006         rtl_writephy(tp, 0x05, 0x8b85);
3007         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3008         rtl_writephy(tp, 0x1f, 0x0004);
3009         rtl_writephy(tp, 0x1f, 0x0007);
3010         rtl_writephy(tp, 0x1e, 0x0020);
3011         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3012         rtl_writephy(tp, 0x1f, 0x0002);
3013         rtl_writephy(tp, 0x1f, 0x0000);
3014         rtl_writephy(tp, 0x0d, 0x0007);
3015         rtl_writephy(tp, 0x0e, 0x003c);
3016         rtl_writephy(tp, 0x0d, 0x4007);
3017         rtl_writephy(tp, 0x0e, 0x0000);
3018         rtl_writephy(tp, 0x0d, 0x0000);
3019
3020         /* Green feature */
3021         rtl_writephy(tp, 0x1f, 0x0003);
3022         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3023         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3024         rtl_writephy(tp, 0x1f, 0x0000);
3025 }
3026
3027 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3028 {
3029         static const struct phy_reg phy_reg_init[] = {
3030                 /* Channel estimation fine tune */
3031                 { 0x1f, 0x0003 },
3032                 { 0x09, 0xa20f },
3033                 { 0x1f, 0x0000 },
3034
3035                 /* Modify green table for giga & fnet */
3036                 { 0x1f, 0x0005 },
3037                 { 0x05, 0x8b55 },
3038                 { 0x06, 0x0000 },
3039                 { 0x05, 0x8b5e },
3040                 { 0x06, 0x0000 },
3041                 { 0x05, 0x8b67 },
3042                 { 0x06, 0x0000 },
3043                 { 0x05, 0x8b70 },
3044                 { 0x06, 0x0000 },
3045                 { 0x1f, 0x0000 },
3046                 { 0x1f, 0x0007 },
3047                 { 0x1e, 0x0078 },
3048                 { 0x17, 0x0000 },
3049                 { 0x19, 0x00fb },
3050                 { 0x1f, 0x0000 },
3051
3052                 /* Modify green table for 10M */
3053                 { 0x1f, 0x0005 },
3054                 { 0x05, 0x8b79 },
3055                 { 0x06, 0xaa00 },
3056                 { 0x1f, 0x0000 },
3057
3058                 /* Disable hiimpedance detection (RTCT) */
3059                 { 0x1f, 0x0003 },
3060                 { 0x01, 0x328a },
3061                 { 0x1f, 0x0000 }
3062         };
3063
3064         rtl_apply_firmware(tp);
3065
3066         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3067
3068         /* For 4-corner performance improve */
3069         rtl_writephy(tp, 0x1f, 0x0005);
3070         rtl_writephy(tp, 0x05, 0x8b80);
3071         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3072         rtl_writephy(tp, 0x1f, 0x0000);
3073
3074         /* PHY auto speed down */
3075         rtl_writephy(tp, 0x1f, 0x0007);
3076         rtl_writephy(tp, 0x1e, 0x002d);
3077         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3078         rtl_writephy(tp, 0x1f, 0x0000);
3079         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3080
3081         /* Improve 10M EEE waveform */
3082         rtl_writephy(tp, 0x1f, 0x0005);
3083         rtl_writephy(tp, 0x05, 0x8b86);
3084         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3085         rtl_writephy(tp, 0x1f, 0x0000);
3086
3087         /* Improve 2-pair detection performance */
3088         rtl_writephy(tp, 0x1f, 0x0005);
3089         rtl_writephy(tp, 0x05, 0x8b85);
3090         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3091         rtl_writephy(tp, 0x1f, 0x0000);
3092 }
3093
3094 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3095 {
3096         rtl_apply_firmware(tp);
3097
3098         /* For 4-corner performance improve */
3099         rtl_writephy(tp, 0x1f, 0x0005);
3100         rtl_writephy(tp, 0x05, 0x8b80);
3101         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3102         rtl_writephy(tp, 0x1f, 0x0000);
3103
3104         /* PHY auto speed down */
3105         rtl_writephy(tp, 0x1f, 0x0007);
3106         rtl_writephy(tp, 0x1e, 0x002d);
3107         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3108         rtl_writephy(tp, 0x1f, 0x0000);
3109         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3110
3111         /* Improve 10M EEE waveform */
3112         rtl_writephy(tp, 0x1f, 0x0005);
3113         rtl_writephy(tp, 0x05, 0x8b86);
3114         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3115         rtl_writephy(tp, 0x1f, 0x0000);
3116 }
3117
3118 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3119 {
3120         static const struct phy_reg phy_reg_init[] = {
3121                 { 0x1f, 0x0003 },
3122                 { 0x08, 0x441d },
3123                 { 0x01, 0x9100 },
3124                 { 0x1f, 0x0000 }
3125         };
3126
3127         rtl_writephy(tp, 0x1f, 0x0000);
3128         rtl_patchphy(tp, 0x11, 1 << 12);
3129         rtl_patchphy(tp, 0x19, 1 << 13);
3130         rtl_patchphy(tp, 0x10, 1 << 15);
3131
3132         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3133 }
3134
3135 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3136 {
3137         static const struct phy_reg phy_reg_init[] = {
3138                 { 0x1f, 0x0005 },
3139                 { 0x1a, 0x0000 },
3140                 { 0x1f, 0x0000 },
3141
3142                 { 0x1f, 0x0004 },
3143                 { 0x1c, 0x0000 },
3144                 { 0x1f, 0x0000 },
3145
3146                 { 0x1f, 0x0001 },
3147                 { 0x15, 0x7701 },
3148                 { 0x1f, 0x0000 }
3149         };
3150
3151         /* Disable ALDPS before ram code */
3152         rtl_writephy(tp, 0x1f, 0x0000);
3153         rtl_writephy(tp, 0x18, 0x0310);
3154         msleep(100);
3155
3156         rtl_apply_firmware(tp);
3157
3158         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3159 }
3160
3161 static void rtl_hw_phy_config(struct net_device *dev)
3162 {
3163         struct rtl8169_private *tp = netdev_priv(dev);
3164
3165         rtl8169_print_mac_version(tp);
3166
3167         switch (tp->mac_version) {
3168         case RTL_GIGA_MAC_VER_01:
3169                 break;
3170         case RTL_GIGA_MAC_VER_02:
3171         case RTL_GIGA_MAC_VER_03:
3172                 rtl8169s_hw_phy_config(tp);
3173                 break;
3174         case RTL_GIGA_MAC_VER_04:
3175                 rtl8169sb_hw_phy_config(tp);
3176                 break;
3177         case RTL_GIGA_MAC_VER_05:
3178                 rtl8169scd_hw_phy_config(tp);
3179                 break;
3180         case RTL_GIGA_MAC_VER_06:
3181                 rtl8169sce_hw_phy_config(tp);
3182                 break;
3183         case RTL_GIGA_MAC_VER_07:
3184         case RTL_GIGA_MAC_VER_08:
3185         case RTL_GIGA_MAC_VER_09:
3186                 rtl8102e_hw_phy_config(tp);
3187                 break;
3188         case RTL_GIGA_MAC_VER_11:
3189                 rtl8168bb_hw_phy_config(tp);
3190                 break;
3191         case RTL_GIGA_MAC_VER_12:
3192                 rtl8168bef_hw_phy_config(tp);
3193                 break;
3194         case RTL_GIGA_MAC_VER_17:
3195                 rtl8168bef_hw_phy_config(tp);
3196                 break;
3197         case RTL_GIGA_MAC_VER_18:
3198                 rtl8168cp_1_hw_phy_config(tp);
3199                 break;
3200         case RTL_GIGA_MAC_VER_19:
3201                 rtl8168c_1_hw_phy_config(tp);
3202                 break;
3203         case RTL_GIGA_MAC_VER_20:
3204                 rtl8168c_2_hw_phy_config(tp);
3205                 break;
3206         case RTL_GIGA_MAC_VER_21:
3207                 rtl8168c_3_hw_phy_config(tp);
3208                 break;
3209         case RTL_GIGA_MAC_VER_22:
3210                 rtl8168c_4_hw_phy_config(tp);
3211                 break;
3212         case RTL_GIGA_MAC_VER_23:
3213         case RTL_GIGA_MAC_VER_24:
3214                 rtl8168cp_2_hw_phy_config(tp);
3215                 break;
3216         case RTL_GIGA_MAC_VER_25:
3217                 rtl8168d_1_hw_phy_config(tp);
3218                 break;
3219         case RTL_GIGA_MAC_VER_26:
3220                 rtl8168d_2_hw_phy_config(tp);
3221                 break;
3222         case RTL_GIGA_MAC_VER_27:
3223                 rtl8168d_3_hw_phy_config(tp);
3224                 break;
3225         case RTL_GIGA_MAC_VER_28:
3226                 rtl8168d_4_hw_phy_config(tp);
3227                 break;
3228         case RTL_GIGA_MAC_VER_29:
3229         case RTL_GIGA_MAC_VER_30:
3230                 rtl8105e_hw_phy_config(tp);
3231                 break;
3232         case RTL_GIGA_MAC_VER_31:
3233                 /* None. */
3234                 break;
3235         case RTL_GIGA_MAC_VER_32:
3236         case RTL_GIGA_MAC_VER_33:
3237                 rtl8168e_1_hw_phy_config(tp);
3238                 break;
3239         case RTL_GIGA_MAC_VER_34:
3240                 rtl8168e_2_hw_phy_config(tp);
3241                 break;
3242         case RTL_GIGA_MAC_VER_35:
3243                 rtl8168f_1_hw_phy_config(tp);
3244                 break;
3245         case RTL_GIGA_MAC_VER_36:
3246                 rtl8168f_2_hw_phy_config(tp);
3247                 break;
3248
3249         default:
3250                 break;
3251         }
3252 }
3253
3254 static void rtl_phy_work(struct rtl8169_private *tp)
3255 {
3256         struct timer_list *timer = &tp->timer;
3257         void __iomem *ioaddr = tp->mmio_addr;
3258         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3259
3260         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3261
3262         if (tp->phy_reset_pending(tp)) {
3263                 /*
3264                  * A busy loop could burn quite a few cycles on nowadays CPU.
3265                  * Let's delay the execution of the timer for a few ticks.
3266                  */
3267                 timeout = HZ/10;
3268                 goto out_mod_timer;
3269         }
3270
3271         if (tp->link_ok(ioaddr))
3272                 return;
3273
3274         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3275
3276         tp->phy_reset_enable(tp);
3277
3278 out_mod_timer:
3279         mod_timer(timer, jiffies + timeout);
3280 }
3281
3282 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3283 {
3284         if (!test_and_set_bit(flag, tp->wk.flags))
3285                 schedule_work(&tp->wk.work);
3286 }
3287
3288 static void rtl8169_phy_timer(unsigned long __opaque)
3289 {
3290         struct net_device *dev = (struct net_device *)__opaque;
3291         struct rtl8169_private *tp = netdev_priv(dev);
3292
3293         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3294 }
3295
3296 #ifdef CONFIG_NET_POLL_CONTROLLER
3297 static void rtl8169_netpoll(struct net_device *dev)
3298 {
3299         struct rtl8169_private *tp = netdev_priv(dev);
3300
3301         rtl8169_interrupt(tp->pci_dev->irq, dev);
3302 }
3303 #endif
3304
3305 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3306                                   void __iomem *ioaddr)
3307 {
3308         iounmap(ioaddr);
3309         pci_release_regions(pdev);
3310         pci_clear_mwi(pdev);
3311         pci_disable_device(pdev);
3312         free_netdev(dev);
3313 }
3314
3315 static void rtl8169_phy_reset(struct net_device *dev,
3316                               struct rtl8169_private *tp)
3317 {
3318         unsigned int i;
3319
3320         tp->phy_reset_enable(tp);
3321         for (i = 0; i < 100; i++) {
3322                 if (!tp->phy_reset_pending(tp))
3323                         return;
3324                 msleep(1);
3325         }
3326         netif_err(tp, link, dev, "PHY reset failed\n");
3327 }
3328
3329 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3330 {
3331         void __iomem *ioaddr = tp->mmio_addr;
3332
3333         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3334             (RTL_R8(PHYstatus) & TBI_Enable);
3335 }
3336
3337 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3338 {
3339         void __iomem *ioaddr = tp->mmio_addr;
3340
3341         rtl_hw_phy_config(dev);
3342
3343         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3344                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3345                 RTL_W8(0x82, 0x01);
3346         }
3347
3348         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3349
3350         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3351                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3352
3353         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3354                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3355                 RTL_W8(0x82, 0x01);
3356                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3357                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3358         }
3359
3360         rtl8169_phy_reset(dev, tp);
3361
3362         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3363                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3364                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3365                           (tp->mii.supports_gmii ?
3366                            ADVERTISED_1000baseT_Half |
3367                            ADVERTISED_1000baseT_Full : 0));
3368
3369         if (rtl_tbi_enabled(tp))
3370                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3371 }
3372
3373 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3374 {
3375         void __iomem *ioaddr = tp->mmio_addr;
3376         u32 high;
3377         u32 low;
3378
3379         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3380         high = addr[4] | (addr[5] << 8);
3381
3382         rtl_lock_work(tp);
3383
3384         RTL_W8(Cfg9346, Cfg9346_Unlock);
3385
3386         RTL_W32(MAC4, high);
3387         RTL_R32(MAC4);
3388
3389         RTL_W32(MAC0, low);
3390         RTL_R32(MAC0);
3391
3392         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3393                 const struct exgmac_reg e[] = {
3394                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3395                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3396                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3397                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3398                                                                 low  >> 16 },
3399                 };
3400
3401                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3402         }
3403
3404         RTL_W8(Cfg9346, Cfg9346_Lock);
3405
3406         rtl_unlock_work(tp);
3407 }
3408
3409 static int rtl_set_mac_address(struct net_device *dev, void *p)
3410 {
3411         struct rtl8169_private *tp = netdev_priv(dev);
3412         struct sockaddr *addr = p;
3413
3414         if (!is_valid_ether_addr(addr->sa_data))
3415                 return -EADDRNOTAVAIL;
3416
3417         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3418
3419         rtl_rar_set(tp, dev->dev_addr);
3420
3421         return 0;
3422 }
3423
3424 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3425 {
3426         struct rtl8169_private *tp = netdev_priv(dev);
3427         struct mii_ioctl_data *data = if_mii(ifr);
3428
3429         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3430 }
3431
3432 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3433                           struct mii_ioctl_data *data, int cmd)
3434 {
3435         switch (cmd) {
3436         case SIOCGMIIPHY:
3437                 data->phy_id = 32; /* Internal PHY */
3438                 return 0;
3439
3440         case SIOCGMIIREG:
3441                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3442                 return 0;
3443
3444         case SIOCSMIIREG:
3445                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3446                 return 0;
3447         }
3448         return -EOPNOTSUPP;
3449 }
3450
3451 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3452 {
3453         return -EOPNOTSUPP;
3454 }
3455
3456 static const struct rtl_cfg_info {
3457         void (*hw_start)(struct net_device *);
3458         unsigned int region;
3459         unsigned int align;
3460         u16 event_slow;
3461         unsigned features;
3462         u8 default_ver;
3463 } rtl_cfg_infos [] = {
3464         [RTL_CFG_0] = {
3465                 .hw_start       = rtl_hw_start_8169,
3466                 .region         = 1,
3467                 .align          = 0,
3468                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
3469                 .features       = RTL_FEATURE_GMII,
3470                 .default_ver    = RTL_GIGA_MAC_VER_01,
3471         },
3472         [RTL_CFG_1] = {
3473                 .hw_start       = rtl_hw_start_8168,
3474                 .region         = 2,
3475                 .align          = 8,
3476                 .event_slow     = SYSErr | LinkChg | RxOverflow,
3477                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3478                 .default_ver    = RTL_GIGA_MAC_VER_11,
3479         },
3480         [RTL_CFG_2] = {
3481                 .hw_start       = rtl_hw_start_8101,
3482                 .region         = 2,
3483                 .align          = 8,
3484                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
3485                                   PCSTimeout,
3486                 .features       = RTL_FEATURE_MSI,
3487                 .default_ver    = RTL_GIGA_MAC_VER_13,
3488         }
3489 };
3490
3491 /* Cfg9346_Unlock assumed. */
3492 static unsigned rtl_try_msi(struct rtl8169_private *tp,
3493                             const struct rtl_cfg_info *cfg)
3494 {
3495         void __iomem *ioaddr = tp->mmio_addr;
3496         unsigned msi = 0;
3497         u8 cfg2;
3498
3499         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3500         if (cfg->features & RTL_FEATURE_MSI) {
3501                 if (pci_enable_msi(tp->pci_dev)) {
3502                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
3503                 } else {
3504                         cfg2 |= MSIEnable;
3505                         msi = RTL_FEATURE_MSI;
3506                 }
3507         }
3508         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3509                 RTL_W8(Config2, cfg2);
3510         return msi;
3511 }
3512
3513 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3514 {
3515         if (tp->features & RTL_FEATURE_MSI) {
3516                 pci_disable_msi(pdev);
3517                 tp->features &= ~RTL_FEATURE_MSI;
3518         }
3519 }
3520
3521 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3522 {
3523         struct mdio_ops *ops = &tp->mdio_ops;
3524
3525         switch (tp->mac_version) {
3526         case RTL_GIGA_MAC_VER_27:
3527                 ops->write      = r8168dp_1_mdio_write;
3528                 ops->read       = r8168dp_1_mdio_read;
3529                 break;
3530         case RTL_GIGA_MAC_VER_28:
3531         case RTL_GIGA_MAC_VER_31:
3532                 ops->write      = r8168dp_2_mdio_write;
3533                 ops->read       = r8168dp_2_mdio_read;
3534                 break;
3535         default:
3536                 ops->write      = r8169_mdio_write;
3537                 ops->read       = r8169_mdio_read;
3538                 break;
3539         }
3540 }
3541
3542 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3543 {
3544         void __iomem *ioaddr = tp->mmio_addr;
3545
3546         switch (tp->mac_version) {
3547         case RTL_GIGA_MAC_VER_29:
3548         case RTL_GIGA_MAC_VER_30:
3549         case RTL_GIGA_MAC_VER_32:
3550         case RTL_GIGA_MAC_VER_33:
3551         case RTL_GIGA_MAC_VER_34:
3552                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3553                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3554                 break;
3555         default:
3556                 break;
3557         }
3558 }
3559
3560 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3561 {
3562         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3563                 return false;
3564
3565         rtl_writephy(tp, 0x1f, 0x0000);
3566         rtl_writephy(tp, MII_BMCR, 0x0000);
3567
3568         rtl_wol_suspend_quirk(tp);
3569
3570         return true;
3571 }
3572
3573 static void r810x_phy_power_down(struct rtl8169_private *tp)
3574 {
3575         rtl_writephy(tp, 0x1f, 0x0000);
3576         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3577 }
3578
3579 static void r810x_phy_power_up(struct rtl8169_private *tp)
3580 {
3581         rtl_writephy(tp, 0x1f, 0x0000);
3582         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3583 }
3584
3585 static void r810x_pll_power_down(struct rtl8169_private *tp)
3586 {
3587         if (rtl_wol_pll_power_down(tp))
3588                 return;
3589
3590         r810x_phy_power_down(tp);
3591 }
3592
3593 static void r810x_pll_power_up(struct rtl8169_private *tp)
3594 {
3595         r810x_phy_power_up(tp);
3596 }
3597
3598 static void r8168_phy_power_up(struct rtl8169_private *tp)
3599 {
3600         rtl_writephy(tp, 0x1f, 0x0000);
3601         switch (tp->mac_version) {
3602         case RTL_GIGA_MAC_VER_11:
3603         case RTL_GIGA_MAC_VER_12:
3604         case RTL_GIGA_MAC_VER_17:
3605         case RTL_GIGA_MAC_VER_18:
3606         case RTL_GIGA_MAC_VER_19:
3607         case RTL_GIGA_MAC_VER_20:
3608         case RTL_GIGA_MAC_VER_21:
3609         case RTL_GIGA_MAC_VER_22:
3610         case RTL_GIGA_MAC_VER_23:
3611         case RTL_GIGA_MAC_VER_24:
3612         case RTL_GIGA_MAC_VER_25:
3613         case RTL_GIGA_MAC_VER_26:
3614         case RTL_GIGA_MAC_VER_27:
3615         case RTL_GIGA_MAC_VER_28:
3616         case RTL_GIGA_MAC_VER_31:
3617                 rtl_writephy(tp, 0x0e, 0x0000);
3618                 break;
3619         default:
3620                 break;
3621         }
3622         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3623 }
3624
3625 static void r8168_phy_power_down(struct rtl8169_private *tp)
3626 {
3627         rtl_writephy(tp, 0x1f, 0x0000);
3628         switch (tp->mac_version) {
3629         case RTL_GIGA_MAC_VER_32:
3630         case RTL_GIGA_MAC_VER_33:
3631                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3632                 break;
3633
3634         case RTL_GIGA_MAC_VER_11:
3635         case RTL_GIGA_MAC_VER_12:
3636         case RTL_GIGA_MAC_VER_17:
3637         case RTL_GIGA_MAC_VER_18:
3638         case RTL_GIGA_MAC_VER_19:
3639         case RTL_GIGA_MAC_VER_20:
3640         case RTL_GIGA_MAC_VER_21:
3641         case RTL_GIGA_MAC_VER_22:
3642         case RTL_GIGA_MAC_VER_23:
3643         case RTL_GIGA_MAC_VER_24:
3644         case RTL_GIGA_MAC_VER_25:
3645         case RTL_GIGA_MAC_VER_26:
3646         case RTL_GIGA_MAC_VER_27:
3647         case RTL_GIGA_MAC_VER_28:
3648         case RTL_GIGA_MAC_VER_31:
3649                 rtl_writephy(tp, 0x0e, 0x0200);
3650         default:
3651                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3652                 break;
3653         }
3654 }
3655
3656 static void r8168_pll_power_down(struct rtl8169_private *tp)
3657 {
3658         void __iomem *ioaddr = tp->mmio_addr;
3659
3660         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3661              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3662              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3663             r8168dp_check_dash(tp)) {
3664                 return;
3665         }
3666
3667         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3668              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3669             (RTL_R16(CPlusCmd) & ASF)) {
3670                 return;
3671         }
3672
3673         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3674             tp->mac_version == RTL_GIGA_MAC_VER_33)
3675                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3676
3677         if (rtl_wol_pll_power_down(tp))
3678                 return;
3679
3680         r8168_phy_power_down(tp);
3681
3682         switch (tp->mac_version) {
3683         case RTL_GIGA_MAC_VER_25:
3684         case RTL_GIGA_MAC_VER_26:
3685         case RTL_GIGA_MAC_VER_27:
3686         case RTL_GIGA_MAC_VER_28:
3687         case RTL_GIGA_MAC_VER_31:
3688         case RTL_GIGA_MAC_VER_32:
3689         case RTL_GIGA_MAC_VER_33:
3690                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3691                 break;
3692         }
3693 }
3694
3695 static void r8168_pll_power_up(struct rtl8169_private *tp)
3696 {
3697         void __iomem *ioaddr = tp->mmio_addr;
3698
3699         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3700              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3701              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3702             r8168dp_check_dash(tp)) {
3703                 return;
3704         }
3705
3706         switch (tp->mac_version) {
3707         case RTL_GIGA_MAC_VER_25:
3708         case RTL_GIGA_MAC_VER_26:
3709         case RTL_GIGA_MAC_VER_27:
3710         case RTL_GIGA_MAC_VER_28:
3711         case RTL_GIGA_MAC_VER_31:
3712         case RTL_GIGA_MAC_VER_32:
3713         case RTL_GIGA_MAC_VER_33:
3714                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3715                 break;
3716         }
3717
3718         r8168_phy_power_up(tp);
3719 }
3720
3721 static void rtl_generic_op(struct rtl8169_private *tp,
3722                            void (*op)(struct rtl8169_private *))
3723 {
3724         if (op)
3725                 op(tp);
3726 }
3727
3728 static void rtl_pll_power_down(struct rtl8169_private *tp)
3729 {
3730         rtl_generic_op(tp, tp->pll_power_ops.down);
3731 }
3732
3733 static void rtl_pll_power_up(struct rtl8169_private *tp)
3734 {
3735         rtl_generic_op(tp, tp->pll_power_ops.up);
3736 }
3737
3738 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3739 {
3740         struct pll_power_ops *ops = &tp->pll_power_ops;
3741
3742         switch (tp->mac_version) {
3743         case RTL_GIGA_MAC_VER_07:
3744         case RTL_GIGA_MAC_VER_08:
3745         case RTL_GIGA_MAC_VER_09:
3746         case RTL_GIGA_MAC_VER_10:
3747         case RTL_GIGA_MAC_VER_16:
3748         case RTL_GIGA_MAC_VER_29:
3749         case RTL_GIGA_MAC_VER_30:
3750                 ops->down       = r810x_pll_power_down;
3751                 ops->up         = r810x_pll_power_up;
3752                 break;
3753
3754         case RTL_GIGA_MAC_VER_11:
3755         case RTL_GIGA_MAC_VER_12:
3756         case RTL_GIGA_MAC_VER_17:
3757         case RTL_GIGA_MAC_VER_18:
3758         case RTL_GIGA_MAC_VER_19:
3759         case RTL_GIGA_MAC_VER_20:
3760         case RTL_GIGA_MAC_VER_21:
3761         case RTL_GIGA_MAC_VER_22:
3762         case RTL_GIGA_MAC_VER_23:
3763         case RTL_GIGA_MAC_VER_24:
3764         case RTL_GIGA_MAC_VER_25:
3765         case RTL_GIGA_MAC_VER_26:
3766         case RTL_GIGA_MAC_VER_27:
3767         case RTL_GIGA_MAC_VER_28:
3768         case RTL_GIGA_MAC_VER_31:
3769         case RTL_GIGA_MAC_VER_32:
3770         case RTL_GIGA_MAC_VER_33:
3771         case RTL_GIGA_MAC_VER_34:
3772         case RTL_GIGA_MAC_VER_35:
3773         case RTL_GIGA_MAC_VER_36:
3774                 ops->down       = r8168_pll_power_down;
3775                 ops->up         = r8168_pll_power_up;
3776                 break;
3777
3778         default:
3779                 ops->down       = NULL;
3780                 ops->up         = NULL;
3781                 break;
3782         }
3783 }
3784
3785 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3786 {
3787         void __iomem *ioaddr = tp->mmio_addr;
3788
3789         switch (tp->mac_version) {
3790         case RTL_GIGA_MAC_VER_01:
3791         case RTL_GIGA_MAC_VER_02:
3792         case RTL_GIGA_MAC_VER_03:
3793         case RTL_GIGA_MAC_VER_04:
3794         case RTL_GIGA_MAC_VER_05:
3795         case RTL_GIGA_MAC_VER_06:
3796         case RTL_GIGA_MAC_VER_10:
3797         case RTL_GIGA_MAC_VER_11:
3798         case RTL_GIGA_MAC_VER_12:
3799         case RTL_GIGA_MAC_VER_13:
3800         case RTL_GIGA_MAC_VER_14:
3801         case RTL_GIGA_MAC_VER_15:
3802         case RTL_GIGA_MAC_VER_16:
3803         case RTL_GIGA_MAC_VER_17:
3804                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3805                 break;
3806         case RTL_GIGA_MAC_VER_18:
3807         case RTL_GIGA_MAC_VER_19:
3808         case RTL_GIGA_MAC_VER_20:
3809         case RTL_GIGA_MAC_VER_21:
3810         case RTL_GIGA_MAC_VER_22:
3811         case RTL_GIGA_MAC_VER_23:
3812         case RTL_GIGA_MAC_VER_24:
3813                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3814                 break;
3815         default:
3816                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3817                 break;
3818         }
3819 }
3820
3821 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3822 {
3823         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3824 }
3825
3826 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3827 {
3828         void __iomem *ioaddr = tp->mmio_addr;
3829
3830         RTL_W8(Cfg9346, Cfg9346_Unlock);
3831         rtl_generic_op(tp, tp->jumbo_ops.enable);
3832         RTL_W8(Cfg9346, Cfg9346_Lock);
3833 }
3834
3835 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3836 {
3837         void __iomem *ioaddr = tp->mmio_addr;
3838
3839         RTL_W8(Cfg9346, Cfg9346_Unlock);
3840         rtl_generic_op(tp, tp->jumbo_ops.disable);
3841         RTL_W8(Cfg9346, Cfg9346_Lock);
3842 }
3843
3844 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3845 {
3846         void __iomem *ioaddr = tp->mmio_addr;
3847
3848         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3849         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3850         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3851 }
3852
3853 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3854 {
3855         void __iomem *ioaddr = tp->mmio_addr;
3856
3857         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3858         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3859         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3860 }
3861
3862 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3863 {
3864         void __iomem *ioaddr = tp->mmio_addr;
3865
3866         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3867 }
3868
3869 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3870 {
3871         void __iomem *ioaddr = tp->mmio_addr;
3872
3873         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3874 }
3875
3876 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3877 {
3878         void __iomem *ioaddr = tp->mmio_addr;
3879
3880         RTL_W8(MaxTxPacketSize, 0x3f);
3881         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3882         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3883         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3884 }
3885
3886 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3887 {
3888         void __iomem *ioaddr = tp->mmio_addr;
3889
3890         RTL_W8(MaxTxPacketSize, 0x0c);
3891         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3892         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3893         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3894 }
3895
3896 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3897 {
3898         rtl_tx_performance_tweak(tp->pci_dev,
3899                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3900 }
3901
3902 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3903 {
3904         rtl_tx_performance_tweak(tp->pci_dev,
3905                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3906 }
3907
3908 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3909 {
3910         void __iomem *ioaddr = tp->mmio_addr;
3911
3912         r8168b_0_hw_jumbo_enable(tp);
3913
3914         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3915 }
3916
3917 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3918 {
3919         void __iomem *ioaddr = tp->mmio_addr;
3920
3921         r8168b_0_hw_jumbo_disable(tp);
3922
3923         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3924 }
3925
3926 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3927 {
3928         struct jumbo_ops *ops = &tp->jumbo_ops;
3929
3930         switch (tp->mac_version) {
3931         case RTL_GIGA_MAC_VER_11:
3932                 ops->disable    = r8168b_0_hw_jumbo_disable;
3933                 ops->enable     = r8168b_0_hw_jumbo_enable;
3934                 break;
3935         case RTL_GIGA_MAC_VER_12:
3936         case RTL_GIGA_MAC_VER_17:
3937                 ops->disable    = r8168b_1_hw_jumbo_disable;
3938                 ops->enable     = r8168b_1_hw_jumbo_enable;
3939                 break;
3940         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3941         case RTL_GIGA_MAC_VER_19:
3942         case RTL_GIGA_MAC_VER_20:
3943         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3944         case RTL_GIGA_MAC_VER_22:
3945         case RTL_GIGA_MAC_VER_23:
3946         case RTL_GIGA_MAC_VER_24:
3947         case RTL_GIGA_MAC_VER_25:
3948         case RTL_GIGA_MAC_VER_26:
3949                 ops->disable    = r8168c_hw_jumbo_disable;
3950                 ops->enable     = r8168c_hw_jumbo_enable;
3951                 break;
3952         case RTL_GIGA_MAC_VER_27:
3953         case RTL_GIGA_MAC_VER_28:
3954                 ops->disable    = r8168dp_hw_jumbo_disable;
3955                 ops->enable     = r8168dp_hw_jumbo_enable;
3956                 break;
3957         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3958         case RTL_GIGA_MAC_VER_32:
3959         case RTL_GIGA_MAC_VER_33:
3960         case RTL_GIGA_MAC_VER_34:
3961                 ops->disable    = r8168e_hw_jumbo_disable;
3962                 ops->enable     = r8168e_hw_jumbo_enable;
3963                 break;
3964
3965         /*
3966          * No action needed for jumbo frames with 8169.
3967          * No jumbo for 810x at all.
3968          */
3969         default:
3970                 ops->disable    = NULL;
3971                 ops->enable     = NULL;
3972                 break;
3973         }
3974 }
3975
3976 static void rtl_hw_reset(struct rtl8169_private *tp)
3977 {
3978         void __iomem *ioaddr = tp->mmio_addr;
3979         int i;
3980
3981         /* Soft reset the chip. */
3982         RTL_W8(ChipCmd, CmdReset);
3983
3984         /* Check that the chip has finished the reset. */
3985         for (i = 0; i < 100; i++) {
3986                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3987                         break;
3988                 udelay(100);
3989         }
3990 }
3991
3992 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3993 {
3994         struct rtl_fw *rtl_fw;
3995         const char *name;
3996         int rc = -ENOMEM;
3997
3998         name = rtl_lookup_firmware_name(tp);
3999         if (!name)
4000                 goto out_no_firmware;
4001
4002         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4003         if (!rtl_fw)
4004                 goto err_warn;
4005
4006         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4007         if (rc < 0)
4008                 goto err_free;
4009
4010         rc = rtl_check_firmware(tp, rtl_fw);
4011         if (rc < 0)
4012                 goto err_release_firmware;
4013
4014         tp->rtl_fw = rtl_fw;
4015 out:
4016         return;
4017
4018 err_release_firmware:
4019         release_firmware(rtl_fw->fw);
4020 err_free:
4021         kfree(rtl_fw);
4022 err_warn:
4023         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4024                    name, rc);
4025 out_no_firmware:
4026         tp->rtl_fw = NULL;
4027         goto out;
4028 }
4029
4030 static void rtl_request_firmware(struct rtl8169_private *tp)
4031 {
4032         if (IS_ERR(tp->rtl_fw))
4033                 rtl_request_uncached_firmware(tp);
4034 }
4035
4036 static void rtl_task(struct work_struct *);
4037
4038 static int rtl8169_open(struct net_device *dev)
4039 {
4040         struct rtl8169_private *tp = netdev_priv(dev);
4041         void __iomem *ioaddr = tp->mmio_addr;
4042         struct pci_dev *pdev = tp->pci_dev;
4043         int retval = -ENOMEM;
4044
4045         pm_runtime_get_sync(&pdev->dev);
4046
4047         /*
4048          * Rx and Tx desscriptors needs 256 bytes alignment.
4049          * dma_alloc_coherent provides more.
4050          */
4051         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4052                                              &tp->TxPhyAddr, GFP_KERNEL);
4053         if (!tp->TxDescArray)
4054                 goto err_pm_runtime_put;
4055
4056         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4057                                              &tp->RxPhyAddr, GFP_KERNEL);
4058         if (!tp->RxDescArray)
4059                 goto err_free_tx_0;
4060
4061         retval = rtl8169_init_ring(dev);
4062         if (retval < 0)
4063                 goto err_free_rx_1;
4064
4065         INIT_WORK(&tp->wk.work, rtl_task);
4066
4067         smp_mb();
4068
4069         rtl_request_firmware(tp);
4070
4071         retval = request_irq(dev->irq, rtl8169_interrupt,
4072                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
4073                              dev->name, dev);
4074         if (retval < 0)
4075                 goto err_release_fw_2;
4076
4077         rtl_lock_work(tp);
4078
4079         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4080
4081         napi_enable(&tp->napi);
4082
4083         rtl8169_init_phy(dev, tp);
4084
4085         __rtl8169_set_features(dev, dev->features);
4086
4087         rtl_pll_power_up(tp);
4088
4089         rtl_hw_start(dev);
4090
4091         netif_start_queue(dev);
4092
4093         rtl_unlock_work(tp);
4094
4095         tp->saved_wolopts = 0;
4096         pm_runtime_put_noidle(&pdev->dev);
4097
4098         rtl8169_check_link_status(dev, tp, ioaddr);
4099 out:
4100         return retval;
4101
4102 err_release_fw_2:
4103         rtl_release_firmware(tp);
4104         rtl8169_rx_clear(tp);
4105 err_free_rx_1:
4106         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4107                           tp->RxPhyAddr);
4108         tp->RxDescArray = NULL;
4109 err_free_tx_0:
4110         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4111                           tp->TxPhyAddr);
4112         tp->TxDescArray = NULL;
4113 err_pm_runtime_put:
4114         pm_runtime_put_noidle(&pdev->dev);
4115         goto out;
4116 }
4117
4118 static void rtl_rx_close(struct rtl8169_private *tp)
4119 {
4120         void __iomem *ioaddr = tp->mmio_addr;
4121
4122         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4123 }
4124
4125 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4126 {
4127         void __iomem *ioaddr = tp->mmio_addr;
4128
4129         /* Disable interrupts */
4130         rtl8169_irq_mask_and_ack(tp);
4131
4132         rtl_rx_close(tp);
4133
4134         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4135             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4136             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4137                 while (RTL_R8(TxPoll) & NPQ)
4138                         udelay(20);
4139         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4140                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4141                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
4142                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4143                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4144                         udelay(100);
4145         } else {
4146                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4147                 udelay(100);
4148         }
4149
4150         rtl_hw_reset(tp);
4151 }
4152
4153 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4154 {
4155         void __iomem *ioaddr = tp->mmio_addr;
4156
4157         /* Set DMA burst size and Interframe Gap Time */
4158         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4159                 (InterFrameGap << TxInterFrameGapShift));
4160 }
4161
4162 static void rtl_hw_start(struct net_device *dev)
4163 {
4164         struct rtl8169_private *tp = netdev_priv(dev);
4165
4166         tp->hw_start(dev);
4167
4168         rtl_irq_enable_all(tp);
4169 }
4170
4171 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4172                                          void __iomem *ioaddr)
4173 {
4174         /*
4175          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4176          * register to be written before TxDescAddrLow to work.
4177          * Switching from MMIO to I/O access fixes the issue as well.
4178          */
4179         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4180         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4181         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4182         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4183 }
4184
4185 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4186 {
4187         u16 cmd;
4188
4189         cmd = RTL_R16(CPlusCmd);
4190         RTL_W16(CPlusCmd, cmd);
4191         return cmd;
4192 }
4193
4194 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4195 {
4196         /* Low hurts. Let's disable the filtering. */
4197         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4198 }
4199
4200 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4201 {
4202         static const struct rtl_cfg2_info {
4203                 u32 mac_version;
4204                 u32 clk;
4205                 u32 val;
4206         } cfg2_info [] = {
4207                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4208                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4209                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4210                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4211         };
4212         const struct rtl_cfg2_info *p = cfg2_info;
4213         unsigned int i;
4214         u32 clk;
4215
4216         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4217         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4218                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4219                         RTL_W32(0x7c, p->val);
4220                         break;
4221                 }
4222         }
4223 }
4224
4225 static void rtl_set_rx_mode(struct net_device *dev)
4226 {
4227         struct rtl8169_private *tp = netdev_priv(dev);
4228         void __iomem *ioaddr = tp->mmio_addr;
4229         u32 mc_filter[2];       /* Multicast hash filter */
4230         int rx_mode;
4231         u32 tmp = 0;
4232
4233         if (dev->flags & IFF_PROMISC) {
4234                 /* Unconditionally log net taps. */
4235                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4236                 rx_mode =
4237                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4238                     AcceptAllPhys;
4239                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4240         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4241                    (dev->flags & IFF_ALLMULTI)) {
4242                 /* Too many to filter perfectly -- accept all multicasts. */
4243                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4244                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4245         } else {
4246                 struct netdev_hw_addr *ha;
4247
4248                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4249                 mc_filter[1] = mc_filter[0] = 0;
4250                 netdev_for_each_mc_addr(ha, dev) {
4251                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4252                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4253                         rx_mode |= AcceptMulticast;
4254                 }
4255         }
4256
4257         if (dev->features & NETIF_F_RXALL)
4258                 rx_mode |= (AcceptErr | AcceptRunt);
4259
4260         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4261
4262         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4263                 u32 data = mc_filter[0];
4264
4265                 mc_filter[0] = swab32(mc_filter[1]);
4266                 mc_filter[1] = swab32(data);
4267         }
4268
4269         RTL_W32(MAR0 + 4, mc_filter[1]);
4270         RTL_W32(MAR0 + 0, mc_filter[0]);
4271
4272         RTL_W32(RxConfig, tmp);
4273 }
4274
4275 static void rtl_hw_start_8169(struct net_device *dev)
4276 {
4277         struct rtl8169_private *tp = netdev_priv(dev);
4278         void __iomem *ioaddr = tp->mmio_addr;
4279         struct pci_dev *pdev = tp->pci_dev;
4280
4281         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4282                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4283                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4284         }
4285
4286         RTL_W8(Cfg9346, Cfg9346_Unlock);
4287         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4288             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4289             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4290             tp->mac_version == RTL_GIGA_MAC_VER_04)
4291                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4292
4293         rtl_init_rxcfg(tp);
4294
4295         RTL_W8(EarlyTxThres, NoEarlyTx);
4296
4297         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4298
4299         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4300             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4301             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4302             tp->mac_version == RTL_GIGA_MAC_VER_04)
4303                 rtl_set_rx_tx_config_registers(tp);
4304
4305         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4306
4307         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4308             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4309                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4310                         "Bit-3 and bit-14 MUST be 1\n");
4311                 tp->cp_cmd |= (1 << 14);
4312         }
4313
4314         RTL_W16(CPlusCmd, tp->cp_cmd);
4315
4316         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4317
4318         /*
4319          * Undocumented corner. Supposedly:
4320          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4321          */
4322         RTL_W16(IntrMitigate, 0x0000);
4323
4324         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4325
4326         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4327             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4328             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4329             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4330                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4331                 rtl_set_rx_tx_config_registers(tp);
4332         }
4333
4334         RTL_W8(Cfg9346, Cfg9346_Lock);
4335
4336         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4337         RTL_R8(IntrMask);
4338
4339         RTL_W32(RxMissed, 0);
4340
4341         rtl_set_rx_mode(dev);
4342
4343         /* no early-rx interrupts */
4344         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4345 }
4346
4347 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4348 {
4349         u32 csi;
4350
4351         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4352         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4353 }
4354
4355 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4356 {
4357         rtl_csi_access_enable(ioaddr, 0x17000000);
4358 }
4359
4360 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4361 {
4362         rtl_csi_access_enable(ioaddr, 0x27000000);
4363 }
4364
4365 struct ephy_info {
4366         unsigned int offset;
4367         u16 mask;
4368         u16 bits;
4369 };
4370
4371 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4372 {
4373         u16 w;
4374
4375         while (len-- > 0) {
4376                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4377                 rtl_ephy_write(ioaddr, e->offset, w);
4378                 e++;
4379         }
4380 }
4381
4382 static void rtl_disable_clock_request(struct pci_dev *pdev)
4383 {
4384         int cap = pci_pcie_cap(pdev);
4385
4386         if (cap) {
4387                 u16 ctl;
4388
4389                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4390                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4391                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4392         }
4393 }
4394
4395 static void rtl_enable_clock_request(struct pci_dev *pdev)
4396 {
4397         int cap = pci_pcie_cap(pdev);
4398
4399         if (cap) {
4400                 u16 ctl;
4401
4402                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4403                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4404                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4405         }
4406 }
4407
4408 #define R8168_CPCMD_QUIRK_MASK (\
4409         EnableBist | \
4410         Mac_dbgo_oe | \
4411         Force_half_dup | \
4412         Force_rxflow_en | \
4413         Force_txflow_en | \
4414         Cxpl_dbg_sel | \
4415         ASF | \
4416         PktCntrDisable | \
4417         Mac_dbgo_sel)
4418
4419 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4420 {
4421         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4422
4423         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4424
4425         rtl_tx_performance_tweak(pdev,
4426                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4427 }
4428
4429 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4430 {
4431         rtl_hw_start_8168bb(ioaddr, pdev);
4432
4433         RTL_W8(MaxTxPacketSize, TxPacketMax);
4434
4435         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4436 }
4437
4438 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4439 {
4440         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4441
4442         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4443
4444         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4445
4446         rtl_disable_clock_request(pdev);
4447
4448         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4449 }
4450
4451 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4452 {
4453         static const struct ephy_info e_info_8168cp[] = {
4454                 { 0x01, 0,      0x0001 },
4455                 { 0x02, 0x0800, 0x1000 },
4456                 { 0x03, 0,      0x0042 },
4457                 { 0x06, 0x0080, 0x0000 },
4458                 { 0x07, 0,      0x2000 }
4459         };
4460
4461         rtl_csi_access_enable_2(ioaddr);
4462
4463         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4464
4465         __rtl_hw_start_8168cp(ioaddr, pdev);
4466 }
4467
4468 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4469 {
4470         rtl_csi_access_enable_2(ioaddr);
4471
4472         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4473
4474         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4475
4476         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4477 }
4478
4479 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4480 {
4481         rtl_csi_access_enable_2(ioaddr);
4482
4483         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4484
4485         /* Magic. */
4486         RTL_W8(DBG_REG, 0x20);
4487
4488         RTL_W8(MaxTxPacketSize, TxPacketMax);
4489
4490         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4491
4492         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4493 }
4494
4495 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4496 {
4497         static const struct ephy_info e_info_8168c_1[] = {
4498                 { 0x02, 0x0800, 0x1000 },
4499                 { 0x03, 0,      0x0002 },
4500                 { 0x06, 0x0080, 0x0000 }
4501         };
4502
4503         rtl_csi_access_enable_2(ioaddr);
4504
4505         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4506
4507         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4508
4509         __rtl_hw_start_8168cp(ioaddr, pdev);
4510 }
4511
4512 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4513 {
4514         static const struct ephy_info e_info_8168c_2[] = {
4515                 { 0x01, 0,      0x0001 },
4516                 { 0x03, 0x0400, 0x0220 }
4517         };
4518
4519         rtl_csi_access_enable_2(ioaddr);
4520
4521         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4522
4523         __rtl_hw_start_8168cp(ioaddr, pdev);
4524 }
4525
4526 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4527 {
4528         rtl_hw_start_8168c_2(ioaddr, pdev);
4529 }
4530
4531 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4532 {
4533         rtl_csi_access_enable_2(ioaddr);
4534
4535         __rtl_hw_start_8168cp(ioaddr, pdev);
4536 }
4537
4538 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4539 {
4540         rtl_csi_access_enable_2(ioaddr);
4541
4542         rtl_disable_clock_request(pdev);
4543
4544         RTL_W8(MaxTxPacketSize, TxPacketMax);
4545
4546         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4547
4548         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4549 }
4550
4551 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4552 {
4553         rtl_csi_access_enable_1(ioaddr);
4554
4555         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4556
4557         RTL_W8(MaxTxPacketSize, TxPacketMax);
4558
4559         rtl_disable_clock_request(pdev);
4560 }
4561
4562 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4563 {
4564         static const struct ephy_info e_info_8168d_4[] = {
4565                 { 0x0b, ~0,     0x48 },
4566                 { 0x19, 0x20,   0x50 },
4567                 { 0x0c, ~0,     0x20 }
4568         };
4569         int i;
4570
4571         rtl_csi_access_enable_1(ioaddr);
4572
4573         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4574
4575         RTL_W8(MaxTxPacketSize, TxPacketMax);
4576
4577         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4578                 const struct ephy_info *e = e_info_8168d_4 + i;
4579                 u16 w;
4580
4581                 w = rtl_ephy_read(ioaddr, e->offset);
4582                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4583         }
4584
4585         rtl_enable_clock_request(pdev);
4586 }
4587
4588 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4589 {
4590         static const struct ephy_info e_info_8168e_1[] = {
4591                 { 0x00, 0x0200, 0x0100 },
4592                 { 0x00, 0x0000, 0x0004 },
4593                 { 0x06, 0x0002, 0x0001 },
4594                 { 0x06, 0x0000, 0x0030 },
4595                 { 0x07, 0x0000, 0x2000 },
4596                 { 0x00, 0x0000, 0x0020 },
4597                 { 0x03, 0x5800, 0x2000 },
4598                 { 0x03, 0x0000, 0x0001 },
4599                 { 0x01, 0x0800, 0x1000 },
4600                 { 0x07, 0x0000, 0x4000 },
4601                 { 0x1e, 0x0000, 0x2000 },
4602                 { 0x19, 0xffff, 0xfe6c },
4603                 { 0x0a, 0x0000, 0x0040 }
4604         };
4605
4606         rtl_csi_access_enable_2(ioaddr);
4607
4608         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4609
4610         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4611
4612         RTL_W8(MaxTxPacketSize, TxPacketMax);
4613
4614         rtl_disable_clock_request(pdev);
4615
4616         /* Reset tx FIFO pointer */
4617         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4618         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4619
4620         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4621 }
4622
4623 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4624 {
4625         static const struct ephy_info e_info_8168e_2[] = {
4626                 { 0x09, 0x0000, 0x0080 },
4627                 { 0x19, 0x0000, 0x0224 }
4628         };
4629
4630         rtl_csi_access_enable_1(ioaddr);
4631
4632         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4633
4634         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4635
4636         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4637         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4638         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4639         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4640         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4641         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4642         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4643         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4644                      ERIAR_EXGMAC);
4645
4646         RTL_W8(MaxTxPacketSize, EarlySize);
4647
4648         rtl_disable_clock_request(pdev);
4649
4650         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4651         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4652
4653         /* Adjust EEE LED frequency */
4654         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4655
4656         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4657         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4658         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4659 }
4660
4661 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4662 {
4663         static const struct ephy_info e_info_8168f_1[] = {
4664                 { 0x06, 0x00c0, 0x0020 },
4665                 { 0x08, 0x0001, 0x0002 },
4666                 { 0x09, 0x0000, 0x0080 },
4667                 { 0x19, 0x0000, 0x0224 }
4668         };
4669
4670         rtl_csi_access_enable_1(ioaddr);
4671
4672         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4673
4674         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4675
4676         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4677         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4678         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4679         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4680         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4681         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4682         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4683         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4684         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4685         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4686         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4687                      ERIAR_EXGMAC);
4688
4689         RTL_W8(MaxTxPacketSize, EarlySize);
4690
4691         rtl_disable_clock_request(pdev);
4692
4693         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4694         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4695
4696         /* Adjust EEE LED frequency */
4697         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4698
4699         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4700         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4701         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4702 }
4703
4704 static void rtl_hw_start_8168(struct net_device *dev)
4705 {
4706         struct rtl8169_private *tp = netdev_priv(dev);
4707         void __iomem *ioaddr = tp->mmio_addr;
4708         struct pci_dev *pdev = tp->pci_dev;
4709
4710         RTL_W8(Cfg9346, Cfg9346_Unlock);
4711
4712         RTL_W8(MaxTxPacketSize, TxPacketMax);
4713
4714         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4715
4716         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4717
4718         RTL_W16(CPlusCmd, tp->cp_cmd);
4719
4720         RTL_W16(IntrMitigate, 0x5151);
4721
4722         /* Work around for RxFIFO overflow. */
4723         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4724                 tp->event_slow |= RxFIFOOver | PCSTimeout;
4725                 tp->event_slow &= ~RxOverflow;
4726         }
4727
4728         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4729
4730         rtl_set_rx_mode(dev);
4731
4732         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4733                 (InterFrameGap << TxInterFrameGapShift));
4734
4735         RTL_R8(IntrMask);
4736
4737         switch (tp->mac_version) {
4738         case RTL_GIGA_MAC_VER_11:
4739                 rtl_hw_start_8168bb(ioaddr, pdev);
4740                 break;
4741
4742         case RTL_GIGA_MAC_VER_12:
4743         case RTL_GIGA_MAC_VER_17:
4744                 rtl_hw_start_8168bef(ioaddr, pdev);
4745                 break;
4746
4747         case RTL_GIGA_MAC_VER_18:
4748                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4749                 break;
4750
4751         case RTL_GIGA_MAC_VER_19:
4752                 rtl_hw_start_8168c_1(ioaddr, pdev);
4753                 break;
4754
4755         case RTL_GIGA_MAC_VER_20:
4756                 rtl_hw_start_8168c_2(ioaddr, pdev);
4757                 break;
4758
4759         case RTL_GIGA_MAC_VER_21:
4760                 rtl_hw_start_8168c_3(ioaddr, pdev);
4761                 break;
4762
4763         case RTL_GIGA_MAC_VER_22:
4764                 rtl_hw_start_8168c_4(ioaddr, pdev);
4765                 break;
4766
4767         case RTL_GIGA_MAC_VER_23:
4768                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4769                 break;
4770
4771         case RTL_GIGA_MAC_VER_24:
4772                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4773                 break;
4774
4775         case RTL_GIGA_MAC_VER_25:
4776         case RTL_GIGA_MAC_VER_26:
4777         case RTL_GIGA_MAC_VER_27:
4778                 rtl_hw_start_8168d(ioaddr, pdev);
4779                 break;
4780
4781         case RTL_GIGA_MAC_VER_28:
4782                 rtl_hw_start_8168d_4(ioaddr, pdev);
4783                 break;
4784
4785         case RTL_GIGA_MAC_VER_31:
4786                 rtl_hw_start_8168dp(ioaddr, pdev);
4787                 break;
4788
4789         case RTL_GIGA_MAC_VER_32:
4790         case RTL_GIGA_MAC_VER_33:
4791                 rtl_hw_start_8168e_1(ioaddr, pdev);
4792                 break;
4793         case RTL_GIGA_MAC_VER_34:
4794                 rtl_hw_start_8168e_2(ioaddr, pdev);
4795                 break;
4796
4797         case RTL_GIGA_MAC_VER_35:
4798         case RTL_GIGA_MAC_VER_36:
4799                 rtl_hw_start_8168f_1(ioaddr, pdev);
4800                 break;
4801
4802         default:
4803                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4804                         dev->name, tp->mac_version);
4805                 break;
4806         }
4807
4808         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4809
4810         RTL_W8(Cfg9346, Cfg9346_Lock);
4811
4812         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4813 }
4814
4815 #define R810X_CPCMD_QUIRK_MASK (\
4816         EnableBist | \
4817         Mac_dbgo_oe | \
4818         Force_half_dup | \
4819         Force_rxflow_en | \
4820         Force_txflow_en | \
4821         Cxpl_dbg_sel | \
4822         ASF | \
4823         PktCntrDisable | \
4824         Mac_dbgo_sel)
4825
4826 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4827 {
4828         static const struct ephy_info e_info_8102e_1[] = {
4829                 { 0x01, 0, 0x6e65 },
4830                 { 0x02, 0, 0x091f },
4831                 { 0x03, 0, 0xc2f9 },
4832                 { 0x06, 0, 0xafb5 },
4833                 { 0x07, 0, 0x0e00 },
4834                 { 0x19, 0, 0xec80 },
4835                 { 0x01, 0, 0x2e65 },
4836                 { 0x01, 0, 0x6e65 }
4837         };
4838         u8 cfg1;
4839
4840         rtl_csi_access_enable_2(ioaddr);
4841
4842         RTL_W8(DBG_REG, FIX_NAK_1);
4843
4844         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4845
4846         RTL_W8(Config1,
4847                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4848         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4849
4850         cfg1 = RTL_R8(Config1);
4851         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4852                 RTL_W8(Config1, cfg1 & ~LEDS0);
4853
4854         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4855 }
4856
4857 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4858 {
4859         rtl_csi_access_enable_2(ioaddr);
4860
4861         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4862
4863         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4864         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4865 }
4866
4867 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4868 {
4869         rtl_hw_start_8102e_2(ioaddr, pdev);
4870
4871         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4872 }
4873
4874 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4875 {
4876         static const struct ephy_info e_info_8105e_1[] = {
4877                 { 0x07, 0, 0x4000 },
4878                 { 0x19, 0, 0x0200 },
4879                 { 0x19, 0, 0x0020 },
4880                 { 0x1e, 0, 0x2000 },
4881                 { 0x03, 0, 0x0001 },
4882                 { 0x19, 0, 0x0100 },
4883                 { 0x19, 0, 0x0004 },
4884                 { 0x0a, 0, 0x0020 }
4885         };
4886
4887         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4888         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4889
4890         /* Disable Early Tally Counter */
4891         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4892
4893         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4894         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4895
4896         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4897 }
4898
4899 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4900 {
4901         rtl_hw_start_8105e_1(ioaddr, pdev);
4902         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4903 }
4904
4905 static void rtl_hw_start_8101(struct net_device *dev)
4906 {
4907         struct rtl8169_private *tp = netdev_priv(dev);
4908         void __iomem *ioaddr = tp->mmio_addr;
4909         struct pci_dev *pdev = tp->pci_dev;
4910
4911         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4912                 tp->event_slow &= ~RxFIFOOver;
4913
4914         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4915             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4916                 int cap = pci_pcie_cap(pdev);
4917
4918                 if (cap) {
4919                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4920                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4921                 }
4922         }
4923
4924         RTL_W8(Cfg9346, Cfg9346_Unlock);
4925
4926         switch (tp->mac_version) {
4927         case RTL_GIGA_MAC_VER_07:
4928                 rtl_hw_start_8102e_1(ioaddr, pdev);
4929                 break;
4930
4931         case RTL_GIGA_MAC_VER_08:
4932                 rtl_hw_start_8102e_3(ioaddr, pdev);
4933                 break;
4934
4935         case RTL_GIGA_MAC_VER_09:
4936                 rtl_hw_start_8102e_2(ioaddr, pdev);
4937                 break;
4938
4939         case RTL_GIGA_MAC_VER_29:
4940                 rtl_hw_start_8105e_1(ioaddr, pdev);
4941                 break;
4942         case RTL_GIGA_MAC_VER_30:
4943                 rtl_hw_start_8105e_2(ioaddr, pdev);
4944                 break;
4945         }
4946
4947         RTL_W8(Cfg9346, Cfg9346_Lock);
4948
4949         RTL_W8(MaxTxPacketSize, TxPacketMax);
4950
4951         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4952
4953         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4954         RTL_W16(CPlusCmd, tp->cp_cmd);
4955
4956         RTL_W16(IntrMitigate, 0x0000);
4957
4958         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4959
4960         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4961         rtl_set_rx_tx_config_registers(tp);
4962
4963         RTL_R8(IntrMask);
4964
4965         rtl_set_rx_mode(dev);
4966
4967         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4968 }
4969
4970 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4971 {
4972         struct rtl8169_private *tp = netdev_priv(dev);
4973
4974         if (new_mtu < ETH_ZLEN ||
4975             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4976                 return -EINVAL;
4977
4978         if (new_mtu > ETH_DATA_LEN)
4979                 rtl_hw_jumbo_enable(tp);
4980         else
4981                 rtl_hw_jumbo_disable(tp);
4982
4983         dev->mtu = new_mtu;
4984         netdev_update_features(dev);
4985
4986         return 0;
4987 }
4988
4989 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4990 {
4991         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4992         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4993 }
4994
4995 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4996                                      void **data_buff, struct RxDesc *desc)
4997 {
4998         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4999                          DMA_FROM_DEVICE);
5000
5001         kfree(*data_buff);
5002         *data_buff = NULL;
5003         rtl8169_make_unusable_by_asic(desc);
5004 }
5005
5006 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5007 {
5008         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5009
5010         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5011 }
5012
5013 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5014                                        u32 rx_buf_sz)
5015 {
5016         desc->addr = cpu_to_le64(mapping);
5017         wmb();
5018         rtl8169_mark_to_asic(desc, rx_buf_sz);
5019 }
5020
5021 static inline void *rtl8169_align(void *data)
5022 {
5023         return (void *)ALIGN((long)data, 16);
5024 }
5025
5026 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5027                                              struct RxDesc *desc)
5028 {
5029         void *data;
5030         dma_addr_t mapping;
5031         struct device *d = &tp->pci_dev->dev;
5032         struct net_device *dev = tp->dev;
5033         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5034
5035         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5036         if (!data)
5037                 return NULL;
5038
5039         if (rtl8169_align(data) != data) {
5040                 kfree(data);
5041                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5042                 if (!data)
5043                         return NULL;
5044         }
5045
5046         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5047                                  DMA_FROM_DEVICE);
5048         if (unlikely(dma_mapping_error(d, mapping))) {
5049                 if (net_ratelimit())
5050                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5051                 goto err_out;
5052         }
5053
5054         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5055         return data;
5056
5057 err_out:
5058         kfree(data);
5059         return NULL;
5060 }
5061
5062 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5063 {
5064         unsigned int i;
5065
5066         for (i = 0; i < NUM_RX_DESC; i++) {
5067                 if (tp->Rx_databuff[i]) {
5068                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5069                                             tp->RxDescArray + i);
5070                 }
5071         }
5072 }
5073
5074 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5075 {
5076         desc->opts1 |= cpu_to_le32(RingEnd);
5077 }
5078
5079 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5080 {
5081         unsigned int i;
5082
5083         for (i = 0; i < NUM_RX_DESC; i++) {
5084                 void *data;
5085
5086                 if (tp->Rx_databuff[i])
5087                         continue;
5088
5089                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5090                 if (!data) {
5091                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5092                         goto err_out;
5093                 }
5094                 tp->Rx_databuff[i] = data;
5095         }
5096
5097         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5098         return 0;
5099
5100 err_out:
5101         rtl8169_rx_clear(tp);
5102         return -ENOMEM;
5103 }
5104
5105 static int rtl8169_init_ring(struct net_device *dev)
5106 {
5107         struct rtl8169_private *tp = netdev_priv(dev);
5108
5109         rtl8169_init_ring_indexes(tp);
5110
5111         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5112         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5113
5114         return rtl8169_rx_fill(tp);
5115 }
5116
5117 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5118                                  struct TxDesc *desc)
5119 {
5120         unsigned int len = tx_skb->len;
5121
5122         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5123
5124         desc->opts1 = 0x00;
5125         desc->opts2 = 0x00;
5126         desc->addr = 0x00;
5127         tx_skb->len = 0;
5128 }
5129
5130 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5131                                    unsigned int n)
5132 {
5133         unsigned int i;
5134
5135         for (i = 0; i < n; i++) {
5136                 unsigned int entry = (start + i) % NUM_TX_DESC;
5137                 struct ring_info *tx_skb = tp->tx_skb + entry;
5138                 unsigned int len = tx_skb->len;
5139
5140                 if (len) {
5141                         struct sk_buff *skb = tx_skb->skb;
5142
5143                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5144                                              tp->TxDescArray + entry);
5145                         if (skb) {
5146                                 tp->dev->stats.tx_dropped++;
5147                                 dev_kfree_skb(skb);
5148                                 tx_skb->skb = NULL;
5149                         }
5150                 }
5151         }
5152 }
5153
5154 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5155 {
5156         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5157         tp->cur_tx = tp->dirty_tx = 0;
5158         netdev_reset_queue(tp->dev);
5159 }
5160
5161 static void rtl_reset_work(struct rtl8169_private *tp)
5162 {
5163         struct net_device *dev = tp->dev;
5164         int i;
5165
5166         napi_disable(&tp->napi);
5167         netif_stop_queue(dev);
5168         synchronize_sched();
5169
5170         rtl8169_hw_reset(tp);
5171
5172         for (i = 0; i < NUM_RX_DESC; i++)
5173                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5174
5175         rtl8169_tx_clear(tp);
5176         rtl8169_init_ring_indexes(tp);
5177
5178         napi_enable(&tp->napi);
5179         rtl_hw_start(dev);
5180         netif_wake_queue(dev);
5181         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5182 }
5183
5184 static void rtl8169_tx_timeout(struct net_device *dev)
5185 {
5186         struct rtl8169_private *tp = netdev_priv(dev);
5187
5188         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5189 }
5190
5191 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5192                               u32 *opts)
5193 {
5194         struct skb_shared_info *info = skb_shinfo(skb);
5195         unsigned int cur_frag, entry;
5196         struct TxDesc * uninitialized_var(txd);
5197         struct device *d = &tp->pci_dev->dev;
5198
5199         entry = tp->cur_tx;
5200         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5201                 const skb_frag_t *frag = info->frags + cur_frag;
5202                 dma_addr_t mapping;
5203                 u32 status, len;
5204                 void *addr;
5205
5206                 entry = (entry + 1) % NUM_TX_DESC;
5207
5208                 txd = tp->TxDescArray + entry;
5209                 len = skb_frag_size(frag);
5210                 addr = skb_frag_address(frag);
5211                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5212                 if (unlikely(dma_mapping_error(d, mapping))) {
5213                         if (net_ratelimit())
5214                                 netif_err(tp, drv, tp->dev,
5215                                           "Failed to map TX fragments DMA!\n");
5216                         goto err_out;
5217                 }
5218
5219                 /* Anti gcc 2.95.3 bugware (sic) */
5220                 status = opts[0] | len |
5221                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5222
5223                 txd->opts1 = cpu_to_le32(status);
5224                 txd->opts2 = cpu_to_le32(opts[1]);
5225                 txd->addr = cpu_to_le64(mapping);
5226
5227                 tp->tx_skb[entry].len = len;
5228         }
5229
5230         if (cur_frag) {
5231                 tp->tx_skb[entry].skb = skb;
5232                 txd->opts1 |= cpu_to_le32(LastFrag);
5233         }
5234
5235         return cur_frag;
5236
5237 err_out:
5238         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5239         return -EIO;
5240 }
5241
5242 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5243                                     struct sk_buff *skb, u32 *opts)
5244 {
5245         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5246         u32 mss = skb_shinfo(skb)->gso_size;
5247         int offset = info->opts_offset;
5248
5249         if (mss) {
5250                 opts[0] |= TD_LSO;
5251                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5252         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5253                 const struct iphdr *ip = ip_hdr(skb);
5254
5255                 if (ip->protocol == IPPROTO_TCP)
5256                         opts[offset] |= info->checksum.tcp;
5257                 else if (ip->protocol == IPPROTO_UDP)
5258                         opts[offset] |= info->checksum.udp;
5259                 else
5260                         WARN_ON_ONCE(1);
5261         }
5262 }
5263
5264 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5265                                       struct net_device *dev)
5266 {
5267         struct rtl8169_private *tp = netdev_priv(dev);
5268         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5269         struct TxDesc *txd = tp->TxDescArray + entry;
5270         void __iomem *ioaddr = tp->mmio_addr;
5271         struct device *d = &tp->pci_dev->dev;
5272         dma_addr_t mapping;
5273         u32 status, len;
5274         u32 opts[2];
5275         int frags;
5276
5277         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5278                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5279                 goto err_stop_0;
5280         }
5281
5282         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5283                 goto err_stop_0;
5284
5285         len = skb_headlen(skb);
5286         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5287         if (unlikely(dma_mapping_error(d, mapping))) {
5288                 if (net_ratelimit())
5289                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5290                 goto err_dma_0;
5291         }
5292
5293         tp->tx_skb[entry].len = len;
5294         txd->addr = cpu_to_le64(mapping);
5295
5296         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5297         opts[0] = DescOwn;
5298
5299         rtl8169_tso_csum(tp, skb, opts);
5300
5301         frags = rtl8169_xmit_frags(tp, skb, opts);
5302         if (frags < 0)
5303                 goto err_dma_1;
5304         else if (frags)
5305                 opts[0] |= FirstFrag;
5306         else {
5307                 opts[0] |= FirstFrag | LastFrag;
5308                 tp->tx_skb[entry].skb = skb;
5309         }
5310
5311         txd->opts2 = cpu_to_le32(opts[1]);
5312
5313         netdev_sent_queue(dev, skb->len);
5314
5315         wmb();
5316
5317         /* Anti gcc 2.95.3 bugware (sic) */
5318         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5319         txd->opts1 = cpu_to_le32(status);
5320
5321         tp->cur_tx += frags + 1;
5322
5323         wmb();
5324
5325         RTL_W8(TxPoll, NPQ);
5326
5327         mmiowb();
5328
5329         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5330                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5331                  * not miss a ring update when it notices a stopped queue.
5332                  */
5333                 smp_wmb();
5334                 netif_stop_queue(dev);
5335                 /* Sync with rtl_tx:
5336                  * - publish queue status and cur_tx ring index (write barrier)
5337                  * - refresh dirty_tx ring index (read barrier).
5338                  * May the current thread have a pessimistic view of the ring
5339                  * status and forget to wake up queue, a racing rtl_tx thread
5340                  * can't.
5341                  */
5342                 smp_mb();
5343                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5344                         netif_wake_queue(dev);
5345         }
5346
5347         return NETDEV_TX_OK;
5348
5349 err_dma_1:
5350         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5351 err_dma_0:
5352         dev_kfree_skb(skb);
5353         dev->stats.tx_dropped++;
5354         return NETDEV_TX_OK;
5355
5356 err_stop_0:
5357         netif_stop_queue(dev);
5358         dev->stats.tx_dropped++;
5359         return NETDEV_TX_BUSY;
5360 }
5361
5362 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5363 {
5364         struct rtl8169_private *tp = netdev_priv(dev);
5365         struct pci_dev *pdev = tp->pci_dev;
5366         u16 pci_status, pci_cmd;
5367
5368         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5369         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5370
5371         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5372                   pci_cmd, pci_status);
5373
5374         /*
5375          * The recovery sequence below admits a very elaborated explanation:
5376          * - it seems to work;
5377          * - I did not see what else could be done;
5378          * - it makes iop3xx happy.
5379          *
5380          * Feel free to adjust to your needs.
5381          */
5382         if (pdev->broken_parity_status)
5383                 pci_cmd &= ~PCI_COMMAND_PARITY;
5384         else
5385                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5386
5387         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5388
5389         pci_write_config_word(pdev, PCI_STATUS,
5390                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5391                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5392                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5393
5394         /* The infamous DAC f*ckup only happens at boot time */
5395         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5396                 void __iomem *ioaddr = tp->mmio_addr;
5397
5398                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5399                 tp->cp_cmd &= ~PCIDAC;
5400                 RTL_W16(CPlusCmd, tp->cp_cmd);
5401                 dev->features &= ~NETIF_F_HIGHDMA;
5402         }
5403
5404         rtl8169_hw_reset(tp);
5405
5406         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5407 }
5408
5409 struct rtl_txc {
5410         int packets;
5411         int bytes;
5412 };
5413
5414 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5415 {
5416         struct rtl8169_stats *tx_stats = &tp->tx_stats;
5417         unsigned int dirty_tx, tx_left;
5418         struct rtl_txc txc = { 0, 0 };
5419
5420         dirty_tx = tp->dirty_tx;
5421         smp_rmb();
5422         tx_left = tp->cur_tx - dirty_tx;
5423
5424         while (tx_left > 0) {
5425                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5426                 struct ring_info *tx_skb = tp->tx_skb + entry;
5427                 u32 status;
5428
5429                 rmb();
5430                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5431                 if (status & DescOwn)
5432                         break;
5433
5434                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5435                                      tp->TxDescArray + entry);
5436                 if (status & LastFrag) {
5437                         struct sk_buff *skb = tx_skb->skb;
5438
5439                         txc.packets++;
5440                         txc.bytes += skb->len;
5441                         dev_kfree_skb(skb);
5442                         tx_skb->skb = NULL;
5443                 }
5444                 dirty_tx++;
5445                 tx_left--;
5446         }
5447
5448         u64_stats_update_begin(&tx_stats->syncp);
5449         tx_stats->packets += txc.packets;
5450         tx_stats->bytes += txc.bytes;
5451         u64_stats_update_end(&tx_stats->syncp);
5452
5453         netdev_completed_queue(dev, txc.packets, txc.bytes);
5454
5455         if (tp->dirty_tx != dirty_tx) {
5456                 tp->dirty_tx = dirty_tx;
5457                 /* Sync with rtl8169_start_xmit:
5458                  * - publish dirty_tx ring index (write barrier)
5459                  * - refresh cur_tx ring index and queue status (read barrier)
5460                  * May the current thread miss the stopped queue condition,
5461                  * a racing xmit thread can only have a right view of the
5462                  * ring status.
5463                  */
5464                 smp_mb();
5465                 if (netif_queue_stopped(dev) &&
5466                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5467                         netif_wake_queue(dev);
5468                 }
5469                 /*
5470                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5471                  * too close. Let's kick an extra TxPoll request when a burst
5472                  * of start_xmit activity is detected (if it is not detected,
5473                  * it is slow enough). -- FR
5474                  */
5475                 if (tp->cur_tx != dirty_tx) {
5476                         void __iomem *ioaddr = tp->mmio_addr;
5477
5478                         RTL_W8(TxPoll, NPQ);
5479                 }
5480         }
5481 }
5482
5483 static inline int rtl8169_fragmented_frame(u32 status)
5484 {
5485         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5486 }
5487
5488 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5489 {
5490         u32 status = opts1 & RxProtoMask;
5491
5492         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5493             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5494                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5495         else
5496                 skb_checksum_none_assert(skb);
5497 }
5498
5499 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5500                                            struct rtl8169_private *tp,
5501                                            int pkt_size,
5502                                            dma_addr_t addr)
5503 {
5504         struct sk_buff *skb;
5505         struct device *d = &tp->pci_dev->dev;
5506
5507         data = rtl8169_align(data);
5508         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5509         prefetch(data);
5510         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5511         if (skb)
5512                 memcpy(skb->data, data, pkt_size);
5513         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5514
5515         return skb;
5516 }
5517
5518 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5519 {
5520         unsigned int cur_rx, rx_left;
5521         unsigned int count;
5522
5523         cur_rx = tp->cur_rx;
5524         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5525         rx_left = min(rx_left, budget);
5526
5527         for (; rx_left > 0; rx_left--, cur_rx++) {
5528                 unsigned int entry = cur_rx % NUM_RX_DESC;
5529                 struct RxDesc *desc = tp->RxDescArray + entry;
5530                 u32 status;
5531
5532                 rmb();
5533                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5534
5535                 if (status & DescOwn)
5536                         break;
5537                 if (unlikely(status & RxRES)) {
5538                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5539                                    status);
5540                         dev->stats.rx_errors++;
5541                         if (status & (RxRWT | RxRUNT))
5542                                 dev->stats.rx_length_errors++;
5543                         if (status & RxCRC)
5544                                 dev->stats.rx_crc_errors++;
5545                         if (status & RxFOVF) {
5546                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5547                                 dev->stats.rx_fifo_errors++;
5548                         }
5549                         if ((status & (RxRUNT | RxCRC)) &&
5550                             !(status & (RxRWT | RxFOVF)) &&
5551                             (dev->features & NETIF_F_RXALL))
5552                                 goto process_pkt;
5553
5554                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5555                 } else {
5556                         struct sk_buff *skb;
5557                         dma_addr_t addr;
5558                         int pkt_size;
5559
5560 process_pkt:
5561                         addr = le64_to_cpu(desc->addr);
5562                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5563                                 pkt_size = (status & 0x00003fff) - 4;
5564                         else
5565                                 pkt_size = status & 0x00003fff;
5566
5567                         /*
5568                          * The driver does not support incoming fragmented
5569                          * frames. They are seen as a symptom of over-mtu
5570                          * sized frames.
5571                          */
5572                         if (unlikely(rtl8169_fragmented_frame(status))) {
5573                                 dev->stats.rx_dropped++;
5574                                 dev->stats.rx_length_errors++;
5575                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5576                                 continue;
5577                         }
5578
5579                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5580                                                   tp, pkt_size, addr);
5581                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5582                         if (!skb) {
5583                                 dev->stats.rx_dropped++;
5584                                 continue;
5585                         }
5586
5587                         rtl8169_rx_csum(skb, status);
5588                         skb_put(skb, pkt_size);
5589                         skb->protocol = eth_type_trans(skb, dev);
5590
5591                         rtl8169_rx_vlan_tag(desc, skb);
5592
5593                         napi_gro_receive(&tp->napi, skb);
5594
5595                         u64_stats_update_begin(&tp->rx_stats.syncp);
5596                         tp->rx_stats.packets++;
5597                         tp->rx_stats.bytes += pkt_size;
5598                         u64_stats_update_end(&tp->rx_stats.syncp);
5599                 }
5600
5601                 /* Work around for AMD plateform. */
5602                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5603                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5604                         desc->opts2 = 0;
5605                         cur_rx++;
5606                 }
5607         }
5608
5609         count = cur_rx - tp->cur_rx;
5610         tp->cur_rx = cur_rx;
5611
5612         tp->dirty_rx += count;
5613
5614         return count;
5615 }
5616
5617 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5618 {
5619         struct net_device *dev = dev_instance;
5620         struct rtl8169_private *tp = netdev_priv(dev);
5621         int handled = 0;
5622         u16 status;
5623
5624         status = rtl_get_events(tp);
5625         if (status && status != 0xffff) {
5626                 status &= RTL_EVENT_NAPI | tp->event_slow;
5627                 if (status) {
5628                         handled = 1;
5629
5630                         rtl_irq_disable(tp);
5631                         napi_schedule(&tp->napi);
5632                 }
5633         }
5634         return IRQ_RETVAL(handled);
5635 }
5636
5637 /*
5638  * Workqueue context.
5639  */
5640 static void rtl_slow_event_work(struct rtl8169_private *tp)
5641 {
5642         struct net_device *dev = tp->dev;
5643         u16 status;
5644
5645         status = rtl_get_events(tp) & tp->event_slow;
5646         rtl_ack_events(tp, status);
5647
5648         if (unlikely(status & RxFIFOOver)) {
5649                 switch (tp->mac_version) {
5650                 /* Work around for rx fifo overflow */
5651                 case RTL_GIGA_MAC_VER_11:
5652                         netif_stop_queue(dev);
5653                         /* XXX - Hack alert. See rtl_task(). */
5654                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5655                 default:
5656                         break;
5657                 }
5658         }
5659
5660         if (unlikely(status & SYSErr))
5661                 rtl8169_pcierr_interrupt(dev);
5662
5663         if (status & LinkChg)
5664                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5665
5666         napi_disable(&tp->napi);
5667         rtl_irq_disable(tp);
5668
5669         napi_enable(&tp->napi);
5670         napi_schedule(&tp->napi);
5671 }
5672
5673 static void rtl_task(struct work_struct *work)
5674 {
5675         static const struct {
5676                 int bitnr;
5677                 void (*action)(struct rtl8169_private *);
5678         } rtl_work[] = {
5679                 /* XXX - keep rtl_slow_event_work() as first element. */
5680                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
5681                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
5682                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
5683         };
5684         struct rtl8169_private *tp =
5685                 container_of(work, struct rtl8169_private, wk.work);
5686         struct net_device *dev = tp->dev;
5687         int i;
5688
5689         rtl_lock_work(tp);
5690
5691         if (!netif_running(dev) ||
5692             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5693                 goto out_unlock;
5694
5695         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5696                 bool pending;
5697
5698                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5699                 if (pending)
5700                         rtl_work[i].action(tp);
5701         }
5702
5703 out_unlock:
5704         rtl_unlock_work(tp);
5705 }
5706
5707 static int rtl8169_poll(struct napi_struct *napi, int budget)
5708 {
5709         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5710         struct net_device *dev = tp->dev;
5711         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5712         int work_done= 0;
5713         u16 status;
5714
5715         status = rtl_get_events(tp);
5716         rtl_ack_events(tp, status & ~tp->event_slow);
5717
5718         if (status & RTL_EVENT_NAPI_RX)
5719                 work_done = rtl_rx(dev, tp, (u32) budget);
5720
5721         if (status & RTL_EVENT_NAPI_TX)
5722                 rtl_tx(dev, tp);
5723
5724         if (status & tp->event_slow) {
5725                 enable_mask &= ~tp->event_slow;
5726
5727                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5728         }
5729
5730         if (work_done < budget) {
5731                 napi_complete(napi);
5732
5733                 rtl_irq_enable(tp, enable_mask);
5734                 mmiowb();
5735         }
5736
5737         return work_done;
5738 }
5739
5740 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5741 {
5742         struct rtl8169_private *tp = netdev_priv(dev);
5743
5744         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5745                 return;
5746
5747         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5748         RTL_W32(RxMissed, 0);
5749 }
5750
5751 static void rtl8169_down(struct net_device *dev)
5752 {
5753         struct rtl8169_private *tp = netdev_priv(dev);
5754         void __iomem *ioaddr = tp->mmio_addr;
5755
5756         del_timer_sync(&tp->timer);
5757
5758         napi_disable(&tp->napi);
5759         netif_stop_queue(dev);
5760
5761         rtl8169_hw_reset(tp);
5762         /*
5763          * At this point device interrupts can not be enabled in any function,
5764          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5765          * and napi is disabled (rtl8169_poll).
5766          */
5767         rtl8169_rx_missed(dev, ioaddr);
5768
5769         /* Give a racing hard_start_xmit a few cycles to complete. */
5770         synchronize_sched();
5771
5772         rtl8169_tx_clear(tp);
5773
5774         rtl8169_rx_clear(tp);
5775
5776         rtl_pll_power_down(tp);
5777 }
5778
5779 static int rtl8169_close(struct net_device *dev)
5780 {
5781         struct rtl8169_private *tp = netdev_priv(dev);
5782         struct pci_dev *pdev = tp->pci_dev;
5783
5784         pm_runtime_get_sync(&pdev->dev);
5785
5786         /* Update counters before going down */
5787         rtl8169_update_counters(dev);
5788
5789         rtl_lock_work(tp);
5790         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5791
5792         rtl8169_down(dev);
5793         rtl_unlock_work(tp);
5794
5795         free_irq(dev->irq, dev);
5796
5797         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5798                           tp->RxPhyAddr);
5799         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5800                           tp->TxPhyAddr);
5801         tp->TxDescArray = NULL;
5802         tp->RxDescArray = NULL;
5803
5804         pm_runtime_put_sync(&pdev->dev);
5805
5806         return 0;
5807 }
5808
5809 static struct rtnl_link_stats64 *
5810 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5811 {
5812         struct rtl8169_private *tp = netdev_priv(dev);
5813         void __iomem *ioaddr = tp->mmio_addr;
5814         unsigned int start;
5815
5816         if (netif_running(dev))
5817                 rtl8169_rx_missed(dev, ioaddr);
5818
5819         do {
5820                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5821                 stats->rx_packets = tp->rx_stats.packets;
5822                 stats->rx_bytes = tp->rx_stats.bytes;
5823         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5824
5825
5826         do {
5827                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5828                 stats->tx_packets = tp->tx_stats.packets;
5829                 stats->tx_bytes = tp->tx_stats.bytes;
5830         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5831
5832         stats->rx_dropped       = dev->stats.rx_dropped;
5833         stats->tx_dropped       = dev->stats.tx_dropped;
5834         stats->rx_length_errors = dev->stats.rx_length_errors;
5835         stats->rx_errors        = dev->stats.rx_errors;
5836         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
5837         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
5838         stats->rx_missed_errors = dev->stats.rx_missed_errors;
5839
5840         return stats;
5841 }
5842
5843 static void rtl8169_net_suspend(struct net_device *dev)
5844 {
5845         struct rtl8169_private *tp = netdev_priv(dev);
5846
5847         if (!netif_running(dev))
5848                 return;
5849
5850         netif_device_detach(dev);
5851         netif_stop_queue(dev);
5852
5853         rtl_lock_work(tp);
5854         napi_disable(&tp->napi);
5855         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5856         rtl_unlock_work(tp);
5857
5858         rtl_pll_power_down(tp);
5859 }
5860
5861 #ifdef CONFIG_PM
5862
5863 static int rtl8169_suspend(struct device *device)
5864 {
5865         struct pci_dev *pdev = to_pci_dev(device);
5866         struct net_device *dev = pci_get_drvdata(pdev);
5867
5868         rtl8169_net_suspend(dev);
5869
5870         return 0;
5871 }
5872
5873 static void __rtl8169_resume(struct net_device *dev)
5874 {
5875         struct rtl8169_private *tp = netdev_priv(dev);
5876
5877         netif_device_attach(dev);
5878
5879         rtl_pll_power_up(tp);
5880
5881         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5882
5883         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5884 }
5885
5886 static int rtl8169_resume(struct device *device)
5887 {
5888         struct pci_dev *pdev = to_pci_dev(device);
5889         struct net_device *dev = pci_get_drvdata(pdev);
5890         struct rtl8169_private *tp = netdev_priv(dev);
5891
5892         rtl8169_init_phy(dev, tp);
5893
5894         if (netif_running(dev))
5895                 __rtl8169_resume(dev);
5896
5897         return 0;
5898 }
5899
5900 static int rtl8169_runtime_suspend(struct device *device)
5901 {
5902         struct pci_dev *pdev = to_pci_dev(device);
5903         struct net_device *dev = pci_get_drvdata(pdev);
5904         struct rtl8169_private *tp = netdev_priv(dev);
5905
5906         if (!tp->TxDescArray)
5907                 return 0;
5908
5909         rtl_lock_work(tp);
5910         tp->saved_wolopts = __rtl8169_get_wol(tp);
5911         __rtl8169_set_wol(tp, WAKE_ANY);
5912         rtl_unlock_work(tp);
5913
5914         rtl8169_net_suspend(dev);
5915
5916         return 0;
5917 }
5918
5919 static int rtl8169_runtime_resume(struct device *device)
5920 {
5921         struct pci_dev *pdev = to_pci_dev(device);
5922         struct net_device *dev = pci_get_drvdata(pdev);
5923         struct rtl8169_private *tp = netdev_priv(dev);
5924
5925         if (!tp->TxDescArray)
5926                 return 0;
5927
5928         rtl_lock_work(tp);
5929         __rtl8169_set_wol(tp, tp->saved_wolopts);
5930         tp->saved_wolopts = 0;
5931         rtl_unlock_work(tp);
5932
5933         rtl8169_init_phy(dev, tp);
5934
5935         __rtl8169_resume(dev);
5936
5937         return 0;
5938 }
5939
5940 static int rtl8169_runtime_idle(struct device *device)
5941 {
5942         struct pci_dev *pdev = to_pci_dev(device);
5943         struct net_device *dev = pci_get_drvdata(pdev);
5944         struct rtl8169_private *tp = netdev_priv(dev);
5945
5946         return tp->TxDescArray ? -EBUSY : 0;
5947 }
5948
5949 static const struct dev_pm_ops rtl8169_pm_ops = {
5950         .suspend                = rtl8169_suspend,
5951         .resume                 = rtl8169_resume,
5952         .freeze                 = rtl8169_suspend,
5953         .thaw                   = rtl8169_resume,
5954         .poweroff               = rtl8169_suspend,
5955         .restore                = rtl8169_resume,
5956         .runtime_suspend        = rtl8169_runtime_suspend,
5957         .runtime_resume         = rtl8169_runtime_resume,
5958         .runtime_idle           = rtl8169_runtime_idle,
5959 };
5960
5961 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5962
5963 #else /* !CONFIG_PM */
5964
5965 #define RTL8169_PM_OPS  NULL
5966
5967 #endif /* !CONFIG_PM */
5968
5969 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5970 {
5971         void __iomem *ioaddr = tp->mmio_addr;
5972
5973         /* WoL fails with 8168b when the receiver is disabled. */
5974         switch (tp->mac_version) {
5975         case RTL_GIGA_MAC_VER_11:
5976         case RTL_GIGA_MAC_VER_12:
5977         case RTL_GIGA_MAC_VER_17:
5978                 pci_clear_master(tp->pci_dev);
5979
5980                 RTL_W8(ChipCmd, CmdRxEnb);
5981                 /* PCI commit */
5982                 RTL_R8(ChipCmd);
5983                 break;
5984         default:
5985                 break;
5986         }
5987 }
5988
5989 static void rtl_shutdown(struct pci_dev *pdev)
5990 {
5991         struct net_device *dev = pci_get_drvdata(pdev);
5992         struct rtl8169_private *tp = netdev_priv(dev);
5993         struct device *d = &pdev->dev;
5994
5995         pm_runtime_get_sync(d);
5996
5997         rtl8169_net_suspend(dev);
5998
5999         /* Restore original MAC address */
6000         rtl_rar_set(tp, dev->perm_addr);
6001
6002         rtl8169_hw_reset(tp);
6003
6004         if (system_state == SYSTEM_POWER_OFF) {
6005                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6006                         rtl_wol_suspend_quirk(tp);
6007                         rtl_wol_shutdown_quirk(tp);
6008                 }
6009
6010                 pci_wake_from_d3(pdev, true);
6011                 pci_set_power_state(pdev, PCI_D3hot);
6012         }
6013
6014         pm_runtime_put_noidle(d);
6015 }
6016
6017 static void __devexit rtl_remove_one(struct pci_dev *pdev)
6018 {
6019         struct net_device *dev = pci_get_drvdata(pdev);
6020         struct rtl8169_private *tp = netdev_priv(dev);
6021
6022         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6023             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6024             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6025                 rtl8168_driver_stop(tp);
6026         }
6027
6028         cancel_work_sync(&tp->wk.work);
6029
6030         unregister_netdev(dev);
6031
6032         rtl_release_firmware(tp);
6033
6034         if (pci_dev_run_wake(pdev))
6035                 pm_runtime_get_noresume(&pdev->dev);
6036
6037         /* restore original MAC address */
6038         rtl_rar_set(tp, dev->perm_addr);
6039
6040         rtl_disable_msi(pdev, tp);
6041         rtl8169_release_board(pdev, dev, tp->mmio_addr);
6042         pci_set_drvdata(pdev, NULL);
6043 }
6044
6045 static const struct net_device_ops rtl_netdev_ops = {
6046         .ndo_open               = rtl8169_open,
6047         .ndo_stop               = rtl8169_close,
6048         .ndo_get_stats64        = rtl8169_get_stats64,
6049         .ndo_start_xmit         = rtl8169_start_xmit,
6050         .ndo_tx_timeout         = rtl8169_tx_timeout,
6051         .ndo_validate_addr      = eth_validate_addr,
6052         .ndo_change_mtu         = rtl8169_change_mtu,
6053         .ndo_fix_features       = rtl8169_fix_features,
6054         .ndo_set_features       = rtl8169_set_features,
6055         .ndo_set_mac_address    = rtl_set_mac_address,
6056         .ndo_do_ioctl           = rtl8169_ioctl,
6057         .ndo_set_rx_mode        = rtl_set_rx_mode,
6058 #ifdef CONFIG_NET_POLL_CONTROLLER
6059         .ndo_poll_controller    = rtl8169_netpoll,
6060 #endif
6061
6062 };
6063
6064 static int __devinit
6065 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6066 {
6067         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6068         const unsigned int region = cfg->region;
6069         struct rtl8169_private *tp;
6070         struct mii_if_info *mii;
6071         struct net_device *dev;
6072         void __iomem *ioaddr;
6073         int chipset, i;
6074         int rc;
6075
6076         if (netif_msg_drv(&debug)) {
6077                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6078                        MODULENAME, RTL8169_VERSION);
6079         }
6080
6081         dev = alloc_etherdev(sizeof (*tp));
6082         if (!dev) {
6083                 rc = -ENOMEM;
6084                 goto out;
6085         }
6086
6087         SET_NETDEV_DEV(dev, &pdev->dev);
6088         dev->netdev_ops = &rtl_netdev_ops;
6089         tp = netdev_priv(dev);
6090         tp->dev = dev;
6091         tp->pci_dev = pdev;
6092         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6093
6094         mii = &tp->mii;
6095         mii->dev = dev;
6096         mii->mdio_read = rtl_mdio_read;
6097         mii->mdio_write = rtl_mdio_write;
6098         mii->phy_id_mask = 0x1f;
6099         mii->reg_num_mask = 0x1f;
6100         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6101
6102         /* disable ASPM completely as that cause random device stop working
6103          * problems as well as full system hangs for some PCIe devices users */
6104         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6105                                      PCIE_LINK_STATE_CLKPM);
6106
6107         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6108         rc = pci_enable_device(pdev);
6109         if (rc < 0) {
6110                 netif_err(tp, probe, dev, "enable failure\n");
6111                 goto err_out_free_dev_1;
6112         }
6113
6114         if (pci_set_mwi(pdev) < 0)
6115                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6116
6117         /* make sure PCI base addr 1 is MMIO */
6118         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6119                 netif_err(tp, probe, dev,
6120                           "region #%d not an MMIO resource, aborting\n",
6121                           region);
6122                 rc = -ENODEV;
6123                 goto err_out_mwi_2;
6124         }
6125
6126         /* check for weird/broken PCI region reporting */
6127         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6128                 netif_err(tp, probe, dev,
6129                           "Invalid PCI region size(s), aborting\n");
6130                 rc = -ENODEV;
6131                 goto err_out_mwi_2;
6132         }
6133
6134         rc = pci_request_regions(pdev, MODULENAME);
6135         if (rc < 0) {
6136                 netif_err(tp, probe, dev, "could not request regions\n");
6137                 goto err_out_mwi_2;
6138         }
6139
6140         tp->cp_cmd = RxChkSum;
6141
6142         if ((sizeof(dma_addr_t) > 4) &&
6143             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6144                 tp->cp_cmd |= PCIDAC;
6145                 dev->features |= NETIF_F_HIGHDMA;
6146         } else {
6147                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6148                 if (rc < 0) {
6149                         netif_err(tp, probe, dev, "DMA configuration failed\n");
6150                         goto err_out_free_res_3;
6151                 }
6152         }
6153
6154         /* ioremap MMIO region */
6155         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6156         if (!ioaddr) {
6157                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6158                 rc = -EIO;
6159                 goto err_out_free_res_3;
6160         }
6161         tp->mmio_addr = ioaddr;
6162
6163         if (!pci_is_pcie(pdev))
6164                 netif_info(tp, probe, dev, "not PCI Express\n");
6165
6166         /* Identify chip attached to board */
6167         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6168
6169         rtl_init_rxcfg(tp);
6170
6171         rtl_irq_disable(tp);
6172
6173         rtl_hw_reset(tp);
6174
6175         rtl_ack_events(tp, 0xffff);
6176
6177         pci_set_master(pdev);
6178
6179         /*
6180          * Pretend we are using VLANs; This bypasses a nasty bug where
6181          * Interrupts stop flowing on high load on 8110SCd controllers.
6182          */
6183         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6184                 tp->cp_cmd |= RxVlan;
6185
6186         rtl_init_mdio_ops(tp);
6187         rtl_init_pll_power_ops(tp);
6188         rtl_init_jumbo_ops(tp);
6189
6190         rtl8169_print_mac_version(tp);
6191
6192         chipset = tp->mac_version;
6193         tp->txd_version = rtl_chip_infos[chipset].txd_version;
6194
6195         RTL_W8(Cfg9346, Cfg9346_Unlock);
6196         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6197         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6198         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6199                 tp->features |= RTL_FEATURE_WOL;
6200         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6201                 tp->features |= RTL_FEATURE_WOL;
6202         tp->features |= rtl_try_msi(tp, cfg);
6203         RTL_W8(Cfg9346, Cfg9346_Lock);
6204
6205         if (rtl_tbi_enabled(tp)) {
6206                 tp->set_speed = rtl8169_set_speed_tbi;
6207                 tp->get_settings = rtl8169_gset_tbi;
6208                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6209                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6210                 tp->link_ok = rtl8169_tbi_link_ok;
6211                 tp->do_ioctl = rtl_tbi_ioctl;
6212         } else {
6213                 tp->set_speed = rtl8169_set_speed_xmii;
6214                 tp->get_settings = rtl8169_gset_xmii;
6215                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6216                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6217                 tp->link_ok = rtl8169_xmii_link_ok;
6218                 tp->do_ioctl = rtl_xmii_ioctl;
6219         }
6220
6221         mutex_init(&tp->wk.mutex);
6222
6223         /* Get MAC address */
6224         for (i = 0; i < ETH_ALEN; i++)
6225                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6226         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6227
6228         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6229         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6230         dev->irq = pdev->irq;
6231         dev->base_addr = (unsigned long) ioaddr;
6232
6233         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6234
6235         /* don't enable SG, IP_CSUM and TSO by default - it might not work
6236          * properly for all devices */
6237         dev->features |= NETIF_F_RXCSUM |
6238                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6239
6240         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6241                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6242         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6243                 NETIF_F_HIGHDMA;
6244
6245         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6246                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6247                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6248
6249         dev->hw_features |= NETIF_F_RXALL;
6250         dev->hw_features |= NETIF_F_RXFCS;
6251
6252         tp->hw_start = cfg->hw_start;
6253         tp->event_slow = cfg->event_slow;
6254
6255         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6256                 ~(RxBOVF | RxFOVF) : ~0;
6257
6258         init_timer(&tp->timer);
6259         tp->timer.data = (unsigned long) dev;
6260         tp->timer.function = rtl8169_phy_timer;
6261
6262         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6263
6264         rc = register_netdev(dev);
6265         if (rc < 0)
6266                 goto err_out_msi_4;
6267
6268         pci_set_drvdata(pdev, dev);
6269
6270         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
6271                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
6272                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
6273         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6274                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6275                            "tx checksumming: %s]\n",
6276                            rtl_chip_infos[chipset].jumbo_max,
6277                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6278         }
6279
6280         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6281             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6282             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6283                 rtl8168_driver_start(tp);
6284         }
6285
6286         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6287
6288         if (pci_dev_run_wake(pdev))
6289                 pm_runtime_put_noidle(&pdev->dev);
6290
6291         netif_carrier_off(dev);
6292
6293 out:
6294         return rc;
6295
6296 err_out_msi_4:
6297         rtl_disable_msi(pdev, tp);
6298         iounmap(ioaddr);
6299 err_out_free_res_3:
6300         pci_release_regions(pdev);
6301 err_out_mwi_2:
6302         pci_clear_mwi(pdev);
6303         pci_disable_device(pdev);
6304 err_out_free_dev_1:
6305         free_netdev(dev);
6306         goto out;
6307 }
6308
6309 static struct pci_driver rtl8169_pci_driver = {
6310         .name           = MODULENAME,
6311         .id_table       = rtl8169_pci_tbl,
6312         .probe          = rtl_init_one,
6313         .remove         = __devexit_p(rtl_remove_one),
6314         .shutdown       = rtl_shutdown,
6315         .driver.pm      = RTL8169_PM_OPS,
6316 };
6317
6318 static int __init rtl8169_init_module(void)
6319 {
6320         return pci_register_driver(&rtl8169_pci_driver);
6321 }
6322
6323 static void __exit rtl8169_cleanup_module(void)
6324 {
6325         pci_unregister_driver(&rtl8169_pci_driver);
6326 }
6327
6328 module_init(rtl8169_init_module);
6329 module_exit(rtl8169_cleanup_module);