3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
23 This driver is for boards based on the RTL8129 and RTL8139
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
46 Tigran Aivazian - bug fixes, skbuff free cleanup
48 Martin Mares - suggestions for PCI cleanup
50 David S. Miller - PCI DMA and softnet updates
52 Ernst Gill - fixes ported from BSD driver
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
57 Gerard Sharp - bug fix, testing and feedback
59 David Ford - Rx ring wrap fix
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
67 Santiago Garcia Mantinan - testing and feedback
69 Jens David - 2.2.x kernel backports
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
74 Jean-Jacques Michel - bug fix
76 Tobias Ringström - Rx interrupt status checking suggestion
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
83 Robert Kuebel - Save kernel thread from dying on any signal.
85 Submitting bug reports:
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
92 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
94 #define DRV_NAME "8139too"
95 #define DRV_VERSION "0.9.28"
98 #include <linux/module.h>
99 #include <linux/kernel.h>
100 #include <linux/compiler.h>
101 #include <linux/pci.h>
102 #include <linux/init.h>
103 #include <linux/interrupt.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/rtnetlink.h>
107 #include <linux/delay.h>
108 #include <linux/ethtool.h>
109 #include <linux/mii.h>
110 #include <linux/completion.h>
111 #include <linux/crc32.h>
112 #include <linux/io.h>
113 #include <linux/uaccess.h>
114 #include <linux/gfp.h>
117 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
119 /* Default Message level */
120 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
125 /* define to 1, 2 or 3 to enable copious debugging info */
126 #define RTL8139_DEBUG 0
128 /* define to 1 to disable lightweight runtime debugging checks */
129 #undef RTL8139_NDEBUG
132 #ifdef RTL8139_NDEBUG
133 # define assert(expr) do {} while (0)
135 # define assert(expr) \
136 if (unlikely(!(expr))) { \
137 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \
138 #expr, __FILE__, __func__, __LINE__); \
143 /* A few user-configurable values. */
146 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
147 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
149 /* Whether to use MMIO or PIO. Default to MMIO. */
150 #ifdef CONFIG_8139TOO_PIO
151 static bool use_io = true;
153 static bool use_io = false;
156 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
157 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
158 static int multicast_filter_limit = 32;
160 /* bitmapped message enable number */
161 static int debug = -1;
165 * Warning: 64K ring has hardware issues and may lock up.
167 #if defined(CONFIG_SH_DREAMCAST)
168 #define RX_BUF_IDX 0 /* 8K ring */
170 #define RX_BUF_IDX 2 /* 32K ring */
172 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
173 #define RX_BUF_PAD 16
174 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
176 #if RX_BUF_LEN == 65536
177 #define RX_BUF_TOT_LEN RX_BUF_LEN
179 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
182 /* Number of Tx descriptor registers. */
183 #define NUM_TX_DESC 4
185 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
186 #define MAX_ETH_FRAME_SIZE 1536
188 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
189 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
190 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
192 /* PCI Tuning Parameters
193 Threshold is bytes transferred to chip before transmission starts. */
194 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
196 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
197 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
198 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
199 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
200 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
202 /* Operational parameters that usually are not changed. */
203 /* Time in jiffies before concluding the transmitter is hung. */
204 #define TX_TIMEOUT (6*HZ)
208 HAS_MII_XCVR = 0x010000,
209 HAS_CHIP_XCVR = 0x020000,
210 HAS_LNK_CHNG = 0x040000,
213 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
214 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
215 #define RTL_MIN_IO_SIZE 0x80
216 #define RTL8139B_IO_SIZE 256
218 #define RTL8129_CAPS HAS_MII_XCVR
219 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
227 /* indexed by board_t, above */
228 static const struct {
232 { "RealTek RTL8139", RTL8139_CAPS },
233 { "RealTek RTL8129", RTL8129_CAPS },
237 static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {
238 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
239 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
240 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
241 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 #ifdef CONFIG_SH_SECUREEDGE5410
259 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
260 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
262 #ifdef CONFIG_8139TOO_8129
263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
266 /* some crazy cards report invalid vendor ids like
267 * 0x0001 here. The other ids are valid and constant,
268 * so we simply don't match on the main vendor id.
270 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
271 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
272 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
276 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
279 const char str[ETH_GSTRING_LEN];
280 } ethtool_stats_keys[] = {
284 { "rx_lost_in_ring" },
287 /* The rest of these values should never change. */
289 /* Symbolic offsets to registers. */
290 enum RTL8139_registers {
291 MAC0 = 0, /* Ethernet hardware address. */
292 MAR0 = 8, /* Multicast filter. */
293 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
294 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
303 Timer = 0x48, /* A general-purpose counter. */
304 RxMissed = 0x4C, /* 24 bits valid, write clears. */
311 Config4 = 0x5A, /* absent on RTL-8139A */
315 BasicModeCtrl = 0x62,
316 BasicModeStatus = 0x64,
319 NWayExpansion = 0x6A,
320 /* Undocumented registers, but required for proper operation. */
321 FIFOTMS = 0x70, /* FIFO Control and test. */
322 CSCR = 0x74, /* Chip Status and Configuration Register. */
324 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
325 PARA7c = 0x7c, /* Magic transceiver parameter register. */
326 Config5 = 0xD8, /* absent on RTL-8139A */
330 MultiIntrClear = 0xF000,
332 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
342 /* Interrupt register bits, using my own meaningful names. */
343 enum IntrStatusBits {
354 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
361 TxOutOfWindow = 0x20000000,
362 TxAborted = 0x40000000,
363 TxCarrierLost = 0x80000000,
366 RxMulticast = 0x8000,
368 RxBroadcast = 0x2000,
369 RxBadSymbol = 0x0020,
377 /* Bits in RxConfig. */
381 AcceptBroadcast = 0x08,
382 AcceptMulticast = 0x04,
384 AcceptAllPhys = 0x01,
387 /* Bits in TxConfig. */
388 enum tx_config_bits {
389 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
391 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
392 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
393 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
394 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
396 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
397 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
398 TxClearAbt = (1 << 0), /* Clear abort (WO) */
399 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
400 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
402 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
405 /* Bits in Config1 */
407 Cfg1_PM_Enable = 0x01,
408 Cfg1_VPD_Enable = 0x02,
411 LWAKE = 0x10, /* not on 8139, 8139A */
412 Cfg1_Driver_Load = 0x20,
415 SLEEP = (1 << 1), /* only on 8139, 8139A */
416 PWRDN = (1 << 0), /* only on 8139, 8139A */
419 /* Bits in Config3 */
421 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
422 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
423 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
424 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
425 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
426 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
427 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
428 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
431 /* Bits in Config4 */
433 LWPTN = (1 << 2), /* not on 8139, 8139A */
436 /* Bits in Config5 */
438 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
439 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
440 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
441 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
442 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
443 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
444 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
448 /* rx fifo threshold */
450 RxCfgFIFONone = (7 << RxCfgFIFOShift),
454 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
456 /* rx ring buffer length */
458 RxCfgRcv16K = (1 << 11),
459 RxCfgRcv32K = (1 << 12),
460 RxCfgRcv64K = (1 << 11) | (1 << 12),
462 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
466 /* Twister tuning parameters from RealTek.
467 Completely undocumented, but required to tune bad links on some boards. */
469 CSCR_LinkOKBit = 0x0400,
470 CSCR_LinkChangeBit = 0x0800,
471 CSCR_LinkStatusBits = 0x0f000,
472 CSCR_LinkDownOffCmd = 0x003c0,
473 CSCR_LinkDownCmd = 0x0f3c0,
478 Cfg9346_Unlock = 0xC0,
495 HasHltClk = (1 << 0),
499 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
500 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
501 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
503 /* directly indexed by chip_t, above */
504 static const struct {
506 u32 version; /* from RTL8139C/RTL8139D docs */
508 } rtl_chip_info[] = {
510 HW_REVID(1, 0, 0, 0, 0, 0, 0),
515 HW_REVID(1, 1, 0, 0, 0, 0, 0),
520 HW_REVID(1, 1, 1, 0, 0, 0, 0),
521 HasHltClk, /* XXX undocumented? */
525 HW_REVID(1, 1, 1, 0, 0, 1, 0),
526 HasHltClk, /* XXX undocumented? */
530 HW_REVID(1, 1, 1, 1, 0, 0, 0),
535 HW_REVID(1, 1, 1, 1, 1, 0, 0),
540 HW_REVID(1, 1, 1, 0, 1, 0, 0),
545 HW_REVID(1, 1, 1, 1, 0, 1, 0),
550 HW_REVID(1, 1, 1, 0, 1, 0, 1),
551 HasHltClk /* XXX undocumented? */
556 HW_REVID(1, 1, 1, 0, 1, 1, 1),
561 struct rtl_extra_stats {
562 unsigned long early_rx;
563 unsigned long tx_buf_mapped;
564 unsigned long tx_timeouts;
565 unsigned long rx_lost_in_ring;
568 struct rtl8139_stats {
571 struct u64_stats_sync syncp;
574 struct rtl8139_private {
575 void __iomem *mmio_addr;
577 struct pci_dev *pci_dev;
579 struct napi_struct napi;
580 struct net_device *dev;
582 unsigned char *rx_ring;
583 unsigned int cur_rx; /* RX buf index of next pkt */
584 struct rtl8139_stats rx_stats;
585 dma_addr_t rx_ring_dma;
587 unsigned int tx_flag;
588 unsigned long cur_tx;
589 unsigned long dirty_tx;
590 struct rtl8139_stats tx_stats;
591 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
592 unsigned char *tx_bufs; /* Tx bounce buffer region. */
593 dma_addr_t tx_bufs_dma;
595 signed char phys[4]; /* MII device addresses. */
597 /* Twister tune state. */
598 char twistie, twist_row, twist_col;
600 unsigned int watchdog_fired : 1;
601 unsigned int default_port : 4; /* Last dev->if_port value. */
602 unsigned int have_thread : 1;
609 struct rtl_extra_stats xstats;
611 struct delayed_work thread;
613 struct mii_if_info mii;
614 unsigned int regs_len;
615 unsigned long fifo_copy_timeout;
618 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
619 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
620 MODULE_LICENSE("GPL");
621 MODULE_VERSION(DRV_VERSION);
623 module_param(use_io, bool, 0);
624 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
625 module_param(multicast_filter_limit, int, 0);
626 module_param_array(media, int, NULL, 0);
627 module_param_array(full_duplex, int, NULL, 0);
628 module_param(debug, int, 0);
629 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
630 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
631 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
632 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
634 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
635 static int rtl8139_open (struct net_device *dev);
636 static int mdio_read (struct net_device *dev, int phy_id, int location);
637 static void mdio_write (struct net_device *dev, int phy_id, int location,
639 static void rtl8139_start_thread(struct rtl8139_private *tp);
640 static void rtl8139_tx_timeout (struct net_device *dev);
641 static void rtl8139_init_ring (struct net_device *dev);
642 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
643 struct net_device *dev);
644 #ifdef CONFIG_NET_POLL_CONTROLLER
645 static void rtl8139_poll_controller(struct net_device *dev);
647 static int rtl8139_set_mac_address(struct net_device *dev, void *p);
648 static int rtl8139_poll(struct napi_struct *napi, int budget);
649 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
650 static int rtl8139_close (struct net_device *dev);
651 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
652 static struct rtnl_link_stats64 *rtl8139_get_stats64(struct net_device *dev,
653 struct rtnl_link_stats64
655 static void rtl8139_set_rx_mode (struct net_device *dev);
656 static void __set_rx_mode (struct net_device *dev);
657 static void rtl8139_hw_start (struct net_device *dev);
658 static void rtl8139_thread (struct work_struct *work);
659 static void rtl8139_tx_timeout_task(struct work_struct *work);
660 static const struct ethtool_ops rtl8139_ethtool_ops;
662 /* write MMIO register, with flush */
663 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
664 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
665 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
666 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
668 /* write MMIO register */
669 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
670 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
671 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
673 /* read MMIO register */
674 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
675 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
676 #define RTL_R32(reg) ioread32 (ioaddr + (reg))
679 static const u16 rtl8139_intr_mask =
680 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
681 TxErr | TxOK | RxErr | RxOK;
683 static const u16 rtl8139_norx_intr_mask =
684 PCIErr | PCSTimeout | RxUnderrun |
685 TxErr | TxOK | RxErr ;
688 static const unsigned int rtl8139_rx_config =
689 RxCfgRcv8K | RxNoWrap |
690 (RX_FIFO_THRESH << RxCfgFIFOShift) |
691 (RX_DMA_BURST << RxCfgDMAShift);
692 #elif RX_BUF_IDX == 1
693 static const unsigned int rtl8139_rx_config =
694 RxCfgRcv16K | RxNoWrap |
695 (RX_FIFO_THRESH << RxCfgFIFOShift) |
696 (RX_DMA_BURST << RxCfgDMAShift);
697 #elif RX_BUF_IDX == 2
698 static const unsigned int rtl8139_rx_config =
699 RxCfgRcv32K | RxNoWrap |
700 (RX_FIFO_THRESH << RxCfgFIFOShift) |
701 (RX_DMA_BURST << RxCfgDMAShift);
702 #elif RX_BUF_IDX == 3
703 static const unsigned int rtl8139_rx_config =
705 (RX_FIFO_THRESH << RxCfgFIFOShift) |
706 (RX_DMA_BURST << RxCfgDMAShift);
708 #error "Invalid configuration for 8139_RXBUF_IDX"
711 static const unsigned int rtl8139_tx_config =
712 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
714 static void __rtl8139_cleanup_dev (struct net_device *dev)
716 struct rtl8139_private *tp = netdev_priv(dev);
717 struct pci_dev *pdev;
719 assert (dev != NULL);
720 assert (tp->pci_dev != NULL);
724 pci_iounmap (pdev, tp->mmio_addr);
726 /* it's ok to call this even if we have no regions to free */
727 pci_release_regions (pdev);
730 pci_set_drvdata (pdev, NULL);
734 static void rtl8139_chip_reset (void __iomem *ioaddr)
738 /* Soft reset the chip. */
739 RTL_W8 (ChipCmd, CmdReset);
741 /* Check that the chip has finished the reset. */
742 for (i = 1000; i > 0; i--) {
744 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
751 static struct net_device *rtl8139_init_board(struct pci_dev *pdev)
753 struct device *d = &pdev->dev;
754 void __iomem *ioaddr;
755 struct net_device *dev;
756 struct rtl8139_private *tp;
758 int rc, disable_dev_on_err = 0;
760 unsigned long io_len;
762 static const struct {
766 { IORESOURCE_IO, "PIO" },
767 { IORESOURCE_MEM, "MMIO" }
770 assert (pdev != NULL);
772 /* dev and priv zeroed in alloc_etherdev */
773 dev = alloc_etherdev (sizeof (*tp));
775 return ERR_PTR(-ENOMEM);
777 SET_NETDEV_DEV(dev, &pdev->dev);
779 tp = netdev_priv(dev);
782 /* enable device (incl. PCI PM wakeup and hotplug setup) */
783 rc = pci_enable_device (pdev);
787 rc = pci_request_regions (pdev, DRV_NAME);
790 disable_dev_on_err = 1;
792 pci_set_master (pdev);
794 u64_stats_init(&tp->rx_stats.syncp);
795 u64_stats_init(&tp->tx_stats.syncp);
798 /* PIO bar register comes first. */
801 io_len = pci_resource_len(pdev, bar);
803 dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len);
805 if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) {
806 dev_err(d, "region #%d not a %s resource, aborting\n", bar,
811 if (io_len < RTL_MIN_IO_SIZE) {
812 dev_err(d, "Invalid PCI %s region size(s), aborting\n",
818 ioaddr = pci_iomap(pdev, bar, 0);
820 dev_err(d, "cannot map %s\n", res[bar].type);
828 tp->regs_len = io_len;
829 tp->mmio_addr = ioaddr;
831 /* Bring old chips out of low-power mode. */
832 RTL_W8 (HltClk, 'R');
834 /* check for missing/broken hardware */
835 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
836 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
841 /* identify chip attached to board */
842 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
843 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
844 if (version == rtl_chip_info[i].version) {
849 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
851 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");
852 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig));
856 pr_debug("chipset id (%d) == index %d, '%s'\n",
857 version, i, rtl_chip_info[i].name);
859 if (tp->chipset >= CH_8139B) {
860 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
861 pr_debug("PCI PM wakeup\n");
862 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
865 new_tmp8 |= Cfg1_PM_Enable;
866 if (new_tmp8 != tmp8) {
867 RTL_W8 (Cfg9346, Cfg9346_Unlock);
868 RTL_W8 (Config1, tmp8);
869 RTL_W8 (Cfg9346, Cfg9346_Lock);
871 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
872 tmp8 = RTL_R8 (Config4);
874 RTL_W8 (Cfg9346, Cfg9346_Unlock);
875 RTL_W8 (Config4, tmp8 & ~LWPTN);
876 RTL_W8 (Cfg9346, Cfg9346_Lock);
880 pr_debug("Old chip wakeup\n");
881 tmp8 = RTL_R8 (Config1);
882 tmp8 &= ~(SLEEP | PWRDN);
883 RTL_W8 (Config1, tmp8);
886 rtl8139_chip_reset (ioaddr);
891 __rtl8139_cleanup_dev (dev);
892 if (disable_dev_on_err)
893 pci_disable_device (pdev);
897 static int rtl8139_set_features(struct net_device *dev, netdev_features_t features)
899 struct rtl8139_private *tp = netdev_priv(dev);
901 netdev_features_t changed = features ^ dev->features;
902 void __iomem *ioaddr = tp->mmio_addr;
904 if (!(changed & (NETIF_F_RXALL)))
907 spin_lock_irqsave(&tp->lock, flags);
909 if (changed & NETIF_F_RXALL) {
910 int rx_mode = tp->rx_config;
911 if (features & NETIF_F_RXALL)
912 rx_mode |= (AcceptErr | AcceptRunt);
914 rx_mode &= ~(AcceptErr | AcceptRunt);
915 tp->rx_config = rtl8139_rx_config | rx_mode;
916 RTL_W32_F(RxConfig, tp->rx_config);
919 spin_unlock_irqrestore(&tp->lock, flags);
924 static const struct net_device_ops rtl8139_netdev_ops = {
925 .ndo_open = rtl8139_open,
926 .ndo_stop = rtl8139_close,
927 .ndo_get_stats64 = rtl8139_get_stats64,
928 .ndo_change_mtu = eth_change_mtu,
929 .ndo_validate_addr = eth_validate_addr,
930 .ndo_set_mac_address = rtl8139_set_mac_address,
931 .ndo_start_xmit = rtl8139_start_xmit,
932 .ndo_set_rx_mode = rtl8139_set_rx_mode,
933 .ndo_do_ioctl = netdev_ioctl,
934 .ndo_tx_timeout = rtl8139_tx_timeout,
935 #ifdef CONFIG_NET_POLL_CONTROLLER
936 .ndo_poll_controller = rtl8139_poll_controller,
938 .ndo_set_features = rtl8139_set_features,
941 static int rtl8139_init_one(struct pci_dev *pdev,
942 const struct pci_device_id *ent)
944 struct net_device *dev = NULL;
945 struct rtl8139_private *tp;
946 int i, addr_len, option;
947 void __iomem *ioaddr;
948 static int board_idx = -1;
950 assert (pdev != NULL);
951 assert (ent != NULL);
955 /* when we're built into the kernel, the driver version message
956 * is only printed if at least one 8139 board has been found
960 static int printed_version;
961 if (!printed_version++)
962 pr_info(RTL8139_DRIVER_NAME "\n");
966 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
967 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
969 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
970 pdev->vendor, pdev->device, pdev->revision);
974 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
975 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
976 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
977 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
978 pr_info("OQO Model 2 detected. Forcing PIO\n");
982 dev = rtl8139_init_board (pdev);
986 assert (dev != NULL);
987 tp = netdev_priv(dev);
990 ioaddr = tp->mmio_addr;
991 assert (ioaddr != NULL);
993 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
994 for (i = 0; i < 3; i++)
995 ((__le16 *) (dev->dev_addr))[i] =
996 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
998 /* The Rtl8139-specific entries in the device structure. */
999 dev->netdev_ops = &rtl8139_netdev_ops;
1000 dev->ethtool_ops = &rtl8139_ethtool_ops;
1001 dev->watchdog_timeo = TX_TIMEOUT;
1002 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
1004 /* note: the hardware is not capable of sg/csum/highdma, however
1005 * through the use of skb_copy_and_csum_dev we enable these
1008 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1009 dev->vlan_features = dev->features;
1011 dev->hw_features |= NETIF_F_RXALL;
1012 dev->hw_features |= NETIF_F_RXFCS;
1014 /* tp zeroed and aligned in alloc_etherdev */
1015 tp = netdev_priv(dev);
1017 /* note: tp->chipset set in rtl8139_init_board */
1018 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1019 tp->mmio_addr = ioaddr;
1021 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1022 spin_lock_init (&tp->lock);
1023 spin_lock_init (&tp->rx_lock);
1024 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1026 tp->mii.mdio_read = mdio_read;
1027 tp->mii.mdio_write = mdio_write;
1028 tp->mii.phy_id_mask = 0x3f;
1029 tp->mii.reg_num_mask = 0x1f;
1031 /* dev is fully set up and ready to use now */
1032 pr_debug("about to register device named %s (%p)...\n",
1034 i = register_netdev (dev);
1035 if (i) goto err_out;
1037 pci_set_drvdata (pdev, dev);
1039 netdev_info(dev, "%s at 0x%p, %pM, IRQ %d\n",
1040 board_info[ent->driver_data].name,
1041 ioaddr, dev->dev_addr, pdev->irq);
1043 netdev_dbg(dev, "Identified 8139 chip type '%s'\n",
1044 rtl_chip_info[tp->chipset].name);
1046 /* Find the connected MII xcvrs.
1047 Doing this in open() would allow detecting external xcvrs later, but
1048 takes too much time. */
1049 #ifdef CONFIG_8139TOO_8129
1050 if (tp->drv_flags & HAS_MII_XCVR) {
1051 int phy, phy_idx = 0;
1052 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1053 int mii_status = mdio_read(dev, phy, 1);
1054 if (mii_status != 0xffff && mii_status != 0x0000) {
1055 u16 advertising = mdio_read(dev, phy, 4);
1056 tp->phys[phy_idx++] = phy;
1057 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n",
1058 phy, mii_status, advertising);
1062 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n");
1068 tp->mii.phy_id = tp->phys[0];
1070 /* The lower four bits are the media type. */
1071 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1073 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1074 tp->default_port = option & 0xFF;
1075 if (tp->default_port)
1076 tp->mii.force_media = 1;
1078 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1079 tp->mii.full_duplex = full_duplex[board_idx];
1080 if (tp->mii.full_duplex) {
1081 netdev_info(dev, "Media type forced to Full Duplex\n");
1082 /* Changing the MII-advertised media because might prevent
1084 tp->mii.force_media = 1;
1086 if (tp->default_port) {
1087 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n",
1088 (option & 0x20 ? 100 : 10),
1089 (option & 0x10 ? "full" : "half"));
1090 mdio_write(dev, tp->phys[0], 0,
1091 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1092 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1095 /* Put the chip into low-power mode. */
1096 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1097 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1102 __rtl8139_cleanup_dev (dev);
1103 pci_disable_device (pdev);
1108 static void rtl8139_remove_one(struct pci_dev *pdev)
1110 struct net_device *dev = pci_get_drvdata (pdev);
1111 struct rtl8139_private *tp = netdev_priv(dev);
1113 assert (dev != NULL);
1115 cancel_delayed_work_sync(&tp->thread);
1117 unregister_netdev (dev);
1119 __rtl8139_cleanup_dev (dev);
1120 pci_disable_device (pdev);
1124 /* Serial EEPROM section. */
1126 /* EEPROM_Ctrl bits. */
1127 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1128 #define EE_CS 0x08 /* EEPROM chip select. */
1129 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1130 #define EE_WRITE_0 0x00
1131 #define EE_WRITE_1 0x02
1132 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1133 #define EE_ENB (0x80 | EE_CS)
1135 /* Delay between EEPROM clock transitions.
1136 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1139 #define eeprom_delay() (void)RTL_R8(Cfg9346)
1141 /* The EEPROM commands include the alway-set leading bit. */
1142 #define EE_WRITE_CMD (5)
1143 #define EE_READ_CMD (6)
1144 #define EE_ERASE_CMD (7)
1146 static int read_eeprom(void __iomem *ioaddr, int location, int addr_len)
1149 unsigned retval = 0;
1150 int read_cmd = location | (EE_READ_CMD << addr_len);
1152 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1153 RTL_W8 (Cfg9346, EE_ENB);
1156 /* Shift the read command bits out. */
1157 for (i = 4 + addr_len; i >= 0; i--) {
1158 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1159 RTL_W8 (Cfg9346, EE_ENB | dataval);
1161 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1164 RTL_W8 (Cfg9346, EE_ENB);
1167 for (i = 16; i > 0; i--) {
1168 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1171 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1173 RTL_W8 (Cfg9346, EE_ENB);
1177 /* Terminate the EEPROM access. */
1184 /* MII serial management: mostly bogus for now. */
1185 /* Read and write the MII management registers using software-generated
1186 serial MDIO protocol.
1187 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1188 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1189 "overclocking" issues. */
1190 #define MDIO_DIR 0x80
1191 #define MDIO_DATA_OUT 0x04
1192 #define MDIO_DATA_IN 0x02
1193 #define MDIO_CLK 0x01
1194 #define MDIO_WRITE0 (MDIO_DIR)
1195 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1197 #define mdio_delay() RTL_R8(Config4)
1200 static const char mii_2_8139_map[8] = {
1212 #ifdef CONFIG_8139TOO_8129
1213 /* Syncronize the MII management interface by shifting 32 one bits out. */
1214 static void mdio_sync (void __iomem *ioaddr)
1218 for (i = 32; i >= 0; i--) {
1219 RTL_W8 (Config4, MDIO_WRITE1);
1221 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1227 static int mdio_read (struct net_device *dev, int phy_id, int location)
1229 struct rtl8139_private *tp = netdev_priv(dev);
1231 #ifdef CONFIG_8139TOO_8129
1232 void __iomem *ioaddr = tp->mmio_addr;
1233 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1237 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1238 void __iomem *ioaddr = tp->mmio_addr;
1239 return location < 8 && mii_2_8139_map[location] ?
1240 RTL_R16 (mii_2_8139_map[location]) : 0;
1243 #ifdef CONFIG_8139TOO_8129
1245 /* Shift the read command bits out. */
1246 for (i = 15; i >= 0; i--) {
1247 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1249 RTL_W8 (Config4, MDIO_DIR | dataval);
1251 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1255 /* Read the two transition, 16 data, and wire-idle bits. */
1256 for (i = 19; i > 0; i--) {
1257 RTL_W8 (Config4, 0);
1259 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1260 RTL_W8 (Config4, MDIO_CLK);
1265 return (retval >> 1) & 0xffff;
1269 static void mdio_write (struct net_device *dev, int phy_id, int location,
1272 struct rtl8139_private *tp = netdev_priv(dev);
1273 #ifdef CONFIG_8139TOO_8129
1274 void __iomem *ioaddr = tp->mmio_addr;
1275 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1279 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1280 void __iomem *ioaddr = tp->mmio_addr;
1281 if (location == 0) {
1282 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1283 RTL_W16 (BasicModeCtrl, value);
1284 RTL_W8 (Cfg9346, Cfg9346_Lock);
1285 } else if (location < 8 && mii_2_8139_map[location])
1286 RTL_W16 (mii_2_8139_map[location], value);
1290 #ifdef CONFIG_8139TOO_8129
1293 /* Shift the command bits out. */
1294 for (i = 31; i >= 0; i--) {
1296 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1297 RTL_W8 (Config4, dataval);
1299 RTL_W8 (Config4, dataval | MDIO_CLK);
1302 /* Clear out extra bits. */
1303 for (i = 2; i > 0; i--) {
1304 RTL_W8 (Config4, 0);
1306 RTL_W8 (Config4, MDIO_CLK);
1313 static int rtl8139_open (struct net_device *dev)
1315 struct rtl8139_private *tp = netdev_priv(dev);
1316 void __iomem *ioaddr = tp->mmio_addr;
1317 const int irq = tp->pci_dev->irq;
1320 retval = request_irq(irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1324 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1325 &tp->tx_bufs_dma, GFP_KERNEL);
1326 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1327 &tp->rx_ring_dma, GFP_KERNEL);
1328 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1332 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1333 tp->tx_bufs, tp->tx_bufs_dma);
1335 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1336 tp->rx_ring, tp->rx_ring_dma);
1342 napi_enable(&tp->napi);
1344 tp->mii.full_duplex = tp->mii.force_media;
1345 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1347 rtl8139_init_ring (dev);
1348 rtl8139_hw_start (dev);
1349 netif_start_queue (dev);
1351 netif_dbg(tp, ifup, dev,
1352 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n",
1354 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1355 irq, RTL_R8 (MediaStatus),
1356 tp->mii.full_duplex ? "full" : "half");
1358 rtl8139_start_thread(tp);
1364 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1366 struct rtl8139_private *tp = netdev_priv(dev);
1368 if (tp->phys[0] >= 0) {
1369 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1373 /* Start the hardware at open or resume. */
1374 static void rtl8139_hw_start (struct net_device *dev)
1376 struct rtl8139_private *tp = netdev_priv(dev);
1377 void __iomem *ioaddr = tp->mmio_addr;
1381 /* Bring old chips out of low-power mode. */
1382 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1383 RTL_W8 (HltClk, 'R');
1385 rtl8139_chip_reset (ioaddr);
1387 /* unlock Config[01234] and BMCR register writes */
1388 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1389 /* Restore our idea of the MAC address. */
1390 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1391 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1395 /* init Rx ring buffer DMA address */
1396 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1398 /* Must enable Tx/Rx before setting transfer thresholds! */
1399 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1401 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1402 RTL_W32 (RxConfig, tp->rx_config);
1403 RTL_W32 (TxConfig, rtl8139_tx_config);
1405 rtl_check_media (dev, 1);
1407 if (tp->chipset >= CH_8139B) {
1408 /* Disable magic packet scanning, which is enabled
1409 * when PM is enabled in Config1. It can be reenabled
1410 * via ETHTOOL_SWOL if desired. */
1411 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1414 netdev_dbg(dev, "init buffer addresses\n");
1416 /* Lock Config[01234] and BMCR register writes */
1417 RTL_W8 (Cfg9346, Cfg9346_Lock);
1419 /* init Tx buffer DMA addresses */
1420 for (i = 0; i < NUM_TX_DESC; i++)
1421 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1423 RTL_W32 (RxMissed, 0);
1425 rtl8139_set_rx_mode (dev);
1427 /* no early-rx interrupts */
1428 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1430 /* make sure RxTx has started */
1431 tmp = RTL_R8 (ChipCmd);
1432 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1433 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1435 /* Enable all known interrupts by setting the interrupt mask. */
1436 RTL_W16 (IntrMask, rtl8139_intr_mask);
1440 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1441 static void rtl8139_init_ring (struct net_device *dev)
1443 struct rtl8139_private *tp = netdev_priv(dev);
1450 for (i = 0; i < NUM_TX_DESC; i++)
1451 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1455 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1456 static int next_tick = 3 * HZ;
1458 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1459 static inline void rtl8139_tune_twister (struct net_device *dev,
1460 struct rtl8139_private *tp) {}
1462 enum TwisterParamVals {
1463 PARA78_default = 0x78fa8388,
1464 PARA7c_default = 0xcb38de43, /* param[0][3] */
1465 PARA7c_xxx = 0xcb38de43,
1468 static const unsigned long param[4][4] = {
1469 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1470 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1471 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1472 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1475 static void rtl8139_tune_twister (struct net_device *dev,
1476 struct rtl8139_private *tp)
1479 void __iomem *ioaddr = tp->mmio_addr;
1481 /* This is a complicated state machine to configure the "twister" for
1482 impedance/echos based on the cable length.
1483 All of this is magic and undocumented.
1485 switch (tp->twistie) {
1487 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1488 /* We have link beat, let us tune the twister. */
1489 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1490 tp->twistie = 2; /* Change to state 2. */
1491 next_tick = HZ / 10;
1493 /* Just put in some reasonable defaults for when beat returns. */
1494 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1495 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1496 RTL_W32 (PARA78, PARA78_default);
1497 RTL_W32 (PARA7c, PARA7c_default);
1498 tp->twistie = 0; /* Bail from future actions. */
1502 /* Read how long it took to hear the echo. */
1503 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1504 if (linkcase == 0x7000)
1506 else if (linkcase == 0x3000)
1508 else if (linkcase == 0x1000)
1513 tp->twistie = 3; /* Change to state 2. */
1514 next_tick = HZ / 10;
1517 /* Put out four tuning parameters, one per 100msec. */
1518 if (tp->twist_col == 0)
1519 RTL_W16 (FIFOTMS, 0);
1520 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1521 [(int) tp->twist_col]);
1522 next_tick = HZ / 10;
1523 if (++tp->twist_col >= 4) {
1524 /* For short cables we are done.
1525 For long cables (row == 3) check for mistune. */
1527 (tp->twist_row == 3) ? 4 : 0;
1531 /* Special case for long cables: check for mistune. */
1532 if ((RTL_R16 (CSCR) &
1533 CSCR_LinkStatusBits) == 0x7000) {
1537 RTL_W32 (PARA7c, 0xfb38de03);
1539 next_tick = HZ / 10;
1543 /* Retune for shorter cable (column 2). */
1544 RTL_W32 (FIFOTMS, 0x20);
1545 RTL_W32 (PARA78, PARA78_default);
1546 RTL_W32 (PARA7c, PARA7c_default);
1547 RTL_W32 (FIFOTMS, 0x00);
1551 next_tick = HZ / 10;
1559 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1561 static inline void rtl8139_thread_iter (struct net_device *dev,
1562 struct rtl8139_private *tp,
1563 void __iomem *ioaddr)
1567 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1569 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1570 int duplex = ((mii_lpa & LPA_100FULL) ||
1571 (mii_lpa & 0x01C0) == 0x0040);
1572 if (tp->mii.full_duplex != duplex) {
1573 tp->mii.full_duplex = duplex;
1576 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n",
1577 tp->mii.full_duplex ? "full" : "half",
1578 tp->phys[0], mii_lpa);
1580 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n");
1583 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1584 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1585 RTL_W8 (Cfg9346, Cfg9346_Lock);
1590 next_tick = HZ * 60;
1592 rtl8139_tune_twister (dev, tp);
1594 netdev_dbg(dev, "Media selection tick, Link partner %04x\n",
1596 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n",
1597 RTL_R16(IntrMask), RTL_R16(IntrStatus));
1598 netdev_dbg(dev, "Chip config %02x %02x\n",
1599 RTL_R8(Config0), RTL_R8(Config1));
1602 static void rtl8139_thread (struct work_struct *work)
1604 struct rtl8139_private *tp =
1605 container_of(work, struct rtl8139_private, thread.work);
1606 struct net_device *dev = tp->mii.dev;
1607 unsigned long thr_delay = next_tick;
1611 if (!netif_running(dev))
1614 if (tp->watchdog_fired) {
1615 tp->watchdog_fired = 0;
1616 rtl8139_tx_timeout_task(work);
1618 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1620 if (tp->have_thread)
1621 schedule_delayed_work(&tp->thread, thr_delay);
1626 static void rtl8139_start_thread(struct rtl8139_private *tp)
1629 if (tp->chipset == CH_8139_K)
1631 else if (tp->drv_flags & HAS_LNK_CHNG)
1634 tp->have_thread = 1;
1635 tp->watchdog_fired = 0;
1637 schedule_delayed_work(&tp->thread, next_tick);
1640 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1645 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1648 static void rtl8139_tx_timeout_task (struct work_struct *work)
1650 struct rtl8139_private *tp =
1651 container_of(work, struct rtl8139_private, thread.work);
1652 struct net_device *dev = tp->mii.dev;
1653 void __iomem *ioaddr = tp->mmio_addr;
1657 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n",
1658 RTL_R8(ChipCmd), RTL_R16(IntrStatus),
1659 RTL_R16(IntrMask), RTL_R8(MediaStatus));
1660 /* Emit info to figure out what went wrong. */
1661 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n",
1662 tp->cur_tx, tp->dirty_tx);
1663 for (i = 0; i < NUM_TX_DESC; i++)
1664 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n",
1665 i, RTL_R32(TxStatus0 + (i * 4)),
1666 i == tp->dirty_tx % NUM_TX_DESC ?
1667 " (queue head)" : "");
1669 tp->xstats.tx_timeouts++;
1671 /* disable Tx ASAP, if not already */
1672 tmp8 = RTL_R8 (ChipCmd);
1673 if (tmp8 & CmdTxEnb)
1674 RTL_W8 (ChipCmd, CmdRxEnb);
1676 spin_lock_bh(&tp->rx_lock);
1677 /* Disable interrupts by clearing the interrupt mask. */
1678 RTL_W16 (IntrMask, 0x0000);
1680 /* Stop a shared interrupt from scavenging while we are. */
1681 spin_lock_irq(&tp->lock);
1682 rtl8139_tx_clear (tp);
1683 spin_unlock_irq(&tp->lock);
1685 /* ...and finally, reset everything */
1686 if (netif_running(dev)) {
1687 rtl8139_hw_start (dev);
1688 netif_wake_queue (dev);
1690 spin_unlock_bh(&tp->rx_lock);
1693 static void rtl8139_tx_timeout (struct net_device *dev)
1695 struct rtl8139_private *tp = netdev_priv(dev);
1697 tp->watchdog_fired = 1;
1698 if (!tp->have_thread) {
1699 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1700 schedule_delayed_work(&tp->thread, next_tick);
1704 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
1705 struct net_device *dev)
1707 struct rtl8139_private *tp = netdev_priv(dev);
1708 void __iomem *ioaddr = tp->mmio_addr;
1710 unsigned int len = skb->len;
1711 unsigned long flags;
1713 /* Calculate the next Tx descriptor entry. */
1714 entry = tp->cur_tx % NUM_TX_DESC;
1716 /* Note: the chip doesn't have auto-pad! */
1717 if (likely(len < TX_BUF_SIZE)) {
1719 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1720 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1724 dev->stats.tx_dropped++;
1725 return NETDEV_TX_OK;
1728 spin_lock_irqsave(&tp->lock, flags);
1730 * Writing to TxStatus triggers a DMA transfer of the data
1731 * copied to tp->tx_buf[entry] above. Use a memory barrier
1732 * to make sure that the device sees the updated data.
1735 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1736 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1740 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1741 netif_stop_queue (dev);
1742 spin_unlock_irqrestore(&tp->lock, flags);
1744 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n",
1747 return NETDEV_TX_OK;
1751 static void rtl8139_tx_interrupt (struct net_device *dev,
1752 struct rtl8139_private *tp,
1753 void __iomem *ioaddr)
1755 unsigned long dirty_tx, tx_left;
1757 assert (dev != NULL);
1758 assert (ioaddr != NULL);
1760 dirty_tx = tp->dirty_tx;
1761 tx_left = tp->cur_tx - dirty_tx;
1762 while (tx_left > 0) {
1763 int entry = dirty_tx % NUM_TX_DESC;
1766 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1768 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1769 break; /* It still hasn't been Txed */
1771 /* Note: TxCarrierLost is always asserted at 100mbps. */
1772 if (txstatus & (TxOutOfWindow | TxAborted)) {
1773 /* There was an major error, log it. */
1774 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n",
1776 dev->stats.tx_errors++;
1777 if (txstatus & TxAborted) {
1778 dev->stats.tx_aborted_errors++;
1779 RTL_W32 (TxConfig, TxClearAbt);
1780 RTL_W16 (IntrStatus, TxErr);
1783 if (txstatus & TxCarrierLost)
1784 dev->stats.tx_carrier_errors++;
1785 if (txstatus & TxOutOfWindow)
1786 dev->stats.tx_window_errors++;
1788 if (txstatus & TxUnderrun) {
1789 /* Add 64 to the Tx FIFO threshold. */
1790 if (tp->tx_flag < 0x00300000)
1791 tp->tx_flag += 0x00020000;
1792 dev->stats.tx_fifo_errors++;
1794 dev->stats.collisions += (txstatus >> 24) & 15;
1795 u64_stats_update_begin(&tp->tx_stats.syncp);
1796 tp->tx_stats.packets++;
1797 tp->tx_stats.bytes += txstatus & 0x7ff;
1798 u64_stats_update_end(&tp->tx_stats.syncp);
1805 #ifndef RTL8139_NDEBUG
1806 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1807 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n",
1808 dirty_tx, tp->cur_tx);
1809 dirty_tx += NUM_TX_DESC;
1811 #endif /* RTL8139_NDEBUG */
1813 /* only wake the queue if we did work, and the queue is stopped */
1814 if (tp->dirty_tx != dirty_tx) {
1815 tp->dirty_tx = dirty_tx;
1817 netif_wake_queue (dev);
1822 /* TODO: clean this up! Rx reset need not be this intensive */
1823 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1824 struct rtl8139_private *tp, void __iomem *ioaddr)
1827 #ifdef CONFIG_8139_OLD_RX_RESET
1831 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n",
1833 dev->stats.rx_errors++;
1834 if (!(rx_status & RxStatusOK)) {
1835 if (rx_status & RxTooLong) {
1836 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n",
1838 /* A.C.: The chip hangs here. */
1840 if (rx_status & (RxBadSymbol | RxBadAlign))
1841 dev->stats.rx_frame_errors++;
1842 if (rx_status & (RxRunt | RxTooLong))
1843 dev->stats.rx_length_errors++;
1844 if (rx_status & RxCRCErr)
1845 dev->stats.rx_crc_errors++;
1847 tp->xstats.rx_lost_in_ring++;
1850 #ifndef CONFIG_8139_OLD_RX_RESET
1851 tmp8 = RTL_R8 (ChipCmd);
1852 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1853 RTL_W8 (ChipCmd, tmp8);
1854 RTL_W32 (RxConfig, tp->rx_config);
1857 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1859 /* disable receive */
1860 RTL_W8_F (ChipCmd, CmdTxEnb);
1862 while (--tmp_work > 0) {
1864 tmp8 = RTL_R8 (ChipCmd);
1865 if (!(tmp8 & CmdRxEnb))
1869 netdev_warn(dev, "rx stop wait too long\n");
1870 /* restart receive */
1872 while (--tmp_work > 0) {
1873 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1875 tmp8 = RTL_R8 (ChipCmd);
1876 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1880 netdev_warn(dev, "tx/rx enable wait too long\n");
1882 /* and reinitialize all rx related registers */
1883 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1884 /* Must enable Tx/Rx before setting transfer thresholds! */
1885 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1887 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1888 RTL_W32 (RxConfig, tp->rx_config);
1891 netdev_dbg(dev, "init buffer addresses\n");
1893 /* Lock Config[01234] and BMCR register writes */
1894 RTL_W8 (Cfg9346, Cfg9346_Lock);
1896 /* init Rx ring buffer DMA address */
1897 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1899 /* A.C.: Reset the multicast list. */
1900 __set_rx_mode (dev);
1905 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1906 u32 offset, unsigned int size)
1908 u32 left = RX_BUF_LEN - offset;
1911 skb_copy_to_linear_data(skb, ring + offset, left);
1912 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1914 skb_copy_to_linear_data(skb, ring + offset, size);
1918 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1920 void __iomem *ioaddr = tp->mmio_addr;
1923 status = RTL_R16 (IntrStatus) & RxAckBits;
1925 /* Clear out errors and receive interrupts */
1926 if (likely(status != 0)) {
1927 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1928 tp->dev->stats.rx_errors++;
1929 if (status & RxFIFOOver)
1930 tp->dev->stats.rx_fifo_errors++;
1932 RTL_W16_F (IntrStatus, RxAckBits);
1936 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1939 void __iomem *ioaddr = tp->mmio_addr;
1941 unsigned char *rx_ring = tp->rx_ring;
1942 unsigned int cur_rx = tp->cur_rx;
1943 unsigned int rx_size = 0;
1945 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
1946 __func__, (u16)cur_rx,
1947 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
1949 while (netif_running(dev) && received < budget &&
1950 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1951 u32 ring_offset = cur_rx % RX_BUF_LEN;
1953 unsigned int pkt_size;
1954 struct sk_buff *skb;
1958 /* read size+status of next frame from DMA ring buffer */
1959 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1960 rx_size = rx_status >> 16;
1961 if (likely(!(dev->features & NETIF_F_RXFCS)))
1962 pkt_size = rx_size - 4;
1966 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n",
1967 __func__, rx_status, rx_size, cur_rx);
1968 #if RTL8139_DEBUG > 2
1969 print_hex_dump(KERN_DEBUG, "Frame contents: ",
1970 DUMP_PREFIX_OFFSET, 16, 1,
1971 &rx_ring[ring_offset], 70, true);
1974 /* Packet copy from FIFO still in progress.
1975 * Theoretically, this should never happen
1976 * since EarlyRx is disabled.
1978 if (unlikely(rx_size == 0xfff0)) {
1979 if (!tp->fifo_copy_timeout)
1980 tp->fifo_copy_timeout = jiffies + 2;
1981 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1982 netdev_dbg(dev, "hung FIFO. Reset\n");
1986 netif_dbg(tp, intr, dev, "fifo copy in progress\n");
1987 tp->xstats.early_rx++;
1992 tp->fifo_copy_timeout = 0;
1994 /* If Rx err or invalid rx_size/rx_status received
1995 * (which happens if we get lost in the ring),
1996 * Rx process gets reset, so we abort any further
1999 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2001 (!(rx_status & RxStatusOK)))) {
2002 if ((dev->features & NETIF_F_RXALL) &&
2003 (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) &&
2005 (!(rx_status & RxStatusOK))) {
2006 /* Length is at least mostly OK, but pkt has
2007 * error. I'm hoping we can handle some of these
2008 * errors without resetting the chip. --Ben
2010 dev->stats.rx_errors++;
2011 if (rx_status & RxCRCErr) {
2012 dev->stats.rx_crc_errors++;
2015 if (rx_status & RxRunt) {
2016 dev->stats.rx_length_errors++;
2020 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2026 /* Malloc up new buffer, compatible with net-2e. */
2027 /* Omit the four octet CRC from the length. */
2029 skb = netdev_alloc_skb_ip_align(dev, pkt_size);
2032 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2034 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2036 skb_put (skb, pkt_size);
2038 skb->protocol = eth_type_trans (skb, dev);
2040 u64_stats_update_begin(&tp->rx_stats.syncp);
2041 tp->rx_stats.packets++;
2042 tp->rx_stats.bytes += pkt_size;
2043 u64_stats_update_end(&tp->rx_stats.syncp);
2045 netif_receive_skb (skb);
2047 dev->stats.rx_dropped++;
2051 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2052 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2054 rtl8139_isr_ack(tp);
2057 if (unlikely(!received || rx_size == 0xfff0))
2058 rtl8139_isr_ack(tp);
2060 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
2062 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
2064 tp->cur_rx = cur_rx;
2067 * The receive buffer should be mostly empty.
2068 * Tell NAPI to reenable the Rx irq.
2070 if (tp->fifo_copy_timeout)
2078 static void rtl8139_weird_interrupt (struct net_device *dev,
2079 struct rtl8139_private *tp,
2080 void __iomem *ioaddr,
2081 int status, int link_changed)
2083 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status);
2085 assert (dev != NULL);
2086 assert (tp != NULL);
2087 assert (ioaddr != NULL);
2089 /* Update the error count. */
2090 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2091 RTL_W32 (RxMissed, 0);
2093 if ((status & RxUnderrun) && link_changed &&
2094 (tp->drv_flags & HAS_LNK_CHNG)) {
2095 rtl_check_media(dev, 0);
2096 status &= ~RxUnderrun;
2099 if (status & (RxUnderrun | RxErr))
2100 dev->stats.rx_errors++;
2102 if (status & PCSTimeout)
2103 dev->stats.rx_length_errors++;
2104 if (status & RxUnderrun)
2105 dev->stats.rx_fifo_errors++;
2106 if (status & PCIErr) {
2108 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2109 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2111 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status);
2115 static int rtl8139_poll(struct napi_struct *napi, int budget)
2117 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2118 struct net_device *dev = tp->dev;
2119 void __iomem *ioaddr = tp->mmio_addr;
2122 spin_lock(&tp->rx_lock);
2124 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2125 work_done += rtl8139_rx(dev, tp, budget);
2127 if (work_done < budget) {
2128 unsigned long flags;
2130 * Order is important since data can get interrupted
2131 * again when we think we are done.
2133 spin_lock_irqsave(&tp->lock, flags);
2134 __napi_complete(napi);
2135 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2136 spin_unlock_irqrestore(&tp->lock, flags);
2138 spin_unlock(&tp->rx_lock);
2143 /* The interrupt handler does all of the Rx thread work and cleans up
2144 after the Tx thread. */
2145 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2147 struct net_device *dev = (struct net_device *) dev_instance;
2148 struct rtl8139_private *tp = netdev_priv(dev);
2149 void __iomem *ioaddr = tp->mmio_addr;
2150 u16 status, ackstat;
2151 int link_changed = 0; /* avoid bogus "uninit" warning */
2154 spin_lock (&tp->lock);
2155 status = RTL_R16 (IntrStatus);
2158 if (unlikely((status & rtl8139_intr_mask) == 0))
2163 /* h/w no longer present (hotplug?) or major error, bail */
2164 if (unlikely(status == 0xFFFF))
2167 /* close possible race's with dev_close */
2168 if (unlikely(!netif_running(dev))) {
2169 RTL_W16 (IntrMask, 0);
2173 /* Acknowledge all of the current interrupt sources ASAP, but
2174 an first get an additional status bit from CSCR. */
2175 if (unlikely(status & RxUnderrun))
2176 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2178 ackstat = status & ~(RxAckBits | TxErr);
2180 RTL_W16 (IntrStatus, ackstat);
2182 /* Receive packets are processed by poll routine.
2183 If not running start it now. */
2184 if (status & RxAckBits){
2185 if (napi_schedule_prep(&tp->napi)) {
2186 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2187 __napi_schedule(&tp->napi);
2191 /* Check uncommon events with one test. */
2192 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2193 rtl8139_weird_interrupt (dev, tp, ioaddr,
2194 status, link_changed);
2196 if (status & (TxOK | TxErr)) {
2197 rtl8139_tx_interrupt (dev, tp, ioaddr);
2199 RTL_W16 (IntrStatus, TxErr);
2202 spin_unlock (&tp->lock);
2204 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n",
2205 RTL_R16(IntrStatus));
2206 return IRQ_RETVAL(handled);
2209 #ifdef CONFIG_NET_POLL_CONTROLLER
2211 * Polling receive - used by netconsole and other diagnostic tools
2212 * to allow network i/o with interrupts disabled.
2214 static void rtl8139_poll_controller(struct net_device *dev)
2216 struct rtl8139_private *tp = netdev_priv(dev);
2217 const int irq = tp->pci_dev->irq;
2220 rtl8139_interrupt(irq, dev);
2225 static int rtl8139_set_mac_address(struct net_device *dev, void *p)
2227 struct rtl8139_private *tp = netdev_priv(dev);
2228 void __iomem *ioaddr = tp->mmio_addr;
2229 struct sockaddr *addr = p;
2231 if (!is_valid_ether_addr(addr->sa_data))
2232 return -EADDRNOTAVAIL;
2234 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2236 spin_lock_irq(&tp->lock);
2238 RTL_W8_F(Cfg9346, Cfg9346_Unlock);
2239 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
2240 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
2241 RTL_W8_F(Cfg9346, Cfg9346_Lock);
2243 spin_unlock_irq(&tp->lock);
2248 static int rtl8139_close (struct net_device *dev)
2250 struct rtl8139_private *tp = netdev_priv(dev);
2251 void __iomem *ioaddr = tp->mmio_addr;
2252 unsigned long flags;
2254 netif_stop_queue(dev);
2255 napi_disable(&tp->napi);
2257 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n",
2258 RTL_R16(IntrStatus));
2260 spin_lock_irqsave (&tp->lock, flags);
2262 /* Stop the chip's Tx and Rx DMA processes. */
2263 RTL_W8 (ChipCmd, 0);
2265 /* Disable interrupts by clearing the interrupt mask. */
2266 RTL_W16 (IntrMask, 0);
2268 /* Update the error counts. */
2269 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2270 RTL_W32 (RxMissed, 0);
2272 spin_unlock_irqrestore (&tp->lock, flags);
2274 free_irq(tp->pci_dev->irq, dev);
2276 rtl8139_tx_clear (tp);
2278 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2279 tp->rx_ring, tp->rx_ring_dma);
2280 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2281 tp->tx_bufs, tp->tx_bufs_dma);
2285 /* Green! Put the chip in low-power mode. */
2286 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2288 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2289 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2295 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2296 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2297 other threads or interrupts aren't messing with the 8139. */
2298 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2300 struct rtl8139_private *tp = netdev_priv(dev);
2301 void __iomem *ioaddr = tp->mmio_addr;
2303 spin_lock_irq(&tp->lock);
2304 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
2305 u8 cfg3 = RTL_R8 (Config3);
2306 u8 cfg5 = RTL_R8 (Config5);
2308 wol->supported = WAKE_PHY | WAKE_MAGIC
2309 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2312 if (cfg3 & Cfg3_LinkUp)
2313 wol->wolopts |= WAKE_PHY;
2314 if (cfg3 & Cfg3_Magic)
2315 wol->wolopts |= WAKE_MAGIC;
2316 /* (KON)FIXME: See how netdev_set_wol() handles the
2317 following constants. */
2318 if (cfg5 & Cfg5_UWF)
2319 wol->wolopts |= WAKE_UCAST;
2320 if (cfg5 & Cfg5_MWF)
2321 wol->wolopts |= WAKE_MCAST;
2322 if (cfg5 & Cfg5_BWF)
2323 wol->wolopts |= WAKE_BCAST;
2325 spin_unlock_irq(&tp->lock);
2329 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2330 that wol points to kernel memory and other threads or interrupts
2331 aren't messing with the 8139. */
2332 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2334 struct rtl8139_private *tp = netdev_priv(dev);
2335 void __iomem *ioaddr = tp->mmio_addr;
2339 support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
2340 ? (WAKE_PHY | WAKE_MAGIC
2341 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2343 if (wol->wolopts & ~support)
2346 spin_lock_irq(&tp->lock);
2347 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2348 if (wol->wolopts & WAKE_PHY)
2349 cfg3 |= Cfg3_LinkUp;
2350 if (wol->wolopts & WAKE_MAGIC)
2352 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2353 RTL_W8 (Config3, cfg3);
2354 RTL_W8 (Cfg9346, Cfg9346_Lock);
2356 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2357 /* (KON)FIXME: These are untested. We may have to set the
2358 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2360 if (wol->wolopts & WAKE_UCAST)
2362 if (wol->wolopts & WAKE_MCAST)
2364 if (wol->wolopts & WAKE_BCAST)
2366 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2367 spin_unlock_irq(&tp->lock);
2372 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2374 struct rtl8139_private *tp = netdev_priv(dev);
2375 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2376 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2377 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
2378 info->regdump_len = tp->regs_len;
2381 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2383 struct rtl8139_private *tp = netdev_priv(dev);
2384 spin_lock_irq(&tp->lock);
2385 mii_ethtool_gset(&tp->mii, cmd);
2386 spin_unlock_irq(&tp->lock);
2390 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2392 struct rtl8139_private *tp = netdev_priv(dev);
2394 spin_lock_irq(&tp->lock);
2395 rc = mii_ethtool_sset(&tp->mii, cmd);
2396 spin_unlock_irq(&tp->lock);
2400 static int rtl8139_nway_reset(struct net_device *dev)
2402 struct rtl8139_private *tp = netdev_priv(dev);
2403 return mii_nway_restart(&tp->mii);
2406 static u32 rtl8139_get_link(struct net_device *dev)
2408 struct rtl8139_private *tp = netdev_priv(dev);
2409 return mii_link_ok(&tp->mii);
2412 static u32 rtl8139_get_msglevel(struct net_device *dev)
2414 struct rtl8139_private *tp = netdev_priv(dev);
2415 return tp->msg_enable;
2418 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2420 struct rtl8139_private *tp = netdev_priv(dev);
2421 tp->msg_enable = datum;
2424 static int rtl8139_get_regs_len(struct net_device *dev)
2426 struct rtl8139_private *tp;
2427 /* TODO: we are too slack to do reg dumping for pio, for now */
2430 tp = netdev_priv(dev);
2431 return tp->regs_len;
2434 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2436 struct rtl8139_private *tp;
2438 /* TODO: we are too slack to do reg dumping for pio, for now */
2441 tp = netdev_priv(dev);
2443 regs->version = RTL_REGS_VER;
2445 spin_lock_irq(&tp->lock);
2446 memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
2447 spin_unlock_irq(&tp->lock);
2450 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2454 return RTL_NUM_STATS;
2460 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2462 struct rtl8139_private *tp = netdev_priv(dev);
2464 data[0] = tp->xstats.early_rx;
2465 data[1] = tp->xstats.tx_buf_mapped;
2466 data[2] = tp->xstats.tx_timeouts;
2467 data[3] = tp->xstats.rx_lost_in_ring;
2470 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2472 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2475 static const struct ethtool_ops rtl8139_ethtool_ops = {
2476 .get_drvinfo = rtl8139_get_drvinfo,
2477 .get_settings = rtl8139_get_settings,
2478 .set_settings = rtl8139_set_settings,
2479 .get_regs_len = rtl8139_get_regs_len,
2480 .get_regs = rtl8139_get_regs,
2481 .nway_reset = rtl8139_nway_reset,
2482 .get_link = rtl8139_get_link,
2483 .get_msglevel = rtl8139_get_msglevel,
2484 .set_msglevel = rtl8139_set_msglevel,
2485 .get_wol = rtl8139_get_wol,
2486 .set_wol = rtl8139_set_wol,
2487 .get_strings = rtl8139_get_strings,
2488 .get_sset_count = rtl8139_get_sset_count,
2489 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2492 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2494 struct rtl8139_private *tp = netdev_priv(dev);
2497 if (!netif_running(dev))
2500 spin_lock_irq(&tp->lock);
2501 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
2502 spin_unlock_irq(&tp->lock);
2508 static struct rtnl_link_stats64 *
2509 rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
2511 struct rtl8139_private *tp = netdev_priv(dev);
2512 void __iomem *ioaddr = tp->mmio_addr;
2513 unsigned long flags;
2516 if (netif_running(dev)) {
2517 spin_lock_irqsave (&tp->lock, flags);
2518 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2519 RTL_W32 (RxMissed, 0);
2520 spin_unlock_irqrestore (&tp->lock, flags);
2523 netdev_stats_to_stats64(stats, &dev->stats);
2526 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
2527 stats->rx_packets = tp->rx_stats.packets;
2528 stats->rx_bytes = tp->rx_stats.bytes;
2529 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
2532 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
2533 stats->tx_packets = tp->tx_stats.packets;
2534 stats->tx_bytes = tp->tx_stats.bytes;
2535 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
2540 /* Set or clear the multicast filter for this adaptor.
2541 This routine is not state sensitive and need not be SMP locked. */
2543 static void __set_rx_mode (struct net_device *dev)
2545 struct rtl8139_private *tp = netdev_priv(dev);
2546 void __iomem *ioaddr = tp->mmio_addr;
2547 u32 mc_filter[2]; /* Multicast hash filter */
2551 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n",
2552 dev->flags, RTL_R32(RxConfig));
2554 /* Note: do not reorder, GCC is clever about common statements. */
2555 if (dev->flags & IFF_PROMISC) {
2557 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2559 mc_filter[1] = mc_filter[0] = 0xffffffff;
2560 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2561 (dev->flags & IFF_ALLMULTI)) {
2562 /* Too many to filter perfectly -- accept all multicasts. */
2563 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2564 mc_filter[1] = mc_filter[0] = 0xffffffff;
2566 struct netdev_hw_addr *ha;
2567 rx_mode = AcceptBroadcast | AcceptMyPhys;
2568 mc_filter[1] = mc_filter[0] = 0;
2569 netdev_for_each_mc_addr(ha, dev) {
2570 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2572 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2573 rx_mode |= AcceptMulticast;
2577 if (dev->features & NETIF_F_RXALL)
2578 rx_mode |= (AcceptErr | AcceptRunt);
2580 /* We can safely update without stopping the chip. */
2581 tmp = rtl8139_rx_config | rx_mode;
2582 if (tp->rx_config != tmp) {
2583 RTL_W32_F (RxConfig, tmp);
2584 tp->rx_config = tmp;
2586 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2587 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2590 static void rtl8139_set_rx_mode (struct net_device *dev)
2592 unsigned long flags;
2593 struct rtl8139_private *tp = netdev_priv(dev);
2595 spin_lock_irqsave (&tp->lock, flags);
2597 spin_unlock_irqrestore (&tp->lock, flags);
2602 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2604 struct net_device *dev = pci_get_drvdata (pdev);
2605 struct rtl8139_private *tp = netdev_priv(dev);
2606 void __iomem *ioaddr = tp->mmio_addr;
2607 unsigned long flags;
2609 pci_save_state (pdev);
2611 if (!netif_running (dev))
2614 netif_device_detach (dev);
2616 spin_lock_irqsave (&tp->lock, flags);
2618 /* Disable interrupts, stop Tx and Rx. */
2619 RTL_W16 (IntrMask, 0);
2620 RTL_W8 (ChipCmd, 0);
2622 /* Update the error counts. */
2623 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2624 RTL_W32 (RxMissed, 0);
2626 spin_unlock_irqrestore (&tp->lock, flags);
2628 pci_set_power_state (pdev, PCI_D3hot);
2634 static int rtl8139_resume (struct pci_dev *pdev)
2636 struct net_device *dev = pci_get_drvdata (pdev);
2638 pci_restore_state (pdev);
2639 if (!netif_running (dev))
2641 pci_set_power_state (pdev, PCI_D0);
2642 rtl8139_init_ring (dev);
2643 rtl8139_hw_start (dev);
2644 netif_device_attach (dev);
2648 #endif /* CONFIG_PM */
2651 static struct pci_driver rtl8139_pci_driver = {
2653 .id_table = rtl8139_pci_tbl,
2654 .probe = rtl8139_init_one,
2655 .remove = rtl8139_remove_one,
2657 .suspend = rtl8139_suspend,
2658 .resume = rtl8139_resume,
2659 #endif /* CONFIG_PM */
2663 static int __init rtl8139_init_module (void)
2665 /* when we're a module, we always print a version message,
2666 * even if no 8139 board is found.
2669 pr_info(RTL8139_DRIVER_NAME "\n");
2672 return pci_register_driver(&rtl8139_pci_driver);
2676 static void __exit rtl8139_cleanup_module (void)
2678 pci_unregister_driver (&rtl8139_pci_driver);
2682 module_init(rtl8139_init_module);
2683 module_exit(rtl8139_cleanup_module);