Pileus Git - ~andy/linux/blob - drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_hdr.h"
  10
  11 #include <linux/slab.h>
  12 #include <net/ip.h>
  13 #include <linux/bitops.h>
  14
  15 #define MASK(n) ((1ULL<<(n))-1)
  16 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  17
  18 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  19
  20 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  21 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  22 #define CRB_WINDOW_2M   (0x130060)
  23 #define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  24 #define CRB_INDIRECT_2M (0x1e0000UL)
  25
  26 struct qlcnic_ms_reg_ctrl {
  27         u32 ocm_window;
  28         u32 control;
  29         u32 hi;
  30         u32 low;
  31         u32 rd[4];
  32         u32 wd[4];
  33         u64 off;
  34 };
  35
  36 #ifndef readq
  37 static inline u64 readq(void __iomem *addr)
  38 {
  39         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  40 }
  41 #endif
  42
  43 #ifndef writeq
  44 static inline void writeq(u64 val, void __iomem *addr)
  45 {
  46         writel(((u32) (val)), (addr));
  47         writel(((u32) (val >> 32)), (addr + 4));
  48 }
  49 #endif
  50
  51 static struct crb_128M_2M_block_map
  52 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  53     {{{0, 0,         0,         0} } },         /* 0: PCI */
  54     {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
  55           {1, 0x0110000, 0x0120000, 0x130000},
  56           {1, 0x0120000, 0x0122000, 0x124000},
  57           {1, 0x0130000, 0x0132000, 0x126000},
  58           {1, 0x0140000, 0x0142000, 0x128000},
  59           {1, 0x0150000, 0x0152000, 0x12a000},
  60           {1, 0x0160000, 0x0170000, 0x110000},
  61           {1, 0x0170000, 0x0172000, 0x12e000},
  62           {0, 0x0000000, 0x0000000, 0x000000},
  63           {0, 0x0000000, 0x0000000, 0x000000},
  64           {0, 0x0000000, 0x0000000, 0x000000},
  65           {0, 0x0000000, 0x0000000, 0x000000},
  66           {0, 0x0000000, 0x0000000, 0x000000},
  67           {0, 0x0000000, 0x0000000, 0x000000},
  68           {1, 0x01e0000, 0x01e0800, 0x122000},
  69           {0, 0x0000000, 0x0000000, 0x000000} } },
  70         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  71     {{{0, 0,         0,         0} } },     /* 3: */
  72     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  73     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
  74     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
  75     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
  76     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
  77       {0, 0x0000000, 0x0000000, 0x000000},
  78       {0, 0x0000000, 0x0000000, 0x000000},
  79       {0, 0x0000000, 0x0000000, 0x000000},
  80       {0, 0x0000000, 0x0000000, 0x000000},
  81       {0, 0x0000000, 0x0000000, 0x000000},
  82       {0, 0x0000000, 0x0000000, 0x000000},
  83       {0, 0x0000000, 0x0000000, 0x000000},
  84       {0, 0x0000000, 0x0000000, 0x000000},
  85       {0, 0x0000000, 0x0000000, 0x000000},
  86       {0, 0x0000000, 0x0000000, 0x000000},
  87       {0, 0x0000000, 0x0000000, 0x000000},
  88       {0, 0x0000000, 0x0000000, 0x000000},
  89       {0, 0x0000000, 0x0000000, 0x000000},
  90       {0, 0x0000000, 0x0000000, 0x000000},
  91       {1, 0x08f0000, 0x08f2000, 0x172000} } },
  92     {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
  93       {0, 0x0000000, 0x0000000, 0x000000},
  94       {0, 0x0000000, 0x0000000, 0x000000},
  95       {0, 0x0000000, 0x0000000, 0x000000},
  96       {0, 0x0000000, 0x0000000, 0x000000},
  97       {0, 0x0000000, 0x0000000, 0x000000},
  98       {0, 0x0000000, 0x0000000, 0x000000},
  99       {0, 0x0000000, 0x0000000, 0x000000},
 100       {0, 0x0000000, 0x0000000, 0x000000},
 101       {0, 0x0000000, 0x0000000, 0x000000},
 102       {0, 0x0000000, 0x0000000, 0x000000},
 103       {0, 0x0000000, 0x0000000, 0x000000},
 104       {0, 0x0000000, 0x0000000, 0x000000},
 105       {0, 0x0000000, 0x0000000, 0x000000},
 106       {0, 0x0000000, 0x0000000, 0x000000},
 107       {1, 0x09f0000, 0x09f2000, 0x176000} } },
 108     {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
 109       {0, 0x0000000, 0x0000000, 0x000000},
 110       {0, 0x0000000, 0x0000000, 0x000000},
 111       {0, 0x0000000, 0x0000000, 0x000000},
 112       {0, 0x0000000, 0x0000000, 0x000000},
 113       {0, 0x0000000, 0x0000000, 0x000000},
 114       {0, 0x0000000, 0x0000000, 0x000000},
 115       {0, 0x0000000, 0x0000000, 0x000000},
 116       {0, 0x0000000, 0x0000000, 0x000000},
 117       {0, 0x0000000, 0x0000000, 0x000000},
 118       {0, 0x0000000, 0x0000000, 0x000000},
 119       {0, 0x0000000, 0x0000000, 0x000000},
 120       {0, 0x0000000, 0x0000000, 0x000000},
 121       {0, 0x0000000, 0x0000000, 0x000000},
 122       {0, 0x0000000, 0x0000000, 0x000000},
 123       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 124     {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
 125       {0, 0x0000000, 0x0000000, 0x000000},
 126       {0, 0x0000000, 0x0000000, 0x000000},
 127       {0, 0x0000000, 0x0000000, 0x000000},
 128       {0, 0x0000000, 0x0000000, 0x000000},
 129       {0, 0x0000000, 0x0000000, 0x000000},
 130       {0, 0x0000000, 0x0000000, 0x000000},
 131       {0, 0x0000000, 0x0000000, 0x000000},
 132       {0, 0x0000000, 0x0000000, 0x000000},
 133       {0, 0x0000000, 0x0000000, 0x000000},
 134       {0, 0x0000000, 0x0000000, 0x000000},
 135       {0, 0x0000000, 0x0000000, 0x000000},
 136       {0, 0x0000000, 0x0000000, 0x000000},
 137       {0, 0x0000000, 0x0000000, 0x000000},
 138       {0, 0x0000000, 0x0000000, 0x000000},
 139       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 140         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 141         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 142         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 143         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 144         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 145         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 146         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 147         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 148         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 149         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 150         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 151         {{{0, 0,         0,         0} } },     /* 23: */
 152         {{{0, 0,         0,         0} } },     /* 24: */
 153         {{{0, 0,         0,         0} } },     /* 25: */
 154         {{{0, 0,         0,         0} } },     /* 26: */
 155         {{{0, 0,         0,         0} } },     /* 27: */
 156         {{{0, 0,         0,         0} } },     /* 28: */
 157         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 158     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 159     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 160         {{{0} } },                              /* 32: PCI */
 161         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 162           {1, 0x2110000, 0x2120000, 0x130000},
 163           {1, 0x2120000, 0x2122000, 0x124000},
 164           {1, 0x2130000, 0x2132000, 0x126000},
 165           {1, 0x2140000, 0x2142000, 0x128000},
 166           {1, 0x2150000, 0x2152000, 0x12a000},
 167           {1, 0x2160000, 0x2170000, 0x110000},
 168           {1, 0x2170000, 0x2172000, 0x12e000},
 169           {0, 0x0000000, 0x0000000, 0x000000},
 170           {0, 0x0000000, 0x0000000, 0x000000},
 171           {0, 0x0000000, 0x0000000, 0x000000},
 172           {0, 0x0000000, 0x0000000, 0x000000},
 173           {0, 0x0000000, 0x0000000, 0x000000},
 174           {0, 0x0000000, 0x0000000, 0x000000},
 175           {0, 0x0000000, 0x0000000, 0x000000},
 176           {0, 0x0000000, 0x0000000, 0x000000} } },
 177         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 178         {{{0} } },                              /* 35: */
 179         {{{0} } },                              /* 36: */
 180         {{{0} } },                              /* 37: */
 181         {{{0} } },                              /* 38: */
 182         {{{0} } },                              /* 39: */
 183         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 184         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 185         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 186         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 187         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 188         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 189         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 190         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 191         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 192         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 193         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 194         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 195         {{{0} } },                              /* 52: */
 196         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 197         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 198         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 199         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 200         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 201         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 202         {{{0} } },                              /* 59: I2C0 */
 203         {{{0} } },                              /* 60: I2C1 */
 204         {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
 205         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 206         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 207 };
 208
 209 /*
 210  * top 12 bits of crb internal address (hub, agent)
 211  */
 212 static const unsigned crb_hub_agt[64] = {
 213         0,
 214         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 215         QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
 216         QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
 217         0,
 218         QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
 219         QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
 220         QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
 221         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
 222         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
 223         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
 224         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
 225         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 226         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 227         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 228         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
 229         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 230         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
 231         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
 232         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
 233         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
 234         QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
 235         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
 236         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
 237         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
 238         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
 239         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
 240         0,
 241         QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
 242         QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
 243         0,
 244         QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
 245         0,
 246         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 247         QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
 248         0,
 249         0,
 250         0,
 251         0,
 252         0,
 253         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 254         0,
 255         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
 256         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
 257         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
 258         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
 259         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
 260         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
 261         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
 262         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 263         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 264         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 265         0,
 266         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
 267         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
 268         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
 269         QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
 270         0,
 271         QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
 272         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
 273         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
 274         0,
 275         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
 276         0,
 277 };
 278
 279 static const u32 msi_tgt_status[8] = {
 280         ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
 281         ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
 282         ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
 283         ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7
 284 };
 285
 286 /*  PCI Windowing for DDR regions.  */
 287
 288 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
 289
 290 static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data)
 291 {
 292         u32 dest;
 293         void __iomem *val;
 294
 295         dest = addr & 0xFFFF0000;
 296         val = bar0 + QLCNIC_FW_DUMP_REG1;
 297         writel(dest, val);
 298         readl(val);
 299         val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
 300         *data = readl(val);
 301 }
 302
 303 static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data)
 304 {
 305         u32 dest;
 306         void __iomem *val;
 307
 308         dest = addr & 0xFFFF0000;
 309         val = bar0 + QLCNIC_FW_DUMP_REG1;
 310         writel(dest, val);
 311         readl(val);
 312         val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
 313         writel(data, val);
 314         readl(val);
 315 }
 316
 317 int
 318 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
 319 {
 320         int done = 0, timeout = 0;
 321
 322         while (!done) {
 323                 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
 324                 if (done == 1)
 325                         break;
 326                 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
 327                         dev_err(&adapter->pdev->dev,
 328                                 "Failed to acquire sem=%d lock; holdby=%d\n",
 329                                 sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
 330                         return -EIO;
 331                 }
 332                 msleep(1);
 333         }
 334
 335         if (id_reg)
 336                 QLCWR32(adapter, id_reg, adapter->portnum);
 337
 338         return 0;
 339 }
 340
 341 void
 342 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
 343 {
 344         QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
 345 }
 346
 347 int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr)
 348 {
 349         u32 data;
 350
 351         if (qlcnic_82xx_check(adapter))
 352                 qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data);
 353         else {
 354                 data = qlcnic_83xx_rd_reg_indirect(adapter, addr);
 355                 if (data == -EIO)
 356                         return -EIO;
 357         }
 358         return data;
 359 }
 360
 361 void qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data)
 362 {
 363         if (qlcnic_82xx_check(adapter))
 364                 qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data);
 365         else
 366                 qlcnic_83xx_wrt_reg_indirect(adapter, addr, data);
 367 }
 368
 369 static int
 370 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
 371                 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
 372 {
 373         u32 i, producer;
 374         struct qlcnic_cmd_buffer *pbuf;
 375         struct cmd_desc_type0 *cmd_desc;
 376         struct qlcnic_host_tx_ring *tx_ring;
 377
 378         i = 0;
 379
 380         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 381                 return -EIO;
 382
 383         tx_ring = adapter->tx_ring;
 384         __netif_tx_lock_bh(tx_ring->txq);
 385
 386         producer = tx_ring->producer;
 387
 388         if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
 389                 netif_tx_stop_queue(tx_ring->txq);
 390                 smp_mb();
 391                 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
 392                         if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
 393                                 netif_tx_wake_queue(tx_ring->txq);
 394                 } else {
 395                         adapter->stats.xmit_off++;
 396                         __netif_tx_unlock_bh(tx_ring->txq);
 397                         return -EBUSY;
 398                 }
 399         }
 400
 401         do {
 402                 cmd_desc = &cmd_desc_arr[i];
 403
 404                 pbuf = &tx_ring->cmd_buf_arr[producer];
 405                 pbuf->skb = NULL;
 406                 pbuf->frag_count = 0;
 407
 408                 memcpy(&tx_ring->desc_head[producer],
 409                        cmd_desc, sizeof(struct cmd_desc_type0));
 410
 411                 producer = get_next_index(producer, tx_ring->num_desc);
 412                 i++;
 413
 414         } while (i != nr_desc);
 415
 416         tx_ring->producer = producer;
 417
 418         qlcnic_update_cmd_producer(tx_ring);
 419
 420         __netif_tx_unlock_bh(tx_ring->txq);
 421
 422         return 0;
 423 }
 424
 425 int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
 426                                    u16 vlan_id, u8 op)
 427 {
 428         struct qlcnic_nic_req req;
 429         struct qlcnic_mac_req *mac_req;
 430         struct qlcnic_vlan_req *vlan_req;
 431         u64 word;
 432
 433         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 434         req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
 435
 436         word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
 437         req.req_hdr = cpu_to_le64(word);
 438
 439         mac_req = (struct qlcnic_mac_req *)&req.words[0];
 440         mac_req->op = op;
 441         memcpy(mac_req->mac_addr, addr, 6);
 442
 443         vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
 444         vlan_req->vlan_id = cpu_to_le16(vlan_id);
 445
 446         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 447 }
 448
 449 int qlcnic_nic_del_mac(struct qlcnic_adapter *adapter, const u8 *addr)
 450 {
 451         struct list_head *head;
 452         struct qlcnic_mac_list_s *cur;
 453         int err = -EINVAL;
 454
 455         /* Delete MAC from the existing list */
 456         list_for_each(head, &adapter->mac_list) {
 457                 cur = list_entry(head, struct qlcnic_mac_list_s, list);
 458                 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
 459                         err = qlcnic_sre_macaddr_change(adapter, cur->mac_addr,
 460                                                         0, QLCNIC_MAC_DEL);
 461                         if (err)
 462                                 return err;
 463                         list_del(&cur->list);
 464                         kfree(cur);
 465                         return err;
 466                 }
 467         }
 468         return err;
 469 }
 470
 471 int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr, u16 vlan)
 472 {
 473         struct list_head *head;
 474         struct qlcnic_mac_list_s *cur;
 475
 476         /* look up if already exists */
 477         list_for_each(head, &adapter->mac_list) {
 478                 cur = list_entry(head, struct qlcnic_mac_list_s, list);
 479                 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
 480                         return 0;
 481         }
 482
 483         cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
 484         if (cur == NULL)
 485                 return -ENOMEM;
 486
 487         memcpy(cur->mac_addr, addr, ETH_ALEN);
 488
 489         if (qlcnic_sre_macaddr_change(adapter,
 490                                 cur->mac_addr, vlan, QLCNIC_MAC_ADD)) {
 491                 kfree(cur);
 492                 return -EIO;
 493         }
 494
 495         list_add_tail(&cur->list, &adapter->mac_list);
 496         return 0;
 497 }
 498
 499 void __qlcnic_set_multi(struct net_device *netdev, u16 vlan)
 500 {
 501         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 502         struct qlcnic_hardware_context *ahw = adapter->ahw;
 503         struct netdev_hw_addr *ha;
 504         static const u8 bcast_addr[ETH_ALEN] = {
 505                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
 506         };
 507         u32 mode = VPORT_MISS_MODE_DROP;
 508
 509         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 510                 return;
 511
 512         if (!qlcnic_sriov_vf_check(adapter))
 513                 qlcnic_nic_add_mac(adapter, adapter->mac_addr, vlan);
 514         qlcnic_nic_add_mac(adapter, bcast_addr, vlan);
 515
 516         if (netdev->flags & IFF_PROMISC) {
 517                 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
 518                         mode = VPORT_MISS_MODE_ACCEPT_ALL;
 519         } else if (netdev->flags & IFF_ALLMULTI) {
 520                 if (netdev_mc_count(netdev) > ahw->max_mc_count) {
 521                         mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 522                 } else if (!netdev_mc_empty(netdev) &&
 523                            !qlcnic_sriov_vf_check(adapter)) {
 524                                 netdev_for_each_mc_addr(ha, netdev)
 525                                         qlcnic_nic_add_mac(adapter, ha->addr,
 526                                                            vlan);
 527                 }
 528                 if (mode != VPORT_MISS_MODE_ACCEPT_MULTI &&
 529                     qlcnic_sriov_vf_check(adapter))
 530                         qlcnic_vf_add_mc_list(netdev, vlan);
 531         }
 532
 533         /* configure unicast MAC address, if there is not sufficient space
 534          * to store all the unicast addresses then enable promiscuous mode
 535          */
 536         if (netdev_uc_count(netdev) > ahw->max_uc_count) {
 537                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 538         } else if (!netdev_uc_empty(netdev)) {
 539                 netdev_for_each_uc_addr(ha, netdev)
 540                         qlcnic_nic_add_mac(adapter, ha->addr, vlan);
 541         }
 542
 543         if (!qlcnic_sriov_vf_check(adapter)) {
 544                 if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
 545                     !adapter->fdb_mac_learn) {
 546                         qlcnic_alloc_lb_filters_mem(adapter);
 547                         adapter->drv_mac_learn = true;
 548                 } else {
 549                         adapter->drv_mac_learn = false;
 550                 }
 551         }
 552
 553         qlcnic_nic_set_promisc(adapter, mode);
 554 }
 555
 556 void qlcnic_set_multi(struct net_device *netdev)
 557 {
 558         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 559         struct netdev_hw_addr *ha;
 560         struct qlcnic_mac_list_s *cur;
 561
 562         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 563                 return;
 564         if (qlcnic_sriov_vf_check(adapter)) {
 565                 if (!netdev_mc_empty(netdev)) {
 566                         netdev_for_each_mc_addr(ha, netdev) {
 567                                 cur = kzalloc(sizeof(struct qlcnic_mac_list_s),
 568                                               GFP_ATOMIC);
 569                                 if (cur == NULL)
 570                                         break;
 571                                 memcpy(cur->mac_addr,
 572                                        ha->addr, ETH_ALEN);
 573                                 list_add_tail(&cur->list, &adapter->vf_mc_list);
 574                         }
 575                 }
 576                 qlcnic_sriov_vf_schedule_multi(adapter->netdev);
 577                 return;
 578         }
 579         __qlcnic_set_multi(netdev, 0);
 580 }
 581
 582 int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
 583 {
 584         struct qlcnic_nic_req req;
 585         u64 word;
 586
 587         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 588
 589         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 590
 591         word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
 592                         ((u64)adapter->portnum << 16);
 593         req.req_hdr = cpu_to_le64(word);
 594
 595         req.words[0] = cpu_to_le64(mode);
 596
 597         return qlcnic_send_cmd_descs(adapter,
 598                                 (struct cmd_desc_type0 *)&req, 1);
 599 }
 600
 601 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter)
 602 {
 603         struct qlcnic_mac_list_s *cur;
 604         struct list_head *head = &adapter->mac_list;
 605
 606         while (!list_empty(head)) {
 607                 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
 608                 qlcnic_sre_macaddr_change(adapter,
 609                                 cur->mac_addr, 0, QLCNIC_MAC_DEL);
 610                 list_del(&cur->list);
 611                 kfree(cur);
 612         }
 613 }
 614
 615 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
 616 {
 617         struct qlcnic_filter *tmp_fil;
 618         struct hlist_node *n;
 619         struct hlist_head *head;
 620         int i;
 621         unsigned long time;
 622         u8 cmd;
 623
 624         for (i = 0; i < adapter->fhash.fbucket_size; i++) {
 625                 head = &(adapter->fhash.fhead[i]);
 626                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
 627                         cmd =  tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 628                                                   QLCNIC_MAC_DEL;
 629                         time = tmp_fil->ftime;
 630                         if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) {
 631                                 qlcnic_sre_macaddr_change(adapter,
 632                                                           tmp_fil->faddr,
 633                                                           tmp_fil->vlan_id,
 634                                                           cmd);
 635                                 spin_lock_bh(&adapter->mac_learn_lock);
 636                                 adapter->fhash.fnum--;
 637                                 hlist_del(&tmp_fil->fnode);
 638                                 spin_unlock_bh(&adapter->mac_learn_lock);
 639                                 kfree(tmp_fil);
 640                         }
 641                 }
 642         }
 643         for (i = 0; i < adapter->rx_fhash.fbucket_size; i++) {
 644                 head = &(adapter->rx_fhash.fhead[i]);
 645
 646                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode)
 647                 {
 648                         time = tmp_fil->ftime;
 649                         if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) {
 650                                 spin_lock_bh(&adapter->rx_mac_learn_lock);
 651                                 adapter->rx_fhash.fnum--;
 652                                 hlist_del(&tmp_fil->fnode);
 653                                 spin_unlock_bh(&adapter->rx_mac_learn_lock);
 654                                 kfree(tmp_fil);
 655                         }
 656                 }
 657         }
 658 }
 659
 660 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
 661 {
 662         struct qlcnic_filter *tmp_fil;
 663         struct hlist_node *n;
 664         struct hlist_head *head;
 665         int i;
 666         u8 cmd;
 667
 668         for (i = 0; i < adapter->fhash.fbucket_size; i++) {
 669                 head = &(adapter->fhash.fhead[i]);
 670                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
 671                         cmd =  tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 672                                                   QLCNIC_MAC_DEL;
 673                         qlcnic_sre_macaddr_change(adapter,
 674                                                   tmp_fil->faddr,
 675                                                   tmp_fil->vlan_id,
 676                                                   cmd);
 677                         spin_lock_bh(&adapter->mac_learn_lock);
 678                         adapter->fhash.fnum--;
 679                         hlist_del(&tmp_fil->fnode);
 680                         spin_unlock_bh(&adapter->mac_learn_lock);
 681                         kfree(tmp_fil);
 682                 }
 683         }
 684 }
 685
 686 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
 687 {
 688         struct qlcnic_nic_req req;
 689         int rv;
 690
 691         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 692
 693         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 694         req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
 695                 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
 696
 697         req.words[0] = cpu_to_le64(flag);
 698
 699         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 700         if (rv != 0)
 701                 dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
 702                                 flag ? "Set" : "Reset");
 703         return rv;
 704 }
 705
 706 int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
 707 {
 708         if (qlcnic_set_fw_loopback(adapter, mode))
 709                 return -EIO;
 710
 711         if (qlcnic_nic_set_promisc(adapter,
 712                                    VPORT_MISS_MODE_ACCEPT_ALL)) {
 713                 qlcnic_set_fw_loopback(adapter, 0);
 714                 return -EIO;
 715         }
 716
 717         msleep(1000);
 718         return 0;
 719 }
 720
 721 int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
 722 {
 723         struct net_device *netdev = adapter->netdev;
 724
 725         mode = VPORT_MISS_MODE_DROP;
 726         qlcnic_set_fw_loopback(adapter, 0);
 727
 728         if (netdev->flags & IFF_PROMISC)
 729                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 730         else if (netdev->flags & IFF_ALLMULTI)
 731                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 732
 733         qlcnic_nic_set_promisc(adapter, mode);
 734         msleep(1000);
 735         return 0;
 736 }
 737
 738 /*
 739  * Send the interrupt coalescing parameter set by ethtool to the card.
 740  */
 741 void qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter)
 742 {
 743         struct qlcnic_nic_req req;
 744         int rv;
 745
 746         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 747
 748         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 749
 750         req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
 751                 ((u64) adapter->portnum << 16));
 752
 753         req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
 754         req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
 755                         ((u64) adapter->ahw->coal.rx_time_us) << 16);
 756         req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
 757                         ((u64) adapter->ahw->coal.type) << 32 |
 758                         ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
 759         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 760         if (rv != 0)
 761                 dev_err(&adapter->netdev->dev,
 762                         "Could not send interrupt coalescing parameters\n");
 763 }
 764
 765 #define QLCNIC_ENABLE_IPV4_LRO          1
 766 #define QLCNIC_ENABLE_IPV6_LRO          2
 767 #define QLCNIC_NO_DEST_IPV4_CHECK       (1 << 8)
 768 #define QLCNIC_NO_DEST_IPV6_CHECK       (2 << 8)
 769
 770 int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
 771 {
 772         struct qlcnic_nic_req req;
 773         u64 word;
 774         int rv;
 775
 776         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 777                 return 0;
 778
 779         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 780
 781         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 782
 783         word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
 784         req.req_hdr = cpu_to_le64(word);
 785
 786         word = 0;
 787         if (enable) {
 788                 word = QLCNIC_ENABLE_IPV4_LRO | QLCNIC_NO_DEST_IPV4_CHECK;
 789                 if (adapter->ahw->extra_capability[0] &
 790                     QLCNIC_FW_CAP2_HW_LRO_IPV6)
 791                         word |= QLCNIC_ENABLE_IPV6_LRO |
 792                                 QLCNIC_NO_DEST_IPV6_CHECK;
 793         }
 794
 795         req.words[0] = cpu_to_le64(word);
 796
 797         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 798         if (rv != 0)
 799                 dev_err(&adapter->netdev->dev,
 800                         "Could not send configure hw lro request\n");
 801
 802         return rv;
 803 }
 804
 805 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
 806 {
 807         struct qlcnic_nic_req req;
 808         u64 word;
 809         int rv;
 810
 811         if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
 812                 return 0;
 813
 814         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 815
 816         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 817
 818         word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
 819                 ((u64)adapter->portnum << 16);
 820         req.req_hdr = cpu_to_le64(word);
 821
 822         req.words[0] = cpu_to_le64(enable);
 823
 824         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 825         if (rv != 0)
 826                 dev_err(&adapter->netdev->dev,
 827                         "Could not send configure bridge mode request\n");
 828
 829         adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
 830
 831         return rv;
 832 }
 833
 834
 835 #define QLCNIC_RSS_HASHTYPE_IP_TCP      0x3
 836 #define QLCNIC_ENABLE_TYPE_C_RSS        BIT_10
 837 #define QLCNIC_RSS_FEATURE_FLAG (1ULL << 63)
 838 #define QLCNIC_RSS_IND_TABLE_MASK       0x7ULL
 839
 840 int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int enable)
 841 {
 842         struct qlcnic_nic_req req;
 843         u64 word;
 844         int i, rv;
 845
 846         static const u64 key[] = {
 847                 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 848                 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 849                 0x255b0ec26d5a56daULL
 850         };
 851
 852         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 853         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 854
 855         word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
 856         req.req_hdr = cpu_to_le64(word);
 857
 858         /*
 859          * RSS request:
 860          * bits 3-0: hash_method
 861          *      5-4: hash_type_ipv4
 862          *      7-6: hash_type_ipv6
 863          *        8: enable
 864          *        9: use indirection table
 865          *       10: type-c rss
 866          *       11: udp rss
 867          *    47-12: reserved
 868          *    62-48: indirection table mask
 869          *       63: feature flag
 870          */
 871         word =  ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
 872                 ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
 873                 ((u64)(enable & 0x1) << 8) |
 874                 ((u64)QLCNIC_RSS_IND_TABLE_MASK << 48) |
 875                 (u64)QLCNIC_ENABLE_TYPE_C_RSS |
 876                 (u64)QLCNIC_RSS_FEATURE_FLAG;
 877
 878         req.words[0] = cpu_to_le64(word);
 879         for (i = 0; i < 5; i++)
 880                 req.words[i+1] = cpu_to_le64(key[i]);
 881
 882         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 883         if (rv != 0)
 884                 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
 885
 886         return rv;
 887 }
 888
 889 void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
 890                                __be32 ip, int cmd)
 891 {
 892         struct qlcnic_nic_req req;
 893         struct qlcnic_ipaddr *ipa;
 894         u64 word;
 895         int rv;
 896
 897         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 898         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 899
 900         word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
 901         req.req_hdr = cpu_to_le64(word);
 902
 903         req.words[0] = cpu_to_le64(cmd);
 904         ipa = (struct qlcnic_ipaddr *)&req.words[1];
 905         ipa->ipv4 = ip;
 906
 907         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 908         if (rv != 0)
 909                 dev_err(&adapter->netdev->dev,
 910                                 "could not notify %s IP 0x%x reuqest\n",
 911                                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
 912 }
 913
 914 int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int enable)
 915 {
 916         struct qlcnic_nic_req req;
 917         u64 word;
 918         int rv;
 919         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 920         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 921
 922         word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
 923         req.req_hdr = cpu_to_le64(word);
 924         req.words[0] = cpu_to_le64(enable | (enable << 8));
 925         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 926         if (rv != 0)
 927                 dev_err(&adapter->netdev->dev,
 928                                 "could not configure link notification\n");
 929
 930         return rv;
 931 }
 932
 933 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
 934 {
 935         struct qlcnic_nic_req req;
 936         u64 word;
 937         int rv;
 938
 939         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 940                 return 0;
 941
 942         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 943         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 944
 945         word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
 946                 ((u64)adapter->portnum << 16) |
 947                 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
 948
 949         req.req_hdr = cpu_to_le64(word);
 950
 951         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 952         if (rv != 0)
 953                 dev_err(&adapter->netdev->dev,
 954                                  "could not cleanup lro flows\n");
 955
 956         return rv;
 957 }
 958
 959 /*
 960  * qlcnic_change_mtu - Change the Maximum Transfer Unit
 961  * @returns 0 on success, negative on failure
 962  */
 963
 964 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
 965 {
 966         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 967         int rc = 0;
 968
 969         if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
 970                 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
 971                         " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
 972                 return -EINVAL;
 973         }
 974
 975         rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
 976
 977         if (!rc)
 978                 netdev->mtu = mtu;
 979
 980         return rc;
 981 }
 982
 983 static netdev_features_t qlcnic_process_flags(struct qlcnic_adapter *adapter,
 984                                               netdev_features_t features)
 985 {
 986         u32 offload_flags = adapter->offload_flags;
 987
 988         if (offload_flags & BIT_0) {
 989                 features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
 990                             NETIF_F_IPV6_CSUM;
 991                 adapter->rx_csum = 1;
 992                 if (QLCNIC_IS_TSO_CAPABLE(adapter)) {
 993                         if (!(offload_flags & BIT_1))
 994                                 features &= ~NETIF_F_TSO;
 995                         else
 996                                 features |= NETIF_F_TSO;
 997
 998                         if (!(offload_flags & BIT_2))
 999                                 features &= ~NETIF_F_TSO6;
1000                         else
1001                                 features |= NETIF_F_TSO6;
1002                 }
1003         } else {
1004                 features &= ~(NETIF_F_RXCSUM |
1005                               NETIF_F_IP_CSUM |
1006                               NETIF_F_IPV6_CSUM);
1007
1008                 if (QLCNIC_IS_TSO_CAPABLE(adapter))
1009                         features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
1010                 adapter->rx_csum = 0;
1011         }
1012
1013         return features;
1014 }
1015
1016 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1017         netdev_features_t features)
1018 {
1019         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1020         netdev_features_t changed;
1021
1022         if (qlcnic_82xx_check(adapter) &&
1023             (adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
1024                 if (adapter->flags & QLCNIC_APP_CHANGED_FLAGS) {
1025                         features = qlcnic_process_flags(adapter, features);
1026                 } else {
1027                         changed = features ^ netdev->features;
1028                         features ^= changed & (NETIF_F_RXCSUM |
1029                                                NETIF_F_IP_CSUM |
1030                                                NETIF_F_IPV6_CSUM |
1031                                                NETIF_F_TSO |
1032                                                NETIF_F_TSO6);
1033                 }
1034         }
1035
1036         if (!(features & NETIF_F_RXCSUM))
1037                 features &= ~NETIF_F_LRO;
1038
1039         return features;
1040 }
1041
1042
1043 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features)
1044 {
1045         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1046         netdev_features_t changed = netdev->features ^ features;
1047         int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
1048
1049         if (!(changed & NETIF_F_LRO))
1050                 return 0;
1051
1052         netdev->features ^= NETIF_F_LRO;
1053
1054         if (qlcnic_config_hw_lro(adapter, hw_lro))
1055                 return -EIO;
1056
1057         if (!hw_lro && qlcnic_82xx_check(adapter)) {
1058                 if (qlcnic_send_lro_cleanup(adapter))
1059                         return -EIO;
1060         }
1061
1062         return 0;
1063 }
1064
1065 /*
1066  * Changes the CRB window to the specified window.
1067  */
1068  /* Returns < 0 if off is not valid,
1069  *       1 if window access is needed. 'off' is set to offset from
1070  *         CRB space in 128M pci map
1071  *       0 if no window access is needed. 'off' is set to 2M addr
1072  * In: 'off' is offset from base in 128M pci map
1073  */
1074 static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw,
1075                                       ulong off, void __iomem **addr)
1076 {
1077         const struct crb_128M_2M_sub_block_map *m;
1078
1079         if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
1080                 return -EINVAL;
1081
1082         off -= QLCNIC_PCI_CRBSPACE;
1083
1084         /*
1085          * Try direct map
1086          */
1087         m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1088
1089         if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1090                 *addr = ahw->pci_base0 + m->start_2M +
1091                         (off - m->start_128M);
1092                 return 0;
1093         }
1094
1095         /*
1096          * Not in direct map, use crb window
1097          */
1098         *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
1099         return 1;
1100 }
1101
1102 /*
1103  * In: 'off' is offset from CRB space in 128M pci map
1104  * Out: 'off' is 2M pci map addr
1105  * side effect: lock crb window
1106  */
1107 static int
1108 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
1109 {
1110         u32 window;
1111         void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
1112
1113         off -= QLCNIC_PCI_CRBSPACE;
1114
1115         window = CRB_HI(off);
1116         if (window == 0) {
1117                 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
1118                 return -EIO;
1119         }
1120
1121         writel(window, addr);
1122         if (readl(addr) != window) {
1123                 if (printk_ratelimit())
1124                         dev_warn(&adapter->pdev->dev,
1125                                 "failed to set CRB window to %d off 0x%lx\n",
1126                                 window, off);
1127                 return -EIO;
1128         }
1129         return 0;
1130 }
1131
1132 int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1133                                u32 data)
1134 {
1135         unsigned long flags;
1136         int rv;
1137         void __iomem *addr = NULL;
1138
1139         rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1140
1141         if (rv == 0) {
1142                 writel(data, addr);
1143                 return 0;
1144         }
1145
1146         if (rv > 0) {
1147                 /* indirect access */
1148                 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1149                 crb_win_lock(adapter);
1150                 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
1151                 if (!rv)
1152                         writel(data, addr);
1153                 crb_win_unlock(adapter);
1154                 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1155                 return rv;
1156         }
1157
1158         dev_err(&adapter->pdev->dev,
1159                         "%s: invalid offset: 0x%016lx\n", __func__, off);
1160         dump_stack();
1161         return -EIO;
1162 }
1163
1164 int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
1165 {
1166         unsigned long flags;
1167         int rv;
1168         u32 data = -1;
1169         void __iomem *addr = NULL;
1170
1171         rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1172
1173         if (rv == 0)
1174                 return readl(addr);
1175
1176         if (rv > 0) {
1177                 /* indirect access */
1178                 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1179                 crb_win_lock(adapter);
1180                 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
1181                         data = readl(addr);
1182                 crb_win_unlock(adapter);
1183                 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1184                 return data;
1185         }
1186
1187         dev_err(&adapter->pdev->dev,
1188                         "%s: invalid offset: 0x%016lx\n", __func__, off);
1189         dump_stack();
1190         return -1;
1191 }
1192
1193 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw,
1194                                 u32 offset)
1195 {
1196         void __iomem *addr = NULL;
1197
1198         WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr));
1199
1200         return addr;
1201 }
1202
1203 static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter,
1204                                         u32 window, u64 off, u64 *data, int op)
1205 {
1206         void __iomem *addr;
1207         u32 start;
1208
1209         mutex_lock(&adapter->ahw->mem_lock);
1210
1211         writel(window, adapter->ahw->ocm_win_crb);
1212         /* read back to flush */
1213         readl(adapter->ahw->ocm_win_crb);
1214         start = QLCNIC_PCI_OCM0_2M + off;
1215
1216         addr = adapter->ahw->pci_base0 + start;
1217
1218         if (op == 0)    /* read */
1219                 *data = readq(addr);
1220         else            /* write */
1221                 writeq(*data, addr);
1222
1223         /* Set window to 0 */
1224         writel(0, adapter->ahw->ocm_win_crb);
1225         readl(adapter->ahw->ocm_win_crb);
1226
1227         mutex_unlock(&adapter->ahw->mem_lock);
1228         return 0;
1229 }
1230
1231 void
1232 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1233 {
1234         void __iomem *addr = adapter->ahw->pci_base0 +
1235                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1236
1237         mutex_lock(&adapter->ahw->mem_lock);
1238         *data = readq(addr);
1239         mutex_unlock(&adapter->ahw->mem_lock);
1240 }
1241
1242 void
1243 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1244 {
1245         void __iomem *addr = adapter->ahw->pci_base0 +
1246                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1247
1248         mutex_lock(&adapter->ahw->mem_lock);
1249         writeq(data, addr);
1250         mutex_unlock(&adapter->ahw->mem_lock);
1251 }
1252
1253
1254
1255 /* Set MS memory control data for different adapters */
1256 static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off,
1257                                    struct qlcnic_ms_reg_ctrl *ms)
1258 {
1259         ms->control = QLCNIC_MS_CTRL;
1260         ms->low = QLCNIC_MS_ADDR_LO;
1261         ms->hi = QLCNIC_MS_ADDR_HI;
1262         if (off & 0xf) {
1263                 ms->wd[0] = QLCNIC_MS_WRTDATA_LO;
1264                 ms->rd[0] = QLCNIC_MS_RDDATA_LO;
1265                 ms->wd[1] = QLCNIC_MS_WRTDATA_HI;
1266                 ms->rd[1] = QLCNIC_MS_RDDATA_HI;
1267                 ms->wd[2] = QLCNIC_MS_WRTDATA_ULO;
1268                 ms->wd[3] = QLCNIC_MS_WRTDATA_UHI;
1269                 ms->rd[2] = QLCNIC_MS_RDDATA_ULO;
1270                 ms->rd[3] = QLCNIC_MS_RDDATA_UHI;
1271         } else {
1272                 ms->wd[0] = QLCNIC_MS_WRTDATA_ULO;
1273                 ms->rd[0] = QLCNIC_MS_RDDATA_ULO;
1274                 ms->wd[1] = QLCNIC_MS_WRTDATA_UHI;
1275                 ms->rd[1] = QLCNIC_MS_RDDATA_UHI;
1276                 ms->wd[2] = QLCNIC_MS_WRTDATA_LO;
1277                 ms->wd[3] = QLCNIC_MS_WRTDATA_HI;
1278                 ms->rd[2] = QLCNIC_MS_RDDATA_LO;
1279                 ms->rd[3] = QLCNIC_MS_RDDATA_HI;
1280         }
1281
1282         ms->ocm_window = OCM_WIN_P3P(off);
1283         ms->off = GET_MEM_OFFS_2M(off);
1284 }
1285
1286 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1287 {
1288         int j, ret = 0;
1289         u32 temp, off8;
1290         struct qlcnic_ms_reg_ctrl ms;
1291
1292         /* Only 64-bit aligned access */
1293         if (off & 7)
1294                 return -EIO;
1295
1296         memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1297         if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1298                             QLCNIC_ADDR_QDR_NET_MAX) ||
1299               ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1300                             QLCNIC_ADDR_DDR_NET_MAX)))
1301                 return -EIO;
1302
1303         qlcnic_set_ms_controls(adapter, off, &ms);
1304
1305         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1306                 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1307                                                     ms.off, &data, 1);
1308
1309         off8 = off & ~0xf;
1310
1311         mutex_lock(&adapter->ahw->mem_lock);
1312
1313         qlcnic_ind_wr(adapter, ms.low, off8);
1314         qlcnic_ind_wr(adapter, ms.hi, 0);
1315
1316         qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1317         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1318
1319         for (j = 0; j < MAX_CTL_CHECK; j++) {
1320                 temp = qlcnic_ind_rd(adapter, ms.control);
1321                 if ((temp & TA_CTL_BUSY) == 0)
1322                         break;
1323         }
1324
1325         if (j >= MAX_CTL_CHECK) {
1326                 ret = -EIO;
1327                 goto done;
1328         }
1329
1330         /* This is the modify part of read-modify-write */
1331         qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0]));
1332         qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1]));
1333         /* This is the write part of read-modify-write */
1334         qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff);
1335         qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff);
1336
1337         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE);
1338         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START);
1339
1340         for (j = 0; j < MAX_CTL_CHECK; j++) {
1341                 temp = qlcnic_ind_rd(adapter, ms.control);
1342                 if ((temp & TA_CTL_BUSY) == 0)
1343                         break;
1344         }
1345
1346         if (j >= MAX_CTL_CHECK) {
1347                 if (printk_ratelimit())
1348                         dev_err(&adapter->pdev->dev,
1349                                         "failed to write through agent\n");
1350                 ret = -EIO;
1351         } else
1352                 ret = 0;
1353
1354 done:
1355         mutex_unlock(&adapter->ahw->mem_lock);
1356
1357         return ret;
1358 }
1359
1360 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1361 {
1362         int j, ret;
1363         u32 temp, off8;
1364         u64 val;
1365         struct qlcnic_ms_reg_ctrl ms;
1366
1367         /* Only 64-bit aligned access */
1368         if (off & 7)
1369                 return -EIO;
1370         if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1371                             QLCNIC_ADDR_QDR_NET_MAX) ||
1372               ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1373                             QLCNIC_ADDR_DDR_NET_MAX)))
1374                 return -EIO;
1375
1376         memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1377         qlcnic_set_ms_controls(adapter, off, &ms);
1378
1379         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1380                 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1381                                                     ms.off, data, 0);
1382
1383         mutex_lock(&adapter->ahw->mem_lock);
1384
1385         off8 = off & ~0xf;
1386
1387         qlcnic_ind_wr(adapter, ms.low, off8);
1388         qlcnic_ind_wr(adapter, ms.hi, 0);
1389
1390         qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1391         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1392
1393         for (j = 0; j < MAX_CTL_CHECK; j++) {
1394                 temp = qlcnic_ind_rd(adapter, ms.control);
1395                 if ((temp & TA_CTL_BUSY) == 0)
1396                         break;
1397         }
1398
1399         if (j >= MAX_CTL_CHECK) {
1400                 if (printk_ratelimit())
1401                         dev_err(&adapter->pdev->dev,
1402                                         "failed to read through agent\n");
1403                 ret = -EIO;
1404         } else {
1405
1406                 temp = qlcnic_ind_rd(adapter, ms.rd[3]);
1407                 val = (u64)temp << 32;
1408                 val |= qlcnic_ind_rd(adapter, ms.rd[2]);
1409                 *data = val;
1410                 ret = 0;
1411         }
1412
1413         mutex_unlock(&adapter->ahw->mem_lock);
1414
1415         return ret;
1416 }
1417
1418 int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter)
1419 {
1420         int offset, board_type, magic;
1421         struct pci_dev *pdev = adapter->pdev;
1422
1423         offset = QLCNIC_FW_MAGIC_OFFSET;
1424         if (qlcnic_rom_fast_read(adapter, offset, &magic))
1425                 return -EIO;
1426
1427         if (magic != QLCNIC_BDINFO_MAGIC) {
1428                 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1429                         magic);
1430                 return -EIO;
1431         }
1432
1433         offset = QLCNIC_BRDTYPE_OFFSET;
1434         if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1435                 return -EIO;
1436
1437         adapter->ahw->board_type = board_type;
1438
1439         if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
1440                 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1441                 if ((gpio & 0x8000) == 0)
1442                         board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
1443         }
1444
1445         switch (board_type) {
1446         case QLCNIC_BRDTYPE_P3P_HMEZ:
1447         case QLCNIC_BRDTYPE_P3P_XG_LOM:
1448         case QLCNIC_BRDTYPE_P3P_10G_CX4:
1449         case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1450         case QLCNIC_BRDTYPE_P3P_IMEZ:
1451         case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1452         case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1453         case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1454         case QLCNIC_BRDTYPE_P3P_10G_XFP:
1455         case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
1456                 adapter->ahw->port_type = QLCNIC_XGBE;
1457                 break;
1458         case QLCNIC_BRDTYPE_P3P_REF_QG:
1459         case QLCNIC_BRDTYPE_P3P_4_GB:
1460         case QLCNIC_BRDTYPE_P3P_4_GB_MM:
1461                 adapter->ahw->port_type = QLCNIC_GBE;
1462                 break;
1463         case QLCNIC_BRDTYPE_P3P_10G_TP:
1464                 adapter->ahw->port_type = (adapter->portnum < 2) ?
1465                         QLCNIC_XGBE : QLCNIC_GBE;
1466                 break;
1467         default:
1468                 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1469                 adapter->ahw->port_type = QLCNIC_XGBE;
1470                 break;
1471         }
1472
1473         return 0;
1474 }
1475
1476 int
1477 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1478 {
1479         u32 wol_cfg;
1480
1481         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1482         if (wol_cfg & (1UL << adapter->portnum)) {
1483                 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1484                 if (wol_cfg & (1 << adapter->portnum))
1485                         return 1;
1486         }
1487
1488         return 0;
1489 }
1490
1491 int qlcnic_82xx_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1492 {
1493         struct qlcnic_nic_req   req;
1494         int rv;
1495         u64 word;
1496
1497         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1498         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1499
1500         word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1501         req.req_hdr = cpu_to_le64(word);
1502
1503         req.words[0] = cpu_to_le64(((u64)rate << 32) | adapter->portnum);
1504         req.words[1] = cpu_to_le64(state);
1505
1506         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1507         if (rv)
1508                 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1509
1510         return rv;
1511 }
1512
1513 int qlcnic_get_beacon_state(struct qlcnic_adapter *adapter, u8 *h_state)
1514 {
1515         struct qlcnic_cmd_args cmd;
1516         int err;
1517
1518         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_STATUS);
1519         if (!err) {
1520                 err = qlcnic_issue_cmd(adapter, &cmd);
1521                 if (!err)
1522                         *h_state = cmd.rsp.arg[1];
1523         }
1524         qlcnic_free_mbx_args(&cmd);
1525         return err;
1526 }
1527
1528 void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter)
1529 {
1530         void __iomem *msix_base_addr;
1531         u32 func;
1532         u32 msix_base;
1533
1534         pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func);
1535         msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE;
1536         msix_base = readl(msix_base_addr);
1537         func = (func - msix_base) / QLCNIC_MSIX_TBL_PGSIZE;
1538         adapter->ahw->pci_func = func;
1539 }
1540
1541 void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
1542                           loff_t offset, size_t size)
1543 {
1544         u32 data;
1545         u64 qmdata;
1546
1547         if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1548                 qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata);
1549                 memcpy(buf, &qmdata, size);
1550         } else {
1551                 data = QLCRD32(adapter, offset);
1552                 memcpy(buf, &data, size);
1553         }
1554 }
1555
1556 void qlcnic_82xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
1557                            loff_t offset, size_t size)
1558 {
1559         u32 data;
1560         u64 qmdata;
1561
1562         if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1563                 memcpy(&qmdata, buf, size);
1564                 qlcnic_pci_camqm_write_2M(adapter, offset, qmdata);
1565         } else {
1566                 memcpy(&data, buf, size);
1567                 QLCWR32(adapter, offset, data);
1568         }
1569 }
1570
1571 int qlcnic_82xx_api_lock(struct qlcnic_adapter *adapter)
1572 {
1573         return qlcnic_pcie_sem_lock(adapter, 5, 0);
1574 }
1575
1576 void qlcnic_82xx_api_unlock(struct qlcnic_adapter *adapter)
1577 {
1578         qlcnic_pcie_sem_unlock(adapter, 5);
1579 }
1580
1581 int qlcnic_82xx_shutdown(struct pci_dev *pdev)
1582 {
1583         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
1584         struct net_device *netdev = adapter->netdev;
1585         int retval;
1586
1587         netif_device_detach(netdev);
1588
1589         qlcnic_cancel_idc_work(adapter);
1590
1591         if (netif_running(netdev))
1592                 qlcnic_down(adapter, netdev);
1593
1594         qlcnic_clr_all_drv_state(adapter, 0);
1595
1596         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1597
1598         retval = pci_save_state(pdev);
1599         if (retval)
1600                 return retval;
1601
1602         if (qlcnic_wol_supported(adapter)) {
1603                 pci_enable_wake(pdev, PCI_D3cold, 1);
1604                 pci_enable_wake(pdev, PCI_D3hot, 1);
1605         }
1606
1607         return 0;
1608 }
1609
1610 int qlcnic_82xx_resume(struct qlcnic_adapter *adapter)
1611 {
1612         struct net_device *netdev = adapter->netdev;
1613         int err;
1614
1615         err = qlcnic_start_firmware(adapter);
1616         if (err) {
1617                 dev_err(&adapter->pdev->dev, "failed to start firmware\n");
1618                 return err;
1619         }
1620
1621         if (netif_running(netdev)) {
1622                 err = qlcnic_up(adapter, netdev);
1623                 if (!err)
1624                         qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1625         }
1626
1627         netif_device_attach(netdev);
1628         qlcnic_schedule_work(adapter, qlcnic_fw_poll_work, FW_POLL_DELAY);
1629         return err;
1630 }