2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
8 #include "qlcnic_sriov.h"
10 #include "qlcnic_hw.h"
12 /* Reset template definitions */
13 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000
14 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000
15 #define QLC_83XX_RESET_SEQ_VERSION 0x0101
17 #define QLC_83XX_OPCODE_NOP 0x0000
18 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001
19 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002
20 #define QLC_83XX_OPCODE_POLL_LIST 0x0004
21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008
22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010
23 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020
24 #define QLC_83XX_OPCODE_SEQ_END 0x0040
25 #define QLC_83XX_OPCODE_TMPL_END 0x0080
26 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100
28 /* EPORT control registers */
29 #define QLC_83XX_RESET_CONTROL 0x28084E50
30 #define QLC_83XX_RESET_REG 0x28084E60
31 #define QLC_83XX_RESET_PORT0 0x28084E70
32 #define QLC_83XX_RESET_PORT1 0x28084E80
33 #define QLC_83XX_RESET_PORT2 0x28084E90
34 #define QLC_83XX_RESET_PORT3 0x28084EA0
35 #define QLC_83XX_RESET_SRESHIM 0x28084EB0
36 #define QLC_83XX_RESET_EPGSHIM 0x28084EC0
37 #define QLC_83XX_RESET_ETHERPCS 0x28084ED0
39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
44 struct qlc_83xx_reset_hdr {
45 #if defined(__LITTLE_ENDIAN)
54 #elif defined(__BIG_ENDIAN)
66 /* Command entry header. */
67 struct qlc_83xx_entry_hdr {
68 #if defined(__LITTLE_ENDIAN)
73 #elif defined(__BIG_ENDIAN)
81 /* Generic poll command */
82 struct qlc_83xx_poll {
87 /* Read modify write command */
92 #if defined(__LITTLE_ENDIAN)
97 #elif defined(__BIG_ENDIAN)
105 /* Generic command with 2 DWORD */
106 struct qlc_83xx_entry {
111 /* Generic command with 4 DWORD */
112 struct qlc_83xx_quad_entry {
118 static const char *const qlc_83xx_idc_states[] = {
130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
134 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
144 cur = adapter->ahw->idc.curr_state;
145 prev = adapter->ahw->idc.prev_state;
147 dev_info(&adapter->pdev->dev,
148 "current state = %s, prev state = %s\n",
149 adapter->ahw->idc.name[cur],
150 adapter->ahw->idc.name[prev]);
153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
160 if (qlcnic_83xx_lock_driver(adapter))
164 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
165 val |= (adapter->portnum & 0xf);
168 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
170 seconds = jiffies / HZ;
173 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
174 adapter->ahw->idc.sec_counter = jiffies / HZ;
177 qlcnic_83xx_unlock_driver(adapter);
182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
186 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
187 val = val & ~(0x3 << (adapter->portnum * 2));
188 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
189 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
198 if (qlcnic_83xx_lock_driver(adapter))
202 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
204 val = val | QLC_83XX_IDC_MAJOR_VERSION;
205 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
208 qlcnic_83xx_unlock_driver(adapter);
214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
215 int status, int lock)
220 if (qlcnic_83xx_lock_driver(adapter))
224 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
227 val = val | (1 << adapter->portnum);
229 val = val & ~(1 << adapter->portnum);
231 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
232 qlcnic_83xx_idc_update_minor_version(adapter);
235 qlcnic_83xx_unlock_driver(adapter);
240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
246 version = val & 0xFF;
248 if (version != QLC_83XX_IDC_MAJOR_VERSION) {
249 dev_info(&adapter->pdev->dev,
250 "%s:mismatch. version 0x%x, expected version 0x%x\n",
251 __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
264 if (qlcnic_83xx_lock_driver(adapter))
268 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
269 /* Clear gracefull reset bit */
270 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
271 val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
272 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
275 qlcnic_83xx_unlock_driver(adapter);
280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
286 if (qlcnic_83xx_lock_driver(adapter))
290 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
292 val = val | (1 << adapter->portnum);
294 val = val & ~(1 << adapter->portnum);
295 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
298 qlcnic_83xx_unlock_driver(adapter);
303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
308 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
309 if (seconds <= time_limit)
316 * qlcnic_83xx_idc_check_reset_ack_reg
318 * @adapter: adapter structure
320 * Check ACK wait limit and clear the functions which failed to ACK
322 * Return 0 if all functions have acknowledged the reset request.
324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
327 u32 ack, presence, val;
329 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
330 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
331 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
332 dev_info(&adapter->pdev->dev,
333 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
334 if (!((ack & presence) == presence)) {
335 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
336 /* Clear functions which failed to ACK */
337 dev_info(&adapter->pdev->dev,
338 "%s: ACK wait exceeds time limit\n", __func__);
339 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
340 val = val & ~(ack ^ presence);
341 if (qlcnic_83xx_lock_driver(adapter))
343 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
344 dev_info(&adapter->pdev->dev,
345 "%s: updated drv presence reg = 0x%x\n",
347 qlcnic_83xx_unlock_driver(adapter);
354 dev_info(&adapter->pdev->dev,
355 "%s: Reset ACK received from all functions\n",
362 * qlcnic_83xx_idc_tx_soft_reset
364 * @adapter: adapter structure
366 * Handle context deletion and recreation request from transmit routine
368 * Returns -EBUSY or Success (0)
371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
373 struct net_device *netdev = adapter->netdev;
375 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
378 netif_device_detach(netdev);
379 qlcnic_down(adapter, netdev);
380 qlcnic_up(adapter, netdev);
381 netif_device_attach(netdev);
382 clear_bit(__QLCNIC_RESETTING, &adapter->state);
383 dev_err(&adapter->pdev->dev, "%s:\n", __func__);
389 * qlcnic_83xx_idc_detach_driver
391 * @adapter: adapter structure
392 * Detach net interface, stop TX and cleanup resources before the HW reset.
396 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
399 struct net_device *netdev = adapter->netdev;
401 netif_device_detach(netdev);
403 /* Disable mailbox interrupt */
404 qlcnic_83xx_disable_mbx_intr(adapter);
405 qlcnic_down(adapter, netdev);
406 for (i = 0; i < adapter->ahw->num_msix; i++) {
407 adapter->ahw->intr_tbl[i].id = i;
408 adapter->ahw->intr_tbl[i].enabled = 0;
409 adapter->ahw->intr_tbl[i].src = 0;
412 if (qlcnic_sriov_pf_check(adapter))
413 qlcnic_sriov_pf_reset(adapter);
417 * qlcnic_83xx_idc_attach_driver
419 * @adapter: adapter structure
421 * Re-attach and re-enable net interface
425 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
427 struct net_device *netdev = adapter->netdev;
429 if (netif_running(netdev)) {
430 if (qlcnic_up(adapter, netdev))
432 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
435 netif_device_attach(netdev);
438 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
442 if (qlcnic_83xx_lock_driver(adapter))
446 qlcnic_83xx_idc_clear_registers(adapter, 0);
447 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
449 qlcnic_83xx_unlock_driver(adapter);
451 qlcnic_83xx_idc_log_state_history(adapter);
452 dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
457 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
461 if (qlcnic_83xx_lock_driver(adapter))
465 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
468 qlcnic_83xx_unlock_driver(adapter);
473 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
477 if (qlcnic_83xx_lock_driver(adapter))
481 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
482 QLC_83XX_IDC_DEV_NEED_QUISCENT);
485 qlcnic_83xx_unlock_driver(adapter);
491 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
494 if (qlcnic_83xx_lock_driver(adapter))
498 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
499 QLC_83XX_IDC_DEV_NEED_RESET);
502 qlcnic_83xx_unlock_driver(adapter);
507 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
511 if (qlcnic_83xx_lock_driver(adapter))
515 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
517 qlcnic_83xx_unlock_driver(adapter);
523 * qlcnic_83xx_idc_find_reset_owner_id
525 * @adapter: adapter structure
527 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
528 * Within the same class, function with lowest PCI ID assumes ownership
530 * Returns: reset owner id or failure indication (-EIO)
533 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
535 u32 reg, reg1, reg2, i, j, owner, class;
537 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
538 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
539 owner = QLCNIC_TYPE_NIC;
545 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
548 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
555 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
556 if (owner == QLCNIC_TYPE_NIC)
557 owner = QLCNIC_TYPE_ISCSI;
558 else if (owner == QLCNIC_TYPE_ISCSI)
559 owner = QLCNIC_TYPE_FCOE;
560 else if (owner == QLCNIC_TYPE_FCOE)
566 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
571 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
575 ret = qlcnic_83xx_restart_hw(adapter);
578 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
580 qlcnic_83xx_idc_clear_registers(adapter, lock);
581 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
587 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
591 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
593 if (status & QLCNIC_RCODE_FATAL_ERROR) {
594 dev_err(&adapter->pdev->dev,
595 "peg halt status1=0x%x\n", status);
596 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
597 dev_err(&adapter->pdev->dev,
598 "On board active cooling fan failed. "
599 "Device has been halted.\n");
600 dev_err(&adapter->pdev->dev,
601 "Replace the adapter.\n");
609 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
613 /* register for NIC IDC AEN Events */
614 qlcnic_83xx_register_nic_idc_func(adapter, 1);
616 err = qlcnic_sriov_pf_reinit(adapter);
620 qlcnic_83xx_enable_mbx_intrpt(adapter);
622 if (qlcnic_83xx_configure_opmode(adapter)) {
623 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
627 if (adapter->nic_ops->init_driver(adapter)) {
628 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
632 qlcnic_set_drv_version(adapter);
633 qlcnic_83xx_idc_attach_driver(adapter);
638 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
640 struct qlcnic_hardware_context *ahw = adapter->ahw;
642 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
643 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
644 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
645 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
647 ahw->idc.quiesce_req = 0;
648 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
649 ahw->idc.err_code = 0;
650 ahw->idc.collect_dump = 0;
651 ahw->reset_context = 0;
652 adapter->tx_timeo_cnt = 0;
653 ahw->idc.delay_reset = 0;
655 clear_bit(__QLCNIC_RESETTING, &adapter->state);
659 * qlcnic_83xx_idc_ready_state_entry
661 * @adapter: adapter structure
663 * Perform ready state initialization, this routine will get invoked only
664 * once from READY state.
666 * Returns: Error code or Success(0)
669 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
671 struct qlcnic_hardware_context *ahw = adapter->ahw;
673 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
674 qlcnic_83xx_idc_update_idc_params(adapter);
675 /* Re-attach the device if required */
676 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
677 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
678 if (qlcnic_83xx_idc_reattach_driver(adapter))
687 * qlcnic_83xx_idc_vnic_pf_entry
689 * @adapter: adapter structure
691 * Ensure vNIC mode privileged function starts only after vNIC mode is
692 * enabled by management function.
693 * If vNIC mode is ready, start initialization.
698 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
701 struct qlcnic_hardware_context *ahw = adapter->ahw;
703 /* Privileged function waits till mgmt function enables VNIC mode */
704 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
705 if (state != QLCNIC_DEV_NPAR_OPER) {
706 if (!ahw->idc.vnic_wait_limit--) {
707 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
710 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
714 /* Perform one time initialization from ready state */
715 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
716 qlcnic_83xx_idc_update_idc_params(adapter);
718 /* If the previous state is UNKNOWN, device will be
719 already attached properly by Init routine*/
720 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
721 if (qlcnic_83xx_idc_reattach_driver(adapter))
724 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER;
725 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
732 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
734 adapter->ahw->idc.err_code = -EIO;
735 dev_err(&adapter->pdev->dev,
736 "%s: Device in unknown state\n", __func__);
741 * qlcnic_83xx_idc_cold_state
743 * @adapter: adapter structure
745 * If HW is up and running device will enter READY state.
746 * If firmware image from host needs to be loaded, device is
747 * forced to start with the file firmware image.
749 * Returns: Error code or Success(0)
752 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
754 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
755 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
757 if (qlcnic_load_fw_file) {
758 qlcnic_83xx_idc_restart_hw(adapter, 0);
760 if (qlcnic_83xx_check_hw_status(adapter)) {
761 qlcnic_83xx_idc_enter_failed_state(adapter, 0);
764 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
771 * qlcnic_83xx_idc_init_state
773 * @adapter: adapter structure
775 * Reset owner will restart the device from this state.
776 * Device will enter failed state if it remains
777 * in this state for more than DEV_INIT time limit.
779 * Returns: Error code or Success(0)
782 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
784 int timeout, ret = 0;
787 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
788 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
789 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
790 if (adapter->ahw->pci_func == owner)
791 ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
793 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
801 * qlcnic_83xx_idc_ready_state
803 * @adapter: adapter structure
805 * Perform IDC protocol specicifed actions after monitoring device state and
808 * Returns: Error code or Success(0)
811 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
814 struct qlcnic_hardware_context *ahw = adapter->ahw;
817 /* Perform NIC configuration based ready state entry actions */
818 if (ahw->idc.state_entry(adapter))
821 if (qlcnic_check_temp(adapter)) {
822 if (ahw->temp == QLCNIC_TEMP_PANIC) {
823 qlcnic_83xx_idc_check_fan_failure(adapter);
824 dev_err(&adapter->pdev->dev,
825 "Error: device temperature %d above limits\n",
827 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
828 set_bit(__QLCNIC_RESETTING, &adapter->state);
829 qlcnic_83xx_idc_detach_driver(adapter);
830 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
835 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
836 ret = qlcnic_83xx_check_heartbeat(adapter);
838 adapter->flags |= QLCNIC_FW_HANG;
839 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
840 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
841 set_bit(__QLCNIC_RESETTING, &adapter->state);
842 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
847 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
848 /* Move to need reset state and prepare for reset */
849 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
853 /* Check for soft reset request */
854 if (ahw->reset_context &&
855 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
856 adapter->ahw->reset_context = 0;
857 qlcnic_83xx_idc_tx_soft_reset(adapter);
861 /* Move to need quiesce state if requested */
862 if (adapter->ahw->idc.quiesce_req) {
863 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
864 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
872 * qlcnic_83xx_idc_need_reset_state
874 * @adapter: adapter structure
876 * Device will remain in this state until:
877 * Reset request ACK's are recieved from all the functions
878 * Wait time exceeds max time limit
880 * Returns: Error code or Success(0)
883 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
887 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
888 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
889 set_bit(__QLCNIC_RESETTING, &adapter->state);
890 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
891 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
892 qlcnic_83xx_disable_vnic_mode(adapter, 1);
894 if (qlcnic_check_diag_status(adapter)) {
895 dev_info(&adapter->pdev->dev,
896 "%s: Wait for diag completion\n", __func__);
897 adapter->ahw->idc.delay_reset = 1;
900 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
901 qlcnic_83xx_idc_detach_driver(adapter);
905 if (qlcnic_check_diag_status(adapter)) {
906 dev_info(&adapter->pdev->dev,
907 "%s: Wait for diag completion\n", __func__);
910 if (adapter->ahw->idc.delay_reset) {
911 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
912 qlcnic_83xx_idc_detach_driver(adapter);
913 adapter->ahw->idc.delay_reset = 0;
916 /* Check for ACK from other functions */
917 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
919 dev_info(&adapter->pdev->dev,
920 "%s: Waiting for reset ACK\n", __func__);
925 /* Transit to INIT state and restart the HW */
926 qlcnic_83xx_idc_enter_init_state(adapter, 1);
931 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
933 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
937 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
939 dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
940 clear_bit(__QLCNIC_RESETTING, &adapter->state);
941 adapter->ahw->idc.err_code = -EIO;
946 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
948 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
952 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
957 cur = adapter->ahw->idc.curr_state;
958 prev = adapter->ahw->idc.prev_state;
961 if ((next < QLC_83XX_IDC_DEV_COLD) ||
962 (next > QLC_83XX_IDC_DEV_QUISCENT)) {
963 dev_err(&adapter->pdev->dev,
964 "%s: curr %d, prev %d, next state %d is invalid\n",
965 __func__, cur, prev, state);
969 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
970 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
971 if ((next != QLC_83XX_IDC_DEV_COLD) &&
972 (next != QLC_83XX_IDC_DEV_READY)) {
973 dev_err(&adapter->pdev->dev,
974 "%s: failed, cur %d prev %d next %d\n",
975 __func__, cur, prev, next);
980 if (next == QLC_83XX_IDC_DEV_INIT) {
981 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
982 (prev != QLC_83XX_IDC_DEV_COLD) &&
983 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
984 dev_err(&adapter->pdev->dev,
985 "%s: failed, cur %d prev %d next %d\n",
986 __func__, cur, prev, next);
994 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
996 if (adapter->fhash.fnum)
997 qlcnic_prune_lb_filters(adapter);
1001 * qlcnic_83xx_idc_poll_dev_state
1003 * @work: kernel work queue structure used to schedule the function
1005 * Poll device state periodically and perform state specific
1006 * actions defined by Inter Driver Communication (IDC) protocol.
1011 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
1013 struct qlcnic_adapter *adapter;
1016 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1017 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1019 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1020 qlcnic_83xx_idc_log_state_history(adapter);
1021 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1023 adapter->ahw->idc.curr_state = state;
1026 switch (adapter->ahw->idc.curr_state) {
1027 case QLC_83XX_IDC_DEV_READY:
1028 qlcnic_83xx_idc_ready_state(adapter);
1030 case QLC_83XX_IDC_DEV_NEED_RESET:
1031 qlcnic_83xx_idc_need_reset_state(adapter);
1033 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1034 qlcnic_83xx_idc_need_quiesce_state(adapter);
1036 case QLC_83XX_IDC_DEV_FAILED:
1037 qlcnic_83xx_idc_failed_state(adapter);
1039 case QLC_83XX_IDC_DEV_INIT:
1040 qlcnic_83xx_idc_init_state(adapter);
1042 case QLC_83XX_IDC_DEV_QUISCENT:
1043 qlcnic_83xx_idc_quiesce_state(adapter);
1046 qlcnic_83xx_idc_unknown_state(adapter);
1049 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1050 qlcnic_83xx_periodic_tasks(adapter);
1052 /* Re-schedule the function */
1053 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1054 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1055 adapter->ahw->idc.delay);
1058 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1060 u32 idc_params, val;
1062 if (qlcnic_83xx_lockless_flash_read32(adapter,
1063 QLC_83XX_IDC_FLASH_PARAM_ADDR,
1064 (u8 *)&idc_params, 1)) {
1065 dev_info(&adapter->pdev->dev,
1066 "%s:failed to get IDC params from flash\n", __func__);
1067 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1068 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1070 adapter->dev_init_timeo = idc_params & 0xFFFF;
1071 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1074 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1075 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1076 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1077 adapter->ahw->idc.err_code = 0;
1078 adapter->ahw->idc.collect_dump = 0;
1079 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1081 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1082 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
1083 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1085 /* Check if reset recovery is disabled */
1086 if (!qlcnic_auto_fw_reset) {
1087 /* Propagate do not reset request to other functions */
1088 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1089 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1090 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1095 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1099 if (qlcnic_83xx_lock_driver(adapter))
1102 /* Clear driver lock register */
1103 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1104 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1105 qlcnic_83xx_unlock_driver(adapter);
1109 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1110 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1111 qlcnic_83xx_unlock_driver(adapter);
1115 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1116 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1117 QLC_83XX_IDC_DEV_COLD);
1118 state = QLC_83XX_IDC_DEV_COLD;
1121 adapter->ahw->idc.curr_state = state;
1122 /* First to load function should cold boot the device */
1123 if (state == QLC_83XX_IDC_DEV_COLD)
1124 qlcnic_83xx_idc_cold_state_handler(adapter);
1126 /* Check if reset recovery is enabled */
1127 if (qlcnic_auto_fw_reset) {
1128 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1129 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1130 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1133 qlcnic_83xx_unlock_driver(adapter);
1138 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1142 qlcnic_83xx_setup_idc_parameters(adapter);
1144 if (qlcnic_83xx_get_reset_instruction_template(adapter))
1147 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1148 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1151 if (qlcnic_83xx_idc_check_major_version(adapter))
1155 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1160 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1165 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1166 usleep_range(10000, 11000);
1168 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1171 if (id == adapter->portnum) {
1172 dev_err(&adapter->pdev->dev,
1173 "%s: wait for lock recovery.. %d\n", __func__, id);
1175 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1179 /* Clear driver presence bit */
1180 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1181 val = val & ~(1 << adapter->portnum);
1182 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1183 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1184 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1186 cancel_delayed_work_sync(&adapter->fw_work);
1189 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1193 if (qlcnic_83xx_lock_driver(adapter)) {
1194 dev_err(&adapter->pdev->dev,
1195 "%s:failed, please retry\n", __func__);
1199 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1200 if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1201 !qlcnic_auto_fw_reset) {
1202 dev_err(&adapter->pdev->dev,
1203 "%s:failed, device in non reset mode\n", __func__);
1204 qlcnic_83xx_unlock_driver(adapter);
1208 if (key == QLCNIC_FORCE_FW_RESET) {
1209 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1210 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1211 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1212 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1213 adapter->ahw->idc.collect_dump = 1;
1216 qlcnic_83xx_unlock_driver(adapter);
1220 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1227 src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1228 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1229 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1231 /* alignment check */
1233 size = (size + 16) & ~0xF;
1235 p_cache = kzalloc(size, GFP_KERNEL);
1236 if (p_cache == NULL)
1239 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1240 size / sizeof(u32));
1245 /* 16 byte write to MS memory */
1246 ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1257 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1265 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1266 size = (adapter->ahw->fw_info.fw->size & ~0xF);
1267 p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1270 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1271 (u32 *)p_cache, size / 16);
1273 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1274 release_firmware(adapter->ahw->fw_info.fw);
1275 adapter->ahw->fw_info.fw = NULL;
1279 /* alignment check */
1280 if (adapter->ahw->fw_info.fw->size & 0xF) {
1282 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1283 data[i] = adapter->ahw->fw_info.fw->data[size + i];
1286 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1289 dev_err(&adapter->pdev->dev,
1290 "MS memory write failed\n");
1291 release_firmware(adapter->ahw->fw_info.fw);
1292 adapter->ahw->fw_info.fw = NULL;
1296 release_firmware(adapter->ahw->fw_info.fw);
1297 adapter->ahw->fw_info.fw = NULL;
1302 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1305 u32 val = 0, val1 = 0, reg = 0;
1307 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG);
1308 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1310 for (j = 0; j < 2; j++) {
1312 dev_info(&adapter->pdev->dev,
1313 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1314 reg = QLC_83XX_PORT0_THRESHOLD;
1315 } else if (j == 1) {
1316 dev_info(&adapter->pdev->dev,
1317 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1318 reg = QLC_83XX_PORT1_THRESHOLD;
1320 for (i = 0; i < 8; i++) {
1321 val = QLCRD32(adapter, reg + (i * 0x4));
1322 dev_info(&adapter->pdev->dev, "0x%x ", val);
1324 dev_info(&adapter->pdev->dev, "\n");
1327 for (j = 0; j < 2; j++) {
1329 dev_info(&adapter->pdev->dev,
1330 "Port 0 RxB TC Max Cell Registers[4..1]:");
1331 reg = QLC_83XX_PORT0_TC_MC_REG;
1332 } else if (j == 1) {
1333 dev_info(&adapter->pdev->dev,
1334 "Port 1 RxB TC Max Cell Registers[4..1]:");
1335 reg = QLC_83XX_PORT1_TC_MC_REG;
1337 for (i = 0; i < 4; i++) {
1338 val = QLCRD32(adapter, reg + (i * 0x4));
1339 dev_info(&adapter->pdev->dev, "0x%x ", val);
1341 dev_info(&adapter->pdev->dev, "\n");
1344 for (j = 0; j < 2; j++) {
1346 dev_info(&adapter->pdev->dev,
1347 "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1348 reg = QLC_83XX_PORT0_TC_STATS;
1349 } else if (j == 1) {
1350 dev_info(&adapter->pdev->dev,
1351 "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1352 reg = QLC_83XX_PORT1_TC_STATS;
1354 for (i = 7; i >= 0; i--) {
1355 val = QLCRD32(adapter, reg);
1356 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */
1357 QLCWR32(adapter, reg, (val | (i << 29)));
1358 val = QLCRD32(adapter, reg);
1359 dev_info(&adapter->pdev->dev, "0x%x ", val);
1361 dev_info(&adapter->pdev->dev, "\n");
1364 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD);
1365 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD);
1366 dev_info(&adapter->pdev->dev,
1367 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1372 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1376 if (qlcnic_83xx_lock_driver(adapter)) {
1377 dev_err(&adapter->pdev->dev,
1378 "%s:failed to acquire driver lock\n", __func__);
1382 qlcnic_83xx_dump_pause_control_regs(adapter);
1383 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1385 for (j = 0; j < 2; j++) {
1387 reg = QLC_83XX_PORT0_THRESHOLD;
1389 reg = QLC_83XX_PORT1_THRESHOLD;
1391 for (i = 0; i < 8; i++)
1392 QLCWR32(adapter, reg + (i * 0x4), 0x0);
1395 for (j = 0; j < 2; j++) {
1397 reg = QLC_83XX_PORT0_TC_MC_REG;
1399 reg = QLC_83XX_PORT1_TC_MC_REG;
1401 for (i = 0; i < 4; i++)
1402 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1405 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1406 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1407 dev_info(&adapter->pdev->dev,
1408 "Disabled pause frames successfully on all ports\n");
1409 qlcnic_83xx_unlock_driver(adapter);
1412 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1414 QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1415 QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1416 QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1417 QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1418 QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1419 QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1420 QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1421 QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1422 QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1425 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1427 u32 heartbeat, peg_status;
1428 int retries, ret = -EIO;
1430 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1431 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1432 QLCNIC_PEG_ALIVE_COUNTER);
1435 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1436 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1437 QLCNIC_PEG_ALIVE_COUNTER);
1438 if (heartbeat != p_dev->heartbeat) {
1439 ret = QLCNIC_RCODE_SUCCESS;
1442 } while (--retries);
1445 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1446 qlcnic_83xx_take_eport_out_of_reset(p_dev);
1447 qlcnic_83xx_disable_pause_frames(p_dev);
1448 peg_status = QLC_SHARED_REG_RD32(p_dev,
1449 QLCNIC_PEG_HALT_STATUS1);
1450 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1451 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1452 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1453 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1454 "PEG_NET_4_PC: 0x%x\n", peg_status,
1455 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1456 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0),
1457 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1),
1458 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2),
1459 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3),
1460 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4));
1462 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1463 dev_err(&p_dev->pdev->dev,
1464 "Device is being reset err code 0x00006700.\n");
1470 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1472 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1476 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1477 if (val == QLC_83XX_CMDPEG_COMPLETE)
1479 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1480 } while (--retries);
1482 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1486 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1490 err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1494 err = qlcnic_83xx_check_heartbeat(p_dev);
1501 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1502 int duration, u32 mask, u32 status)
1508 value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1509 retries = duration / 10;
1512 if ((value & mask) != status) {
1514 msleep(duration / 10);
1515 value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1520 } while (retries--);
1522 if (timeout_error) {
1523 p_dev->ahw->reset.seq_error++;
1524 dev_err(&p_dev->pdev->dev,
1525 "%s: Timeout Err, entry_num = %d\n",
1526 __func__, p_dev->ahw->reset.seq_index);
1527 dev_err(&p_dev->pdev->dev,
1528 "0x%08x 0x%08x 0x%08x\n",
1529 value, mask, status);
1532 return timeout_error;
1535 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1538 u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1539 int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1545 sum = (sum & 0xFFFF) + (sum >> 16);
1550 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1555 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1557 struct qlcnic_hardware_context *ahw = p_dev->ahw;
1558 u32 addr, count, prev_ver, curr_ver;
1561 if (ahw->reset.buff != NULL) {
1562 prev_ver = p_dev->fw_version;
1563 curr_ver = qlcnic_83xx_get_fw_version(p_dev);
1564 if (curr_ver > prev_ver)
1565 kfree(ahw->reset.buff);
1570 ahw->reset.seq_error = 0;
1571 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1572 if (p_dev->ahw->reset.buff == NULL)
1575 p_buff = p_dev->ahw->reset.buff;
1576 addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1577 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1579 /* Copy template header from flash */
1580 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1581 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1584 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1585 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1586 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1587 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1589 /* Copy rest of the template */
1590 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1591 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1595 if (qlcnic_83xx_reset_template_checksum(p_dev))
1597 /* Get Stop, Start and Init command offsets */
1598 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1599 ahw->reset.start_offset = ahw->reset.buff +
1600 ahw->reset.hdr->start_offset;
1601 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1605 /* Read Write HW register command */
1606 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1607 u32 raddr, u32 waddr)
1611 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1612 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1615 /* Read Modify Write HW register command */
1616 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1617 u32 raddr, u32 waddr,
1618 struct qlc_83xx_rmw *p_rmw_hdr)
1622 if (p_rmw_hdr->index_a)
1623 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1625 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1627 value &= p_rmw_hdr->mask;
1628 value <<= p_rmw_hdr->shl;
1629 value >>= p_rmw_hdr->shr;
1630 value |= p_rmw_hdr->or_value;
1631 value ^= p_rmw_hdr->xor_value;
1632 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1635 /* Write HW register command */
1636 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1637 struct qlc_83xx_entry_hdr *p_hdr)
1640 struct qlc_83xx_entry *entry;
1642 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1643 sizeof(struct qlc_83xx_entry_hdr));
1645 for (i = 0; i < p_hdr->count; i++, entry++) {
1646 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1649 udelay((u32)(p_hdr->delay));
1653 /* Read and Write instruction */
1654 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1655 struct qlc_83xx_entry_hdr *p_hdr)
1658 struct qlc_83xx_entry *entry;
1660 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1661 sizeof(struct qlc_83xx_entry_hdr));
1663 for (i = 0; i < p_hdr->count; i++, entry++) {
1664 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1667 udelay((u32)(p_hdr->delay));
1671 /* Poll HW register command */
1672 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1673 struct qlc_83xx_entry_hdr *p_hdr)
1676 struct qlc_83xx_entry *entry;
1677 struct qlc_83xx_poll *poll;
1679 unsigned long arg1, arg2;
1681 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1682 sizeof(struct qlc_83xx_entry_hdr));
1684 entry = (struct qlc_83xx_entry *)((char *)poll +
1685 sizeof(struct qlc_83xx_poll));
1686 delay = (long)p_hdr->delay;
1689 for (i = 0; i < p_hdr->count; i++, entry++)
1690 qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1694 for (i = 0; i < p_hdr->count; i++, entry++) {
1698 if (qlcnic_83xx_poll_reg(p_dev,
1702 qlcnic_83xx_rd_reg_indirect(p_dev,
1704 qlcnic_83xx_rd_reg_indirect(p_dev,
1712 /* Poll and write HW register command */
1713 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1714 struct qlc_83xx_entry_hdr *p_hdr)
1718 struct qlc_83xx_quad_entry *entry;
1719 struct qlc_83xx_poll *poll;
1721 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1722 sizeof(struct qlc_83xx_entry_hdr));
1723 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1724 sizeof(struct qlc_83xx_poll));
1725 delay = (long)p_hdr->delay;
1727 for (i = 0; i < p_hdr->count; i++, entry++) {
1728 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1730 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1733 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1734 poll->mask, poll->status);
1738 /* Read Modify Write register command */
1739 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1740 struct qlc_83xx_entry_hdr *p_hdr)
1743 struct qlc_83xx_entry *entry;
1744 struct qlc_83xx_rmw *rmw_hdr;
1746 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1747 sizeof(struct qlc_83xx_entry_hdr));
1749 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1750 sizeof(struct qlc_83xx_rmw));
1752 for (i = 0; i < p_hdr->count; i++, entry++) {
1753 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1754 entry->arg2, rmw_hdr);
1756 udelay((u32)(p_hdr->delay));
1760 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1763 mdelay((u32)((long)p_hdr->delay));
1766 /* Read and poll register command */
1767 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1768 struct qlc_83xx_entry_hdr *p_hdr)
1772 struct qlc_83xx_quad_entry *entry;
1773 struct qlc_83xx_poll *poll;
1776 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1777 sizeof(struct qlc_83xx_entry_hdr));
1779 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1780 sizeof(struct qlc_83xx_poll));
1781 delay = (long)p_hdr->delay;
1783 for (i = 0; i < p_hdr->count; i++, entry++) {
1784 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1787 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1788 poll->mask, poll->status)){
1789 index = p_dev->ahw->reset.array_index;
1790 addr = entry->dr_addr;
1791 j = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1792 p_dev->ahw->reset.array[index++] = j;
1794 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1795 p_dev->ahw->reset.array_index = 1;
1801 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1803 p_dev->ahw->reset.seq_end = 1;
1806 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1808 p_dev->ahw->reset.template_end = 1;
1809 if (p_dev->ahw->reset.seq_error == 0)
1810 dev_err(&p_dev->pdev->dev,
1811 "HW restart process completed successfully.\n");
1813 dev_err(&p_dev->pdev->dev,
1814 "HW restart completed with timeout errors.\n");
1818 * qlcnic_83xx_exec_template_cmd
1820 * @p_dev: adapter structure
1821 * @p_buff: Poiter to instruction template
1823 * Template provides instructions to stop, restart and initalize firmware.
1824 * These instructions are abstracted as a series of read, write and
1825 * poll operations on hardware registers. Register information and operation
1826 * specifics are not exposed to the driver. Driver reads the template from
1827 * flash and executes the instructions located at pre-defined offsets.
1831 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1835 struct qlc_83xx_entry_hdr *p_hdr;
1836 char *entry = p_buff;
1838 p_dev->ahw->reset.seq_end = 0;
1839 p_dev->ahw->reset.template_end = 0;
1840 entries = p_dev->ahw->reset.hdr->entries;
1841 index = p_dev->ahw->reset.seq_index;
1843 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1844 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1846 switch (p_hdr->cmd) {
1847 case QLC_83XX_OPCODE_NOP:
1849 case QLC_83XX_OPCODE_WRITE_LIST:
1850 qlcnic_83xx_write_list(p_dev, p_hdr);
1852 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1853 qlcnic_83xx_read_write_list(p_dev, p_hdr);
1855 case QLC_83XX_OPCODE_POLL_LIST:
1856 qlcnic_83xx_poll_list(p_dev, p_hdr);
1858 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1859 qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1861 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1862 qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1864 case QLC_83XX_OPCODE_SEQ_PAUSE:
1865 qlcnic_83xx_pause(p_hdr);
1867 case QLC_83XX_OPCODE_SEQ_END:
1868 qlcnic_83xx_seq_end(p_dev);
1870 case QLC_83XX_OPCODE_TMPL_END:
1871 qlcnic_83xx_template_end(p_dev);
1873 case QLC_83XX_OPCODE_POLL_READ_LIST:
1874 qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1877 dev_err(&p_dev->pdev->dev,
1878 "%s: Unknown opcode 0x%04x in template %d\n",
1879 __func__, p_hdr->cmd, index);
1882 entry += p_hdr->size;
1884 p_dev->ahw->reset.seq_index = index;
1887 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1889 p_dev->ahw->reset.seq_index = 0;
1891 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1892 if (p_dev->ahw->reset.seq_end != 1)
1893 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1896 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1898 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1899 if (p_dev->ahw->reset.template_end != 1)
1900 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1903 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1905 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1906 if (p_dev->ahw->reset.seq_end != 1)
1907 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1910 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1914 if (request_firmware(&adapter->ahw->fw_info.fw,
1915 QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) {
1916 dev_err(&adapter->pdev->dev,
1917 "No file FW image, loading flash FW image.\n");
1918 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1919 QLC_83XX_BOOT_FROM_FLASH);
1921 if (qlcnic_83xx_copy_fw_file(adapter))
1923 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1924 QLC_83XX_BOOT_FROM_FILE);
1930 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1935 qlcnic_83xx_stop_hw(adapter);
1937 /* Collect FW register dump if required */
1938 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1939 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1940 qlcnic_dump_fw(adapter);
1941 qlcnic_83xx_init_hw(adapter);
1943 if (qlcnic_83xx_copy_bootloader(adapter))
1945 /* Boot either flash image or firmware image from host file system */
1946 if (qlcnic_load_fw_file) {
1947 if (qlcnic_83xx_load_fw_image_from_host(adapter))
1950 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1951 QLC_83XX_BOOT_FROM_FLASH);
1954 qlcnic_83xx_start_hw(adapter);
1955 if (qlcnic_83xx_check_hw_status(adapter))
1962 * qlcnic_83xx_config_default_opmode
1964 * @adapter: adapter structure
1966 * Configure default driver operating mode
1968 * Returns: Error code or Success(0)
1970 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
1973 struct qlcnic_hardware_context *ahw = adapter->ahw;
1975 qlcnic_get_func_no(adapter);
1976 op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
1978 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
1979 op_mode = QLC_83XX_DEFAULT_OPMODE;
1981 if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
1982 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
1983 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
1991 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
1994 struct qlcnic_info nic_info;
1995 struct qlcnic_hardware_context *ahw = adapter->ahw;
1997 memset(&nic_info, 0, sizeof(struct qlcnic_info));
1998 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
2002 ahw->physical_port = (u8) nic_info.phys_port;
2003 ahw->switch_mode = nic_info.switch_mode;
2004 ahw->max_tx_ques = nic_info.max_tx_ques;
2005 ahw->max_rx_ques = nic_info.max_rx_ques;
2006 ahw->capabilities = nic_info.capabilities;
2007 ahw->max_mac_filters = nic_info.max_mac_filters;
2008 ahw->max_mtu = nic_info.max_mtu;
2010 /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
2011 * set in case device is SRIOV capable. VNIC and SRIOV are mutually
2012 * exclusive. So in case of sriov capable device load driver in
2015 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
2016 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2017 return ahw->nic_mode;
2020 if (ahw->capabilities & BIT_23)
2021 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
2023 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2025 return ahw->nic_mode;
2028 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
2032 ret = qlcnic_83xx_get_nic_configuration(adapter);
2036 if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
2037 if (qlcnic_83xx_config_vnic_opmode(adapter))
2039 } else if (ret == QLC_83XX_DEFAULT_MODE) {
2040 if (qlcnic_83xx_config_default_opmode(adapter))
2047 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2049 struct qlcnic_hardware_context *ahw = adapter->ahw;
2051 if (ahw->port_type == QLCNIC_XGBE) {
2052 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2053 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2054 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2055 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2057 } else if (ahw->port_type == QLCNIC_GBE) {
2058 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2059 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2060 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2061 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2063 adapter->num_txd = MAX_CMD_DESCRIPTORS;
2064 adapter->max_rds_rings = MAX_RDS_RINGS;
2067 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2071 qlcnic_83xx_get_minidump_template(adapter);
2072 if (qlcnic_83xx_get_port_info(adapter))
2075 qlcnic_83xx_config_buff_descriptors(adapter);
2076 adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2077 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2079 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2080 adapter->ahw->fw_hal_version);
2085 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2086 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2088 struct qlcnic_cmd_args cmd;
2089 u32 presence_mask, audit_mask;
2092 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2093 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2095 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2096 status = qlcnic_alloc_mbx_args(&cmd, adapter,
2097 QLCNIC_CMD_STOP_NIC_FUNC);
2101 cmd.req.arg[1] = BIT_31;
2102 status = qlcnic_issue_cmd(adapter, &cmd);
2104 dev_err(&adapter->pdev->dev,
2105 "Failed to clean up the function resources\n");
2106 qlcnic_free_mbx_args(&cmd);
2110 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2112 struct qlcnic_hardware_context *ahw = adapter->ahw;
2114 if (qlcnic_sriov_vf_check(adapter))
2115 return qlcnic_sriov_vf_init(adapter, pci_using_dac);
2117 if (qlcnic_83xx_check_hw_status(adapter))
2120 /* Initilaize 83xx mailbox spinlock */
2121 spin_lock_init(&ahw->mbx_lock);
2123 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
2124 qlcnic_83xx_clear_function_resources(adapter);
2126 /* register for NIC IDC AEN Events */
2127 qlcnic_83xx_register_nic_idc_func(adapter, 1);
2129 if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2130 qlcnic_83xx_read_flash_mfg_id(adapter);
2132 if (qlcnic_83xx_idc_init(adapter))
2135 /* Configure default, SR-IOV or Virtual NIC mode of operation */
2136 if (qlcnic_83xx_configure_opmode(adapter))
2139 /* Perform operating mode specific initialization */
2140 if (adapter->nic_ops->init_driver(adapter))
2143 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2145 /* Periodically monitor device status */
2146 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2148 return adapter->ahw->idc.err_code;