Pileus Git - ~andy/linux/blob - drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic_sriov.h"
   9 #include "qlcnic.h"
  10 #include "qlcnic_hw.h"
  11
  12 /* Reset template definitions */
  13 #define QLC_83XX_RESTART_TEMPLATE_SIZE          0x2000
  14 #define QLC_83XX_RESET_TEMPLATE_ADDR            0x4F0000
  15 #define QLC_83XX_RESET_SEQ_VERSION              0x0101
  16
  17 #define QLC_83XX_OPCODE_NOP                     0x0000
  18 #define QLC_83XX_OPCODE_WRITE_LIST              0x0001
  19 #define QLC_83XX_OPCODE_READ_WRITE_LIST         0x0002
  20 #define QLC_83XX_OPCODE_POLL_LIST               0x0004
  21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST         0x0008
  22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE       0x0010
  23 #define QLC_83XX_OPCODE_SEQ_PAUSE               0x0020
  24 #define QLC_83XX_OPCODE_SEQ_END                 0x0040
  25 #define QLC_83XX_OPCODE_TMPL_END                0x0080
  26 #define QLC_83XX_OPCODE_POLL_READ_LIST          0x0100
  27
  28 /* EPORT control registers */
  29 #define QLC_83XX_RESET_CONTROL                  0x28084E50
  30 #define QLC_83XX_RESET_REG                      0x28084E60
  31 #define QLC_83XX_RESET_PORT0                    0x28084E70
  32 #define QLC_83XX_RESET_PORT1                    0x28084E80
  33 #define QLC_83XX_RESET_PORT2                    0x28084E90
  34 #define QLC_83XX_RESET_PORT3                    0x28084EA0
  35 #define QLC_83XX_RESET_SRESHIM                  0x28084EB0
  36 #define QLC_83XX_RESET_EPGSHIM                  0x28084EC0
  37 #define QLC_83XX_RESET_ETHERPCS                 0x28084ED0
  38
  39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
  40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
  41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
  42
  43 /* Template header */
  44 struct qlc_83xx_reset_hdr {
  45 #if defined(__LITTLE_ENDIAN)
  46         u16     version;
  47         u16     signature;
  48         u16     size;
  49         u16     entries;
  50         u16     hdr_size;
  51         u16     checksum;
  52         u16     init_offset;
  53         u16     start_offset;
  54 #elif defined(__BIG_ENDIAN)
  55         u16     signature;
  56         u16     version;
  57         u16     entries;
  58         u16     size;
  59         u16     checksum;
  60         u16     hdr_size;
  61         u16     start_offset;
  62         u16     init_offset;
  63 #endif
  64 } __packed;
  65
  66 /* Command entry header. */
  67 struct qlc_83xx_entry_hdr {
  68 #if defined(__LITTLE_ENDIAN)
  69         u16     cmd;
  70         u16     size;
  71         u16     count;
  72         u16     delay;
  73 #elif defined(__BIG_ENDIAN)
  74         u16     size;
  75         u16     cmd;
  76         u16     delay;
  77         u16     count;
  78 #endif
  79 } __packed;
  80
  81 /* Generic poll command */
  82 struct qlc_83xx_poll {
  83         u32     mask;
  84         u32     status;
  85 } __packed;
  86
  87 /* Read modify write command */
  88 struct qlc_83xx_rmw {
  89         u32     mask;
  90         u32     xor_value;
  91         u32     or_value;
  92 #if defined(__LITTLE_ENDIAN)
  93         u8      shl;
  94         u8      shr;
  95         u8      index_a;
  96         u8      rsvd;
  97 #elif defined(__BIG_ENDIAN)
  98         u8      rsvd;
  99         u8      index_a;
 100         u8      shr;
 101         u8      shl;
 102 #endif
 103 } __packed;
 104
 105 /* Generic command with 2 DWORD */
 106 struct qlc_83xx_entry {
 107         u32 arg1;
 108         u32 arg2;
 109 } __packed;
 110
 111 /* Generic command with 4 DWORD */
 112 struct qlc_83xx_quad_entry {
 113         u32 dr_addr;
 114         u32 dr_value;
 115         u32 ar_addr;
 116         u32 ar_value;
 117 } __packed;
 118 static const char *const qlc_83xx_idc_states[] = {
 119         "Unknown",
 120         "Cold",
 121         "Init",
 122         "Ready",
 123         "Need Reset",
 124         "Need Quiesce",
 125         "Failed",
 126         "Quiesce"
 127 };
 128
 129 static int
 130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
 131 {
 132         u32 val;
 133
 134         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 135         if ((val & 0xFFFF))
 136                 return 1;
 137         else
 138                 return 0;
 139 }
 140
 141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
 142 {
 143         u32 cur, prev;
 144         cur = adapter->ahw->idc.curr_state;
 145         prev = adapter->ahw->idc.prev_state;
 146
 147         dev_info(&adapter->pdev->dev,
 148                  "current state  = %s,  prev state = %s\n",
 149                  adapter->ahw->idc.name[cur],
 150                  adapter->ahw->idc.name[prev]);
 151 }
 152
 153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
 154                                             u8 mode, int lock)
 155 {
 156         u32 val;
 157         int seconds;
 158
 159         if (lock) {
 160                 if (qlcnic_83xx_lock_driver(adapter))
 161                         return -EBUSY;
 162         }
 163
 164         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
 165         val |= (adapter->portnum & 0xf);
 166         val |= mode << 7;
 167         if (mode)
 168                 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 169         else
 170                 seconds = jiffies / HZ;
 171
 172         val |= seconds << 8;
 173         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
 174         adapter->ahw->idc.sec_counter = jiffies / HZ;
 175
 176         if (lock)
 177                 qlcnic_83xx_unlock_driver(adapter);
 178
 179         return 0;
 180 }
 181
 182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
 183 {
 184         u32 val;
 185
 186         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
 187         val = val & ~(0x3 << (adapter->portnum * 2));
 188         val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
 189         QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
 190 }
 191
 192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
 193                                                 int lock)
 194 {
 195         u32 val;
 196
 197         if (lock) {
 198                 if (qlcnic_83xx_lock_driver(adapter))
 199                         return -EBUSY;
 200         }
 201
 202         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 203         val = val & ~0xFF;
 204         val = val | QLC_83XX_IDC_MAJOR_VERSION;
 205         QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
 206
 207         if (lock)
 208                 qlcnic_83xx_unlock_driver(adapter);
 209
 210         return 0;
 211 }
 212
 213 static int
 214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
 215                                         int status, int lock)
 216 {
 217         u32 val;
 218
 219         if (lock) {
 220                 if (qlcnic_83xx_lock_driver(adapter))
 221                         return -EBUSY;
 222         }
 223
 224         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 225
 226         if (status)
 227                 val = val | (1 << adapter->portnum);
 228         else
 229                 val = val & ~(1 << adapter->portnum);
 230
 231         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 232         qlcnic_83xx_idc_update_minor_version(adapter);
 233
 234         if (lock)
 235                 qlcnic_83xx_unlock_driver(adapter);
 236
 237         return 0;
 238 }
 239
 240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
 241 {
 242         u32 val;
 243         u8 version;
 244
 245         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 246         version = val & 0xFF;
 247
 248         if (version != QLC_83XX_IDC_MAJOR_VERSION) {
 249                 dev_info(&adapter->pdev->dev,
 250                          "%s:mismatch. version 0x%x, expected version 0x%x\n",
 251                          __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
 252                 return -EIO;
 253         }
 254
 255         return 0;
 256 }
 257
 258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
 259                                            int lock)
 260 {
 261         u32 val;
 262
 263         if (lock) {
 264                 if (qlcnic_83xx_lock_driver(adapter))
 265                         return -EBUSY;
 266         }
 267
 268         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
 269         /* Clear gracefull reset bit */
 270         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 271         val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
 272         QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
 273
 274         if (lock)
 275                 qlcnic_83xx_unlock_driver(adapter);
 276
 277         return 0;
 278 }
 279
 280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
 281                                               int flag, int lock)
 282 {
 283         u32 val;
 284
 285         if (lock) {
 286                 if (qlcnic_83xx_lock_driver(adapter))
 287                         return -EBUSY;
 288         }
 289
 290         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 291         if (flag)
 292                 val = val | (1 << adapter->portnum);
 293         else
 294                 val = val & ~(1 << adapter->portnum);
 295         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
 296
 297         if (lock)
 298                 qlcnic_83xx_unlock_driver(adapter);
 299
 300         return 0;
 301 }
 302
 303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
 304                                          int time_limit)
 305 {
 306         u64 seconds;
 307
 308         seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 309         if (seconds <= time_limit)
 310                 return 0;
 311         else
 312                 return -EBUSY;
 313 }
 314
 315 /**
 316  * qlcnic_83xx_idc_check_reset_ack_reg
 317  *
 318  * @adapter: adapter structure
 319  *
 320  * Check ACK wait limit and clear the functions which failed to ACK
 321  *
 322  * Return 0 if all functions have acknowledged the reset request.
 323  **/
 324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
 325 {
 326         int timeout;
 327         u32 ack, presence, val;
 328
 329         timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
 330         ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 331         presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 332         dev_info(&adapter->pdev->dev,
 333                  "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
 334         if (!((ack & presence) == presence)) {
 335                 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
 336                         /* Clear functions which failed to ACK */
 337                         dev_info(&adapter->pdev->dev,
 338                                  "%s: ACK wait exceeds time limit\n", __func__);
 339                         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 340                         val = val & ~(ack ^ presence);
 341                         if (qlcnic_83xx_lock_driver(adapter))
 342                                 return -EBUSY;
 343                         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 344                         dev_info(&adapter->pdev->dev,
 345                                  "%s: updated drv presence reg = 0x%x\n",
 346                                  __func__, val);
 347                         qlcnic_83xx_unlock_driver(adapter);
 348                         return 0;
 349
 350                 } else {
 351                         return 1;
 352                 }
 353         } else {
 354                 dev_info(&adapter->pdev->dev,
 355                          "%s: Reset ACK received from all functions\n",
 356                          __func__);
 357                 return 0;
 358         }
 359 }
 360
 361 /**
 362  * qlcnic_83xx_idc_tx_soft_reset
 363  *
 364  * @adapter: adapter structure
 365  *
 366  * Handle context deletion and recreation request from transmit routine
 367  *
 368  * Returns -EBUSY  or Success (0)
 369  *
 370  **/
 371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
 372 {
 373         struct net_device *netdev = adapter->netdev;
 374
 375         if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
 376                 return -EBUSY;
 377
 378         netif_device_detach(netdev);
 379         qlcnic_down(adapter, netdev);
 380         qlcnic_up(adapter, netdev);
 381         netif_device_attach(netdev);
 382         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 383         dev_err(&adapter->pdev->dev, "%s:\n", __func__);
 384
 385         return 0;
 386 }
 387
 388 /**
 389  * qlcnic_83xx_idc_detach_driver
 390  *
 391  * @adapter: adapter structure
 392  * Detach net interface, stop TX and cleanup resources before the HW reset.
 393  * Returns: None
 394  *
 395  **/
 396 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
 397 {
 398         int i;
 399         struct net_device *netdev = adapter->netdev;
 400
 401         netif_device_detach(netdev);
 402         qlcnic_83xx_detach_mailbox_work(adapter);
 403
 404         /* Disable mailbox interrupt */
 405         qlcnic_83xx_disable_mbx_intr(adapter);
 406         qlcnic_down(adapter, netdev);
 407         for (i = 0; i < adapter->ahw->num_msix; i++) {
 408                 adapter->ahw->intr_tbl[i].id = i;
 409                 adapter->ahw->intr_tbl[i].enabled = 0;
 410                 adapter->ahw->intr_tbl[i].src = 0;
 411         }
 412
 413         if (qlcnic_sriov_pf_check(adapter))
 414                 qlcnic_sriov_pf_reset(adapter);
 415 }
 416
 417 /**
 418  * qlcnic_83xx_idc_attach_driver
 419  *
 420  * @adapter: adapter structure
 421  *
 422  * Re-attach and re-enable net interface
 423  * Returns: None
 424  *
 425  **/
 426 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
 427 {
 428         struct net_device *netdev = adapter->netdev;
 429
 430         if (netif_running(netdev)) {
 431                 if (qlcnic_up(adapter, netdev))
 432                         goto done;
 433                 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
 434         }
 435 done:
 436         netif_device_attach(netdev);
 437 }
 438
 439 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
 440                                               int lock)
 441 {
 442         if (lock) {
 443                 if (qlcnic_83xx_lock_driver(adapter))
 444                         return -EBUSY;
 445         }
 446
 447         qlcnic_83xx_idc_clear_registers(adapter, 0);
 448         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
 449         if (lock)
 450                 qlcnic_83xx_unlock_driver(adapter);
 451
 452         qlcnic_83xx_idc_log_state_history(adapter);
 453         dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
 454
 455         return 0;
 456 }
 457
 458 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
 459                                             int lock)
 460 {
 461         if (lock) {
 462                 if (qlcnic_83xx_lock_driver(adapter))
 463                         return -EBUSY;
 464         }
 465
 466         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
 467
 468         if (lock)
 469                 qlcnic_83xx_unlock_driver(adapter);
 470
 471         return 0;
 472 }
 473
 474 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
 475                                               int lock)
 476 {
 477         if (lock) {
 478                 if (qlcnic_83xx_lock_driver(adapter))
 479                         return -EBUSY;
 480         }
 481
 482         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 483                QLC_83XX_IDC_DEV_NEED_QUISCENT);
 484
 485         if (lock)
 486                 qlcnic_83xx_unlock_driver(adapter);
 487
 488         return 0;
 489 }
 490
 491 static int
 492 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
 493 {
 494         if (lock) {
 495                 if (qlcnic_83xx_lock_driver(adapter))
 496                         return -EBUSY;
 497         }
 498
 499         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 500                QLC_83XX_IDC_DEV_NEED_RESET);
 501
 502         if (lock)
 503                 qlcnic_83xx_unlock_driver(adapter);
 504
 505         return 0;
 506 }
 507
 508 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
 509                                              int lock)
 510 {
 511         if (lock) {
 512                 if (qlcnic_83xx_lock_driver(adapter))
 513                         return -EBUSY;
 514         }
 515
 516         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
 517         if (lock)
 518                 qlcnic_83xx_unlock_driver(adapter);
 519
 520         return 0;
 521 }
 522
 523 /**
 524  * qlcnic_83xx_idc_find_reset_owner_id
 525  *
 526  * @adapter: adapter structure
 527  *
 528  * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
 529  * Within the same class, function with lowest PCI ID assumes ownership
 530  *
 531  * Returns: reset owner id or failure indication (-EIO)
 532  *
 533  **/
 534 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
 535 {
 536         u32 reg, reg1, reg2, i, j, owner, class;
 537
 538         reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
 539         reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
 540         owner = QLCNIC_TYPE_NIC;
 541         i = 0;
 542         j = 0;
 543         reg = reg1;
 544
 545         do {
 546                 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
 547                 if (class == owner)
 548                         break;
 549                 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
 550                         reg = reg2;
 551                         j = 0;
 552                 } else {
 553                         j++;
 554                 }
 555
 556                 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
 557                         if (owner == QLCNIC_TYPE_NIC)
 558                                 owner = QLCNIC_TYPE_ISCSI;
 559                         else if (owner == QLCNIC_TYPE_ISCSI)
 560                                 owner = QLCNIC_TYPE_FCOE;
 561                         else if (owner == QLCNIC_TYPE_FCOE)
 562                                 return -EIO;
 563                         reg = reg1;
 564                         j = 0;
 565                         i = 0;
 566                 }
 567         } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
 568
 569         return i;
 570 }
 571
 572 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
 573 {
 574         int ret = 0;
 575
 576         ret = qlcnic_83xx_restart_hw(adapter);
 577
 578         if (ret) {
 579                 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
 580         } else {
 581                 qlcnic_83xx_idc_clear_registers(adapter, lock);
 582                 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
 583         }
 584
 585         return ret;
 586 }
 587
 588 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
 589 {
 590         u32 status;
 591
 592         status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
 593
 594         if (status & QLCNIC_RCODE_FATAL_ERROR) {
 595                 dev_err(&adapter->pdev->dev,
 596                         "peg halt status1=0x%x\n", status);
 597                 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
 598                         dev_err(&adapter->pdev->dev,
 599                                 "On board active cooling fan failed. "
 600                                 "Device has been halted.\n");
 601                         dev_err(&adapter->pdev->dev,
 602                                 "Replace the adapter.\n");
 603                         return -EIO;
 604                 }
 605         }
 606
 607         return 0;
 608 }
 609
 610 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
 611 {
 612         int err;
 613
 614         qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
 615         qlcnic_83xx_enable_mbx_interrupt(adapter);
 616
 617         qlcnic_83xx_initialize_nic(adapter, 1);
 618
 619         err = qlcnic_sriov_pf_reinit(adapter);
 620         if (err)
 621                 return err;
 622
 623         qlcnic_83xx_enable_mbx_interrupt(adapter);
 624
 625         if (qlcnic_83xx_configure_opmode(adapter)) {
 626                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 627                 return -EIO;
 628         }
 629
 630         if (adapter->nic_ops->init_driver(adapter)) {
 631                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 632                 return -EIO;
 633         }
 634
 635         if (adapter->portnum == 0)
 636                 qlcnic_set_drv_version(adapter);
 637
 638         qlcnic_dcb_get_info(adapter->dcb);
 639         qlcnic_83xx_idc_attach_driver(adapter);
 640
 641         return 0;
 642 }
 643
 644 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
 645 {
 646         struct qlcnic_hardware_context *ahw = adapter->ahw;
 647
 648         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
 649         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 650         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
 651
 652         ahw->idc.quiesce_req = 0;
 653         ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
 654         ahw->idc.err_code = 0;
 655         ahw->idc.collect_dump = 0;
 656         ahw->reset_context = 0;
 657         adapter->tx_timeo_cnt = 0;
 658         ahw->idc.delay_reset = 0;
 659
 660         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 661 }
 662
 663 /**
 664  * qlcnic_83xx_idc_ready_state_entry
 665  *
 666  * @adapter: adapter structure
 667  *
 668  * Perform ready state initialization, this routine will get invoked only
 669  * once from READY state.
 670  *
 671  * Returns: Error code or Success(0)
 672  *
 673  **/
 674 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
 675 {
 676         struct qlcnic_hardware_context *ahw = adapter->ahw;
 677
 678         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
 679                 qlcnic_83xx_idc_update_idc_params(adapter);
 680                 /* Re-attach the device if required */
 681                 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
 682                     (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
 683                         if (qlcnic_83xx_idc_reattach_driver(adapter))
 684                                 return -EIO;
 685                 }
 686         }
 687
 688         return 0;
 689 }
 690
 691 /**
 692  * qlcnic_83xx_idc_vnic_pf_entry
 693  *
 694  * @adapter: adapter structure
 695  *
 696  * Ensure vNIC mode privileged function starts only after vNIC mode is
 697  * enabled by management function.
 698  * If vNIC mode is ready, start initialization.
 699  *
 700  * Returns: -EIO or 0
 701  *
 702  **/
 703 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
 704 {
 705         u32 state;
 706         struct qlcnic_hardware_context *ahw = adapter->ahw;
 707
 708         /* Privileged function waits till mgmt function enables VNIC mode */
 709         state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
 710         if (state != QLCNIC_DEV_NPAR_OPER) {
 711                 if (!ahw->idc.vnic_wait_limit--) {
 712                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 713                         return -EIO;
 714                 }
 715                 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
 716                 return -EIO;
 717
 718         } else {
 719                 /* Perform one time initialization from ready state */
 720                 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
 721                         qlcnic_83xx_idc_update_idc_params(adapter);
 722
 723                         /* If the previous state is UNKNOWN, device will be
 724                            already attached properly by Init routine*/
 725                         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
 726                                 if (qlcnic_83xx_idc_reattach_driver(adapter))
 727                                         return -EIO;
 728                         }
 729                         adapter->ahw->idc.vnic_state =  QLCNIC_DEV_NPAR_OPER;
 730                         dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
 731                 }
 732         }
 733
 734         return 0;
 735 }
 736
 737 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
 738 {
 739         adapter->ahw->idc.err_code = -EIO;
 740         dev_err(&adapter->pdev->dev,
 741                 "%s: Device in unknown state\n", __func__);
 742         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 743         return 0;
 744 }
 745
 746 /**
 747  * qlcnic_83xx_idc_cold_state
 748  *
 749  * @adapter: adapter structure
 750  *
 751  * If HW is up and running device will enter READY state.
 752  * If firmware image from host needs to be loaded, device is
 753  * forced to start with the file firmware image.
 754  *
 755  * Returns: Error code or Success(0)
 756  *
 757  **/
 758 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
 759 {
 760         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
 761         qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
 762
 763         if (qlcnic_load_fw_file) {
 764                 qlcnic_83xx_idc_restart_hw(adapter, 0);
 765         } else {
 766                 if (qlcnic_83xx_check_hw_status(adapter)) {
 767                         qlcnic_83xx_idc_enter_failed_state(adapter, 0);
 768                         return -EIO;
 769                 } else {
 770                         qlcnic_83xx_idc_enter_ready_state(adapter, 0);
 771                 }
 772         }
 773         return 0;
 774 }
 775
 776 /**
 777  * qlcnic_83xx_idc_init_state
 778  *
 779  * @adapter: adapter structure
 780  *
 781  * Reset owner will restart the device from this state.
 782  * Device will enter failed state if it remains
 783  * in this state for more than DEV_INIT time limit.
 784  *
 785  * Returns: Error code or Success(0)
 786  *
 787  **/
 788 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
 789 {
 790         int timeout, ret = 0;
 791         u32 owner;
 792
 793         timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
 794         if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
 795                 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
 796                 if (adapter->ahw->pci_func == owner)
 797                         ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
 798         } else {
 799                 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
 800         }
 801
 802         return ret;
 803 }
 804
 805 /**
 806  * qlcnic_83xx_idc_ready_state
 807  *
 808  * @adapter: adapter structure
 809  *
 810  * Perform IDC protocol specicifed actions after monitoring device state and
 811  * events.
 812  *
 813  * Returns: Error code or Success(0)
 814  *
 815  **/
 816 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
 817 {
 818         struct qlcnic_hardware_context *ahw = adapter->ahw;
 819         struct qlcnic_mailbox *mbx = ahw->mailbox;
 820         int ret = 0;
 821         u32 val;
 822
 823         /* Perform NIC configuration based ready state entry actions */
 824         if (ahw->idc.state_entry(adapter))
 825                 return -EIO;
 826
 827         if (qlcnic_check_temp(adapter)) {
 828                 if (ahw->temp == QLCNIC_TEMP_PANIC) {
 829                         qlcnic_83xx_idc_check_fan_failure(adapter);
 830                         dev_err(&adapter->pdev->dev,
 831                                 "Error: device temperature %d above limits\n",
 832                                 adapter->ahw->temp);
 833                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 834                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 835                         qlcnic_83xx_idc_detach_driver(adapter);
 836                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 837                         return -EIO;
 838                 }
 839         }
 840
 841         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 842         ret = qlcnic_83xx_check_heartbeat(adapter);
 843         if (ret) {
 844                 adapter->flags |= QLCNIC_FW_HANG;
 845                 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 846                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 847                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 848                         qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 849                 }  else {
 850                         netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n",
 851                                     __func__);
 852                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 853                 }
 854                 return -EIO;
 855         }
 856
 857         if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
 858                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 859
 860                 /* Move to need reset state and prepare for reset */
 861                 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 862                 return ret;
 863         }
 864
 865         /* Check for soft reset request */
 866         if (ahw->reset_context &&
 867             !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 868                 adapter->ahw->reset_context = 0;
 869                 qlcnic_83xx_idc_tx_soft_reset(adapter);
 870                 return ret;
 871         }
 872
 873         /* Move to need quiesce state if requested */
 874         if (adapter->ahw->idc.quiesce_req) {
 875                 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
 876                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 877                 return ret;
 878         }
 879
 880         return ret;
 881 }
 882
 883 /**
 884  * qlcnic_83xx_idc_need_reset_state
 885  *
 886  * @adapter: adapter structure
 887  *
 888  * Device will remain in this state until:
 889  *      Reset request ACK's are recieved from all the functions
 890  *      Wait time exceeds max time limit
 891  *
 892  * Returns: Error code or Success(0)
 893  *
 894  **/
 895 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
 896 {
 897         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 898         int ret = 0;
 899
 900         if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
 901                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 902                 set_bit(__QLCNIC_RESETTING, &adapter->state);
 903                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 904                 if (adapter->ahw->nic_mode == QLCNIC_VNIC_MODE)
 905                         qlcnic_83xx_disable_vnic_mode(adapter, 1);
 906
 907                 if (qlcnic_check_diag_status(adapter)) {
 908                         dev_info(&adapter->pdev->dev,
 909                                  "%s: Wait for diag completion\n", __func__);
 910                         adapter->ahw->idc.delay_reset = 1;
 911                         return 0;
 912                 } else {
 913                         qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 914                         qlcnic_83xx_idc_detach_driver(adapter);
 915                 }
 916         }
 917
 918         if (qlcnic_check_diag_status(adapter)) {
 919                 dev_info(&adapter->pdev->dev,
 920                          "%s: Wait for diag completion\n", __func__);
 921                 return  -1;
 922         } else {
 923                 if (adapter->ahw->idc.delay_reset) {
 924                         qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 925                         qlcnic_83xx_idc_detach_driver(adapter);
 926                         adapter->ahw->idc.delay_reset = 0;
 927                 }
 928
 929                 /* Check for ACK from other functions */
 930                 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
 931                 if (ret) {
 932                         dev_info(&adapter->pdev->dev,
 933                                  "%s: Waiting for reset ACK\n", __func__);
 934                         return -1;
 935                 }
 936         }
 937
 938         /* Transit to INIT state and restart the HW */
 939         qlcnic_83xx_idc_enter_init_state(adapter, 1);
 940
 941         return ret;
 942 }
 943
 944 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
 945 {
 946         dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
 947         return 0;
 948 }
 949
 950 static void qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
 951 {
 952         struct qlcnic_hardware_context *ahw = adapter->ahw;
 953         u32 val, owner;
 954
 955         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 956         if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) {
 957                 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
 958                 if (ahw->pci_func == owner) {
 959                         qlcnic_83xx_stop_hw(adapter);
 960                         qlcnic_dump_fw(adapter);
 961                 }
 962         }
 963
 964         netdev_warn(adapter->netdev, "%s: Reboot will be required to recover the adapter!!\n",
 965                     __func__);
 966         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 967         ahw->idc.err_code = -EIO;
 968
 969         return;
 970 }
 971
 972 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
 973 {
 974         dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
 975         return 0;
 976 }
 977
 978 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
 979                                                 u32 state)
 980 {
 981         u32 cur, prev, next;
 982
 983         cur = adapter->ahw->idc.curr_state;
 984         prev = adapter->ahw->idc.prev_state;
 985         next = state;
 986
 987         if ((next < QLC_83XX_IDC_DEV_COLD) ||
 988             (next > QLC_83XX_IDC_DEV_QUISCENT)) {
 989                 dev_err(&adapter->pdev->dev,
 990                         "%s: curr %d, prev %d, next state %d is  invalid\n",
 991                         __func__, cur, prev, state);
 992                 return 1;
 993         }
 994
 995         if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
 996             (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
 997                 if ((next != QLC_83XX_IDC_DEV_COLD) &&
 998                     (next != QLC_83XX_IDC_DEV_READY)) {
 999                         dev_err(&adapter->pdev->dev,
1000                                 "%s: failed, cur %d prev %d next %d\n",
1001                                 __func__, cur, prev, next);
1002                         return 1;
1003                 }
1004         }
1005
1006         if (next == QLC_83XX_IDC_DEV_INIT) {
1007                 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
1008                     (prev != QLC_83XX_IDC_DEV_COLD) &&
1009                     (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
1010                         dev_err(&adapter->pdev->dev,
1011                                 "%s: failed, cur %d prev %d next %d\n",
1012                                 __func__, cur, prev, next);
1013                         return 1;
1014                 }
1015         }
1016
1017         return 0;
1018 }
1019
1020 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
1021 {
1022         if (adapter->fhash.fnum)
1023                 qlcnic_prune_lb_filters(adapter);
1024 }
1025
1026 /**
1027  * qlcnic_83xx_idc_poll_dev_state
1028  *
1029  * @work: kernel work queue structure used to schedule the function
1030  *
1031  * Poll device state periodically and perform state specific
1032  * actions defined by Inter Driver Communication (IDC) protocol.
1033  *
1034  * Returns: None
1035  *
1036  **/
1037 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
1038 {
1039         struct qlcnic_adapter *adapter;
1040         u32 state;
1041
1042         adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1043         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1044
1045         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1046                 qlcnic_83xx_idc_log_state_history(adapter);
1047                 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1048         } else {
1049                 adapter->ahw->idc.curr_state = state;
1050         }
1051
1052         switch (adapter->ahw->idc.curr_state) {
1053         case QLC_83XX_IDC_DEV_READY:
1054                 qlcnic_83xx_idc_ready_state(adapter);
1055                 break;
1056         case QLC_83XX_IDC_DEV_NEED_RESET:
1057                 qlcnic_83xx_idc_need_reset_state(adapter);
1058                 break;
1059         case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1060                 qlcnic_83xx_idc_need_quiesce_state(adapter);
1061                 break;
1062         case QLC_83XX_IDC_DEV_FAILED:
1063                 qlcnic_83xx_idc_failed_state(adapter);
1064                 return;
1065         case QLC_83XX_IDC_DEV_INIT:
1066                 qlcnic_83xx_idc_init_state(adapter);
1067                 break;
1068         case QLC_83XX_IDC_DEV_QUISCENT:
1069                 qlcnic_83xx_idc_quiesce_state(adapter);
1070                 break;
1071         default:
1072                 qlcnic_83xx_idc_unknown_state(adapter);
1073                 return;
1074         }
1075         adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1076         qlcnic_83xx_periodic_tasks(adapter);
1077
1078         /* Re-schedule the function */
1079         if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1080                 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1081                                      adapter->ahw->idc.delay);
1082 }
1083
1084 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1085 {
1086         u32 idc_params, val;
1087
1088         if (qlcnic_83xx_lockless_flash_read32(adapter,
1089                                               QLC_83XX_IDC_FLASH_PARAM_ADDR,
1090                                               (u8 *)&idc_params, 1)) {
1091                 dev_info(&adapter->pdev->dev,
1092                          "%s:failed to get IDC params from flash\n", __func__);
1093                 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1094                 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1095         } else {
1096                 adapter->dev_init_timeo = idc_params & 0xFFFF;
1097                 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1098         }
1099
1100         adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1101         adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1102         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1103         adapter->ahw->idc.err_code = 0;
1104         adapter->ahw->idc.collect_dump = 0;
1105         adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1106
1107         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1108         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1109
1110         /* Check if reset recovery is disabled */
1111         if (!qlcnic_auto_fw_reset) {
1112                 /* Propagate do not reset request to other functions */
1113                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1114                 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1115                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1116         }
1117 }
1118
1119 static int
1120 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1121 {
1122         u32 state, val;
1123
1124         if (qlcnic_83xx_lock_driver(adapter))
1125                 return -EIO;
1126
1127         /* Clear driver lock register */
1128         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1129         if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1130                 qlcnic_83xx_unlock_driver(adapter);
1131                 return -EIO;
1132         }
1133
1134         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1135         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1136                 qlcnic_83xx_unlock_driver(adapter);
1137                 return -EIO;
1138         }
1139
1140         if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1141                 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1142                        QLC_83XX_IDC_DEV_COLD);
1143                 state = QLC_83XX_IDC_DEV_COLD;
1144         }
1145
1146         adapter->ahw->idc.curr_state = state;
1147         /* First to load function should cold boot the device */
1148         if (state == QLC_83XX_IDC_DEV_COLD)
1149                 qlcnic_83xx_idc_cold_state_handler(adapter);
1150
1151         /* Check if reset recovery is enabled */
1152         if (qlcnic_auto_fw_reset) {
1153                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1154                 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1155                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1156         }
1157
1158         qlcnic_83xx_unlock_driver(adapter);
1159
1160         return 0;
1161 }
1162
1163 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1164 {
1165         int ret = -EIO;
1166
1167         qlcnic_83xx_setup_idc_parameters(adapter);
1168
1169         if (qlcnic_83xx_get_reset_instruction_template(adapter))
1170                 return ret;
1171
1172         if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1173                 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1174                         return -EIO;
1175         } else {
1176                 if (qlcnic_83xx_idc_check_major_version(adapter))
1177                         return -EIO;
1178         }
1179
1180         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1181
1182         return 0;
1183 }
1184
1185 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1186 {
1187         int id;
1188         u32 val;
1189
1190         while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1191                 usleep_range(10000, 11000);
1192
1193         id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1194         id = id & 0xFF;
1195
1196         if (id == adapter->portnum) {
1197                 dev_err(&adapter->pdev->dev,
1198                         "%s: wait for lock recovery.. %d\n", __func__, id);
1199                 msleep(20);
1200                 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1201                 id = id & 0xFF;
1202         }
1203
1204         /* Clear driver presence bit */
1205         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1206         val = val & ~(1 << adapter->portnum);
1207         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1208         clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1209         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1210
1211         cancel_delayed_work_sync(&adapter->fw_work);
1212 }
1213
1214 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1215 {
1216         u32 val;
1217
1218         if (qlcnic_sriov_vf_check(adapter))
1219                 return;
1220
1221         if (qlcnic_83xx_lock_driver(adapter)) {
1222                 dev_err(&adapter->pdev->dev,
1223                         "%s:failed, please retry\n", __func__);
1224                 return;
1225         }
1226
1227         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1228         if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) {
1229                 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n",
1230                             __func__);
1231                 qlcnic_83xx_idc_enter_failed_state(adapter, 0);
1232                 qlcnic_83xx_unlock_driver(adapter);
1233                 return;
1234         }
1235
1236         if (key == QLCNIC_FORCE_FW_RESET) {
1237                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1238                 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1239                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1240         } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1241                 adapter->ahw->idc.collect_dump = 1;
1242         }
1243
1244         qlcnic_83xx_unlock_driver(adapter);
1245         return;
1246 }
1247
1248 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1249 {
1250         u8 *p_cache;
1251         u32 src, size;
1252         u64 dest;
1253         int ret = -EIO;
1254
1255         src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1256         dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1257         size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1258
1259         /* alignment check */
1260         if (size & 0xF)
1261                 size = (size + 16) & ~0xF;
1262
1263         p_cache = vzalloc(size);
1264         if (p_cache == NULL)
1265                 return -ENOMEM;
1266
1267         ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1268                                                 size / sizeof(u32));
1269         if (ret) {
1270                 vfree(p_cache);
1271                 return ret;
1272         }
1273         /* 16 byte write to MS memory */
1274         ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1275                                           size / 16);
1276         if (ret) {
1277                 vfree(p_cache);
1278                 return ret;
1279         }
1280         vfree(p_cache);
1281
1282         return ret;
1283 }
1284
1285 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1286 {
1287         struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
1288         const struct firmware *fw = fw_info->fw;
1289         u32 dest, *p_cache;
1290         int i, ret = -EIO;
1291         u8 data[16];
1292         size_t size;
1293         u64 addr;
1294
1295         dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1296         size = (fw->size & ~0xF);
1297         p_cache = (u32 *)fw->data;
1298         addr = (u64)dest;
1299
1300         ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1301                                           (u32 *)p_cache, size / 16);
1302         if (ret) {
1303                 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1304                 release_firmware(fw);
1305                 fw_info->fw = NULL;
1306                 return -EIO;
1307         }
1308
1309         /* alignment check */
1310         if (fw->size & 0xF) {
1311                 addr = dest + size;
1312                 for (i = 0; i < (fw->size & 0xF); i++)
1313                         data[i] = fw->data[size + i];
1314                 for (; i < 16; i++)
1315                         data[i] = 0;
1316                 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1317                                                   (u32 *)data, 1);
1318                 if (ret) {
1319                         dev_err(&adapter->pdev->dev,
1320                                 "MS memory write failed\n");
1321                         release_firmware(fw);
1322                         fw_info->fw = NULL;
1323                         return -EIO;
1324                 }
1325         }
1326         release_firmware(fw);
1327         fw_info->fw = NULL;
1328
1329         return 0;
1330 }
1331
1332 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1333 {
1334         int i, j;
1335         u32 val = 0, val1 = 0, reg = 0;
1336         int err = 0;
1337
1338         val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err);
1339         if (err == -EIO)
1340                 return;
1341         dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1342
1343         for (j = 0; j < 2; j++) {
1344                 if (j == 0) {
1345                         dev_info(&adapter->pdev->dev,
1346                                  "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1347                         reg = QLC_83XX_PORT0_THRESHOLD;
1348                 } else if (j == 1) {
1349                         dev_info(&adapter->pdev->dev,
1350                                  "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1351                         reg = QLC_83XX_PORT1_THRESHOLD;
1352                 }
1353                 for (i = 0; i < 8; i++) {
1354                         val = QLCRD32(adapter, reg + (i * 0x4), &err);
1355                         if (err == -EIO)
1356                                 return;
1357                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1358                 }
1359                 dev_info(&adapter->pdev->dev, "\n");
1360         }
1361
1362         for (j = 0; j < 2; j++) {
1363                 if (j == 0) {
1364                         dev_info(&adapter->pdev->dev,
1365                                  "Port 0 RxB TC Max Cell Registers[4..1]:");
1366                         reg = QLC_83XX_PORT0_TC_MC_REG;
1367                 } else if (j == 1) {
1368                         dev_info(&adapter->pdev->dev,
1369                                  "Port 1 RxB TC Max Cell Registers[4..1]:");
1370                         reg = QLC_83XX_PORT1_TC_MC_REG;
1371                 }
1372                 for (i = 0; i < 4; i++) {
1373                         val = QLCRD32(adapter, reg + (i * 0x4), &err);
1374                         if (err == -EIO)
1375                                 return;
1376                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1377                 }
1378                 dev_info(&adapter->pdev->dev, "\n");
1379         }
1380
1381         for (j = 0; j < 2; j++) {
1382                 if (j == 0) {
1383                         dev_info(&adapter->pdev->dev,
1384                                  "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1385                         reg = QLC_83XX_PORT0_TC_STATS;
1386                 } else if (j == 1) {
1387                         dev_info(&adapter->pdev->dev,
1388                                  "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1389                         reg = QLC_83XX_PORT1_TC_STATS;
1390                 }
1391                 for (i = 7; i >= 0; i--) {
1392                         val = QLCRD32(adapter, reg, &err);
1393                         if (err == -EIO)
1394                                 return;
1395                         val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
1396                         QLCWR32(adapter, reg, (val | (i << 29)));
1397                         val = QLCRD32(adapter, reg, &err);
1398                         if (err == -EIO)
1399                                 return;
1400                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1401                 }
1402                 dev_info(&adapter->pdev->dev, "\n");
1403         }
1404
1405         val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err);
1406         if (err == -EIO)
1407                 return;
1408         val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err);
1409         if (err == -EIO)
1410                 return;
1411         dev_info(&adapter->pdev->dev,
1412                  "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1413                  val, val1);
1414 }
1415
1416
1417 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1418 {
1419         u32 reg = 0, i, j;
1420
1421         if (qlcnic_83xx_lock_driver(adapter)) {
1422                 dev_err(&adapter->pdev->dev,
1423                         "%s:failed to acquire driver lock\n", __func__);
1424                 return;
1425         }
1426
1427         qlcnic_83xx_dump_pause_control_regs(adapter);
1428         QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1429
1430         for (j = 0; j < 2; j++) {
1431                 if (j == 0)
1432                         reg = QLC_83XX_PORT0_THRESHOLD;
1433                 else if (j == 1)
1434                         reg = QLC_83XX_PORT1_THRESHOLD;
1435
1436                 for (i = 0; i < 8; i++)
1437                         QLCWR32(adapter, reg + (i * 0x4), 0x0);
1438         }
1439
1440         for (j = 0; j < 2; j++) {
1441                 if (j == 0)
1442                         reg = QLC_83XX_PORT0_TC_MC_REG;
1443                 else if (j == 1)
1444                         reg = QLC_83XX_PORT1_TC_MC_REG;
1445
1446                 for (i = 0; i < 4; i++)
1447                         QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1448         }
1449
1450         QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1451         QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1452         dev_info(&adapter->pdev->dev,
1453                  "Disabled pause frames successfully on all ports\n");
1454         qlcnic_83xx_unlock_driver(adapter);
1455 }
1456
1457 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1458 {
1459         QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1460         QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1461         QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1462         QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1463         QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1464         QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1465         QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1466         QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1467         QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1468 }
1469
1470 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1471 {
1472         u32 heartbeat, peg_status;
1473         int retries, ret = -EIO, err = 0;
1474
1475         retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1476         p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1477                                                QLCNIC_PEG_ALIVE_COUNTER);
1478
1479         do {
1480                 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1481                 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1482                                                 QLCNIC_PEG_ALIVE_COUNTER);
1483                 if (heartbeat != p_dev->heartbeat) {
1484                         ret = QLCNIC_RCODE_SUCCESS;
1485                         break;
1486                 }
1487         } while (--retries);
1488
1489         if (ret) {
1490                 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1491                 qlcnic_83xx_take_eport_out_of_reset(p_dev);
1492                 qlcnic_83xx_disable_pause_frames(p_dev);
1493                 peg_status = QLC_SHARED_REG_RD32(p_dev,
1494                                                  QLCNIC_PEG_HALT_STATUS1);
1495                 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1496                          "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1497                          "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1498                          "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1499                          "PEG_NET_4_PC: 0x%x\n", peg_status,
1500                          QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1501                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err),
1502                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err),
1503                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err),
1504                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err),
1505                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err));
1506
1507                 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1508                         dev_err(&p_dev->pdev->dev,
1509                                 "Device is being reset err code 0x00006700.\n");
1510         }
1511
1512         return ret;
1513 }
1514
1515 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1516 {
1517         int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1518         u32 val;
1519
1520         do {
1521                 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1522                 if (val == QLC_83XX_CMDPEG_COMPLETE)
1523                         return 0;
1524                 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1525         } while (--retries);
1526
1527         dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1528         return -EIO;
1529 }
1530
1531 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1532 {
1533         int err;
1534
1535         err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1536         if (err)
1537                 return err;
1538
1539         err = qlcnic_83xx_check_heartbeat(p_dev);
1540         if (err)
1541                 return err;
1542
1543         return err;
1544 }
1545
1546 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1547                                 int duration, u32 mask, u32 status)
1548 {
1549         int timeout_error, err = 0;
1550         u32 value;
1551         u8 retries;
1552
1553         value = QLCRD32(p_dev, addr, &err);
1554         if (err == -EIO)
1555                 return err;
1556         retries = duration / 10;
1557
1558         do {
1559                 if ((value & mask) != status) {
1560                         timeout_error = 1;
1561                         msleep(duration / 10);
1562                         value = QLCRD32(p_dev, addr, &err);
1563                         if (err == -EIO)
1564                                 return err;
1565                 } else {
1566                         timeout_error = 0;
1567                         break;
1568                 }
1569         } while (retries--);
1570
1571         if (timeout_error) {
1572                 p_dev->ahw->reset.seq_error++;
1573                 dev_err(&p_dev->pdev->dev,
1574                         "%s: Timeout Err, entry_num = %d\n",
1575                         __func__, p_dev->ahw->reset.seq_index);
1576                 dev_err(&p_dev->pdev->dev,
1577                         "0x%08x 0x%08x 0x%08x\n",
1578                         value, mask, status);
1579         }
1580
1581         return timeout_error;
1582 }
1583
1584 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1585 {
1586         u32 sum = 0;
1587         u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1588         int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1589
1590         while (count-- > 0)
1591                 sum += *buff++;
1592
1593         while (sum >> 16)
1594                 sum = (sum & 0xFFFF) + (sum >> 16);
1595
1596         if (~sum) {
1597                 return 0;
1598         } else {
1599                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1600                 return -1;
1601         }
1602 }
1603
1604 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1605 {
1606         struct qlcnic_hardware_context *ahw = p_dev->ahw;
1607         u32 addr, count, prev_ver, curr_ver;
1608         u8 *p_buff;
1609
1610         if (ahw->reset.buff != NULL) {
1611                 prev_ver = p_dev->fw_version;
1612                 curr_ver = qlcnic_83xx_get_fw_version(p_dev);
1613                 if (curr_ver > prev_ver)
1614                         kfree(ahw->reset.buff);
1615                 else
1616                         return 0;
1617         }
1618
1619         ahw->reset.seq_error = 0;
1620         ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1621         if (p_dev->ahw->reset.buff == NULL)
1622                 return -ENOMEM;
1623
1624         p_buff = p_dev->ahw->reset.buff;
1625         addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1626         count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1627
1628         /* Copy template header from flash */
1629         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1630                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1631                 return -EIO;
1632         }
1633         ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1634         addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1635         p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1636         count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1637
1638         /* Copy rest of the template */
1639         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1640                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1641                 return -EIO;
1642         }
1643
1644         if (qlcnic_83xx_reset_template_checksum(p_dev))
1645                 return -EIO;
1646         /* Get Stop, Start and Init command offsets */
1647         ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1648         ahw->reset.start_offset = ahw->reset.buff +
1649                                   ahw->reset.hdr->start_offset;
1650         ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1651         return 0;
1652 }
1653
1654 /* Read Write HW register command */
1655 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1656                                            u32 raddr, u32 waddr)
1657 {
1658         int err = 0;
1659         u32 value;
1660
1661         value = QLCRD32(p_dev, raddr, &err);
1662         if (err == -EIO)
1663                 return;
1664         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1665 }
1666
1667 /* Read Modify Write HW register command */
1668 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1669                                     u32 raddr, u32 waddr,
1670                                     struct qlc_83xx_rmw *p_rmw_hdr)
1671 {
1672         int err = 0;
1673         u32 value;
1674
1675         if (p_rmw_hdr->index_a) {
1676                 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1677         } else {
1678                 value = QLCRD32(p_dev, raddr, &err);
1679                 if (err == -EIO)
1680                         return;
1681         }
1682
1683         value &= p_rmw_hdr->mask;
1684         value <<= p_rmw_hdr->shl;
1685         value >>= p_rmw_hdr->shr;
1686         value |= p_rmw_hdr->or_value;
1687         value ^= p_rmw_hdr->xor_value;
1688         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1689 }
1690
1691 /* Write HW register command */
1692 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1693                                    struct qlc_83xx_entry_hdr *p_hdr)
1694 {
1695         int i;
1696         struct qlc_83xx_entry *entry;
1697
1698         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1699                                           sizeof(struct qlc_83xx_entry_hdr));
1700
1701         for (i = 0; i < p_hdr->count; i++, entry++) {
1702                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1703                                              entry->arg2);
1704                 if (p_hdr->delay)
1705                         udelay((u32)(p_hdr->delay));
1706         }
1707 }
1708
1709 /* Read and Write instruction */
1710 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1711                                         struct qlc_83xx_entry_hdr *p_hdr)
1712 {
1713         int i;
1714         struct qlc_83xx_entry *entry;
1715
1716         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1717                                           sizeof(struct qlc_83xx_entry_hdr));
1718
1719         for (i = 0; i < p_hdr->count; i++, entry++) {
1720                 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1721                                                entry->arg2);
1722                 if (p_hdr->delay)
1723                         udelay((u32)(p_hdr->delay));
1724         }
1725 }
1726
1727 /* Poll HW register command */
1728 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1729                                   struct qlc_83xx_entry_hdr *p_hdr)
1730 {
1731         long delay;
1732         struct qlc_83xx_entry *entry;
1733         struct qlc_83xx_poll *poll;
1734         int i, err = 0;
1735         unsigned long arg1, arg2;
1736
1737         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1738                                         sizeof(struct qlc_83xx_entry_hdr));
1739
1740         entry = (struct qlc_83xx_entry *)((char *)poll +
1741                                           sizeof(struct qlc_83xx_poll));
1742         delay = (long)p_hdr->delay;
1743
1744         if (!delay) {
1745                 for (i = 0; i < p_hdr->count; i++, entry++)
1746                         qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1747                                              delay, poll->mask,
1748                                              poll->status);
1749         } else {
1750                 for (i = 0; i < p_hdr->count; i++, entry++) {
1751                         arg1 = entry->arg1;
1752                         arg2 = entry->arg2;
1753                         if (delay) {
1754                                 if (qlcnic_83xx_poll_reg(p_dev,
1755                                                          arg1, delay,
1756                                                          poll->mask,
1757                                                          poll->status)){
1758                                         QLCRD32(p_dev, arg1, &err);
1759                                         if (err == -EIO)
1760                                                 return;
1761                                         QLCRD32(p_dev, arg2, &err);
1762                                         if (err == -EIO)
1763                                                 return;
1764                                 }
1765                         }
1766                 }
1767         }
1768 }
1769
1770 /* Poll and write HW register command */
1771 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1772                                         struct qlc_83xx_entry_hdr *p_hdr)
1773 {
1774         int i;
1775         long delay;
1776         struct qlc_83xx_quad_entry *entry;
1777         struct qlc_83xx_poll *poll;
1778
1779         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1780                                         sizeof(struct qlc_83xx_entry_hdr));
1781         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1782                                                sizeof(struct qlc_83xx_poll));
1783         delay = (long)p_hdr->delay;
1784
1785         for (i = 0; i < p_hdr->count; i++, entry++) {
1786                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1787                                              entry->dr_value);
1788                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1789                                              entry->ar_value);
1790                 if (delay)
1791                         qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1792                                              poll->mask, poll->status);
1793         }
1794 }
1795
1796 /* Read Modify Write register command */
1797 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1798                                           struct qlc_83xx_entry_hdr *p_hdr)
1799 {
1800         int i;
1801         struct qlc_83xx_entry *entry;
1802         struct qlc_83xx_rmw *rmw_hdr;
1803
1804         rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1805                                           sizeof(struct qlc_83xx_entry_hdr));
1806
1807         entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1808                                           sizeof(struct qlc_83xx_rmw));
1809
1810         for (i = 0; i < p_hdr->count; i++, entry++) {
1811                 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1812                                         entry->arg2, rmw_hdr);
1813                 if (p_hdr->delay)
1814                         udelay((u32)(p_hdr->delay));
1815         }
1816 }
1817
1818 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1819 {
1820         if (p_hdr->delay)
1821                 mdelay((u32)((long)p_hdr->delay));
1822 }
1823
1824 /* Read and poll register command */
1825 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1826                                        struct qlc_83xx_entry_hdr *p_hdr)
1827 {
1828         long delay;
1829         int index, i, j, err;
1830         struct qlc_83xx_quad_entry *entry;
1831         struct qlc_83xx_poll *poll;
1832         unsigned long addr;
1833
1834         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1835                                         sizeof(struct qlc_83xx_entry_hdr));
1836
1837         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1838                                                sizeof(struct qlc_83xx_poll));
1839         delay = (long)p_hdr->delay;
1840
1841         for (i = 0; i < p_hdr->count; i++, entry++) {
1842                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1843                                              entry->ar_value);
1844                 if (delay) {
1845                         if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1846                                                   poll->mask, poll->status)){
1847                                 index = p_dev->ahw->reset.array_index;
1848                                 addr = entry->dr_addr;
1849                                 j = QLCRD32(p_dev, addr, &err);
1850                                 if (err == -EIO)
1851                                         return;
1852
1853                                 p_dev->ahw->reset.array[index++] = j;
1854
1855                                 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1856                                         p_dev->ahw->reset.array_index = 1;
1857                         }
1858                 }
1859         }
1860 }
1861
1862 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1863 {
1864         p_dev->ahw->reset.seq_end = 1;
1865 }
1866
1867 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1868 {
1869         p_dev->ahw->reset.template_end = 1;
1870         if (p_dev->ahw->reset.seq_error == 0)
1871                 dev_err(&p_dev->pdev->dev,
1872                         "HW restart process completed successfully.\n");
1873         else
1874                 dev_err(&p_dev->pdev->dev,
1875                         "HW restart completed with timeout errors.\n");
1876 }
1877
1878 /**
1879 * qlcnic_83xx_exec_template_cmd
1880 *
1881 * @p_dev: adapter structure
1882 * @p_buff: Poiter to instruction template
1883 *
1884 * Template provides instructions to stop, restart and initalize firmware.
1885 * These instructions are abstracted as a series of read, write and
1886 * poll operations on hardware registers. Register information and operation
1887 * specifics are not exposed to the driver. Driver reads the template from
1888 * flash and executes the instructions located at pre-defined offsets.
1889 *
1890 * Returns: None
1891 * */
1892 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1893                                           char *p_buff)
1894 {
1895         int index, entries;
1896         struct qlc_83xx_entry_hdr *p_hdr;
1897         char *entry = p_buff;
1898
1899         p_dev->ahw->reset.seq_end = 0;
1900         p_dev->ahw->reset.template_end = 0;
1901         entries = p_dev->ahw->reset.hdr->entries;
1902         index = p_dev->ahw->reset.seq_index;
1903
1904         for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1905                 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1906
1907                 switch (p_hdr->cmd) {
1908                 case QLC_83XX_OPCODE_NOP:
1909                         break;
1910                 case QLC_83XX_OPCODE_WRITE_LIST:
1911                         qlcnic_83xx_write_list(p_dev, p_hdr);
1912                         break;
1913                 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1914                         qlcnic_83xx_read_write_list(p_dev, p_hdr);
1915                         break;
1916                 case QLC_83XX_OPCODE_POLL_LIST:
1917                         qlcnic_83xx_poll_list(p_dev, p_hdr);
1918                         break;
1919                 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1920                         qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1921                         break;
1922                 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1923                         qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1924                         break;
1925                 case QLC_83XX_OPCODE_SEQ_PAUSE:
1926                         qlcnic_83xx_pause(p_hdr);
1927                         break;
1928                 case QLC_83XX_OPCODE_SEQ_END:
1929                         qlcnic_83xx_seq_end(p_dev);
1930                         break;
1931                 case QLC_83XX_OPCODE_TMPL_END:
1932                         qlcnic_83xx_template_end(p_dev);
1933                         break;
1934                 case QLC_83XX_OPCODE_POLL_READ_LIST:
1935                         qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1936                         break;
1937                 default:
1938                         dev_err(&p_dev->pdev->dev,
1939                                 "%s: Unknown opcode 0x%04x in template %d\n",
1940                                 __func__, p_hdr->cmd, index);
1941                         break;
1942                 }
1943                 entry += p_hdr->size;
1944         }
1945         p_dev->ahw->reset.seq_index = index;
1946 }
1947
1948 void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1949 {
1950         p_dev->ahw->reset.seq_index = 0;
1951
1952         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1953         if (p_dev->ahw->reset.seq_end != 1)
1954                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1955 }
1956
1957 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1958 {
1959         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1960         if (p_dev->ahw->reset.template_end != 1)
1961                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1962 }
1963
1964 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1965 {
1966         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1967         if (p_dev->ahw->reset.seq_end != 1)
1968                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1969 }
1970
1971 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1972 {
1973         struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
1974         int err = -EIO;
1975
1976         if (request_firmware(&fw_info->fw, fw_info->fw_file_name,
1977                              &(adapter->pdev->dev))) {
1978                 dev_err(&adapter->pdev->dev,
1979                         "No file FW image, loading flash FW image.\n");
1980                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1981                                     QLC_83XX_BOOT_FROM_FLASH);
1982         } else {
1983                 if (qlcnic_83xx_copy_fw_file(adapter))
1984                         return err;
1985                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1986                                     QLC_83XX_BOOT_FROM_FILE);
1987         }
1988
1989         return 0;
1990 }
1991
1992 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1993 {
1994         u32 val;
1995         int err = -EIO;
1996
1997         qlcnic_83xx_stop_hw(adapter);
1998
1999         /* Collect FW register dump if required */
2000         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
2001         if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
2002                 qlcnic_dump_fw(adapter);
2003
2004         if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) {
2005                 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n",
2006                             __func__);
2007                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
2008                 return err;
2009         }
2010
2011         qlcnic_83xx_init_hw(adapter);
2012
2013         if (qlcnic_83xx_copy_bootloader(adapter))
2014                 return err;
2015         /* Boot either flash image or firmware image from host file system */
2016         if (qlcnic_load_fw_file) {
2017                 if (qlcnic_83xx_load_fw_image_from_host(adapter))
2018                         return err;
2019         } else {
2020                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2021                                     QLC_83XX_BOOT_FROM_FLASH);
2022         }
2023
2024         qlcnic_83xx_start_hw(adapter);
2025         if (qlcnic_83xx_check_hw_status(adapter))
2026                 return -EIO;
2027
2028         return 0;
2029 }
2030
2031 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
2032 {
2033         int err;
2034         struct qlcnic_info nic_info;
2035         struct qlcnic_hardware_context *ahw = adapter->ahw;
2036
2037         memset(&nic_info, 0, sizeof(struct qlcnic_info));
2038         err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
2039         if (err)
2040                 return -EIO;
2041
2042         ahw->physical_port = (u8) nic_info.phys_port;
2043         ahw->switch_mode = nic_info.switch_mode;
2044         ahw->max_tx_ques = nic_info.max_tx_ques;
2045         ahw->max_rx_ques = nic_info.max_rx_ques;
2046         ahw->capabilities = nic_info.capabilities;
2047         ahw->max_mac_filters = nic_info.max_mac_filters;
2048         ahw->max_mtu = nic_info.max_mtu;
2049
2050         adapter->max_tx_rings = ahw->max_tx_ques;
2051         adapter->max_sds_rings = ahw->max_rx_ques;
2052         /* eSwitch capability indicates vNIC mode.
2053          * vNIC and SRIOV are mutually exclusive operational modes.
2054          * If SR-IOV capability is detected, SR-IOV physical function
2055          * will get initialized in default mode.
2056          * SR-IOV virtual function initialization follows a
2057          * different code path and opmode.
2058          * SRIOV mode has precedence over vNIC mode.
2059          */
2060         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
2061                 return QLC_83XX_DEFAULT_OPMODE;
2062
2063         if (ahw->capabilities & QLC_83XX_ESWITCH_CAPABILITY)
2064                 return QLCNIC_VNIC_MODE;
2065
2066         return QLC_83XX_DEFAULT_OPMODE;
2067 }
2068
2069 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
2070 {
2071         struct qlcnic_hardware_context *ahw = adapter->ahw;
2072         int ret;
2073
2074         ret = qlcnic_83xx_get_nic_configuration(adapter);
2075         if (ret == -EIO)
2076                 return -EIO;
2077
2078         if (ret == QLCNIC_VNIC_MODE) {
2079                 ahw->nic_mode = QLCNIC_VNIC_MODE;
2080
2081                 if (qlcnic_83xx_config_vnic_opmode(adapter))
2082                         return -EIO;
2083
2084                 adapter->max_sds_rings = QLCNIC_MAX_VNIC_SDS_RINGS;
2085                 adapter->max_tx_rings = QLCNIC_MAX_VNIC_TX_RINGS;
2086         } else if (ret == QLC_83XX_DEFAULT_OPMODE) {
2087                 ahw->nic_mode = QLCNIC_DEFAULT_MODE;
2088                 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
2089                 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
2090                 adapter->max_sds_rings = QLCNIC_MAX_SDS_RINGS;
2091                 adapter->max_tx_rings = QLCNIC_MAX_TX_RINGS;
2092         } else {
2093                 return -EIO;
2094         }
2095
2096         return 0;
2097 }
2098
2099 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2100 {
2101         struct qlcnic_hardware_context *ahw = adapter->ahw;
2102
2103         if (ahw->port_type == QLCNIC_XGBE) {
2104                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2105                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2106                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2107                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2108
2109         } else if (ahw->port_type == QLCNIC_GBE) {
2110                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2111                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2112                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2113                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2114         }
2115         adapter->num_txd = MAX_CMD_DESCRIPTORS;
2116         adapter->max_rds_rings = MAX_RDS_RINGS;
2117 }
2118
2119 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2120 {
2121         int err = -EIO;
2122
2123         qlcnic_83xx_get_minidump_template(adapter);
2124         if (qlcnic_83xx_get_port_info(adapter))
2125                 return err;
2126
2127         qlcnic_83xx_config_buff_descriptors(adapter);
2128         adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2129         adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2130
2131         dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2132                  adapter->ahw->fw_hal_version);
2133
2134         return 0;
2135 }
2136
2137 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2138 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2139 {
2140         struct qlcnic_cmd_args cmd;
2141         u32 presence_mask, audit_mask;
2142         int status;
2143
2144         presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2145         audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2146
2147         if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2148                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
2149                                                QLCNIC_CMD_STOP_NIC_FUNC);
2150                 if (status)
2151                         return;
2152
2153                 cmd.req.arg[1] = BIT_31;
2154                 status = qlcnic_issue_cmd(adapter, &cmd);
2155                 if (status)
2156                         dev_err(&adapter->pdev->dev,
2157                                 "Failed to clean up the function resources\n");
2158                 qlcnic_free_mbx_args(&cmd);
2159         }
2160 }
2161
2162 static int qlcnic_83xx_get_fw_info(struct qlcnic_adapter *adapter)
2163 {
2164         struct qlcnic_hardware_context *ahw = adapter->ahw;
2165         struct pci_dev *pdev = adapter->pdev;
2166         struct qlc_83xx_fw_info *fw_info;
2167         int err = 0;
2168
2169         ahw->fw_info = kzalloc(sizeof(*fw_info), GFP_KERNEL);
2170         if (!ahw->fw_info) {
2171                 err = -ENOMEM;
2172         } else {
2173                 fw_info = ahw->fw_info;
2174                 switch (pdev->device) {
2175                 case PCI_DEVICE_ID_QLOGIC_QLE834X:
2176                         strncpy(fw_info->fw_file_name, QLC_83XX_FW_FILE_NAME,
2177                                 QLC_FW_FILE_NAME_LEN);
2178                         break;
2179                 case PCI_DEVICE_ID_QLOGIC_QLE844X:
2180                         strncpy(fw_info->fw_file_name, QLC_84XX_FW_FILE_NAME,
2181                                 QLC_FW_FILE_NAME_LEN);
2182                         break;
2183                 default:
2184                         dev_err(&pdev->dev, "%s: Invalid device id\n",
2185                                 __func__);
2186                         err = -EINVAL;
2187                         break;
2188                 }
2189         }
2190
2191         return err;
2192 }
2193
2194 static void qlcnic_83xx_init_rings(struct qlcnic_adapter *adapter)
2195 {
2196         u8 rx_cnt = QLCNIC_DEF_SDS_RINGS;
2197         u8 tx_cnt = QLCNIC_DEF_TX_RINGS;
2198
2199         adapter->max_tx_rings = QLCNIC_MAX_TX_RINGS;
2200         adapter->max_sds_rings = QLCNIC_MAX_SDS_RINGS;
2201
2202         if (!adapter->ahw->msix_supported) {
2203                 rx_cnt = QLCNIC_SINGLE_RING;
2204                 tx_cnt = QLCNIC_SINGLE_RING;
2205         }
2206
2207         /* compute and set drv sds rings */
2208         qlcnic_set_tx_ring_count(adapter, tx_cnt);
2209         qlcnic_set_sds_ring_count(adapter, rx_cnt);
2210 }
2211
2212 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2213 {
2214         struct qlcnic_hardware_context *ahw = adapter->ahw;
2215         int err = 0;
2216
2217         adapter->rx_mac_learn = 0;
2218         ahw->msix_supported = !!qlcnic_use_msi_x;
2219
2220         qlcnic_83xx_init_rings(adapter);
2221
2222         err = qlcnic_83xx_init_mailbox_work(adapter);
2223         if (err)
2224                 goto exit;
2225
2226         if (qlcnic_sriov_vf_check(adapter)) {
2227                 err = qlcnic_sriov_vf_init(adapter, pci_using_dac);
2228                 if (err)
2229                         goto detach_mbx;
2230                 else
2231                         return err;
2232         }
2233
2234         if (qlcnic_83xx_read_flash_descriptor_table(adapter) ||
2235             qlcnic_83xx_read_flash_mfg_id(adapter)) {
2236                 dev_err(&adapter->pdev->dev, "Failed reading flash mfg id\n");
2237                 err = -ENOTRECOVERABLE;
2238                 goto detach_mbx;
2239         }
2240
2241         err = qlcnic_83xx_check_hw_status(adapter);
2242         if (err)
2243                 goto detach_mbx;
2244
2245         err = qlcnic_83xx_get_fw_info(adapter);
2246         if (err)
2247                 goto detach_mbx;
2248
2249         err = qlcnic_83xx_idc_init(adapter);
2250         if (err)
2251                 goto detach_mbx;
2252
2253         err = qlcnic_setup_intr(adapter);
2254         if (err) {
2255                 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
2256                 goto disable_intr;
2257         }
2258
2259         err = qlcnic_83xx_setup_mbx_intr(adapter);
2260         if (err)
2261                 goto disable_mbx_intr;
2262
2263         qlcnic_83xx_clear_function_resources(adapter);
2264
2265         INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2266
2267         qlcnic_83xx_initialize_nic(adapter, 1);
2268
2269         /* Configure default, SR-IOV or Virtual NIC mode of operation */
2270         err = qlcnic_83xx_configure_opmode(adapter);
2271         if (err)
2272                 goto disable_mbx_intr;
2273
2274
2275         /* Perform operating mode specific initialization */
2276         err = adapter->nic_ops->init_driver(adapter);
2277         if (err)
2278                 goto disable_mbx_intr;
2279
2280         /* Periodically monitor device status */
2281         qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2282         return 0;
2283
2284 disable_mbx_intr:
2285         qlcnic_83xx_free_mbx_intr(adapter);
2286
2287 disable_intr:
2288         qlcnic_teardown_intr(adapter);
2289
2290 detach_mbx:
2291         qlcnic_83xx_detach_mailbox_work(adapter);
2292         qlcnic_83xx_free_mailbox(ahw->mailbox);
2293         ahw->mailbox = NULL;
2294 exit:
2295         return err;
2296 }
2297
2298 void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *adapter)
2299 {
2300         struct qlcnic_hardware_context *ahw = adapter->ahw;
2301         struct qlc_83xx_idc *idc = &ahw->idc;
2302
2303         clear_bit(QLC_83XX_MBX_READY, &idc->status);
2304         cancel_delayed_work_sync(&adapter->fw_work);
2305
2306         if (ahw->nic_mode == QLCNIC_VNIC_MODE)
2307                 qlcnic_83xx_disable_vnic_mode(adapter, 1);
2308
2309         qlcnic_83xx_idc_detach_driver(adapter);
2310         qlcnic_83xx_initialize_nic(adapter, 0);
2311
2312         cancel_delayed_work_sync(&adapter->idc_aen_work);
2313 }
2314
2315 int qlcnic_83xx_aer_reset(struct qlcnic_adapter *adapter)
2316 {
2317         struct qlcnic_hardware_context *ahw = adapter->ahw;
2318         struct qlc_83xx_idc *idc = &ahw->idc;
2319         int ret = 0;
2320         u32 owner;
2321
2322         /* Mark the previous IDC state as NEED_RESET so
2323          * that state_entry() will perform the reattachment
2324          * and bringup the device
2325          */
2326         idc->prev_state = QLC_83XX_IDC_DEV_NEED_RESET;
2327         owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
2328         if (ahw->pci_func == owner) {
2329                 ret = qlcnic_83xx_restart_hw(adapter);
2330                 if (ret < 0)
2331                         return ret;
2332                 qlcnic_83xx_idc_clear_registers(adapter, 0);
2333         }
2334
2335         ret = idc->state_entry(adapter);
2336         return ret;
2337 }
2338
2339 void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *adapter)
2340 {
2341         struct qlcnic_hardware_context *ahw = adapter->ahw;
2342         struct qlc_83xx_idc *idc = &ahw->idc;
2343         u32 owner;
2344
2345         idc->prev_state = QLC_83XX_IDC_DEV_READY;
2346         owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
2347         if (ahw->pci_func == owner)
2348                 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
2349
2350         qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 0);
2351 }