Pileus Git - ~andy/linux/blob - drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_sriov.h"
  10 #include <linux/if_vlan.h>
  11 #include <linux/ipv6.h>
  12 #include <linux/ethtool.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/aer.h>
  15
  16 #define RSS_HASHTYPE_IP_TCP             0x3
  17 #define QLC_83XX_FW_MBX_CMD             0
  18 #define QLC_SKIP_INACTIVE_PCI_REGS      7
  19
  20 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
  21         {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
  22         {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
  23         {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
  24         {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  25         {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
  26         {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  27         {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
  28         {QLCNIC_CMD_INTRPT_TEST, 22, 12},
  29         {QLCNIC_CMD_SET_MTU, 3, 1},
  30         {QLCNIC_CMD_READ_PHY, 4, 2},
  31         {QLCNIC_CMD_WRITE_PHY, 5, 1},
  32         {QLCNIC_CMD_READ_HW_REG, 4, 1},
  33         {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  34         {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  35         {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  36         {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  37         {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  38         {QLCNIC_CMD_GET_PCI_INFO, 1, 129},
  39         {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
  40         {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
  41         {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  42         {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  43         {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  44         {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  45         {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  46         {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  47         {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  48         {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  49         {QLCNIC_CMD_TEMP_SIZE, 1, 4},
  50         {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
  51         {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
  52         {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
  53         {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
  54         {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
  55         {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
  56         {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
  57         {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
  58         {QLCNIC_CMD_GET_STATISTICS, 2, 80},
  59         {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
  60         {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
  61         {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
  62         {QLCNIC_CMD_IDC_ACK, 5, 1},
  63         {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
  64         {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
  65         {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
  66         {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
  67         {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
  68         {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
  69         {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
  70         {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
  71         {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
  72         {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
  73 };
  74
  75 const u32 qlcnic_83xx_ext_reg_tbl[] = {
  76         0x38CC,         /* Global Reset */
  77         0x38F0,         /* Wildcard */
  78         0x38FC,         /* Informant */
  79         0x3038,         /* Host MBX ctrl */
  80         0x303C,         /* FW MBX ctrl */
  81         0x355C,         /* BOOT LOADER ADDRESS REG */
  82         0x3560,         /* BOOT LOADER SIZE REG */
  83         0x3564,         /* FW IMAGE ADDR REG */
  84         0x1000,         /* MBX intr enable */
  85         0x1200,         /* Default Intr mask */
  86         0x1204,         /* Default Interrupt ID */
  87         0x3780,         /* QLC_83XX_IDC_MAJ_VERSION */
  88         0x3784,         /* QLC_83XX_IDC_DEV_STATE */
  89         0x3788,         /* QLC_83XX_IDC_DRV_PRESENCE */
  90         0x378C,         /* QLC_83XX_IDC_DRV_ACK */
  91         0x3790,         /* QLC_83XX_IDC_CTRL */
  92         0x3794,         /* QLC_83XX_IDC_DRV_AUDIT */
  93         0x3798,         /* QLC_83XX_IDC_MIN_VERSION */
  94         0x379C,         /* QLC_83XX_RECOVER_DRV_LOCK */
  95         0x37A0,         /* QLC_83XX_IDC_PF_0 */
  96         0x37A4,         /* QLC_83XX_IDC_PF_1 */
  97         0x37A8,         /* QLC_83XX_IDC_PF_2 */
  98         0x37AC,         /* QLC_83XX_IDC_PF_3 */
  99         0x37B0,         /* QLC_83XX_IDC_PF_4 */
 100         0x37B4,         /* QLC_83XX_IDC_PF_5 */
 101         0x37B8,         /* QLC_83XX_IDC_PF_6 */
 102         0x37BC,         /* QLC_83XX_IDC_PF_7 */
 103         0x37C0,         /* QLC_83XX_IDC_PF_8 */
 104         0x37C4,         /* QLC_83XX_IDC_PF_9 */
 105         0x37C8,         /* QLC_83XX_IDC_PF_10 */
 106         0x37CC,         /* QLC_83XX_IDC_PF_11 */
 107         0x37D0,         /* QLC_83XX_IDC_PF_12 */
 108         0x37D4,         /* QLC_83XX_IDC_PF_13 */
 109         0x37D8,         /* QLC_83XX_IDC_PF_14 */
 110         0x37DC,         /* QLC_83XX_IDC_PF_15 */
 111         0x37E0,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
 112         0x37E4,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
 113         0x37F0,         /* QLC_83XX_DRV_OP_MODE */
 114         0x37F4,         /* QLC_83XX_VNIC_STATE */
 115         0x3868,         /* QLC_83XX_DRV_LOCK */
 116         0x386C,         /* QLC_83XX_DRV_UNLOCK */
 117         0x3504,         /* QLC_83XX_DRV_LOCK_ID */
 118         0x34A4,         /* QLC_83XX_ASIC_TEMP */
 119 };
 120
 121 const u32 qlcnic_83xx_reg_tbl[] = {
 122         0x34A8,         /* PEG_HALT_STAT1 */
 123         0x34AC,         /* PEG_HALT_STAT2 */
 124         0x34B0,         /* FW_HEARTBEAT */
 125         0x3500,         /* FLASH LOCK_ID */
 126         0x3528,         /* FW_CAPABILITIES */
 127         0x3538,         /* Driver active, DRV_REG0 */
 128         0x3540,         /* Device state, DRV_REG1 */
 129         0x3544,         /* Driver state, DRV_REG2 */
 130         0x3548,         /* Driver scratch, DRV_REG3 */
 131         0x354C,         /* Device partiton info, DRV_REG4 */
 132         0x3524,         /* Driver IDC ver, DRV_REG5 */
 133         0x3550,         /* FW_VER_MAJOR */
 134         0x3554,         /* FW_VER_MINOR */
 135         0x3558,         /* FW_VER_SUB */
 136         0x359C,         /* NPAR STATE */
 137         0x35FC,         /* FW_IMG_VALID */
 138         0x3650,         /* CMD_PEG_STATE */
 139         0x373C,         /* RCV_PEG_STATE */
 140         0x37B4,         /* ASIC TEMP */
 141         0x356C,         /* FW API */
 142         0x3570,         /* DRV OP MODE */
 143         0x3850,         /* FLASH LOCK */
 144         0x3854,         /* FLASH UNLOCK */
 145 };
 146
 147 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
 148         .read_crb                       = qlcnic_83xx_read_crb,
 149         .write_crb                      = qlcnic_83xx_write_crb,
 150         .read_reg                       = qlcnic_83xx_rd_reg_indirect,
 151         .write_reg                      = qlcnic_83xx_wrt_reg_indirect,
 152         .get_mac_address                = qlcnic_83xx_get_mac_address,
 153         .setup_intr                     = qlcnic_83xx_setup_intr,
 154         .alloc_mbx_args                 = qlcnic_83xx_alloc_mbx_args,
 155         .mbx_cmd                        = qlcnic_83xx_issue_cmd,
 156         .get_func_no                    = qlcnic_83xx_get_func_no,
 157         .api_lock                       = qlcnic_83xx_cam_lock,
 158         .api_unlock                     = qlcnic_83xx_cam_unlock,
 159         .add_sysfs                      = qlcnic_83xx_add_sysfs,
 160         .remove_sysfs                   = qlcnic_83xx_remove_sysfs,
 161         .process_lb_rcv_ring_diag       = qlcnic_83xx_process_rcv_ring_diag,
 162         .create_rx_ctx                  = qlcnic_83xx_create_rx_ctx,
 163         .create_tx_ctx                  = qlcnic_83xx_create_tx_ctx,
 164         .del_rx_ctx                     = qlcnic_83xx_del_rx_ctx,
 165         .del_tx_ctx                     = qlcnic_83xx_del_tx_ctx,
 166         .setup_link_event               = qlcnic_83xx_setup_link_event,
 167         .get_nic_info                   = qlcnic_83xx_get_nic_info,
 168         .get_pci_info                   = qlcnic_83xx_get_pci_info,
 169         .set_nic_info                   = qlcnic_83xx_set_nic_info,
 170         .change_macvlan                 = qlcnic_83xx_sre_macaddr_change,
 171         .napi_enable                    = qlcnic_83xx_napi_enable,
 172         .napi_disable                   = qlcnic_83xx_napi_disable,
 173         .config_intr_coal               = qlcnic_83xx_config_intr_coal,
 174         .config_rss                     = qlcnic_83xx_config_rss,
 175         .config_hw_lro                  = qlcnic_83xx_config_hw_lro,
 176         .config_promisc_mode            = qlcnic_83xx_nic_set_promisc,
 177         .change_l2_filter               = qlcnic_83xx_change_l2_filter,
 178         .get_board_info                 = qlcnic_83xx_get_port_info,
 179         .set_mac_filter_count           = qlcnic_83xx_set_mac_filter_count,
 180         .free_mac_list                  = qlcnic_82xx_free_mac_list,
 181         .io_error_detected              = qlcnic_83xx_io_error_detected,
 182         .io_slot_reset                  = qlcnic_83xx_io_slot_reset,
 183         .io_resume                      = qlcnic_83xx_io_resume,
 184
 185 };
 186
 187 static struct qlcnic_nic_template qlcnic_83xx_ops = {
 188         .config_bridged_mode    = qlcnic_config_bridged_mode,
 189         .config_led             = qlcnic_config_led,
 190         .request_reset          = qlcnic_83xx_idc_request_reset,
 191         .cancel_idc_work        = qlcnic_83xx_idc_exit,
 192         .napi_add               = qlcnic_83xx_napi_add,
 193         .napi_del               = qlcnic_83xx_napi_del,
 194         .config_ipaddr          = qlcnic_83xx_config_ipaddr,
 195         .clear_legacy_intr      = qlcnic_83xx_clear_legacy_intr,
 196         .shutdown               = qlcnic_83xx_shutdown,
 197         .resume                 = qlcnic_83xx_resume,
 198 };
 199
 200 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
 201 {
 202         ahw->hw_ops             = &qlcnic_83xx_hw_ops;
 203         ahw->reg_tbl            = (u32 *)qlcnic_83xx_reg_tbl;
 204         ahw->ext_reg_tbl        = (u32 *)qlcnic_83xx_ext_reg_tbl;
 205 }
 206
 207 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
 208 {
 209         u32 fw_major, fw_minor, fw_build;
 210         struct pci_dev *pdev = adapter->pdev;
 211
 212         fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
 213         fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
 214         fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
 215         adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
 216
 217         dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
 218                  QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
 219
 220         return adapter->fw_version;
 221 }
 222
 223 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
 224 {
 225         void __iomem *base;
 226         u32 val;
 227
 228         base = adapter->ahw->pci_base0 +
 229                QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
 230         writel(addr, base);
 231         val = readl(base);
 232         if (val != addr)
 233                 return -EIO;
 234
 235         return 0;
 236 }
 237
 238 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 239                                 int *err)
 240 {
 241         struct qlcnic_hardware_context *ahw = adapter->ahw;
 242
 243         *err = __qlcnic_set_win_base(adapter, (u32) addr);
 244         if (!*err) {
 245                 return QLCRDX(ahw, QLCNIC_WILDCARD);
 246         } else {
 247                 dev_err(&adapter->pdev->dev,
 248                         "%s failed, addr = 0x%lx\n", __func__, addr);
 249                 return -EIO;
 250         }
 251 }
 252
 253 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 254                                  u32 data)
 255 {
 256         int err;
 257         struct qlcnic_hardware_context *ahw = adapter->ahw;
 258
 259         err = __qlcnic_set_win_base(adapter, (u32) addr);
 260         if (!err) {
 261                 QLCWRX(ahw, QLCNIC_WILDCARD, data);
 262                 return 0;
 263         } else {
 264                 dev_err(&adapter->pdev->dev,
 265                         "%s failed, addr = 0x%x data = 0x%x\n",
 266                         __func__, (int)addr, data);
 267                 return err;
 268         }
 269 }
 270
 271 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
 272 {
 273         int err, i, num_msix;
 274         struct qlcnic_hardware_context *ahw = adapter->ahw;
 275
 276         num_msix = adapter->drv_sds_rings;
 277
 278         /* account for AEN interrupt MSI-X based interrupts */
 279         num_msix += 1;
 280
 281         if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
 282                 num_msix += adapter->drv_tx_rings;
 283
 284         err = qlcnic_enable_msix(adapter, num_msix);
 285         if (err == -ENOMEM)
 286                 return err;
 287         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 288                 num_msix = adapter->ahw->num_msix;
 289         else {
 290                 if (qlcnic_sriov_vf_check(adapter))
 291                         return -EINVAL;
 292                 num_msix = 1;
 293                 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
 294         }
 295         /* setup interrupt mapping table for fw */
 296         ahw->intr_tbl = vzalloc(num_msix *
 297                                 sizeof(struct qlcnic_intrpt_config));
 298         if (!ahw->intr_tbl)
 299                 return -ENOMEM;
 300         if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
 301                 /* MSI-X enablement failed, use legacy interrupt */
 302                 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
 303                 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
 304                 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
 305                 adapter->msix_entries[0].vector = adapter->pdev->irq;
 306                 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
 307         }
 308
 309         for (i = 0; i < num_msix; i++) {
 310                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
 311                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
 312                 else
 313                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
 314                 ahw->intr_tbl[i].id = i;
 315                 ahw->intr_tbl[i].src = 0;
 316         }
 317         return 0;
 318 }
 319
 320 static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
 321 {
 322         writel(0, adapter->tgt_mask_reg);
 323 }
 324
 325 static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
 326 {
 327         if (adapter->tgt_mask_reg)
 328                 writel(1, adapter->tgt_mask_reg);
 329 }
 330
 331 /* Enable MSI-x and INT-x interrupts */
 332 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
 333                              struct qlcnic_host_sds_ring *sds_ring)
 334 {
 335         writel(0, sds_ring->crb_intr_mask);
 336 }
 337
 338 /* Disable MSI-x and INT-x interrupts */
 339 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
 340                               struct qlcnic_host_sds_ring *sds_ring)
 341 {
 342         writel(1, sds_ring->crb_intr_mask);
 343 }
 344
 345 static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
 346                                                     *adapter)
 347 {
 348         u32 mask;
 349
 350         /* Mailbox in MSI-x mode and Legacy Interrupt share the same
 351          * source register. We could be here before contexts are created
 352          * and sds_ring->crb_intr_mask has not been initialized, calculate
 353          * BAR offset for Interrupt Source Register
 354          */
 355         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 356         writel(0, adapter->ahw->pci_base0 + mask);
 357 }
 358
 359 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
 360 {
 361         u32 mask;
 362
 363         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 364         writel(1, adapter->ahw->pci_base0 + mask);
 365         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
 366 }
 367
 368 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
 369                                      struct qlcnic_cmd_args *cmd)
 370 {
 371         int i;
 372
 373         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 374                 return;
 375
 376         for (i = 0; i < cmd->rsp.num; i++)
 377                 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
 378 }
 379
 380 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
 381 {
 382         u32 intr_val;
 383         struct qlcnic_hardware_context *ahw = adapter->ahw;
 384         int retries = 0;
 385
 386         intr_val = readl(adapter->tgt_status_reg);
 387
 388         if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
 389                 return IRQ_NONE;
 390
 391         if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
 392                 adapter->stats.spurious_intr++;
 393                 return IRQ_NONE;
 394         }
 395         /* The barrier is required to ensure writes to the registers */
 396         wmb();
 397
 398         /* clear the interrupt trigger control register */
 399         writel(0, adapter->isr_int_vec);
 400         intr_val = readl(adapter->isr_int_vec);
 401         do {
 402                 intr_val = readl(adapter->tgt_status_reg);
 403                 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
 404                         break;
 405                 retries++;
 406         } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
 407                  (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
 408
 409         return IRQ_HANDLED;
 410 }
 411
 412 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
 413 {
 414         atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
 415         complete(&mbx->completion);
 416 }
 417
 418 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
 419 {
 420         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 421         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 422         unsigned long flags;
 423
 424         spin_lock_irqsave(&mbx->aen_lock, flags);
 425         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
 426         if (!(resp & QLCNIC_SET_OWNER))
 427                 goto out;
 428
 429         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
 430         if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 431                 __qlcnic_83xx_process_aen(adapter);
 432         } else {
 433                 if (atomic_read(&mbx->rsp_status) != rsp_status)
 434                         qlcnic_83xx_notify_mbx_response(mbx);
 435         }
 436 out:
 437         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 438         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 439 }
 440
 441 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
 442 {
 443         struct qlcnic_adapter *adapter = data;
 444         struct qlcnic_host_sds_ring *sds_ring;
 445         struct qlcnic_hardware_context *ahw = adapter->ahw;
 446
 447         if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
 448                 return IRQ_NONE;
 449
 450         qlcnic_83xx_poll_process_aen(adapter);
 451
 452         if (ahw->diag_test) {
 453                 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
 454                         ahw->diag_cnt++;
 455                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 456                 return IRQ_HANDLED;
 457         }
 458
 459         if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
 460                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 461         } else {
 462                 sds_ring = &adapter->recv_ctx->sds_rings[0];
 463                 napi_schedule(&sds_ring->napi);
 464         }
 465
 466         return IRQ_HANDLED;
 467 }
 468
 469 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
 470 {
 471         struct qlcnic_host_sds_ring *sds_ring = data;
 472         struct qlcnic_adapter *adapter = sds_ring->adapter;
 473
 474         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 475                 goto done;
 476
 477         if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
 478                 return IRQ_NONE;
 479
 480 done:
 481         adapter->ahw->diag_cnt++;
 482         qlcnic_83xx_enable_intr(adapter, sds_ring);
 483
 484         return IRQ_HANDLED;
 485 }
 486
 487 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
 488 {
 489         u32 num_msix;
 490
 491         if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
 492                 qlcnic_83xx_set_legacy_intr_mask(adapter);
 493
 494         qlcnic_83xx_disable_mbx_intr(adapter);
 495
 496         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 497                 num_msix = adapter->ahw->num_msix - 1;
 498         else
 499                 num_msix = 0;
 500
 501         msleep(20);
 502
 503         if (adapter->msix_entries) {
 504                 synchronize_irq(adapter->msix_entries[num_msix].vector);
 505                 free_irq(adapter->msix_entries[num_msix].vector, adapter);
 506         }
 507 }
 508
 509 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
 510 {
 511         irq_handler_t handler;
 512         u32 val;
 513         int err = 0;
 514         unsigned long flags = 0;
 515
 516         if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
 517             !(adapter->flags & QLCNIC_MSIX_ENABLED))
 518                 flags |= IRQF_SHARED;
 519
 520         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 521                 handler = qlcnic_83xx_handle_aen;
 522                 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
 523                 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
 524                 if (err) {
 525                         dev_err(&adapter->pdev->dev,
 526                                 "failed to register MBX interrupt\n");
 527                         return err;
 528                 }
 529         } else {
 530                 handler = qlcnic_83xx_intr;
 531                 val = adapter->msix_entries[0].vector;
 532                 err = request_irq(val, handler, flags, "qlcnic", adapter);
 533                 if (err) {
 534                         dev_err(&adapter->pdev->dev,
 535                                 "failed to register INTx interrupt\n");
 536                         return err;
 537                 }
 538                 qlcnic_83xx_clear_legacy_intr_mask(adapter);
 539         }
 540
 541         /* Enable mailbox interrupt */
 542         qlcnic_83xx_enable_mbx_interrupt(adapter);
 543
 544         return err;
 545 }
 546
 547 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
 548 {
 549         u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
 550         adapter->ahw->pci_func = (val >> 24) & 0xff;
 551 }
 552
 553 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
 554 {
 555         void __iomem *addr;
 556         u32 val, limit = 0;
 557
 558         struct qlcnic_hardware_context *ahw = adapter->ahw;
 559
 560         addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
 561         do {
 562                 val = readl(addr);
 563                 if (val) {
 564                         /* write the function number to register */
 565                         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
 566                                             ahw->pci_func);
 567                         return 0;
 568                 }
 569                 usleep_range(1000, 2000);
 570         } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
 571
 572         return -EIO;
 573 }
 574
 575 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
 576 {
 577         void __iomem *addr;
 578         u32 val;
 579         struct qlcnic_hardware_context *ahw = adapter->ahw;
 580
 581         addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
 582         val = readl(addr);
 583 }
 584
 585 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
 586                           loff_t offset, size_t size)
 587 {
 588         int ret = 0;
 589         u32 data;
 590
 591         if (qlcnic_api_lock(adapter)) {
 592                 dev_err(&adapter->pdev->dev,
 593                         "%s: failed to acquire lock. addr offset 0x%x\n",
 594                         __func__, (u32)offset);
 595                 return;
 596         }
 597
 598         data = QLCRD32(adapter, (u32) offset, &ret);
 599         qlcnic_api_unlock(adapter);
 600
 601         if (ret == -EIO) {
 602                 dev_err(&adapter->pdev->dev,
 603                         "%s: failed. addr offset 0x%x\n",
 604                         __func__, (u32)offset);
 605                 return;
 606         }
 607         memcpy(buf, &data, size);
 608 }
 609
 610 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
 611                            loff_t offset, size_t size)
 612 {
 613         u32 data;
 614
 615         memcpy(&data, buf, size);
 616         qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
 617 }
 618
 619 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
 620 {
 621         int status;
 622
 623         status = qlcnic_83xx_get_port_config(adapter);
 624         if (status) {
 625                 dev_err(&adapter->pdev->dev,
 626                         "Get Port Info failed\n");
 627         } else {
 628                 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
 629                         adapter->ahw->port_type = QLCNIC_XGBE;
 630                 else
 631                         adapter->ahw->port_type = QLCNIC_GBE;
 632
 633                 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
 634                         adapter->ahw->link_autoneg = AUTONEG_ENABLE;
 635         }
 636         return status;
 637 }
 638
 639 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
 640 {
 641         struct qlcnic_hardware_context *ahw = adapter->ahw;
 642         u16 act_pci_fn = ahw->total_nic_func;
 643         u16 count;
 644
 645         ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
 646         if (act_pci_fn <= 2)
 647                 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
 648                          act_pci_fn;
 649         else
 650                 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
 651                          act_pci_fn;
 652         ahw->max_uc_count = count;
 653 }
 654
 655 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
 656 {
 657         u32 val;
 658
 659         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 660                 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
 661         else
 662                 val = BIT_2;
 663
 664         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
 665         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 666 }
 667
 668 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
 669                           const struct pci_device_id *ent)
 670 {
 671         u32 op_mode, priv_level;
 672         struct qlcnic_hardware_context *ahw = adapter->ahw;
 673
 674         ahw->fw_hal_version = 2;
 675         qlcnic_get_func_no(adapter);
 676
 677         if (qlcnic_sriov_vf_check(adapter)) {
 678                 qlcnic_sriov_vf_set_ops(adapter);
 679                 return;
 680         }
 681
 682         /* Determine function privilege level */
 683         op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
 684         if (op_mode == QLC_83XX_DEFAULT_OPMODE)
 685                 priv_level = QLCNIC_MGMT_FUNC;
 686         else
 687                 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
 688                                                          ahw->pci_func);
 689
 690         if (priv_level == QLCNIC_NON_PRIV_FUNC) {
 691                 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
 692                 dev_info(&adapter->pdev->dev,
 693                          "HAL Version: %d Non Privileged function\n",
 694                          ahw->fw_hal_version);
 695                 adapter->nic_ops = &qlcnic_vf_ops;
 696         } else {
 697                 if (pci_find_ext_capability(adapter->pdev,
 698                                             PCI_EXT_CAP_ID_SRIOV))
 699                         set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
 700                 adapter->nic_ops = &qlcnic_83xx_ops;
 701         }
 702 }
 703
 704 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
 705                                         u32 data[]);
 706 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 707                                             u32 data[]);
 708
 709 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
 710                      struct qlcnic_cmd_args *cmd)
 711 {
 712         int i;
 713
 714         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 715                 return;
 716
 717         dev_info(&adapter->pdev->dev,
 718                  "Host MBX regs(%d)\n", cmd->req.num);
 719         for (i = 0; i < cmd->req.num; i++) {
 720                 if (i && !(i % 8))
 721                         pr_info("\n");
 722                 pr_info("%08x ", cmd->req.arg[i]);
 723         }
 724         pr_info("\n");
 725         dev_info(&adapter->pdev->dev,
 726                  "FW MBX regs(%d)\n", cmd->rsp.num);
 727         for (i = 0; i < cmd->rsp.num; i++) {
 728                 if (i && !(i % 8))
 729                         pr_info("\n");
 730                 pr_info("%08x ", cmd->rsp.arg[i]);
 731         }
 732         pr_info("\n");
 733 }
 734
 735 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
 736                                                 struct qlcnic_cmd_args *cmd)
 737 {
 738         struct qlcnic_hardware_context *ahw = adapter->ahw;
 739         int opcode = LSW(cmd->req.arg[0]);
 740         unsigned long max_loops;
 741
 742         max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
 743
 744         for (; max_loops; max_loops--) {
 745                 if (atomic_read(&cmd->rsp_status) ==
 746                     QLC_83XX_MBX_RESPONSE_ARRIVED)
 747                         return;
 748
 749                 udelay(1);
 750         }
 751
 752         dev_err(&adapter->pdev->dev,
 753                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 754                 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
 755         flush_workqueue(ahw->mailbox->work_q);
 756         return;
 757 }
 758
 759 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
 760                           struct qlcnic_cmd_args *cmd)
 761 {
 762         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 763         struct qlcnic_hardware_context *ahw = adapter->ahw;
 764         int cmd_type, err, opcode;
 765         unsigned long timeout;
 766
 767         if (!mbx)
 768                 return -EIO;
 769
 770         opcode = LSW(cmd->req.arg[0]);
 771         cmd_type = cmd->type;
 772         err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
 773         if (err) {
 774                 dev_err(&adapter->pdev->dev,
 775                         "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 776                         __func__, opcode, cmd->type, ahw->pci_func,
 777                         ahw->op_mode);
 778                 return err;
 779         }
 780
 781         switch (cmd_type) {
 782         case QLC_83XX_MBX_CMD_WAIT:
 783                 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
 784                         dev_err(&adapter->pdev->dev,
 785                                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 786                                 __func__, opcode, cmd_type, ahw->pci_func,
 787                                 ahw->op_mode);
 788                         flush_workqueue(mbx->work_q);
 789                 }
 790                 break;
 791         case QLC_83XX_MBX_CMD_NO_WAIT:
 792                 return 0;
 793         case QLC_83XX_MBX_CMD_BUSY_WAIT:
 794                 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
 795                 break;
 796         default:
 797                 dev_err(&adapter->pdev->dev,
 798                         "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 799                         __func__, opcode, cmd_type, ahw->pci_func,
 800                         ahw->op_mode);
 801                 qlcnic_83xx_detach_mailbox_work(adapter);
 802         }
 803
 804         return cmd->rsp_opcode;
 805 }
 806
 807 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
 808                                struct qlcnic_adapter *adapter, u32 type)
 809 {
 810         int i, size;
 811         u32 temp;
 812         const struct qlcnic_mailbox_metadata *mbx_tbl;
 813
 814         memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
 815         mbx_tbl = qlcnic_83xx_mbx_tbl;
 816         size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
 817         for (i = 0; i < size; i++) {
 818                 if (type == mbx_tbl[i].cmd) {
 819                         mbx->op_type = QLC_83XX_FW_MBX_CMD;
 820                         mbx->req.num = mbx_tbl[i].in_args;
 821                         mbx->rsp.num = mbx_tbl[i].out_args;
 822                         mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
 823                                                GFP_ATOMIC);
 824                         if (!mbx->req.arg)
 825                                 return -ENOMEM;
 826                         mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
 827                                                GFP_ATOMIC);
 828                         if (!mbx->rsp.arg) {
 829                                 kfree(mbx->req.arg);
 830                                 mbx->req.arg = NULL;
 831                                 return -ENOMEM;
 832                         }
 833                         memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
 834                         memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
 835                         temp = adapter->ahw->fw_hal_version << 29;
 836                         mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
 837                         mbx->cmd_op = type;
 838                         return 0;
 839                 }
 840         }
 841         return -EINVAL;
 842 }
 843
 844 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
 845 {
 846         struct qlcnic_adapter *adapter;
 847         struct qlcnic_cmd_args cmd;
 848         int i, err = 0;
 849
 850         adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
 851         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
 852         if (err)
 853                 return;
 854
 855         for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
 856                 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
 857
 858         err = qlcnic_issue_cmd(adapter, &cmd);
 859         if (err)
 860                 dev_info(&adapter->pdev->dev,
 861                          "%s: Mailbox IDC ACK failed.\n", __func__);
 862         qlcnic_free_mbx_args(&cmd);
 863 }
 864
 865 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 866                                             u32 data[])
 867 {
 868         dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
 869                 QLCNIC_MBX_RSP(data[0]));
 870         clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
 871         return;
 872 }
 873
 874 void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 875 {
 876         struct qlcnic_hardware_context *ahw = adapter->ahw;
 877         u32 event[QLC_83XX_MBX_AEN_CNT];
 878         int i;
 879
 880         for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 881                 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
 882
 883         switch (QLCNIC_MBX_RSP(event[0])) {
 884
 885         case QLCNIC_MBX_LINK_EVENT:
 886                 qlcnic_83xx_handle_link_aen(adapter, event);
 887                 break;
 888         case QLCNIC_MBX_COMP_EVENT:
 889                 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
 890                 break;
 891         case QLCNIC_MBX_REQUEST_EVENT:
 892                 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 893                         adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
 894                 queue_delayed_work(adapter->qlcnic_wq,
 895                                    &adapter->idc_aen_work, 0);
 896                 break;
 897         case QLCNIC_MBX_TIME_EXTEND_EVENT:
 898                 ahw->extend_lb_time = event[1] >> 8 & 0xf;
 899                 break;
 900         case QLCNIC_MBX_BC_EVENT:
 901                 qlcnic_sriov_handle_bc_event(adapter, event[1]);
 902                 break;
 903         case QLCNIC_MBX_SFP_INSERT_EVENT:
 904                 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
 905                          QLCNIC_MBX_RSP(event[0]));
 906                 break;
 907         case QLCNIC_MBX_SFP_REMOVE_EVENT:
 908                 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
 909                          QLCNIC_MBX_RSP(event[0]));
 910                 break;
 911         case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
 912                 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
 913                 break;
 914         default:
 915                 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
 916                         QLCNIC_MBX_RSP(event[0]));
 917                 break;
 918         }
 919
 920         QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
 921 }
 922
 923 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 924 {
 925         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 926         struct qlcnic_hardware_context *ahw = adapter->ahw;
 927         struct qlcnic_mailbox *mbx = ahw->mailbox;
 928         unsigned long flags;
 929
 930         spin_lock_irqsave(&mbx->aen_lock, flags);
 931         resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
 932         if (resp & QLCNIC_SET_OWNER) {
 933                 event = readl(QLCNIC_MBX_FW(ahw, 0));
 934                 if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 935                         __qlcnic_83xx_process_aen(adapter);
 936                 } else {
 937                         if (atomic_read(&mbx->rsp_status) != rsp_status)
 938                                 qlcnic_83xx_notify_mbx_response(mbx);
 939                 }
 940         }
 941         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 942 }
 943
 944 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
 945 {
 946         struct qlcnic_adapter *adapter;
 947
 948         adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
 949
 950         if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 951                 return;
 952
 953         qlcnic_83xx_process_aen(adapter);
 954         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
 955                            (HZ / 10));
 956 }
 957
 958 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
 959 {
 960         if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 961                 return;
 962
 963         INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
 964         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
 965 }
 966
 967 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
 968 {
 969         if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 970                 return;
 971         cancel_delayed_work_sync(&adapter->mbx_poll_work);
 972 }
 973
 974 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
 975 {
 976         int index, i, err, sds_mbx_size;
 977         u32 *buf, intrpt_id, intr_mask;
 978         u16 context_id;
 979         u8 num_sds;
 980         struct qlcnic_cmd_args cmd;
 981         struct qlcnic_host_sds_ring *sds;
 982         struct qlcnic_sds_mbx sds_mbx;
 983         struct qlcnic_add_rings_mbx_out *mbx_out;
 984         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
 985         struct qlcnic_hardware_context *ahw = adapter->ahw;
 986
 987         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
 988         context_id = recv_ctx->context_id;
 989         num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
 990         ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
 991                                     QLCNIC_CMD_ADD_RCV_RINGS);
 992         cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
 993
 994         /* set up status rings, mbx 2-81 */
 995         index = 2;
 996         for (i = 8; i < adapter->drv_sds_rings; i++) {
 997                 memset(&sds_mbx, 0, sds_mbx_size);
 998                 sds = &recv_ctx->sds_rings[i];
 999                 sds->consumer = 0;
1000                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1001                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1002                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1003                 sds_mbx.sds_ring_size = sds->num_desc;
1004
1005                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1006                         intrpt_id = ahw->intr_tbl[i].id;
1007                 else
1008                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1009
1010                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1011                         sds_mbx.intrpt_id = intrpt_id;
1012                 else
1013                         sds_mbx.intrpt_id = 0xffff;
1014                 sds_mbx.intrpt_val = 0;
1015                 buf = &cmd.req.arg[index];
1016                 memcpy(buf, &sds_mbx, sds_mbx_size);
1017                 index += sds_mbx_size / sizeof(u32);
1018         }
1019
1020         /* send the mailbox command */
1021         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1022         if (err) {
1023                 dev_err(&adapter->pdev->dev,
1024                         "Failed to add rings %d\n", err);
1025                 goto out;
1026         }
1027
1028         mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1029         index = 0;
1030         /* status descriptor ring */
1031         for (i = 8; i < adapter->drv_sds_rings; i++) {
1032                 sds = &recv_ctx->sds_rings[i];
1033                 sds->crb_sts_consumer = ahw->pci_base0 +
1034                                         mbx_out->host_csmr[index];
1035                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1036                         intr_mask = ahw->intr_tbl[i].src;
1037                 else
1038                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1039
1040                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1041                 index++;
1042         }
1043 out:
1044         qlcnic_free_mbx_args(&cmd);
1045         return err;
1046 }
1047
1048 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1049 {
1050         int err;
1051         u32 temp = 0;
1052         struct qlcnic_cmd_args cmd;
1053         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1054
1055         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1056                 return;
1057
1058         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1059                 cmd.req.arg[0] |= (0x3 << 29);
1060
1061         if (qlcnic_sriov_pf_check(adapter))
1062                 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1063
1064         cmd.req.arg[1] = recv_ctx->context_id | temp;
1065         err = qlcnic_issue_cmd(adapter, &cmd);
1066         if (err)
1067                 dev_err(&adapter->pdev->dev,
1068                         "Failed to destroy rx ctx in firmware\n");
1069
1070         recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1071         qlcnic_free_mbx_args(&cmd);
1072 }
1073
1074 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1075 {
1076         int i, err, index, sds_mbx_size, rds_mbx_size;
1077         u8 num_sds, num_rds;
1078         u32 *buf, intrpt_id, intr_mask, cap = 0;
1079         struct qlcnic_host_sds_ring *sds;
1080         struct qlcnic_host_rds_ring *rds;
1081         struct qlcnic_sds_mbx sds_mbx;
1082         struct qlcnic_rds_mbx rds_mbx;
1083         struct qlcnic_cmd_args cmd;
1084         struct qlcnic_rcv_mbx_out *mbx_out;
1085         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1086         struct qlcnic_hardware_context *ahw = adapter->ahw;
1087         num_rds = adapter->max_rds_rings;
1088
1089         if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1090                 num_sds = adapter->drv_sds_rings;
1091         else
1092                 num_sds = QLCNIC_MAX_SDS_RINGS;
1093
1094         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1095         rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1096         cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1097
1098         if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1099                 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1100
1101         /* set mailbox hdr and capabilities */
1102         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1103                                     QLCNIC_CMD_CREATE_RX_CTX);
1104         if (err)
1105                 return err;
1106
1107         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1108                 cmd.req.arg[0] |= (0x3 << 29);
1109
1110         cmd.req.arg[1] = cap;
1111         cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1112                          (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1113
1114         if (qlcnic_sriov_pf_check(adapter))
1115                 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1116                                                          &cmd.req.arg[6]);
1117         /* set up status rings, mbx 8-57/87 */
1118         index = QLC_83XX_HOST_SDS_MBX_IDX;
1119         for (i = 0; i < num_sds; i++) {
1120                 memset(&sds_mbx, 0, sds_mbx_size);
1121                 sds = &recv_ctx->sds_rings[i];
1122                 sds->consumer = 0;
1123                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1124                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1125                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1126                 sds_mbx.sds_ring_size = sds->num_desc;
1127                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1128                         intrpt_id = ahw->intr_tbl[i].id;
1129                 else
1130                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1131                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1132                         sds_mbx.intrpt_id = intrpt_id;
1133                 else
1134                         sds_mbx.intrpt_id = 0xffff;
1135                 sds_mbx.intrpt_val = 0;
1136                 buf = &cmd.req.arg[index];
1137                 memcpy(buf, &sds_mbx, sds_mbx_size);
1138                 index += sds_mbx_size / sizeof(u32);
1139         }
1140         /* set up receive rings, mbx 88-111/135 */
1141         index = QLCNIC_HOST_RDS_MBX_IDX;
1142         rds = &recv_ctx->rds_rings[0];
1143         rds->producer = 0;
1144         memset(&rds_mbx, 0, rds_mbx_size);
1145         rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1146         rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1147         rds_mbx.reg_ring_sz = rds->dma_size;
1148         rds_mbx.reg_ring_len = rds->num_desc;
1149         /* Jumbo ring */
1150         rds = &recv_ctx->rds_rings[1];
1151         rds->producer = 0;
1152         rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1153         rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1154         rds_mbx.jmb_ring_sz = rds->dma_size;
1155         rds_mbx.jmb_ring_len = rds->num_desc;
1156         buf = &cmd.req.arg[index];
1157         memcpy(buf, &rds_mbx, rds_mbx_size);
1158
1159         /* send the mailbox command */
1160         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1161         if (err) {
1162                 dev_err(&adapter->pdev->dev,
1163                         "Failed to create Rx ctx in firmware%d\n", err);
1164                 goto out;
1165         }
1166         mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1167         recv_ctx->context_id = mbx_out->ctx_id;
1168         recv_ctx->state = mbx_out->state;
1169         recv_ctx->virt_port = mbx_out->vport_id;
1170         dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1171                  recv_ctx->context_id, recv_ctx->state);
1172         /* Receive descriptor ring */
1173         /* Standard ring */
1174         rds = &recv_ctx->rds_rings[0];
1175         rds->crb_rcv_producer = ahw->pci_base0 +
1176                                 mbx_out->host_prod[0].reg_buf;
1177         /* Jumbo ring */
1178         rds = &recv_ctx->rds_rings[1];
1179         rds->crb_rcv_producer = ahw->pci_base0 +
1180                                 mbx_out->host_prod[0].jmb_buf;
1181         /* status descriptor ring */
1182         for (i = 0; i < num_sds; i++) {
1183                 sds = &recv_ctx->sds_rings[i];
1184                 sds->crb_sts_consumer = ahw->pci_base0 +
1185                                         mbx_out->host_csmr[i];
1186                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1187                         intr_mask = ahw->intr_tbl[i].src;
1188                 else
1189                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1190                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1191         }
1192
1193         if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1194                 err = qlcnic_83xx_add_rings(adapter);
1195 out:
1196         qlcnic_free_mbx_args(&cmd);
1197         return err;
1198 }
1199
1200 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1201                             struct qlcnic_host_tx_ring *tx_ring)
1202 {
1203         struct qlcnic_cmd_args cmd;
1204         u32 temp = 0;
1205
1206         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1207                 return;
1208
1209         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1210                 cmd.req.arg[0] |= (0x3 << 29);
1211
1212         if (qlcnic_sriov_pf_check(adapter))
1213                 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1214
1215         cmd.req.arg[1] = tx_ring->ctx_id | temp;
1216         if (qlcnic_issue_cmd(adapter, &cmd))
1217                 dev_err(&adapter->pdev->dev,
1218                         "Failed to destroy tx ctx in firmware\n");
1219         qlcnic_free_mbx_args(&cmd);
1220 }
1221
1222 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1223                               struct qlcnic_host_tx_ring *tx, int ring)
1224 {
1225         int err;
1226         u16 msix_id;
1227         u32 *buf, intr_mask, temp = 0;
1228         struct qlcnic_cmd_args cmd;
1229         struct qlcnic_tx_mbx mbx;
1230         struct qlcnic_tx_mbx_out *mbx_out;
1231         struct qlcnic_hardware_context *ahw = adapter->ahw;
1232         u32 msix_vector;
1233
1234         /* Reset host resources */
1235         tx->producer = 0;
1236         tx->sw_consumer = 0;
1237         *(tx->hw_consumer) = 0;
1238
1239         memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1240
1241         /* setup mailbox inbox registerss */
1242         mbx.phys_addr_low = LSD(tx->phys_addr);
1243         mbx.phys_addr_high = MSD(tx->phys_addr);
1244         mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1245         mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1246         mbx.size = tx->num_desc;
1247         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1248                 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1249                         msix_vector = adapter->drv_sds_rings + ring;
1250                 else
1251                         msix_vector = adapter->drv_sds_rings - 1;
1252                 msix_id = ahw->intr_tbl[msix_vector].id;
1253         } else {
1254                 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1255         }
1256
1257         if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1258                 mbx.intr_id = msix_id;
1259         else
1260                 mbx.intr_id = 0xffff;
1261         mbx.src = 0;
1262
1263         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1264         if (err)
1265                 return err;
1266
1267         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1268                 cmd.req.arg[0] |= (0x3 << 29);
1269
1270         if (qlcnic_sriov_pf_check(adapter))
1271                 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1272
1273         cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1274         cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1275
1276         buf = &cmd.req.arg[6];
1277         memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1278         /* send the mailbox command*/
1279         err = qlcnic_issue_cmd(adapter, &cmd);
1280         if (err) {
1281                 dev_err(&adapter->pdev->dev,
1282                         "Failed to create Tx ctx in firmware 0x%x\n", err);
1283                 goto out;
1284         }
1285         mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1286         tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1287         tx->ctx_id = mbx_out->ctx_id;
1288         if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1289             !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1290                 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1291                 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1292         }
1293         dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1294                  tx->ctx_id, mbx_out->state);
1295 out:
1296         qlcnic_free_mbx_args(&cmd);
1297         return err;
1298 }
1299
1300 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1301                                       u8 num_sds_ring)
1302 {
1303         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1304         struct qlcnic_host_sds_ring *sds_ring;
1305         struct qlcnic_host_rds_ring *rds_ring;
1306         u16 adapter_state = adapter->is_up;
1307         u8 ring;
1308         int ret;
1309
1310         netif_device_detach(netdev);
1311
1312         if (netif_running(netdev))
1313                 __qlcnic_down(adapter, netdev);
1314
1315         qlcnic_detach(adapter);
1316
1317         adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1318         adapter->ahw->diag_test = test;
1319         adapter->ahw->linkup = 0;
1320
1321         ret = qlcnic_attach(adapter);
1322         if (ret) {
1323                 netif_device_attach(netdev);
1324                 return ret;
1325         }
1326
1327         ret = qlcnic_fw_create_ctx(adapter);
1328         if (ret) {
1329                 qlcnic_detach(adapter);
1330                 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1331                         adapter->drv_sds_rings = num_sds_ring;
1332                         qlcnic_attach(adapter);
1333                 }
1334                 netif_device_attach(netdev);
1335                 return ret;
1336         }
1337
1338         for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1339                 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1340                 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1341         }
1342
1343         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1344                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1345                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1346                         qlcnic_83xx_enable_intr(adapter, sds_ring);
1347                 }
1348         }
1349
1350         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1351                 adapter->ahw->loopback_state = 0;
1352                 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1353         }
1354
1355         set_bit(__QLCNIC_DEV_UP, &adapter->state);
1356         return 0;
1357 }
1358
1359 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1360                                       u8 drv_sds_rings)
1361 {
1362         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1363         struct qlcnic_host_sds_ring *sds_ring;
1364         int ring;
1365
1366         clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1367         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1368                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1369                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1370                         if (adapter->flags & QLCNIC_MSIX_ENABLED)
1371                                 qlcnic_83xx_disable_intr(adapter, sds_ring);
1372                 }
1373         }
1374
1375         qlcnic_fw_destroy_ctx(adapter);
1376         qlcnic_detach(adapter);
1377
1378         adapter->ahw->diag_test = 0;
1379         adapter->drv_sds_rings = drv_sds_rings;
1380
1381         if (qlcnic_attach(adapter))
1382                 goto out;
1383
1384         if (netif_running(netdev))
1385                 __qlcnic_up(adapter, netdev);
1386
1387 out:
1388         netif_device_attach(netdev);
1389 }
1390
1391 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1392                            u32 beacon)
1393 {
1394         struct qlcnic_cmd_args cmd;
1395         u32 mbx_in;
1396         int i, status = 0;
1397
1398         if (state) {
1399                 /* Get LED configuration */
1400                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1401                                                QLCNIC_CMD_GET_LED_CONFIG);
1402                 if (status)
1403                         return status;
1404
1405                 status = qlcnic_issue_cmd(adapter, &cmd);
1406                 if (status) {
1407                         dev_err(&adapter->pdev->dev,
1408                                 "Get led config failed.\n");
1409                         goto mbx_err;
1410                 } else {
1411                         for (i = 0; i < 4; i++)
1412                                 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1413                 }
1414                 qlcnic_free_mbx_args(&cmd);
1415                 /* Set LED Configuration */
1416                 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1417                           LSW(QLC_83XX_LED_CONFIG);
1418                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1419                                                QLCNIC_CMD_SET_LED_CONFIG);
1420                 if (status)
1421                         return status;
1422
1423                 cmd.req.arg[1] = mbx_in;
1424                 cmd.req.arg[2] = mbx_in;
1425                 cmd.req.arg[3] = mbx_in;
1426                 if (beacon)
1427                         cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1428                 status = qlcnic_issue_cmd(adapter, &cmd);
1429                 if (status) {
1430                         dev_err(&adapter->pdev->dev,
1431                                 "Set led config failed.\n");
1432                 }
1433 mbx_err:
1434                 qlcnic_free_mbx_args(&cmd);
1435                 return status;
1436
1437         } else {
1438                 /* Restoring default LED configuration */
1439                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1440                                                QLCNIC_CMD_SET_LED_CONFIG);
1441                 if (status)
1442                         return status;
1443
1444                 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1445                 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1446                 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1447                 if (beacon)
1448                         cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1449                 status = qlcnic_issue_cmd(adapter, &cmd);
1450                 if (status)
1451                         dev_err(&adapter->pdev->dev,
1452                                 "Restoring led config failed.\n");
1453                 qlcnic_free_mbx_args(&cmd);
1454                 return status;
1455         }
1456 }
1457
1458 int  qlcnic_83xx_set_led(struct net_device *netdev,
1459                          enum ethtool_phys_id_state state)
1460 {
1461         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1462         int err = -EIO, active = 1;
1463
1464         if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1465                 netdev_warn(netdev,
1466                             "LED test is not supported in non-privileged mode\n");
1467                 return -EOPNOTSUPP;
1468         }
1469
1470         switch (state) {
1471         case ETHTOOL_ID_ACTIVE:
1472                 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1473                         return -EBUSY;
1474
1475                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1476                         break;
1477
1478                 err = qlcnic_83xx_config_led(adapter, active, 0);
1479                 if (err)
1480                         netdev_err(netdev, "Failed to set LED blink state\n");
1481                 break;
1482         case ETHTOOL_ID_INACTIVE:
1483                 active = 0;
1484
1485                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1486                         break;
1487
1488                 err = qlcnic_83xx_config_led(adapter, active, 0);
1489                 if (err)
1490                         netdev_err(netdev, "Failed to reset LED blink state\n");
1491                 break;
1492
1493         default:
1494                 return -EINVAL;
1495         }
1496
1497         if (!active || err)
1498                 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1499
1500         return err;
1501 }
1502
1503 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable)
1504 {
1505         struct qlcnic_cmd_args cmd;
1506         int status;
1507
1508         if (qlcnic_sriov_vf_check(adapter))
1509                 return;
1510
1511         if (enable)
1512                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1513                                                QLCNIC_CMD_INIT_NIC_FUNC);
1514         else
1515                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1516                                                QLCNIC_CMD_STOP_NIC_FUNC);
1517
1518         if (status)
1519                 return;
1520
1521         cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES;
1522
1523         if (adapter->dcb)
1524                 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1525
1526         status = qlcnic_issue_cmd(adapter, &cmd);
1527         if (status)
1528                 dev_err(&adapter->pdev->dev,
1529                         "Failed to %s in NIC IDC function event.\n",
1530                         (enable ? "register" : "unregister"));
1531
1532         qlcnic_free_mbx_args(&cmd);
1533 }
1534
1535 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1536 {
1537         struct qlcnic_cmd_args cmd;
1538         int err;
1539
1540         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1541         if (err)
1542                 return err;
1543
1544         cmd.req.arg[1] = adapter->ahw->port_config;
1545         err = qlcnic_issue_cmd(adapter, &cmd);
1546         if (err)
1547                 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1548         qlcnic_free_mbx_args(&cmd);
1549         return err;
1550 }
1551
1552 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1553 {
1554         struct qlcnic_cmd_args cmd;
1555         int err;
1556
1557         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1558         if (err)
1559                 return err;
1560
1561         err = qlcnic_issue_cmd(adapter, &cmd);
1562         if (err)
1563                 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1564         else
1565                 adapter->ahw->port_config = cmd.rsp.arg[1];
1566         qlcnic_free_mbx_args(&cmd);
1567         return err;
1568 }
1569
1570 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1571 {
1572         int err;
1573         u32 temp;
1574         struct qlcnic_cmd_args cmd;
1575
1576         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1577         if (err)
1578                 return err;
1579
1580         temp = adapter->recv_ctx->context_id << 16;
1581         cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1582         err = qlcnic_issue_cmd(adapter, &cmd);
1583         if (err)
1584                 dev_info(&adapter->pdev->dev,
1585                          "Setup linkevent mailbox failed\n");
1586         qlcnic_free_mbx_args(&cmd);
1587         return err;
1588 }
1589
1590 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1591                                                  u32 *interface_id)
1592 {
1593         if (qlcnic_sriov_pf_check(adapter)) {
1594                 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1595         } else {
1596                 if (!qlcnic_sriov_vf_check(adapter))
1597                         *interface_id = adapter->recv_ctx->context_id << 16;
1598         }
1599 }
1600
1601 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1602 {
1603         struct qlcnic_cmd_args *cmd = NULL;
1604         u32 temp = 0;
1605         int err;
1606
1607         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1608                 return -EIO;
1609
1610         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1611         if (!cmd)
1612                 return -ENOMEM;
1613
1614         err = qlcnic_alloc_mbx_args(cmd, adapter,
1615                                     QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1616         if (err)
1617                 goto out;
1618
1619         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1620         qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1621         cmd->req.arg[1] = mode | temp;
1622         err = qlcnic_issue_cmd(adapter, cmd);
1623         if (!err)
1624                 return err;
1625
1626         qlcnic_free_mbx_args(cmd);
1627
1628 out:
1629         kfree(cmd);
1630         return err;
1631 }
1632
1633 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1634 {
1635         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1636         struct qlcnic_hardware_context *ahw = adapter->ahw;
1637         u8 drv_sds_rings = adapter->drv_sds_rings;
1638         u8 drv_tx_rings = adapter->drv_tx_rings;
1639         int ret = 0, loop = 0;
1640
1641         if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1642                 netdev_warn(netdev,
1643                             "Loopback test not supported in non privileged mode\n");
1644                 return -ENOTSUPP;
1645         }
1646
1647         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1648                 netdev_info(netdev, "Device is resetting\n");
1649                 return -EBUSY;
1650         }
1651
1652         if (qlcnic_get_diag_lock(adapter)) {
1653                 netdev_info(netdev, "Device is in diagnostics mode\n");
1654                 return -EBUSY;
1655         }
1656
1657         netdev_info(netdev, "%s loopback test in progress\n",
1658                     mode == QLCNIC_ILB_MODE ? "internal" : "external");
1659
1660         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1661                                          drv_sds_rings);
1662         if (ret)
1663                 goto fail_diag_alloc;
1664
1665         ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1666         if (ret)
1667                 goto free_diag_res;
1668
1669         /* Poll for link up event before running traffic */
1670         do {
1671                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1672
1673                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1674                         netdev_info(netdev,
1675                                     "Device is resetting, free LB test resources\n");
1676                         ret = -EBUSY;
1677                         goto free_diag_res;
1678                 }
1679                 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1680                         netdev_info(netdev,
1681                                     "Firmware didn't sent link up event to loopback request\n");
1682                         ret = -ETIMEDOUT;
1683                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1684                         goto free_diag_res;
1685                 }
1686         } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1687
1688         ret = qlcnic_do_lb_test(adapter, mode);
1689
1690         qlcnic_83xx_clear_lb_mode(adapter, mode);
1691
1692 free_diag_res:
1693         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1694
1695 fail_diag_alloc:
1696         adapter->drv_sds_rings = drv_sds_rings;
1697         adapter->drv_tx_rings = drv_tx_rings;
1698         qlcnic_release_diag_lock(adapter);
1699         return ret;
1700 }
1701
1702 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1703                                              u32 *max_wait_count)
1704 {
1705         struct qlcnic_hardware_context *ahw = adapter->ahw;
1706         int temp;
1707
1708         netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1709                     ahw->extend_lb_time);
1710         temp = ahw->extend_lb_time * 1000;
1711         *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1712         ahw->extend_lb_time = 0;
1713 }
1714
1715 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1716 {
1717         struct qlcnic_hardware_context *ahw = adapter->ahw;
1718         struct net_device *netdev = adapter->netdev;
1719         u32 config, max_wait_count;
1720         int status = 0, loop = 0;
1721
1722         ahw->extend_lb_time = 0;
1723         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1724         status = qlcnic_83xx_get_port_config(adapter);
1725         if (status)
1726                 return status;
1727
1728         config = ahw->port_config;
1729
1730         /* Check if port is already in loopback mode */
1731         if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1732             (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1733                 netdev_err(netdev,
1734                            "Port already in Loopback mode.\n");
1735                 return -EINPROGRESS;
1736         }
1737
1738         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1739
1740         if (mode == QLCNIC_ILB_MODE)
1741                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1742         if (mode == QLCNIC_ELB_MODE)
1743                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1744
1745         status = qlcnic_83xx_set_port_config(adapter);
1746         if (status) {
1747                 netdev_err(netdev,
1748                            "Failed to Set Loopback Mode = 0x%x.\n",
1749                            ahw->port_config);
1750                 ahw->port_config = config;
1751                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1752                 return status;
1753         }
1754
1755         /* Wait for Link and IDC Completion AEN */
1756         do {
1757                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1758
1759                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1760                         netdev_info(netdev,
1761                                     "Device is resetting, free LB test resources\n");
1762                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1763                         return -EBUSY;
1764                 }
1765
1766                 if (ahw->extend_lb_time)
1767                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1768                                                          &max_wait_count);
1769
1770                 if (loop++ > max_wait_count) {
1771                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1772                                    __func__);
1773                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1774                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1775                         return -ETIMEDOUT;
1776                 }
1777         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1778
1779         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1780                                   QLCNIC_MAC_ADD);
1781         return status;
1782 }
1783
1784 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1785 {
1786         struct qlcnic_hardware_context *ahw = adapter->ahw;
1787         u32 config = ahw->port_config, max_wait_count;
1788         struct net_device *netdev = adapter->netdev;
1789         int status = 0, loop = 0;
1790
1791         ahw->extend_lb_time = 0;
1792         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1793         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1794         if (mode == QLCNIC_ILB_MODE)
1795                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1796         if (mode == QLCNIC_ELB_MODE)
1797                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1798
1799         status = qlcnic_83xx_set_port_config(adapter);
1800         if (status) {
1801                 netdev_err(netdev,
1802                            "Failed to Clear Loopback Mode = 0x%x.\n",
1803                            ahw->port_config);
1804                 ahw->port_config = config;
1805                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1806                 return status;
1807         }
1808
1809         /* Wait for Link and IDC Completion AEN */
1810         do {
1811                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1812
1813                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1814                         netdev_info(netdev,
1815                                     "Device is resetting, free LB test resources\n");
1816                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1817                         return -EBUSY;
1818                 }
1819
1820                 if (ahw->extend_lb_time)
1821                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1822                                                          &max_wait_count);
1823
1824                 if (loop++ > max_wait_count) {
1825                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1826                                    __func__);
1827                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1828                         return -ETIMEDOUT;
1829                 }
1830         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1831
1832         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1833                                   QLCNIC_MAC_DEL);
1834         return status;
1835 }
1836
1837 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1838                                                 u32 *interface_id)
1839 {
1840         if (qlcnic_sriov_pf_check(adapter)) {
1841                 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1842         } else {
1843                 if (!qlcnic_sriov_vf_check(adapter))
1844                         *interface_id = adapter->recv_ctx->context_id << 16;
1845         }
1846 }
1847
1848 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1849                                int mode)
1850 {
1851         int err;
1852         u32 temp = 0, temp_ip;
1853         struct qlcnic_cmd_args cmd;
1854
1855         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1856                                     QLCNIC_CMD_CONFIGURE_IP_ADDR);
1857         if (err)
1858                 return;
1859
1860         qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1861
1862         if (mode == QLCNIC_IP_UP)
1863                 cmd.req.arg[1] = 1 | temp;
1864         else
1865                 cmd.req.arg[1] = 2 | temp;
1866
1867         /*
1868          * Adapter needs IP address in network byte order.
1869          * But hardware mailbox registers go through writel(), hence IP address
1870          * gets swapped on big endian architecture.
1871          * To negate swapping of writel() on big endian architecture
1872          * use swab32(value).
1873          */
1874
1875         temp_ip = swab32(ntohl(ip));
1876         memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1877         err = qlcnic_issue_cmd(adapter, &cmd);
1878         if (err != QLCNIC_RCODE_SUCCESS)
1879                 dev_err(&adapter->netdev->dev,
1880                         "could not notify %s IP 0x%x request\n",
1881                         (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1882
1883         qlcnic_free_mbx_args(&cmd);
1884 }
1885
1886 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1887 {
1888         int err;
1889         u32 temp, arg1;
1890         struct qlcnic_cmd_args cmd;
1891         int lro_bit_mask;
1892
1893         lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1894
1895         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1896                 return 0;
1897
1898         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1899         if (err)
1900                 return err;
1901
1902         temp = adapter->recv_ctx->context_id << 16;
1903         arg1 = lro_bit_mask | temp;
1904         cmd.req.arg[1] = arg1;
1905
1906         err = qlcnic_issue_cmd(adapter, &cmd);
1907         if (err)
1908                 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1909         qlcnic_free_mbx_args(&cmd);
1910
1911         return err;
1912 }
1913
1914 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1915 {
1916         int err;
1917         u32 word;
1918         struct qlcnic_cmd_args cmd;
1919         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1920                             0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1921                             0x255b0ec26d5a56daULL };
1922
1923         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1924         if (err)
1925                 return err;
1926         /*
1927          * RSS request:
1928          * bits 3-0: Rsvd
1929          *      5-4: hash_type_ipv4
1930          *      7-6: hash_type_ipv6
1931          *        8: enable
1932          *        9: use indirection table
1933          *    16-31: indirection table mask
1934          */
1935         word =  ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1936                 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1937                 ((u32)(enable & 0x1) << 8) |
1938                 ((0x7ULL) << 16);
1939         cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1940         cmd.req.arg[2] = word;
1941         memcpy(&cmd.req.arg[4], key, sizeof(key));
1942
1943         err = qlcnic_issue_cmd(adapter, &cmd);
1944
1945         if (err)
1946                 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1947         qlcnic_free_mbx_args(&cmd);
1948
1949         return err;
1950
1951 }
1952
1953 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1954                                                  u32 *interface_id)
1955 {
1956         if (qlcnic_sriov_pf_check(adapter)) {
1957                 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1958         } else {
1959                 if (!qlcnic_sriov_vf_check(adapter))
1960                         *interface_id = adapter->recv_ctx->context_id << 16;
1961         }
1962 }
1963
1964 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1965                                    u16 vlan_id, u8 op)
1966 {
1967         struct qlcnic_cmd_args *cmd = NULL;
1968         struct qlcnic_macvlan_mbx mv;
1969         u32 *buf, temp = 0;
1970         int err;
1971
1972         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1973                 return -EIO;
1974
1975         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1976         if (!cmd)
1977                 return -ENOMEM;
1978
1979         err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
1980         if (err)
1981                 goto out;
1982
1983         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1984
1985         if (vlan_id)
1986                 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
1987                      QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
1988
1989         cmd->req.arg[1] = op | (1 << 8);
1990         qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
1991         cmd->req.arg[1] |= temp;
1992         mv.vlan = vlan_id;
1993         mv.mac_addr0 = addr[0];
1994         mv.mac_addr1 = addr[1];
1995         mv.mac_addr2 = addr[2];
1996         mv.mac_addr3 = addr[3];
1997         mv.mac_addr4 = addr[4];
1998         mv.mac_addr5 = addr[5];
1999         buf = &cmd->req.arg[2];
2000         memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2001         err = qlcnic_issue_cmd(adapter, cmd);
2002         if (!err)
2003                 return err;
2004
2005         qlcnic_free_mbx_args(cmd);
2006 out:
2007         kfree(cmd);
2008         return err;
2009 }
2010
2011 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2012                                   u16 vlan_id)
2013 {
2014         u8 mac[ETH_ALEN];
2015         memcpy(&mac, addr, ETH_ALEN);
2016         qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2017 }
2018
2019 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2020                                u8 type, struct qlcnic_cmd_args *cmd)
2021 {
2022         switch (type) {
2023         case QLCNIC_SET_STATION_MAC:
2024         case QLCNIC_SET_FAC_DEF_MAC:
2025                 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2026                 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2027                 break;
2028         }
2029         cmd->req.arg[1] = type;
2030 }
2031
2032 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2033                                 u8 function)
2034 {
2035         int err, i;
2036         struct qlcnic_cmd_args cmd;
2037         u32 mac_low, mac_high;
2038
2039         function = 0;
2040         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2041         if (err)
2042                 return err;
2043
2044         qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2045         err = qlcnic_issue_cmd(adapter, &cmd);
2046
2047         if (err == QLCNIC_RCODE_SUCCESS) {
2048                 mac_low = cmd.rsp.arg[1];
2049                 mac_high = cmd.rsp.arg[2];
2050
2051                 for (i = 0; i < 2; i++)
2052                         mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2053                 for (i = 2; i < 6; i++)
2054                         mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2055         } else {
2056                 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2057                         err);
2058                 err = -EIO;
2059         }
2060         qlcnic_free_mbx_args(&cmd);
2061         return err;
2062 }
2063
2064 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2065 {
2066         int err;
2067         u16 temp;
2068         struct qlcnic_cmd_args cmd;
2069         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2070
2071         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2072                 return;
2073
2074         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2075         if (err)
2076                 return;
2077
2078         if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2079                 temp = adapter->recv_ctx->context_id;
2080                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2081                 temp = coal->rx_time_us;
2082                 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2083         } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2084                 temp = adapter->tx_ring->ctx_id;
2085                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2086                 temp = coal->tx_time_us;
2087                 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2088         }
2089         cmd.req.arg[3] = coal->flag;
2090         err = qlcnic_issue_cmd(adapter, &cmd);
2091         if (err != QLCNIC_RCODE_SUCCESS)
2092                 dev_info(&adapter->pdev->dev,
2093                          "Failed to send interrupt coalescence parameters\n");
2094         qlcnic_free_mbx_args(&cmd);
2095 }
2096
2097 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2098                                         u32 data[])
2099 {
2100         struct qlcnic_hardware_context *ahw = adapter->ahw;
2101         u8 link_status, duplex;
2102         /* link speed */
2103         link_status = LSB(data[3]) & 1;
2104         if (link_status) {
2105                 ahw->link_speed = MSW(data[2]);
2106                 duplex = LSB(MSW(data[3]));
2107                 if (duplex)
2108                         ahw->link_duplex = DUPLEX_FULL;
2109                 else
2110                         ahw->link_duplex = DUPLEX_HALF;
2111         } else {
2112                 ahw->link_speed = SPEED_UNKNOWN;
2113                 ahw->link_duplex = DUPLEX_UNKNOWN;
2114         }
2115
2116         ahw->link_autoneg = MSB(MSW(data[3]));
2117         ahw->module_type = MSB(LSW(data[3]));
2118         ahw->has_link_events = 1;
2119         ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK;
2120         qlcnic_advert_link_change(adapter, link_status);
2121 }
2122
2123 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2124 {
2125         struct qlcnic_adapter *adapter = data;
2126         struct qlcnic_mailbox *mbx;
2127         u32 mask, resp, event;
2128         unsigned long flags;
2129
2130         mbx = adapter->ahw->mailbox;
2131         spin_lock_irqsave(&mbx->aen_lock, flags);
2132         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2133         if (!(resp & QLCNIC_SET_OWNER))
2134                 goto out;
2135
2136         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2137         if (event &  QLCNIC_MBX_ASYNC_EVENT)
2138                 __qlcnic_83xx_process_aen(adapter);
2139         else
2140                 qlcnic_83xx_notify_mbx_response(mbx);
2141
2142 out:
2143         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2144         writel(0, adapter->ahw->pci_base0 + mask);
2145         spin_unlock_irqrestore(&mbx->aen_lock, flags);
2146         return IRQ_HANDLED;
2147 }
2148
2149 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
2150 {
2151         int err = -EIO;
2152         struct qlcnic_cmd_args cmd;
2153
2154         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2155                 dev_err(&adapter->pdev->dev,
2156                         "%s: Error, invoked by non management func\n",
2157                         __func__);
2158                 return err;
2159         }
2160
2161         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
2162         if (err)
2163                 return err;
2164
2165         cmd.req.arg[1] = (port & 0xf) | BIT_4;
2166         err = qlcnic_issue_cmd(adapter, &cmd);
2167
2168         if (err != QLCNIC_RCODE_SUCCESS) {
2169                 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
2170                         err);
2171                 err = -EIO;
2172         }
2173         qlcnic_free_mbx_args(&cmd);
2174
2175         return err;
2176
2177 }
2178
2179 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2180                              struct qlcnic_info *nic)
2181 {
2182         int i, err = -EIO;
2183         struct qlcnic_cmd_args cmd;
2184
2185         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2186                 dev_err(&adapter->pdev->dev,
2187                         "%s: Error, invoked by non management func\n",
2188                         __func__);
2189                 return err;
2190         }
2191
2192         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2193         if (err)
2194                 return err;
2195
2196         cmd.req.arg[1] = (nic->pci_func << 16);
2197         cmd.req.arg[2] = 0x1 << 16;
2198         cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2199         cmd.req.arg[4] = nic->capabilities;
2200         cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2201         cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2202         cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2203         for (i = 8; i < 32; i++)
2204                 cmd.req.arg[i] = 0;
2205
2206         err = qlcnic_issue_cmd(adapter, &cmd);
2207
2208         if (err != QLCNIC_RCODE_SUCCESS) {
2209                 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2210                         err);
2211                 err = -EIO;
2212         }
2213
2214         qlcnic_free_mbx_args(&cmd);
2215
2216         return err;
2217 }
2218
2219 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2220                              struct qlcnic_info *npar_info, u8 func_id)
2221 {
2222         int err;
2223         u32 temp;
2224         u8 op = 0;
2225         struct qlcnic_cmd_args cmd;
2226         struct qlcnic_hardware_context *ahw = adapter->ahw;
2227
2228         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2229         if (err)
2230                 return err;
2231
2232         if (func_id != ahw->pci_func) {
2233                 temp = func_id << 16;
2234                 cmd.req.arg[1] = op | BIT_31 | temp;
2235         } else {
2236                 cmd.req.arg[1] = ahw->pci_func << 16;
2237         }
2238         err = qlcnic_issue_cmd(adapter, &cmd);
2239         if (err) {
2240                 dev_info(&adapter->pdev->dev,
2241                          "Failed to get nic info %d\n", err);
2242                 goto out;
2243         }
2244
2245         npar_info->op_type = cmd.rsp.arg[1];
2246         npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2247         npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2248         npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2249         npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2250         npar_info->capabilities = cmd.rsp.arg[4];
2251         npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2252         npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2253         npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2254         npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2255         npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2256         npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2257         if (cmd.rsp.arg[8] & 0x1)
2258                 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2259         if (cmd.rsp.arg[8] & 0x10000) {
2260                 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2261                 npar_info->max_linkspeed_reg_offset = temp;
2262         }
2263
2264         memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2265                sizeof(ahw->extra_capability));
2266
2267 out:
2268         qlcnic_free_mbx_args(&cmd);
2269         return err;
2270 }
2271
2272 int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type,
2273                              u16 *nic, u16 *fcoe, u16 *iscsi)
2274 {
2275         struct device *dev = &adapter->pdev->dev;
2276         int err = 0;
2277
2278         switch (type) {
2279         case QLCNIC_TYPE_NIC:
2280                 (*nic)++;
2281                 break;
2282         case QLCNIC_TYPE_FCOE:
2283                 (*fcoe)++;
2284                 break;
2285         case QLCNIC_TYPE_ISCSI:
2286                 (*iscsi)++;
2287                 break;
2288         default:
2289                 dev_err(dev, "%s: Unknown PCI type[%x]\n",
2290                         __func__, type);
2291                 err = -EIO;
2292         }
2293
2294         return err;
2295 }
2296
2297 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2298                              struct qlcnic_pci_info *pci_info)
2299 {
2300         struct qlcnic_hardware_context *ahw = adapter->ahw;
2301         struct device *dev = &adapter->pdev->dev;
2302         u16 nic = 0, fcoe = 0, iscsi = 0;
2303         struct qlcnic_cmd_args cmd;
2304         int i, err = 0, j = 0;
2305         u32 temp;
2306
2307         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2308         if (err)
2309                 return err;
2310
2311         err = qlcnic_issue_cmd(adapter, &cmd);
2312
2313         ahw->total_nic_func = 0;
2314         if (err == QLCNIC_RCODE_SUCCESS) {
2315                 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2316                 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) {
2317                         pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2318                         pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2319                         i++;
2320                         if (!pci_info->active) {
2321                                 i += QLC_SKIP_INACTIVE_PCI_REGS;
2322                                 continue;
2323                         }
2324                         pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2325                         err = qlcnic_get_pci_func_type(adapter, pci_info->type,
2326                                                        &nic, &fcoe, &iscsi);
2327                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2328                         pci_info->default_port = temp;
2329                         i++;
2330                         pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2331                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2332                         pci_info->tx_max_bw = temp;
2333                         i = i + 2;
2334                         memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2335                         i++;
2336                         memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2337                         i = i + 3;
2338                 }
2339         } else {
2340                 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2341                 err = -EIO;
2342         }
2343
2344         ahw->total_nic_func = nic;
2345         ahw->total_pci_func = nic + fcoe + iscsi;
2346         if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
2347                 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
2348                         __func__, ahw->total_nic_func, ahw->total_pci_func);
2349                 err = -EIO;
2350         }
2351         qlcnic_free_mbx_args(&cmd);
2352
2353         return err;
2354 }
2355
2356 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2357 {
2358         int i, index, err;
2359         u8 max_ints;
2360         u32 val, temp, type;
2361         struct qlcnic_cmd_args cmd;
2362
2363         max_ints = adapter->ahw->num_msix - 1;
2364         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2365         if (err)
2366                 return err;
2367
2368         cmd.req.arg[1] = max_ints;
2369
2370         if (qlcnic_sriov_vf_check(adapter))
2371                 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2372
2373         for (i = 0, index = 2; i < max_ints; i++) {
2374                 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2375                 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2376                 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2377                         val |= (adapter->ahw->intr_tbl[i].id << 16);
2378                 cmd.req.arg[index++] = val;
2379         }
2380         err = qlcnic_issue_cmd(adapter, &cmd);
2381         if (err) {
2382                 dev_err(&adapter->pdev->dev,
2383                         "Failed to configure interrupts 0x%x\n", err);
2384                 goto out;
2385         }
2386
2387         max_ints = cmd.rsp.arg[1];
2388         for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2389                 val = cmd.rsp.arg[index];
2390                 if (LSB(val)) {
2391                         dev_info(&adapter->pdev->dev,
2392                                  "Can't configure interrupt %d\n",
2393                                  adapter->ahw->intr_tbl[i].id);
2394                         continue;
2395                 }
2396                 if (op_type) {
2397                         adapter->ahw->intr_tbl[i].id = MSW(val);
2398                         adapter->ahw->intr_tbl[i].enabled = 1;
2399                         temp = cmd.rsp.arg[index + 1];
2400                         adapter->ahw->intr_tbl[i].src = temp;
2401                 } else {
2402                         adapter->ahw->intr_tbl[i].id = i;
2403                         adapter->ahw->intr_tbl[i].enabled = 0;
2404                         adapter->ahw->intr_tbl[i].src = 0;
2405                 }
2406         }
2407 out:
2408         qlcnic_free_mbx_args(&cmd);
2409         return err;
2410 }
2411
2412 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2413 {
2414         int id, timeout = 0;
2415         u32 status = 0;
2416
2417         while (status == 0) {
2418                 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2419                 if (status)
2420                         break;
2421
2422                 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2423                         id = QLC_SHARED_REG_RD32(adapter,
2424                                                  QLCNIC_FLASH_LOCK_OWNER);
2425                         dev_err(&adapter->pdev->dev,
2426                                 "%s: failed, lock held by %d\n", __func__, id);
2427                         return -EIO;
2428                 }
2429                 usleep_range(1000, 2000);
2430         }
2431
2432         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2433         return 0;
2434 }
2435
2436 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2437 {
2438         QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2439         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2440 }
2441
2442 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2443                                       u32 flash_addr, u8 *p_data,
2444                                       int count)
2445 {
2446         u32 word, range, flash_offset, addr = flash_addr, ret;
2447         ulong indirect_add, direct_window;
2448         int i, err = 0;
2449
2450         flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2451         if (addr & 0x3) {
2452                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2453                 return -EIO;
2454         }
2455
2456         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2457                                      (addr));
2458
2459         range = flash_offset + (count * sizeof(u32));
2460         /* Check if data is spread across multiple sectors */
2461         if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2462
2463                 /* Multi sector read */
2464                 for (i = 0; i < count; i++) {
2465                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2466                         ret = QLCRD32(adapter, indirect_add, &err);
2467                         if (err == -EIO)
2468                                 return err;
2469
2470                         word = ret;
2471                         *(u32 *)p_data  = word;
2472                         p_data = p_data + 4;
2473                         addr = addr + 4;
2474                         flash_offset = flash_offset + 4;
2475
2476                         if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2477                                 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2478                                 /* This write is needed once for each sector */
2479                                 qlcnic_83xx_wrt_reg_indirect(adapter,
2480                                                              direct_window,
2481                                                              (addr));
2482                                 flash_offset = 0;
2483                         }
2484                 }
2485         } else {
2486                 /* Single sector read */
2487                 for (i = 0; i < count; i++) {
2488                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2489                         ret = QLCRD32(adapter, indirect_add, &err);
2490                         if (err == -EIO)
2491                                 return err;
2492
2493                         word = ret;
2494                         *(u32 *)p_data  = word;
2495                         p_data = p_data + 4;
2496                         addr = addr + 4;
2497                 }
2498         }
2499
2500         return 0;
2501 }
2502
2503 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2504 {
2505         u32 status;
2506         int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2507         int err = 0;
2508
2509         do {
2510                 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2511                 if (err == -EIO)
2512                         return err;
2513
2514                 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2515                     QLC_83XX_FLASH_STATUS_READY)
2516                         break;
2517
2518                 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2519         } while (--retries);
2520
2521         if (!retries)
2522                 return -EIO;
2523
2524         return 0;
2525 }
2526
2527 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2528 {
2529         int ret;
2530         u32 cmd;
2531         cmd = adapter->ahw->fdt.write_statusreg_cmd;
2532         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2533                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2534         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2535                                      adapter->ahw->fdt.write_enable_bits);
2536         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2537                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2538         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2539         if (ret)
2540                 return -EIO;
2541
2542         return 0;
2543 }
2544
2545 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2546 {
2547         int ret;
2548
2549         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2550                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2551                                      adapter->ahw->fdt.write_statusreg_cmd));
2552         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2553                                      adapter->ahw->fdt.write_disable_bits);
2554         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2555                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2556         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2557         if (ret)
2558                 return -EIO;
2559
2560         return 0;
2561 }
2562
2563 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2564 {
2565         int ret, err = 0;
2566         u32 mfg_id;
2567
2568         if (qlcnic_83xx_lock_flash(adapter))
2569                 return -EIO;
2570
2571         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2572                                      QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2573         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2574                                      QLC_83XX_FLASH_READ_CTRL);
2575         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2576         if (ret) {
2577                 qlcnic_83xx_unlock_flash(adapter);
2578                 return -EIO;
2579         }
2580
2581         mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2582         if (err == -EIO) {
2583                 qlcnic_83xx_unlock_flash(adapter);
2584                 return err;
2585         }
2586
2587         adapter->flash_mfg_id = (mfg_id & 0xFF);
2588         qlcnic_83xx_unlock_flash(adapter);
2589
2590         return 0;
2591 }
2592
2593 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2594 {
2595         int count, fdt_size, ret = 0;
2596
2597         fdt_size = sizeof(struct qlcnic_fdt);
2598         count = fdt_size / sizeof(u32);
2599
2600         if (qlcnic_83xx_lock_flash(adapter))
2601                 return -EIO;
2602
2603         memset(&adapter->ahw->fdt, 0, fdt_size);
2604         ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2605                                                 (u8 *)&adapter->ahw->fdt,
2606                                                 count);
2607
2608         qlcnic_83xx_unlock_flash(adapter);
2609         return ret;
2610 }
2611
2612 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2613                                    u32 sector_start_addr)
2614 {
2615         u32 reversed_addr, addr1, addr2, cmd;
2616         int ret = -EIO;
2617
2618         if (qlcnic_83xx_lock_flash(adapter) != 0)
2619                 return -EIO;
2620
2621         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2622                 ret = qlcnic_83xx_enable_flash_write(adapter);
2623                 if (ret) {
2624                         qlcnic_83xx_unlock_flash(adapter);
2625                         dev_err(&adapter->pdev->dev,
2626                                 "%s failed at %d\n",
2627                                 __func__, __LINE__);
2628                         return ret;
2629                 }
2630         }
2631
2632         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2633         if (ret) {
2634                 qlcnic_83xx_unlock_flash(adapter);
2635                 dev_err(&adapter->pdev->dev,
2636                         "%s: failed at %d\n", __func__, __LINE__);
2637                 return -EIO;
2638         }
2639
2640         addr1 = (sector_start_addr & 0xFF) << 16;
2641         addr2 = (sector_start_addr & 0xFF0000) >> 16;
2642         reversed_addr = addr1 | addr2;
2643
2644         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2645                                      reversed_addr);
2646         cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2647         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2648                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2649         else
2650                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2651                                              QLC_83XX_FLASH_OEM_ERASE_SIG);
2652         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2653                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2654
2655         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2656         if (ret) {
2657                 qlcnic_83xx_unlock_flash(adapter);
2658                 dev_err(&adapter->pdev->dev,
2659                         "%s: failed at %d\n", __func__, __LINE__);
2660                 return -EIO;
2661         }
2662
2663         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2664                 ret = qlcnic_83xx_disable_flash_write(adapter);
2665                 if (ret) {
2666                         qlcnic_83xx_unlock_flash(adapter);
2667                         dev_err(&adapter->pdev->dev,
2668                                 "%s: failed at %d\n", __func__, __LINE__);
2669                         return ret;
2670                 }
2671         }
2672
2673         qlcnic_83xx_unlock_flash(adapter);
2674
2675         return 0;
2676 }
2677
2678 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2679                               u32 *p_data)
2680 {
2681         int ret = -EIO;
2682         u32 addr1 = 0x00800000 | (addr >> 2);
2683
2684         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2685         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2686         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2687                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2688         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2689         if (ret) {
2690                 dev_err(&adapter->pdev->dev,
2691                         "%s: failed at %d\n", __func__, __LINE__);
2692                 return -EIO;
2693         }
2694
2695         return 0;
2696 }
2697
2698 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2699                                  u32 *p_data, int count)
2700 {
2701         u32 temp;
2702         int ret = -EIO, err = 0;
2703
2704         if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2705             (count > QLC_83XX_FLASH_WRITE_MAX)) {
2706                 dev_err(&adapter->pdev->dev,
2707                         "%s: Invalid word count\n", __func__);
2708                 return -EIO;
2709         }
2710
2711         temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2712         if (err == -EIO)
2713                 return err;
2714
2715         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2716                                      (temp | QLC_83XX_FLASH_SPI_CTRL));
2717         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2718                                      QLC_83XX_FLASH_ADDR_TEMP_VAL);
2719
2720         /* First DWORD write */
2721         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2722         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2723                                      QLC_83XX_FLASH_FIRST_MS_PATTERN);
2724         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2725         if (ret) {
2726                 dev_err(&adapter->pdev->dev,
2727                         "%s: failed at %d\n", __func__, __LINE__);
2728                 return -EIO;
2729         }
2730
2731         count--;
2732         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2733                                      QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2734         /* Second to N-1 DWORD writes */
2735         while (count != 1) {
2736                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2737                                              *p_data++);
2738                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2739                                              QLC_83XX_FLASH_SECOND_MS_PATTERN);
2740                 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2741                 if (ret) {
2742                         dev_err(&adapter->pdev->dev,
2743                                 "%s: failed at %d\n", __func__, __LINE__);
2744                         return -EIO;
2745                 }
2746                 count--;
2747         }
2748
2749         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2750                                      QLC_83XX_FLASH_ADDR_TEMP_VAL |
2751                                      (addr >> 2));
2752         /* Last DWORD write */
2753         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2754         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2755                                      QLC_83XX_FLASH_LAST_MS_PATTERN);
2756         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2757         if (ret) {
2758                 dev_err(&adapter->pdev->dev,
2759                         "%s: failed at %d\n", __func__, __LINE__);
2760                 return -EIO;
2761         }
2762
2763         ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2764         if (err == -EIO)
2765                 return err;
2766
2767         if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2768                 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2769                         __func__, __LINE__);
2770                 /* Operation failed, clear error bit */
2771                 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2772                 if (err == -EIO)
2773                         return err;
2774
2775                 qlcnic_83xx_wrt_reg_indirect(adapter,
2776                                              QLC_83XX_FLASH_SPI_CONTROL,
2777                                              (temp | QLC_83XX_FLASH_SPI_CTRL));
2778         }
2779
2780         return 0;
2781 }
2782
2783 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2784 {
2785         u32 val, id;
2786
2787         val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2788
2789         /* Check if recovery need to be performed by the calling function */
2790         if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2791                 val = val & ~0x3F;
2792                 val = val | ((adapter->portnum << 2) |
2793                              QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2794                 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2795                 dev_info(&adapter->pdev->dev,
2796                          "%s: lock recovery initiated\n", __func__);
2797                 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2798                 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2799                 id = ((val >> 2) & 0xF);
2800                 if (id == adapter->portnum) {
2801                         val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2802                         val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2803                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2804                         /* Force release the lock */
2805                         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2806                         /* Clear recovery bits */
2807                         val = val & ~0x3F;
2808                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2809                         dev_info(&adapter->pdev->dev,
2810                                  "%s: lock recovery completed\n", __func__);
2811                 } else {
2812                         dev_info(&adapter->pdev->dev,
2813                                  "%s: func %d to resume lock recovery process\n",
2814                                  __func__, id);
2815                 }
2816         } else {
2817                 dev_info(&adapter->pdev->dev,
2818                          "%s: lock recovery initiated by other functions\n",
2819                          __func__);
2820         }
2821 }
2822
2823 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2824 {
2825         u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2826         int max_attempt = 0;
2827
2828         while (status == 0) {
2829                 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2830                 if (status)
2831                         break;
2832
2833                 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2834                 i++;
2835
2836                 if (i == 1)
2837                         temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2838
2839                 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2840                         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2841                         if (val == temp) {
2842                                 id = val & 0xFF;
2843                                 dev_info(&adapter->pdev->dev,
2844                                          "%s: lock to be recovered from %d\n",
2845                                          __func__, id);
2846                                 qlcnic_83xx_recover_driver_lock(adapter);
2847                                 i = 0;
2848                                 max_attempt++;
2849                         } else {
2850                                 dev_err(&adapter->pdev->dev,
2851                                         "%s: failed to get lock\n", __func__);
2852                                 return -EIO;
2853                         }
2854                 }
2855
2856                 /* Force exit from while loop after few attempts */
2857                 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2858                         dev_err(&adapter->pdev->dev,
2859                                 "%s: failed to get lock\n", __func__);
2860                         return -EIO;
2861                 }
2862         }
2863
2864         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2865         lock_alive_counter = val >> 8;
2866         lock_alive_counter++;
2867         val = lock_alive_counter << 8 | adapter->portnum;
2868         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2869
2870         return 0;
2871 }
2872
2873 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2874 {
2875         u32 val, lock_alive_counter, id;
2876
2877         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2878         id = val & 0xFF;
2879         lock_alive_counter = val >> 8;
2880
2881         if (id != adapter->portnum)
2882                 dev_err(&adapter->pdev->dev,
2883                         "%s:Warning func %d is unlocking lock owned by %d\n",
2884                         __func__, adapter->portnum, id);
2885
2886         val = (lock_alive_counter << 8) | 0xFF;
2887         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2888         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2889 }
2890
2891 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2892                                 u32 *data, u32 count)
2893 {
2894         int i, j, ret = 0;
2895         u32 temp;
2896         int err = 0;
2897
2898         /* Check alignment */
2899         if (addr & 0xF)
2900                 return -EIO;
2901
2902         mutex_lock(&adapter->ahw->mem_lock);
2903         qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2904
2905         for (i = 0; i < count; i++, addr += 16) {
2906                 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2907                                      QLCNIC_ADDR_QDR_NET_MAX)) ||
2908                       (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2909                                      QLCNIC_ADDR_DDR_NET_MAX)))) {
2910                         mutex_unlock(&adapter->ahw->mem_lock);
2911                         return -EIO;
2912                 }
2913
2914                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2915                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2916                                              *data++);
2917                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2918                                              *data++);
2919                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2920                                              *data++);
2921                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2922                                              *data++);
2923                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2924                                              QLCNIC_TA_WRITE_ENABLE);
2925                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2926                                              QLCNIC_TA_WRITE_START);
2927
2928                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2929                         temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err);
2930                         if (err == -EIO) {
2931                                 mutex_unlock(&adapter->ahw->mem_lock);
2932                                 return err;
2933                         }
2934
2935                         if ((temp & TA_CTL_BUSY) == 0)
2936                                 break;
2937                 }
2938
2939                 /* Status check failure */
2940                 if (j >= MAX_CTL_CHECK) {
2941                         printk_ratelimited(KERN_WARNING
2942                                            "MS memory write failed\n");
2943                         mutex_unlock(&adapter->ahw->mem_lock);
2944                         return -EIO;
2945                 }
2946         }
2947
2948         mutex_unlock(&adapter->ahw->mem_lock);
2949
2950         return ret;
2951 }
2952
2953 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2954                              u8 *p_data, int count)
2955 {
2956         u32 word, addr = flash_addr, ret;
2957         ulong  indirect_addr;
2958         int i, err = 0;
2959
2960         if (qlcnic_83xx_lock_flash(adapter) != 0)
2961                 return -EIO;
2962
2963         if (addr & 0x3) {
2964                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2965                 qlcnic_83xx_unlock_flash(adapter);
2966                 return -EIO;
2967         }
2968
2969         for (i = 0; i < count; i++) {
2970                 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2971                                                  QLC_83XX_FLASH_DIRECT_WINDOW,
2972                                                  (addr))) {
2973                         qlcnic_83xx_unlock_flash(adapter);
2974                         return -EIO;
2975                 }
2976
2977                 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2978                 ret = QLCRD32(adapter, indirect_addr, &err);
2979                 if (err == -EIO)
2980                         return err;
2981
2982                 word = ret;
2983                 *(u32 *)p_data  = word;
2984                 p_data = p_data + 4;
2985                 addr = addr + 4;
2986         }
2987
2988         qlcnic_83xx_unlock_flash(adapter);
2989
2990         return 0;
2991 }
2992
2993 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2994 {
2995         u8 pci_func;
2996         int err;
2997         u32 config = 0, state;
2998         struct qlcnic_cmd_args cmd;
2999         struct qlcnic_hardware_context *ahw = adapter->ahw;
3000
3001         if (qlcnic_sriov_vf_check(adapter))
3002                 pci_func = adapter->portnum;
3003         else
3004                 pci_func = ahw->pci_func;
3005
3006         state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
3007         if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
3008                 dev_info(&adapter->pdev->dev, "link state down\n");
3009                 return config;
3010         }
3011
3012         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3013         if (err)
3014                 return err;
3015
3016         err = qlcnic_issue_cmd(adapter, &cmd);
3017         if (err) {
3018                 dev_info(&adapter->pdev->dev,
3019                          "Get Link Status Command failed: 0x%x\n", err);
3020                 goto out;
3021         } else {
3022                 config = cmd.rsp.arg[1];
3023                 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3024                 case QLC_83XX_10M_LINK:
3025                         ahw->link_speed = SPEED_10;
3026                         break;
3027                 case QLC_83XX_100M_LINK:
3028                         ahw->link_speed = SPEED_100;
3029                         break;
3030                 case QLC_83XX_1G_LINK:
3031                         ahw->link_speed = SPEED_1000;
3032                         break;
3033                 case QLC_83XX_10G_LINK:
3034                         ahw->link_speed = SPEED_10000;
3035                         break;
3036                 default:
3037                         ahw->link_speed = 0;
3038                         break;
3039                 }
3040                 config = cmd.rsp.arg[3];
3041                 if (QLC_83XX_SFP_PRESENT(config)) {
3042                         switch (ahw->module_type) {
3043                         case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
3044                         case LINKEVENT_MODULE_OPTICAL_SRLR:
3045                         case LINKEVENT_MODULE_OPTICAL_LRM:
3046                         case LINKEVENT_MODULE_OPTICAL_SFP_1G:
3047                                 ahw->supported_type = PORT_FIBRE;
3048                                 break;
3049                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
3050                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
3051                         case LINKEVENT_MODULE_TWINAX:
3052                                 ahw->supported_type = PORT_TP;
3053                                 break;
3054                         default:
3055                                 ahw->supported_type = PORT_OTHER;
3056                         }
3057                 }
3058                 if (config & 1)
3059                         err = 1;
3060         }
3061 out:
3062         qlcnic_free_mbx_args(&cmd);
3063         return config;
3064 }
3065
3066 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3067                              struct ethtool_cmd *ecmd)
3068 {
3069         u32 config = 0;
3070         int status = 0;
3071         struct qlcnic_hardware_context *ahw = adapter->ahw;
3072
3073         if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3074                 /* Get port configuration info */
3075                 status = qlcnic_83xx_get_port_info(adapter);
3076                 /* Get Link Status related info */
3077                 config = qlcnic_83xx_test_link(adapter);
3078                 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3079         }
3080
3081         /* hard code until there is a way to get it from flash */
3082         ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3083
3084         if (netif_running(adapter->netdev) && ahw->has_link_events) {
3085                 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3086                 ecmd->duplex = ahw->link_duplex;
3087                 ecmd->autoneg = ahw->link_autoneg;
3088         } else {
3089                 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3090                 ecmd->duplex = DUPLEX_UNKNOWN;
3091                 ecmd->autoneg = AUTONEG_DISABLE;
3092         }
3093
3094         if (ahw->port_type == QLCNIC_XGBE) {
3095                 ecmd->supported = SUPPORTED_10000baseT_Full;
3096                 ecmd->advertising = ADVERTISED_10000baseT_Full;
3097         } else {
3098                 ecmd->supported = (SUPPORTED_10baseT_Half |
3099                                    SUPPORTED_10baseT_Full |
3100                                    SUPPORTED_100baseT_Half |
3101                                    SUPPORTED_100baseT_Full |
3102                                    SUPPORTED_1000baseT_Half |
3103                                    SUPPORTED_1000baseT_Full);
3104                 ecmd->advertising = (ADVERTISED_100baseT_Half |
3105                                      ADVERTISED_100baseT_Full |
3106                                      ADVERTISED_1000baseT_Half |
3107                                      ADVERTISED_1000baseT_Full);
3108         }
3109
3110         switch (ahw->supported_type) {
3111         case PORT_FIBRE:
3112                 ecmd->supported |= SUPPORTED_FIBRE;
3113                 ecmd->advertising |= ADVERTISED_FIBRE;
3114                 ecmd->port = PORT_FIBRE;
3115                 ecmd->transceiver = XCVR_EXTERNAL;
3116                 break;
3117         case PORT_TP:
3118                 ecmd->supported |= SUPPORTED_TP;
3119                 ecmd->advertising |= ADVERTISED_TP;
3120                 ecmd->port = PORT_TP;
3121                 ecmd->transceiver = XCVR_INTERNAL;
3122                 break;
3123         default:
3124                 ecmd->supported |= SUPPORTED_FIBRE;
3125                 ecmd->advertising |= ADVERTISED_FIBRE;
3126                 ecmd->port = PORT_OTHER;
3127                 ecmd->transceiver = XCVR_EXTERNAL;
3128                 break;
3129         }
3130         ecmd->phy_address = ahw->physical_port;
3131         return status;
3132 }
3133
3134 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3135                              struct ethtool_cmd *ecmd)
3136 {
3137         int status = 0;
3138         u32 config = adapter->ahw->port_config;
3139
3140         if (ecmd->autoneg)
3141                 adapter->ahw->port_config |= BIT_15;
3142
3143         switch (ethtool_cmd_speed(ecmd)) {
3144         case SPEED_10:
3145                 adapter->ahw->port_config |= BIT_8;
3146                 break;
3147         case SPEED_100:
3148                 adapter->ahw->port_config |= BIT_9;
3149                 break;
3150         case SPEED_1000:
3151                 adapter->ahw->port_config |= BIT_10;
3152                 break;
3153         case SPEED_10000:
3154                 adapter->ahw->port_config |= BIT_11;
3155                 break;
3156         default:
3157                 return -EINVAL;
3158         }
3159
3160         status = qlcnic_83xx_set_port_config(adapter);
3161         if (status) {
3162                 dev_info(&adapter->pdev->dev,
3163                          "Failed to Set Link Speed and autoneg.\n");
3164                 adapter->ahw->port_config = config;
3165         }
3166         return status;
3167 }
3168
3169 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3170                                           u64 *data, int index)
3171 {
3172         u32 low, hi;
3173         u64 val;
3174
3175         low = cmd->rsp.arg[index];
3176         hi = cmd->rsp.arg[index + 1];
3177         val = (((u64) low) | (((u64) hi) << 32));
3178         *data++ = val;
3179         return data;
3180 }
3181
3182 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3183                                    struct qlcnic_cmd_args *cmd, u64 *data,
3184                                    int type, int *ret)
3185 {
3186         int err, k, total_regs;
3187
3188         *ret = 0;
3189         err = qlcnic_issue_cmd(adapter, cmd);
3190         if (err != QLCNIC_RCODE_SUCCESS) {
3191                 dev_info(&adapter->pdev->dev,
3192                          "Error in get statistics mailbox command\n");
3193                 *ret = -EIO;
3194                 return data;
3195         }
3196         total_regs = cmd->rsp.num;
3197         switch (type) {
3198         case QLC_83XX_STAT_MAC:
3199                 /* fill in MAC tx counters */
3200                 for (k = 2; k < 28; k += 2)
3201                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3202                 /* skip 24 bytes of reserved area */
3203                 /* fill in MAC rx counters */
3204                 for (k += 6; k < 60; k += 2)
3205                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3206                 /* skip 24 bytes of reserved area */
3207                 /* fill in MAC rx frame stats */
3208                 for (k += 6; k < 80; k += 2)
3209                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3210                 /* fill in eSwitch stats */
3211                 for (; k < total_regs; k += 2)
3212                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3213                 break;
3214         case QLC_83XX_STAT_RX:
3215                 for (k = 2; k < 8; k += 2)
3216                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3217                 /* skip 8 bytes of reserved data */
3218                 for (k += 2; k < 24; k += 2)
3219                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3220                 /* skip 8 bytes containing RE1FBQ error data */
3221                 for (k += 2; k < total_regs; k += 2)
3222                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3223                 break;
3224         case QLC_83XX_STAT_TX:
3225                 for (k = 2; k < 10; k += 2)
3226                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3227                 /* skip 8 bytes of reserved data */
3228                 for (k += 2; k < total_regs; k += 2)
3229                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3230                 break;
3231         default:
3232                 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3233                 *ret = -EIO;
3234         }
3235         return data;
3236 }
3237
3238 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3239 {
3240         struct qlcnic_cmd_args cmd;
3241         struct net_device *netdev = adapter->netdev;
3242         int ret = 0;
3243
3244         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3245         if (ret)
3246                 return;
3247         /* Get Tx stats */
3248         cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3249         cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3250         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3251                                       QLC_83XX_STAT_TX, &ret);
3252         if (ret) {
3253                 netdev_err(netdev, "Error getting Tx stats\n");
3254                 goto out;
3255         }
3256         /* Get MAC stats */
3257         cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3258         cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3259         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3260         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3261                                       QLC_83XX_STAT_MAC, &ret);
3262         if (ret) {
3263                 netdev_err(netdev, "Error getting MAC stats\n");
3264                 goto out;
3265         }
3266         /* Get Rx stats */
3267         cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3268         cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3269         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3270         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3271                                       QLC_83XX_STAT_RX, &ret);
3272         if (ret)
3273                 netdev_err(netdev, "Error getting Rx stats\n");
3274 out:
3275         qlcnic_free_mbx_args(&cmd);
3276 }
3277
3278 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3279 {
3280         u32 major, minor, sub;
3281
3282         major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3283         minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3284         sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3285
3286         if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3287                 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3288                          __func__);
3289                 return 1;
3290         }
3291         return 0;
3292 }
3293
3294 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3295 {
3296         return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3297                 sizeof(*adapter->ahw->ext_reg_tbl)) +
3298                 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3299                 sizeof(*adapter->ahw->reg_tbl));
3300 }
3301
3302 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3303 {
3304         int i, j = 0;
3305
3306         for (i = QLCNIC_DEV_INFO_SIZE + 1;
3307              j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3308                 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3309
3310         for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3311                 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3312         return i;
3313 }
3314
3315 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3316 {
3317         struct qlcnic_adapter *adapter = netdev_priv(netdev);
3318         struct qlcnic_hardware_context *ahw = adapter->ahw;
3319         struct qlcnic_cmd_args cmd;
3320         u8 val, drv_sds_rings = adapter->drv_sds_rings;
3321         u8 drv_tx_rings = adapter->drv_tx_rings;
3322         u32 data;
3323         u16 intrpt_id, id;
3324         int ret;
3325
3326         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3327                 netdev_info(netdev, "Device is resetting\n");
3328                 return -EBUSY;
3329         }
3330
3331         if (qlcnic_get_diag_lock(adapter)) {
3332                 netdev_info(netdev, "Device in diagnostics mode\n");
3333                 return -EBUSY;
3334         }
3335
3336         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3337                                          drv_sds_rings);
3338         if (ret)
3339                 goto fail_diag_irq;
3340
3341         ahw->diag_cnt = 0;
3342         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3343         if (ret)
3344                 goto fail_diag_irq;
3345
3346         if (adapter->flags & QLCNIC_MSIX_ENABLED)
3347                 intrpt_id = ahw->intr_tbl[0].id;
3348         else
3349                 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3350
3351         cmd.req.arg[1] = 1;
3352         cmd.req.arg[2] = intrpt_id;
3353         cmd.req.arg[3] = BIT_0;
3354
3355         ret = qlcnic_issue_cmd(adapter, &cmd);
3356         data = cmd.rsp.arg[2];
3357         id = LSW(data);
3358         val = LSB(MSW(data));
3359         if (id != intrpt_id)
3360                 dev_info(&adapter->pdev->dev,
3361                          "Interrupt generated: 0x%x, requested:0x%x\n",
3362                          id, intrpt_id);
3363         if (val)
3364                 dev_err(&adapter->pdev->dev,
3365                          "Interrupt test error: 0x%x\n", val);
3366         if (ret)
3367                 goto done;
3368
3369         msleep(20);
3370         ret = !ahw->diag_cnt;
3371
3372 done:
3373         qlcnic_free_mbx_args(&cmd);
3374         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3375
3376 fail_diag_irq:
3377         adapter->drv_sds_rings = drv_sds_rings;
3378         adapter->drv_tx_rings = drv_tx_rings;
3379         qlcnic_release_diag_lock(adapter);
3380         return ret;
3381 }
3382
3383 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3384                                 struct ethtool_pauseparam *pause)
3385 {
3386         struct qlcnic_hardware_context *ahw = adapter->ahw;
3387         int status = 0;
3388         u32 config;
3389
3390         status = qlcnic_83xx_get_port_config(adapter);
3391         if (status) {
3392                 dev_err(&adapter->pdev->dev,
3393                         "%s: Get Pause Config failed\n", __func__);
3394                 return;
3395         }
3396         config = ahw->port_config;
3397         if (config & QLC_83XX_CFG_STD_PAUSE) {
3398                 switch (MSW(config)) {
3399                 case QLC_83XX_TX_PAUSE:
3400                         pause->tx_pause = 1;
3401                         break;
3402                 case QLC_83XX_RX_PAUSE:
3403                         pause->rx_pause = 1;
3404                         break;
3405                 case QLC_83XX_TX_RX_PAUSE:
3406                 default:
3407                         /* Backward compatibility for existing
3408                          * flash definitions
3409                          */
3410                         pause->tx_pause = 1;
3411                         pause->rx_pause = 1;
3412                 }
3413         }
3414
3415         if (QLC_83XX_AUTONEG(config))
3416                 pause->autoneg = 1;
3417 }
3418
3419 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3420                                struct ethtool_pauseparam *pause)
3421 {
3422         struct qlcnic_hardware_context *ahw = adapter->ahw;
3423         int status = 0;
3424         u32 config;
3425
3426         status = qlcnic_83xx_get_port_config(adapter);
3427         if (status) {
3428                 dev_err(&adapter->pdev->dev,
3429                         "%s: Get Pause Config failed.\n", __func__);
3430                 return status;
3431         }
3432         config = ahw->port_config;
3433
3434         if (ahw->port_type == QLCNIC_GBE) {
3435                 if (pause->autoneg)
3436                         ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3437                 if (!pause->autoneg)
3438                         ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3439         } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3440                 return -EOPNOTSUPP;
3441         }
3442
3443         if (!(config & QLC_83XX_CFG_STD_PAUSE))
3444                 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3445
3446         if (pause->rx_pause && pause->tx_pause) {
3447                 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3448         } else if (pause->rx_pause && !pause->tx_pause) {
3449                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3450                 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3451         } else if (pause->tx_pause && !pause->rx_pause) {
3452                 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3453                 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3454         } else if (!pause->rx_pause && !pause->tx_pause) {
3455                 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3456                                       QLC_83XX_CFG_STD_PAUSE);
3457         }
3458         status = qlcnic_83xx_set_port_config(adapter);
3459         if (status) {
3460                 dev_err(&adapter->pdev->dev,
3461                         "%s: Set Pause Config failed.\n", __func__);
3462                 ahw->port_config = config;
3463         }
3464         return status;
3465 }
3466
3467 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3468 {
3469         int ret, err = 0;
3470         u32 temp;
3471
3472         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3473                                      QLC_83XX_FLASH_OEM_READ_SIG);
3474         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3475                                      QLC_83XX_FLASH_READ_CTRL);
3476         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3477         if (ret)
3478                 return -EIO;
3479
3480         temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3481         if (err == -EIO)
3482                 return err;
3483
3484         return temp & 0xFF;
3485 }
3486
3487 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3488 {
3489         int status;
3490
3491         status = qlcnic_83xx_read_flash_status_reg(adapter);
3492         if (status == -EIO) {
3493                 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3494                          __func__);
3495                 return 1;
3496         }
3497         return 0;
3498 }
3499
3500 int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3501 {
3502         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3503         struct net_device *netdev = adapter->netdev;
3504         int retval;
3505
3506         netif_device_detach(netdev);
3507         qlcnic_cancel_idc_work(adapter);
3508
3509         if (netif_running(netdev))
3510                 qlcnic_down(adapter, netdev);
3511
3512         qlcnic_83xx_disable_mbx_intr(adapter);
3513         cancel_delayed_work_sync(&adapter->idc_aen_work);
3514
3515         retval = pci_save_state(pdev);
3516         if (retval)
3517                 return retval;
3518
3519         return 0;
3520 }
3521
3522 int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3523 {
3524         struct qlcnic_hardware_context *ahw = adapter->ahw;
3525         struct qlc_83xx_idc *idc = &ahw->idc;
3526         int err = 0;
3527
3528         err = qlcnic_83xx_idc_init(adapter);
3529         if (err)
3530                 return err;
3531
3532         if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3533                 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3534                         qlcnic_83xx_set_vnic_opmode(adapter);
3535                 } else {
3536                         err = qlcnic_83xx_check_vnic_state(adapter);
3537                         if (err)
3538                                 return err;
3539                 }
3540         }
3541
3542         err = qlcnic_83xx_idc_reattach_driver(adapter);
3543         if (err)
3544                 return err;
3545
3546         qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3547                              idc->delay);
3548         return err;
3549 }
3550
3551 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3552 {
3553         reinit_completion(&mbx->completion);
3554         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3555 }
3556
3557 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3558 {
3559         if (!mbx)
3560                 return;
3561
3562         destroy_workqueue(mbx->work_q);
3563         kfree(mbx);
3564 }
3565
3566 static inline void
3567 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3568                                   struct qlcnic_cmd_args *cmd)
3569 {
3570         atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3571
3572         if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3573                 qlcnic_free_mbx_args(cmd);
3574                 kfree(cmd);
3575                 return;
3576         }
3577         complete(&cmd->completion);
3578 }
3579
3580 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3581 {
3582         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3583         struct list_head *head = &mbx->cmd_q;
3584         struct qlcnic_cmd_args *cmd = NULL;
3585
3586         spin_lock(&mbx->queue_lock);
3587
3588         while (!list_empty(head)) {
3589                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3590                 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3591                          __func__, cmd->cmd_op);
3592                 list_del(&cmd->list);
3593                 mbx->num_cmds--;
3594                 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3595         }
3596
3597         spin_unlock(&mbx->queue_lock);
3598 }
3599
3600 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3601 {
3602         struct qlcnic_hardware_context *ahw = adapter->ahw;
3603         struct qlcnic_mailbox *mbx = ahw->mailbox;
3604         u32 host_mbx_ctrl;
3605
3606         if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3607                 return -EBUSY;
3608
3609         host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3610         if (host_mbx_ctrl) {
3611                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3612                 ahw->idc.collect_dump = 1;
3613                 return -EIO;
3614         }
3615
3616         return 0;
3617 }
3618
3619 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3620                                               u8 issue_cmd)
3621 {
3622         if (issue_cmd)
3623                 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3624         else
3625                 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3626 }
3627
3628 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3629                                         struct qlcnic_cmd_args *cmd)
3630 {
3631         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3632
3633         spin_lock(&mbx->queue_lock);
3634
3635         list_del(&cmd->list);
3636         mbx->num_cmds--;
3637
3638         spin_unlock(&mbx->queue_lock);
3639
3640         qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3641 }
3642
3643 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3644                                        struct qlcnic_cmd_args *cmd)
3645 {
3646         u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3647         struct qlcnic_hardware_context *ahw = adapter->ahw;
3648         int i, j;
3649
3650         if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3651                 mbx_cmd = cmd->req.arg[0];
3652                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3653                 for (i = 1; i < cmd->req.num; i++)
3654                         writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3655         } else {
3656                 fw_hal_version = ahw->fw_hal_version;
3657                 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3658                 total_size = cmd->pay_size + hdr_size;
3659                 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3660                 mbx_cmd = tmp | fw_hal_version << 29;
3661                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3662
3663                 /* Back channel specific operations bits */
3664                 mbx_cmd = 0x1 | 1 << 4;
3665
3666                 if (qlcnic_sriov_pf_check(adapter))
3667                         mbx_cmd |= cmd->func_num << 5;
3668
3669                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3670
3671                 for (i = 2, j = 0; j < hdr_size; i++, j++)
3672                         writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3673                 for (j = 0; j < cmd->pay_size; j++, i++)
3674                         writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3675         }
3676 }
3677
3678 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3679 {
3680         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3681
3682         if (!mbx)
3683                 return;
3684
3685         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3686         complete(&mbx->completion);
3687         cancel_work_sync(&mbx->work);
3688         flush_workqueue(mbx->work_q);
3689         qlcnic_83xx_flush_mbx_queue(adapter);
3690 }
3691
3692 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3693                                        struct qlcnic_cmd_args *cmd,
3694                                        unsigned long *timeout)
3695 {
3696         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3697
3698         if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3699                 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3700                 init_completion(&cmd->completion);
3701                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3702
3703                 spin_lock(&mbx->queue_lock);
3704
3705                 list_add_tail(&cmd->list, &mbx->cmd_q);
3706                 mbx->num_cmds++;
3707                 cmd->total_cmds = mbx->num_cmds;
3708                 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3709                 queue_work(mbx->work_q, &mbx->work);
3710
3711                 spin_unlock(&mbx->queue_lock);
3712
3713                 return 0;
3714         }
3715
3716         return -EBUSY;
3717 }
3718
3719 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3720                                        struct qlcnic_cmd_args *cmd)
3721 {
3722         u8 mac_cmd_rcode;
3723         u32 fw_data;
3724
3725         if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3726                 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3727                 mac_cmd_rcode = (u8)fw_data;
3728                 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3729                     mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3730                     mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3731                         cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3732                         return QLCNIC_RCODE_SUCCESS;
3733                 }
3734         }
3735
3736         return -EINVAL;
3737 }
3738
3739 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3740                                        struct qlcnic_cmd_args *cmd)
3741 {
3742         struct qlcnic_hardware_context *ahw = adapter->ahw;
3743         struct device *dev = &adapter->pdev->dev;
3744         u8 mbx_err_code;
3745         u32 fw_data;
3746
3747         fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3748         mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3749         qlcnic_83xx_get_mbx_data(adapter, cmd);
3750
3751         switch (mbx_err_code) {
3752         case QLCNIC_MBX_RSP_OK:
3753         case QLCNIC_MBX_PORT_RSP_OK:
3754                 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3755                 break;
3756         default:
3757                 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3758                         break;
3759
3760                 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3761                         __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3762                         ahw->op_mode, mbx_err_code);
3763                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3764                 qlcnic_dump_mbx(adapter, cmd);
3765         }
3766
3767         return;
3768 }
3769
3770 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter)
3771 {
3772         struct qlcnic_hardware_context *ahw = adapter->ahw;
3773         u32 offset;
3774
3775         offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
3776         dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x",
3777                  readl(ahw->pci_base0 + offset),
3778                  QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL),
3779                  QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL),
3780                  QLCRDX(ahw, QLCNIC_FW_MBX_CTRL));
3781 }
3782
3783 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3784 {
3785         struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3786                                                   work);
3787         struct qlcnic_adapter *adapter = mbx->adapter;
3788         struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3789         struct device *dev = &adapter->pdev->dev;
3790         atomic_t *rsp_status = &mbx->rsp_status;
3791         struct list_head *head = &mbx->cmd_q;
3792         struct qlcnic_hardware_context *ahw;
3793         struct qlcnic_cmd_args *cmd = NULL;
3794
3795         ahw = adapter->ahw;
3796
3797         while (true) {
3798                 if (qlcnic_83xx_check_mbx_status(adapter)) {
3799                         qlcnic_83xx_flush_mbx_queue(adapter);
3800                         return;
3801                 }
3802
3803                 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3804
3805                 spin_lock(&mbx->queue_lock);
3806
3807                 if (list_empty(head)) {
3808                         spin_unlock(&mbx->queue_lock);
3809                         return;
3810                 }
3811                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3812
3813                 spin_unlock(&mbx->queue_lock);
3814
3815                 mbx_ops->encode_cmd(adapter, cmd);
3816                 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3817
3818                 if (wait_for_completion_timeout(&mbx->completion,
3819                                                 QLC_83XX_MBX_TIMEOUT)) {
3820                         mbx_ops->decode_resp(adapter, cmd);
3821                         mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3822                 } else {
3823                         dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3824                                 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3825                                 ahw->op_mode);
3826                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3827                         qlcnic_dump_mailbox_registers(adapter);
3828                         qlcnic_83xx_get_mbx_data(adapter, cmd);
3829                         qlcnic_dump_mbx(adapter, cmd);
3830                         qlcnic_83xx_idc_request_reset(adapter,
3831                                                       QLCNIC_FORCE_FW_DUMP_KEY);
3832                         cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3833                 }
3834                 mbx_ops->dequeue_cmd(adapter, cmd);
3835         }
3836 }
3837
3838 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3839         .enqueue_cmd    = qlcnic_83xx_enqueue_mbx_cmd,
3840         .dequeue_cmd    = qlcnic_83xx_dequeue_mbx_cmd,
3841         .decode_resp    = qlcnic_83xx_decode_mbx_rsp,
3842         .encode_cmd     = qlcnic_83xx_encode_mbx_cmd,
3843         .nofity_fw      = qlcnic_83xx_signal_mbx_cmd,
3844 };
3845
3846 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3847 {
3848         struct qlcnic_hardware_context *ahw = adapter->ahw;
3849         struct qlcnic_mailbox *mbx;
3850
3851         ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3852         if (!ahw->mailbox)
3853                 return -ENOMEM;
3854
3855         mbx = ahw->mailbox;
3856         mbx->ops = &qlcnic_83xx_mbx_ops;
3857         mbx->adapter = adapter;
3858
3859         spin_lock_init(&mbx->queue_lock);
3860         spin_lock_init(&mbx->aen_lock);
3861         INIT_LIST_HEAD(&mbx->cmd_q);
3862         init_completion(&mbx->completion);
3863
3864         mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3865         if (mbx->work_q == NULL) {
3866                 kfree(mbx);
3867                 return -ENOMEM;
3868         }
3869
3870         INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
3871         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3872         return 0;
3873 }
3874
3875 pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
3876                                                pci_channel_state_t state)
3877 {
3878         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3879
3880         if (state == pci_channel_io_perm_failure)
3881                 return PCI_ERS_RESULT_DISCONNECT;
3882
3883         if (state == pci_channel_io_normal)
3884                 return PCI_ERS_RESULT_RECOVERED;
3885
3886         set_bit(__QLCNIC_AER, &adapter->state);
3887         set_bit(__QLCNIC_RESETTING, &adapter->state);
3888
3889         qlcnic_83xx_aer_stop_poll_work(adapter);
3890
3891         pci_save_state(pdev);
3892         pci_disable_device(pdev);
3893
3894         return PCI_ERS_RESULT_NEED_RESET;
3895 }
3896
3897 pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
3898 {
3899         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3900         int err = 0;
3901
3902         pdev->error_state = pci_channel_io_normal;
3903         err = pci_enable_device(pdev);
3904         if (err)
3905                 goto disconnect;
3906
3907         pci_set_power_state(pdev, PCI_D0);
3908         pci_set_master(pdev);
3909         pci_restore_state(pdev);
3910
3911         err = qlcnic_83xx_aer_reset(adapter);
3912         if (err == 0)
3913                 return PCI_ERS_RESULT_RECOVERED;
3914 disconnect:
3915         clear_bit(__QLCNIC_AER, &adapter->state);
3916         clear_bit(__QLCNIC_RESETTING, &adapter->state);
3917         return PCI_ERS_RESULT_DISCONNECT;
3918 }
3919
3920 void qlcnic_83xx_io_resume(struct pci_dev *pdev)
3921 {
3922         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3923
3924         pci_cleanup_aer_uncorrect_error_status(pdev);
3925         if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
3926                 qlcnic_83xx_aer_start_poll_work(adapter);
3927 }