Pileus Git - ~andy/linux/blob - drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_sriov.h"
  10 #include <linux/if_vlan.h>
  11 #include <linux/ipv6.h>
  12 #include <linux/ethtool.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/aer.h>
  15
  16 #define RSS_HASHTYPE_IP_TCP             0x3
  17 #define QLC_83XX_FW_MBX_CMD             0
  18
  19 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
  20         {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
  21         {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
  22         {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
  23         {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  24         {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
  25         {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  26         {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
  27         {QLCNIC_CMD_INTRPT_TEST, 22, 12},
  28         {QLCNIC_CMD_SET_MTU, 3, 1},
  29         {QLCNIC_CMD_READ_PHY, 4, 2},
  30         {QLCNIC_CMD_WRITE_PHY, 5, 1},
  31         {QLCNIC_CMD_READ_HW_REG, 4, 1},
  32         {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  33         {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  34         {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  35         {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  36         {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  37         {QLCNIC_CMD_GET_PCI_INFO, 1, 66},
  38         {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
  39         {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
  40         {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  41         {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  42         {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  43         {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  44         {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  45         {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  46         {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  47         {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  48         {QLCNIC_CMD_TEMP_SIZE, 1, 4},
  49         {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
  50         {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
  51         {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
  52         {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
  53         {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
  54         {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
  55         {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
  56         {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
  57         {QLCNIC_CMD_GET_STATISTICS, 2, 80},
  58         {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
  59         {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
  60         {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
  61         {QLCNIC_CMD_IDC_ACK, 5, 1},
  62         {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
  63         {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
  64         {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
  65         {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
  66         {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
  67         {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
  68         {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
  69         {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
  70         {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
  71         {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
  72 };
  73
  74 const u32 qlcnic_83xx_ext_reg_tbl[] = {
  75         0x38CC,         /* Global Reset */
  76         0x38F0,         /* Wildcard */
  77         0x38FC,         /* Informant */
  78         0x3038,         /* Host MBX ctrl */
  79         0x303C,         /* FW MBX ctrl */
  80         0x355C,         /* BOOT LOADER ADDRESS REG */
  81         0x3560,         /* BOOT LOADER SIZE REG */
  82         0x3564,         /* FW IMAGE ADDR REG */
  83         0x1000,         /* MBX intr enable */
  84         0x1200,         /* Default Intr mask */
  85         0x1204,         /* Default Interrupt ID */
  86         0x3780,         /* QLC_83XX_IDC_MAJ_VERSION */
  87         0x3784,         /* QLC_83XX_IDC_DEV_STATE */
  88         0x3788,         /* QLC_83XX_IDC_DRV_PRESENCE */
  89         0x378C,         /* QLC_83XX_IDC_DRV_ACK */
  90         0x3790,         /* QLC_83XX_IDC_CTRL */
  91         0x3794,         /* QLC_83XX_IDC_DRV_AUDIT */
  92         0x3798,         /* QLC_83XX_IDC_MIN_VERSION */
  93         0x379C,         /* QLC_83XX_RECOVER_DRV_LOCK */
  94         0x37A0,         /* QLC_83XX_IDC_PF_0 */
  95         0x37A4,         /* QLC_83XX_IDC_PF_1 */
  96         0x37A8,         /* QLC_83XX_IDC_PF_2 */
  97         0x37AC,         /* QLC_83XX_IDC_PF_3 */
  98         0x37B0,         /* QLC_83XX_IDC_PF_4 */
  99         0x37B4,         /* QLC_83XX_IDC_PF_5 */
 100         0x37B8,         /* QLC_83XX_IDC_PF_6 */
 101         0x37BC,         /* QLC_83XX_IDC_PF_7 */
 102         0x37C0,         /* QLC_83XX_IDC_PF_8 */
 103         0x37C4,         /* QLC_83XX_IDC_PF_9 */
 104         0x37C8,         /* QLC_83XX_IDC_PF_10 */
 105         0x37CC,         /* QLC_83XX_IDC_PF_11 */
 106         0x37D0,         /* QLC_83XX_IDC_PF_12 */
 107         0x37D4,         /* QLC_83XX_IDC_PF_13 */
 108         0x37D8,         /* QLC_83XX_IDC_PF_14 */
 109         0x37DC,         /* QLC_83XX_IDC_PF_15 */
 110         0x37E0,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
 111         0x37E4,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
 112         0x37F0,         /* QLC_83XX_DRV_OP_MODE */
 113         0x37F4,         /* QLC_83XX_VNIC_STATE */
 114         0x3868,         /* QLC_83XX_DRV_LOCK */
 115         0x386C,         /* QLC_83XX_DRV_UNLOCK */
 116         0x3504,         /* QLC_83XX_DRV_LOCK_ID */
 117         0x34A4,         /* QLC_83XX_ASIC_TEMP */
 118 };
 119
 120 const u32 qlcnic_83xx_reg_tbl[] = {
 121         0x34A8,         /* PEG_HALT_STAT1 */
 122         0x34AC,         /* PEG_HALT_STAT2 */
 123         0x34B0,         /* FW_HEARTBEAT */
 124         0x3500,         /* FLASH LOCK_ID */
 125         0x3528,         /* FW_CAPABILITIES */
 126         0x3538,         /* Driver active, DRV_REG0 */
 127         0x3540,         /* Device state, DRV_REG1 */
 128         0x3544,         /* Driver state, DRV_REG2 */
 129         0x3548,         /* Driver scratch, DRV_REG3 */
 130         0x354C,         /* Device partiton info, DRV_REG4 */
 131         0x3524,         /* Driver IDC ver, DRV_REG5 */
 132         0x3550,         /* FW_VER_MAJOR */
 133         0x3554,         /* FW_VER_MINOR */
 134         0x3558,         /* FW_VER_SUB */
 135         0x359C,         /* NPAR STATE */
 136         0x35FC,         /* FW_IMG_VALID */
 137         0x3650,         /* CMD_PEG_STATE */
 138         0x373C,         /* RCV_PEG_STATE */
 139         0x37B4,         /* ASIC TEMP */
 140         0x356C,         /* FW API */
 141         0x3570,         /* DRV OP MODE */
 142         0x3850,         /* FLASH LOCK */
 143         0x3854,         /* FLASH UNLOCK */
 144 };
 145
 146 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
 147         .read_crb                       = qlcnic_83xx_read_crb,
 148         .write_crb                      = qlcnic_83xx_write_crb,
 149         .read_reg                       = qlcnic_83xx_rd_reg_indirect,
 150         .write_reg                      = qlcnic_83xx_wrt_reg_indirect,
 151         .get_mac_address                = qlcnic_83xx_get_mac_address,
 152         .setup_intr                     = qlcnic_83xx_setup_intr,
 153         .alloc_mbx_args                 = qlcnic_83xx_alloc_mbx_args,
 154         .mbx_cmd                        = qlcnic_83xx_issue_cmd,
 155         .get_func_no                    = qlcnic_83xx_get_func_no,
 156         .api_lock                       = qlcnic_83xx_cam_lock,
 157         .api_unlock                     = qlcnic_83xx_cam_unlock,
 158         .add_sysfs                      = qlcnic_83xx_add_sysfs,
 159         .remove_sysfs                   = qlcnic_83xx_remove_sysfs,
 160         .process_lb_rcv_ring_diag       = qlcnic_83xx_process_rcv_ring_diag,
 161         .create_rx_ctx                  = qlcnic_83xx_create_rx_ctx,
 162         .create_tx_ctx                  = qlcnic_83xx_create_tx_ctx,
 163         .del_rx_ctx                     = qlcnic_83xx_del_rx_ctx,
 164         .del_tx_ctx                     = qlcnic_83xx_del_tx_ctx,
 165         .setup_link_event               = qlcnic_83xx_setup_link_event,
 166         .get_nic_info                   = qlcnic_83xx_get_nic_info,
 167         .get_pci_info                   = qlcnic_83xx_get_pci_info,
 168         .set_nic_info                   = qlcnic_83xx_set_nic_info,
 169         .change_macvlan                 = qlcnic_83xx_sre_macaddr_change,
 170         .napi_enable                    = qlcnic_83xx_napi_enable,
 171         .napi_disable                   = qlcnic_83xx_napi_disable,
 172         .config_intr_coal               = qlcnic_83xx_config_intr_coal,
 173         .config_rss                     = qlcnic_83xx_config_rss,
 174         .config_hw_lro                  = qlcnic_83xx_config_hw_lro,
 175         .config_promisc_mode            = qlcnic_83xx_nic_set_promisc,
 176         .change_l2_filter               = qlcnic_83xx_change_l2_filter,
 177         .get_board_info                 = qlcnic_83xx_get_port_info,
 178         .set_mac_filter_count           = qlcnic_83xx_set_mac_filter_count,
 179         .free_mac_list                  = qlcnic_82xx_free_mac_list,
 180         .io_error_detected              = qlcnic_83xx_io_error_detected,
 181         .io_slot_reset                  = qlcnic_83xx_io_slot_reset,
 182         .io_resume                      = qlcnic_83xx_io_resume,
 183
 184 };
 185
 186 static struct qlcnic_nic_template qlcnic_83xx_ops = {
 187         .config_bridged_mode    = qlcnic_config_bridged_mode,
 188         .config_led             = qlcnic_config_led,
 189         .request_reset          = qlcnic_83xx_idc_request_reset,
 190         .cancel_idc_work        = qlcnic_83xx_idc_exit,
 191         .napi_add               = qlcnic_83xx_napi_add,
 192         .napi_del               = qlcnic_83xx_napi_del,
 193         .config_ipaddr          = qlcnic_83xx_config_ipaddr,
 194         .clear_legacy_intr      = qlcnic_83xx_clear_legacy_intr,
 195         .shutdown               = qlcnic_83xx_shutdown,
 196         .resume                 = qlcnic_83xx_resume,
 197 };
 198
 199 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
 200 {
 201         ahw->hw_ops             = &qlcnic_83xx_hw_ops;
 202         ahw->reg_tbl            = (u32 *)qlcnic_83xx_reg_tbl;
 203         ahw->ext_reg_tbl        = (u32 *)qlcnic_83xx_ext_reg_tbl;
 204 }
 205
 206 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
 207 {
 208         u32 fw_major, fw_minor, fw_build;
 209         struct pci_dev *pdev = adapter->pdev;
 210
 211         fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
 212         fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
 213         fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
 214         adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
 215
 216         dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
 217                  QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
 218
 219         return adapter->fw_version;
 220 }
 221
 222 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
 223 {
 224         void __iomem *base;
 225         u32 val;
 226
 227         base = adapter->ahw->pci_base0 +
 228                QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
 229         writel(addr, base);
 230         val = readl(base);
 231         if (val != addr)
 232                 return -EIO;
 233
 234         return 0;
 235 }
 236
 237 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 238                                 int *err)
 239 {
 240         struct qlcnic_hardware_context *ahw = adapter->ahw;
 241
 242         *err = __qlcnic_set_win_base(adapter, (u32) addr);
 243         if (!*err) {
 244                 return QLCRDX(ahw, QLCNIC_WILDCARD);
 245         } else {
 246                 dev_err(&adapter->pdev->dev,
 247                         "%s failed, addr = 0x%lx\n", __func__, addr);
 248                 return -EIO;
 249         }
 250 }
 251
 252 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 253                                  u32 data)
 254 {
 255         int err;
 256         struct qlcnic_hardware_context *ahw = adapter->ahw;
 257
 258         err = __qlcnic_set_win_base(adapter, (u32) addr);
 259         if (!err) {
 260                 QLCWRX(ahw, QLCNIC_WILDCARD, data);
 261                 return 0;
 262         } else {
 263                 dev_err(&adapter->pdev->dev,
 264                         "%s failed, addr = 0x%x data = 0x%x\n",
 265                         __func__, (int)addr, data);
 266                 return err;
 267         }
 268 }
 269
 270 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
 271 {
 272         int err, i, num_msix;
 273         struct qlcnic_hardware_context *ahw = adapter->ahw;
 274
 275         num_msix = adapter->drv_sds_rings;
 276
 277         /* account for AEN interrupt MSI-X based interrupts */
 278         num_msix += 1;
 279
 280         if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
 281                 num_msix += adapter->drv_tx_rings;
 282
 283         err = qlcnic_enable_msix(adapter, num_msix);
 284         if (err == -ENOMEM)
 285                 return err;
 286         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 287                 num_msix = adapter->ahw->num_msix;
 288         else {
 289                 if (qlcnic_sriov_vf_check(adapter))
 290                         return -EINVAL;
 291                 num_msix = 1;
 292         }
 293         /* setup interrupt mapping table for fw */
 294         ahw->intr_tbl = vzalloc(num_msix *
 295                                 sizeof(struct qlcnic_intrpt_config));
 296         if (!ahw->intr_tbl)
 297                 return -ENOMEM;
 298         if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
 299                 /* MSI-X enablement failed, use legacy interrupt */
 300                 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
 301                 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
 302                 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
 303                 adapter->msix_entries[0].vector = adapter->pdev->irq;
 304                 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
 305         }
 306
 307         for (i = 0; i < num_msix; i++) {
 308                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
 309                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
 310                 else
 311                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
 312                 ahw->intr_tbl[i].id = i;
 313                 ahw->intr_tbl[i].src = 0;
 314         }
 315         return 0;
 316 }
 317
 318 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
 319 {
 320         writel(0, adapter->tgt_mask_reg);
 321 }
 322
 323 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
 324 {
 325         if (adapter->tgt_mask_reg)
 326                 writel(1, adapter->tgt_mask_reg);
 327 }
 328
 329 /* Enable MSI-x and INT-x interrupts */
 330 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
 331                              struct qlcnic_host_sds_ring *sds_ring)
 332 {
 333         writel(0, sds_ring->crb_intr_mask);
 334 }
 335
 336 /* Disable MSI-x and INT-x interrupts */
 337 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
 338                               struct qlcnic_host_sds_ring *sds_ring)
 339 {
 340         writel(1, sds_ring->crb_intr_mask);
 341 }
 342
 343 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
 344                                                     *adapter)
 345 {
 346         u32 mask;
 347
 348         /* Mailbox in MSI-x mode and Legacy Interrupt share the same
 349          * source register. We could be here before contexts are created
 350          * and sds_ring->crb_intr_mask has not been initialized, calculate
 351          * BAR offset for Interrupt Source Register
 352          */
 353         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 354         writel(0, adapter->ahw->pci_base0 + mask);
 355 }
 356
 357 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
 358 {
 359         u32 mask;
 360
 361         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 362         writel(1, adapter->ahw->pci_base0 + mask);
 363         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
 364 }
 365
 366 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
 367                                      struct qlcnic_cmd_args *cmd)
 368 {
 369         int i;
 370
 371         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 372                 return;
 373
 374         for (i = 0; i < cmd->rsp.num; i++)
 375                 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
 376 }
 377
 378 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
 379 {
 380         u32 intr_val;
 381         struct qlcnic_hardware_context *ahw = adapter->ahw;
 382         int retries = 0;
 383
 384         intr_val = readl(adapter->tgt_status_reg);
 385
 386         if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
 387                 return IRQ_NONE;
 388
 389         if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
 390                 adapter->stats.spurious_intr++;
 391                 return IRQ_NONE;
 392         }
 393         /* The barrier is required to ensure writes to the registers */
 394         wmb();
 395
 396         /* clear the interrupt trigger control register */
 397         writel(0, adapter->isr_int_vec);
 398         intr_val = readl(adapter->isr_int_vec);
 399         do {
 400                 intr_val = readl(adapter->tgt_status_reg);
 401                 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
 402                         break;
 403                 retries++;
 404         } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
 405                  (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
 406
 407         return IRQ_HANDLED;
 408 }
 409
 410 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
 411 {
 412         atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
 413         complete(&mbx->completion);
 414 }
 415
 416 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
 417 {
 418         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 419         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 420         unsigned long flags;
 421
 422         spin_lock_irqsave(&mbx->aen_lock, flags);
 423         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
 424         if (!(resp & QLCNIC_SET_OWNER))
 425                 goto out;
 426
 427         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
 428         if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 429                 __qlcnic_83xx_process_aen(adapter);
 430         } else {
 431                 if (atomic_read(&mbx->rsp_status) != rsp_status)
 432                         qlcnic_83xx_notify_mbx_response(mbx);
 433         }
 434 out:
 435         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 436         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 437 }
 438
 439 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
 440 {
 441         struct qlcnic_adapter *adapter = data;
 442         struct qlcnic_host_sds_ring *sds_ring;
 443         struct qlcnic_hardware_context *ahw = adapter->ahw;
 444
 445         if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
 446                 return IRQ_NONE;
 447
 448         qlcnic_83xx_poll_process_aen(adapter);
 449
 450         if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
 451                 ahw->diag_cnt++;
 452                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 453                 return IRQ_HANDLED;
 454         }
 455
 456         if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
 457                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 458         } else {
 459                 sds_ring = &adapter->recv_ctx->sds_rings[0];
 460                 napi_schedule(&sds_ring->napi);
 461         }
 462
 463         return IRQ_HANDLED;
 464 }
 465
 466 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
 467 {
 468         struct qlcnic_host_sds_ring *sds_ring = data;
 469         struct qlcnic_adapter *adapter = sds_ring->adapter;
 470
 471         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 472                 goto done;
 473
 474         if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
 475                 return IRQ_NONE;
 476
 477 done:
 478         adapter->ahw->diag_cnt++;
 479         qlcnic_83xx_enable_intr(adapter, sds_ring);
 480
 481         return IRQ_HANDLED;
 482 }
 483
 484 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
 485 {
 486         u32 num_msix;
 487
 488         if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
 489                 qlcnic_83xx_set_legacy_intr_mask(adapter);
 490
 491         qlcnic_83xx_disable_mbx_intr(adapter);
 492
 493         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 494                 num_msix = adapter->ahw->num_msix - 1;
 495         else
 496                 num_msix = 0;
 497
 498         msleep(20);
 499
 500         if (adapter->msix_entries) {
 501                 synchronize_irq(adapter->msix_entries[num_msix].vector);
 502                 free_irq(adapter->msix_entries[num_msix].vector, adapter);
 503         }
 504 }
 505
 506 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
 507 {
 508         irq_handler_t handler;
 509         u32 val;
 510         int err = 0;
 511         unsigned long flags = 0;
 512
 513         if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
 514             !(adapter->flags & QLCNIC_MSIX_ENABLED))
 515                 flags |= IRQF_SHARED;
 516
 517         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 518                 handler = qlcnic_83xx_handle_aen;
 519                 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
 520                 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
 521                 if (err) {
 522                         dev_err(&adapter->pdev->dev,
 523                                 "failed to register MBX interrupt\n");
 524                         return err;
 525                 }
 526         } else {
 527                 handler = qlcnic_83xx_intr;
 528                 val = adapter->msix_entries[0].vector;
 529                 err = request_irq(val, handler, flags, "qlcnic", adapter);
 530                 if (err) {
 531                         dev_err(&adapter->pdev->dev,
 532                                 "failed to register INTx interrupt\n");
 533                         return err;
 534                 }
 535                 qlcnic_83xx_clear_legacy_intr_mask(adapter);
 536         }
 537
 538         /* Enable mailbox interrupt */
 539         qlcnic_83xx_enable_mbx_interrupt(adapter);
 540
 541         return err;
 542 }
 543
 544 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
 545 {
 546         u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
 547         adapter->ahw->pci_func = (val >> 24) & 0xff;
 548 }
 549
 550 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
 551 {
 552         void __iomem *addr;
 553         u32 val, limit = 0;
 554
 555         struct qlcnic_hardware_context *ahw = adapter->ahw;
 556
 557         addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
 558         do {
 559                 val = readl(addr);
 560                 if (val) {
 561                         /* write the function number to register */
 562                         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
 563                                             ahw->pci_func);
 564                         return 0;
 565                 }
 566                 usleep_range(1000, 2000);
 567         } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
 568
 569         return -EIO;
 570 }
 571
 572 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
 573 {
 574         void __iomem *addr;
 575         u32 val;
 576         struct qlcnic_hardware_context *ahw = adapter->ahw;
 577
 578         addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
 579         val = readl(addr);
 580 }
 581
 582 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
 583                           loff_t offset, size_t size)
 584 {
 585         int ret = 0;
 586         u32 data;
 587
 588         if (qlcnic_api_lock(adapter)) {
 589                 dev_err(&adapter->pdev->dev,
 590                         "%s: failed to acquire lock. addr offset 0x%x\n",
 591                         __func__, (u32)offset);
 592                 return;
 593         }
 594
 595         data = QLCRD32(adapter, (u32) offset, &ret);
 596         qlcnic_api_unlock(adapter);
 597
 598         if (ret == -EIO) {
 599                 dev_err(&adapter->pdev->dev,
 600                         "%s: failed. addr offset 0x%x\n",
 601                         __func__, (u32)offset);
 602                 return;
 603         }
 604         memcpy(buf, &data, size);
 605 }
 606
 607 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
 608                            loff_t offset, size_t size)
 609 {
 610         u32 data;
 611
 612         memcpy(&data, buf, size);
 613         qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
 614 }
 615
 616 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
 617 {
 618         int status;
 619
 620         status = qlcnic_83xx_get_port_config(adapter);
 621         if (status) {
 622                 dev_err(&adapter->pdev->dev,
 623                         "Get Port Info failed\n");
 624         } else {
 625                 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
 626                         adapter->ahw->port_type = QLCNIC_XGBE;
 627                 else
 628                         adapter->ahw->port_type = QLCNIC_GBE;
 629
 630                 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
 631                         adapter->ahw->link_autoneg = AUTONEG_ENABLE;
 632         }
 633         return status;
 634 }
 635
 636 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
 637 {
 638         struct qlcnic_hardware_context *ahw = adapter->ahw;
 639         u16 act_pci_fn = ahw->act_pci_func;
 640         u16 count;
 641
 642         ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
 643         if (act_pci_fn <= 2)
 644                 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
 645                          act_pci_fn;
 646         else
 647                 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
 648                          act_pci_fn;
 649         ahw->max_uc_count = count;
 650 }
 651
 652 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
 653 {
 654         u32 val;
 655
 656         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 657                 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
 658         else
 659                 val = BIT_2;
 660
 661         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
 662         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 663 }
 664
 665 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
 666                           const struct pci_device_id *ent)
 667 {
 668         u32 op_mode, priv_level;
 669         struct qlcnic_hardware_context *ahw = adapter->ahw;
 670
 671         ahw->fw_hal_version = 2;
 672         qlcnic_get_func_no(adapter);
 673
 674         if (qlcnic_sriov_vf_check(adapter)) {
 675                 qlcnic_sriov_vf_set_ops(adapter);
 676                 return;
 677         }
 678
 679         /* Determine function privilege level */
 680         op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
 681         if (op_mode == QLC_83XX_DEFAULT_OPMODE)
 682                 priv_level = QLCNIC_MGMT_FUNC;
 683         else
 684                 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
 685                                                          ahw->pci_func);
 686
 687         if (priv_level == QLCNIC_NON_PRIV_FUNC) {
 688                 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
 689                 dev_info(&adapter->pdev->dev,
 690                          "HAL Version: %d Non Privileged function\n",
 691                          ahw->fw_hal_version);
 692                 adapter->nic_ops = &qlcnic_vf_ops;
 693         } else {
 694                 if (pci_find_ext_capability(adapter->pdev,
 695                                             PCI_EXT_CAP_ID_SRIOV))
 696                         set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
 697                 adapter->nic_ops = &qlcnic_83xx_ops;
 698         }
 699 }
 700
 701 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
 702                                         u32 data[]);
 703 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 704                                             u32 data[]);
 705
 706 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
 707                      struct qlcnic_cmd_args *cmd)
 708 {
 709         int i;
 710
 711         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 712                 return;
 713
 714         dev_info(&adapter->pdev->dev,
 715                  "Host MBX regs(%d)\n", cmd->req.num);
 716         for (i = 0; i < cmd->req.num; i++) {
 717                 if (i && !(i % 8))
 718                         pr_info("\n");
 719                 pr_info("%08x ", cmd->req.arg[i]);
 720         }
 721         pr_info("\n");
 722         dev_info(&adapter->pdev->dev,
 723                  "FW MBX regs(%d)\n", cmd->rsp.num);
 724         for (i = 0; i < cmd->rsp.num; i++) {
 725                 if (i && !(i % 8))
 726                         pr_info("\n");
 727                 pr_info("%08x ", cmd->rsp.arg[i]);
 728         }
 729         pr_info("\n");
 730 }
 731
 732 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
 733                                                 struct qlcnic_cmd_args *cmd)
 734 {
 735         struct qlcnic_hardware_context *ahw = adapter->ahw;
 736         int opcode = LSW(cmd->req.arg[0]);
 737         unsigned long max_loops;
 738
 739         max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
 740
 741         for (; max_loops; max_loops--) {
 742                 if (atomic_read(&cmd->rsp_status) ==
 743                     QLC_83XX_MBX_RESPONSE_ARRIVED)
 744                         return;
 745
 746                 udelay(1);
 747         }
 748
 749         dev_err(&adapter->pdev->dev,
 750                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 751                 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
 752         flush_workqueue(ahw->mailbox->work_q);
 753         return;
 754 }
 755
 756 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
 757                           struct qlcnic_cmd_args *cmd)
 758 {
 759         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 760         struct qlcnic_hardware_context *ahw = adapter->ahw;
 761         int cmd_type, err, opcode;
 762         unsigned long timeout;
 763
 764         if (!mbx)
 765                 return -EIO;
 766
 767         opcode = LSW(cmd->req.arg[0]);
 768         cmd_type = cmd->type;
 769         err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
 770         if (err) {
 771                 dev_err(&adapter->pdev->dev,
 772                         "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 773                         __func__, opcode, cmd->type, ahw->pci_func,
 774                         ahw->op_mode);
 775                 return err;
 776         }
 777
 778         switch (cmd_type) {
 779         case QLC_83XX_MBX_CMD_WAIT:
 780                 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
 781                         dev_err(&adapter->pdev->dev,
 782                                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 783                                 __func__, opcode, cmd_type, ahw->pci_func,
 784                                 ahw->op_mode);
 785                         flush_workqueue(mbx->work_q);
 786                 }
 787                 break;
 788         case QLC_83XX_MBX_CMD_NO_WAIT:
 789                 return 0;
 790         case QLC_83XX_MBX_CMD_BUSY_WAIT:
 791                 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
 792                 break;
 793         default:
 794                 dev_err(&adapter->pdev->dev,
 795                         "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 796                         __func__, opcode, cmd_type, ahw->pci_func,
 797                         ahw->op_mode);
 798                 qlcnic_83xx_detach_mailbox_work(adapter);
 799         }
 800
 801         return cmd->rsp_opcode;
 802 }
 803
 804 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
 805                                struct qlcnic_adapter *adapter, u32 type)
 806 {
 807         int i, size;
 808         u32 temp;
 809         const struct qlcnic_mailbox_metadata *mbx_tbl;
 810
 811         memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
 812         mbx_tbl = qlcnic_83xx_mbx_tbl;
 813         size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
 814         for (i = 0; i < size; i++) {
 815                 if (type == mbx_tbl[i].cmd) {
 816                         mbx->op_type = QLC_83XX_FW_MBX_CMD;
 817                         mbx->req.num = mbx_tbl[i].in_args;
 818                         mbx->rsp.num = mbx_tbl[i].out_args;
 819                         mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
 820                                                GFP_ATOMIC);
 821                         if (!mbx->req.arg)
 822                                 return -ENOMEM;
 823                         mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
 824                                                GFP_ATOMIC);
 825                         if (!mbx->rsp.arg) {
 826                                 kfree(mbx->req.arg);
 827                                 mbx->req.arg = NULL;
 828                                 return -ENOMEM;
 829                         }
 830                         memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
 831                         memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
 832                         temp = adapter->ahw->fw_hal_version << 29;
 833                         mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
 834                         mbx->cmd_op = type;
 835                         return 0;
 836                 }
 837         }
 838         return -EINVAL;
 839 }
 840
 841 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
 842 {
 843         struct qlcnic_adapter *adapter;
 844         struct qlcnic_cmd_args cmd;
 845         int i, err = 0;
 846
 847         adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
 848         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
 849         if (err)
 850                 return;
 851
 852         for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
 853                 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
 854
 855         err = qlcnic_issue_cmd(adapter, &cmd);
 856         if (err)
 857                 dev_info(&adapter->pdev->dev,
 858                          "%s: Mailbox IDC ACK failed.\n", __func__);
 859         qlcnic_free_mbx_args(&cmd);
 860 }
 861
 862 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 863                                             u32 data[])
 864 {
 865         dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
 866                 QLCNIC_MBX_RSP(data[0]));
 867         clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
 868         return;
 869 }
 870
 871 void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 872 {
 873         struct qlcnic_hardware_context *ahw = adapter->ahw;
 874         u32 event[QLC_83XX_MBX_AEN_CNT];
 875         int i;
 876
 877         for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 878                 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
 879
 880         switch (QLCNIC_MBX_RSP(event[0])) {
 881
 882         case QLCNIC_MBX_LINK_EVENT:
 883                 qlcnic_83xx_handle_link_aen(adapter, event);
 884                 break;
 885         case QLCNIC_MBX_COMP_EVENT:
 886                 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
 887                 break;
 888         case QLCNIC_MBX_REQUEST_EVENT:
 889                 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 890                         adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
 891                 queue_delayed_work(adapter->qlcnic_wq,
 892                                    &adapter->idc_aen_work, 0);
 893                 break;
 894         case QLCNIC_MBX_TIME_EXTEND_EVENT:
 895                 ahw->extend_lb_time = event[1] >> 8 & 0xf;
 896                 break;
 897         case QLCNIC_MBX_BC_EVENT:
 898                 qlcnic_sriov_handle_bc_event(adapter, event[1]);
 899                 break;
 900         case QLCNIC_MBX_SFP_INSERT_EVENT:
 901                 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
 902                          QLCNIC_MBX_RSP(event[0]));
 903                 break;
 904         case QLCNIC_MBX_SFP_REMOVE_EVENT:
 905                 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
 906                          QLCNIC_MBX_RSP(event[0]));
 907                 break;
 908         case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
 909                 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
 910                 break;
 911         default:
 912                 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
 913                         QLCNIC_MBX_RSP(event[0]));
 914                 break;
 915         }
 916
 917         QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
 918 }
 919
 920 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 921 {
 922         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 923         struct qlcnic_hardware_context *ahw = adapter->ahw;
 924         struct qlcnic_mailbox *mbx = ahw->mailbox;
 925         unsigned long flags;
 926
 927         spin_lock_irqsave(&mbx->aen_lock, flags);
 928         resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
 929         if (resp & QLCNIC_SET_OWNER) {
 930                 event = readl(QLCNIC_MBX_FW(ahw, 0));
 931                 if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 932                         __qlcnic_83xx_process_aen(adapter);
 933                 } else {
 934                         if (atomic_read(&mbx->rsp_status) != rsp_status)
 935                                 qlcnic_83xx_notify_mbx_response(mbx);
 936                 }
 937         }
 938         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 939 }
 940
 941 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
 942 {
 943         struct qlcnic_adapter *adapter;
 944
 945         adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
 946
 947         if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 948                 return;
 949
 950         qlcnic_83xx_process_aen(adapter);
 951         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
 952                            (HZ / 10));
 953 }
 954
 955 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
 956 {
 957         if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 958                 return;
 959
 960         INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
 961         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
 962 }
 963
 964 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
 965 {
 966         if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 967                 return;
 968         cancel_delayed_work_sync(&adapter->mbx_poll_work);
 969 }
 970
 971 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
 972 {
 973         int index, i, err, sds_mbx_size;
 974         u32 *buf, intrpt_id, intr_mask;
 975         u16 context_id;
 976         u8 num_sds;
 977         struct qlcnic_cmd_args cmd;
 978         struct qlcnic_host_sds_ring *sds;
 979         struct qlcnic_sds_mbx sds_mbx;
 980         struct qlcnic_add_rings_mbx_out *mbx_out;
 981         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
 982         struct qlcnic_hardware_context *ahw = adapter->ahw;
 983
 984         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
 985         context_id = recv_ctx->context_id;
 986         num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
 987         ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
 988                                     QLCNIC_CMD_ADD_RCV_RINGS);
 989         cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
 990
 991         /* set up status rings, mbx 2-81 */
 992         index = 2;
 993         for (i = 8; i < adapter->drv_sds_rings; i++) {
 994                 memset(&sds_mbx, 0, sds_mbx_size);
 995                 sds = &recv_ctx->sds_rings[i];
 996                 sds->consumer = 0;
 997                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
 998                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
 999                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1000                 sds_mbx.sds_ring_size = sds->num_desc;
1001
1002                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1003                         intrpt_id = ahw->intr_tbl[i].id;
1004                 else
1005                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1006
1007                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1008                         sds_mbx.intrpt_id = intrpt_id;
1009                 else
1010                         sds_mbx.intrpt_id = 0xffff;
1011                 sds_mbx.intrpt_val = 0;
1012                 buf = &cmd.req.arg[index];
1013                 memcpy(buf, &sds_mbx, sds_mbx_size);
1014                 index += sds_mbx_size / sizeof(u32);
1015         }
1016
1017         /* send the mailbox command */
1018         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1019         if (err) {
1020                 dev_err(&adapter->pdev->dev,
1021                         "Failed to add rings %d\n", err);
1022                 goto out;
1023         }
1024
1025         mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1026         index = 0;
1027         /* status descriptor ring */
1028         for (i = 8; i < adapter->drv_sds_rings; i++) {
1029                 sds = &recv_ctx->sds_rings[i];
1030                 sds->crb_sts_consumer = ahw->pci_base0 +
1031                                         mbx_out->host_csmr[index];
1032                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1033                         intr_mask = ahw->intr_tbl[i].src;
1034                 else
1035                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1036
1037                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1038                 index++;
1039         }
1040 out:
1041         qlcnic_free_mbx_args(&cmd);
1042         return err;
1043 }
1044
1045 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1046 {
1047         int err;
1048         u32 temp = 0;
1049         struct qlcnic_cmd_args cmd;
1050         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1051
1052         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1053                 return;
1054
1055         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1056                 cmd.req.arg[0] |= (0x3 << 29);
1057
1058         if (qlcnic_sriov_pf_check(adapter))
1059                 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1060
1061         cmd.req.arg[1] = recv_ctx->context_id | temp;
1062         err = qlcnic_issue_cmd(adapter, &cmd);
1063         if (err)
1064                 dev_err(&adapter->pdev->dev,
1065                         "Failed to destroy rx ctx in firmware\n");
1066
1067         recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1068         qlcnic_free_mbx_args(&cmd);
1069 }
1070
1071 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1072 {
1073         int i, err, index, sds_mbx_size, rds_mbx_size;
1074         u8 num_sds, num_rds;
1075         u32 *buf, intrpt_id, intr_mask, cap = 0;
1076         struct qlcnic_host_sds_ring *sds;
1077         struct qlcnic_host_rds_ring *rds;
1078         struct qlcnic_sds_mbx sds_mbx;
1079         struct qlcnic_rds_mbx rds_mbx;
1080         struct qlcnic_cmd_args cmd;
1081         struct qlcnic_rcv_mbx_out *mbx_out;
1082         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1083         struct qlcnic_hardware_context *ahw = adapter->ahw;
1084         num_rds = adapter->max_rds_rings;
1085
1086         if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1087                 num_sds = adapter->drv_sds_rings;
1088         else
1089                 num_sds = QLCNIC_MAX_SDS_RINGS;
1090
1091         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1092         rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1093         cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1094
1095         if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1096                 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1097
1098         /* set mailbox hdr and capabilities */
1099         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1100                                     QLCNIC_CMD_CREATE_RX_CTX);
1101         if (err)
1102                 return err;
1103
1104         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1105                 cmd.req.arg[0] |= (0x3 << 29);
1106
1107         cmd.req.arg[1] = cap;
1108         cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1109                          (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1110
1111         if (qlcnic_sriov_pf_check(adapter))
1112                 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1113                                                          &cmd.req.arg[6]);
1114         /* set up status rings, mbx 8-57/87 */
1115         index = QLC_83XX_HOST_SDS_MBX_IDX;
1116         for (i = 0; i < num_sds; i++) {
1117                 memset(&sds_mbx, 0, sds_mbx_size);
1118                 sds = &recv_ctx->sds_rings[i];
1119                 sds->consumer = 0;
1120                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1121                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1122                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1123                 sds_mbx.sds_ring_size = sds->num_desc;
1124                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1125                         intrpt_id = ahw->intr_tbl[i].id;
1126                 else
1127                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1128                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1129                         sds_mbx.intrpt_id = intrpt_id;
1130                 else
1131                         sds_mbx.intrpt_id = 0xffff;
1132                 sds_mbx.intrpt_val = 0;
1133                 buf = &cmd.req.arg[index];
1134                 memcpy(buf, &sds_mbx, sds_mbx_size);
1135                 index += sds_mbx_size / sizeof(u32);
1136         }
1137         /* set up receive rings, mbx 88-111/135 */
1138         index = QLCNIC_HOST_RDS_MBX_IDX;
1139         rds = &recv_ctx->rds_rings[0];
1140         rds->producer = 0;
1141         memset(&rds_mbx, 0, rds_mbx_size);
1142         rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1143         rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1144         rds_mbx.reg_ring_sz = rds->dma_size;
1145         rds_mbx.reg_ring_len = rds->num_desc;
1146         /* Jumbo ring */
1147         rds = &recv_ctx->rds_rings[1];
1148         rds->producer = 0;
1149         rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1150         rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1151         rds_mbx.jmb_ring_sz = rds->dma_size;
1152         rds_mbx.jmb_ring_len = rds->num_desc;
1153         buf = &cmd.req.arg[index];
1154         memcpy(buf, &rds_mbx, rds_mbx_size);
1155
1156         /* send the mailbox command */
1157         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1158         if (err) {
1159                 dev_err(&adapter->pdev->dev,
1160                         "Failed to create Rx ctx in firmware%d\n", err);
1161                 goto out;
1162         }
1163         mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1164         recv_ctx->context_id = mbx_out->ctx_id;
1165         recv_ctx->state = mbx_out->state;
1166         recv_ctx->virt_port = mbx_out->vport_id;
1167         dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1168                  recv_ctx->context_id, recv_ctx->state);
1169         /* Receive descriptor ring */
1170         /* Standard ring */
1171         rds = &recv_ctx->rds_rings[0];
1172         rds->crb_rcv_producer = ahw->pci_base0 +
1173                                 mbx_out->host_prod[0].reg_buf;
1174         /* Jumbo ring */
1175         rds = &recv_ctx->rds_rings[1];
1176         rds->crb_rcv_producer = ahw->pci_base0 +
1177                                 mbx_out->host_prod[0].jmb_buf;
1178         /* status descriptor ring */
1179         for (i = 0; i < num_sds; i++) {
1180                 sds = &recv_ctx->sds_rings[i];
1181                 sds->crb_sts_consumer = ahw->pci_base0 +
1182                                         mbx_out->host_csmr[i];
1183                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1184                         intr_mask = ahw->intr_tbl[i].src;
1185                 else
1186                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1187                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1188         }
1189
1190         if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1191                 err = qlcnic_83xx_add_rings(adapter);
1192 out:
1193         qlcnic_free_mbx_args(&cmd);
1194         return err;
1195 }
1196
1197 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1198                             struct qlcnic_host_tx_ring *tx_ring)
1199 {
1200         struct qlcnic_cmd_args cmd;
1201         u32 temp = 0;
1202
1203         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1204                 return;
1205
1206         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1207                 cmd.req.arg[0] |= (0x3 << 29);
1208
1209         if (qlcnic_sriov_pf_check(adapter))
1210                 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1211
1212         cmd.req.arg[1] = tx_ring->ctx_id | temp;
1213         if (qlcnic_issue_cmd(adapter, &cmd))
1214                 dev_err(&adapter->pdev->dev,
1215                         "Failed to destroy tx ctx in firmware\n");
1216         qlcnic_free_mbx_args(&cmd);
1217 }
1218
1219 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1220                               struct qlcnic_host_tx_ring *tx, int ring)
1221 {
1222         int err;
1223         u16 msix_id;
1224         u32 *buf, intr_mask, temp = 0;
1225         struct qlcnic_cmd_args cmd;
1226         struct qlcnic_tx_mbx mbx;
1227         struct qlcnic_tx_mbx_out *mbx_out;
1228         struct qlcnic_hardware_context *ahw = adapter->ahw;
1229         u32 msix_vector;
1230
1231         /* Reset host resources */
1232         tx->producer = 0;
1233         tx->sw_consumer = 0;
1234         *(tx->hw_consumer) = 0;
1235
1236         memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1237
1238         /* setup mailbox inbox registerss */
1239         mbx.phys_addr_low = LSD(tx->phys_addr);
1240         mbx.phys_addr_high = MSD(tx->phys_addr);
1241         mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1242         mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1243         mbx.size = tx->num_desc;
1244         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1245                 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1246                         msix_vector = adapter->drv_sds_rings + ring;
1247                 else
1248                         msix_vector = adapter->drv_sds_rings - 1;
1249                 msix_id = ahw->intr_tbl[msix_vector].id;
1250         } else {
1251                 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1252         }
1253
1254         if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1255                 mbx.intr_id = msix_id;
1256         else
1257                 mbx.intr_id = 0xffff;
1258         mbx.src = 0;
1259
1260         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1261         if (err)
1262                 return err;
1263
1264         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1265                 cmd.req.arg[0] |= (0x3 << 29);
1266
1267         if (qlcnic_sriov_pf_check(adapter))
1268                 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1269
1270         cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1271         cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1272
1273         buf = &cmd.req.arg[6];
1274         memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1275         /* send the mailbox command*/
1276         err = qlcnic_issue_cmd(adapter, &cmd);
1277         if (err) {
1278                 dev_err(&adapter->pdev->dev,
1279                         "Failed to create Tx ctx in firmware 0x%x\n", err);
1280                 goto out;
1281         }
1282         mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1283         tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1284         tx->ctx_id = mbx_out->ctx_id;
1285         if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1286             !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1287                 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1288                 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1289         }
1290         dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1291                  tx->ctx_id, mbx_out->state);
1292 out:
1293         qlcnic_free_mbx_args(&cmd);
1294         return err;
1295 }
1296
1297 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1298                                       u8 num_sds_ring)
1299 {
1300         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1301         struct qlcnic_host_sds_ring *sds_ring;
1302         struct qlcnic_host_rds_ring *rds_ring;
1303         u16 adapter_state = adapter->is_up;
1304         u8 ring;
1305         int ret;
1306
1307         netif_device_detach(netdev);
1308
1309         if (netif_running(netdev))
1310                 __qlcnic_down(adapter, netdev);
1311
1312         qlcnic_detach(adapter);
1313
1314         adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1315         adapter->ahw->diag_test = test;
1316         adapter->ahw->linkup = 0;
1317
1318         ret = qlcnic_attach(adapter);
1319         if (ret) {
1320                 netif_device_attach(netdev);
1321                 return ret;
1322         }
1323
1324         ret = qlcnic_fw_create_ctx(adapter);
1325         if (ret) {
1326                 qlcnic_detach(adapter);
1327                 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1328                         adapter->drv_sds_rings = num_sds_ring;
1329                         qlcnic_attach(adapter);
1330                 }
1331                 netif_device_attach(netdev);
1332                 return ret;
1333         }
1334
1335         for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1336                 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1337                 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1338         }
1339
1340         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1341                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1342                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1343                         qlcnic_83xx_enable_intr(adapter, sds_ring);
1344                 }
1345         }
1346
1347         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1348                 /* disable and free mailbox interrupt */
1349                 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1350                         qlcnic_83xx_enable_mbx_poll(adapter);
1351                         qlcnic_83xx_free_mbx_intr(adapter);
1352                 }
1353                 adapter->ahw->loopback_state = 0;
1354                 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1355         }
1356
1357         set_bit(__QLCNIC_DEV_UP, &adapter->state);
1358         return 0;
1359 }
1360
1361 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1362                                       u8 drv_sds_rings)
1363 {
1364         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1365         struct qlcnic_host_sds_ring *sds_ring;
1366         int ring, err;
1367
1368         clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1369         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1370                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1371                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1372                         qlcnic_83xx_disable_intr(adapter, sds_ring);
1373                         if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1374                                 qlcnic_83xx_enable_mbx_poll(adapter);
1375                 }
1376         }
1377
1378         qlcnic_fw_destroy_ctx(adapter);
1379         qlcnic_detach(adapter);
1380
1381         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1382                 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1383                         err = qlcnic_83xx_setup_mbx_intr(adapter);
1384                         qlcnic_83xx_disable_mbx_poll(adapter);
1385                         if (err) {
1386                                 dev_err(&adapter->pdev->dev,
1387                                         "%s: failed to setup mbx interrupt\n",
1388                                         __func__);
1389                                 goto out;
1390                         }
1391                 }
1392         }
1393         adapter->ahw->diag_test = 0;
1394         adapter->drv_sds_rings = drv_sds_rings;
1395
1396         if (qlcnic_attach(adapter))
1397                 goto out;
1398
1399         if (netif_running(netdev))
1400                 __qlcnic_up(adapter, netdev);
1401
1402         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST &&
1403             !(adapter->flags & QLCNIC_MSIX_ENABLED))
1404                 qlcnic_83xx_disable_mbx_poll(adapter);
1405 out:
1406         netif_device_attach(netdev);
1407 }
1408
1409 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1410                            u32 beacon)
1411 {
1412         struct qlcnic_cmd_args cmd;
1413         u32 mbx_in;
1414         int i, status = 0;
1415
1416         if (state) {
1417                 /* Get LED configuration */
1418                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1419                                                QLCNIC_CMD_GET_LED_CONFIG);
1420                 if (status)
1421                         return status;
1422
1423                 status = qlcnic_issue_cmd(adapter, &cmd);
1424                 if (status) {
1425                         dev_err(&adapter->pdev->dev,
1426                                 "Get led config failed.\n");
1427                         goto mbx_err;
1428                 } else {
1429                         for (i = 0; i < 4; i++)
1430                                 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1431                 }
1432                 qlcnic_free_mbx_args(&cmd);
1433                 /* Set LED Configuration */
1434                 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1435                           LSW(QLC_83XX_LED_CONFIG);
1436                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1437                                                QLCNIC_CMD_SET_LED_CONFIG);
1438                 if (status)
1439                         return status;
1440
1441                 cmd.req.arg[1] = mbx_in;
1442                 cmd.req.arg[2] = mbx_in;
1443                 cmd.req.arg[3] = mbx_in;
1444                 if (beacon)
1445                         cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1446                 status = qlcnic_issue_cmd(adapter, &cmd);
1447                 if (status) {
1448                         dev_err(&adapter->pdev->dev,
1449                                 "Set led config failed.\n");
1450                 }
1451 mbx_err:
1452                 qlcnic_free_mbx_args(&cmd);
1453                 return status;
1454
1455         } else {
1456                 /* Restoring default LED configuration */
1457                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1458                                                QLCNIC_CMD_SET_LED_CONFIG);
1459                 if (status)
1460                         return status;
1461
1462                 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1463                 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1464                 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1465                 if (beacon)
1466                         cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1467                 status = qlcnic_issue_cmd(adapter, &cmd);
1468                 if (status)
1469                         dev_err(&adapter->pdev->dev,
1470                                 "Restoring led config failed.\n");
1471                 qlcnic_free_mbx_args(&cmd);
1472                 return status;
1473         }
1474 }
1475
1476 int  qlcnic_83xx_set_led(struct net_device *netdev,
1477                          enum ethtool_phys_id_state state)
1478 {
1479         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1480         int err = -EIO, active = 1;
1481
1482         if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1483                 netdev_warn(netdev,
1484                             "LED test is not supported in non-privileged mode\n");
1485                 return -EOPNOTSUPP;
1486         }
1487
1488         switch (state) {
1489         case ETHTOOL_ID_ACTIVE:
1490                 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1491                         return -EBUSY;
1492
1493                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1494                         break;
1495
1496                 err = qlcnic_83xx_config_led(adapter, active, 0);
1497                 if (err)
1498                         netdev_err(netdev, "Failed to set LED blink state\n");
1499                 break;
1500         case ETHTOOL_ID_INACTIVE:
1501                 active = 0;
1502
1503                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1504                         break;
1505
1506                 err = qlcnic_83xx_config_led(adapter, active, 0);
1507                 if (err)
1508                         netdev_err(netdev, "Failed to reset LED blink state\n");
1509                 break;
1510
1511         default:
1512                 return -EINVAL;
1513         }
1514
1515         if (!active || err)
1516                 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1517
1518         return err;
1519 }
1520
1521 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter,
1522                                        int enable)
1523 {
1524         struct qlcnic_cmd_args cmd;
1525         int status;
1526
1527         if (qlcnic_sriov_vf_check(adapter))
1528                 return;
1529
1530         if (enable) {
1531                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1532                                                QLCNIC_CMD_INIT_NIC_FUNC);
1533                 if (status)
1534                         return;
1535
1536                 cmd.req.arg[1] = BIT_0 | BIT_31;
1537         } else {
1538                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1539                                                QLCNIC_CMD_STOP_NIC_FUNC);
1540                 if (status)
1541                         return;
1542
1543                 cmd.req.arg[1] = BIT_0 | BIT_31;
1544         }
1545
1546         if (adapter->dcb)
1547                 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1548
1549         status = qlcnic_issue_cmd(adapter, &cmd);
1550         if (status)
1551                 dev_err(&adapter->pdev->dev,
1552                         "Failed to %s in NIC IDC function event.\n",
1553                         (enable ? "register" : "unregister"));
1554
1555         qlcnic_free_mbx_args(&cmd);
1556 }
1557
1558 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1559 {
1560         struct qlcnic_cmd_args cmd;
1561         int err;
1562
1563         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1564         if (err)
1565                 return err;
1566
1567         cmd.req.arg[1] = adapter->ahw->port_config;
1568         err = qlcnic_issue_cmd(adapter, &cmd);
1569         if (err)
1570                 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1571         qlcnic_free_mbx_args(&cmd);
1572         return err;
1573 }
1574
1575 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1576 {
1577         struct qlcnic_cmd_args cmd;
1578         int err;
1579
1580         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1581         if (err)
1582                 return err;
1583
1584         err = qlcnic_issue_cmd(adapter, &cmd);
1585         if (err)
1586                 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1587         else
1588                 adapter->ahw->port_config = cmd.rsp.arg[1];
1589         qlcnic_free_mbx_args(&cmd);
1590         return err;
1591 }
1592
1593 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1594 {
1595         int err;
1596         u32 temp;
1597         struct qlcnic_cmd_args cmd;
1598
1599         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1600         if (err)
1601                 return err;
1602
1603         temp = adapter->recv_ctx->context_id << 16;
1604         cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1605         err = qlcnic_issue_cmd(adapter, &cmd);
1606         if (err)
1607                 dev_info(&adapter->pdev->dev,
1608                          "Setup linkevent mailbox failed\n");
1609         qlcnic_free_mbx_args(&cmd);
1610         return err;
1611 }
1612
1613 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1614                                                  u32 *interface_id)
1615 {
1616         if (qlcnic_sriov_pf_check(adapter)) {
1617                 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1618         } else {
1619                 if (!qlcnic_sriov_vf_check(adapter))
1620                         *interface_id = adapter->recv_ctx->context_id << 16;
1621         }
1622 }
1623
1624 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1625 {
1626         struct qlcnic_cmd_args *cmd = NULL;
1627         u32 temp = 0;
1628         int err;
1629
1630         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1631                 return -EIO;
1632
1633         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1634         if (!cmd)
1635                 return -ENOMEM;
1636
1637         err = qlcnic_alloc_mbx_args(cmd, adapter,
1638                                     QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1639         if (err)
1640                 goto out;
1641
1642         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1643         qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1644         cmd->req.arg[1] = (mode ? 1 : 0) | temp;
1645         err = qlcnic_issue_cmd(adapter, cmd);
1646         if (!err)
1647                 return err;
1648
1649         qlcnic_free_mbx_args(cmd);
1650
1651 out:
1652         kfree(cmd);
1653         return err;
1654 }
1655
1656 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1657 {
1658         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1659         struct qlcnic_hardware_context *ahw = adapter->ahw;
1660         u8 drv_sds_rings = adapter->drv_sds_rings;
1661         u8 drv_tx_rings = adapter->drv_tx_rings;
1662         int ret = 0, loop = 0;
1663
1664         if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1665                 netdev_warn(netdev,
1666                             "Loopback test not supported in non privileged mode\n");
1667                 return -ENOTSUPP;
1668         }
1669
1670         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1671                 netdev_info(netdev, "Device is resetting\n");
1672                 return -EBUSY;
1673         }
1674
1675         if (qlcnic_get_diag_lock(adapter)) {
1676                 netdev_info(netdev, "Device is in diagnostics mode\n");
1677                 return -EBUSY;
1678         }
1679
1680         netdev_info(netdev, "%s loopback test in progress\n",
1681                     mode == QLCNIC_ILB_MODE ? "internal" : "external");
1682
1683         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1684                                          drv_sds_rings);
1685         if (ret)
1686                 goto fail_diag_alloc;
1687
1688         ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1689         if (ret)
1690                 goto free_diag_res;
1691
1692         /* Poll for link up event before running traffic */
1693         do {
1694                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1695
1696                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1697                         netdev_info(netdev,
1698                                     "Device is resetting, free LB test resources\n");
1699                         ret = -EBUSY;
1700                         goto free_diag_res;
1701                 }
1702                 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1703                         netdev_info(netdev,
1704                                     "Firmware didn't sent link up event to loopback request\n");
1705                         ret = -ETIMEDOUT;
1706                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1707                         goto free_diag_res;
1708                 }
1709         } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1710
1711         /* Make sure carrier is off and queue is stopped during loopback */
1712         if (netif_running(netdev)) {
1713                 netif_carrier_off(netdev);
1714                 netif_tx_stop_all_queues(netdev);
1715         }
1716
1717         ret = qlcnic_do_lb_test(adapter, mode);
1718
1719         qlcnic_83xx_clear_lb_mode(adapter, mode);
1720
1721 free_diag_res:
1722         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1723
1724 fail_diag_alloc:
1725         adapter->drv_sds_rings = drv_sds_rings;
1726         adapter->drv_tx_rings = drv_tx_rings;
1727         qlcnic_release_diag_lock(adapter);
1728         return ret;
1729 }
1730
1731 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1732                                              u32 *max_wait_count)
1733 {
1734         struct qlcnic_hardware_context *ahw = adapter->ahw;
1735         int temp;
1736
1737         netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1738                     ahw->extend_lb_time);
1739         temp = ahw->extend_lb_time * 1000;
1740         *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1741         ahw->extend_lb_time = 0;
1742 }
1743
1744 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1745 {
1746         struct qlcnic_hardware_context *ahw = adapter->ahw;
1747         struct net_device *netdev = adapter->netdev;
1748         u32 config, max_wait_count;
1749         int status = 0, loop = 0;
1750
1751         ahw->extend_lb_time = 0;
1752         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1753         status = qlcnic_83xx_get_port_config(adapter);
1754         if (status)
1755                 return status;
1756
1757         config = ahw->port_config;
1758
1759         /* Check if port is already in loopback mode */
1760         if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1761             (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1762                 netdev_err(netdev,
1763                            "Port already in Loopback mode.\n");
1764                 return -EINPROGRESS;
1765         }
1766
1767         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1768
1769         if (mode == QLCNIC_ILB_MODE)
1770                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1771         if (mode == QLCNIC_ELB_MODE)
1772                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1773
1774         status = qlcnic_83xx_set_port_config(adapter);
1775         if (status) {
1776                 netdev_err(netdev,
1777                            "Failed to Set Loopback Mode = 0x%x.\n",
1778                            ahw->port_config);
1779                 ahw->port_config = config;
1780                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1781                 return status;
1782         }
1783
1784         /* Wait for Link and IDC Completion AEN */
1785         do {
1786                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1787
1788                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1789                         netdev_info(netdev,
1790                                     "Device is resetting, free LB test resources\n");
1791                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1792                         return -EBUSY;
1793                 }
1794
1795                 if (ahw->extend_lb_time)
1796                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1797                                                          &max_wait_count);
1798
1799                 if (loop++ > max_wait_count) {
1800                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1801                                    __func__);
1802                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1803                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1804                         return -ETIMEDOUT;
1805                 }
1806         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1807
1808         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1809                                   QLCNIC_MAC_ADD);
1810         return status;
1811 }
1812
1813 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1814 {
1815         struct qlcnic_hardware_context *ahw = adapter->ahw;
1816         u32 config = ahw->port_config, max_wait_count;
1817         struct net_device *netdev = adapter->netdev;
1818         int status = 0, loop = 0;
1819
1820         ahw->extend_lb_time = 0;
1821         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1822         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1823         if (mode == QLCNIC_ILB_MODE)
1824                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1825         if (mode == QLCNIC_ELB_MODE)
1826                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1827
1828         status = qlcnic_83xx_set_port_config(adapter);
1829         if (status) {
1830                 netdev_err(netdev,
1831                            "Failed to Clear Loopback Mode = 0x%x.\n",
1832                            ahw->port_config);
1833                 ahw->port_config = config;
1834                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1835                 return status;
1836         }
1837
1838         /* Wait for Link and IDC Completion AEN */
1839         do {
1840                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1841
1842                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1843                         netdev_info(netdev,
1844                                     "Device is resetting, free LB test resources\n");
1845                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1846                         return -EBUSY;
1847                 }
1848
1849                 if (ahw->extend_lb_time)
1850                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1851                                                          &max_wait_count);
1852
1853                 if (loop++ > max_wait_count) {
1854                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1855                                    __func__);
1856                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1857                         return -ETIMEDOUT;
1858                 }
1859         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1860
1861         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1862                                   QLCNIC_MAC_DEL);
1863         return status;
1864 }
1865
1866 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1867                                                 u32 *interface_id)
1868 {
1869         if (qlcnic_sriov_pf_check(adapter)) {
1870                 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1871         } else {
1872                 if (!qlcnic_sriov_vf_check(adapter))
1873                         *interface_id = adapter->recv_ctx->context_id << 16;
1874         }
1875 }
1876
1877 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1878                                int mode)
1879 {
1880         int err;
1881         u32 temp = 0, temp_ip;
1882         struct qlcnic_cmd_args cmd;
1883
1884         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1885                                     QLCNIC_CMD_CONFIGURE_IP_ADDR);
1886         if (err)
1887                 return;
1888
1889         qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1890
1891         if (mode == QLCNIC_IP_UP)
1892                 cmd.req.arg[1] = 1 | temp;
1893         else
1894                 cmd.req.arg[1] = 2 | temp;
1895
1896         /*
1897          * Adapter needs IP address in network byte order.
1898          * But hardware mailbox registers go through writel(), hence IP address
1899          * gets swapped on big endian architecture.
1900          * To negate swapping of writel() on big endian architecture
1901          * use swab32(value).
1902          */
1903
1904         temp_ip = swab32(ntohl(ip));
1905         memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1906         err = qlcnic_issue_cmd(adapter, &cmd);
1907         if (err != QLCNIC_RCODE_SUCCESS)
1908                 dev_err(&adapter->netdev->dev,
1909                         "could not notify %s IP 0x%x request\n",
1910                         (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1911
1912         qlcnic_free_mbx_args(&cmd);
1913 }
1914
1915 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1916 {
1917         int err;
1918         u32 temp, arg1;
1919         struct qlcnic_cmd_args cmd;
1920         int lro_bit_mask;
1921
1922         lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1923
1924         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1925                 return 0;
1926
1927         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1928         if (err)
1929                 return err;
1930
1931         temp = adapter->recv_ctx->context_id << 16;
1932         arg1 = lro_bit_mask | temp;
1933         cmd.req.arg[1] = arg1;
1934
1935         err = qlcnic_issue_cmd(adapter, &cmd);
1936         if (err)
1937                 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1938         qlcnic_free_mbx_args(&cmd);
1939
1940         return err;
1941 }
1942
1943 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1944 {
1945         int err;
1946         u32 word;
1947         struct qlcnic_cmd_args cmd;
1948         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1949                             0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1950                             0x255b0ec26d5a56daULL };
1951
1952         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1953         if (err)
1954                 return err;
1955         /*
1956          * RSS request:
1957          * bits 3-0: Rsvd
1958          *      5-4: hash_type_ipv4
1959          *      7-6: hash_type_ipv6
1960          *        8: enable
1961          *        9: use indirection table
1962          *    16-31: indirection table mask
1963          */
1964         word =  ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1965                 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1966                 ((u32)(enable & 0x1) << 8) |
1967                 ((0x7ULL) << 16);
1968         cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1969         cmd.req.arg[2] = word;
1970         memcpy(&cmd.req.arg[4], key, sizeof(key));
1971
1972         err = qlcnic_issue_cmd(adapter, &cmd);
1973
1974         if (err)
1975                 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1976         qlcnic_free_mbx_args(&cmd);
1977
1978         return err;
1979
1980 }
1981
1982 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1983                                                  u32 *interface_id)
1984 {
1985         if (qlcnic_sriov_pf_check(adapter)) {
1986                 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1987         } else {
1988                 if (!qlcnic_sriov_vf_check(adapter))
1989                         *interface_id = adapter->recv_ctx->context_id << 16;
1990         }
1991 }
1992
1993 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1994                                    u16 vlan_id, u8 op)
1995 {
1996         struct qlcnic_cmd_args *cmd = NULL;
1997         struct qlcnic_macvlan_mbx mv;
1998         u32 *buf, temp = 0;
1999         int err;
2000
2001         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2002                 return -EIO;
2003
2004         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
2005         if (!cmd)
2006                 return -ENOMEM;
2007
2008         err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
2009         if (err)
2010                 goto out;
2011
2012         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
2013
2014         if (vlan_id)
2015                 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2016                      QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2017
2018         cmd->req.arg[1] = op | (1 << 8);
2019         qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
2020         cmd->req.arg[1] |= temp;
2021         mv.vlan = vlan_id;
2022         mv.mac_addr0 = addr[0];
2023         mv.mac_addr1 = addr[1];
2024         mv.mac_addr2 = addr[2];
2025         mv.mac_addr3 = addr[3];
2026         mv.mac_addr4 = addr[4];
2027         mv.mac_addr5 = addr[5];
2028         buf = &cmd->req.arg[2];
2029         memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2030         err = qlcnic_issue_cmd(adapter, cmd);
2031         if (!err)
2032                 return err;
2033
2034         qlcnic_free_mbx_args(cmd);
2035 out:
2036         kfree(cmd);
2037         return err;
2038 }
2039
2040 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2041                                   u16 vlan_id)
2042 {
2043         u8 mac[ETH_ALEN];
2044         memcpy(&mac, addr, ETH_ALEN);
2045         qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2046 }
2047
2048 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2049                                u8 type, struct qlcnic_cmd_args *cmd)
2050 {
2051         switch (type) {
2052         case QLCNIC_SET_STATION_MAC:
2053         case QLCNIC_SET_FAC_DEF_MAC:
2054                 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2055                 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2056                 break;
2057         }
2058         cmd->req.arg[1] = type;
2059 }
2060
2061 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2062                                 u8 function)
2063 {
2064         int err, i;
2065         struct qlcnic_cmd_args cmd;
2066         u32 mac_low, mac_high;
2067
2068         function = 0;
2069         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2070         if (err)
2071                 return err;
2072
2073         qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2074         err = qlcnic_issue_cmd(adapter, &cmd);
2075
2076         if (err == QLCNIC_RCODE_SUCCESS) {
2077                 mac_low = cmd.rsp.arg[1];
2078                 mac_high = cmd.rsp.arg[2];
2079
2080                 for (i = 0; i < 2; i++)
2081                         mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2082                 for (i = 2; i < 6; i++)
2083                         mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2084         } else {
2085                 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2086                         err);
2087                 err = -EIO;
2088         }
2089         qlcnic_free_mbx_args(&cmd);
2090         return err;
2091 }
2092
2093 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2094 {
2095         int err;
2096         u16 temp;
2097         struct qlcnic_cmd_args cmd;
2098         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2099
2100         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2101                 return;
2102
2103         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2104         if (err)
2105                 return;
2106
2107         if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2108                 temp = adapter->recv_ctx->context_id;
2109                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2110                 temp = coal->rx_time_us;
2111                 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2112         } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2113                 temp = adapter->tx_ring->ctx_id;
2114                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2115                 temp = coal->tx_time_us;
2116                 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2117         }
2118         cmd.req.arg[3] = coal->flag;
2119         err = qlcnic_issue_cmd(adapter, &cmd);
2120         if (err != QLCNIC_RCODE_SUCCESS)
2121                 dev_info(&adapter->pdev->dev,
2122                          "Failed to send interrupt coalescence parameters\n");
2123         qlcnic_free_mbx_args(&cmd);
2124 }
2125
2126 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2127                                         u32 data[])
2128 {
2129         struct qlcnic_hardware_context *ahw = adapter->ahw;
2130         u8 link_status, duplex;
2131         /* link speed */
2132         link_status = LSB(data[3]) & 1;
2133         if (link_status) {
2134                 ahw->link_speed = MSW(data[2]);
2135                 duplex = LSB(MSW(data[3]));
2136                 if (duplex)
2137                         ahw->link_duplex = DUPLEX_FULL;
2138                 else
2139                         ahw->link_duplex = DUPLEX_HALF;
2140         } else {
2141                 ahw->link_speed = SPEED_UNKNOWN;
2142                 ahw->link_duplex = DUPLEX_UNKNOWN;
2143         }
2144
2145         ahw->link_autoneg = MSB(MSW(data[3]));
2146         ahw->module_type = MSB(LSW(data[3]));
2147         ahw->has_link_events = 1;
2148         qlcnic_advert_link_change(adapter, link_status);
2149 }
2150
2151 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2152 {
2153         struct qlcnic_adapter *adapter = data;
2154         struct qlcnic_mailbox *mbx;
2155         u32 mask, resp, event;
2156         unsigned long flags;
2157
2158         mbx = adapter->ahw->mailbox;
2159         spin_lock_irqsave(&mbx->aen_lock, flags);
2160         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2161         if (!(resp & QLCNIC_SET_OWNER))
2162                 goto out;
2163
2164         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2165         if (event &  QLCNIC_MBX_ASYNC_EVENT)
2166                 __qlcnic_83xx_process_aen(adapter);
2167         else
2168                 qlcnic_83xx_notify_mbx_response(mbx);
2169
2170 out:
2171         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2172         writel(0, adapter->ahw->pci_base0 + mask);
2173         spin_unlock_irqrestore(&mbx->aen_lock, flags);
2174         return IRQ_HANDLED;
2175 }
2176
2177 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
2178 {
2179         int err = -EIO;
2180         struct qlcnic_cmd_args cmd;
2181
2182         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2183                 dev_err(&adapter->pdev->dev,
2184                         "%s: Error, invoked by non management func\n",
2185                         __func__);
2186                 return err;
2187         }
2188
2189         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
2190         if (err)
2191                 return err;
2192
2193         cmd.req.arg[1] = (port & 0xf) | BIT_4;
2194         err = qlcnic_issue_cmd(adapter, &cmd);
2195
2196         if (err != QLCNIC_RCODE_SUCCESS) {
2197                 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
2198                         err);
2199                 err = -EIO;
2200         }
2201         qlcnic_free_mbx_args(&cmd);
2202
2203         return err;
2204
2205 }
2206
2207 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2208                              struct qlcnic_info *nic)
2209 {
2210         int i, err = -EIO;
2211         struct qlcnic_cmd_args cmd;
2212
2213         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2214                 dev_err(&adapter->pdev->dev,
2215                         "%s: Error, invoked by non management func\n",
2216                         __func__);
2217                 return err;
2218         }
2219
2220         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2221         if (err)
2222                 return err;
2223
2224         cmd.req.arg[1] = (nic->pci_func << 16);
2225         cmd.req.arg[2] = 0x1 << 16;
2226         cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2227         cmd.req.arg[4] = nic->capabilities;
2228         cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2229         cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2230         cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2231         for (i = 8; i < 32; i++)
2232                 cmd.req.arg[i] = 0;
2233
2234         err = qlcnic_issue_cmd(adapter, &cmd);
2235
2236         if (err != QLCNIC_RCODE_SUCCESS) {
2237                 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2238                         err);
2239                 err = -EIO;
2240         }
2241
2242         qlcnic_free_mbx_args(&cmd);
2243
2244         return err;
2245 }
2246
2247 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2248                              struct qlcnic_info *npar_info, u8 func_id)
2249 {
2250         int err;
2251         u32 temp;
2252         u8 op = 0;
2253         struct qlcnic_cmd_args cmd;
2254         struct qlcnic_hardware_context *ahw = adapter->ahw;
2255
2256         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2257         if (err)
2258                 return err;
2259
2260         if (func_id != ahw->pci_func) {
2261                 temp = func_id << 16;
2262                 cmd.req.arg[1] = op | BIT_31 | temp;
2263         } else {
2264                 cmd.req.arg[1] = ahw->pci_func << 16;
2265         }
2266         err = qlcnic_issue_cmd(adapter, &cmd);
2267         if (err) {
2268                 dev_info(&adapter->pdev->dev,
2269                          "Failed to get nic info %d\n", err);
2270                 goto out;
2271         }
2272
2273         npar_info->op_type = cmd.rsp.arg[1];
2274         npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2275         npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2276         npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2277         npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2278         npar_info->capabilities = cmd.rsp.arg[4];
2279         npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2280         npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2281         npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2282         npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2283         npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2284         npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2285         if (cmd.rsp.arg[8] & 0x1)
2286                 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2287         if (cmd.rsp.arg[8] & 0x10000) {
2288                 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2289                 npar_info->max_linkspeed_reg_offset = temp;
2290         }
2291
2292         memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2293                sizeof(ahw->extra_capability));
2294
2295 out:
2296         qlcnic_free_mbx_args(&cmd);
2297         return err;
2298 }
2299
2300 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2301                              struct qlcnic_pci_info *pci_info)
2302 {
2303         struct qlcnic_hardware_context *ahw = adapter->ahw;
2304         struct device *dev = &adapter->pdev->dev;
2305         struct qlcnic_cmd_args cmd;
2306         int i, err = 0, j = 0;
2307         u32 temp;
2308
2309         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2310         if (err)
2311                 return err;
2312
2313         err = qlcnic_issue_cmd(adapter, &cmd);
2314
2315         ahw->act_pci_func = 0;
2316         if (err == QLCNIC_RCODE_SUCCESS) {
2317                 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2318                 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) {
2319                         pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2320                         pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2321                         i++;
2322                         pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2323                         if (pci_info->type == QLCNIC_TYPE_NIC)
2324                                 ahw->act_pci_func++;
2325                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2326                         pci_info->default_port = temp;
2327                         i++;
2328                         pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2329                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2330                         pci_info->tx_max_bw = temp;
2331                         i = i + 2;
2332                         memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2333                         i++;
2334                         memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2335                         i = i + 3;
2336                 }
2337         } else {
2338                 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2339                 err = -EIO;
2340         }
2341
2342         qlcnic_free_mbx_args(&cmd);
2343
2344         return err;
2345 }
2346
2347 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2348 {
2349         int i, index, err;
2350         u8 max_ints;
2351         u32 val, temp, type;
2352         struct qlcnic_cmd_args cmd;
2353
2354         max_ints = adapter->ahw->num_msix - 1;
2355         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2356         if (err)
2357                 return err;
2358
2359         cmd.req.arg[1] = max_ints;
2360
2361         if (qlcnic_sriov_vf_check(adapter))
2362                 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2363
2364         for (i = 0, index = 2; i < max_ints; i++) {
2365                 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2366                 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2367                 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2368                         val |= (adapter->ahw->intr_tbl[i].id << 16);
2369                 cmd.req.arg[index++] = val;
2370         }
2371         err = qlcnic_issue_cmd(adapter, &cmd);
2372         if (err) {
2373                 dev_err(&adapter->pdev->dev,
2374                         "Failed to configure interrupts 0x%x\n", err);
2375                 goto out;
2376         }
2377
2378         max_ints = cmd.rsp.arg[1];
2379         for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2380                 val = cmd.rsp.arg[index];
2381                 if (LSB(val)) {
2382                         dev_info(&adapter->pdev->dev,
2383                                  "Can't configure interrupt %d\n",
2384                                  adapter->ahw->intr_tbl[i].id);
2385                         continue;
2386                 }
2387                 if (op_type) {
2388                         adapter->ahw->intr_tbl[i].id = MSW(val);
2389                         adapter->ahw->intr_tbl[i].enabled = 1;
2390                         temp = cmd.rsp.arg[index + 1];
2391                         adapter->ahw->intr_tbl[i].src = temp;
2392                 } else {
2393                         adapter->ahw->intr_tbl[i].id = i;
2394                         adapter->ahw->intr_tbl[i].enabled = 0;
2395                         adapter->ahw->intr_tbl[i].src = 0;
2396                 }
2397         }
2398 out:
2399         qlcnic_free_mbx_args(&cmd);
2400         return err;
2401 }
2402
2403 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2404 {
2405         int id, timeout = 0;
2406         u32 status = 0;
2407
2408         while (status == 0) {
2409                 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2410                 if (status)
2411                         break;
2412
2413                 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2414                         id = QLC_SHARED_REG_RD32(adapter,
2415                                                  QLCNIC_FLASH_LOCK_OWNER);
2416                         dev_err(&adapter->pdev->dev,
2417                                 "%s: failed, lock held by %d\n", __func__, id);
2418                         return -EIO;
2419                 }
2420                 usleep_range(1000, 2000);
2421         }
2422
2423         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2424         return 0;
2425 }
2426
2427 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2428 {
2429         QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2430         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2431 }
2432
2433 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2434                                       u32 flash_addr, u8 *p_data,
2435                                       int count)
2436 {
2437         u32 word, range, flash_offset, addr = flash_addr, ret;
2438         ulong indirect_add, direct_window;
2439         int i, err = 0;
2440
2441         flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2442         if (addr & 0x3) {
2443                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2444                 return -EIO;
2445         }
2446
2447         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2448                                      (addr));
2449
2450         range = flash_offset + (count * sizeof(u32));
2451         /* Check if data is spread across multiple sectors */
2452         if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2453
2454                 /* Multi sector read */
2455                 for (i = 0; i < count; i++) {
2456                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2457                         ret = QLCRD32(adapter, indirect_add, &err);
2458                         if (err == -EIO)
2459                                 return err;
2460
2461                         word = ret;
2462                         *(u32 *)p_data  = word;
2463                         p_data = p_data + 4;
2464                         addr = addr + 4;
2465                         flash_offset = flash_offset + 4;
2466
2467                         if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2468                                 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2469                                 /* This write is needed once for each sector */
2470                                 qlcnic_83xx_wrt_reg_indirect(adapter,
2471                                                              direct_window,
2472                                                              (addr));
2473                                 flash_offset = 0;
2474                         }
2475                 }
2476         } else {
2477                 /* Single sector read */
2478                 for (i = 0; i < count; i++) {
2479                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2480                         ret = QLCRD32(adapter, indirect_add, &err);
2481                         if (err == -EIO)
2482                                 return err;
2483
2484                         word = ret;
2485                         *(u32 *)p_data  = word;
2486                         p_data = p_data + 4;
2487                         addr = addr + 4;
2488                 }
2489         }
2490
2491         return 0;
2492 }
2493
2494 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2495 {
2496         u32 status;
2497         int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2498         int err = 0;
2499
2500         do {
2501                 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2502                 if (err == -EIO)
2503                         return err;
2504
2505                 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2506                     QLC_83XX_FLASH_STATUS_READY)
2507                         break;
2508
2509                 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2510         } while (--retries);
2511
2512         if (!retries)
2513                 return -EIO;
2514
2515         return 0;
2516 }
2517
2518 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2519 {
2520         int ret;
2521         u32 cmd;
2522         cmd = adapter->ahw->fdt.write_statusreg_cmd;
2523         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2524                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2525         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2526                                      adapter->ahw->fdt.write_enable_bits);
2527         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2528                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2529         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2530         if (ret)
2531                 return -EIO;
2532
2533         return 0;
2534 }
2535
2536 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2537 {
2538         int ret;
2539
2540         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2541                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2542                                      adapter->ahw->fdt.write_statusreg_cmd));
2543         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2544                                      adapter->ahw->fdt.write_disable_bits);
2545         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2546                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2547         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2548         if (ret)
2549                 return -EIO;
2550
2551         return 0;
2552 }
2553
2554 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2555 {
2556         int ret, err = 0;
2557         u32 mfg_id;
2558
2559         if (qlcnic_83xx_lock_flash(adapter))
2560                 return -EIO;
2561
2562         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2563                                      QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2564         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2565                                      QLC_83XX_FLASH_READ_CTRL);
2566         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2567         if (ret) {
2568                 qlcnic_83xx_unlock_flash(adapter);
2569                 return -EIO;
2570         }
2571
2572         mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2573         if (err == -EIO) {
2574                 qlcnic_83xx_unlock_flash(adapter);
2575                 return err;
2576         }
2577
2578         adapter->flash_mfg_id = (mfg_id & 0xFF);
2579         qlcnic_83xx_unlock_flash(adapter);
2580
2581         return 0;
2582 }
2583
2584 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2585 {
2586         int count, fdt_size, ret = 0;
2587
2588         fdt_size = sizeof(struct qlcnic_fdt);
2589         count = fdt_size / sizeof(u32);
2590
2591         if (qlcnic_83xx_lock_flash(adapter))
2592                 return -EIO;
2593
2594         memset(&adapter->ahw->fdt, 0, fdt_size);
2595         ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2596                                                 (u8 *)&adapter->ahw->fdt,
2597                                                 count);
2598
2599         qlcnic_83xx_unlock_flash(adapter);
2600         return ret;
2601 }
2602
2603 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2604                                    u32 sector_start_addr)
2605 {
2606         u32 reversed_addr, addr1, addr2, cmd;
2607         int ret = -EIO;
2608
2609         if (qlcnic_83xx_lock_flash(adapter) != 0)
2610                 return -EIO;
2611
2612         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2613                 ret = qlcnic_83xx_enable_flash_write(adapter);
2614                 if (ret) {
2615                         qlcnic_83xx_unlock_flash(adapter);
2616                         dev_err(&adapter->pdev->dev,
2617                                 "%s failed at %d\n",
2618                                 __func__, __LINE__);
2619                         return ret;
2620                 }
2621         }
2622
2623         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2624         if (ret) {
2625                 qlcnic_83xx_unlock_flash(adapter);
2626                 dev_err(&adapter->pdev->dev,
2627                         "%s: failed at %d\n", __func__, __LINE__);
2628                 return -EIO;
2629         }
2630
2631         addr1 = (sector_start_addr & 0xFF) << 16;
2632         addr2 = (sector_start_addr & 0xFF0000) >> 16;
2633         reversed_addr = addr1 | addr2;
2634
2635         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2636                                      reversed_addr);
2637         cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2638         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2639                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2640         else
2641                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2642                                              QLC_83XX_FLASH_OEM_ERASE_SIG);
2643         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2644                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2645
2646         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2647         if (ret) {
2648                 qlcnic_83xx_unlock_flash(adapter);
2649                 dev_err(&adapter->pdev->dev,
2650                         "%s: failed at %d\n", __func__, __LINE__);
2651                 return -EIO;
2652         }
2653
2654         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2655                 ret = qlcnic_83xx_disable_flash_write(adapter);
2656                 if (ret) {
2657                         qlcnic_83xx_unlock_flash(adapter);
2658                         dev_err(&adapter->pdev->dev,
2659                                 "%s: failed at %d\n", __func__, __LINE__);
2660                         return ret;
2661                 }
2662         }
2663
2664         qlcnic_83xx_unlock_flash(adapter);
2665
2666         return 0;
2667 }
2668
2669 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2670                               u32 *p_data)
2671 {
2672         int ret = -EIO;
2673         u32 addr1 = 0x00800000 | (addr >> 2);
2674
2675         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2676         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2677         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2678                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2679         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2680         if (ret) {
2681                 dev_err(&adapter->pdev->dev,
2682                         "%s: failed at %d\n", __func__, __LINE__);
2683                 return -EIO;
2684         }
2685
2686         return 0;
2687 }
2688
2689 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2690                                  u32 *p_data, int count)
2691 {
2692         u32 temp;
2693         int ret = -EIO, err = 0;
2694
2695         if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2696             (count > QLC_83XX_FLASH_WRITE_MAX)) {
2697                 dev_err(&adapter->pdev->dev,
2698                         "%s: Invalid word count\n", __func__);
2699                 return -EIO;
2700         }
2701
2702         temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2703         if (err == -EIO)
2704                 return err;
2705
2706         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2707                                      (temp | QLC_83XX_FLASH_SPI_CTRL));
2708         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2709                                      QLC_83XX_FLASH_ADDR_TEMP_VAL);
2710
2711         /* First DWORD write */
2712         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2713         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2714                                      QLC_83XX_FLASH_FIRST_MS_PATTERN);
2715         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2716         if (ret) {
2717                 dev_err(&adapter->pdev->dev,
2718                         "%s: failed at %d\n", __func__, __LINE__);
2719                 return -EIO;
2720         }
2721
2722         count--;
2723         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2724                                      QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2725         /* Second to N-1 DWORD writes */
2726         while (count != 1) {
2727                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2728                                              *p_data++);
2729                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2730                                              QLC_83XX_FLASH_SECOND_MS_PATTERN);
2731                 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2732                 if (ret) {
2733                         dev_err(&adapter->pdev->dev,
2734                                 "%s: failed at %d\n", __func__, __LINE__);
2735                         return -EIO;
2736                 }
2737                 count--;
2738         }
2739
2740         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2741                                      QLC_83XX_FLASH_ADDR_TEMP_VAL |
2742                                      (addr >> 2));
2743         /* Last DWORD write */
2744         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2745         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2746                                      QLC_83XX_FLASH_LAST_MS_PATTERN);
2747         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2748         if (ret) {
2749                 dev_err(&adapter->pdev->dev,
2750                         "%s: failed at %d\n", __func__, __LINE__);
2751                 return -EIO;
2752         }
2753
2754         ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2755         if (err == -EIO)
2756                 return err;
2757
2758         if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2759                 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2760                         __func__, __LINE__);
2761                 /* Operation failed, clear error bit */
2762                 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2763                 if (err == -EIO)
2764                         return err;
2765
2766                 qlcnic_83xx_wrt_reg_indirect(adapter,
2767                                              QLC_83XX_FLASH_SPI_CONTROL,
2768                                              (temp | QLC_83XX_FLASH_SPI_CTRL));
2769         }
2770
2771         return 0;
2772 }
2773
2774 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2775 {
2776         u32 val, id;
2777
2778         val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2779
2780         /* Check if recovery need to be performed by the calling function */
2781         if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2782                 val = val & ~0x3F;
2783                 val = val | ((adapter->portnum << 2) |
2784                              QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2785                 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2786                 dev_info(&adapter->pdev->dev,
2787                          "%s: lock recovery initiated\n", __func__);
2788                 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2789                 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2790                 id = ((val >> 2) & 0xF);
2791                 if (id == adapter->portnum) {
2792                         val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2793                         val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2794                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2795                         /* Force release the lock */
2796                         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2797                         /* Clear recovery bits */
2798                         val = val & ~0x3F;
2799                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2800                         dev_info(&adapter->pdev->dev,
2801                                  "%s: lock recovery completed\n", __func__);
2802                 } else {
2803                         dev_info(&adapter->pdev->dev,
2804                                  "%s: func %d to resume lock recovery process\n",
2805                                  __func__, id);
2806                 }
2807         } else {
2808                 dev_info(&adapter->pdev->dev,
2809                          "%s: lock recovery initiated by other functions\n",
2810                          __func__);
2811         }
2812 }
2813
2814 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2815 {
2816         u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2817         int max_attempt = 0;
2818
2819         while (status == 0) {
2820                 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2821                 if (status)
2822                         break;
2823
2824                 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2825                 i++;
2826
2827                 if (i == 1)
2828                         temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2829
2830                 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2831                         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2832                         if (val == temp) {
2833                                 id = val & 0xFF;
2834                                 dev_info(&adapter->pdev->dev,
2835                                          "%s: lock to be recovered from %d\n",
2836                                          __func__, id);
2837                                 qlcnic_83xx_recover_driver_lock(adapter);
2838                                 i = 0;
2839                                 max_attempt++;
2840                         } else {
2841                                 dev_err(&adapter->pdev->dev,
2842                                         "%s: failed to get lock\n", __func__);
2843                                 return -EIO;
2844                         }
2845                 }
2846
2847                 /* Force exit from while loop after few attempts */
2848                 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2849                         dev_err(&adapter->pdev->dev,
2850                                 "%s: failed to get lock\n", __func__);
2851                         return -EIO;
2852                 }
2853         }
2854
2855         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2856         lock_alive_counter = val >> 8;
2857         lock_alive_counter++;
2858         val = lock_alive_counter << 8 | adapter->portnum;
2859         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2860
2861         return 0;
2862 }
2863
2864 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2865 {
2866         u32 val, lock_alive_counter, id;
2867
2868         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2869         id = val & 0xFF;
2870         lock_alive_counter = val >> 8;
2871
2872         if (id != adapter->portnum)
2873                 dev_err(&adapter->pdev->dev,
2874                         "%s:Warning func %d is unlocking lock owned by %d\n",
2875                         __func__, adapter->portnum, id);
2876
2877         val = (lock_alive_counter << 8) | 0xFF;
2878         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2879         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2880 }
2881
2882 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2883                                 u32 *data, u32 count)
2884 {
2885         int i, j, ret = 0;
2886         u32 temp;
2887         int err = 0;
2888
2889         /* Check alignment */
2890         if (addr & 0xF)
2891                 return -EIO;
2892
2893         mutex_lock(&adapter->ahw->mem_lock);
2894         qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2895
2896         for (i = 0; i < count; i++, addr += 16) {
2897                 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2898                                      QLCNIC_ADDR_QDR_NET_MAX)) ||
2899                       (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2900                                      QLCNIC_ADDR_DDR_NET_MAX)))) {
2901                         mutex_unlock(&adapter->ahw->mem_lock);
2902                         return -EIO;
2903                 }
2904
2905                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2906                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2907                                              *data++);
2908                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2909                                              *data++);
2910                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2911                                              *data++);
2912                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2913                                              *data++);
2914                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2915                                              QLCNIC_TA_WRITE_ENABLE);
2916                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2917                                              QLCNIC_TA_WRITE_START);
2918
2919                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2920                         temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err);
2921                         if (err == -EIO) {
2922                                 mutex_unlock(&adapter->ahw->mem_lock);
2923                                 return err;
2924                         }
2925
2926                         if ((temp & TA_CTL_BUSY) == 0)
2927                                 break;
2928                 }
2929
2930                 /* Status check failure */
2931                 if (j >= MAX_CTL_CHECK) {
2932                         printk_ratelimited(KERN_WARNING
2933                                            "MS memory write failed\n");
2934                         mutex_unlock(&adapter->ahw->mem_lock);
2935                         return -EIO;
2936                 }
2937         }
2938
2939         mutex_unlock(&adapter->ahw->mem_lock);
2940
2941         return ret;
2942 }
2943
2944 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2945                              u8 *p_data, int count)
2946 {
2947         u32 word, addr = flash_addr, ret;
2948         ulong  indirect_addr;
2949         int i, err = 0;
2950
2951         if (qlcnic_83xx_lock_flash(adapter) != 0)
2952                 return -EIO;
2953
2954         if (addr & 0x3) {
2955                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2956                 qlcnic_83xx_unlock_flash(adapter);
2957                 return -EIO;
2958         }
2959
2960         for (i = 0; i < count; i++) {
2961                 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2962                                                  QLC_83XX_FLASH_DIRECT_WINDOW,
2963                                                  (addr))) {
2964                         qlcnic_83xx_unlock_flash(adapter);
2965                         return -EIO;
2966                 }
2967
2968                 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2969                 ret = QLCRD32(adapter, indirect_addr, &err);
2970                 if (err == -EIO)
2971                         return err;
2972
2973                 word = ret;
2974                 *(u32 *)p_data  = word;
2975                 p_data = p_data + 4;
2976                 addr = addr + 4;
2977         }
2978
2979         qlcnic_83xx_unlock_flash(adapter);
2980
2981         return 0;
2982 }
2983
2984 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2985 {
2986         u8 pci_func;
2987         int err;
2988         u32 config = 0, state;
2989         struct qlcnic_cmd_args cmd;
2990         struct qlcnic_hardware_context *ahw = adapter->ahw;
2991
2992         if (qlcnic_sriov_vf_check(adapter))
2993                 pci_func = adapter->portnum;
2994         else
2995                 pci_func = ahw->pci_func;
2996
2997         state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
2998         if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
2999                 dev_info(&adapter->pdev->dev, "link state down\n");
3000                 return config;
3001         }
3002
3003         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3004         if (err)
3005                 return err;
3006
3007         err = qlcnic_issue_cmd(adapter, &cmd);
3008         if (err) {
3009                 dev_info(&adapter->pdev->dev,
3010                          "Get Link Status Command failed: 0x%x\n", err);
3011                 goto out;
3012         } else {
3013                 config = cmd.rsp.arg[1];
3014                 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3015                 case QLC_83XX_10M_LINK:
3016                         ahw->link_speed = SPEED_10;
3017                         break;
3018                 case QLC_83XX_100M_LINK:
3019                         ahw->link_speed = SPEED_100;
3020                         break;
3021                 case QLC_83XX_1G_LINK:
3022                         ahw->link_speed = SPEED_1000;
3023                         break;
3024                 case QLC_83XX_10G_LINK:
3025                         ahw->link_speed = SPEED_10000;
3026                         break;
3027                 default:
3028                         ahw->link_speed = 0;
3029                         break;
3030                 }
3031                 config = cmd.rsp.arg[3];
3032                 if (QLC_83XX_SFP_PRESENT(config)) {
3033                         switch (ahw->module_type) {
3034                         case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
3035                         case LINKEVENT_MODULE_OPTICAL_SRLR:
3036                         case LINKEVENT_MODULE_OPTICAL_LRM:
3037                         case LINKEVENT_MODULE_OPTICAL_SFP_1G:
3038                                 ahw->supported_type = PORT_FIBRE;
3039                                 break;
3040                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
3041                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
3042                         case LINKEVENT_MODULE_TWINAX:
3043                                 ahw->supported_type = PORT_TP;
3044                                 break;
3045                         default:
3046                                 ahw->supported_type = PORT_OTHER;
3047                         }
3048                 }
3049                 if (config & 1)
3050                         err = 1;
3051         }
3052 out:
3053         qlcnic_free_mbx_args(&cmd);
3054         return config;
3055 }
3056
3057 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3058                              struct ethtool_cmd *ecmd)
3059 {
3060         u32 config = 0;
3061         int status = 0;
3062         struct qlcnic_hardware_context *ahw = adapter->ahw;
3063
3064         if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3065                 /* Get port configuration info */
3066                 status = qlcnic_83xx_get_port_info(adapter);
3067                 /* Get Link Status related info */
3068                 config = qlcnic_83xx_test_link(adapter);
3069                 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3070         }
3071
3072         /* hard code until there is a way to get it from flash */
3073         ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3074
3075         if (netif_running(adapter->netdev) && ahw->has_link_events) {
3076                 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3077                 ecmd->duplex = ahw->link_duplex;
3078                 ecmd->autoneg = ahw->link_autoneg;
3079         } else {
3080                 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3081                 ecmd->duplex = DUPLEX_UNKNOWN;
3082                 ecmd->autoneg = AUTONEG_DISABLE;
3083         }
3084
3085         if (ahw->port_type == QLCNIC_XGBE) {
3086                 ecmd->supported = SUPPORTED_10000baseT_Full;
3087                 ecmd->advertising = ADVERTISED_10000baseT_Full;
3088         } else {
3089                 ecmd->supported = (SUPPORTED_10baseT_Half |
3090                                    SUPPORTED_10baseT_Full |
3091                                    SUPPORTED_100baseT_Half |
3092                                    SUPPORTED_100baseT_Full |
3093                                    SUPPORTED_1000baseT_Half |
3094                                    SUPPORTED_1000baseT_Full);
3095                 ecmd->advertising = (ADVERTISED_100baseT_Half |
3096                                      ADVERTISED_100baseT_Full |
3097                                      ADVERTISED_1000baseT_Half |
3098                                      ADVERTISED_1000baseT_Full);
3099         }
3100
3101         switch (ahw->supported_type) {
3102         case PORT_FIBRE:
3103                 ecmd->supported |= SUPPORTED_FIBRE;
3104                 ecmd->advertising |= ADVERTISED_FIBRE;
3105                 ecmd->port = PORT_FIBRE;
3106                 ecmd->transceiver = XCVR_EXTERNAL;
3107                 break;
3108         case PORT_TP:
3109                 ecmd->supported |= SUPPORTED_TP;
3110                 ecmd->advertising |= ADVERTISED_TP;
3111                 ecmd->port = PORT_TP;
3112                 ecmd->transceiver = XCVR_INTERNAL;
3113                 break;
3114         default:
3115                 ecmd->supported |= SUPPORTED_FIBRE;
3116                 ecmd->advertising |= ADVERTISED_FIBRE;
3117                 ecmd->port = PORT_OTHER;
3118                 ecmd->transceiver = XCVR_EXTERNAL;
3119                 break;
3120         }
3121         ecmd->phy_address = ahw->physical_port;
3122         return status;
3123 }
3124
3125 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3126                              struct ethtool_cmd *ecmd)
3127 {
3128         int status = 0;
3129         u32 config = adapter->ahw->port_config;
3130
3131         if (ecmd->autoneg)
3132                 adapter->ahw->port_config |= BIT_15;
3133
3134         switch (ethtool_cmd_speed(ecmd)) {
3135         case SPEED_10:
3136                 adapter->ahw->port_config |= BIT_8;
3137                 break;
3138         case SPEED_100:
3139                 adapter->ahw->port_config |= BIT_9;
3140                 break;
3141         case SPEED_1000:
3142                 adapter->ahw->port_config |= BIT_10;
3143                 break;
3144         case SPEED_10000:
3145                 adapter->ahw->port_config |= BIT_11;
3146                 break;
3147         default:
3148                 return -EINVAL;
3149         }
3150
3151         status = qlcnic_83xx_set_port_config(adapter);
3152         if (status) {
3153                 dev_info(&adapter->pdev->dev,
3154                          "Failed to Set Link Speed and autoneg.\n");
3155                 adapter->ahw->port_config = config;
3156         }
3157         return status;
3158 }
3159
3160 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3161                                           u64 *data, int index)
3162 {
3163         u32 low, hi;
3164         u64 val;
3165
3166         low = cmd->rsp.arg[index];
3167         hi = cmd->rsp.arg[index + 1];
3168         val = (((u64) low) | (((u64) hi) << 32));
3169         *data++ = val;
3170         return data;
3171 }
3172
3173 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3174                                    struct qlcnic_cmd_args *cmd, u64 *data,
3175                                    int type, int *ret)
3176 {
3177         int err, k, total_regs;
3178
3179         *ret = 0;
3180         err = qlcnic_issue_cmd(adapter, cmd);
3181         if (err != QLCNIC_RCODE_SUCCESS) {
3182                 dev_info(&adapter->pdev->dev,
3183                          "Error in get statistics mailbox command\n");
3184                 *ret = -EIO;
3185                 return data;
3186         }
3187         total_regs = cmd->rsp.num;
3188         switch (type) {
3189         case QLC_83XX_STAT_MAC:
3190                 /* fill in MAC tx counters */
3191                 for (k = 2; k < 28; k += 2)
3192                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3193                 /* skip 24 bytes of reserved area */
3194                 /* fill in MAC rx counters */
3195                 for (k += 6; k < 60; k += 2)
3196                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3197                 /* skip 24 bytes of reserved area */
3198                 /* fill in MAC rx frame stats */
3199                 for (k += 6; k < 80; k += 2)
3200                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3201                 /* fill in eSwitch stats */
3202                 for (; k < total_regs; k += 2)
3203                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3204                 break;
3205         case QLC_83XX_STAT_RX:
3206                 for (k = 2; k < 8; k += 2)
3207                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3208                 /* skip 8 bytes of reserved data */
3209                 for (k += 2; k < 24; k += 2)
3210                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3211                 /* skip 8 bytes containing RE1FBQ error data */
3212                 for (k += 2; k < total_regs; k += 2)
3213                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3214                 break;
3215         case QLC_83XX_STAT_TX:
3216                 for (k = 2; k < 10; k += 2)
3217                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3218                 /* skip 8 bytes of reserved data */
3219                 for (k += 2; k < total_regs; k += 2)
3220                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3221                 break;
3222         default:
3223                 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3224                 *ret = -EIO;
3225         }
3226         return data;
3227 }
3228
3229 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3230 {
3231         struct qlcnic_cmd_args cmd;
3232         struct net_device *netdev = adapter->netdev;
3233         int ret = 0;
3234
3235         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3236         if (ret)
3237                 return;
3238         /* Get Tx stats */
3239         cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3240         cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3241         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3242                                       QLC_83XX_STAT_TX, &ret);
3243         if (ret) {
3244                 netdev_err(netdev, "Error getting Tx stats\n");
3245                 goto out;
3246         }
3247         /* Get MAC stats */
3248         cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3249         cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3250         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3251         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3252                                       QLC_83XX_STAT_MAC, &ret);
3253         if (ret) {
3254                 netdev_err(netdev, "Error getting MAC stats\n");
3255                 goto out;
3256         }
3257         /* Get Rx stats */
3258         cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3259         cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3260         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3261         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3262                                       QLC_83XX_STAT_RX, &ret);
3263         if (ret)
3264                 netdev_err(netdev, "Error getting Rx stats\n");
3265 out:
3266         qlcnic_free_mbx_args(&cmd);
3267 }
3268
3269 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3270 {
3271         u32 major, minor, sub;
3272
3273         major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3274         minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3275         sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3276
3277         if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3278                 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3279                          __func__);
3280                 return 1;
3281         }
3282         return 0;
3283 }
3284
3285 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3286 {
3287         return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3288                 sizeof(*adapter->ahw->ext_reg_tbl)) +
3289                 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3290                 sizeof(*adapter->ahw->reg_tbl));
3291 }
3292
3293 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3294 {
3295         int i, j = 0;
3296
3297         for (i = QLCNIC_DEV_INFO_SIZE + 1;
3298              j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3299                 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3300
3301         for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3302                 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3303         return i;
3304 }
3305
3306 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3307 {
3308         struct qlcnic_adapter *adapter = netdev_priv(netdev);
3309         struct qlcnic_hardware_context *ahw = adapter->ahw;
3310         struct qlcnic_cmd_args cmd;
3311         u8 val, drv_sds_rings = adapter->drv_sds_rings;
3312         u8 drv_tx_rings = adapter->drv_tx_rings;
3313         u32 data;
3314         u16 intrpt_id, id;
3315         int ret;
3316
3317         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3318                 netdev_info(netdev, "Device is resetting\n");
3319                 return -EBUSY;
3320         }
3321
3322         if (qlcnic_get_diag_lock(adapter)) {
3323                 netdev_info(netdev, "Device in diagnostics mode\n");
3324                 return -EBUSY;
3325         }
3326
3327         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3328                                          drv_sds_rings);
3329         if (ret)
3330                 goto fail_diag_irq;
3331
3332         ahw->diag_cnt = 0;
3333         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3334         if (ret)
3335                 goto fail_diag_irq;
3336
3337         if (adapter->flags & QLCNIC_MSIX_ENABLED)
3338                 intrpt_id = ahw->intr_tbl[0].id;
3339         else
3340                 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3341
3342         cmd.req.arg[1] = 1;
3343         cmd.req.arg[2] = intrpt_id;
3344         cmd.req.arg[3] = BIT_0;
3345
3346         ret = qlcnic_issue_cmd(adapter, &cmd);
3347         data = cmd.rsp.arg[2];
3348         id = LSW(data);
3349         val = LSB(MSW(data));
3350         if (id != intrpt_id)
3351                 dev_info(&adapter->pdev->dev,
3352                          "Interrupt generated: 0x%x, requested:0x%x\n",
3353                          id, intrpt_id);
3354         if (val)
3355                 dev_err(&adapter->pdev->dev,
3356                          "Interrupt test error: 0x%x\n", val);
3357         if (ret)
3358                 goto done;
3359
3360         msleep(20);
3361         ret = !ahw->diag_cnt;
3362
3363 done:
3364         qlcnic_free_mbx_args(&cmd);
3365         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3366
3367 fail_diag_irq:
3368         adapter->drv_sds_rings = drv_sds_rings;
3369         adapter->drv_tx_rings = drv_tx_rings;
3370         qlcnic_release_diag_lock(adapter);
3371         return ret;
3372 }
3373
3374 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3375                                 struct ethtool_pauseparam *pause)
3376 {
3377         struct qlcnic_hardware_context *ahw = adapter->ahw;
3378         int status = 0;
3379         u32 config;
3380
3381         status = qlcnic_83xx_get_port_config(adapter);
3382         if (status) {
3383                 dev_err(&adapter->pdev->dev,
3384                         "%s: Get Pause Config failed\n", __func__);
3385                 return;
3386         }
3387         config = ahw->port_config;
3388         if (config & QLC_83XX_CFG_STD_PAUSE) {
3389                 switch (MSW(config)) {
3390                 case QLC_83XX_TX_PAUSE:
3391                         pause->tx_pause = 1;
3392                         break;
3393                 case QLC_83XX_RX_PAUSE:
3394                         pause->rx_pause = 1;
3395                         break;
3396                 case QLC_83XX_TX_RX_PAUSE:
3397                 default:
3398                         /* Backward compatibility for existing
3399                          * flash definitions
3400                          */
3401                         pause->tx_pause = 1;
3402                         pause->rx_pause = 1;
3403                 }
3404         }
3405
3406         if (QLC_83XX_AUTONEG(config))
3407                 pause->autoneg = 1;
3408 }
3409
3410 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3411                                struct ethtool_pauseparam *pause)
3412 {
3413         struct qlcnic_hardware_context *ahw = adapter->ahw;
3414         int status = 0;
3415         u32 config;
3416
3417         status = qlcnic_83xx_get_port_config(adapter);
3418         if (status) {
3419                 dev_err(&adapter->pdev->dev,
3420                         "%s: Get Pause Config failed.\n", __func__);
3421                 return status;
3422         }
3423         config = ahw->port_config;
3424
3425         if (ahw->port_type == QLCNIC_GBE) {
3426                 if (pause->autoneg)
3427                         ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3428                 if (!pause->autoneg)
3429                         ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3430         } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3431                 return -EOPNOTSUPP;
3432         }
3433
3434         if (!(config & QLC_83XX_CFG_STD_PAUSE))
3435                 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3436
3437         if (pause->rx_pause && pause->tx_pause) {
3438                 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3439         } else if (pause->rx_pause && !pause->tx_pause) {
3440                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3441                 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3442         } else if (pause->tx_pause && !pause->rx_pause) {
3443                 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3444                 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3445         } else if (!pause->rx_pause && !pause->tx_pause) {
3446                 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3447                                       QLC_83XX_CFG_STD_PAUSE);
3448         }
3449         status = qlcnic_83xx_set_port_config(adapter);
3450         if (status) {
3451                 dev_err(&adapter->pdev->dev,
3452                         "%s: Set Pause Config failed.\n", __func__);
3453                 ahw->port_config = config;
3454         }
3455         return status;
3456 }
3457
3458 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3459 {
3460         int ret, err = 0;
3461         u32 temp;
3462
3463         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3464                                      QLC_83XX_FLASH_OEM_READ_SIG);
3465         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3466                                      QLC_83XX_FLASH_READ_CTRL);
3467         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3468         if (ret)
3469                 return -EIO;
3470
3471         temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3472         if (err == -EIO)
3473                 return err;
3474
3475         return temp & 0xFF;
3476 }
3477
3478 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3479 {
3480         int status;
3481
3482         status = qlcnic_83xx_read_flash_status_reg(adapter);
3483         if (status == -EIO) {
3484                 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3485                          __func__);
3486                 return 1;
3487         }
3488         return 0;
3489 }
3490
3491 int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3492 {
3493         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3494         struct net_device *netdev = adapter->netdev;
3495         int retval;
3496
3497         netif_device_detach(netdev);
3498         qlcnic_cancel_idc_work(adapter);
3499
3500         if (netif_running(netdev))
3501                 qlcnic_down(adapter, netdev);
3502
3503         qlcnic_83xx_disable_mbx_intr(adapter);
3504         cancel_delayed_work_sync(&adapter->idc_aen_work);
3505
3506         retval = pci_save_state(pdev);
3507         if (retval)
3508                 return retval;
3509
3510         return 0;
3511 }
3512
3513 int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3514 {
3515         struct qlcnic_hardware_context *ahw = adapter->ahw;
3516         struct qlc_83xx_idc *idc = &ahw->idc;
3517         int err = 0;
3518
3519         err = qlcnic_83xx_idc_init(adapter);
3520         if (err)
3521                 return err;
3522
3523         if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3524                 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3525                         qlcnic_83xx_set_vnic_opmode(adapter);
3526                 } else {
3527                         err = qlcnic_83xx_check_vnic_state(adapter);
3528                         if (err)
3529                                 return err;
3530                 }
3531         }
3532
3533         err = qlcnic_83xx_idc_reattach_driver(adapter);
3534         if (err)
3535                 return err;
3536
3537         qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3538                              idc->delay);
3539         return err;
3540 }
3541
3542 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3543 {
3544         reinit_completion(&mbx->completion);
3545         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3546 }
3547
3548 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3549 {
3550         if (!mbx)
3551                 return;
3552
3553         destroy_workqueue(mbx->work_q);
3554         kfree(mbx);
3555 }
3556
3557 static inline void
3558 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3559                                   struct qlcnic_cmd_args *cmd)
3560 {
3561         atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3562
3563         if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3564                 qlcnic_free_mbx_args(cmd);
3565                 kfree(cmd);
3566                 return;
3567         }
3568         complete(&cmd->completion);
3569 }
3570
3571 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3572 {
3573         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3574         struct list_head *head = &mbx->cmd_q;
3575         struct qlcnic_cmd_args *cmd = NULL;
3576
3577         spin_lock(&mbx->queue_lock);
3578
3579         while (!list_empty(head)) {
3580                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3581                 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3582                          __func__, cmd->cmd_op);
3583                 list_del(&cmd->list);
3584                 mbx->num_cmds--;
3585                 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3586         }
3587
3588         spin_unlock(&mbx->queue_lock);
3589 }
3590
3591 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3592 {
3593         struct qlcnic_hardware_context *ahw = adapter->ahw;
3594         struct qlcnic_mailbox *mbx = ahw->mailbox;
3595         u32 host_mbx_ctrl;
3596
3597         if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3598                 return -EBUSY;
3599
3600         host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3601         if (host_mbx_ctrl) {
3602                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3603                 ahw->idc.collect_dump = 1;
3604                 return -EIO;
3605         }
3606
3607         return 0;
3608 }
3609
3610 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3611                                               u8 issue_cmd)
3612 {
3613         if (issue_cmd)
3614                 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3615         else
3616                 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3617 }
3618
3619 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3620                                         struct qlcnic_cmd_args *cmd)
3621 {
3622         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3623
3624         spin_lock(&mbx->queue_lock);
3625
3626         list_del(&cmd->list);
3627         mbx->num_cmds--;
3628
3629         spin_unlock(&mbx->queue_lock);
3630
3631         qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3632 }
3633
3634 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3635                                        struct qlcnic_cmd_args *cmd)
3636 {
3637         u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3638         struct qlcnic_hardware_context *ahw = adapter->ahw;
3639         int i, j;
3640
3641         if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3642                 mbx_cmd = cmd->req.arg[0];
3643                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3644                 for (i = 1; i < cmd->req.num; i++)
3645                         writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3646         } else {
3647                 fw_hal_version = ahw->fw_hal_version;
3648                 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3649                 total_size = cmd->pay_size + hdr_size;
3650                 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3651                 mbx_cmd = tmp | fw_hal_version << 29;
3652                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3653
3654                 /* Back channel specific operations bits */
3655                 mbx_cmd = 0x1 | 1 << 4;
3656
3657                 if (qlcnic_sriov_pf_check(adapter))
3658                         mbx_cmd |= cmd->func_num << 5;
3659
3660                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3661
3662                 for (i = 2, j = 0; j < hdr_size; i++, j++)
3663                         writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3664                 for (j = 0; j < cmd->pay_size; j++, i++)
3665                         writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3666         }
3667 }
3668
3669 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3670 {
3671         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3672
3673         if (!mbx)
3674                 return;
3675
3676         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3677         complete(&mbx->completion);
3678         cancel_work_sync(&mbx->work);
3679         flush_workqueue(mbx->work_q);
3680         qlcnic_83xx_flush_mbx_queue(adapter);
3681 }
3682
3683 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3684                                        struct qlcnic_cmd_args *cmd,
3685                                        unsigned long *timeout)
3686 {
3687         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3688
3689         if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3690                 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3691                 init_completion(&cmd->completion);
3692                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3693
3694                 spin_lock(&mbx->queue_lock);
3695
3696                 list_add_tail(&cmd->list, &mbx->cmd_q);
3697                 mbx->num_cmds++;
3698                 cmd->total_cmds = mbx->num_cmds;
3699                 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3700                 queue_work(mbx->work_q, &mbx->work);
3701
3702                 spin_unlock(&mbx->queue_lock);
3703
3704                 return 0;
3705         }
3706
3707         return -EBUSY;
3708 }
3709
3710 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3711                                        struct qlcnic_cmd_args *cmd)
3712 {
3713         u8 mac_cmd_rcode;
3714         u32 fw_data;
3715
3716         if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3717                 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3718                 mac_cmd_rcode = (u8)fw_data;
3719                 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3720                     mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3721                     mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3722                         cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3723                         return QLCNIC_RCODE_SUCCESS;
3724                 }
3725         }
3726
3727         return -EINVAL;
3728 }
3729
3730 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3731                                        struct qlcnic_cmd_args *cmd)
3732 {
3733         struct qlcnic_hardware_context *ahw = adapter->ahw;
3734         struct device *dev = &adapter->pdev->dev;
3735         u8 mbx_err_code;
3736         u32 fw_data;
3737
3738         fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3739         mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3740         qlcnic_83xx_get_mbx_data(adapter, cmd);
3741
3742         switch (mbx_err_code) {
3743         case QLCNIC_MBX_RSP_OK:
3744         case QLCNIC_MBX_PORT_RSP_OK:
3745                 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3746                 break;
3747         default:
3748                 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3749                         break;
3750
3751                 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3752                         __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3753                         ahw->op_mode, mbx_err_code);
3754                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3755                 qlcnic_dump_mbx(adapter, cmd);
3756         }
3757
3758         return;
3759 }
3760
3761 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3762 {
3763         struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3764                                                   work);
3765         struct qlcnic_adapter *adapter = mbx->adapter;
3766         struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3767         struct device *dev = &adapter->pdev->dev;
3768         atomic_t *rsp_status = &mbx->rsp_status;
3769         struct list_head *head = &mbx->cmd_q;
3770         struct qlcnic_hardware_context *ahw;
3771         struct qlcnic_cmd_args *cmd = NULL;
3772
3773         ahw = adapter->ahw;
3774
3775         while (true) {
3776                 if (qlcnic_83xx_check_mbx_status(adapter)) {
3777                         qlcnic_83xx_flush_mbx_queue(adapter);
3778                         return;
3779                 }
3780
3781                 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3782
3783                 spin_lock(&mbx->queue_lock);
3784
3785                 if (list_empty(head)) {
3786                         spin_unlock(&mbx->queue_lock);
3787                         return;
3788                 }
3789                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3790
3791                 spin_unlock(&mbx->queue_lock);
3792
3793                 mbx_ops->encode_cmd(adapter, cmd);
3794                 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3795
3796                 if (wait_for_completion_timeout(&mbx->completion,
3797                                                 QLC_83XX_MBX_TIMEOUT)) {
3798                         mbx_ops->decode_resp(adapter, cmd);
3799                         mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3800                 } else {
3801                         dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3802                                 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3803                                 ahw->op_mode);
3804                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3805                         qlcnic_dump_mbx(adapter, cmd);
3806                         qlcnic_83xx_idc_request_reset(adapter,
3807                                                       QLCNIC_FORCE_FW_DUMP_KEY);
3808                         cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3809                 }
3810                 mbx_ops->dequeue_cmd(adapter, cmd);
3811         }
3812 }
3813
3814 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3815         .enqueue_cmd    = qlcnic_83xx_enqueue_mbx_cmd,
3816         .dequeue_cmd    = qlcnic_83xx_dequeue_mbx_cmd,
3817         .decode_resp    = qlcnic_83xx_decode_mbx_rsp,
3818         .encode_cmd     = qlcnic_83xx_encode_mbx_cmd,
3819         .nofity_fw      = qlcnic_83xx_signal_mbx_cmd,
3820 };
3821
3822 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3823 {
3824         struct qlcnic_hardware_context *ahw = adapter->ahw;
3825         struct qlcnic_mailbox *mbx;
3826
3827         ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3828         if (!ahw->mailbox)
3829                 return -ENOMEM;
3830
3831         mbx = ahw->mailbox;
3832         mbx->ops = &qlcnic_83xx_mbx_ops;
3833         mbx->adapter = adapter;
3834
3835         spin_lock_init(&mbx->queue_lock);
3836         spin_lock_init(&mbx->aen_lock);
3837         INIT_LIST_HEAD(&mbx->cmd_q);
3838         init_completion(&mbx->completion);
3839
3840         mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3841         if (mbx->work_q == NULL) {
3842                 kfree(mbx);
3843                 return -ENOMEM;
3844         }
3845
3846         INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
3847         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3848         return 0;
3849 }
3850
3851 pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
3852                                                pci_channel_state_t state)
3853 {
3854         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3855
3856         if (state == pci_channel_io_perm_failure)
3857                 return PCI_ERS_RESULT_DISCONNECT;
3858
3859         if (state == pci_channel_io_normal)
3860                 return PCI_ERS_RESULT_RECOVERED;
3861
3862         set_bit(__QLCNIC_AER, &adapter->state);
3863         set_bit(__QLCNIC_RESETTING, &adapter->state);
3864
3865         qlcnic_83xx_aer_stop_poll_work(adapter);
3866
3867         pci_save_state(pdev);
3868         pci_disable_device(pdev);
3869
3870         return PCI_ERS_RESULT_NEED_RESET;
3871 }
3872
3873 pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
3874 {
3875         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3876         int err = 0;
3877
3878         pdev->error_state = pci_channel_io_normal;
3879         err = pci_enable_device(pdev);
3880         if (err)
3881                 goto disconnect;
3882
3883         pci_set_power_state(pdev, PCI_D0);
3884         pci_set_master(pdev);
3885         pci_restore_state(pdev);
3886
3887         err = qlcnic_83xx_aer_reset(adapter);
3888         if (err == 0)
3889                 return PCI_ERS_RESULT_RECOVERED;
3890 disconnect:
3891         clear_bit(__QLCNIC_AER, &adapter->state);
3892         clear_bit(__QLCNIC_RESETTING, &adapter->state);
3893         return PCI_ERS_RESULT_DISCONNECT;
3894 }
3895
3896 void qlcnic_83xx_io_resume(struct pci_dev *pdev)
3897 {
3898         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3899
3900         pci_cleanup_aer_uncorrect_error_status(pdev);
3901         if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
3902                 qlcnic_83xx_aer_start_poll_work(adapter);
3903 }