Pileus Git - ~andy/linux/blob - drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_sriov.h"
  10 #include <linux/if_vlan.h>
  11 #include <linux/ipv6.h>
  12 #include <linux/ethtool.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/aer.h>
  15
  16 #define RSS_HASHTYPE_IP_TCP             0x3
  17 #define QLC_83XX_FW_MBX_CMD             0
  18 #define QLC_SKIP_INACTIVE_PCI_REGS      7
  19
  20 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
  21         {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
  22         {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
  23         {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
  24         {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  25         {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
  26         {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  27         {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
  28         {QLCNIC_CMD_INTRPT_TEST, 22, 12},
  29         {QLCNIC_CMD_SET_MTU, 3, 1},
  30         {QLCNIC_CMD_READ_PHY, 4, 2},
  31         {QLCNIC_CMD_WRITE_PHY, 5, 1},
  32         {QLCNIC_CMD_READ_HW_REG, 4, 1},
  33         {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  34         {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  35         {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  36         {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  37         {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  38         {QLCNIC_CMD_GET_PCI_INFO, 1, 129},
  39         {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
  40         {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
  41         {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  42         {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  43         {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  44         {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  45         {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  46         {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  47         {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  48         {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  49         {QLCNIC_CMD_TEMP_SIZE, 1, 4},
  50         {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
  51         {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
  52         {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
  53         {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
  54         {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
  55         {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
  56         {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
  57         {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
  58         {QLCNIC_CMD_GET_STATISTICS, 2, 80},
  59         {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
  60         {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
  61         {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
  62         {QLCNIC_CMD_IDC_ACK, 5, 1},
  63         {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
  64         {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
  65         {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
  66         {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
  67         {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
  68         {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
  69         {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
  70         {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
  71         {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
  72         {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
  73 };
  74
  75 const u32 qlcnic_83xx_ext_reg_tbl[] = {
  76         0x38CC,         /* Global Reset */
  77         0x38F0,         /* Wildcard */
  78         0x38FC,         /* Informant */
  79         0x3038,         /* Host MBX ctrl */
  80         0x303C,         /* FW MBX ctrl */
  81         0x355C,         /* BOOT LOADER ADDRESS REG */
  82         0x3560,         /* BOOT LOADER SIZE REG */
  83         0x3564,         /* FW IMAGE ADDR REG */
  84         0x1000,         /* MBX intr enable */
  85         0x1200,         /* Default Intr mask */
  86         0x1204,         /* Default Interrupt ID */
  87         0x3780,         /* QLC_83XX_IDC_MAJ_VERSION */
  88         0x3784,         /* QLC_83XX_IDC_DEV_STATE */
  89         0x3788,         /* QLC_83XX_IDC_DRV_PRESENCE */
  90         0x378C,         /* QLC_83XX_IDC_DRV_ACK */
  91         0x3790,         /* QLC_83XX_IDC_CTRL */
  92         0x3794,         /* QLC_83XX_IDC_DRV_AUDIT */
  93         0x3798,         /* QLC_83XX_IDC_MIN_VERSION */
  94         0x379C,         /* QLC_83XX_RECOVER_DRV_LOCK */
  95         0x37A0,         /* QLC_83XX_IDC_PF_0 */
  96         0x37A4,         /* QLC_83XX_IDC_PF_1 */
  97         0x37A8,         /* QLC_83XX_IDC_PF_2 */
  98         0x37AC,         /* QLC_83XX_IDC_PF_3 */
  99         0x37B0,         /* QLC_83XX_IDC_PF_4 */
 100         0x37B4,         /* QLC_83XX_IDC_PF_5 */
 101         0x37B8,         /* QLC_83XX_IDC_PF_6 */
 102         0x37BC,         /* QLC_83XX_IDC_PF_7 */
 103         0x37C0,         /* QLC_83XX_IDC_PF_8 */
 104         0x37C4,         /* QLC_83XX_IDC_PF_9 */
 105         0x37C8,         /* QLC_83XX_IDC_PF_10 */
 106         0x37CC,         /* QLC_83XX_IDC_PF_11 */
 107         0x37D0,         /* QLC_83XX_IDC_PF_12 */
 108         0x37D4,         /* QLC_83XX_IDC_PF_13 */
 109         0x37D8,         /* QLC_83XX_IDC_PF_14 */
 110         0x37DC,         /* QLC_83XX_IDC_PF_15 */
 111         0x37E0,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
 112         0x37E4,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
 113         0x37F0,         /* QLC_83XX_DRV_OP_MODE */
 114         0x37F4,         /* QLC_83XX_VNIC_STATE */
 115         0x3868,         /* QLC_83XX_DRV_LOCK */
 116         0x386C,         /* QLC_83XX_DRV_UNLOCK */
 117         0x3504,         /* QLC_83XX_DRV_LOCK_ID */
 118         0x34A4,         /* QLC_83XX_ASIC_TEMP */
 119 };
 120
 121 const u32 qlcnic_83xx_reg_tbl[] = {
 122         0x34A8,         /* PEG_HALT_STAT1 */
 123         0x34AC,         /* PEG_HALT_STAT2 */
 124         0x34B0,         /* FW_HEARTBEAT */
 125         0x3500,         /* FLASH LOCK_ID */
 126         0x3528,         /* FW_CAPABILITIES */
 127         0x3538,         /* Driver active, DRV_REG0 */
 128         0x3540,         /* Device state, DRV_REG1 */
 129         0x3544,         /* Driver state, DRV_REG2 */
 130         0x3548,         /* Driver scratch, DRV_REG3 */
 131         0x354C,         /* Device partiton info, DRV_REG4 */
 132         0x3524,         /* Driver IDC ver, DRV_REG5 */
 133         0x3550,         /* FW_VER_MAJOR */
 134         0x3554,         /* FW_VER_MINOR */
 135         0x3558,         /* FW_VER_SUB */
 136         0x359C,         /* NPAR STATE */
 137         0x35FC,         /* FW_IMG_VALID */
 138         0x3650,         /* CMD_PEG_STATE */
 139         0x373C,         /* RCV_PEG_STATE */
 140         0x37B4,         /* ASIC TEMP */
 141         0x356C,         /* FW API */
 142         0x3570,         /* DRV OP MODE */
 143         0x3850,         /* FLASH LOCK */
 144         0x3854,         /* FLASH UNLOCK */
 145 };
 146
 147 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
 148         .read_crb                       = qlcnic_83xx_read_crb,
 149         .write_crb                      = qlcnic_83xx_write_crb,
 150         .read_reg                       = qlcnic_83xx_rd_reg_indirect,
 151         .write_reg                      = qlcnic_83xx_wrt_reg_indirect,
 152         .get_mac_address                = qlcnic_83xx_get_mac_address,
 153         .setup_intr                     = qlcnic_83xx_setup_intr,
 154         .alloc_mbx_args                 = qlcnic_83xx_alloc_mbx_args,
 155         .mbx_cmd                        = qlcnic_83xx_issue_cmd,
 156         .get_func_no                    = qlcnic_83xx_get_func_no,
 157         .api_lock                       = qlcnic_83xx_cam_lock,
 158         .api_unlock                     = qlcnic_83xx_cam_unlock,
 159         .add_sysfs                      = qlcnic_83xx_add_sysfs,
 160         .remove_sysfs                   = qlcnic_83xx_remove_sysfs,
 161         .process_lb_rcv_ring_diag       = qlcnic_83xx_process_rcv_ring_diag,
 162         .create_rx_ctx                  = qlcnic_83xx_create_rx_ctx,
 163         .create_tx_ctx                  = qlcnic_83xx_create_tx_ctx,
 164         .del_rx_ctx                     = qlcnic_83xx_del_rx_ctx,
 165         .del_tx_ctx                     = qlcnic_83xx_del_tx_ctx,
 166         .setup_link_event               = qlcnic_83xx_setup_link_event,
 167         .get_nic_info                   = qlcnic_83xx_get_nic_info,
 168         .get_pci_info                   = qlcnic_83xx_get_pci_info,
 169         .set_nic_info                   = qlcnic_83xx_set_nic_info,
 170         .change_macvlan                 = qlcnic_83xx_sre_macaddr_change,
 171         .napi_enable                    = qlcnic_83xx_napi_enable,
 172         .napi_disable                   = qlcnic_83xx_napi_disable,
 173         .config_intr_coal               = qlcnic_83xx_config_intr_coal,
 174         .config_rss                     = qlcnic_83xx_config_rss,
 175         .config_hw_lro                  = qlcnic_83xx_config_hw_lro,
 176         .config_promisc_mode            = qlcnic_83xx_nic_set_promisc,
 177         .change_l2_filter               = qlcnic_83xx_change_l2_filter,
 178         .get_board_info                 = qlcnic_83xx_get_port_info,
 179         .set_mac_filter_count           = qlcnic_83xx_set_mac_filter_count,
 180         .free_mac_list                  = qlcnic_82xx_free_mac_list,
 181         .io_error_detected              = qlcnic_83xx_io_error_detected,
 182         .io_slot_reset                  = qlcnic_83xx_io_slot_reset,
 183         .io_resume                      = qlcnic_83xx_io_resume,
 184
 185 };
 186
 187 static struct qlcnic_nic_template qlcnic_83xx_ops = {
 188         .config_bridged_mode    = qlcnic_config_bridged_mode,
 189         .config_led             = qlcnic_config_led,
 190         .request_reset          = qlcnic_83xx_idc_request_reset,
 191         .cancel_idc_work        = qlcnic_83xx_idc_exit,
 192         .napi_add               = qlcnic_83xx_napi_add,
 193         .napi_del               = qlcnic_83xx_napi_del,
 194         .config_ipaddr          = qlcnic_83xx_config_ipaddr,
 195         .clear_legacy_intr      = qlcnic_83xx_clear_legacy_intr,
 196         .shutdown               = qlcnic_83xx_shutdown,
 197         .resume                 = qlcnic_83xx_resume,
 198 };
 199
 200 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
 201 {
 202         ahw->hw_ops             = &qlcnic_83xx_hw_ops;
 203         ahw->reg_tbl            = (u32 *)qlcnic_83xx_reg_tbl;
 204         ahw->ext_reg_tbl        = (u32 *)qlcnic_83xx_ext_reg_tbl;
 205 }
 206
 207 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
 208 {
 209         u32 fw_major, fw_minor, fw_build;
 210         struct pci_dev *pdev = adapter->pdev;
 211
 212         fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
 213         fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
 214         fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
 215         adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
 216
 217         dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
 218                  QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
 219
 220         return adapter->fw_version;
 221 }
 222
 223 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
 224 {
 225         void __iomem *base;
 226         u32 val;
 227
 228         base = adapter->ahw->pci_base0 +
 229                QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
 230         writel(addr, base);
 231         val = readl(base);
 232         if (val != addr)
 233                 return -EIO;
 234
 235         return 0;
 236 }
 237
 238 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 239                                 int *err)
 240 {
 241         struct qlcnic_hardware_context *ahw = adapter->ahw;
 242
 243         *err = __qlcnic_set_win_base(adapter, (u32) addr);
 244         if (!*err) {
 245                 return QLCRDX(ahw, QLCNIC_WILDCARD);
 246         } else {
 247                 dev_err(&adapter->pdev->dev,
 248                         "%s failed, addr = 0x%lx\n", __func__, addr);
 249                 return -EIO;
 250         }
 251 }
 252
 253 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 254                                  u32 data)
 255 {
 256         int err;
 257         struct qlcnic_hardware_context *ahw = adapter->ahw;
 258
 259         err = __qlcnic_set_win_base(adapter, (u32) addr);
 260         if (!err) {
 261                 QLCWRX(ahw, QLCNIC_WILDCARD, data);
 262                 return 0;
 263         } else {
 264                 dev_err(&adapter->pdev->dev,
 265                         "%s failed, addr = 0x%x data = 0x%x\n",
 266                         __func__, (int)addr, data);
 267                 return err;
 268         }
 269 }
 270
 271 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
 272 {
 273         int err, i, num_msix;
 274         struct qlcnic_hardware_context *ahw = adapter->ahw;
 275
 276         num_msix = adapter->drv_sds_rings;
 277
 278         /* account for AEN interrupt MSI-X based interrupts */
 279         num_msix += 1;
 280
 281         if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
 282                 num_msix += adapter->drv_tx_rings;
 283
 284         err = qlcnic_enable_msix(adapter, num_msix);
 285         if (err == -ENOMEM)
 286                 return err;
 287         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 288                 num_msix = adapter->ahw->num_msix;
 289         else {
 290                 if (qlcnic_sriov_vf_check(adapter))
 291                         return -EINVAL;
 292                 num_msix = 1;
 293                 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
 294         }
 295         /* setup interrupt mapping table for fw */
 296         ahw->intr_tbl = vzalloc(num_msix *
 297                                 sizeof(struct qlcnic_intrpt_config));
 298         if (!ahw->intr_tbl)
 299                 return -ENOMEM;
 300         if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
 301                 /* MSI-X enablement failed, use legacy interrupt */
 302                 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
 303                 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
 304                 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
 305                 adapter->msix_entries[0].vector = adapter->pdev->irq;
 306                 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
 307         }
 308
 309         for (i = 0; i < num_msix; i++) {
 310                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
 311                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
 312                 else
 313                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
 314                 ahw->intr_tbl[i].id = i;
 315                 ahw->intr_tbl[i].src = 0;
 316         }
 317         return 0;
 318 }
 319
 320 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
 321 {
 322         writel(0, adapter->tgt_mask_reg);
 323 }
 324
 325 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
 326 {
 327         if (adapter->tgt_mask_reg)
 328                 writel(1, adapter->tgt_mask_reg);
 329 }
 330
 331 /* Enable MSI-x and INT-x interrupts */
 332 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
 333                              struct qlcnic_host_sds_ring *sds_ring)
 334 {
 335         writel(0, sds_ring->crb_intr_mask);
 336 }
 337
 338 /* Disable MSI-x and INT-x interrupts */
 339 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
 340                               struct qlcnic_host_sds_ring *sds_ring)
 341 {
 342         writel(1, sds_ring->crb_intr_mask);
 343 }
 344
 345 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
 346                                                     *adapter)
 347 {
 348         u32 mask;
 349
 350         /* Mailbox in MSI-x mode and Legacy Interrupt share the same
 351          * source register. We could be here before contexts are created
 352          * and sds_ring->crb_intr_mask has not been initialized, calculate
 353          * BAR offset for Interrupt Source Register
 354          */
 355         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 356         writel(0, adapter->ahw->pci_base0 + mask);
 357 }
 358
 359 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
 360 {
 361         u32 mask;
 362
 363         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 364         writel(1, adapter->ahw->pci_base0 + mask);
 365         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
 366 }
 367
 368 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
 369                                      struct qlcnic_cmd_args *cmd)
 370 {
 371         int i;
 372
 373         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 374                 return;
 375
 376         for (i = 0; i < cmd->rsp.num; i++)
 377                 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
 378 }
 379
 380 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
 381 {
 382         u32 intr_val;
 383         struct qlcnic_hardware_context *ahw = adapter->ahw;
 384         int retries = 0;
 385
 386         intr_val = readl(adapter->tgt_status_reg);
 387
 388         if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
 389                 return IRQ_NONE;
 390
 391         if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
 392                 adapter->stats.spurious_intr++;
 393                 return IRQ_NONE;
 394         }
 395         /* The barrier is required to ensure writes to the registers */
 396         wmb();
 397
 398         /* clear the interrupt trigger control register */
 399         writel(0, adapter->isr_int_vec);
 400         intr_val = readl(adapter->isr_int_vec);
 401         do {
 402                 intr_val = readl(adapter->tgt_status_reg);
 403                 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
 404                         break;
 405                 retries++;
 406         } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
 407                  (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
 408
 409         return IRQ_HANDLED;
 410 }
 411
 412 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
 413 {
 414         atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
 415         complete(&mbx->completion);
 416 }
 417
 418 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
 419 {
 420         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 421         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 422         unsigned long flags;
 423
 424         spin_lock_irqsave(&mbx->aen_lock, flags);
 425         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
 426         if (!(resp & QLCNIC_SET_OWNER))
 427                 goto out;
 428
 429         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
 430         if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 431                 __qlcnic_83xx_process_aen(adapter);
 432         } else {
 433                 if (atomic_read(&mbx->rsp_status) != rsp_status)
 434                         qlcnic_83xx_notify_mbx_response(mbx);
 435         }
 436 out:
 437         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 438         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 439 }
 440
 441 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
 442 {
 443         struct qlcnic_adapter *adapter = data;
 444         struct qlcnic_host_sds_ring *sds_ring;
 445         struct qlcnic_hardware_context *ahw = adapter->ahw;
 446
 447         if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
 448                 return IRQ_NONE;
 449
 450         qlcnic_83xx_poll_process_aen(adapter);
 451
 452         if (ahw->diag_test) {
 453                 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
 454                         ahw->diag_cnt++;
 455                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 456                 return IRQ_HANDLED;
 457         }
 458
 459         if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
 460                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 461         } else {
 462                 sds_ring = &adapter->recv_ctx->sds_rings[0];
 463                 napi_schedule(&sds_ring->napi);
 464         }
 465
 466         return IRQ_HANDLED;
 467 }
 468
 469 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
 470 {
 471         struct qlcnic_host_sds_ring *sds_ring = data;
 472         struct qlcnic_adapter *adapter = sds_ring->adapter;
 473
 474         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 475                 goto done;
 476
 477         if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
 478                 return IRQ_NONE;
 479
 480 done:
 481         adapter->ahw->diag_cnt++;
 482         qlcnic_83xx_enable_intr(adapter, sds_ring);
 483
 484         return IRQ_HANDLED;
 485 }
 486
 487 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
 488 {
 489         u32 num_msix;
 490
 491         if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
 492                 qlcnic_83xx_set_legacy_intr_mask(adapter);
 493
 494         qlcnic_83xx_disable_mbx_intr(adapter);
 495
 496         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 497                 num_msix = adapter->ahw->num_msix - 1;
 498         else
 499                 num_msix = 0;
 500
 501         msleep(20);
 502
 503         if (adapter->msix_entries) {
 504                 synchronize_irq(adapter->msix_entries[num_msix].vector);
 505                 free_irq(adapter->msix_entries[num_msix].vector, adapter);
 506         }
 507 }
 508
 509 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
 510 {
 511         irq_handler_t handler;
 512         u32 val;
 513         int err = 0;
 514         unsigned long flags = 0;
 515
 516         if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
 517             !(adapter->flags & QLCNIC_MSIX_ENABLED))
 518                 flags |= IRQF_SHARED;
 519
 520         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 521                 handler = qlcnic_83xx_handle_aen;
 522                 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
 523                 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
 524                 if (err) {
 525                         dev_err(&adapter->pdev->dev,
 526                                 "failed to register MBX interrupt\n");
 527                         return err;
 528                 }
 529         } else {
 530                 handler = qlcnic_83xx_intr;
 531                 val = adapter->msix_entries[0].vector;
 532                 err = request_irq(val, handler, flags, "qlcnic", adapter);
 533                 if (err) {
 534                         dev_err(&adapter->pdev->dev,
 535                                 "failed to register INTx interrupt\n");
 536                         return err;
 537                 }
 538                 qlcnic_83xx_clear_legacy_intr_mask(adapter);
 539         }
 540
 541         /* Enable mailbox interrupt */
 542         qlcnic_83xx_enable_mbx_interrupt(adapter);
 543
 544         return err;
 545 }
 546
 547 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
 548 {
 549         u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
 550         adapter->ahw->pci_func = (val >> 24) & 0xff;
 551 }
 552
 553 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
 554 {
 555         void __iomem *addr;
 556         u32 val, limit = 0;
 557
 558         struct qlcnic_hardware_context *ahw = adapter->ahw;
 559
 560         addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
 561         do {
 562                 val = readl(addr);
 563                 if (val) {
 564                         /* write the function number to register */
 565                         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
 566                                             ahw->pci_func);
 567                         return 0;
 568                 }
 569                 usleep_range(1000, 2000);
 570         } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
 571
 572         return -EIO;
 573 }
 574
 575 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
 576 {
 577         void __iomem *addr;
 578         u32 val;
 579         struct qlcnic_hardware_context *ahw = adapter->ahw;
 580
 581         addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
 582         val = readl(addr);
 583 }
 584
 585 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
 586                           loff_t offset, size_t size)
 587 {
 588         int ret = 0;
 589         u32 data;
 590
 591         if (qlcnic_api_lock(adapter)) {
 592                 dev_err(&adapter->pdev->dev,
 593                         "%s: failed to acquire lock. addr offset 0x%x\n",
 594                         __func__, (u32)offset);
 595                 return;
 596         }
 597
 598         data = QLCRD32(adapter, (u32) offset, &ret);
 599         qlcnic_api_unlock(adapter);
 600
 601         if (ret == -EIO) {
 602                 dev_err(&adapter->pdev->dev,
 603                         "%s: failed. addr offset 0x%x\n",
 604                         __func__, (u32)offset);
 605                 return;
 606         }
 607         memcpy(buf, &data, size);
 608 }
 609
 610 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
 611                            loff_t offset, size_t size)
 612 {
 613         u32 data;
 614
 615         memcpy(&data, buf, size);
 616         qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
 617 }
 618
 619 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
 620 {
 621         int status;
 622
 623         status = qlcnic_83xx_get_port_config(adapter);
 624         if (status) {
 625                 dev_err(&adapter->pdev->dev,
 626                         "Get Port Info failed\n");
 627         } else {
 628                 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
 629                         adapter->ahw->port_type = QLCNIC_XGBE;
 630                 else
 631                         adapter->ahw->port_type = QLCNIC_GBE;
 632
 633                 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
 634                         adapter->ahw->link_autoneg = AUTONEG_ENABLE;
 635         }
 636         return status;
 637 }
 638
 639 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
 640 {
 641         struct qlcnic_hardware_context *ahw = adapter->ahw;
 642         u16 act_pci_fn = ahw->total_nic_func;
 643         u16 count;
 644
 645         ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
 646         if (act_pci_fn <= 2)
 647                 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
 648                          act_pci_fn;
 649         else
 650                 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
 651                          act_pci_fn;
 652         ahw->max_uc_count = count;
 653 }
 654
 655 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
 656 {
 657         u32 val;
 658
 659         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 660                 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
 661         else
 662                 val = BIT_2;
 663
 664         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
 665         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 666 }
 667
 668 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
 669                           const struct pci_device_id *ent)
 670 {
 671         u32 op_mode, priv_level;
 672         struct qlcnic_hardware_context *ahw = adapter->ahw;
 673
 674         ahw->fw_hal_version = 2;
 675         qlcnic_get_func_no(adapter);
 676
 677         if (qlcnic_sriov_vf_check(adapter)) {
 678                 qlcnic_sriov_vf_set_ops(adapter);
 679                 return;
 680         }
 681
 682         /* Determine function privilege level */
 683         op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
 684         if (op_mode == QLC_83XX_DEFAULT_OPMODE)
 685                 priv_level = QLCNIC_MGMT_FUNC;
 686         else
 687                 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
 688                                                          ahw->pci_func);
 689
 690         if (priv_level == QLCNIC_NON_PRIV_FUNC) {
 691                 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
 692                 dev_info(&adapter->pdev->dev,
 693                          "HAL Version: %d Non Privileged function\n",
 694                          ahw->fw_hal_version);
 695                 adapter->nic_ops = &qlcnic_vf_ops;
 696         } else {
 697                 if (pci_find_ext_capability(adapter->pdev,
 698                                             PCI_EXT_CAP_ID_SRIOV))
 699                         set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
 700                 adapter->nic_ops = &qlcnic_83xx_ops;
 701         }
 702 }
 703
 704 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
 705                                         u32 data[]);
 706 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 707                                             u32 data[]);
 708
 709 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
 710                      struct qlcnic_cmd_args *cmd)
 711 {
 712         int i;
 713
 714         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 715                 return;
 716
 717         dev_info(&adapter->pdev->dev,
 718                  "Host MBX regs(%d)\n", cmd->req.num);
 719         for (i = 0; i < cmd->req.num; i++) {
 720                 if (i && !(i % 8))
 721                         pr_info("\n");
 722                 pr_info("%08x ", cmd->req.arg[i]);
 723         }
 724         pr_info("\n");
 725         dev_info(&adapter->pdev->dev,
 726                  "FW MBX regs(%d)\n", cmd->rsp.num);
 727         for (i = 0; i < cmd->rsp.num; i++) {
 728                 if (i && !(i % 8))
 729                         pr_info("\n");
 730                 pr_info("%08x ", cmd->rsp.arg[i]);
 731         }
 732         pr_info("\n");
 733 }
 734
 735 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
 736                                                 struct qlcnic_cmd_args *cmd)
 737 {
 738         struct qlcnic_hardware_context *ahw = adapter->ahw;
 739         int opcode = LSW(cmd->req.arg[0]);
 740         unsigned long max_loops;
 741
 742         max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
 743
 744         for (; max_loops; max_loops--) {
 745                 if (atomic_read(&cmd->rsp_status) ==
 746                     QLC_83XX_MBX_RESPONSE_ARRIVED)
 747                         return;
 748
 749                 udelay(1);
 750         }
 751
 752         dev_err(&adapter->pdev->dev,
 753                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 754                 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
 755         flush_workqueue(ahw->mailbox->work_q);
 756         return;
 757 }
 758
 759 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
 760                           struct qlcnic_cmd_args *cmd)
 761 {
 762         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 763         struct qlcnic_hardware_context *ahw = adapter->ahw;
 764         int cmd_type, err, opcode;
 765         unsigned long timeout;
 766
 767         if (!mbx)
 768                 return -EIO;
 769
 770         opcode = LSW(cmd->req.arg[0]);
 771         cmd_type = cmd->type;
 772         err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
 773         if (err) {
 774                 dev_err(&adapter->pdev->dev,
 775                         "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 776                         __func__, opcode, cmd->type, ahw->pci_func,
 777                         ahw->op_mode);
 778                 return err;
 779         }
 780
 781         switch (cmd_type) {
 782         case QLC_83XX_MBX_CMD_WAIT:
 783                 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
 784                         dev_err(&adapter->pdev->dev,
 785                                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 786                                 __func__, opcode, cmd_type, ahw->pci_func,
 787                                 ahw->op_mode);
 788                         flush_workqueue(mbx->work_q);
 789                 }
 790                 break;
 791         case QLC_83XX_MBX_CMD_NO_WAIT:
 792                 return 0;
 793         case QLC_83XX_MBX_CMD_BUSY_WAIT:
 794                 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
 795                 break;
 796         default:
 797                 dev_err(&adapter->pdev->dev,
 798                         "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 799                         __func__, opcode, cmd_type, ahw->pci_func,
 800                         ahw->op_mode);
 801                 qlcnic_83xx_detach_mailbox_work(adapter);
 802         }
 803
 804         return cmd->rsp_opcode;
 805 }
 806
 807 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
 808                                struct qlcnic_adapter *adapter, u32 type)
 809 {
 810         int i, size;
 811         u32 temp;
 812         const struct qlcnic_mailbox_metadata *mbx_tbl;
 813
 814         memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
 815         mbx_tbl = qlcnic_83xx_mbx_tbl;
 816         size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
 817         for (i = 0; i < size; i++) {
 818                 if (type == mbx_tbl[i].cmd) {
 819                         mbx->op_type = QLC_83XX_FW_MBX_CMD;
 820                         mbx->req.num = mbx_tbl[i].in_args;
 821                         mbx->rsp.num = mbx_tbl[i].out_args;
 822                         mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
 823                                                GFP_ATOMIC);
 824                         if (!mbx->req.arg)
 825                                 return -ENOMEM;
 826                         mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
 827                                                GFP_ATOMIC);
 828                         if (!mbx->rsp.arg) {
 829                                 kfree(mbx->req.arg);
 830                                 mbx->req.arg = NULL;
 831                                 return -ENOMEM;
 832                         }
 833                         memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
 834                         memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
 835                         temp = adapter->ahw->fw_hal_version << 29;
 836                         mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
 837                         mbx->cmd_op = type;
 838                         return 0;
 839                 }
 840         }
 841         return -EINVAL;
 842 }
 843
 844 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
 845 {
 846         struct qlcnic_adapter *adapter;
 847         struct qlcnic_cmd_args cmd;
 848         int i, err = 0;
 849
 850         adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
 851         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
 852         if (err)
 853                 return;
 854
 855         for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
 856                 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
 857
 858         err = qlcnic_issue_cmd(adapter, &cmd);
 859         if (err)
 860                 dev_info(&adapter->pdev->dev,
 861                          "%s: Mailbox IDC ACK failed.\n", __func__);
 862         qlcnic_free_mbx_args(&cmd);
 863 }
 864
 865 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 866                                             u32 data[])
 867 {
 868         dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
 869                 QLCNIC_MBX_RSP(data[0]));
 870         clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
 871         return;
 872 }
 873
 874 void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 875 {
 876         struct qlcnic_hardware_context *ahw = adapter->ahw;
 877         u32 event[QLC_83XX_MBX_AEN_CNT];
 878         int i;
 879
 880         for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 881                 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
 882
 883         switch (QLCNIC_MBX_RSP(event[0])) {
 884
 885         case QLCNIC_MBX_LINK_EVENT:
 886                 qlcnic_83xx_handle_link_aen(adapter, event);
 887                 break;
 888         case QLCNIC_MBX_COMP_EVENT:
 889                 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
 890                 break;
 891         case QLCNIC_MBX_REQUEST_EVENT:
 892                 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 893                         adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
 894                 queue_delayed_work(adapter->qlcnic_wq,
 895                                    &adapter->idc_aen_work, 0);
 896                 break;
 897         case QLCNIC_MBX_TIME_EXTEND_EVENT:
 898                 ahw->extend_lb_time = event[1] >> 8 & 0xf;
 899                 break;
 900         case QLCNIC_MBX_BC_EVENT:
 901                 qlcnic_sriov_handle_bc_event(adapter, event[1]);
 902                 break;
 903         case QLCNIC_MBX_SFP_INSERT_EVENT:
 904                 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
 905                          QLCNIC_MBX_RSP(event[0]));
 906                 break;
 907         case QLCNIC_MBX_SFP_REMOVE_EVENT:
 908                 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
 909                          QLCNIC_MBX_RSP(event[0]));
 910                 break;
 911         case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
 912                 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
 913                 break;
 914         default:
 915                 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
 916                         QLCNIC_MBX_RSP(event[0]));
 917                 break;
 918         }
 919
 920         QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
 921 }
 922
 923 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 924 {
 925         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 926         struct qlcnic_hardware_context *ahw = adapter->ahw;
 927         struct qlcnic_mailbox *mbx = ahw->mailbox;
 928         unsigned long flags;
 929
 930         spin_lock_irqsave(&mbx->aen_lock, flags);
 931         resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
 932         if (resp & QLCNIC_SET_OWNER) {
 933                 event = readl(QLCNIC_MBX_FW(ahw, 0));
 934                 if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 935                         __qlcnic_83xx_process_aen(adapter);
 936                 } else {
 937                         if (atomic_read(&mbx->rsp_status) != rsp_status)
 938                                 qlcnic_83xx_notify_mbx_response(mbx);
 939                 }
 940         }
 941         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 942 }
 943
 944 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
 945 {
 946         struct qlcnic_adapter *adapter;
 947
 948         adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
 949
 950         if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 951                 return;
 952
 953         qlcnic_83xx_process_aen(adapter);
 954         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
 955                            (HZ / 10));
 956 }
 957
 958 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
 959 {
 960         if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 961                 return;
 962
 963         INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
 964         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
 965 }
 966
 967 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
 968 {
 969         if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 970                 return;
 971         cancel_delayed_work_sync(&adapter->mbx_poll_work);
 972 }
 973
 974 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
 975 {
 976         int index, i, err, sds_mbx_size;
 977         u32 *buf, intrpt_id, intr_mask;
 978         u16 context_id;
 979         u8 num_sds;
 980         struct qlcnic_cmd_args cmd;
 981         struct qlcnic_host_sds_ring *sds;
 982         struct qlcnic_sds_mbx sds_mbx;
 983         struct qlcnic_add_rings_mbx_out *mbx_out;
 984         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
 985         struct qlcnic_hardware_context *ahw = adapter->ahw;
 986
 987         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
 988         context_id = recv_ctx->context_id;
 989         num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
 990         ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
 991                                     QLCNIC_CMD_ADD_RCV_RINGS);
 992         cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
 993
 994         /* set up status rings, mbx 2-81 */
 995         index = 2;
 996         for (i = 8; i < adapter->drv_sds_rings; i++) {
 997                 memset(&sds_mbx, 0, sds_mbx_size);
 998                 sds = &recv_ctx->sds_rings[i];
 999                 sds->consumer = 0;
1000                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1001                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1002                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1003                 sds_mbx.sds_ring_size = sds->num_desc;
1004
1005                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1006                         intrpt_id = ahw->intr_tbl[i].id;
1007                 else
1008                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1009
1010                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1011                         sds_mbx.intrpt_id = intrpt_id;
1012                 else
1013                         sds_mbx.intrpt_id = 0xffff;
1014                 sds_mbx.intrpt_val = 0;
1015                 buf = &cmd.req.arg[index];
1016                 memcpy(buf, &sds_mbx, sds_mbx_size);
1017                 index += sds_mbx_size / sizeof(u32);
1018         }
1019
1020         /* send the mailbox command */
1021         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1022         if (err) {
1023                 dev_err(&adapter->pdev->dev,
1024                         "Failed to add rings %d\n", err);
1025                 goto out;
1026         }
1027
1028         mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1029         index = 0;
1030         /* status descriptor ring */
1031         for (i = 8; i < adapter->drv_sds_rings; i++) {
1032                 sds = &recv_ctx->sds_rings[i];
1033                 sds->crb_sts_consumer = ahw->pci_base0 +
1034                                         mbx_out->host_csmr[index];
1035                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1036                         intr_mask = ahw->intr_tbl[i].src;
1037                 else
1038                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1039
1040                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1041                 index++;
1042         }
1043 out:
1044         qlcnic_free_mbx_args(&cmd);
1045         return err;
1046 }
1047
1048 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1049 {
1050         int err;
1051         u32 temp = 0;
1052         struct qlcnic_cmd_args cmd;
1053         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1054
1055         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1056                 return;
1057
1058         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1059                 cmd.req.arg[0] |= (0x3 << 29);
1060
1061         if (qlcnic_sriov_pf_check(adapter))
1062                 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1063
1064         cmd.req.arg[1] = recv_ctx->context_id | temp;
1065         err = qlcnic_issue_cmd(adapter, &cmd);
1066         if (err)
1067                 dev_err(&adapter->pdev->dev,
1068                         "Failed to destroy rx ctx in firmware\n");
1069
1070         recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1071         qlcnic_free_mbx_args(&cmd);
1072 }
1073
1074 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1075 {
1076         int i, err, index, sds_mbx_size, rds_mbx_size;
1077         u8 num_sds, num_rds;
1078         u32 *buf, intrpt_id, intr_mask, cap = 0;
1079         struct qlcnic_host_sds_ring *sds;
1080         struct qlcnic_host_rds_ring *rds;
1081         struct qlcnic_sds_mbx sds_mbx;
1082         struct qlcnic_rds_mbx rds_mbx;
1083         struct qlcnic_cmd_args cmd;
1084         struct qlcnic_rcv_mbx_out *mbx_out;
1085         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1086         struct qlcnic_hardware_context *ahw = adapter->ahw;
1087         num_rds = adapter->max_rds_rings;
1088
1089         if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1090                 num_sds = adapter->drv_sds_rings;
1091         else
1092                 num_sds = QLCNIC_MAX_SDS_RINGS;
1093
1094         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1095         rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1096         cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1097
1098         if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1099                 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1100
1101         /* set mailbox hdr and capabilities */
1102         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1103                                     QLCNIC_CMD_CREATE_RX_CTX);
1104         if (err)
1105                 return err;
1106
1107         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1108                 cmd.req.arg[0] |= (0x3 << 29);
1109
1110         cmd.req.arg[1] = cap;
1111         cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1112                          (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1113
1114         if (qlcnic_sriov_pf_check(adapter))
1115                 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1116                                                          &cmd.req.arg[6]);
1117         /* set up status rings, mbx 8-57/87 */
1118         index = QLC_83XX_HOST_SDS_MBX_IDX;
1119         for (i = 0; i < num_sds; i++) {
1120                 memset(&sds_mbx, 0, sds_mbx_size);
1121                 sds = &recv_ctx->sds_rings[i];
1122                 sds->consumer = 0;
1123                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1124                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1125                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1126                 sds_mbx.sds_ring_size = sds->num_desc;
1127                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1128                         intrpt_id = ahw->intr_tbl[i].id;
1129                 else
1130                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1131                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1132                         sds_mbx.intrpt_id = intrpt_id;
1133                 else
1134                         sds_mbx.intrpt_id = 0xffff;
1135                 sds_mbx.intrpt_val = 0;
1136                 buf = &cmd.req.arg[index];
1137                 memcpy(buf, &sds_mbx, sds_mbx_size);
1138                 index += sds_mbx_size / sizeof(u32);
1139         }
1140         /* set up receive rings, mbx 88-111/135 */
1141         index = QLCNIC_HOST_RDS_MBX_IDX;
1142         rds = &recv_ctx->rds_rings[0];
1143         rds->producer = 0;
1144         memset(&rds_mbx, 0, rds_mbx_size);
1145         rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1146         rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1147         rds_mbx.reg_ring_sz = rds->dma_size;
1148         rds_mbx.reg_ring_len = rds->num_desc;
1149         /* Jumbo ring */
1150         rds = &recv_ctx->rds_rings[1];
1151         rds->producer = 0;
1152         rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1153         rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1154         rds_mbx.jmb_ring_sz = rds->dma_size;
1155         rds_mbx.jmb_ring_len = rds->num_desc;
1156         buf = &cmd.req.arg[index];
1157         memcpy(buf, &rds_mbx, rds_mbx_size);
1158
1159         /* send the mailbox command */
1160         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1161         if (err) {
1162                 dev_err(&adapter->pdev->dev,
1163                         "Failed to create Rx ctx in firmware%d\n", err);
1164                 goto out;
1165         }
1166         mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1167         recv_ctx->context_id = mbx_out->ctx_id;
1168         recv_ctx->state = mbx_out->state;
1169         recv_ctx->virt_port = mbx_out->vport_id;
1170         dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1171                  recv_ctx->context_id, recv_ctx->state);
1172         /* Receive descriptor ring */
1173         /* Standard ring */
1174         rds = &recv_ctx->rds_rings[0];
1175         rds->crb_rcv_producer = ahw->pci_base0 +
1176                                 mbx_out->host_prod[0].reg_buf;
1177         /* Jumbo ring */
1178         rds = &recv_ctx->rds_rings[1];
1179         rds->crb_rcv_producer = ahw->pci_base0 +
1180                                 mbx_out->host_prod[0].jmb_buf;
1181         /* status descriptor ring */
1182         for (i = 0; i < num_sds; i++) {
1183                 sds = &recv_ctx->sds_rings[i];
1184                 sds->crb_sts_consumer = ahw->pci_base0 +
1185                                         mbx_out->host_csmr[i];
1186                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1187                         intr_mask = ahw->intr_tbl[i].src;
1188                 else
1189                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1190                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1191         }
1192
1193         if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1194                 err = qlcnic_83xx_add_rings(adapter);
1195 out:
1196         qlcnic_free_mbx_args(&cmd);
1197         return err;
1198 }
1199
1200 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1201                             struct qlcnic_host_tx_ring *tx_ring)
1202 {
1203         struct qlcnic_cmd_args cmd;
1204         u32 temp = 0;
1205
1206         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1207                 return;
1208
1209         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1210                 cmd.req.arg[0] |= (0x3 << 29);
1211
1212         if (qlcnic_sriov_pf_check(adapter))
1213                 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1214
1215         cmd.req.arg[1] = tx_ring->ctx_id | temp;
1216         if (qlcnic_issue_cmd(adapter, &cmd))
1217                 dev_err(&adapter->pdev->dev,
1218                         "Failed to destroy tx ctx in firmware\n");
1219         qlcnic_free_mbx_args(&cmd);
1220 }
1221
1222 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1223                               struct qlcnic_host_tx_ring *tx, int ring)
1224 {
1225         int err;
1226         u16 msix_id;
1227         u32 *buf, intr_mask, temp = 0;
1228         struct qlcnic_cmd_args cmd;
1229         struct qlcnic_tx_mbx mbx;
1230         struct qlcnic_tx_mbx_out *mbx_out;
1231         struct qlcnic_hardware_context *ahw = adapter->ahw;
1232         u32 msix_vector;
1233
1234         /* Reset host resources */
1235         tx->producer = 0;
1236         tx->sw_consumer = 0;
1237         *(tx->hw_consumer) = 0;
1238
1239         memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1240
1241         /* setup mailbox inbox registerss */
1242         mbx.phys_addr_low = LSD(tx->phys_addr);
1243         mbx.phys_addr_high = MSD(tx->phys_addr);
1244         mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1245         mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1246         mbx.size = tx->num_desc;
1247         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1248                 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1249                         msix_vector = adapter->drv_sds_rings + ring;
1250                 else
1251                         msix_vector = adapter->drv_sds_rings - 1;
1252                 msix_id = ahw->intr_tbl[msix_vector].id;
1253         } else {
1254                 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1255         }
1256
1257         if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1258                 mbx.intr_id = msix_id;
1259         else
1260                 mbx.intr_id = 0xffff;
1261         mbx.src = 0;
1262
1263         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1264         if (err)
1265                 return err;
1266
1267         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1268                 cmd.req.arg[0] |= (0x3 << 29);
1269
1270         if (qlcnic_sriov_pf_check(adapter))
1271                 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1272
1273         cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1274         cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1275
1276         buf = &cmd.req.arg[6];
1277         memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1278         /* send the mailbox command*/
1279         err = qlcnic_issue_cmd(adapter, &cmd);
1280         if (err) {
1281                 dev_err(&adapter->pdev->dev,
1282                         "Failed to create Tx ctx in firmware 0x%x\n", err);
1283                 goto out;
1284         }
1285         mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1286         tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1287         tx->ctx_id = mbx_out->ctx_id;
1288         if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1289             !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1290                 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1291                 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1292         }
1293         dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1294                  tx->ctx_id, mbx_out->state);
1295 out:
1296         qlcnic_free_mbx_args(&cmd);
1297         return err;
1298 }
1299
1300 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1301                                       u8 num_sds_ring)
1302 {
1303         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1304         struct qlcnic_host_sds_ring *sds_ring;
1305         struct qlcnic_host_rds_ring *rds_ring;
1306         u16 adapter_state = adapter->is_up;
1307         u8 ring;
1308         int ret;
1309
1310         netif_device_detach(netdev);
1311
1312         if (netif_running(netdev))
1313                 __qlcnic_down(adapter, netdev);
1314
1315         qlcnic_detach(adapter);
1316
1317         adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1318         adapter->ahw->diag_test = test;
1319         adapter->ahw->linkup = 0;
1320
1321         ret = qlcnic_attach(adapter);
1322         if (ret) {
1323                 netif_device_attach(netdev);
1324                 return ret;
1325         }
1326
1327         ret = qlcnic_fw_create_ctx(adapter);
1328         if (ret) {
1329                 qlcnic_detach(adapter);
1330                 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1331                         adapter->drv_sds_rings = num_sds_ring;
1332                         qlcnic_attach(adapter);
1333                 }
1334                 netif_device_attach(netdev);
1335                 return ret;
1336         }
1337
1338         for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1339                 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1340                 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1341         }
1342
1343         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1344                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1345                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1346                         qlcnic_83xx_enable_intr(adapter, sds_ring);
1347                 }
1348         }
1349
1350         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1351                 adapter->ahw->loopback_state = 0;
1352                 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1353         }
1354
1355         set_bit(__QLCNIC_DEV_UP, &adapter->state);
1356         return 0;
1357 }
1358
1359 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1360                                       u8 drv_sds_rings)
1361 {
1362         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1363         struct qlcnic_host_sds_ring *sds_ring;
1364         int ring;
1365
1366         clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1367         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1368                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1369                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1370                         if (adapter->flags & QLCNIC_MSIX_ENABLED)
1371                                 qlcnic_83xx_disable_intr(adapter, sds_ring);
1372                 }
1373         }
1374
1375         qlcnic_fw_destroy_ctx(adapter);
1376         qlcnic_detach(adapter);
1377
1378         adapter->ahw->diag_test = 0;
1379         adapter->drv_sds_rings = drv_sds_rings;
1380
1381         if (qlcnic_attach(adapter))
1382                 goto out;
1383
1384         if (netif_running(netdev))
1385                 __qlcnic_up(adapter, netdev);
1386
1387 out:
1388         netif_device_attach(netdev);
1389 }
1390
1391 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1392                            u32 beacon)
1393 {
1394         struct qlcnic_cmd_args cmd;
1395         u32 mbx_in;
1396         int i, status = 0;
1397
1398         if (state) {
1399                 /* Get LED configuration */
1400                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1401                                                QLCNIC_CMD_GET_LED_CONFIG);
1402                 if (status)
1403                         return status;
1404
1405                 status = qlcnic_issue_cmd(adapter, &cmd);
1406                 if (status) {
1407                         dev_err(&adapter->pdev->dev,
1408                                 "Get led config failed.\n");
1409                         goto mbx_err;
1410                 } else {
1411                         for (i = 0; i < 4; i++)
1412                                 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1413                 }
1414                 qlcnic_free_mbx_args(&cmd);
1415                 /* Set LED Configuration */
1416                 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1417                           LSW(QLC_83XX_LED_CONFIG);
1418                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1419                                                QLCNIC_CMD_SET_LED_CONFIG);
1420                 if (status)
1421                         return status;
1422
1423                 cmd.req.arg[1] = mbx_in;
1424                 cmd.req.arg[2] = mbx_in;
1425                 cmd.req.arg[3] = mbx_in;
1426                 if (beacon)
1427                         cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1428                 status = qlcnic_issue_cmd(adapter, &cmd);
1429                 if (status) {
1430                         dev_err(&adapter->pdev->dev,
1431                                 "Set led config failed.\n");
1432                 }
1433 mbx_err:
1434                 qlcnic_free_mbx_args(&cmd);
1435                 return status;
1436
1437         } else {
1438                 /* Restoring default LED configuration */
1439                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1440                                                QLCNIC_CMD_SET_LED_CONFIG);
1441                 if (status)
1442                         return status;
1443
1444                 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1445                 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1446                 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1447                 if (beacon)
1448                         cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1449                 status = qlcnic_issue_cmd(adapter, &cmd);
1450                 if (status)
1451                         dev_err(&adapter->pdev->dev,
1452                                 "Restoring led config failed.\n");
1453                 qlcnic_free_mbx_args(&cmd);
1454                 return status;
1455         }
1456 }
1457
1458 int  qlcnic_83xx_set_led(struct net_device *netdev,
1459                          enum ethtool_phys_id_state state)
1460 {
1461         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1462         int err = -EIO, active = 1;
1463
1464         if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1465                 netdev_warn(netdev,
1466                             "LED test is not supported in non-privileged mode\n");
1467                 return -EOPNOTSUPP;
1468         }
1469
1470         switch (state) {
1471         case ETHTOOL_ID_ACTIVE:
1472                 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1473                         return -EBUSY;
1474
1475                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1476                         break;
1477
1478                 err = qlcnic_83xx_config_led(adapter, active, 0);
1479                 if (err)
1480                         netdev_err(netdev, "Failed to set LED blink state\n");
1481                 break;
1482         case ETHTOOL_ID_INACTIVE:
1483                 active = 0;
1484
1485                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1486                         break;
1487
1488                 err = qlcnic_83xx_config_led(adapter, active, 0);
1489                 if (err)
1490                         netdev_err(netdev, "Failed to reset LED blink state\n");
1491                 break;
1492
1493         default:
1494                 return -EINVAL;
1495         }
1496
1497         if (!active || err)
1498                 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1499
1500         return err;
1501 }
1502
1503 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable)
1504 {
1505         struct qlcnic_cmd_args cmd;
1506         int status;
1507
1508         if (qlcnic_sriov_vf_check(adapter))
1509                 return;
1510
1511         if (enable)
1512                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1513                                                QLCNIC_CMD_INIT_NIC_FUNC);
1514         else
1515                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1516                                                QLCNIC_CMD_STOP_NIC_FUNC);
1517
1518         if (status)
1519                 return;
1520
1521         cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES;
1522
1523         if (adapter->dcb)
1524                 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1525
1526         status = qlcnic_issue_cmd(adapter, &cmd);
1527         if (status)
1528                 dev_err(&adapter->pdev->dev,
1529                         "Failed to %s in NIC IDC function event.\n",
1530                         (enable ? "register" : "unregister"));
1531
1532         qlcnic_free_mbx_args(&cmd);
1533 }
1534
1535 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1536 {
1537         struct qlcnic_cmd_args cmd;
1538         int err;
1539
1540         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1541         if (err)
1542                 return err;
1543
1544         cmd.req.arg[1] = adapter->ahw->port_config;
1545         err = qlcnic_issue_cmd(adapter, &cmd);
1546         if (err)
1547                 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1548         qlcnic_free_mbx_args(&cmd);
1549         return err;
1550 }
1551
1552 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1553 {
1554         struct qlcnic_cmd_args cmd;
1555         int err;
1556
1557         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1558         if (err)
1559                 return err;
1560
1561         err = qlcnic_issue_cmd(adapter, &cmd);
1562         if (err)
1563                 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1564         else
1565                 adapter->ahw->port_config = cmd.rsp.arg[1];
1566         qlcnic_free_mbx_args(&cmd);
1567         return err;
1568 }
1569
1570 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1571 {
1572         int err;
1573         u32 temp;
1574         struct qlcnic_cmd_args cmd;
1575
1576         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1577         if (err)
1578                 return err;
1579
1580         temp = adapter->recv_ctx->context_id << 16;
1581         cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1582         err = qlcnic_issue_cmd(adapter, &cmd);
1583         if (err)
1584                 dev_info(&adapter->pdev->dev,
1585                          "Setup linkevent mailbox failed\n");
1586         qlcnic_free_mbx_args(&cmd);
1587         return err;
1588 }
1589
1590 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1591                                                  u32 *interface_id)
1592 {
1593         if (qlcnic_sriov_pf_check(adapter)) {
1594                 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1595         } else {
1596                 if (!qlcnic_sriov_vf_check(adapter))
1597                         *interface_id = adapter->recv_ctx->context_id << 16;
1598         }
1599 }
1600
1601 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1602 {
1603         struct qlcnic_cmd_args *cmd = NULL;
1604         u32 temp = 0;
1605         int err;
1606
1607         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1608                 return -EIO;
1609
1610         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1611         if (!cmd)
1612                 return -ENOMEM;
1613
1614         err = qlcnic_alloc_mbx_args(cmd, adapter,
1615                                     QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1616         if (err)
1617                 goto out;
1618
1619         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1620         qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1621         cmd->req.arg[1] = mode | temp;
1622         err = qlcnic_issue_cmd(adapter, cmd);
1623         if (!err)
1624                 return err;
1625
1626         qlcnic_free_mbx_args(cmd);
1627
1628 out:
1629         kfree(cmd);
1630         return err;
1631 }
1632
1633 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1634 {
1635         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1636         struct qlcnic_hardware_context *ahw = adapter->ahw;
1637         u8 drv_sds_rings = adapter->drv_sds_rings;
1638         u8 drv_tx_rings = adapter->drv_tx_rings;
1639         int ret = 0, loop = 0;
1640
1641         if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1642                 netdev_warn(netdev,
1643                             "Loopback test not supported in non privileged mode\n");
1644                 return -ENOTSUPP;
1645         }
1646
1647         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1648                 netdev_info(netdev, "Device is resetting\n");
1649                 return -EBUSY;
1650         }
1651
1652         if (qlcnic_get_diag_lock(adapter)) {
1653                 netdev_info(netdev, "Device is in diagnostics mode\n");
1654                 return -EBUSY;
1655         }
1656
1657         netdev_info(netdev, "%s loopback test in progress\n",
1658                     mode == QLCNIC_ILB_MODE ? "internal" : "external");
1659
1660         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1661                                          drv_sds_rings);
1662         if (ret)
1663                 goto fail_diag_alloc;
1664
1665         ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1666         if (ret)
1667                 goto free_diag_res;
1668
1669         /* Poll for link up event before running traffic */
1670         do {
1671                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1672
1673                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1674                         netdev_info(netdev,
1675                                     "Device is resetting, free LB test resources\n");
1676                         ret = -EBUSY;
1677                         goto free_diag_res;
1678                 }
1679                 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1680                         netdev_info(netdev,
1681                                     "Firmware didn't sent link up event to loopback request\n");
1682                         ret = -ETIMEDOUT;
1683                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1684                         goto free_diag_res;
1685                 }
1686         } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1687
1688         /* Make sure carrier is off and queue is stopped during loopback */
1689         if (netif_running(netdev)) {
1690                 netif_carrier_off(netdev);
1691                 netif_tx_stop_all_queues(netdev);
1692         }
1693
1694         ret = qlcnic_do_lb_test(adapter, mode);
1695
1696         qlcnic_83xx_clear_lb_mode(adapter, mode);
1697
1698 free_diag_res:
1699         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1700
1701 fail_diag_alloc:
1702         adapter->drv_sds_rings = drv_sds_rings;
1703         adapter->drv_tx_rings = drv_tx_rings;
1704         qlcnic_release_diag_lock(adapter);
1705         return ret;
1706 }
1707
1708 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1709                                              u32 *max_wait_count)
1710 {
1711         struct qlcnic_hardware_context *ahw = adapter->ahw;
1712         int temp;
1713
1714         netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1715                     ahw->extend_lb_time);
1716         temp = ahw->extend_lb_time * 1000;
1717         *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1718         ahw->extend_lb_time = 0;
1719 }
1720
1721 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1722 {
1723         struct qlcnic_hardware_context *ahw = adapter->ahw;
1724         struct net_device *netdev = adapter->netdev;
1725         u32 config, max_wait_count;
1726         int status = 0, loop = 0;
1727
1728         ahw->extend_lb_time = 0;
1729         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1730         status = qlcnic_83xx_get_port_config(adapter);
1731         if (status)
1732                 return status;
1733
1734         config = ahw->port_config;
1735
1736         /* Check if port is already in loopback mode */
1737         if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1738             (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1739                 netdev_err(netdev,
1740                            "Port already in Loopback mode.\n");
1741                 return -EINPROGRESS;
1742         }
1743
1744         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1745
1746         if (mode == QLCNIC_ILB_MODE)
1747                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1748         if (mode == QLCNIC_ELB_MODE)
1749                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1750
1751         status = qlcnic_83xx_set_port_config(adapter);
1752         if (status) {
1753                 netdev_err(netdev,
1754                            "Failed to Set Loopback Mode = 0x%x.\n",
1755                            ahw->port_config);
1756                 ahw->port_config = config;
1757                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1758                 return status;
1759         }
1760
1761         /* Wait for Link and IDC Completion AEN */
1762         do {
1763                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1764
1765                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1766                         netdev_info(netdev,
1767                                     "Device is resetting, free LB test resources\n");
1768                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1769                         return -EBUSY;
1770                 }
1771
1772                 if (ahw->extend_lb_time)
1773                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1774                                                          &max_wait_count);
1775
1776                 if (loop++ > max_wait_count) {
1777                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1778                                    __func__);
1779                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1780                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1781                         return -ETIMEDOUT;
1782                 }
1783         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1784
1785         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1786                                   QLCNIC_MAC_ADD);
1787         return status;
1788 }
1789
1790 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1791 {
1792         struct qlcnic_hardware_context *ahw = adapter->ahw;
1793         u32 config = ahw->port_config, max_wait_count;
1794         struct net_device *netdev = adapter->netdev;
1795         int status = 0, loop = 0;
1796
1797         ahw->extend_lb_time = 0;
1798         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1799         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1800         if (mode == QLCNIC_ILB_MODE)
1801                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1802         if (mode == QLCNIC_ELB_MODE)
1803                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1804
1805         status = qlcnic_83xx_set_port_config(adapter);
1806         if (status) {
1807                 netdev_err(netdev,
1808                            "Failed to Clear Loopback Mode = 0x%x.\n",
1809                            ahw->port_config);
1810                 ahw->port_config = config;
1811                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1812                 return status;
1813         }
1814
1815         /* Wait for Link and IDC Completion AEN */
1816         do {
1817                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1818
1819                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1820                         netdev_info(netdev,
1821                                     "Device is resetting, free LB test resources\n");
1822                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1823                         return -EBUSY;
1824                 }
1825
1826                 if (ahw->extend_lb_time)
1827                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1828                                                          &max_wait_count);
1829
1830                 if (loop++ > max_wait_count) {
1831                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1832                                    __func__);
1833                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1834                         return -ETIMEDOUT;
1835                 }
1836         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1837
1838         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1839                                   QLCNIC_MAC_DEL);
1840         return status;
1841 }
1842
1843 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1844                                                 u32 *interface_id)
1845 {
1846         if (qlcnic_sriov_pf_check(adapter)) {
1847                 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1848         } else {
1849                 if (!qlcnic_sriov_vf_check(adapter))
1850                         *interface_id = adapter->recv_ctx->context_id << 16;
1851         }
1852 }
1853
1854 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1855                                int mode)
1856 {
1857         int err;
1858         u32 temp = 0, temp_ip;
1859         struct qlcnic_cmd_args cmd;
1860
1861         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1862                                     QLCNIC_CMD_CONFIGURE_IP_ADDR);
1863         if (err)
1864                 return;
1865
1866         qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1867
1868         if (mode == QLCNIC_IP_UP)
1869                 cmd.req.arg[1] = 1 | temp;
1870         else
1871                 cmd.req.arg[1] = 2 | temp;
1872
1873         /*
1874          * Adapter needs IP address in network byte order.
1875          * But hardware mailbox registers go through writel(), hence IP address
1876          * gets swapped on big endian architecture.
1877          * To negate swapping of writel() on big endian architecture
1878          * use swab32(value).
1879          */
1880
1881         temp_ip = swab32(ntohl(ip));
1882         memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1883         err = qlcnic_issue_cmd(adapter, &cmd);
1884         if (err != QLCNIC_RCODE_SUCCESS)
1885                 dev_err(&adapter->netdev->dev,
1886                         "could not notify %s IP 0x%x request\n",
1887                         (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1888
1889         qlcnic_free_mbx_args(&cmd);
1890 }
1891
1892 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1893 {
1894         int err;
1895         u32 temp, arg1;
1896         struct qlcnic_cmd_args cmd;
1897         int lro_bit_mask;
1898
1899         lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1900
1901         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1902                 return 0;
1903
1904         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1905         if (err)
1906                 return err;
1907
1908         temp = adapter->recv_ctx->context_id << 16;
1909         arg1 = lro_bit_mask | temp;
1910         cmd.req.arg[1] = arg1;
1911
1912         err = qlcnic_issue_cmd(adapter, &cmd);
1913         if (err)
1914                 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1915         qlcnic_free_mbx_args(&cmd);
1916
1917         return err;
1918 }
1919
1920 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1921 {
1922         int err;
1923         u32 word;
1924         struct qlcnic_cmd_args cmd;
1925         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1926                             0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1927                             0x255b0ec26d5a56daULL };
1928
1929         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1930         if (err)
1931                 return err;
1932         /*
1933          * RSS request:
1934          * bits 3-0: Rsvd
1935          *      5-4: hash_type_ipv4
1936          *      7-6: hash_type_ipv6
1937          *        8: enable
1938          *        9: use indirection table
1939          *    16-31: indirection table mask
1940          */
1941         word =  ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1942                 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1943                 ((u32)(enable & 0x1) << 8) |
1944                 ((0x7ULL) << 16);
1945         cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1946         cmd.req.arg[2] = word;
1947         memcpy(&cmd.req.arg[4], key, sizeof(key));
1948
1949         err = qlcnic_issue_cmd(adapter, &cmd);
1950
1951         if (err)
1952                 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1953         qlcnic_free_mbx_args(&cmd);
1954
1955         return err;
1956
1957 }
1958
1959 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1960                                                  u32 *interface_id)
1961 {
1962         if (qlcnic_sriov_pf_check(adapter)) {
1963                 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1964         } else {
1965                 if (!qlcnic_sriov_vf_check(adapter))
1966                         *interface_id = adapter->recv_ctx->context_id << 16;
1967         }
1968 }
1969
1970 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1971                                    u16 vlan_id, u8 op)
1972 {
1973         struct qlcnic_cmd_args *cmd = NULL;
1974         struct qlcnic_macvlan_mbx mv;
1975         u32 *buf, temp = 0;
1976         int err;
1977
1978         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1979                 return -EIO;
1980
1981         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1982         if (!cmd)
1983                 return -ENOMEM;
1984
1985         err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
1986         if (err)
1987                 goto out;
1988
1989         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1990
1991         if (vlan_id)
1992                 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
1993                      QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
1994
1995         cmd->req.arg[1] = op | (1 << 8);
1996         qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
1997         cmd->req.arg[1] |= temp;
1998         mv.vlan = vlan_id;
1999         mv.mac_addr0 = addr[0];
2000         mv.mac_addr1 = addr[1];
2001         mv.mac_addr2 = addr[2];
2002         mv.mac_addr3 = addr[3];
2003         mv.mac_addr4 = addr[4];
2004         mv.mac_addr5 = addr[5];
2005         buf = &cmd->req.arg[2];
2006         memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2007         err = qlcnic_issue_cmd(adapter, cmd);
2008         if (!err)
2009                 return err;
2010
2011         qlcnic_free_mbx_args(cmd);
2012 out:
2013         kfree(cmd);
2014         return err;
2015 }
2016
2017 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2018                                   u16 vlan_id)
2019 {
2020         u8 mac[ETH_ALEN];
2021         memcpy(&mac, addr, ETH_ALEN);
2022         qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2023 }
2024
2025 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2026                                u8 type, struct qlcnic_cmd_args *cmd)
2027 {
2028         switch (type) {
2029         case QLCNIC_SET_STATION_MAC:
2030         case QLCNIC_SET_FAC_DEF_MAC:
2031                 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2032                 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2033                 break;
2034         }
2035         cmd->req.arg[1] = type;
2036 }
2037
2038 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2039                                 u8 function)
2040 {
2041         int err, i;
2042         struct qlcnic_cmd_args cmd;
2043         u32 mac_low, mac_high;
2044
2045         function = 0;
2046         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2047         if (err)
2048                 return err;
2049
2050         qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2051         err = qlcnic_issue_cmd(adapter, &cmd);
2052
2053         if (err == QLCNIC_RCODE_SUCCESS) {
2054                 mac_low = cmd.rsp.arg[1];
2055                 mac_high = cmd.rsp.arg[2];
2056
2057                 for (i = 0; i < 2; i++)
2058                         mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2059                 for (i = 2; i < 6; i++)
2060                         mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2061         } else {
2062                 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2063                         err);
2064                 err = -EIO;
2065         }
2066         qlcnic_free_mbx_args(&cmd);
2067         return err;
2068 }
2069
2070 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2071 {
2072         int err;
2073         u16 temp;
2074         struct qlcnic_cmd_args cmd;
2075         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2076
2077         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2078                 return;
2079
2080         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2081         if (err)
2082                 return;
2083
2084         if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2085                 temp = adapter->recv_ctx->context_id;
2086                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2087                 temp = coal->rx_time_us;
2088                 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2089         } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2090                 temp = adapter->tx_ring->ctx_id;
2091                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2092                 temp = coal->tx_time_us;
2093                 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2094         }
2095         cmd.req.arg[3] = coal->flag;
2096         err = qlcnic_issue_cmd(adapter, &cmd);
2097         if (err != QLCNIC_RCODE_SUCCESS)
2098                 dev_info(&adapter->pdev->dev,
2099                          "Failed to send interrupt coalescence parameters\n");
2100         qlcnic_free_mbx_args(&cmd);
2101 }
2102
2103 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2104                                         u32 data[])
2105 {
2106         struct qlcnic_hardware_context *ahw = adapter->ahw;
2107         u8 link_status, duplex;
2108         /* link speed */
2109         link_status = LSB(data[3]) & 1;
2110         if (link_status) {
2111                 ahw->link_speed = MSW(data[2]);
2112                 duplex = LSB(MSW(data[3]));
2113                 if (duplex)
2114                         ahw->link_duplex = DUPLEX_FULL;
2115                 else
2116                         ahw->link_duplex = DUPLEX_HALF;
2117         } else {
2118                 ahw->link_speed = SPEED_UNKNOWN;
2119                 ahw->link_duplex = DUPLEX_UNKNOWN;
2120         }
2121
2122         ahw->link_autoneg = MSB(MSW(data[3]));
2123         ahw->module_type = MSB(LSW(data[3]));
2124         ahw->has_link_events = 1;
2125         qlcnic_advert_link_change(adapter, link_status);
2126 }
2127
2128 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2129 {
2130         struct qlcnic_adapter *adapter = data;
2131         struct qlcnic_mailbox *mbx;
2132         u32 mask, resp, event;
2133         unsigned long flags;
2134
2135         mbx = adapter->ahw->mailbox;
2136         spin_lock_irqsave(&mbx->aen_lock, flags);
2137         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2138         if (!(resp & QLCNIC_SET_OWNER))
2139                 goto out;
2140
2141         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2142         if (event &  QLCNIC_MBX_ASYNC_EVENT)
2143                 __qlcnic_83xx_process_aen(adapter);
2144         else
2145                 qlcnic_83xx_notify_mbx_response(mbx);
2146
2147 out:
2148         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2149         writel(0, adapter->ahw->pci_base0 + mask);
2150         spin_unlock_irqrestore(&mbx->aen_lock, flags);
2151         return IRQ_HANDLED;
2152 }
2153
2154 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
2155 {
2156         int err = -EIO;
2157         struct qlcnic_cmd_args cmd;
2158
2159         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2160                 dev_err(&adapter->pdev->dev,
2161                         "%s: Error, invoked by non management func\n",
2162                         __func__);
2163                 return err;
2164         }
2165
2166         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
2167         if (err)
2168                 return err;
2169
2170         cmd.req.arg[1] = (port & 0xf) | BIT_4;
2171         err = qlcnic_issue_cmd(adapter, &cmd);
2172
2173         if (err != QLCNIC_RCODE_SUCCESS) {
2174                 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
2175                         err);
2176                 err = -EIO;
2177         }
2178         qlcnic_free_mbx_args(&cmd);
2179
2180         return err;
2181
2182 }
2183
2184 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2185                              struct qlcnic_info *nic)
2186 {
2187         int i, err = -EIO;
2188         struct qlcnic_cmd_args cmd;
2189
2190         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2191                 dev_err(&adapter->pdev->dev,
2192                         "%s: Error, invoked by non management func\n",
2193                         __func__);
2194                 return err;
2195         }
2196
2197         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2198         if (err)
2199                 return err;
2200
2201         cmd.req.arg[1] = (nic->pci_func << 16);
2202         cmd.req.arg[2] = 0x1 << 16;
2203         cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2204         cmd.req.arg[4] = nic->capabilities;
2205         cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2206         cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2207         cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2208         for (i = 8; i < 32; i++)
2209                 cmd.req.arg[i] = 0;
2210
2211         err = qlcnic_issue_cmd(adapter, &cmd);
2212
2213         if (err != QLCNIC_RCODE_SUCCESS) {
2214                 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2215                         err);
2216                 err = -EIO;
2217         }
2218
2219         qlcnic_free_mbx_args(&cmd);
2220
2221         return err;
2222 }
2223
2224 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2225                              struct qlcnic_info *npar_info, u8 func_id)
2226 {
2227         int err;
2228         u32 temp;
2229         u8 op = 0;
2230         struct qlcnic_cmd_args cmd;
2231         struct qlcnic_hardware_context *ahw = adapter->ahw;
2232
2233         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2234         if (err)
2235                 return err;
2236
2237         if (func_id != ahw->pci_func) {
2238                 temp = func_id << 16;
2239                 cmd.req.arg[1] = op | BIT_31 | temp;
2240         } else {
2241                 cmd.req.arg[1] = ahw->pci_func << 16;
2242         }
2243         err = qlcnic_issue_cmd(adapter, &cmd);
2244         if (err) {
2245                 dev_info(&adapter->pdev->dev,
2246                          "Failed to get nic info %d\n", err);
2247                 goto out;
2248         }
2249
2250         npar_info->op_type = cmd.rsp.arg[1];
2251         npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2252         npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2253         npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2254         npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2255         npar_info->capabilities = cmd.rsp.arg[4];
2256         npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2257         npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2258         npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2259         npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2260         npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2261         npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2262         if (cmd.rsp.arg[8] & 0x1)
2263                 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2264         if (cmd.rsp.arg[8] & 0x10000) {
2265                 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2266                 npar_info->max_linkspeed_reg_offset = temp;
2267         }
2268
2269         memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2270                sizeof(ahw->extra_capability));
2271
2272 out:
2273         qlcnic_free_mbx_args(&cmd);
2274         return err;
2275 }
2276
2277 int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type,
2278                              u16 *nic, u16 *fcoe, u16 *iscsi)
2279 {
2280         struct device *dev = &adapter->pdev->dev;
2281         int err = 0;
2282
2283         switch (type) {
2284         case QLCNIC_TYPE_NIC:
2285                 (*nic)++;
2286                 break;
2287         case QLCNIC_TYPE_FCOE:
2288                 (*fcoe)++;
2289                 break;
2290         case QLCNIC_TYPE_ISCSI:
2291                 (*iscsi)++;
2292                 break;
2293         default:
2294                 dev_err(dev, "%s: Unknown PCI type[%x]\n",
2295                         __func__, type);
2296                 err = -EIO;
2297         }
2298
2299         return err;
2300 }
2301
2302 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2303                              struct qlcnic_pci_info *pci_info)
2304 {
2305         struct qlcnic_hardware_context *ahw = adapter->ahw;
2306         struct device *dev = &adapter->pdev->dev;
2307         u16 nic = 0, fcoe = 0, iscsi = 0;
2308         struct qlcnic_cmd_args cmd;
2309         int i, err = 0, j = 0;
2310         u32 temp;
2311
2312         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2313         if (err)
2314                 return err;
2315
2316         err = qlcnic_issue_cmd(adapter, &cmd);
2317
2318         ahw->total_nic_func = 0;
2319         if (err == QLCNIC_RCODE_SUCCESS) {
2320                 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2321                 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) {
2322                         pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2323                         pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2324                         i++;
2325                         if (!pci_info->active) {
2326                                 i += QLC_SKIP_INACTIVE_PCI_REGS;
2327                                 continue;
2328                         }
2329                         pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2330                         err = qlcnic_get_pci_func_type(adapter, pci_info->type,
2331                                                        &nic, &fcoe, &iscsi);
2332                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2333                         pci_info->default_port = temp;
2334                         i++;
2335                         pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2336                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2337                         pci_info->tx_max_bw = temp;
2338                         i = i + 2;
2339                         memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2340                         i++;
2341                         memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2342                         i = i + 3;
2343                 }
2344         } else {
2345                 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2346                 err = -EIO;
2347         }
2348
2349         ahw->total_nic_func = nic;
2350         ahw->total_pci_func = nic + fcoe + iscsi;
2351         if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
2352                 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
2353                         __func__, ahw->total_nic_func, ahw->total_pci_func);
2354                 err = -EIO;
2355         }
2356         qlcnic_free_mbx_args(&cmd);
2357
2358         return err;
2359 }
2360
2361 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2362 {
2363         int i, index, err;
2364         u8 max_ints;
2365         u32 val, temp, type;
2366         struct qlcnic_cmd_args cmd;
2367
2368         max_ints = adapter->ahw->num_msix - 1;
2369         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2370         if (err)
2371                 return err;
2372
2373         cmd.req.arg[1] = max_ints;
2374
2375         if (qlcnic_sriov_vf_check(adapter))
2376                 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2377
2378         for (i = 0, index = 2; i < max_ints; i++) {
2379                 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2380                 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2381                 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2382                         val |= (adapter->ahw->intr_tbl[i].id << 16);
2383                 cmd.req.arg[index++] = val;
2384         }
2385         err = qlcnic_issue_cmd(adapter, &cmd);
2386         if (err) {
2387                 dev_err(&adapter->pdev->dev,
2388                         "Failed to configure interrupts 0x%x\n", err);
2389                 goto out;
2390         }
2391
2392         max_ints = cmd.rsp.arg[1];
2393         for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2394                 val = cmd.rsp.arg[index];
2395                 if (LSB(val)) {
2396                         dev_info(&adapter->pdev->dev,
2397                                  "Can't configure interrupt %d\n",
2398                                  adapter->ahw->intr_tbl[i].id);
2399                         continue;
2400                 }
2401                 if (op_type) {
2402                         adapter->ahw->intr_tbl[i].id = MSW(val);
2403                         adapter->ahw->intr_tbl[i].enabled = 1;
2404                         temp = cmd.rsp.arg[index + 1];
2405                         adapter->ahw->intr_tbl[i].src = temp;
2406                 } else {
2407                         adapter->ahw->intr_tbl[i].id = i;
2408                         adapter->ahw->intr_tbl[i].enabled = 0;
2409                         adapter->ahw->intr_tbl[i].src = 0;
2410                 }
2411         }
2412 out:
2413         qlcnic_free_mbx_args(&cmd);
2414         return err;
2415 }
2416
2417 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2418 {
2419         int id, timeout = 0;
2420         u32 status = 0;
2421
2422         while (status == 0) {
2423                 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2424                 if (status)
2425                         break;
2426
2427                 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2428                         id = QLC_SHARED_REG_RD32(adapter,
2429                                                  QLCNIC_FLASH_LOCK_OWNER);
2430                         dev_err(&adapter->pdev->dev,
2431                                 "%s: failed, lock held by %d\n", __func__, id);
2432                         return -EIO;
2433                 }
2434                 usleep_range(1000, 2000);
2435         }
2436
2437         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2438         return 0;
2439 }
2440
2441 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2442 {
2443         QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2444         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2445 }
2446
2447 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2448                                       u32 flash_addr, u8 *p_data,
2449                                       int count)
2450 {
2451         u32 word, range, flash_offset, addr = flash_addr, ret;
2452         ulong indirect_add, direct_window;
2453         int i, err = 0;
2454
2455         flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2456         if (addr & 0x3) {
2457                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2458                 return -EIO;
2459         }
2460
2461         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2462                                      (addr));
2463
2464         range = flash_offset + (count * sizeof(u32));
2465         /* Check if data is spread across multiple sectors */
2466         if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2467
2468                 /* Multi sector read */
2469                 for (i = 0; i < count; i++) {
2470                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2471                         ret = QLCRD32(adapter, indirect_add, &err);
2472                         if (err == -EIO)
2473                                 return err;
2474
2475                         word = ret;
2476                         *(u32 *)p_data  = word;
2477                         p_data = p_data + 4;
2478                         addr = addr + 4;
2479                         flash_offset = flash_offset + 4;
2480
2481                         if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2482                                 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2483                                 /* This write is needed once for each sector */
2484                                 qlcnic_83xx_wrt_reg_indirect(adapter,
2485                                                              direct_window,
2486                                                              (addr));
2487                                 flash_offset = 0;
2488                         }
2489                 }
2490         } else {
2491                 /* Single sector read */
2492                 for (i = 0; i < count; i++) {
2493                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2494                         ret = QLCRD32(adapter, indirect_add, &err);
2495                         if (err == -EIO)
2496                                 return err;
2497
2498                         word = ret;
2499                         *(u32 *)p_data  = word;
2500                         p_data = p_data + 4;
2501                         addr = addr + 4;
2502                 }
2503         }
2504
2505         return 0;
2506 }
2507
2508 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2509 {
2510         u32 status;
2511         int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2512         int err = 0;
2513
2514         do {
2515                 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2516                 if (err == -EIO)
2517                         return err;
2518
2519                 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2520                     QLC_83XX_FLASH_STATUS_READY)
2521                         break;
2522
2523                 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2524         } while (--retries);
2525
2526         if (!retries)
2527                 return -EIO;
2528
2529         return 0;
2530 }
2531
2532 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2533 {
2534         int ret;
2535         u32 cmd;
2536         cmd = adapter->ahw->fdt.write_statusreg_cmd;
2537         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2538                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2539         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2540                                      adapter->ahw->fdt.write_enable_bits);
2541         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2542                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2543         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2544         if (ret)
2545                 return -EIO;
2546
2547         return 0;
2548 }
2549
2550 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2551 {
2552         int ret;
2553
2554         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2555                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2556                                      adapter->ahw->fdt.write_statusreg_cmd));
2557         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2558                                      adapter->ahw->fdt.write_disable_bits);
2559         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2560                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2561         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2562         if (ret)
2563                 return -EIO;
2564
2565         return 0;
2566 }
2567
2568 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2569 {
2570         int ret, err = 0;
2571         u32 mfg_id;
2572
2573         if (qlcnic_83xx_lock_flash(adapter))
2574                 return -EIO;
2575
2576         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2577                                      QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2578         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2579                                      QLC_83XX_FLASH_READ_CTRL);
2580         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2581         if (ret) {
2582                 qlcnic_83xx_unlock_flash(adapter);
2583                 return -EIO;
2584         }
2585
2586         mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2587         if (err == -EIO) {
2588                 qlcnic_83xx_unlock_flash(adapter);
2589                 return err;
2590         }
2591
2592         adapter->flash_mfg_id = (mfg_id & 0xFF);
2593         qlcnic_83xx_unlock_flash(adapter);
2594
2595         return 0;
2596 }
2597
2598 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2599 {
2600         int count, fdt_size, ret = 0;
2601
2602         fdt_size = sizeof(struct qlcnic_fdt);
2603         count = fdt_size / sizeof(u32);
2604
2605         if (qlcnic_83xx_lock_flash(adapter))
2606                 return -EIO;
2607
2608         memset(&adapter->ahw->fdt, 0, fdt_size);
2609         ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2610                                                 (u8 *)&adapter->ahw->fdt,
2611                                                 count);
2612
2613         qlcnic_83xx_unlock_flash(adapter);
2614         return ret;
2615 }
2616
2617 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2618                                    u32 sector_start_addr)
2619 {
2620         u32 reversed_addr, addr1, addr2, cmd;
2621         int ret = -EIO;
2622
2623         if (qlcnic_83xx_lock_flash(adapter) != 0)
2624                 return -EIO;
2625
2626         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2627                 ret = qlcnic_83xx_enable_flash_write(adapter);
2628                 if (ret) {
2629                         qlcnic_83xx_unlock_flash(adapter);
2630                         dev_err(&adapter->pdev->dev,
2631                                 "%s failed at %d\n",
2632                                 __func__, __LINE__);
2633                         return ret;
2634                 }
2635         }
2636
2637         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2638         if (ret) {
2639                 qlcnic_83xx_unlock_flash(adapter);
2640                 dev_err(&adapter->pdev->dev,
2641                         "%s: failed at %d\n", __func__, __LINE__);
2642                 return -EIO;
2643         }
2644
2645         addr1 = (sector_start_addr & 0xFF) << 16;
2646         addr2 = (sector_start_addr & 0xFF0000) >> 16;
2647         reversed_addr = addr1 | addr2;
2648
2649         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2650                                      reversed_addr);
2651         cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2652         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2653                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2654         else
2655                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2656                                              QLC_83XX_FLASH_OEM_ERASE_SIG);
2657         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2658                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2659
2660         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2661         if (ret) {
2662                 qlcnic_83xx_unlock_flash(adapter);
2663                 dev_err(&adapter->pdev->dev,
2664                         "%s: failed at %d\n", __func__, __LINE__);
2665                 return -EIO;
2666         }
2667
2668         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2669                 ret = qlcnic_83xx_disable_flash_write(adapter);
2670                 if (ret) {
2671                         qlcnic_83xx_unlock_flash(adapter);
2672                         dev_err(&adapter->pdev->dev,
2673                                 "%s: failed at %d\n", __func__, __LINE__);
2674                         return ret;
2675                 }
2676         }
2677
2678         qlcnic_83xx_unlock_flash(adapter);
2679
2680         return 0;
2681 }
2682
2683 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2684                               u32 *p_data)
2685 {
2686         int ret = -EIO;
2687         u32 addr1 = 0x00800000 | (addr >> 2);
2688
2689         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2690         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2691         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2692                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2693         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2694         if (ret) {
2695                 dev_err(&adapter->pdev->dev,
2696                         "%s: failed at %d\n", __func__, __LINE__);
2697                 return -EIO;
2698         }
2699
2700         return 0;
2701 }
2702
2703 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2704                                  u32 *p_data, int count)
2705 {
2706         u32 temp;
2707         int ret = -EIO, err = 0;
2708
2709         if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2710             (count > QLC_83XX_FLASH_WRITE_MAX)) {
2711                 dev_err(&adapter->pdev->dev,
2712                         "%s: Invalid word count\n", __func__);
2713                 return -EIO;
2714         }
2715
2716         temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2717         if (err == -EIO)
2718                 return err;
2719
2720         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2721                                      (temp | QLC_83XX_FLASH_SPI_CTRL));
2722         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2723                                      QLC_83XX_FLASH_ADDR_TEMP_VAL);
2724
2725         /* First DWORD write */
2726         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2727         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2728                                      QLC_83XX_FLASH_FIRST_MS_PATTERN);
2729         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2730         if (ret) {
2731                 dev_err(&adapter->pdev->dev,
2732                         "%s: failed at %d\n", __func__, __LINE__);
2733                 return -EIO;
2734         }
2735
2736         count--;
2737         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2738                                      QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2739         /* Second to N-1 DWORD writes */
2740         while (count != 1) {
2741                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2742                                              *p_data++);
2743                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2744                                              QLC_83XX_FLASH_SECOND_MS_PATTERN);
2745                 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2746                 if (ret) {
2747                         dev_err(&adapter->pdev->dev,
2748                                 "%s: failed at %d\n", __func__, __LINE__);
2749                         return -EIO;
2750                 }
2751                 count--;
2752         }
2753
2754         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2755                                      QLC_83XX_FLASH_ADDR_TEMP_VAL |
2756                                      (addr >> 2));
2757         /* Last DWORD write */
2758         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2759         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2760                                      QLC_83XX_FLASH_LAST_MS_PATTERN);
2761         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2762         if (ret) {
2763                 dev_err(&adapter->pdev->dev,
2764                         "%s: failed at %d\n", __func__, __LINE__);
2765                 return -EIO;
2766         }
2767
2768         ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2769         if (err == -EIO)
2770                 return err;
2771
2772         if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2773                 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2774                         __func__, __LINE__);
2775                 /* Operation failed, clear error bit */
2776                 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2777                 if (err == -EIO)
2778                         return err;
2779
2780                 qlcnic_83xx_wrt_reg_indirect(adapter,
2781                                              QLC_83XX_FLASH_SPI_CONTROL,
2782                                              (temp | QLC_83XX_FLASH_SPI_CTRL));
2783         }
2784
2785         return 0;
2786 }
2787
2788 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2789 {
2790         u32 val, id;
2791
2792         val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2793
2794         /* Check if recovery need to be performed by the calling function */
2795         if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2796                 val = val & ~0x3F;
2797                 val = val | ((adapter->portnum << 2) |
2798                              QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2799                 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2800                 dev_info(&adapter->pdev->dev,
2801                          "%s: lock recovery initiated\n", __func__);
2802                 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2803                 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2804                 id = ((val >> 2) & 0xF);
2805                 if (id == adapter->portnum) {
2806                         val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2807                         val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2808                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2809                         /* Force release the lock */
2810                         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2811                         /* Clear recovery bits */
2812                         val = val & ~0x3F;
2813                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2814                         dev_info(&adapter->pdev->dev,
2815                                  "%s: lock recovery completed\n", __func__);
2816                 } else {
2817                         dev_info(&adapter->pdev->dev,
2818                                  "%s: func %d to resume lock recovery process\n",
2819                                  __func__, id);
2820                 }
2821         } else {
2822                 dev_info(&adapter->pdev->dev,
2823                          "%s: lock recovery initiated by other functions\n",
2824                          __func__);
2825         }
2826 }
2827
2828 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2829 {
2830         u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2831         int max_attempt = 0;
2832
2833         while (status == 0) {
2834                 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2835                 if (status)
2836                         break;
2837
2838                 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2839                 i++;
2840
2841                 if (i == 1)
2842                         temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2843
2844                 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2845                         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2846                         if (val == temp) {
2847                                 id = val & 0xFF;
2848                                 dev_info(&adapter->pdev->dev,
2849                                          "%s: lock to be recovered from %d\n",
2850                                          __func__, id);
2851                                 qlcnic_83xx_recover_driver_lock(adapter);
2852                                 i = 0;
2853                                 max_attempt++;
2854                         } else {
2855                                 dev_err(&adapter->pdev->dev,
2856                                         "%s: failed to get lock\n", __func__);
2857                                 return -EIO;
2858                         }
2859                 }
2860
2861                 /* Force exit from while loop after few attempts */
2862                 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2863                         dev_err(&adapter->pdev->dev,
2864                                 "%s: failed to get lock\n", __func__);
2865                         return -EIO;
2866                 }
2867         }
2868
2869         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2870         lock_alive_counter = val >> 8;
2871         lock_alive_counter++;
2872         val = lock_alive_counter << 8 | adapter->portnum;
2873         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2874
2875         return 0;
2876 }
2877
2878 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2879 {
2880         u32 val, lock_alive_counter, id;
2881
2882         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2883         id = val & 0xFF;
2884         lock_alive_counter = val >> 8;
2885
2886         if (id != adapter->portnum)
2887                 dev_err(&adapter->pdev->dev,
2888                         "%s:Warning func %d is unlocking lock owned by %d\n",
2889                         __func__, adapter->portnum, id);
2890
2891         val = (lock_alive_counter << 8) | 0xFF;
2892         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2893         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2894 }
2895
2896 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2897                                 u32 *data, u32 count)
2898 {
2899         int i, j, ret = 0;
2900         u32 temp;
2901         int err = 0;
2902
2903         /* Check alignment */
2904         if (addr & 0xF)
2905                 return -EIO;
2906
2907         mutex_lock(&adapter->ahw->mem_lock);
2908         qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2909
2910         for (i = 0; i < count; i++, addr += 16) {
2911                 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2912                                      QLCNIC_ADDR_QDR_NET_MAX)) ||
2913                       (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2914                                      QLCNIC_ADDR_DDR_NET_MAX)))) {
2915                         mutex_unlock(&adapter->ahw->mem_lock);
2916                         return -EIO;
2917                 }
2918
2919                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2920                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2921                                              *data++);
2922                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2923                                              *data++);
2924                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2925                                              *data++);
2926                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2927                                              *data++);
2928                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2929                                              QLCNIC_TA_WRITE_ENABLE);
2930                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2931                                              QLCNIC_TA_WRITE_START);
2932
2933                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2934                         temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err);
2935                         if (err == -EIO) {
2936                                 mutex_unlock(&adapter->ahw->mem_lock);
2937                                 return err;
2938                         }
2939
2940                         if ((temp & TA_CTL_BUSY) == 0)
2941                                 break;
2942                 }
2943
2944                 /* Status check failure */
2945                 if (j >= MAX_CTL_CHECK) {
2946                         printk_ratelimited(KERN_WARNING
2947                                            "MS memory write failed\n");
2948                         mutex_unlock(&adapter->ahw->mem_lock);
2949                         return -EIO;
2950                 }
2951         }
2952
2953         mutex_unlock(&adapter->ahw->mem_lock);
2954
2955         return ret;
2956 }
2957
2958 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2959                              u8 *p_data, int count)
2960 {
2961         u32 word, addr = flash_addr, ret;
2962         ulong  indirect_addr;
2963         int i, err = 0;
2964
2965         if (qlcnic_83xx_lock_flash(adapter) != 0)
2966                 return -EIO;
2967
2968         if (addr & 0x3) {
2969                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2970                 qlcnic_83xx_unlock_flash(adapter);
2971                 return -EIO;
2972         }
2973
2974         for (i = 0; i < count; i++) {
2975                 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2976                                                  QLC_83XX_FLASH_DIRECT_WINDOW,
2977                                                  (addr))) {
2978                         qlcnic_83xx_unlock_flash(adapter);
2979                         return -EIO;
2980                 }
2981
2982                 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2983                 ret = QLCRD32(adapter, indirect_addr, &err);
2984                 if (err == -EIO)
2985                         return err;
2986
2987                 word = ret;
2988                 *(u32 *)p_data  = word;
2989                 p_data = p_data + 4;
2990                 addr = addr + 4;
2991         }
2992
2993         qlcnic_83xx_unlock_flash(adapter);
2994
2995         return 0;
2996 }
2997
2998 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2999 {
3000         u8 pci_func;
3001         int err;
3002         u32 config = 0, state;
3003         struct qlcnic_cmd_args cmd;
3004         struct qlcnic_hardware_context *ahw = adapter->ahw;
3005
3006         if (qlcnic_sriov_vf_check(adapter))
3007                 pci_func = adapter->portnum;
3008         else
3009                 pci_func = ahw->pci_func;
3010
3011         state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
3012         if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
3013                 dev_info(&adapter->pdev->dev, "link state down\n");
3014                 return config;
3015         }
3016
3017         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3018         if (err)
3019                 return err;
3020
3021         err = qlcnic_issue_cmd(adapter, &cmd);
3022         if (err) {
3023                 dev_info(&adapter->pdev->dev,
3024                          "Get Link Status Command failed: 0x%x\n", err);
3025                 goto out;
3026         } else {
3027                 config = cmd.rsp.arg[1];
3028                 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3029                 case QLC_83XX_10M_LINK:
3030                         ahw->link_speed = SPEED_10;
3031                         break;
3032                 case QLC_83XX_100M_LINK:
3033                         ahw->link_speed = SPEED_100;
3034                         break;
3035                 case QLC_83XX_1G_LINK:
3036                         ahw->link_speed = SPEED_1000;
3037                         break;
3038                 case QLC_83XX_10G_LINK:
3039                         ahw->link_speed = SPEED_10000;
3040                         break;
3041                 default:
3042                         ahw->link_speed = 0;
3043                         break;
3044                 }
3045                 config = cmd.rsp.arg[3];
3046                 if (QLC_83XX_SFP_PRESENT(config)) {
3047                         switch (ahw->module_type) {
3048                         case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
3049                         case LINKEVENT_MODULE_OPTICAL_SRLR:
3050                         case LINKEVENT_MODULE_OPTICAL_LRM:
3051                         case LINKEVENT_MODULE_OPTICAL_SFP_1G:
3052                                 ahw->supported_type = PORT_FIBRE;
3053                                 break;
3054                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
3055                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
3056                         case LINKEVENT_MODULE_TWINAX:
3057                                 ahw->supported_type = PORT_TP;
3058                                 break;
3059                         default:
3060                                 ahw->supported_type = PORT_OTHER;
3061                         }
3062                 }
3063                 if (config & 1)
3064                         err = 1;
3065         }
3066 out:
3067         qlcnic_free_mbx_args(&cmd);
3068         return config;
3069 }
3070
3071 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3072                              struct ethtool_cmd *ecmd)
3073 {
3074         u32 config = 0;
3075         int status = 0;
3076         struct qlcnic_hardware_context *ahw = adapter->ahw;
3077
3078         if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3079                 /* Get port configuration info */
3080                 status = qlcnic_83xx_get_port_info(adapter);
3081                 /* Get Link Status related info */
3082                 config = qlcnic_83xx_test_link(adapter);
3083                 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3084         }
3085
3086         /* hard code until there is a way to get it from flash */
3087         ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3088
3089         if (netif_running(adapter->netdev) && ahw->has_link_events) {
3090                 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3091                 ecmd->duplex = ahw->link_duplex;
3092                 ecmd->autoneg = ahw->link_autoneg;
3093         } else {
3094                 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3095                 ecmd->duplex = DUPLEX_UNKNOWN;
3096                 ecmd->autoneg = AUTONEG_DISABLE;
3097         }
3098
3099         if (ahw->port_type == QLCNIC_XGBE) {
3100                 ecmd->supported = SUPPORTED_10000baseT_Full;
3101                 ecmd->advertising = ADVERTISED_10000baseT_Full;
3102         } else {
3103                 ecmd->supported = (SUPPORTED_10baseT_Half |
3104                                    SUPPORTED_10baseT_Full |
3105                                    SUPPORTED_100baseT_Half |
3106                                    SUPPORTED_100baseT_Full |
3107                                    SUPPORTED_1000baseT_Half |
3108                                    SUPPORTED_1000baseT_Full);
3109                 ecmd->advertising = (ADVERTISED_100baseT_Half |
3110                                      ADVERTISED_100baseT_Full |
3111                                      ADVERTISED_1000baseT_Half |
3112                                      ADVERTISED_1000baseT_Full);
3113         }
3114
3115         switch (ahw->supported_type) {
3116         case PORT_FIBRE:
3117                 ecmd->supported |= SUPPORTED_FIBRE;
3118                 ecmd->advertising |= ADVERTISED_FIBRE;
3119                 ecmd->port = PORT_FIBRE;
3120                 ecmd->transceiver = XCVR_EXTERNAL;
3121                 break;
3122         case PORT_TP:
3123                 ecmd->supported |= SUPPORTED_TP;
3124                 ecmd->advertising |= ADVERTISED_TP;
3125                 ecmd->port = PORT_TP;
3126                 ecmd->transceiver = XCVR_INTERNAL;
3127                 break;
3128         default:
3129                 ecmd->supported |= SUPPORTED_FIBRE;
3130                 ecmd->advertising |= ADVERTISED_FIBRE;
3131                 ecmd->port = PORT_OTHER;
3132                 ecmd->transceiver = XCVR_EXTERNAL;
3133                 break;
3134         }
3135         ecmd->phy_address = ahw->physical_port;
3136         return status;
3137 }
3138
3139 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3140                              struct ethtool_cmd *ecmd)
3141 {
3142         int status = 0;
3143         u32 config = adapter->ahw->port_config;
3144
3145         if (ecmd->autoneg)
3146                 adapter->ahw->port_config |= BIT_15;
3147
3148         switch (ethtool_cmd_speed(ecmd)) {
3149         case SPEED_10:
3150                 adapter->ahw->port_config |= BIT_8;
3151                 break;
3152         case SPEED_100:
3153                 adapter->ahw->port_config |= BIT_9;
3154                 break;
3155         case SPEED_1000:
3156                 adapter->ahw->port_config |= BIT_10;
3157                 break;
3158         case SPEED_10000:
3159                 adapter->ahw->port_config |= BIT_11;
3160                 break;
3161         default:
3162                 return -EINVAL;
3163         }
3164
3165         status = qlcnic_83xx_set_port_config(adapter);
3166         if (status) {
3167                 dev_info(&adapter->pdev->dev,
3168                          "Failed to Set Link Speed and autoneg.\n");
3169                 adapter->ahw->port_config = config;
3170         }
3171         return status;
3172 }
3173
3174 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3175                                           u64 *data, int index)
3176 {
3177         u32 low, hi;
3178         u64 val;
3179
3180         low = cmd->rsp.arg[index];
3181         hi = cmd->rsp.arg[index + 1];
3182         val = (((u64) low) | (((u64) hi) << 32));
3183         *data++ = val;
3184         return data;
3185 }
3186
3187 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3188                                    struct qlcnic_cmd_args *cmd, u64 *data,
3189                                    int type, int *ret)
3190 {
3191         int err, k, total_regs;
3192
3193         *ret = 0;
3194         err = qlcnic_issue_cmd(adapter, cmd);
3195         if (err != QLCNIC_RCODE_SUCCESS) {
3196                 dev_info(&adapter->pdev->dev,
3197                          "Error in get statistics mailbox command\n");
3198                 *ret = -EIO;
3199                 return data;
3200         }
3201         total_regs = cmd->rsp.num;
3202         switch (type) {
3203         case QLC_83XX_STAT_MAC:
3204                 /* fill in MAC tx counters */
3205                 for (k = 2; k < 28; k += 2)
3206                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3207                 /* skip 24 bytes of reserved area */
3208                 /* fill in MAC rx counters */
3209                 for (k += 6; k < 60; k += 2)
3210                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3211                 /* skip 24 bytes of reserved area */
3212                 /* fill in MAC rx frame stats */
3213                 for (k += 6; k < 80; k += 2)
3214                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3215                 /* fill in eSwitch stats */
3216                 for (; k < total_regs; k += 2)
3217                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3218                 break;
3219         case QLC_83XX_STAT_RX:
3220                 for (k = 2; k < 8; k += 2)
3221                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3222                 /* skip 8 bytes of reserved data */
3223                 for (k += 2; k < 24; k += 2)
3224                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3225                 /* skip 8 bytes containing RE1FBQ error data */
3226                 for (k += 2; k < total_regs; k += 2)
3227                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3228                 break;
3229         case QLC_83XX_STAT_TX:
3230                 for (k = 2; k < 10; k += 2)
3231                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3232                 /* skip 8 bytes of reserved data */
3233                 for (k += 2; k < total_regs; k += 2)
3234                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3235                 break;
3236         default:
3237                 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3238                 *ret = -EIO;
3239         }
3240         return data;
3241 }
3242
3243 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3244 {
3245         struct qlcnic_cmd_args cmd;
3246         struct net_device *netdev = adapter->netdev;
3247         int ret = 0;
3248
3249         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3250         if (ret)
3251                 return;
3252         /* Get Tx stats */
3253         cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3254         cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3255         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3256                                       QLC_83XX_STAT_TX, &ret);
3257         if (ret) {
3258                 netdev_err(netdev, "Error getting Tx stats\n");
3259                 goto out;
3260         }
3261         /* Get MAC stats */
3262         cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3263         cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3264         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3265         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3266                                       QLC_83XX_STAT_MAC, &ret);
3267         if (ret) {
3268                 netdev_err(netdev, "Error getting MAC stats\n");
3269                 goto out;
3270         }
3271         /* Get Rx stats */
3272         cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3273         cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3274         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3275         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3276                                       QLC_83XX_STAT_RX, &ret);
3277         if (ret)
3278                 netdev_err(netdev, "Error getting Rx stats\n");
3279 out:
3280         qlcnic_free_mbx_args(&cmd);
3281 }
3282
3283 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3284 {
3285         u32 major, minor, sub;
3286
3287         major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3288         minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3289         sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3290
3291         if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3292                 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3293                          __func__);
3294                 return 1;
3295         }
3296         return 0;
3297 }
3298
3299 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3300 {
3301         return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3302                 sizeof(*adapter->ahw->ext_reg_tbl)) +
3303                 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3304                 sizeof(*adapter->ahw->reg_tbl));
3305 }
3306
3307 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3308 {
3309         int i, j = 0;
3310
3311         for (i = QLCNIC_DEV_INFO_SIZE + 1;
3312              j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3313                 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3314
3315         for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3316                 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3317         return i;
3318 }
3319
3320 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3321 {
3322         struct qlcnic_adapter *adapter = netdev_priv(netdev);
3323         struct qlcnic_hardware_context *ahw = adapter->ahw;
3324         struct qlcnic_cmd_args cmd;
3325         u8 val, drv_sds_rings = adapter->drv_sds_rings;
3326         u8 drv_tx_rings = adapter->drv_tx_rings;
3327         u32 data;
3328         u16 intrpt_id, id;
3329         int ret;
3330
3331         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3332                 netdev_info(netdev, "Device is resetting\n");
3333                 return -EBUSY;
3334         }
3335
3336         if (qlcnic_get_diag_lock(adapter)) {
3337                 netdev_info(netdev, "Device in diagnostics mode\n");
3338                 return -EBUSY;
3339         }
3340
3341         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3342                                          drv_sds_rings);
3343         if (ret)
3344                 goto fail_diag_irq;
3345
3346         ahw->diag_cnt = 0;
3347         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3348         if (ret)
3349                 goto fail_diag_irq;
3350
3351         if (adapter->flags & QLCNIC_MSIX_ENABLED)
3352                 intrpt_id = ahw->intr_tbl[0].id;
3353         else
3354                 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3355
3356         cmd.req.arg[1] = 1;
3357         cmd.req.arg[2] = intrpt_id;
3358         cmd.req.arg[3] = BIT_0;
3359
3360         ret = qlcnic_issue_cmd(adapter, &cmd);
3361         data = cmd.rsp.arg[2];
3362         id = LSW(data);
3363         val = LSB(MSW(data));
3364         if (id != intrpt_id)
3365                 dev_info(&adapter->pdev->dev,
3366                          "Interrupt generated: 0x%x, requested:0x%x\n",
3367                          id, intrpt_id);
3368         if (val)
3369                 dev_err(&adapter->pdev->dev,
3370                          "Interrupt test error: 0x%x\n", val);
3371         if (ret)
3372                 goto done;
3373
3374         msleep(20);
3375         ret = !ahw->diag_cnt;
3376
3377 done:
3378         qlcnic_free_mbx_args(&cmd);
3379         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3380
3381 fail_diag_irq:
3382         adapter->drv_sds_rings = drv_sds_rings;
3383         adapter->drv_tx_rings = drv_tx_rings;
3384         qlcnic_release_diag_lock(adapter);
3385         return ret;
3386 }
3387
3388 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3389                                 struct ethtool_pauseparam *pause)
3390 {
3391         struct qlcnic_hardware_context *ahw = adapter->ahw;
3392         int status = 0;
3393         u32 config;
3394
3395         status = qlcnic_83xx_get_port_config(adapter);
3396         if (status) {
3397                 dev_err(&adapter->pdev->dev,
3398                         "%s: Get Pause Config failed\n", __func__);
3399                 return;
3400         }
3401         config = ahw->port_config;
3402         if (config & QLC_83XX_CFG_STD_PAUSE) {
3403                 switch (MSW(config)) {
3404                 case QLC_83XX_TX_PAUSE:
3405                         pause->tx_pause = 1;
3406                         break;
3407                 case QLC_83XX_RX_PAUSE:
3408                         pause->rx_pause = 1;
3409                         break;
3410                 case QLC_83XX_TX_RX_PAUSE:
3411                 default:
3412                         /* Backward compatibility for existing
3413                          * flash definitions
3414                          */
3415                         pause->tx_pause = 1;
3416                         pause->rx_pause = 1;
3417                 }
3418         }
3419
3420         if (QLC_83XX_AUTONEG(config))
3421                 pause->autoneg = 1;
3422 }
3423
3424 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3425                                struct ethtool_pauseparam *pause)
3426 {
3427         struct qlcnic_hardware_context *ahw = adapter->ahw;
3428         int status = 0;
3429         u32 config;
3430
3431         status = qlcnic_83xx_get_port_config(adapter);
3432         if (status) {
3433                 dev_err(&adapter->pdev->dev,
3434                         "%s: Get Pause Config failed.\n", __func__);
3435                 return status;
3436         }
3437         config = ahw->port_config;
3438
3439         if (ahw->port_type == QLCNIC_GBE) {
3440                 if (pause->autoneg)
3441                         ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3442                 if (!pause->autoneg)
3443                         ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3444         } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3445                 return -EOPNOTSUPP;
3446         }
3447
3448         if (!(config & QLC_83XX_CFG_STD_PAUSE))
3449                 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3450
3451         if (pause->rx_pause && pause->tx_pause) {
3452                 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3453         } else if (pause->rx_pause && !pause->tx_pause) {
3454                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3455                 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3456         } else if (pause->tx_pause && !pause->rx_pause) {
3457                 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3458                 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3459         } else if (!pause->rx_pause && !pause->tx_pause) {
3460                 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3461                                       QLC_83XX_CFG_STD_PAUSE);
3462         }
3463         status = qlcnic_83xx_set_port_config(adapter);
3464         if (status) {
3465                 dev_err(&adapter->pdev->dev,
3466                         "%s: Set Pause Config failed.\n", __func__);
3467                 ahw->port_config = config;
3468         }
3469         return status;
3470 }
3471
3472 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3473 {
3474         int ret, err = 0;
3475         u32 temp;
3476
3477         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3478                                      QLC_83XX_FLASH_OEM_READ_SIG);
3479         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3480                                      QLC_83XX_FLASH_READ_CTRL);
3481         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3482         if (ret)
3483                 return -EIO;
3484
3485         temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3486         if (err == -EIO)
3487                 return err;
3488
3489         return temp & 0xFF;
3490 }
3491
3492 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3493 {
3494         int status;
3495
3496         status = qlcnic_83xx_read_flash_status_reg(adapter);
3497         if (status == -EIO) {
3498                 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3499                          __func__);
3500                 return 1;
3501         }
3502         return 0;
3503 }
3504
3505 int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3506 {
3507         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3508         struct net_device *netdev = adapter->netdev;
3509         int retval;
3510
3511         netif_device_detach(netdev);
3512         qlcnic_cancel_idc_work(adapter);
3513
3514         if (netif_running(netdev))
3515                 qlcnic_down(adapter, netdev);
3516
3517         qlcnic_83xx_disable_mbx_intr(adapter);
3518         cancel_delayed_work_sync(&adapter->idc_aen_work);
3519
3520         retval = pci_save_state(pdev);
3521         if (retval)
3522                 return retval;
3523
3524         return 0;
3525 }
3526
3527 int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3528 {
3529         struct qlcnic_hardware_context *ahw = adapter->ahw;
3530         struct qlc_83xx_idc *idc = &ahw->idc;
3531         int err = 0;
3532
3533         err = qlcnic_83xx_idc_init(adapter);
3534         if (err)
3535                 return err;
3536
3537         if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3538                 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3539                         qlcnic_83xx_set_vnic_opmode(adapter);
3540                 } else {
3541                         err = qlcnic_83xx_check_vnic_state(adapter);
3542                         if (err)
3543                                 return err;
3544                 }
3545         }
3546
3547         err = qlcnic_83xx_idc_reattach_driver(adapter);
3548         if (err)
3549                 return err;
3550
3551         qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3552                              idc->delay);
3553         return err;
3554 }
3555
3556 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3557 {
3558         reinit_completion(&mbx->completion);
3559         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3560 }
3561
3562 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3563 {
3564         if (!mbx)
3565                 return;
3566
3567         destroy_workqueue(mbx->work_q);
3568         kfree(mbx);
3569 }
3570
3571 static inline void
3572 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3573                                   struct qlcnic_cmd_args *cmd)
3574 {
3575         atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3576
3577         if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3578                 qlcnic_free_mbx_args(cmd);
3579                 kfree(cmd);
3580                 return;
3581         }
3582         complete(&cmd->completion);
3583 }
3584
3585 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3586 {
3587         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3588         struct list_head *head = &mbx->cmd_q;
3589         struct qlcnic_cmd_args *cmd = NULL;
3590
3591         spin_lock(&mbx->queue_lock);
3592
3593         while (!list_empty(head)) {
3594                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3595                 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3596                          __func__, cmd->cmd_op);
3597                 list_del(&cmd->list);
3598                 mbx->num_cmds--;
3599                 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3600         }
3601
3602         spin_unlock(&mbx->queue_lock);
3603 }
3604
3605 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3606 {
3607         struct qlcnic_hardware_context *ahw = adapter->ahw;
3608         struct qlcnic_mailbox *mbx = ahw->mailbox;
3609         u32 host_mbx_ctrl;
3610
3611         if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3612                 return -EBUSY;
3613
3614         host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3615         if (host_mbx_ctrl) {
3616                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3617                 ahw->idc.collect_dump = 1;
3618                 return -EIO;
3619         }
3620
3621         return 0;
3622 }
3623
3624 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3625                                               u8 issue_cmd)
3626 {
3627         if (issue_cmd)
3628                 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3629         else
3630                 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3631 }
3632
3633 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3634                                         struct qlcnic_cmd_args *cmd)
3635 {
3636         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3637
3638         spin_lock(&mbx->queue_lock);
3639
3640         list_del(&cmd->list);
3641         mbx->num_cmds--;
3642
3643         spin_unlock(&mbx->queue_lock);
3644
3645         qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3646 }
3647
3648 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3649                                        struct qlcnic_cmd_args *cmd)
3650 {
3651         u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3652         struct qlcnic_hardware_context *ahw = adapter->ahw;
3653         int i, j;
3654
3655         if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3656                 mbx_cmd = cmd->req.arg[0];
3657                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3658                 for (i = 1; i < cmd->req.num; i++)
3659                         writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3660         } else {
3661                 fw_hal_version = ahw->fw_hal_version;
3662                 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3663                 total_size = cmd->pay_size + hdr_size;
3664                 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3665                 mbx_cmd = tmp | fw_hal_version << 29;
3666                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3667
3668                 /* Back channel specific operations bits */
3669                 mbx_cmd = 0x1 | 1 << 4;
3670
3671                 if (qlcnic_sriov_pf_check(adapter))
3672                         mbx_cmd |= cmd->func_num << 5;
3673
3674                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3675
3676                 for (i = 2, j = 0; j < hdr_size; i++, j++)
3677                         writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3678                 for (j = 0; j < cmd->pay_size; j++, i++)
3679                         writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3680         }
3681 }
3682
3683 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3684 {
3685         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3686
3687         if (!mbx)
3688                 return;
3689
3690         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3691         complete(&mbx->completion);
3692         cancel_work_sync(&mbx->work);
3693         flush_workqueue(mbx->work_q);
3694         qlcnic_83xx_flush_mbx_queue(adapter);
3695 }
3696
3697 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3698                                        struct qlcnic_cmd_args *cmd,
3699                                        unsigned long *timeout)
3700 {
3701         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3702
3703         if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3704                 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3705                 init_completion(&cmd->completion);
3706                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3707
3708                 spin_lock(&mbx->queue_lock);
3709
3710                 list_add_tail(&cmd->list, &mbx->cmd_q);
3711                 mbx->num_cmds++;
3712                 cmd->total_cmds = mbx->num_cmds;
3713                 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3714                 queue_work(mbx->work_q, &mbx->work);
3715
3716                 spin_unlock(&mbx->queue_lock);
3717
3718                 return 0;
3719         }
3720
3721         return -EBUSY;
3722 }
3723
3724 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3725                                        struct qlcnic_cmd_args *cmd)
3726 {
3727         u8 mac_cmd_rcode;
3728         u32 fw_data;
3729
3730         if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3731                 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3732                 mac_cmd_rcode = (u8)fw_data;
3733                 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3734                     mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3735                     mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3736                         cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3737                         return QLCNIC_RCODE_SUCCESS;
3738                 }
3739         }
3740
3741         return -EINVAL;
3742 }
3743
3744 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3745                                        struct qlcnic_cmd_args *cmd)
3746 {
3747         struct qlcnic_hardware_context *ahw = adapter->ahw;
3748         struct device *dev = &adapter->pdev->dev;
3749         u8 mbx_err_code;
3750         u32 fw_data;
3751
3752         fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3753         mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3754         qlcnic_83xx_get_mbx_data(adapter, cmd);
3755
3756         switch (mbx_err_code) {
3757         case QLCNIC_MBX_RSP_OK:
3758         case QLCNIC_MBX_PORT_RSP_OK:
3759                 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3760                 break;
3761         default:
3762                 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3763                         break;
3764
3765                 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3766                         __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3767                         ahw->op_mode, mbx_err_code);
3768                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3769                 qlcnic_dump_mbx(adapter, cmd);
3770         }
3771
3772         return;
3773 }
3774
3775 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter)
3776 {
3777         struct qlcnic_hardware_context *ahw = adapter->ahw;
3778         u32 offset;
3779
3780         offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
3781         dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x",
3782                  readl(ahw->pci_base0 + offset),
3783                  QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL),
3784                  QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL),
3785                  QLCRDX(ahw, QLCNIC_FW_MBX_CTRL));
3786 }
3787
3788 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3789 {
3790         struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3791                                                   work);
3792         struct qlcnic_adapter *adapter = mbx->adapter;
3793         struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3794         struct device *dev = &adapter->pdev->dev;
3795         atomic_t *rsp_status = &mbx->rsp_status;
3796         struct list_head *head = &mbx->cmd_q;
3797         struct qlcnic_hardware_context *ahw;
3798         struct qlcnic_cmd_args *cmd = NULL;
3799
3800         ahw = adapter->ahw;
3801
3802         while (true) {
3803                 if (qlcnic_83xx_check_mbx_status(adapter)) {
3804                         qlcnic_83xx_flush_mbx_queue(adapter);
3805                         return;
3806                 }
3807
3808                 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3809
3810                 spin_lock(&mbx->queue_lock);
3811
3812                 if (list_empty(head)) {
3813                         spin_unlock(&mbx->queue_lock);
3814                         return;
3815                 }
3816                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3817
3818                 spin_unlock(&mbx->queue_lock);
3819
3820                 mbx_ops->encode_cmd(adapter, cmd);
3821                 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3822
3823                 if (wait_for_completion_timeout(&mbx->completion,
3824                                                 QLC_83XX_MBX_TIMEOUT)) {
3825                         mbx_ops->decode_resp(adapter, cmd);
3826                         mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3827                 } else {
3828                         dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3829                                 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3830                                 ahw->op_mode);
3831                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3832                         qlcnic_dump_mailbox_registers(adapter);
3833                         qlcnic_83xx_get_mbx_data(adapter, cmd);
3834                         qlcnic_dump_mbx(adapter, cmd);
3835                         qlcnic_83xx_idc_request_reset(adapter,
3836                                                       QLCNIC_FORCE_FW_DUMP_KEY);
3837                         cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3838                 }
3839                 mbx_ops->dequeue_cmd(adapter, cmd);
3840         }
3841 }
3842
3843 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3844         .enqueue_cmd    = qlcnic_83xx_enqueue_mbx_cmd,
3845         .dequeue_cmd    = qlcnic_83xx_dequeue_mbx_cmd,
3846         .decode_resp    = qlcnic_83xx_decode_mbx_rsp,
3847         .encode_cmd     = qlcnic_83xx_encode_mbx_cmd,
3848         .nofity_fw      = qlcnic_83xx_signal_mbx_cmd,
3849 };
3850
3851 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3852 {
3853         struct qlcnic_hardware_context *ahw = adapter->ahw;
3854         struct qlcnic_mailbox *mbx;
3855
3856         ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3857         if (!ahw->mailbox)
3858                 return -ENOMEM;
3859
3860         mbx = ahw->mailbox;
3861         mbx->ops = &qlcnic_83xx_mbx_ops;
3862         mbx->adapter = adapter;
3863
3864         spin_lock_init(&mbx->queue_lock);
3865         spin_lock_init(&mbx->aen_lock);
3866         INIT_LIST_HEAD(&mbx->cmd_q);
3867         init_completion(&mbx->completion);
3868
3869         mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3870         if (mbx->work_q == NULL) {
3871                 kfree(mbx);
3872                 return -ENOMEM;
3873         }
3874
3875         INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
3876         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3877         return 0;
3878 }
3879
3880 pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
3881                                                pci_channel_state_t state)
3882 {
3883         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3884
3885         if (state == pci_channel_io_perm_failure)
3886                 return PCI_ERS_RESULT_DISCONNECT;
3887
3888         if (state == pci_channel_io_normal)
3889                 return PCI_ERS_RESULT_RECOVERED;
3890
3891         set_bit(__QLCNIC_AER, &adapter->state);
3892         set_bit(__QLCNIC_RESETTING, &adapter->state);
3893
3894         qlcnic_83xx_aer_stop_poll_work(adapter);
3895
3896         pci_save_state(pdev);
3897         pci_disable_device(pdev);
3898
3899         return PCI_ERS_RESULT_NEED_RESET;
3900 }
3901
3902 pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
3903 {
3904         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3905         int err = 0;
3906
3907         pdev->error_state = pci_channel_io_normal;
3908         err = pci_enable_device(pdev);
3909         if (err)
3910                 goto disconnect;
3911
3912         pci_set_power_state(pdev, PCI_D0);
3913         pci_set_master(pdev);
3914         pci_restore_state(pdev);
3915
3916         err = qlcnic_83xx_aer_reset(adapter);
3917         if (err == 0)
3918                 return PCI_ERS_RESULT_RECOVERED;
3919 disconnect:
3920         clear_bit(__QLCNIC_AER, &adapter->state);
3921         clear_bit(__QLCNIC_RESETTING, &adapter->state);
3922         return PCI_ERS_RESULT_DISCONNECT;
3923 }
3924
3925 void qlcnic_83xx_io_resume(struct pci_dev *pdev)
3926 {
3927         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3928
3929         pci_cleanup_aer_uncorrect_error_status(pdev);
3930         if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
3931                 qlcnic_83xx_aer_start_poll_work(adapter);
3932 }