Pileus Git - ~andy/linux/blob - drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_sriov.h"
  10 #include <linux/if_vlan.h>
  11 #include <linux/ipv6.h>
  12 #include <linux/ethtool.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/aer.h>
  15
  16 #define RSS_HASHTYPE_IP_TCP             0x3
  17 #define QLC_83XX_FW_MBX_CMD             0
  18
  19 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
  20         {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
  21         {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
  22         {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
  23         {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  24         {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
  25         {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  26         {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
  27         {QLCNIC_CMD_INTRPT_TEST, 22, 12},
  28         {QLCNIC_CMD_SET_MTU, 3, 1},
  29         {QLCNIC_CMD_READ_PHY, 4, 2},
  30         {QLCNIC_CMD_WRITE_PHY, 5, 1},
  31         {QLCNIC_CMD_READ_HW_REG, 4, 1},
  32         {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  33         {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  34         {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  35         {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  36         {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  37         {QLCNIC_CMD_GET_PCI_INFO, 1, 66},
  38         {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
  39         {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
  40         {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  41         {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  42         {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  43         {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  44         {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  45         {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  46         {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  47         {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  48         {QLCNIC_CMD_TEMP_SIZE, 1, 4},
  49         {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
  50         {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
  51         {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
  52         {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
  53         {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
  54         {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
  55         {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
  56         {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
  57         {QLCNIC_CMD_GET_STATISTICS, 2, 80},
  58         {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
  59         {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
  60         {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
  61         {QLCNIC_CMD_IDC_ACK, 5, 1},
  62         {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
  63         {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
  64         {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
  65         {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
  66         {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
  67         {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
  68         {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
  69         {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
  70         {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
  71         {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
  72 };
  73
  74 const u32 qlcnic_83xx_ext_reg_tbl[] = {
  75         0x38CC,         /* Global Reset */
  76         0x38F0,         /* Wildcard */
  77         0x38FC,         /* Informant */
  78         0x3038,         /* Host MBX ctrl */
  79         0x303C,         /* FW MBX ctrl */
  80         0x355C,         /* BOOT LOADER ADDRESS REG */
  81         0x3560,         /* BOOT LOADER SIZE REG */
  82         0x3564,         /* FW IMAGE ADDR REG */
  83         0x1000,         /* MBX intr enable */
  84         0x1200,         /* Default Intr mask */
  85         0x1204,         /* Default Interrupt ID */
  86         0x3780,         /* QLC_83XX_IDC_MAJ_VERSION */
  87         0x3784,         /* QLC_83XX_IDC_DEV_STATE */
  88         0x3788,         /* QLC_83XX_IDC_DRV_PRESENCE */
  89         0x378C,         /* QLC_83XX_IDC_DRV_ACK */
  90         0x3790,         /* QLC_83XX_IDC_CTRL */
  91         0x3794,         /* QLC_83XX_IDC_DRV_AUDIT */
  92         0x3798,         /* QLC_83XX_IDC_MIN_VERSION */
  93         0x379C,         /* QLC_83XX_RECOVER_DRV_LOCK */
  94         0x37A0,         /* QLC_83XX_IDC_PF_0 */
  95         0x37A4,         /* QLC_83XX_IDC_PF_1 */
  96         0x37A8,         /* QLC_83XX_IDC_PF_2 */
  97         0x37AC,         /* QLC_83XX_IDC_PF_3 */
  98         0x37B0,         /* QLC_83XX_IDC_PF_4 */
  99         0x37B4,         /* QLC_83XX_IDC_PF_5 */
 100         0x37B8,         /* QLC_83XX_IDC_PF_6 */
 101         0x37BC,         /* QLC_83XX_IDC_PF_7 */
 102         0x37C0,         /* QLC_83XX_IDC_PF_8 */
 103         0x37C4,         /* QLC_83XX_IDC_PF_9 */
 104         0x37C8,         /* QLC_83XX_IDC_PF_10 */
 105         0x37CC,         /* QLC_83XX_IDC_PF_11 */
 106         0x37D0,         /* QLC_83XX_IDC_PF_12 */
 107         0x37D4,         /* QLC_83XX_IDC_PF_13 */
 108         0x37D8,         /* QLC_83XX_IDC_PF_14 */
 109         0x37DC,         /* QLC_83XX_IDC_PF_15 */
 110         0x37E0,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
 111         0x37E4,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
 112         0x37F0,         /* QLC_83XX_DRV_OP_MODE */
 113         0x37F4,         /* QLC_83XX_VNIC_STATE */
 114         0x3868,         /* QLC_83XX_DRV_LOCK */
 115         0x386C,         /* QLC_83XX_DRV_UNLOCK */
 116         0x3504,         /* QLC_83XX_DRV_LOCK_ID */
 117         0x34A4,         /* QLC_83XX_ASIC_TEMP */
 118 };
 119
 120 const u32 qlcnic_83xx_reg_tbl[] = {
 121         0x34A8,         /* PEG_HALT_STAT1 */
 122         0x34AC,         /* PEG_HALT_STAT2 */
 123         0x34B0,         /* FW_HEARTBEAT */
 124         0x3500,         /* FLASH LOCK_ID */
 125         0x3528,         /* FW_CAPABILITIES */
 126         0x3538,         /* Driver active, DRV_REG0 */
 127         0x3540,         /* Device state, DRV_REG1 */
 128         0x3544,         /* Driver state, DRV_REG2 */
 129         0x3548,         /* Driver scratch, DRV_REG3 */
 130         0x354C,         /* Device partiton info, DRV_REG4 */
 131         0x3524,         /* Driver IDC ver, DRV_REG5 */
 132         0x3550,         /* FW_VER_MAJOR */
 133         0x3554,         /* FW_VER_MINOR */
 134         0x3558,         /* FW_VER_SUB */
 135         0x359C,         /* NPAR STATE */
 136         0x35FC,         /* FW_IMG_VALID */
 137         0x3650,         /* CMD_PEG_STATE */
 138         0x373C,         /* RCV_PEG_STATE */
 139         0x37B4,         /* ASIC TEMP */
 140         0x356C,         /* FW API */
 141         0x3570,         /* DRV OP MODE */
 142         0x3850,         /* FLASH LOCK */
 143         0x3854,         /* FLASH UNLOCK */
 144 };
 145
 146 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
 147         .read_crb                       = qlcnic_83xx_read_crb,
 148         .write_crb                      = qlcnic_83xx_write_crb,
 149         .read_reg                       = qlcnic_83xx_rd_reg_indirect,
 150         .write_reg                      = qlcnic_83xx_wrt_reg_indirect,
 151         .get_mac_address                = qlcnic_83xx_get_mac_address,
 152         .setup_intr                     = qlcnic_83xx_setup_intr,
 153         .alloc_mbx_args                 = qlcnic_83xx_alloc_mbx_args,
 154         .mbx_cmd                        = qlcnic_83xx_issue_cmd,
 155         .get_func_no                    = qlcnic_83xx_get_func_no,
 156         .api_lock                       = qlcnic_83xx_cam_lock,
 157         .api_unlock                     = qlcnic_83xx_cam_unlock,
 158         .add_sysfs                      = qlcnic_83xx_add_sysfs,
 159         .remove_sysfs                   = qlcnic_83xx_remove_sysfs,
 160         .process_lb_rcv_ring_diag       = qlcnic_83xx_process_rcv_ring_diag,
 161         .create_rx_ctx                  = qlcnic_83xx_create_rx_ctx,
 162         .create_tx_ctx                  = qlcnic_83xx_create_tx_ctx,
 163         .del_rx_ctx                     = qlcnic_83xx_del_rx_ctx,
 164         .del_tx_ctx                     = qlcnic_83xx_del_tx_ctx,
 165         .setup_link_event               = qlcnic_83xx_setup_link_event,
 166         .get_nic_info                   = qlcnic_83xx_get_nic_info,
 167         .get_pci_info                   = qlcnic_83xx_get_pci_info,
 168         .set_nic_info                   = qlcnic_83xx_set_nic_info,
 169         .change_macvlan                 = qlcnic_83xx_sre_macaddr_change,
 170         .napi_enable                    = qlcnic_83xx_napi_enable,
 171         .napi_disable                   = qlcnic_83xx_napi_disable,
 172         .config_intr_coal               = qlcnic_83xx_config_intr_coal,
 173         .config_rss                     = qlcnic_83xx_config_rss,
 174         .config_hw_lro                  = qlcnic_83xx_config_hw_lro,
 175         .config_promisc_mode            = qlcnic_83xx_nic_set_promisc,
 176         .change_l2_filter               = qlcnic_83xx_change_l2_filter,
 177         .get_board_info                 = qlcnic_83xx_get_port_info,
 178         .set_mac_filter_count           = qlcnic_83xx_set_mac_filter_count,
 179         .free_mac_list                  = qlcnic_82xx_free_mac_list,
 180         .io_error_detected              = qlcnic_83xx_io_error_detected,
 181         .io_slot_reset                  = qlcnic_83xx_io_slot_reset,
 182         .io_resume                      = qlcnic_83xx_io_resume,
 183
 184 };
 185
 186 static struct qlcnic_nic_template qlcnic_83xx_ops = {
 187         .config_bridged_mode    = qlcnic_config_bridged_mode,
 188         .config_led             = qlcnic_config_led,
 189         .request_reset          = qlcnic_83xx_idc_request_reset,
 190         .cancel_idc_work        = qlcnic_83xx_idc_exit,
 191         .napi_add               = qlcnic_83xx_napi_add,
 192         .napi_del               = qlcnic_83xx_napi_del,
 193         .config_ipaddr          = qlcnic_83xx_config_ipaddr,
 194         .clear_legacy_intr      = qlcnic_83xx_clear_legacy_intr,
 195         .shutdown               = qlcnic_83xx_shutdown,
 196         .resume                 = qlcnic_83xx_resume,
 197 };
 198
 199 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
 200 {
 201         ahw->hw_ops             = &qlcnic_83xx_hw_ops;
 202         ahw->reg_tbl            = (u32 *)qlcnic_83xx_reg_tbl;
 203         ahw->ext_reg_tbl        = (u32 *)qlcnic_83xx_ext_reg_tbl;
 204 }
 205
 206 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
 207 {
 208         u32 fw_major, fw_minor, fw_build;
 209         struct pci_dev *pdev = adapter->pdev;
 210
 211         fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
 212         fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
 213         fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
 214         adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
 215
 216         dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
 217                  QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
 218
 219         return adapter->fw_version;
 220 }
 221
 222 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
 223 {
 224         void __iomem *base;
 225         u32 val;
 226
 227         base = adapter->ahw->pci_base0 +
 228                QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
 229         writel(addr, base);
 230         val = readl(base);
 231         if (val != addr)
 232                 return -EIO;
 233
 234         return 0;
 235 }
 236
 237 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 238                                 int *err)
 239 {
 240         struct qlcnic_hardware_context *ahw = adapter->ahw;
 241
 242         *err = __qlcnic_set_win_base(adapter, (u32) addr);
 243         if (!*err) {
 244                 return QLCRDX(ahw, QLCNIC_WILDCARD);
 245         } else {
 246                 dev_err(&adapter->pdev->dev,
 247                         "%s failed, addr = 0x%lx\n", __func__, addr);
 248                 return -EIO;
 249         }
 250 }
 251
 252 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 253                                  u32 data)
 254 {
 255         int err;
 256         struct qlcnic_hardware_context *ahw = adapter->ahw;
 257
 258         err = __qlcnic_set_win_base(adapter, (u32) addr);
 259         if (!err) {
 260                 QLCWRX(ahw, QLCNIC_WILDCARD, data);
 261                 return 0;
 262         } else {
 263                 dev_err(&adapter->pdev->dev,
 264                         "%s failed, addr = 0x%x data = 0x%x\n",
 265                         __func__, (int)addr, data);
 266                 return err;
 267         }
 268 }
 269
 270 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
 271 {
 272         int err, i, num_msix;
 273         struct qlcnic_hardware_context *ahw = adapter->ahw;
 274
 275         num_msix = adapter->drv_sds_rings;
 276
 277         /* account for AEN interrupt MSI-X based interrupts */
 278         num_msix += 1;
 279
 280         if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
 281                 num_msix += adapter->drv_tx_rings;
 282
 283         err = qlcnic_enable_msix(adapter, num_msix);
 284         if (err == -ENOMEM)
 285                 return err;
 286         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 287                 num_msix = adapter->ahw->num_msix;
 288         else {
 289                 if (qlcnic_sriov_vf_check(adapter))
 290                         return -EINVAL;
 291                 num_msix = 1;
 292                 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
 293         }
 294         /* setup interrupt mapping table for fw */
 295         ahw->intr_tbl = vzalloc(num_msix *
 296                                 sizeof(struct qlcnic_intrpt_config));
 297         if (!ahw->intr_tbl)
 298                 return -ENOMEM;
 299         if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
 300                 /* MSI-X enablement failed, use legacy interrupt */
 301                 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
 302                 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
 303                 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
 304                 adapter->msix_entries[0].vector = adapter->pdev->irq;
 305                 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
 306         }
 307
 308         for (i = 0; i < num_msix; i++) {
 309                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
 310                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
 311                 else
 312                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
 313                 ahw->intr_tbl[i].id = i;
 314                 ahw->intr_tbl[i].src = 0;
 315         }
 316         return 0;
 317 }
 318
 319 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
 320 {
 321         writel(0, adapter->tgt_mask_reg);
 322 }
 323
 324 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
 325 {
 326         if (adapter->tgt_mask_reg)
 327                 writel(1, adapter->tgt_mask_reg);
 328 }
 329
 330 /* Enable MSI-x and INT-x interrupts */
 331 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
 332                              struct qlcnic_host_sds_ring *sds_ring)
 333 {
 334         writel(0, sds_ring->crb_intr_mask);
 335 }
 336
 337 /* Disable MSI-x and INT-x interrupts */
 338 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
 339                               struct qlcnic_host_sds_ring *sds_ring)
 340 {
 341         writel(1, sds_ring->crb_intr_mask);
 342 }
 343
 344 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
 345                                                     *adapter)
 346 {
 347         u32 mask;
 348
 349         /* Mailbox in MSI-x mode and Legacy Interrupt share the same
 350          * source register. We could be here before contexts are created
 351          * and sds_ring->crb_intr_mask has not been initialized, calculate
 352          * BAR offset for Interrupt Source Register
 353          */
 354         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 355         writel(0, adapter->ahw->pci_base0 + mask);
 356 }
 357
 358 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
 359 {
 360         u32 mask;
 361
 362         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 363         writel(1, adapter->ahw->pci_base0 + mask);
 364         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
 365 }
 366
 367 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
 368                                      struct qlcnic_cmd_args *cmd)
 369 {
 370         int i;
 371
 372         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 373                 return;
 374
 375         for (i = 0; i < cmd->rsp.num; i++)
 376                 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
 377 }
 378
 379 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
 380 {
 381         u32 intr_val;
 382         struct qlcnic_hardware_context *ahw = adapter->ahw;
 383         int retries = 0;
 384
 385         intr_val = readl(adapter->tgt_status_reg);
 386
 387         if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
 388                 return IRQ_NONE;
 389
 390         if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
 391                 adapter->stats.spurious_intr++;
 392                 return IRQ_NONE;
 393         }
 394         /* The barrier is required to ensure writes to the registers */
 395         wmb();
 396
 397         /* clear the interrupt trigger control register */
 398         writel(0, adapter->isr_int_vec);
 399         intr_val = readl(adapter->isr_int_vec);
 400         do {
 401                 intr_val = readl(adapter->tgt_status_reg);
 402                 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
 403                         break;
 404                 retries++;
 405         } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
 406                  (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
 407
 408         return IRQ_HANDLED;
 409 }
 410
 411 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
 412 {
 413         atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
 414         complete(&mbx->completion);
 415 }
 416
 417 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
 418 {
 419         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 420         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 421         unsigned long flags;
 422
 423         spin_lock_irqsave(&mbx->aen_lock, flags);
 424         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
 425         if (!(resp & QLCNIC_SET_OWNER))
 426                 goto out;
 427
 428         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
 429         if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 430                 __qlcnic_83xx_process_aen(adapter);
 431         } else {
 432                 if (atomic_read(&mbx->rsp_status) != rsp_status)
 433                         qlcnic_83xx_notify_mbx_response(mbx);
 434         }
 435 out:
 436         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 437         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 438 }
 439
 440 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
 441 {
 442         struct qlcnic_adapter *adapter = data;
 443         struct qlcnic_host_sds_ring *sds_ring;
 444         struct qlcnic_hardware_context *ahw = adapter->ahw;
 445
 446         if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
 447                 return IRQ_NONE;
 448
 449         qlcnic_83xx_poll_process_aen(adapter);
 450
 451         if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
 452                 ahw->diag_cnt++;
 453                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 454                 return IRQ_HANDLED;
 455         }
 456
 457         if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
 458                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 459         } else {
 460                 sds_ring = &adapter->recv_ctx->sds_rings[0];
 461                 napi_schedule(&sds_ring->napi);
 462         }
 463
 464         return IRQ_HANDLED;
 465 }
 466
 467 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
 468 {
 469         struct qlcnic_host_sds_ring *sds_ring = data;
 470         struct qlcnic_adapter *adapter = sds_ring->adapter;
 471
 472         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 473                 goto done;
 474
 475         if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
 476                 return IRQ_NONE;
 477
 478 done:
 479         adapter->ahw->diag_cnt++;
 480         qlcnic_83xx_enable_intr(adapter, sds_ring);
 481
 482         return IRQ_HANDLED;
 483 }
 484
 485 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
 486 {
 487         u32 num_msix;
 488
 489         if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
 490                 qlcnic_83xx_set_legacy_intr_mask(adapter);
 491
 492         qlcnic_83xx_disable_mbx_intr(adapter);
 493
 494         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 495                 num_msix = adapter->ahw->num_msix - 1;
 496         else
 497                 num_msix = 0;
 498
 499         msleep(20);
 500
 501         if (adapter->msix_entries) {
 502                 synchronize_irq(adapter->msix_entries[num_msix].vector);
 503                 free_irq(adapter->msix_entries[num_msix].vector, adapter);
 504         }
 505 }
 506
 507 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
 508 {
 509         irq_handler_t handler;
 510         u32 val;
 511         int err = 0;
 512         unsigned long flags = 0;
 513
 514         if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
 515             !(adapter->flags & QLCNIC_MSIX_ENABLED))
 516                 flags |= IRQF_SHARED;
 517
 518         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 519                 handler = qlcnic_83xx_handle_aen;
 520                 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
 521                 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
 522                 if (err) {
 523                         dev_err(&adapter->pdev->dev,
 524                                 "failed to register MBX interrupt\n");
 525                         return err;
 526                 }
 527         } else {
 528                 handler = qlcnic_83xx_intr;
 529                 val = adapter->msix_entries[0].vector;
 530                 err = request_irq(val, handler, flags, "qlcnic", adapter);
 531                 if (err) {
 532                         dev_err(&adapter->pdev->dev,
 533                                 "failed to register INTx interrupt\n");
 534                         return err;
 535                 }
 536                 qlcnic_83xx_clear_legacy_intr_mask(adapter);
 537         }
 538
 539         /* Enable mailbox interrupt */
 540         qlcnic_83xx_enable_mbx_interrupt(adapter);
 541
 542         return err;
 543 }
 544
 545 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
 546 {
 547         u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
 548         adapter->ahw->pci_func = (val >> 24) & 0xff;
 549 }
 550
 551 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
 552 {
 553         void __iomem *addr;
 554         u32 val, limit = 0;
 555
 556         struct qlcnic_hardware_context *ahw = adapter->ahw;
 557
 558         addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
 559         do {
 560                 val = readl(addr);
 561                 if (val) {
 562                         /* write the function number to register */
 563                         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
 564                                             ahw->pci_func);
 565                         return 0;
 566                 }
 567                 usleep_range(1000, 2000);
 568         } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
 569
 570         return -EIO;
 571 }
 572
 573 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
 574 {
 575         void __iomem *addr;
 576         u32 val;
 577         struct qlcnic_hardware_context *ahw = adapter->ahw;
 578
 579         addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
 580         val = readl(addr);
 581 }
 582
 583 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
 584                           loff_t offset, size_t size)
 585 {
 586         int ret = 0;
 587         u32 data;
 588
 589         if (qlcnic_api_lock(adapter)) {
 590                 dev_err(&adapter->pdev->dev,
 591                         "%s: failed to acquire lock. addr offset 0x%x\n",
 592                         __func__, (u32)offset);
 593                 return;
 594         }
 595
 596         data = QLCRD32(adapter, (u32) offset, &ret);
 597         qlcnic_api_unlock(adapter);
 598
 599         if (ret == -EIO) {
 600                 dev_err(&adapter->pdev->dev,
 601                         "%s: failed. addr offset 0x%x\n",
 602                         __func__, (u32)offset);
 603                 return;
 604         }
 605         memcpy(buf, &data, size);
 606 }
 607
 608 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
 609                            loff_t offset, size_t size)
 610 {
 611         u32 data;
 612
 613         memcpy(&data, buf, size);
 614         qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
 615 }
 616
 617 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
 618 {
 619         int status;
 620
 621         status = qlcnic_83xx_get_port_config(adapter);
 622         if (status) {
 623                 dev_err(&adapter->pdev->dev,
 624                         "Get Port Info failed\n");
 625         } else {
 626                 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
 627                         adapter->ahw->port_type = QLCNIC_XGBE;
 628                 else
 629                         adapter->ahw->port_type = QLCNIC_GBE;
 630
 631                 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
 632                         adapter->ahw->link_autoneg = AUTONEG_ENABLE;
 633         }
 634         return status;
 635 }
 636
 637 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
 638 {
 639         struct qlcnic_hardware_context *ahw = adapter->ahw;
 640         u16 act_pci_fn = ahw->act_pci_func;
 641         u16 count;
 642
 643         ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
 644         if (act_pci_fn <= 2)
 645                 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
 646                          act_pci_fn;
 647         else
 648                 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
 649                          act_pci_fn;
 650         ahw->max_uc_count = count;
 651 }
 652
 653 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
 654 {
 655         u32 val;
 656
 657         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 658                 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
 659         else
 660                 val = BIT_2;
 661
 662         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
 663         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 664 }
 665
 666 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
 667                           const struct pci_device_id *ent)
 668 {
 669         u32 op_mode, priv_level;
 670         struct qlcnic_hardware_context *ahw = adapter->ahw;
 671
 672         ahw->fw_hal_version = 2;
 673         qlcnic_get_func_no(adapter);
 674
 675         if (qlcnic_sriov_vf_check(adapter)) {
 676                 qlcnic_sriov_vf_set_ops(adapter);
 677                 return;
 678         }
 679
 680         /* Determine function privilege level */
 681         op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
 682         if (op_mode == QLC_83XX_DEFAULT_OPMODE)
 683                 priv_level = QLCNIC_MGMT_FUNC;
 684         else
 685                 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
 686                                                          ahw->pci_func);
 687
 688         if (priv_level == QLCNIC_NON_PRIV_FUNC) {
 689                 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
 690                 dev_info(&adapter->pdev->dev,
 691                          "HAL Version: %d Non Privileged function\n",
 692                          ahw->fw_hal_version);
 693                 adapter->nic_ops = &qlcnic_vf_ops;
 694         } else {
 695                 if (pci_find_ext_capability(adapter->pdev,
 696                                             PCI_EXT_CAP_ID_SRIOV))
 697                         set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
 698                 adapter->nic_ops = &qlcnic_83xx_ops;
 699         }
 700 }
 701
 702 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
 703                                         u32 data[]);
 704 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 705                                             u32 data[]);
 706
 707 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
 708                      struct qlcnic_cmd_args *cmd)
 709 {
 710         int i;
 711
 712         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 713                 return;
 714
 715         dev_info(&adapter->pdev->dev,
 716                  "Host MBX regs(%d)\n", cmd->req.num);
 717         for (i = 0; i < cmd->req.num; i++) {
 718                 if (i && !(i % 8))
 719                         pr_info("\n");
 720                 pr_info("%08x ", cmd->req.arg[i]);
 721         }
 722         pr_info("\n");
 723         dev_info(&adapter->pdev->dev,
 724                  "FW MBX regs(%d)\n", cmd->rsp.num);
 725         for (i = 0; i < cmd->rsp.num; i++) {
 726                 if (i && !(i % 8))
 727                         pr_info("\n");
 728                 pr_info("%08x ", cmd->rsp.arg[i]);
 729         }
 730         pr_info("\n");
 731 }
 732
 733 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
 734                                                 struct qlcnic_cmd_args *cmd)
 735 {
 736         struct qlcnic_hardware_context *ahw = adapter->ahw;
 737         int opcode = LSW(cmd->req.arg[0]);
 738         unsigned long max_loops;
 739
 740         max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
 741
 742         for (; max_loops; max_loops--) {
 743                 if (atomic_read(&cmd->rsp_status) ==
 744                     QLC_83XX_MBX_RESPONSE_ARRIVED)
 745                         return;
 746
 747                 udelay(1);
 748         }
 749
 750         dev_err(&adapter->pdev->dev,
 751                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 752                 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
 753         flush_workqueue(ahw->mailbox->work_q);
 754         return;
 755 }
 756
 757 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
 758                           struct qlcnic_cmd_args *cmd)
 759 {
 760         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 761         struct qlcnic_hardware_context *ahw = adapter->ahw;
 762         int cmd_type, err, opcode;
 763         unsigned long timeout;
 764
 765         if (!mbx)
 766                 return -EIO;
 767
 768         opcode = LSW(cmd->req.arg[0]);
 769         cmd_type = cmd->type;
 770         err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
 771         if (err) {
 772                 dev_err(&adapter->pdev->dev,
 773                         "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 774                         __func__, opcode, cmd->type, ahw->pci_func,
 775                         ahw->op_mode);
 776                 return err;
 777         }
 778
 779         switch (cmd_type) {
 780         case QLC_83XX_MBX_CMD_WAIT:
 781                 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
 782                         dev_err(&adapter->pdev->dev,
 783                                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 784                                 __func__, opcode, cmd_type, ahw->pci_func,
 785                                 ahw->op_mode);
 786                         flush_workqueue(mbx->work_q);
 787                 }
 788                 break;
 789         case QLC_83XX_MBX_CMD_NO_WAIT:
 790                 return 0;
 791         case QLC_83XX_MBX_CMD_BUSY_WAIT:
 792                 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
 793                 break;
 794         default:
 795                 dev_err(&adapter->pdev->dev,
 796                         "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 797                         __func__, opcode, cmd_type, ahw->pci_func,
 798                         ahw->op_mode);
 799                 qlcnic_83xx_detach_mailbox_work(adapter);
 800         }
 801
 802         return cmd->rsp_opcode;
 803 }
 804
 805 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
 806                                struct qlcnic_adapter *adapter, u32 type)
 807 {
 808         int i, size;
 809         u32 temp;
 810         const struct qlcnic_mailbox_metadata *mbx_tbl;
 811
 812         memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
 813         mbx_tbl = qlcnic_83xx_mbx_tbl;
 814         size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
 815         for (i = 0; i < size; i++) {
 816                 if (type == mbx_tbl[i].cmd) {
 817                         mbx->op_type = QLC_83XX_FW_MBX_CMD;
 818                         mbx->req.num = mbx_tbl[i].in_args;
 819                         mbx->rsp.num = mbx_tbl[i].out_args;
 820                         mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
 821                                                GFP_ATOMIC);
 822                         if (!mbx->req.arg)
 823                                 return -ENOMEM;
 824                         mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
 825                                                GFP_ATOMIC);
 826                         if (!mbx->rsp.arg) {
 827                                 kfree(mbx->req.arg);
 828                                 mbx->req.arg = NULL;
 829                                 return -ENOMEM;
 830                         }
 831                         memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
 832                         memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
 833                         temp = adapter->ahw->fw_hal_version << 29;
 834                         mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
 835                         mbx->cmd_op = type;
 836                         return 0;
 837                 }
 838         }
 839         return -EINVAL;
 840 }
 841
 842 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
 843 {
 844         struct qlcnic_adapter *adapter;
 845         struct qlcnic_cmd_args cmd;
 846         int i, err = 0;
 847
 848         adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
 849         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
 850         if (err)
 851                 return;
 852
 853         for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
 854                 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
 855
 856         err = qlcnic_issue_cmd(adapter, &cmd);
 857         if (err)
 858                 dev_info(&adapter->pdev->dev,
 859                          "%s: Mailbox IDC ACK failed.\n", __func__);
 860         qlcnic_free_mbx_args(&cmd);
 861 }
 862
 863 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 864                                             u32 data[])
 865 {
 866         dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
 867                 QLCNIC_MBX_RSP(data[0]));
 868         clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
 869         return;
 870 }
 871
 872 void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 873 {
 874         struct qlcnic_hardware_context *ahw = adapter->ahw;
 875         u32 event[QLC_83XX_MBX_AEN_CNT];
 876         int i;
 877
 878         for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 879                 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
 880
 881         switch (QLCNIC_MBX_RSP(event[0])) {
 882
 883         case QLCNIC_MBX_LINK_EVENT:
 884                 qlcnic_83xx_handle_link_aen(adapter, event);
 885                 break;
 886         case QLCNIC_MBX_COMP_EVENT:
 887                 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
 888                 break;
 889         case QLCNIC_MBX_REQUEST_EVENT:
 890                 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 891                         adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
 892                 queue_delayed_work(adapter->qlcnic_wq,
 893                                    &adapter->idc_aen_work, 0);
 894                 break;
 895         case QLCNIC_MBX_TIME_EXTEND_EVENT:
 896                 ahw->extend_lb_time = event[1] >> 8 & 0xf;
 897                 break;
 898         case QLCNIC_MBX_BC_EVENT:
 899                 qlcnic_sriov_handle_bc_event(adapter, event[1]);
 900                 break;
 901         case QLCNIC_MBX_SFP_INSERT_EVENT:
 902                 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
 903                          QLCNIC_MBX_RSP(event[0]));
 904                 break;
 905         case QLCNIC_MBX_SFP_REMOVE_EVENT:
 906                 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
 907                          QLCNIC_MBX_RSP(event[0]));
 908                 break;
 909         case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
 910                 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
 911                 break;
 912         default:
 913                 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
 914                         QLCNIC_MBX_RSP(event[0]));
 915                 break;
 916         }
 917
 918         QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
 919 }
 920
 921 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 922 {
 923         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 924         struct qlcnic_hardware_context *ahw = adapter->ahw;
 925         struct qlcnic_mailbox *mbx = ahw->mailbox;
 926         unsigned long flags;
 927
 928         spin_lock_irqsave(&mbx->aen_lock, flags);
 929         resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
 930         if (resp & QLCNIC_SET_OWNER) {
 931                 event = readl(QLCNIC_MBX_FW(ahw, 0));
 932                 if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 933                         __qlcnic_83xx_process_aen(adapter);
 934                 } else {
 935                         if (atomic_read(&mbx->rsp_status) != rsp_status)
 936                                 qlcnic_83xx_notify_mbx_response(mbx);
 937                 }
 938         }
 939         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 940 }
 941
 942 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
 943 {
 944         struct qlcnic_adapter *adapter;
 945
 946         adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
 947
 948         if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 949                 return;
 950
 951         qlcnic_83xx_process_aen(adapter);
 952         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
 953                            (HZ / 10));
 954 }
 955
 956 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
 957 {
 958         if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 959                 return;
 960
 961         INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
 962         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
 963 }
 964
 965 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
 966 {
 967         if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 968                 return;
 969         cancel_delayed_work_sync(&adapter->mbx_poll_work);
 970 }
 971
 972 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
 973 {
 974         int index, i, err, sds_mbx_size;
 975         u32 *buf, intrpt_id, intr_mask;
 976         u16 context_id;
 977         u8 num_sds;
 978         struct qlcnic_cmd_args cmd;
 979         struct qlcnic_host_sds_ring *sds;
 980         struct qlcnic_sds_mbx sds_mbx;
 981         struct qlcnic_add_rings_mbx_out *mbx_out;
 982         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
 983         struct qlcnic_hardware_context *ahw = adapter->ahw;
 984
 985         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
 986         context_id = recv_ctx->context_id;
 987         num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
 988         ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
 989                                     QLCNIC_CMD_ADD_RCV_RINGS);
 990         cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
 991
 992         /* set up status rings, mbx 2-81 */
 993         index = 2;
 994         for (i = 8; i < adapter->drv_sds_rings; i++) {
 995                 memset(&sds_mbx, 0, sds_mbx_size);
 996                 sds = &recv_ctx->sds_rings[i];
 997                 sds->consumer = 0;
 998                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
 999                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1000                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1001                 sds_mbx.sds_ring_size = sds->num_desc;
1002
1003                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1004                         intrpt_id = ahw->intr_tbl[i].id;
1005                 else
1006                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1007
1008                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1009                         sds_mbx.intrpt_id = intrpt_id;
1010                 else
1011                         sds_mbx.intrpt_id = 0xffff;
1012                 sds_mbx.intrpt_val = 0;
1013                 buf = &cmd.req.arg[index];
1014                 memcpy(buf, &sds_mbx, sds_mbx_size);
1015                 index += sds_mbx_size / sizeof(u32);
1016         }
1017
1018         /* send the mailbox command */
1019         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1020         if (err) {
1021                 dev_err(&adapter->pdev->dev,
1022                         "Failed to add rings %d\n", err);
1023                 goto out;
1024         }
1025
1026         mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1027         index = 0;
1028         /* status descriptor ring */
1029         for (i = 8; i < adapter->drv_sds_rings; i++) {
1030                 sds = &recv_ctx->sds_rings[i];
1031                 sds->crb_sts_consumer = ahw->pci_base0 +
1032                                         mbx_out->host_csmr[index];
1033                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1034                         intr_mask = ahw->intr_tbl[i].src;
1035                 else
1036                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1037
1038                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1039                 index++;
1040         }
1041 out:
1042         qlcnic_free_mbx_args(&cmd);
1043         return err;
1044 }
1045
1046 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1047 {
1048         int err;
1049         u32 temp = 0;
1050         struct qlcnic_cmd_args cmd;
1051         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1052
1053         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1054                 return;
1055
1056         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1057                 cmd.req.arg[0] |= (0x3 << 29);
1058
1059         if (qlcnic_sriov_pf_check(adapter))
1060                 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1061
1062         cmd.req.arg[1] = recv_ctx->context_id | temp;
1063         err = qlcnic_issue_cmd(adapter, &cmd);
1064         if (err)
1065                 dev_err(&adapter->pdev->dev,
1066                         "Failed to destroy rx ctx in firmware\n");
1067
1068         recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1069         qlcnic_free_mbx_args(&cmd);
1070 }
1071
1072 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1073 {
1074         int i, err, index, sds_mbx_size, rds_mbx_size;
1075         u8 num_sds, num_rds;
1076         u32 *buf, intrpt_id, intr_mask, cap = 0;
1077         struct qlcnic_host_sds_ring *sds;
1078         struct qlcnic_host_rds_ring *rds;
1079         struct qlcnic_sds_mbx sds_mbx;
1080         struct qlcnic_rds_mbx rds_mbx;
1081         struct qlcnic_cmd_args cmd;
1082         struct qlcnic_rcv_mbx_out *mbx_out;
1083         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1084         struct qlcnic_hardware_context *ahw = adapter->ahw;
1085         num_rds = adapter->max_rds_rings;
1086
1087         if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1088                 num_sds = adapter->drv_sds_rings;
1089         else
1090                 num_sds = QLCNIC_MAX_SDS_RINGS;
1091
1092         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1093         rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1094         cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1095
1096         if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1097                 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1098
1099         /* set mailbox hdr and capabilities */
1100         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1101                                     QLCNIC_CMD_CREATE_RX_CTX);
1102         if (err)
1103                 return err;
1104
1105         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1106                 cmd.req.arg[0] |= (0x3 << 29);
1107
1108         cmd.req.arg[1] = cap;
1109         cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1110                          (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1111
1112         if (qlcnic_sriov_pf_check(adapter))
1113                 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1114                                                          &cmd.req.arg[6]);
1115         /* set up status rings, mbx 8-57/87 */
1116         index = QLC_83XX_HOST_SDS_MBX_IDX;
1117         for (i = 0; i < num_sds; i++) {
1118                 memset(&sds_mbx, 0, sds_mbx_size);
1119                 sds = &recv_ctx->sds_rings[i];
1120                 sds->consumer = 0;
1121                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1122                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1123                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1124                 sds_mbx.sds_ring_size = sds->num_desc;
1125                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1126                         intrpt_id = ahw->intr_tbl[i].id;
1127                 else
1128                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1129                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1130                         sds_mbx.intrpt_id = intrpt_id;
1131                 else
1132                         sds_mbx.intrpt_id = 0xffff;
1133                 sds_mbx.intrpt_val = 0;
1134                 buf = &cmd.req.arg[index];
1135                 memcpy(buf, &sds_mbx, sds_mbx_size);
1136                 index += sds_mbx_size / sizeof(u32);
1137         }
1138         /* set up receive rings, mbx 88-111/135 */
1139         index = QLCNIC_HOST_RDS_MBX_IDX;
1140         rds = &recv_ctx->rds_rings[0];
1141         rds->producer = 0;
1142         memset(&rds_mbx, 0, rds_mbx_size);
1143         rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1144         rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1145         rds_mbx.reg_ring_sz = rds->dma_size;
1146         rds_mbx.reg_ring_len = rds->num_desc;
1147         /* Jumbo ring */
1148         rds = &recv_ctx->rds_rings[1];
1149         rds->producer = 0;
1150         rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1151         rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1152         rds_mbx.jmb_ring_sz = rds->dma_size;
1153         rds_mbx.jmb_ring_len = rds->num_desc;
1154         buf = &cmd.req.arg[index];
1155         memcpy(buf, &rds_mbx, rds_mbx_size);
1156
1157         /* send the mailbox command */
1158         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1159         if (err) {
1160                 dev_err(&adapter->pdev->dev,
1161                         "Failed to create Rx ctx in firmware%d\n", err);
1162                 goto out;
1163         }
1164         mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1165         recv_ctx->context_id = mbx_out->ctx_id;
1166         recv_ctx->state = mbx_out->state;
1167         recv_ctx->virt_port = mbx_out->vport_id;
1168         dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1169                  recv_ctx->context_id, recv_ctx->state);
1170         /* Receive descriptor ring */
1171         /* Standard ring */
1172         rds = &recv_ctx->rds_rings[0];
1173         rds->crb_rcv_producer = ahw->pci_base0 +
1174                                 mbx_out->host_prod[0].reg_buf;
1175         /* Jumbo ring */
1176         rds = &recv_ctx->rds_rings[1];
1177         rds->crb_rcv_producer = ahw->pci_base0 +
1178                                 mbx_out->host_prod[0].jmb_buf;
1179         /* status descriptor ring */
1180         for (i = 0; i < num_sds; i++) {
1181                 sds = &recv_ctx->sds_rings[i];
1182                 sds->crb_sts_consumer = ahw->pci_base0 +
1183                                         mbx_out->host_csmr[i];
1184                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1185                         intr_mask = ahw->intr_tbl[i].src;
1186                 else
1187                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1188                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1189         }
1190
1191         if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1192                 err = qlcnic_83xx_add_rings(adapter);
1193 out:
1194         qlcnic_free_mbx_args(&cmd);
1195         return err;
1196 }
1197
1198 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1199                             struct qlcnic_host_tx_ring *tx_ring)
1200 {
1201         struct qlcnic_cmd_args cmd;
1202         u32 temp = 0;
1203
1204         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1205                 return;
1206
1207         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1208                 cmd.req.arg[0] |= (0x3 << 29);
1209
1210         if (qlcnic_sriov_pf_check(adapter))
1211                 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1212
1213         cmd.req.arg[1] = tx_ring->ctx_id | temp;
1214         if (qlcnic_issue_cmd(adapter, &cmd))
1215                 dev_err(&adapter->pdev->dev,
1216                         "Failed to destroy tx ctx in firmware\n");
1217         qlcnic_free_mbx_args(&cmd);
1218 }
1219
1220 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1221                               struct qlcnic_host_tx_ring *tx, int ring)
1222 {
1223         int err;
1224         u16 msix_id;
1225         u32 *buf, intr_mask, temp = 0;
1226         struct qlcnic_cmd_args cmd;
1227         struct qlcnic_tx_mbx mbx;
1228         struct qlcnic_tx_mbx_out *mbx_out;
1229         struct qlcnic_hardware_context *ahw = adapter->ahw;
1230         u32 msix_vector;
1231
1232         /* Reset host resources */
1233         tx->producer = 0;
1234         tx->sw_consumer = 0;
1235         *(tx->hw_consumer) = 0;
1236
1237         memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1238
1239         /* setup mailbox inbox registerss */
1240         mbx.phys_addr_low = LSD(tx->phys_addr);
1241         mbx.phys_addr_high = MSD(tx->phys_addr);
1242         mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1243         mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1244         mbx.size = tx->num_desc;
1245         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1246                 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1247                         msix_vector = adapter->drv_sds_rings + ring;
1248                 else
1249                         msix_vector = adapter->drv_sds_rings - 1;
1250                 msix_id = ahw->intr_tbl[msix_vector].id;
1251         } else {
1252                 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1253         }
1254
1255         if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1256                 mbx.intr_id = msix_id;
1257         else
1258                 mbx.intr_id = 0xffff;
1259         mbx.src = 0;
1260
1261         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1262         if (err)
1263                 return err;
1264
1265         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1266                 cmd.req.arg[0] |= (0x3 << 29);
1267
1268         if (qlcnic_sriov_pf_check(adapter))
1269                 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1270
1271         cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1272         cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1273
1274         buf = &cmd.req.arg[6];
1275         memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1276         /* send the mailbox command*/
1277         err = qlcnic_issue_cmd(adapter, &cmd);
1278         if (err) {
1279                 dev_err(&adapter->pdev->dev,
1280                         "Failed to create Tx ctx in firmware 0x%x\n", err);
1281                 goto out;
1282         }
1283         mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1284         tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1285         tx->ctx_id = mbx_out->ctx_id;
1286         if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1287             !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1288                 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1289                 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1290         }
1291         dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1292                  tx->ctx_id, mbx_out->state);
1293 out:
1294         qlcnic_free_mbx_args(&cmd);
1295         return err;
1296 }
1297
1298 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1299                                       u8 num_sds_ring)
1300 {
1301         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1302         struct qlcnic_host_sds_ring *sds_ring;
1303         struct qlcnic_host_rds_ring *rds_ring;
1304         u16 adapter_state = adapter->is_up;
1305         u8 ring;
1306         int ret;
1307
1308         netif_device_detach(netdev);
1309
1310         if (netif_running(netdev))
1311                 __qlcnic_down(adapter, netdev);
1312
1313         qlcnic_detach(adapter);
1314
1315         adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1316         adapter->ahw->diag_test = test;
1317         adapter->ahw->linkup = 0;
1318
1319         ret = qlcnic_attach(adapter);
1320         if (ret) {
1321                 netif_device_attach(netdev);
1322                 return ret;
1323         }
1324
1325         ret = qlcnic_fw_create_ctx(adapter);
1326         if (ret) {
1327                 qlcnic_detach(adapter);
1328                 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1329                         adapter->drv_sds_rings = num_sds_ring;
1330                         qlcnic_attach(adapter);
1331                 }
1332                 netif_device_attach(netdev);
1333                 return ret;
1334         }
1335
1336         for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1337                 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1338                 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1339         }
1340
1341         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1342                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1343                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1344                         qlcnic_83xx_enable_intr(adapter, sds_ring);
1345                 }
1346         }
1347
1348         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1349                 /* disable and free mailbox interrupt */
1350                 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1351                         qlcnic_83xx_enable_mbx_poll(adapter);
1352                         qlcnic_83xx_free_mbx_intr(adapter);
1353                 }
1354                 adapter->ahw->loopback_state = 0;
1355                 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1356         }
1357
1358         set_bit(__QLCNIC_DEV_UP, &adapter->state);
1359         return 0;
1360 }
1361
1362 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1363                                       u8 drv_sds_rings)
1364 {
1365         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1366         struct qlcnic_host_sds_ring *sds_ring;
1367         int ring, err;
1368
1369         clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1370         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1371                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1372                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1373                         qlcnic_83xx_disable_intr(adapter, sds_ring);
1374                         if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1375                                 qlcnic_83xx_enable_mbx_poll(adapter);
1376                 }
1377         }
1378
1379         qlcnic_fw_destroy_ctx(adapter);
1380         qlcnic_detach(adapter);
1381
1382         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1383                 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1384                         err = qlcnic_83xx_setup_mbx_intr(adapter);
1385                         qlcnic_83xx_disable_mbx_poll(adapter);
1386                         if (err) {
1387                                 dev_err(&adapter->pdev->dev,
1388                                         "%s: failed to setup mbx interrupt\n",
1389                                         __func__);
1390                                 goto out;
1391                         }
1392                 }
1393         }
1394         adapter->ahw->diag_test = 0;
1395         adapter->drv_sds_rings = drv_sds_rings;
1396
1397         if (qlcnic_attach(adapter))
1398                 goto out;
1399
1400         if (netif_running(netdev))
1401                 __qlcnic_up(adapter, netdev);
1402
1403         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST &&
1404             !(adapter->flags & QLCNIC_MSIX_ENABLED))
1405                 qlcnic_83xx_disable_mbx_poll(adapter);
1406 out:
1407         netif_device_attach(netdev);
1408 }
1409
1410 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1411                            u32 beacon)
1412 {
1413         struct qlcnic_cmd_args cmd;
1414         u32 mbx_in;
1415         int i, status = 0;
1416
1417         if (state) {
1418                 /* Get LED configuration */
1419                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1420                                                QLCNIC_CMD_GET_LED_CONFIG);
1421                 if (status)
1422                         return status;
1423
1424                 status = qlcnic_issue_cmd(adapter, &cmd);
1425                 if (status) {
1426                         dev_err(&adapter->pdev->dev,
1427                                 "Get led config failed.\n");
1428                         goto mbx_err;
1429                 } else {
1430                         for (i = 0; i < 4; i++)
1431                                 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1432                 }
1433                 qlcnic_free_mbx_args(&cmd);
1434                 /* Set LED Configuration */
1435                 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1436                           LSW(QLC_83XX_LED_CONFIG);
1437                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1438                                                QLCNIC_CMD_SET_LED_CONFIG);
1439                 if (status)
1440                         return status;
1441
1442                 cmd.req.arg[1] = mbx_in;
1443                 cmd.req.arg[2] = mbx_in;
1444                 cmd.req.arg[3] = mbx_in;
1445                 if (beacon)
1446                         cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1447                 status = qlcnic_issue_cmd(adapter, &cmd);
1448                 if (status) {
1449                         dev_err(&adapter->pdev->dev,
1450                                 "Set led config failed.\n");
1451                 }
1452 mbx_err:
1453                 qlcnic_free_mbx_args(&cmd);
1454                 return status;
1455
1456         } else {
1457                 /* Restoring default LED configuration */
1458                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1459                                                QLCNIC_CMD_SET_LED_CONFIG);
1460                 if (status)
1461                         return status;
1462
1463                 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1464                 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1465                 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1466                 if (beacon)
1467                         cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1468                 status = qlcnic_issue_cmd(adapter, &cmd);
1469                 if (status)
1470                         dev_err(&adapter->pdev->dev,
1471                                 "Restoring led config failed.\n");
1472                 qlcnic_free_mbx_args(&cmd);
1473                 return status;
1474         }
1475 }
1476
1477 int  qlcnic_83xx_set_led(struct net_device *netdev,
1478                          enum ethtool_phys_id_state state)
1479 {
1480         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1481         int err = -EIO, active = 1;
1482
1483         if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1484                 netdev_warn(netdev,
1485                             "LED test is not supported in non-privileged mode\n");
1486                 return -EOPNOTSUPP;
1487         }
1488
1489         switch (state) {
1490         case ETHTOOL_ID_ACTIVE:
1491                 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1492                         return -EBUSY;
1493
1494                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1495                         break;
1496
1497                 err = qlcnic_83xx_config_led(adapter, active, 0);
1498                 if (err)
1499                         netdev_err(netdev, "Failed to set LED blink state\n");
1500                 break;
1501         case ETHTOOL_ID_INACTIVE:
1502                 active = 0;
1503
1504                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1505                         break;
1506
1507                 err = qlcnic_83xx_config_led(adapter, active, 0);
1508                 if (err)
1509                         netdev_err(netdev, "Failed to reset LED blink state\n");
1510                 break;
1511
1512         default:
1513                 return -EINVAL;
1514         }
1515
1516         if (!active || err)
1517                 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1518
1519         return err;
1520 }
1521
1522 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable)
1523 {
1524         struct qlcnic_cmd_args cmd;
1525         int status;
1526
1527         if (qlcnic_sriov_vf_check(adapter))
1528                 return;
1529
1530         if (enable)
1531                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1532                                                QLCNIC_CMD_INIT_NIC_FUNC);
1533         else
1534                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1535                                                QLCNIC_CMD_STOP_NIC_FUNC);
1536
1537         if (status)
1538                 return;
1539
1540         cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES;
1541
1542         if (adapter->dcb)
1543                 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1544
1545         status = qlcnic_issue_cmd(adapter, &cmd);
1546         if (status)
1547                 dev_err(&adapter->pdev->dev,
1548                         "Failed to %s in NIC IDC function event.\n",
1549                         (enable ? "register" : "unregister"));
1550
1551         qlcnic_free_mbx_args(&cmd);
1552 }
1553
1554 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1555 {
1556         struct qlcnic_cmd_args cmd;
1557         int err;
1558
1559         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1560         if (err)
1561                 return err;
1562
1563         cmd.req.arg[1] = adapter->ahw->port_config;
1564         err = qlcnic_issue_cmd(adapter, &cmd);
1565         if (err)
1566                 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1567         qlcnic_free_mbx_args(&cmd);
1568         return err;
1569 }
1570
1571 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1572 {
1573         struct qlcnic_cmd_args cmd;
1574         int err;
1575
1576         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1577         if (err)
1578                 return err;
1579
1580         err = qlcnic_issue_cmd(adapter, &cmd);
1581         if (err)
1582                 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1583         else
1584                 adapter->ahw->port_config = cmd.rsp.arg[1];
1585         qlcnic_free_mbx_args(&cmd);
1586         return err;
1587 }
1588
1589 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1590 {
1591         int err;
1592         u32 temp;
1593         struct qlcnic_cmd_args cmd;
1594
1595         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1596         if (err)
1597                 return err;
1598
1599         temp = adapter->recv_ctx->context_id << 16;
1600         cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1601         err = qlcnic_issue_cmd(adapter, &cmd);
1602         if (err)
1603                 dev_info(&adapter->pdev->dev,
1604                          "Setup linkevent mailbox failed\n");
1605         qlcnic_free_mbx_args(&cmd);
1606         return err;
1607 }
1608
1609 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1610                                                  u32 *interface_id)
1611 {
1612         if (qlcnic_sriov_pf_check(adapter)) {
1613                 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1614         } else {
1615                 if (!qlcnic_sriov_vf_check(adapter))
1616                         *interface_id = adapter->recv_ctx->context_id << 16;
1617         }
1618 }
1619
1620 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1621 {
1622         struct qlcnic_cmd_args *cmd = NULL;
1623         u32 temp = 0;
1624         int err;
1625
1626         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1627                 return -EIO;
1628
1629         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1630         if (!cmd)
1631                 return -ENOMEM;
1632
1633         err = qlcnic_alloc_mbx_args(cmd, adapter,
1634                                     QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1635         if (err)
1636                 goto out;
1637
1638         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1639         qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1640         cmd->req.arg[1] = mode | temp;
1641         err = qlcnic_issue_cmd(adapter, cmd);
1642         if (!err)
1643                 return err;
1644
1645         qlcnic_free_mbx_args(cmd);
1646
1647 out:
1648         kfree(cmd);
1649         return err;
1650 }
1651
1652 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1653 {
1654         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1655         struct qlcnic_hardware_context *ahw = adapter->ahw;
1656         u8 drv_sds_rings = adapter->drv_sds_rings;
1657         u8 drv_tx_rings = adapter->drv_tx_rings;
1658         int ret = 0, loop = 0;
1659
1660         if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1661                 netdev_warn(netdev,
1662                             "Loopback test not supported in non privileged mode\n");
1663                 return -ENOTSUPP;
1664         }
1665
1666         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1667                 netdev_info(netdev, "Device is resetting\n");
1668                 return -EBUSY;
1669         }
1670
1671         if (qlcnic_get_diag_lock(adapter)) {
1672                 netdev_info(netdev, "Device is in diagnostics mode\n");
1673                 return -EBUSY;
1674         }
1675
1676         netdev_info(netdev, "%s loopback test in progress\n",
1677                     mode == QLCNIC_ILB_MODE ? "internal" : "external");
1678
1679         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1680                                          drv_sds_rings);
1681         if (ret)
1682                 goto fail_diag_alloc;
1683
1684         ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1685         if (ret)
1686                 goto free_diag_res;
1687
1688         /* Poll for link up event before running traffic */
1689         do {
1690                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1691
1692                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1693                         netdev_info(netdev,
1694                                     "Device is resetting, free LB test resources\n");
1695                         ret = -EBUSY;
1696                         goto free_diag_res;
1697                 }
1698                 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1699                         netdev_info(netdev,
1700                                     "Firmware didn't sent link up event to loopback request\n");
1701                         ret = -ETIMEDOUT;
1702                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1703                         goto free_diag_res;
1704                 }
1705         } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1706
1707         /* Make sure carrier is off and queue is stopped during loopback */
1708         if (netif_running(netdev)) {
1709                 netif_carrier_off(netdev);
1710                 netif_tx_stop_all_queues(netdev);
1711         }
1712
1713         ret = qlcnic_do_lb_test(adapter, mode);
1714
1715         qlcnic_83xx_clear_lb_mode(adapter, mode);
1716
1717 free_diag_res:
1718         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1719
1720 fail_diag_alloc:
1721         adapter->drv_sds_rings = drv_sds_rings;
1722         adapter->drv_tx_rings = drv_tx_rings;
1723         qlcnic_release_diag_lock(adapter);
1724         return ret;
1725 }
1726
1727 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1728                                              u32 *max_wait_count)
1729 {
1730         struct qlcnic_hardware_context *ahw = adapter->ahw;
1731         int temp;
1732
1733         netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1734                     ahw->extend_lb_time);
1735         temp = ahw->extend_lb_time * 1000;
1736         *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1737         ahw->extend_lb_time = 0;
1738 }
1739
1740 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1741 {
1742         struct qlcnic_hardware_context *ahw = adapter->ahw;
1743         struct net_device *netdev = adapter->netdev;
1744         u32 config, max_wait_count;
1745         int status = 0, loop = 0;
1746
1747         ahw->extend_lb_time = 0;
1748         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1749         status = qlcnic_83xx_get_port_config(adapter);
1750         if (status)
1751                 return status;
1752
1753         config = ahw->port_config;
1754
1755         /* Check if port is already in loopback mode */
1756         if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1757             (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1758                 netdev_err(netdev,
1759                            "Port already in Loopback mode.\n");
1760                 return -EINPROGRESS;
1761         }
1762
1763         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1764
1765         if (mode == QLCNIC_ILB_MODE)
1766                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1767         if (mode == QLCNIC_ELB_MODE)
1768                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1769
1770         status = qlcnic_83xx_set_port_config(adapter);
1771         if (status) {
1772                 netdev_err(netdev,
1773                            "Failed to Set Loopback Mode = 0x%x.\n",
1774                            ahw->port_config);
1775                 ahw->port_config = config;
1776                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1777                 return status;
1778         }
1779
1780         /* Wait for Link and IDC Completion AEN */
1781         do {
1782                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1783
1784                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1785                         netdev_info(netdev,
1786                                     "Device is resetting, free LB test resources\n");
1787                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1788                         return -EBUSY;
1789                 }
1790
1791                 if (ahw->extend_lb_time)
1792                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1793                                                          &max_wait_count);
1794
1795                 if (loop++ > max_wait_count) {
1796                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1797                                    __func__);
1798                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1799                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1800                         return -ETIMEDOUT;
1801                 }
1802         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1803
1804         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1805                                   QLCNIC_MAC_ADD);
1806         return status;
1807 }
1808
1809 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1810 {
1811         struct qlcnic_hardware_context *ahw = adapter->ahw;
1812         u32 config = ahw->port_config, max_wait_count;
1813         struct net_device *netdev = adapter->netdev;
1814         int status = 0, loop = 0;
1815
1816         ahw->extend_lb_time = 0;
1817         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1818         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1819         if (mode == QLCNIC_ILB_MODE)
1820                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1821         if (mode == QLCNIC_ELB_MODE)
1822                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1823
1824         status = qlcnic_83xx_set_port_config(adapter);
1825         if (status) {
1826                 netdev_err(netdev,
1827                            "Failed to Clear Loopback Mode = 0x%x.\n",
1828                            ahw->port_config);
1829                 ahw->port_config = config;
1830                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1831                 return status;
1832         }
1833
1834         /* Wait for Link and IDC Completion AEN */
1835         do {
1836                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1837
1838                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1839                         netdev_info(netdev,
1840                                     "Device is resetting, free LB test resources\n");
1841                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1842                         return -EBUSY;
1843                 }
1844
1845                 if (ahw->extend_lb_time)
1846                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1847                                                          &max_wait_count);
1848
1849                 if (loop++ > max_wait_count) {
1850                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1851                                    __func__);
1852                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1853                         return -ETIMEDOUT;
1854                 }
1855         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1856
1857         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1858                                   QLCNIC_MAC_DEL);
1859         return status;
1860 }
1861
1862 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1863                                                 u32 *interface_id)
1864 {
1865         if (qlcnic_sriov_pf_check(adapter)) {
1866                 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1867         } else {
1868                 if (!qlcnic_sriov_vf_check(adapter))
1869                         *interface_id = adapter->recv_ctx->context_id << 16;
1870         }
1871 }
1872
1873 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1874                                int mode)
1875 {
1876         int err;
1877         u32 temp = 0, temp_ip;
1878         struct qlcnic_cmd_args cmd;
1879
1880         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1881                                     QLCNIC_CMD_CONFIGURE_IP_ADDR);
1882         if (err)
1883                 return;
1884
1885         qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1886
1887         if (mode == QLCNIC_IP_UP)
1888                 cmd.req.arg[1] = 1 | temp;
1889         else
1890                 cmd.req.arg[1] = 2 | temp;
1891
1892         /*
1893          * Adapter needs IP address in network byte order.
1894          * But hardware mailbox registers go through writel(), hence IP address
1895          * gets swapped on big endian architecture.
1896          * To negate swapping of writel() on big endian architecture
1897          * use swab32(value).
1898          */
1899
1900         temp_ip = swab32(ntohl(ip));
1901         memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1902         err = qlcnic_issue_cmd(adapter, &cmd);
1903         if (err != QLCNIC_RCODE_SUCCESS)
1904                 dev_err(&adapter->netdev->dev,
1905                         "could not notify %s IP 0x%x request\n",
1906                         (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1907
1908         qlcnic_free_mbx_args(&cmd);
1909 }
1910
1911 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1912 {
1913         int err;
1914         u32 temp, arg1;
1915         struct qlcnic_cmd_args cmd;
1916         int lro_bit_mask;
1917
1918         lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1919
1920         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1921                 return 0;
1922
1923         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1924         if (err)
1925                 return err;
1926
1927         temp = adapter->recv_ctx->context_id << 16;
1928         arg1 = lro_bit_mask | temp;
1929         cmd.req.arg[1] = arg1;
1930
1931         err = qlcnic_issue_cmd(adapter, &cmd);
1932         if (err)
1933                 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1934         qlcnic_free_mbx_args(&cmd);
1935
1936         return err;
1937 }
1938
1939 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1940 {
1941         int err;
1942         u32 word;
1943         struct qlcnic_cmd_args cmd;
1944         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1945                             0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1946                             0x255b0ec26d5a56daULL };
1947
1948         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1949         if (err)
1950                 return err;
1951         /*
1952          * RSS request:
1953          * bits 3-0: Rsvd
1954          *      5-4: hash_type_ipv4
1955          *      7-6: hash_type_ipv6
1956          *        8: enable
1957          *        9: use indirection table
1958          *    16-31: indirection table mask
1959          */
1960         word =  ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1961                 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1962                 ((u32)(enable & 0x1) << 8) |
1963                 ((0x7ULL) << 16);
1964         cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1965         cmd.req.arg[2] = word;
1966         memcpy(&cmd.req.arg[4], key, sizeof(key));
1967
1968         err = qlcnic_issue_cmd(adapter, &cmd);
1969
1970         if (err)
1971                 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1972         qlcnic_free_mbx_args(&cmd);
1973
1974         return err;
1975
1976 }
1977
1978 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1979                                                  u32 *interface_id)
1980 {
1981         if (qlcnic_sriov_pf_check(adapter)) {
1982                 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1983         } else {
1984                 if (!qlcnic_sriov_vf_check(adapter))
1985                         *interface_id = adapter->recv_ctx->context_id << 16;
1986         }
1987 }
1988
1989 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1990                                    u16 vlan_id, u8 op)
1991 {
1992         struct qlcnic_cmd_args *cmd = NULL;
1993         struct qlcnic_macvlan_mbx mv;
1994         u32 *buf, temp = 0;
1995         int err;
1996
1997         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1998                 return -EIO;
1999
2000         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
2001         if (!cmd)
2002                 return -ENOMEM;
2003
2004         err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
2005         if (err)
2006                 goto out;
2007
2008         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
2009
2010         if (vlan_id)
2011                 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2012                      QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2013
2014         cmd->req.arg[1] = op | (1 << 8);
2015         qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
2016         cmd->req.arg[1] |= temp;
2017         mv.vlan = vlan_id;
2018         mv.mac_addr0 = addr[0];
2019         mv.mac_addr1 = addr[1];
2020         mv.mac_addr2 = addr[2];
2021         mv.mac_addr3 = addr[3];
2022         mv.mac_addr4 = addr[4];
2023         mv.mac_addr5 = addr[5];
2024         buf = &cmd->req.arg[2];
2025         memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2026         err = qlcnic_issue_cmd(adapter, cmd);
2027         if (!err)
2028                 return err;
2029
2030         qlcnic_free_mbx_args(cmd);
2031 out:
2032         kfree(cmd);
2033         return err;
2034 }
2035
2036 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2037                                   u16 vlan_id)
2038 {
2039         u8 mac[ETH_ALEN];
2040         memcpy(&mac, addr, ETH_ALEN);
2041         qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2042 }
2043
2044 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2045                                u8 type, struct qlcnic_cmd_args *cmd)
2046 {
2047         switch (type) {
2048         case QLCNIC_SET_STATION_MAC:
2049         case QLCNIC_SET_FAC_DEF_MAC:
2050                 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2051                 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2052                 break;
2053         }
2054         cmd->req.arg[1] = type;
2055 }
2056
2057 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2058                                 u8 function)
2059 {
2060         int err, i;
2061         struct qlcnic_cmd_args cmd;
2062         u32 mac_low, mac_high;
2063
2064         function = 0;
2065         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2066         if (err)
2067                 return err;
2068
2069         qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2070         err = qlcnic_issue_cmd(adapter, &cmd);
2071
2072         if (err == QLCNIC_RCODE_SUCCESS) {
2073                 mac_low = cmd.rsp.arg[1];
2074                 mac_high = cmd.rsp.arg[2];
2075
2076                 for (i = 0; i < 2; i++)
2077                         mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2078                 for (i = 2; i < 6; i++)
2079                         mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2080         } else {
2081                 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2082                         err);
2083                 err = -EIO;
2084         }
2085         qlcnic_free_mbx_args(&cmd);
2086         return err;
2087 }
2088
2089 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2090 {
2091         int err;
2092         u16 temp;
2093         struct qlcnic_cmd_args cmd;
2094         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2095
2096         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2097                 return;
2098
2099         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2100         if (err)
2101                 return;
2102
2103         if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2104                 temp = adapter->recv_ctx->context_id;
2105                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2106                 temp = coal->rx_time_us;
2107                 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2108         } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2109                 temp = adapter->tx_ring->ctx_id;
2110                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2111                 temp = coal->tx_time_us;
2112                 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2113         }
2114         cmd.req.arg[3] = coal->flag;
2115         err = qlcnic_issue_cmd(adapter, &cmd);
2116         if (err != QLCNIC_RCODE_SUCCESS)
2117                 dev_info(&adapter->pdev->dev,
2118                          "Failed to send interrupt coalescence parameters\n");
2119         qlcnic_free_mbx_args(&cmd);
2120 }
2121
2122 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2123                                         u32 data[])
2124 {
2125         struct qlcnic_hardware_context *ahw = adapter->ahw;
2126         u8 link_status, duplex;
2127         /* link speed */
2128         link_status = LSB(data[3]) & 1;
2129         if (link_status) {
2130                 ahw->link_speed = MSW(data[2]);
2131                 duplex = LSB(MSW(data[3]));
2132                 if (duplex)
2133                         ahw->link_duplex = DUPLEX_FULL;
2134                 else
2135                         ahw->link_duplex = DUPLEX_HALF;
2136         } else {
2137                 ahw->link_speed = SPEED_UNKNOWN;
2138                 ahw->link_duplex = DUPLEX_UNKNOWN;
2139         }
2140
2141         ahw->link_autoneg = MSB(MSW(data[3]));
2142         ahw->module_type = MSB(LSW(data[3]));
2143         ahw->has_link_events = 1;
2144         qlcnic_advert_link_change(adapter, link_status);
2145 }
2146
2147 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2148 {
2149         struct qlcnic_adapter *adapter = data;
2150         struct qlcnic_mailbox *mbx;
2151         u32 mask, resp, event;
2152         unsigned long flags;
2153
2154         mbx = adapter->ahw->mailbox;
2155         spin_lock_irqsave(&mbx->aen_lock, flags);
2156         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2157         if (!(resp & QLCNIC_SET_OWNER))
2158                 goto out;
2159
2160         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2161         if (event &  QLCNIC_MBX_ASYNC_EVENT)
2162                 __qlcnic_83xx_process_aen(adapter);
2163         else
2164                 qlcnic_83xx_notify_mbx_response(mbx);
2165
2166 out:
2167         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2168         writel(0, adapter->ahw->pci_base0 + mask);
2169         spin_unlock_irqrestore(&mbx->aen_lock, flags);
2170         return IRQ_HANDLED;
2171 }
2172
2173 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
2174 {
2175         int err = -EIO;
2176         struct qlcnic_cmd_args cmd;
2177
2178         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2179                 dev_err(&adapter->pdev->dev,
2180                         "%s: Error, invoked by non management func\n",
2181                         __func__);
2182                 return err;
2183         }
2184
2185         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
2186         if (err)
2187                 return err;
2188
2189         cmd.req.arg[1] = (port & 0xf) | BIT_4;
2190         err = qlcnic_issue_cmd(adapter, &cmd);
2191
2192         if (err != QLCNIC_RCODE_SUCCESS) {
2193                 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
2194                         err);
2195                 err = -EIO;
2196         }
2197         qlcnic_free_mbx_args(&cmd);
2198
2199         return err;
2200
2201 }
2202
2203 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2204                              struct qlcnic_info *nic)
2205 {
2206         int i, err = -EIO;
2207         struct qlcnic_cmd_args cmd;
2208
2209         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2210                 dev_err(&adapter->pdev->dev,
2211                         "%s: Error, invoked by non management func\n",
2212                         __func__);
2213                 return err;
2214         }
2215
2216         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2217         if (err)
2218                 return err;
2219
2220         cmd.req.arg[1] = (nic->pci_func << 16);
2221         cmd.req.arg[2] = 0x1 << 16;
2222         cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2223         cmd.req.arg[4] = nic->capabilities;
2224         cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2225         cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2226         cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2227         for (i = 8; i < 32; i++)
2228                 cmd.req.arg[i] = 0;
2229
2230         err = qlcnic_issue_cmd(adapter, &cmd);
2231
2232         if (err != QLCNIC_RCODE_SUCCESS) {
2233                 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2234                         err);
2235                 err = -EIO;
2236         }
2237
2238         qlcnic_free_mbx_args(&cmd);
2239
2240         return err;
2241 }
2242
2243 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2244                              struct qlcnic_info *npar_info, u8 func_id)
2245 {
2246         int err;
2247         u32 temp;
2248         u8 op = 0;
2249         struct qlcnic_cmd_args cmd;
2250         struct qlcnic_hardware_context *ahw = adapter->ahw;
2251
2252         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2253         if (err)
2254                 return err;
2255
2256         if (func_id != ahw->pci_func) {
2257                 temp = func_id << 16;
2258                 cmd.req.arg[1] = op | BIT_31 | temp;
2259         } else {
2260                 cmd.req.arg[1] = ahw->pci_func << 16;
2261         }
2262         err = qlcnic_issue_cmd(adapter, &cmd);
2263         if (err) {
2264                 dev_info(&adapter->pdev->dev,
2265                          "Failed to get nic info %d\n", err);
2266                 goto out;
2267         }
2268
2269         npar_info->op_type = cmd.rsp.arg[1];
2270         npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2271         npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2272         npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2273         npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2274         npar_info->capabilities = cmd.rsp.arg[4];
2275         npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2276         npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2277         npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2278         npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2279         npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2280         npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2281         if (cmd.rsp.arg[8] & 0x1)
2282                 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2283         if (cmd.rsp.arg[8] & 0x10000) {
2284                 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2285                 npar_info->max_linkspeed_reg_offset = temp;
2286         }
2287
2288         memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2289                sizeof(ahw->extra_capability));
2290
2291 out:
2292         qlcnic_free_mbx_args(&cmd);
2293         return err;
2294 }
2295
2296 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2297                              struct qlcnic_pci_info *pci_info)
2298 {
2299         struct qlcnic_hardware_context *ahw = adapter->ahw;
2300         struct device *dev = &adapter->pdev->dev;
2301         struct qlcnic_cmd_args cmd;
2302         int i, err = 0, j = 0;
2303         u32 temp;
2304
2305         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2306         if (err)
2307                 return err;
2308
2309         err = qlcnic_issue_cmd(adapter, &cmd);
2310
2311         ahw->act_pci_func = 0;
2312         if (err == QLCNIC_RCODE_SUCCESS) {
2313                 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2314                 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) {
2315                         pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2316                         pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2317                         i++;
2318                         pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2319                         if (pci_info->type == QLCNIC_TYPE_NIC)
2320                                 ahw->act_pci_func++;
2321                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2322                         pci_info->default_port = temp;
2323                         i++;
2324                         pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2325                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2326                         pci_info->tx_max_bw = temp;
2327                         i = i + 2;
2328                         memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2329                         i++;
2330                         memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2331                         i = i + 3;
2332                 }
2333         } else {
2334                 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2335                 err = -EIO;
2336         }
2337
2338         qlcnic_free_mbx_args(&cmd);
2339
2340         return err;
2341 }
2342
2343 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2344 {
2345         int i, index, err;
2346         u8 max_ints;
2347         u32 val, temp, type;
2348         struct qlcnic_cmd_args cmd;
2349
2350         max_ints = adapter->ahw->num_msix - 1;
2351         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2352         if (err)
2353                 return err;
2354
2355         cmd.req.arg[1] = max_ints;
2356
2357         if (qlcnic_sriov_vf_check(adapter))
2358                 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2359
2360         for (i = 0, index = 2; i < max_ints; i++) {
2361                 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2362                 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2363                 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2364                         val |= (adapter->ahw->intr_tbl[i].id << 16);
2365                 cmd.req.arg[index++] = val;
2366         }
2367         err = qlcnic_issue_cmd(adapter, &cmd);
2368         if (err) {
2369                 dev_err(&adapter->pdev->dev,
2370                         "Failed to configure interrupts 0x%x\n", err);
2371                 goto out;
2372         }
2373
2374         max_ints = cmd.rsp.arg[1];
2375         for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2376                 val = cmd.rsp.arg[index];
2377                 if (LSB(val)) {
2378                         dev_info(&adapter->pdev->dev,
2379                                  "Can't configure interrupt %d\n",
2380                                  adapter->ahw->intr_tbl[i].id);
2381                         continue;
2382                 }
2383                 if (op_type) {
2384                         adapter->ahw->intr_tbl[i].id = MSW(val);
2385                         adapter->ahw->intr_tbl[i].enabled = 1;
2386                         temp = cmd.rsp.arg[index + 1];
2387                         adapter->ahw->intr_tbl[i].src = temp;
2388                 } else {
2389                         adapter->ahw->intr_tbl[i].id = i;
2390                         adapter->ahw->intr_tbl[i].enabled = 0;
2391                         adapter->ahw->intr_tbl[i].src = 0;
2392                 }
2393         }
2394 out:
2395         qlcnic_free_mbx_args(&cmd);
2396         return err;
2397 }
2398
2399 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2400 {
2401         int id, timeout = 0;
2402         u32 status = 0;
2403
2404         while (status == 0) {
2405                 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2406                 if (status)
2407                         break;
2408
2409                 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2410                         id = QLC_SHARED_REG_RD32(adapter,
2411                                                  QLCNIC_FLASH_LOCK_OWNER);
2412                         dev_err(&adapter->pdev->dev,
2413                                 "%s: failed, lock held by %d\n", __func__, id);
2414                         return -EIO;
2415                 }
2416                 usleep_range(1000, 2000);
2417         }
2418
2419         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2420         return 0;
2421 }
2422
2423 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2424 {
2425         QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2426         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2427 }
2428
2429 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2430                                       u32 flash_addr, u8 *p_data,
2431                                       int count)
2432 {
2433         u32 word, range, flash_offset, addr = flash_addr, ret;
2434         ulong indirect_add, direct_window;
2435         int i, err = 0;
2436
2437         flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2438         if (addr & 0x3) {
2439                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2440                 return -EIO;
2441         }
2442
2443         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2444                                      (addr));
2445
2446         range = flash_offset + (count * sizeof(u32));
2447         /* Check if data is spread across multiple sectors */
2448         if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2449
2450                 /* Multi sector read */
2451                 for (i = 0; i < count; i++) {
2452                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2453                         ret = QLCRD32(adapter, indirect_add, &err);
2454                         if (err == -EIO)
2455                                 return err;
2456
2457                         word = ret;
2458                         *(u32 *)p_data  = word;
2459                         p_data = p_data + 4;
2460                         addr = addr + 4;
2461                         flash_offset = flash_offset + 4;
2462
2463                         if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2464                                 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2465                                 /* This write is needed once for each sector */
2466                                 qlcnic_83xx_wrt_reg_indirect(adapter,
2467                                                              direct_window,
2468                                                              (addr));
2469                                 flash_offset = 0;
2470                         }
2471                 }
2472         } else {
2473                 /* Single sector read */
2474                 for (i = 0; i < count; i++) {
2475                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2476                         ret = QLCRD32(adapter, indirect_add, &err);
2477                         if (err == -EIO)
2478                                 return err;
2479
2480                         word = ret;
2481                         *(u32 *)p_data  = word;
2482                         p_data = p_data + 4;
2483                         addr = addr + 4;
2484                 }
2485         }
2486
2487         return 0;
2488 }
2489
2490 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2491 {
2492         u32 status;
2493         int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2494         int err = 0;
2495
2496         do {
2497                 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2498                 if (err == -EIO)
2499                         return err;
2500
2501                 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2502                     QLC_83XX_FLASH_STATUS_READY)
2503                         break;
2504
2505                 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2506         } while (--retries);
2507
2508         if (!retries)
2509                 return -EIO;
2510
2511         return 0;
2512 }
2513
2514 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2515 {
2516         int ret;
2517         u32 cmd;
2518         cmd = adapter->ahw->fdt.write_statusreg_cmd;
2519         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2520                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2521         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2522                                      adapter->ahw->fdt.write_enable_bits);
2523         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2524                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2525         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2526         if (ret)
2527                 return -EIO;
2528
2529         return 0;
2530 }
2531
2532 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2533 {
2534         int ret;
2535
2536         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2537                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2538                                      adapter->ahw->fdt.write_statusreg_cmd));
2539         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2540                                      adapter->ahw->fdt.write_disable_bits);
2541         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2542                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2543         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2544         if (ret)
2545                 return -EIO;
2546
2547         return 0;
2548 }
2549
2550 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2551 {
2552         int ret, err = 0;
2553         u32 mfg_id;
2554
2555         if (qlcnic_83xx_lock_flash(adapter))
2556                 return -EIO;
2557
2558         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2559                                      QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2560         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2561                                      QLC_83XX_FLASH_READ_CTRL);
2562         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2563         if (ret) {
2564                 qlcnic_83xx_unlock_flash(adapter);
2565                 return -EIO;
2566         }
2567
2568         mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2569         if (err == -EIO) {
2570                 qlcnic_83xx_unlock_flash(adapter);
2571                 return err;
2572         }
2573
2574         adapter->flash_mfg_id = (mfg_id & 0xFF);
2575         qlcnic_83xx_unlock_flash(adapter);
2576
2577         return 0;
2578 }
2579
2580 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2581 {
2582         int count, fdt_size, ret = 0;
2583
2584         fdt_size = sizeof(struct qlcnic_fdt);
2585         count = fdt_size / sizeof(u32);
2586
2587         if (qlcnic_83xx_lock_flash(adapter))
2588                 return -EIO;
2589
2590         memset(&adapter->ahw->fdt, 0, fdt_size);
2591         ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2592                                                 (u8 *)&adapter->ahw->fdt,
2593                                                 count);
2594
2595         qlcnic_83xx_unlock_flash(adapter);
2596         return ret;
2597 }
2598
2599 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2600                                    u32 sector_start_addr)
2601 {
2602         u32 reversed_addr, addr1, addr2, cmd;
2603         int ret = -EIO;
2604
2605         if (qlcnic_83xx_lock_flash(adapter) != 0)
2606                 return -EIO;
2607
2608         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2609                 ret = qlcnic_83xx_enable_flash_write(adapter);
2610                 if (ret) {
2611                         qlcnic_83xx_unlock_flash(adapter);
2612                         dev_err(&adapter->pdev->dev,
2613                                 "%s failed at %d\n",
2614                                 __func__, __LINE__);
2615                         return ret;
2616                 }
2617         }
2618
2619         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2620         if (ret) {
2621                 qlcnic_83xx_unlock_flash(adapter);
2622                 dev_err(&adapter->pdev->dev,
2623                         "%s: failed at %d\n", __func__, __LINE__);
2624                 return -EIO;
2625         }
2626
2627         addr1 = (sector_start_addr & 0xFF) << 16;
2628         addr2 = (sector_start_addr & 0xFF0000) >> 16;
2629         reversed_addr = addr1 | addr2;
2630
2631         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2632                                      reversed_addr);
2633         cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2634         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2635                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2636         else
2637                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2638                                              QLC_83XX_FLASH_OEM_ERASE_SIG);
2639         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2640                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2641
2642         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2643         if (ret) {
2644                 qlcnic_83xx_unlock_flash(adapter);
2645                 dev_err(&adapter->pdev->dev,
2646                         "%s: failed at %d\n", __func__, __LINE__);
2647                 return -EIO;
2648         }
2649
2650         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2651                 ret = qlcnic_83xx_disable_flash_write(adapter);
2652                 if (ret) {
2653                         qlcnic_83xx_unlock_flash(adapter);
2654                         dev_err(&adapter->pdev->dev,
2655                                 "%s: failed at %d\n", __func__, __LINE__);
2656                         return ret;
2657                 }
2658         }
2659
2660         qlcnic_83xx_unlock_flash(adapter);
2661
2662         return 0;
2663 }
2664
2665 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2666                               u32 *p_data)
2667 {
2668         int ret = -EIO;
2669         u32 addr1 = 0x00800000 | (addr >> 2);
2670
2671         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2672         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2673         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2674                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2675         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2676         if (ret) {
2677                 dev_err(&adapter->pdev->dev,
2678                         "%s: failed at %d\n", __func__, __LINE__);
2679                 return -EIO;
2680         }
2681
2682         return 0;
2683 }
2684
2685 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2686                                  u32 *p_data, int count)
2687 {
2688         u32 temp;
2689         int ret = -EIO, err = 0;
2690
2691         if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2692             (count > QLC_83XX_FLASH_WRITE_MAX)) {
2693                 dev_err(&adapter->pdev->dev,
2694                         "%s: Invalid word count\n", __func__);
2695                 return -EIO;
2696         }
2697
2698         temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2699         if (err == -EIO)
2700                 return err;
2701
2702         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2703                                      (temp | QLC_83XX_FLASH_SPI_CTRL));
2704         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2705                                      QLC_83XX_FLASH_ADDR_TEMP_VAL);
2706
2707         /* First DWORD write */
2708         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2709         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2710                                      QLC_83XX_FLASH_FIRST_MS_PATTERN);
2711         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2712         if (ret) {
2713                 dev_err(&adapter->pdev->dev,
2714                         "%s: failed at %d\n", __func__, __LINE__);
2715                 return -EIO;
2716         }
2717
2718         count--;
2719         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2720                                      QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2721         /* Second to N-1 DWORD writes */
2722         while (count != 1) {
2723                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2724                                              *p_data++);
2725                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2726                                              QLC_83XX_FLASH_SECOND_MS_PATTERN);
2727                 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2728                 if (ret) {
2729                         dev_err(&adapter->pdev->dev,
2730                                 "%s: failed at %d\n", __func__, __LINE__);
2731                         return -EIO;
2732                 }
2733                 count--;
2734         }
2735
2736         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2737                                      QLC_83XX_FLASH_ADDR_TEMP_VAL |
2738                                      (addr >> 2));
2739         /* Last DWORD write */
2740         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2741         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2742                                      QLC_83XX_FLASH_LAST_MS_PATTERN);
2743         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2744         if (ret) {
2745                 dev_err(&adapter->pdev->dev,
2746                         "%s: failed at %d\n", __func__, __LINE__);
2747                 return -EIO;
2748         }
2749
2750         ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2751         if (err == -EIO)
2752                 return err;
2753
2754         if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2755                 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2756                         __func__, __LINE__);
2757                 /* Operation failed, clear error bit */
2758                 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2759                 if (err == -EIO)
2760                         return err;
2761
2762                 qlcnic_83xx_wrt_reg_indirect(adapter,
2763                                              QLC_83XX_FLASH_SPI_CONTROL,
2764                                              (temp | QLC_83XX_FLASH_SPI_CTRL));
2765         }
2766
2767         return 0;
2768 }
2769
2770 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2771 {
2772         u32 val, id;
2773
2774         val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2775
2776         /* Check if recovery need to be performed by the calling function */
2777         if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2778                 val = val & ~0x3F;
2779                 val = val | ((adapter->portnum << 2) |
2780                              QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2781                 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2782                 dev_info(&adapter->pdev->dev,
2783                          "%s: lock recovery initiated\n", __func__);
2784                 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2785                 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2786                 id = ((val >> 2) & 0xF);
2787                 if (id == adapter->portnum) {
2788                         val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2789                         val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2790                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2791                         /* Force release the lock */
2792                         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2793                         /* Clear recovery bits */
2794                         val = val & ~0x3F;
2795                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2796                         dev_info(&adapter->pdev->dev,
2797                                  "%s: lock recovery completed\n", __func__);
2798                 } else {
2799                         dev_info(&adapter->pdev->dev,
2800                                  "%s: func %d to resume lock recovery process\n",
2801                                  __func__, id);
2802                 }
2803         } else {
2804                 dev_info(&adapter->pdev->dev,
2805                          "%s: lock recovery initiated by other functions\n",
2806                          __func__);
2807         }
2808 }
2809
2810 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2811 {
2812         u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2813         int max_attempt = 0;
2814
2815         while (status == 0) {
2816                 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2817                 if (status)
2818                         break;
2819
2820                 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2821                 i++;
2822
2823                 if (i == 1)
2824                         temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2825
2826                 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2827                         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2828                         if (val == temp) {
2829                                 id = val & 0xFF;
2830                                 dev_info(&adapter->pdev->dev,
2831                                          "%s: lock to be recovered from %d\n",
2832                                          __func__, id);
2833                                 qlcnic_83xx_recover_driver_lock(adapter);
2834                                 i = 0;
2835                                 max_attempt++;
2836                         } else {
2837                                 dev_err(&adapter->pdev->dev,
2838                                         "%s: failed to get lock\n", __func__);
2839                                 return -EIO;
2840                         }
2841                 }
2842
2843                 /* Force exit from while loop after few attempts */
2844                 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2845                         dev_err(&adapter->pdev->dev,
2846                                 "%s: failed to get lock\n", __func__);
2847                         return -EIO;
2848                 }
2849         }
2850
2851         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2852         lock_alive_counter = val >> 8;
2853         lock_alive_counter++;
2854         val = lock_alive_counter << 8 | adapter->portnum;
2855         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2856
2857         return 0;
2858 }
2859
2860 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2861 {
2862         u32 val, lock_alive_counter, id;
2863
2864         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2865         id = val & 0xFF;
2866         lock_alive_counter = val >> 8;
2867
2868         if (id != adapter->portnum)
2869                 dev_err(&adapter->pdev->dev,
2870                         "%s:Warning func %d is unlocking lock owned by %d\n",
2871                         __func__, adapter->portnum, id);
2872
2873         val = (lock_alive_counter << 8) | 0xFF;
2874         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2875         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2876 }
2877
2878 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2879                                 u32 *data, u32 count)
2880 {
2881         int i, j, ret = 0;
2882         u32 temp;
2883         int err = 0;
2884
2885         /* Check alignment */
2886         if (addr & 0xF)
2887                 return -EIO;
2888
2889         mutex_lock(&adapter->ahw->mem_lock);
2890         qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2891
2892         for (i = 0; i < count; i++, addr += 16) {
2893                 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2894                                      QLCNIC_ADDR_QDR_NET_MAX)) ||
2895                       (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2896                                      QLCNIC_ADDR_DDR_NET_MAX)))) {
2897                         mutex_unlock(&adapter->ahw->mem_lock);
2898                         return -EIO;
2899                 }
2900
2901                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2902                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2903                                              *data++);
2904                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2905                                              *data++);
2906                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2907                                              *data++);
2908                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2909                                              *data++);
2910                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2911                                              QLCNIC_TA_WRITE_ENABLE);
2912                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2913                                              QLCNIC_TA_WRITE_START);
2914
2915                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2916                         temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err);
2917                         if (err == -EIO) {
2918                                 mutex_unlock(&adapter->ahw->mem_lock);
2919                                 return err;
2920                         }
2921
2922                         if ((temp & TA_CTL_BUSY) == 0)
2923                                 break;
2924                 }
2925
2926                 /* Status check failure */
2927                 if (j >= MAX_CTL_CHECK) {
2928                         printk_ratelimited(KERN_WARNING
2929                                            "MS memory write failed\n");
2930                         mutex_unlock(&adapter->ahw->mem_lock);
2931                         return -EIO;
2932                 }
2933         }
2934
2935         mutex_unlock(&adapter->ahw->mem_lock);
2936
2937         return ret;
2938 }
2939
2940 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2941                              u8 *p_data, int count)
2942 {
2943         u32 word, addr = flash_addr, ret;
2944         ulong  indirect_addr;
2945         int i, err = 0;
2946
2947         if (qlcnic_83xx_lock_flash(adapter) != 0)
2948                 return -EIO;
2949
2950         if (addr & 0x3) {
2951                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2952                 qlcnic_83xx_unlock_flash(adapter);
2953                 return -EIO;
2954         }
2955
2956         for (i = 0; i < count; i++) {
2957                 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2958                                                  QLC_83XX_FLASH_DIRECT_WINDOW,
2959                                                  (addr))) {
2960                         qlcnic_83xx_unlock_flash(adapter);
2961                         return -EIO;
2962                 }
2963
2964                 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2965                 ret = QLCRD32(adapter, indirect_addr, &err);
2966                 if (err == -EIO)
2967                         return err;
2968
2969                 word = ret;
2970                 *(u32 *)p_data  = word;
2971                 p_data = p_data + 4;
2972                 addr = addr + 4;
2973         }
2974
2975         qlcnic_83xx_unlock_flash(adapter);
2976
2977         return 0;
2978 }
2979
2980 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2981 {
2982         u8 pci_func;
2983         int err;
2984         u32 config = 0, state;
2985         struct qlcnic_cmd_args cmd;
2986         struct qlcnic_hardware_context *ahw = adapter->ahw;
2987
2988         if (qlcnic_sriov_vf_check(adapter))
2989                 pci_func = adapter->portnum;
2990         else
2991                 pci_func = ahw->pci_func;
2992
2993         state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
2994         if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
2995                 dev_info(&adapter->pdev->dev, "link state down\n");
2996                 return config;
2997         }
2998
2999         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3000         if (err)
3001                 return err;
3002
3003         err = qlcnic_issue_cmd(adapter, &cmd);
3004         if (err) {
3005                 dev_info(&adapter->pdev->dev,
3006                          "Get Link Status Command failed: 0x%x\n", err);
3007                 goto out;
3008         } else {
3009                 config = cmd.rsp.arg[1];
3010                 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3011                 case QLC_83XX_10M_LINK:
3012                         ahw->link_speed = SPEED_10;
3013                         break;
3014                 case QLC_83XX_100M_LINK:
3015                         ahw->link_speed = SPEED_100;
3016                         break;
3017                 case QLC_83XX_1G_LINK:
3018                         ahw->link_speed = SPEED_1000;
3019                         break;
3020                 case QLC_83XX_10G_LINK:
3021                         ahw->link_speed = SPEED_10000;
3022                         break;
3023                 default:
3024                         ahw->link_speed = 0;
3025                         break;
3026                 }
3027                 config = cmd.rsp.arg[3];
3028                 if (QLC_83XX_SFP_PRESENT(config)) {
3029                         switch (ahw->module_type) {
3030                         case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
3031                         case LINKEVENT_MODULE_OPTICAL_SRLR:
3032                         case LINKEVENT_MODULE_OPTICAL_LRM:
3033                         case LINKEVENT_MODULE_OPTICAL_SFP_1G:
3034                                 ahw->supported_type = PORT_FIBRE;
3035                                 break;
3036                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
3037                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
3038                         case LINKEVENT_MODULE_TWINAX:
3039                                 ahw->supported_type = PORT_TP;
3040                                 break;
3041                         default:
3042                                 ahw->supported_type = PORT_OTHER;
3043                         }
3044                 }
3045                 if (config & 1)
3046                         err = 1;
3047         }
3048 out:
3049         qlcnic_free_mbx_args(&cmd);
3050         return config;
3051 }
3052
3053 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3054                              struct ethtool_cmd *ecmd)
3055 {
3056         u32 config = 0;
3057         int status = 0;
3058         struct qlcnic_hardware_context *ahw = adapter->ahw;
3059
3060         if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3061                 /* Get port configuration info */
3062                 status = qlcnic_83xx_get_port_info(adapter);
3063                 /* Get Link Status related info */
3064                 config = qlcnic_83xx_test_link(adapter);
3065                 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3066         }
3067
3068         /* hard code until there is a way to get it from flash */
3069         ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3070
3071         if (netif_running(adapter->netdev) && ahw->has_link_events) {
3072                 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3073                 ecmd->duplex = ahw->link_duplex;
3074                 ecmd->autoneg = ahw->link_autoneg;
3075         } else {
3076                 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3077                 ecmd->duplex = DUPLEX_UNKNOWN;
3078                 ecmd->autoneg = AUTONEG_DISABLE;
3079         }
3080
3081         if (ahw->port_type == QLCNIC_XGBE) {
3082                 ecmd->supported = SUPPORTED_10000baseT_Full;
3083                 ecmd->advertising = ADVERTISED_10000baseT_Full;
3084         } else {
3085                 ecmd->supported = (SUPPORTED_10baseT_Half |
3086                                    SUPPORTED_10baseT_Full |
3087                                    SUPPORTED_100baseT_Half |
3088                                    SUPPORTED_100baseT_Full |
3089                                    SUPPORTED_1000baseT_Half |
3090                                    SUPPORTED_1000baseT_Full);
3091                 ecmd->advertising = (ADVERTISED_100baseT_Half |
3092                                      ADVERTISED_100baseT_Full |
3093                                      ADVERTISED_1000baseT_Half |
3094                                      ADVERTISED_1000baseT_Full);
3095         }
3096
3097         switch (ahw->supported_type) {
3098         case PORT_FIBRE:
3099                 ecmd->supported |= SUPPORTED_FIBRE;
3100                 ecmd->advertising |= ADVERTISED_FIBRE;
3101                 ecmd->port = PORT_FIBRE;
3102                 ecmd->transceiver = XCVR_EXTERNAL;
3103                 break;
3104         case PORT_TP:
3105                 ecmd->supported |= SUPPORTED_TP;
3106                 ecmd->advertising |= ADVERTISED_TP;
3107                 ecmd->port = PORT_TP;
3108                 ecmd->transceiver = XCVR_INTERNAL;
3109                 break;
3110         default:
3111                 ecmd->supported |= SUPPORTED_FIBRE;
3112                 ecmd->advertising |= ADVERTISED_FIBRE;
3113                 ecmd->port = PORT_OTHER;
3114                 ecmd->transceiver = XCVR_EXTERNAL;
3115                 break;
3116         }
3117         ecmd->phy_address = ahw->physical_port;
3118         return status;
3119 }
3120
3121 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3122                              struct ethtool_cmd *ecmd)
3123 {
3124         int status = 0;
3125         u32 config = adapter->ahw->port_config;
3126
3127         if (ecmd->autoneg)
3128                 adapter->ahw->port_config |= BIT_15;
3129
3130         switch (ethtool_cmd_speed(ecmd)) {
3131         case SPEED_10:
3132                 adapter->ahw->port_config |= BIT_8;
3133                 break;
3134         case SPEED_100:
3135                 adapter->ahw->port_config |= BIT_9;
3136                 break;
3137         case SPEED_1000:
3138                 adapter->ahw->port_config |= BIT_10;
3139                 break;
3140         case SPEED_10000:
3141                 adapter->ahw->port_config |= BIT_11;
3142                 break;
3143         default:
3144                 return -EINVAL;
3145         }
3146
3147         status = qlcnic_83xx_set_port_config(adapter);
3148         if (status) {
3149                 dev_info(&adapter->pdev->dev,
3150                          "Failed to Set Link Speed and autoneg.\n");
3151                 adapter->ahw->port_config = config;
3152         }
3153         return status;
3154 }
3155
3156 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3157                                           u64 *data, int index)
3158 {
3159         u32 low, hi;
3160         u64 val;
3161
3162         low = cmd->rsp.arg[index];
3163         hi = cmd->rsp.arg[index + 1];
3164         val = (((u64) low) | (((u64) hi) << 32));
3165         *data++ = val;
3166         return data;
3167 }
3168
3169 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3170                                    struct qlcnic_cmd_args *cmd, u64 *data,
3171                                    int type, int *ret)
3172 {
3173         int err, k, total_regs;
3174
3175         *ret = 0;
3176         err = qlcnic_issue_cmd(adapter, cmd);
3177         if (err != QLCNIC_RCODE_SUCCESS) {
3178                 dev_info(&adapter->pdev->dev,
3179                          "Error in get statistics mailbox command\n");
3180                 *ret = -EIO;
3181                 return data;
3182         }
3183         total_regs = cmd->rsp.num;
3184         switch (type) {
3185         case QLC_83XX_STAT_MAC:
3186                 /* fill in MAC tx counters */
3187                 for (k = 2; k < 28; k += 2)
3188                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3189                 /* skip 24 bytes of reserved area */
3190                 /* fill in MAC rx counters */
3191                 for (k += 6; k < 60; k += 2)
3192                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3193                 /* skip 24 bytes of reserved area */
3194                 /* fill in MAC rx frame stats */
3195                 for (k += 6; k < 80; k += 2)
3196                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3197                 /* fill in eSwitch stats */
3198                 for (; k < total_regs; k += 2)
3199                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3200                 break;
3201         case QLC_83XX_STAT_RX:
3202                 for (k = 2; k < 8; k += 2)
3203                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3204                 /* skip 8 bytes of reserved data */
3205                 for (k += 2; k < 24; k += 2)
3206                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3207                 /* skip 8 bytes containing RE1FBQ error data */
3208                 for (k += 2; k < total_regs; k += 2)
3209                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3210                 break;
3211         case QLC_83XX_STAT_TX:
3212                 for (k = 2; k < 10; k += 2)
3213                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3214                 /* skip 8 bytes of reserved data */
3215                 for (k += 2; k < total_regs; k += 2)
3216                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3217                 break;
3218         default:
3219                 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3220                 *ret = -EIO;
3221         }
3222         return data;
3223 }
3224
3225 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3226 {
3227         struct qlcnic_cmd_args cmd;
3228         struct net_device *netdev = adapter->netdev;
3229         int ret = 0;
3230
3231         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3232         if (ret)
3233                 return;
3234         /* Get Tx stats */
3235         cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3236         cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3237         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3238                                       QLC_83XX_STAT_TX, &ret);
3239         if (ret) {
3240                 netdev_err(netdev, "Error getting Tx stats\n");
3241                 goto out;
3242         }
3243         /* Get MAC stats */
3244         cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3245         cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3246         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3247         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3248                                       QLC_83XX_STAT_MAC, &ret);
3249         if (ret) {
3250                 netdev_err(netdev, "Error getting MAC stats\n");
3251                 goto out;
3252         }
3253         /* Get Rx stats */
3254         cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3255         cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3256         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3257         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3258                                       QLC_83XX_STAT_RX, &ret);
3259         if (ret)
3260                 netdev_err(netdev, "Error getting Rx stats\n");
3261 out:
3262         qlcnic_free_mbx_args(&cmd);
3263 }
3264
3265 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3266 {
3267         u32 major, minor, sub;
3268
3269         major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3270         minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3271         sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3272
3273         if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3274                 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3275                          __func__);
3276                 return 1;
3277         }
3278         return 0;
3279 }
3280
3281 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3282 {
3283         return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3284                 sizeof(*adapter->ahw->ext_reg_tbl)) +
3285                 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3286                 sizeof(*adapter->ahw->reg_tbl));
3287 }
3288
3289 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3290 {
3291         int i, j = 0;
3292
3293         for (i = QLCNIC_DEV_INFO_SIZE + 1;
3294              j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3295                 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3296
3297         for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3298                 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3299         return i;
3300 }
3301
3302 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3303 {
3304         struct qlcnic_adapter *adapter = netdev_priv(netdev);
3305         struct qlcnic_hardware_context *ahw = adapter->ahw;
3306         struct qlcnic_cmd_args cmd;
3307         u8 val, drv_sds_rings = adapter->drv_sds_rings;
3308         u8 drv_tx_rings = adapter->drv_tx_rings;
3309         u32 data;
3310         u16 intrpt_id, id;
3311         int ret;
3312
3313         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3314                 netdev_info(netdev, "Device is resetting\n");
3315                 return -EBUSY;
3316         }
3317
3318         if (qlcnic_get_diag_lock(adapter)) {
3319                 netdev_info(netdev, "Device in diagnostics mode\n");
3320                 return -EBUSY;
3321         }
3322
3323         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3324                                          drv_sds_rings);
3325         if (ret)
3326                 goto fail_diag_irq;
3327
3328         ahw->diag_cnt = 0;
3329         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3330         if (ret)
3331                 goto fail_diag_irq;
3332
3333         if (adapter->flags & QLCNIC_MSIX_ENABLED)
3334                 intrpt_id = ahw->intr_tbl[0].id;
3335         else
3336                 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3337
3338         cmd.req.arg[1] = 1;
3339         cmd.req.arg[2] = intrpt_id;
3340         cmd.req.arg[3] = BIT_0;
3341
3342         ret = qlcnic_issue_cmd(adapter, &cmd);
3343         data = cmd.rsp.arg[2];
3344         id = LSW(data);
3345         val = LSB(MSW(data));
3346         if (id != intrpt_id)
3347                 dev_info(&adapter->pdev->dev,
3348                          "Interrupt generated: 0x%x, requested:0x%x\n",
3349                          id, intrpt_id);
3350         if (val)
3351                 dev_err(&adapter->pdev->dev,
3352                          "Interrupt test error: 0x%x\n", val);
3353         if (ret)
3354                 goto done;
3355
3356         msleep(20);
3357         ret = !ahw->diag_cnt;
3358
3359 done:
3360         qlcnic_free_mbx_args(&cmd);
3361         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3362
3363 fail_diag_irq:
3364         adapter->drv_sds_rings = drv_sds_rings;
3365         adapter->drv_tx_rings = drv_tx_rings;
3366         qlcnic_release_diag_lock(adapter);
3367         return ret;
3368 }
3369
3370 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3371                                 struct ethtool_pauseparam *pause)
3372 {
3373         struct qlcnic_hardware_context *ahw = adapter->ahw;
3374         int status = 0;
3375         u32 config;
3376
3377         status = qlcnic_83xx_get_port_config(adapter);
3378         if (status) {
3379                 dev_err(&adapter->pdev->dev,
3380                         "%s: Get Pause Config failed\n", __func__);
3381                 return;
3382         }
3383         config = ahw->port_config;
3384         if (config & QLC_83XX_CFG_STD_PAUSE) {
3385                 switch (MSW(config)) {
3386                 case QLC_83XX_TX_PAUSE:
3387                         pause->tx_pause = 1;
3388                         break;
3389                 case QLC_83XX_RX_PAUSE:
3390                         pause->rx_pause = 1;
3391                         break;
3392                 case QLC_83XX_TX_RX_PAUSE:
3393                 default:
3394                         /* Backward compatibility for existing
3395                          * flash definitions
3396                          */
3397                         pause->tx_pause = 1;
3398                         pause->rx_pause = 1;
3399                 }
3400         }
3401
3402         if (QLC_83XX_AUTONEG(config))
3403                 pause->autoneg = 1;
3404 }
3405
3406 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3407                                struct ethtool_pauseparam *pause)
3408 {
3409         struct qlcnic_hardware_context *ahw = adapter->ahw;
3410         int status = 0;
3411         u32 config;
3412
3413         status = qlcnic_83xx_get_port_config(adapter);
3414         if (status) {
3415                 dev_err(&adapter->pdev->dev,
3416                         "%s: Get Pause Config failed.\n", __func__);
3417                 return status;
3418         }
3419         config = ahw->port_config;
3420
3421         if (ahw->port_type == QLCNIC_GBE) {
3422                 if (pause->autoneg)
3423                         ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3424                 if (!pause->autoneg)
3425                         ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3426         } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3427                 return -EOPNOTSUPP;
3428         }
3429
3430         if (!(config & QLC_83XX_CFG_STD_PAUSE))
3431                 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3432
3433         if (pause->rx_pause && pause->tx_pause) {
3434                 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3435         } else if (pause->rx_pause && !pause->tx_pause) {
3436                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3437                 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3438         } else if (pause->tx_pause && !pause->rx_pause) {
3439                 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3440                 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3441         } else if (!pause->rx_pause && !pause->tx_pause) {
3442                 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3443                                       QLC_83XX_CFG_STD_PAUSE);
3444         }
3445         status = qlcnic_83xx_set_port_config(adapter);
3446         if (status) {
3447                 dev_err(&adapter->pdev->dev,
3448                         "%s: Set Pause Config failed.\n", __func__);
3449                 ahw->port_config = config;
3450         }
3451         return status;
3452 }
3453
3454 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3455 {
3456         int ret, err = 0;
3457         u32 temp;
3458
3459         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3460                                      QLC_83XX_FLASH_OEM_READ_SIG);
3461         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3462                                      QLC_83XX_FLASH_READ_CTRL);
3463         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3464         if (ret)
3465                 return -EIO;
3466
3467         temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3468         if (err == -EIO)
3469                 return err;
3470
3471         return temp & 0xFF;
3472 }
3473
3474 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3475 {
3476         int status;
3477
3478         status = qlcnic_83xx_read_flash_status_reg(adapter);
3479         if (status == -EIO) {
3480                 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3481                          __func__);
3482                 return 1;
3483         }
3484         return 0;
3485 }
3486
3487 int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3488 {
3489         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3490         struct net_device *netdev = adapter->netdev;
3491         int retval;
3492
3493         netif_device_detach(netdev);
3494         qlcnic_cancel_idc_work(adapter);
3495
3496         if (netif_running(netdev))
3497                 qlcnic_down(adapter, netdev);
3498
3499         qlcnic_83xx_disable_mbx_intr(adapter);
3500         cancel_delayed_work_sync(&adapter->idc_aen_work);
3501
3502         retval = pci_save_state(pdev);
3503         if (retval)
3504                 return retval;
3505
3506         return 0;
3507 }
3508
3509 int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3510 {
3511         struct qlcnic_hardware_context *ahw = adapter->ahw;
3512         struct qlc_83xx_idc *idc = &ahw->idc;
3513         int err = 0;
3514
3515         err = qlcnic_83xx_idc_init(adapter);
3516         if (err)
3517                 return err;
3518
3519         if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3520                 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3521                         qlcnic_83xx_set_vnic_opmode(adapter);
3522                 } else {
3523                         err = qlcnic_83xx_check_vnic_state(adapter);
3524                         if (err)
3525                                 return err;
3526                 }
3527         }
3528
3529         err = qlcnic_83xx_idc_reattach_driver(adapter);
3530         if (err)
3531                 return err;
3532
3533         qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3534                              idc->delay);
3535         return err;
3536 }
3537
3538 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3539 {
3540         reinit_completion(&mbx->completion);
3541         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3542 }
3543
3544 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3545 {
3546         if (!mbx)
3547                 return;
3548
3549         destroy_workqueue(mbx->work_q);
3550         kfree(mbx);
3551 }
3552
3553 static inline void
3554 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3555                                   struct qlcnic_cmd_args *cmd)
3556 {
3557         atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3558
3559         if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3560                 qlcnic_free_mbx_args(cmd);
3561                 kfree(cmd);
3562                 return;
3563         }
3564         complete(&cmd->completion);
3565 }
3566
3567 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3568 {
3569         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3570         struct list_head *head = &mbx->cmd_q;
3571         struct qlcnic_cmd_args *cmd = NULL;
3572
3573         spin_lock(&mbx->queue_lock);
3574
3575         while (!list_empty(head)) {
3576                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3577                 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3578                          __func__, cmd->cmd_op);
3579                 list_del(&cmd->list);
3580                 mbx->num_cmds--;
3581                 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3582         }
3583
3584         spin_unlock(&mbx->queue_lock);
3585 }
3586
3587 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3588 {
3589         struct qlcnic_hardware_context *ahw = adapter->ahw;
3590         struct qlcnic_mailbox *mbx = ahw->mailbox;
3591         u32 host_mbx_ctrl;
3592
3593         if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3594                 return -EBUSY;
3595
3596         host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3597         if (host_mbx_ctrl) {
3598                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3599                 ahw->idc.collect_dump = 1;
3600                 return -EIO;
3601         }
3602
3603         return 0;
3604 }
3605
3606 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3607                                               u8 issue_cmd)
3608 {
3609         if (issue_cmd)
3610                 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3611         else
3612                 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3613 }
3614
3615 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3616                                         struct qlcnic_cmd_args *cmd)
3617 {
3618         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3619
3620         spin_lock(&mbx->queue_lock);
3621
3622         list_del(&cmd->list);
3623         mbx->num_cmds--;
3624
3625         spin_unlock(&mbx->queue_lock);
3626
3627         qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3628 }
3629
3630 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3631                                        struct qlcnic_cmd_args *cmd)
3632 {
3633         u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3634         struct qlcnic_hardware_context *ahw = adapter->ahw;
3635         int i, j;
3636
3637         if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3638                 mbx_cmd = cmd->req.arg[0];
3639                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3640                 for (i = 1; i < cmd->req.num; i++)
3641                         writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3642         } else {
3643                 fw_hal_version = ahw->fw_hal_version;
3644                 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3645                 total_size = cmd->pay_size + hdr_size;
3646                 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3647                 mbx_cmd = tmp | fw_hal_version << 29;
3648                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3649
3650                 /* Back channel specific operations bits */
3651                 mbx_cmd = 0x1 | 1 << 4;
3652
3653                 if (qlcnic_sriov_pf_check(adapter))
3654                         mbx_cmd |= cmd->func_num << 5;
3655
3656                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3657
3658                 for (i = 2, j = 0; j < hdr_size; i++, j++)
3659                         writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3660                 for (j = 0; j < cmd->pay_size; j++, i++)
3661                         writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3662         }
3663 }
3664
3665 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3666 {
3667         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3668
3669         if (!mbx)
3670                 return;
3671
3672         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3673         complete(&mbx->completion);
3674         cancel_work_sync(&mbx->work);
3675         flush_workqueue(mbx->work_q);
3676         qlcnic_83xx_flush_mbx_queue(adapter);
3677 }
3678
3679 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3680                                        struct qlcnic_cmd_args *cmd,
3681                                        unsigned long *timeout)
3682 {
3683         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3684
3685         if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3686                 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3687                 init_completion(&cmd->completion);
3688                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3689
3690                 spin_lock(&mbx->queue_lock);
3691
3692                 list_add_tail(&cmd->list, &mbx->cmd_q);
3693                 mbx->num_cmds++;
3694                 cmd->total_cmds = mbx->num_cmds;
3695                 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3696                 queue_work(mbx->work_q, &mbx->work);
3697
3698                 spin_unlock(&mbx->queue_lock);
3699
3700                 return 0;
3701         }
3702
3703         return -EBUSY;
3704 }
3705
3706 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3707                                        struct qlcnic_cmd_args *cmd)
3708 {
3709         u8 mac_cmd_rcode;
3710         u32 fw_data;
3711
3712         if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3713                 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3714                 mac_cmd_rcode = (u8)fw_data;
3715                 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3716                     mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3717                     mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3718                         cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3719                         return QLCNIC_RCODE_SUCCESS;
3720                 }
3721         }
3722
3723         return -EINVAL;
3724 }
3725
3726 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3727                                        struct qlcnic_cmd_args *cmd)
3728 {
3729         struct qlcnic_hardware_context *ahw = adapter->ahw;
3730         struct device *dev = &adapter->pdev->dev;
3731         u8 mbx_err_code;
3732         u32 fw_data;
3733
3734         fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3735         mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3736         qlcnic_83xx_get_mbx_data(adapter, cmd);
3737
3738         switch (mbx_err_code) {
3739         case QLCNIC_MBX_RSP_OK:
3740         case QLCNIC_MBX_PORT_RSP_OK:
3741                 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3742                 break;
3743         default:
3744                 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3745                         break;
3746
3747                 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3748                         __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3749                         ahw->op_mode, mbx_err_code);
3750                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3751                 qlcnic_dump_mbx(adapter, cmd);
3752         }
3753
3754         return;
3755 }
3756
3757 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3758 {
3759         struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3760                                                   work);
3761         struct qlcnic_adapter *adapter = mbx->adapter;
3762         struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3763         struct device *dev = &adapter->pdev->dev;
3764         atomic_t *rsp_status = &mbx->rsp_status;
3765         struct list_head *head = &mbx->cmd_q;
3766         struct qlcnic_hardware_context *ahw;
3767         struct qlcnic_cmd_args *cmd = NULL;
3768
3769         ahw = adapter->ahw;
3770
3771         while (true) {
3772                 if (qlcnic_83xx_check_mbx_status(adapter)) {
3773                         qlcnic_83xx_flush_mbx_queue(adapter);
3774                         return;
3775                 }
3776
3777                 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3778
3779                 spin_lock(&mbx->queue_lock);
3780
3781                 if (list_empty(head)) {
3782                         spin_unlock(&mbx->queue_lock);
3783                         return;
3784                 }
3785                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3786
3787                 spin_unlock(&mbx->queue_lock);
3788
3789                 mbx_ops->encode_cmd(adapter, cmd);
3790                 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3791
3792                 if (wait_for_completion_timeout(&mbx->completion,
3793                                                 QLC_83XX_MBX_TIMEOUT)) {
3794                         mbx_ops->decode_resp(adapter, cmd);
3795                         mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3796                 } else {
3797                         dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3798                                 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3799                                 ahw->op_mode);
3800                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3801                         qlcnic_dump_mbx(adapter, cmd);
3802                         qlcnic_83xx_idc_request_reset(adapter,
3803                                                       QLCNIC_FORCE_FW_DUMP_KEY);
3804                         cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3805                 }
3806                 mbx_ops->dequeue_cmd(adapter, cmd);
3807         }
3808 }
3809
3810 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3811         .enqueue_cmd    = qlcnic_83xx_enqueue_mbx_cmd,
3812         .dequeue_cmd    = qlcnic_83xx_dequeue_mbx_cmd,
3813         .decode_resp    = qlcnic_83xx_decode_mbx_rsp,
3814         .encode_cmd     = qlcnic_83xx_encode_mbx_cmd,
3815         .nofity_fw      = qlcnic_83xx_signal_mbx_cmd,
3816 };
3817
3818 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3819 {
3820         struct qlcnic_hardware_context *ahw = adapter->ahw;
3821         struct qlcnic_mailbox *mbx;
3822
3823         ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3824         if (!ahw->mailbox)
3825                 return -ENOMEM;
3826
3827         mbx = ahw->mailbox;
3828         mbx->ops = &qlcnic_83xx_mbx_ops;
3829         mbx->adapter = adapter;
3830
3831         spin_lock_init(&mbx->queue_lock);
3832         spin_lock_init(&mbx->aen_lock);
3833         INIT_LIST_HEAD(&mbx->cmd_q);
3834         init_completion(&mbx->completion);
3835
3836         mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3837         if (mbx->work_q == NULL) {
3838                 kfree(mbx);
3839                 return -ENOMEM;
3840         }
3841
3842         INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
3843         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3844         return 0;
3845 }
3846
3847 pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
3848                                                pci_channel_state_t state)
3849 {
3850         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3851
3852         if (state == pci_channel_io_perm_failure)
3853                 return PCI_ERS_RESULT_DISCONNECT;
3854
3855         if (state == pci_channel_io_normal)
3856                 return PCI_ERS_RESULT_RECOVERED;
3857
3858         set_bit(__QLCNIC_AER, &adapter->state);
3859         set_bit(__QLCNIC_RESETTING, &adapter->state);
3860
3861         qlcnic_83xx_aer_stop_poll_work(adapter);
3862
3863         pci_save_state(pdev);
3864         pci_disable_device(pdev);
3865
3866         return PCI_ERS_RESULT_NEED_RESET;
3867 }
3868
3869 pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
3870 {
3871         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3872         int err = 0;
3873
3874         pdev->error_state = pci_channel_io_normal;
3875         err = pci_enable_device(pdev);
3876         if (err)
3877                 goto disconnect;
3878
3879         pci_set_power_state(pdev, PCI_D0);
3880         pci_set_master(pdev);
3881         pci_restore_state(pdev);
3882
3883         err = qlcnic_83xx_aer_reset(adapter);
3884         if (err == 0)
3885                 return PCI_ERS_RESULT_RECOVERED;
3886 disconnect:
3887         clear_bit(__QLCNIC_AER, &adapter->state);
3888         clear_bit(__QLCNIC_RESETTING, &adapter->state);
3889         return PCI_ERS_RESULT_DISCONNECT;
3890 }
3891
3892 void qlcnic_83xx_io_resume(struct pci_dev *pdev)
3893 {
3894         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3895
3896         pci_cleanup_aer_uncorrect_error_status(pdev);
3897         if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
3898                 qlcnic_83xx_aer_start_poll_work(adapter);
3899 }