Pileus Git - ~andy/linux/blob - drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_sriov.h"
  10 #include <linux/if_vlan.h>
  11 #include <linux/ipv6.h>
  12 #include <linux/ethtool.h>
  13 #include <linux/interrupt.h>
  14
  15 #define QLCNIC_MAX_TX_QUEUES            1
  16 #define RSS_HASHTYPE_IP_TCP             0x3
  17 #define QLC_83XX_FW_MBX_CMD             0
  18
  19 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
  20         {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
  21         {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
  22         {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
  23         {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  24         {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
  25         {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  26         {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
  27         {QLCNIC_CMD_INTRPT_TEST, 22, 12},
  28         {QLCNIC_CMD_SET_MTU, 3, 1},
  29         {QLCNIC_CMD_READ_PHY, 4, 2},
  30         {QLCNIC_CMD_WRITE_PHY, 5, 1},
  31         {QLCNIC_CMD_READ_HW_REG, 4, 1},
  32         {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  33         {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  34         {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  35         {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  36         {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  37         {QLCNIC_CMD_GET_PCI_INFO, 1, 66},
  38         {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
  39         {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
  40         {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  41         {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  42         {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  43         {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  44         {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  45         {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  46         {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  47         {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  48         {QLCNIC_CMD_TEMP_SIZE, 1, 4},
  49         {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
  50         {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
  51         {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
  52         {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
  53         {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
  54         {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
  55         {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
  56         {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
  57         {QLCNIC_CMD_GET_STATISTICS, 2, 80},
  58         {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
  59         {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
  60         {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
  61         {QLCNIC_CMD_IDC_ACK, 5, 1},
  62         {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
  63         {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
  64         {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
  65         {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
  66         {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
  67         {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
  68         {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
  69 };
  70
  71 const u32 qlcnic_83xx_ext_reg_tbl[] = {
  72         0x38CC,         /* Global Reset */
  73         0x38F0,         /* Wildcard */
  74         0x38FC,         /* Informant */
  75         0x3038,         /* Host MBX ctrl */
  76         0x303C,         /* FW MBX ctrl */
  77         0x355C,         /* BOOT LOADER ADDRESS REG */
  78         0x3560,         /* BOOT LOADER SIZE REG */
  79         0x3564,         /* FW IMAGE ADDR REG */
  80         0x1000,         /* MBX intr enable */
  81         0x1200,         /* Default Intr mask */
  82         0x1204,         /* Default Interrupt ID */
  83         0x3780,         /* QLC_83XX_IDC_MAJ_VERSION */
  84         0x3784,         /* QLC_83XX_IDC_DEV_STATE */
  85         0x3788,         /* QLC_83XX_IDC_DRV_PRESENCE */
  86         0x378C,         /* QLC_83XX_IDC_DRV_ACK */
  87         0x3790,         /* QLC_83XX_IDC_CTRL */
  88         0x3794,         /* QLC_83XX_IDC_DRV_AUDIT */
  89         0x3798,         /* QLC_83XX_IDC_MIN_VERSION */
  90         0x379C,         /* QLC_83XX_RECOVER_DRV_LOCK */
  91         0x37A0,         /* QLC_83XX_IDC_PF_0 */
  92         0x37A4,         /* QLC_83XX_IDC_PF_1 */
  93         0x37A8,         /* QLC_83XX_IDC_PF_2 */
  94         0x37AC,         /* QLC_83XX_IDC_PF_3 */
  95         0x37B0,         /* QLC_83XX_IDC_PF_4 */
  96         0x37B4,         /* QLC_83XX_IDC_PF_5 */
  97         0x37B8,         /* QLC_83XX_IDC_PF_6 */
  98         0x37BC,         /* QLC_83XX_IDC_PF_7 */
  99         0x37C0,         /* QLC_83XX_IDC_PF_8 */
 100         0x37C4,         /* QLC_83XX_IDC_PF_9 */
 101         0x37C8,         /* QLC_83XX_IDC_PF_10 */
 102         0x37CC,         /* QLC_83XX_IDC_PF_11 */
 103         0x37D0,         /* QLC_83XX_IDC_PF_12 */
 104         0x37D4,         /* QLC_83XX_IDC_PF_13 */
 105         0x37D8,         /* QLC_83XX_IDC_PF_14 */
 106         0x37DC,         /* QLC_83XX_IDC_PF_15 */
 107         0x37E0,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
 108         0x37E4,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
 109         0x37F0,         /* QLC_83XX_DRV_OP_MODE */
 110         0x37F4,         /* QLC_83XX_VNIC_STATE */
 111         0x3868,         /* QLC_83XX_DRV_LOCK */
 112         0x386C,         /* QLC_83XX_DRV_UNLOCK */
 113         0x3504,         /* QLC_83XX_DRV_LOCK_ID */
 114         0x34A4,         /* QLC_83XX_ASIC_TEMP */
 115 };
 116
 117 const u32 qlcnic_83xx_reg_tbl[] = {
 118         0x34A8,         /* PEG_HALT_STAT1 */
 119         0x34AC,         /* PEG_HALT_STAT2 */
 120         0x34B0,         /* FW_HEARTBEAT */
 121         0x3500,         /* FLASH LOCK_ID */
 122         0x3528,         /* FW_CAPABILITIES */
 123         0x3538,         /* Driver active, DRV_REG0 */
 124         0x3540,         /* Device state, DRV_REG1 */
 125         0x3544,         /* Driver state, DRV_REG2 */
 126         0x3548,         /* Driver scratch, DRV_REG3 */
 127         0x354C,         /* Device partiton info, DRV_REG4 */
 128         0x3524,         /* Driver IDC ver, DRV_REG5 */
 129         0x3550,         /* FW_VER_MAJOR */
 130         0x3554,         /* FW_VER_MINOR */
 131         0x3558,         /* FW_VER_SUB */
 132         0x359C,         /* NPAR STATE */
 133         0x35FC,         /* FW_IMG_VALID */
 134         0x3650,         /* CMD_PEG_STATE */
 135         0x373C,         /* RCV_PEG_STATE */
 136         0x37B4,         /* ASIC TEMP */
 137         0x356C,         /* FW API */
 138         0x3570,         /* DRV OP MODE */
 139         0x3850,         /* FLASH LOCK */
 140         0x3854,         /* FLASH UNLOCK */
 141 };
 142
 143 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
 144         .read_crb                       = qlcnic_83xx_read_crb,
 145         .write_crb                      = qlcnic_83xx_write_crb,
 146         .read_reg                       = qlcnic_83xx_rd_reg_indirect,
 147         .write_reg                      = qlcnic_83xx_wrt_reg_indirect,
 148         .get_mac_address                = qlcnic_83xx_get_mac_address,
 149         .setup_intr                     = qlcnic_83xx_setup_intr,
 150         .alloc_mbx_args                 = qlcnic_83xx_alloc_mbx_args,
 151         .mbx_cmd                        = qlcnic_83xx_mbx_op,
 152         .get_func_no                    = qlcnic_83xx_get_func_no,
 153         .api_lock                       = qlcnic_83xx_cam_lock,
 154         .api_unlock                     = qlcnic_83xx_cam_unlock,
 155         .add_sysfs                      = qlcnic_83xx_add_sysfs,
 156         .remove_sysfs                   = qlcnic_83xx_remove_sysfs,
 157         .process_lb_rcv_ring_diag       = qlcnic_83xx_process_rcv_ring_diag,
 158         .create_rx_ctx                  = qlcnic_83xx_create_rx_ctx,
 159         .create_tx_ctx                  = qlcnic_83xx_create_tx_ctx,
 160         .del_rx_ctx                     = qlcnic_83xx_del_rx_ctx,
 161         .del_tx_ctx                     = qlcnic_83xx_del_tx_ctx,
 162         .setup_link_event               = qlcnic_83xx_setup_link_event,
 163         .get_nic_info                   = qlcnic_83xx_get_nic_info,
 164         .get_pci_info                   = qlcnic_83xx_get_pci_info,
 165         .set_nic_info                   = qlcnic_83xx_set_nic_info,
 166         .change_macvlan                 = qlcnic_83xx_sre_macaddr_change,
 167         .napi_enable                    = qlcnic_83xx_napi_enable,
 168         .napi_disable                   = qlcnic_83xx_napi_disable,
 169         .config_intr_coal               = qlcnic_83xx_config_intr_coal,
 170         .config_rss                     = qlcnic_83xx_config_rss,
 171         .config_hw_lro                  = qlcnic_83xx_config_hw_lro,
 172         .config_promisc_mode            = qlcnic_83xx_nic_set_promisc,
 173         .change_l2_filter               = qlcnic_83xx_change_l2_filter,
 174         .get_board_info                 = qlcnic_83xx_get_port_info,
 175         .free_mac_list                  = qlcnic_82xx_free_mac_list,
 176 };
 177
 178 static struct qlcnic_nic_template qlcnic_83xx_ops = {
 179         .config_bridged_mode    = qlcnic_config_bridged_mode,
 180         .config_led             = qlcnic_config_led,
 181         .request_reset          = qlcnic_83xx_idc_request_reset,
 182         .cancel_idc_work        = qlcnic_83xx_idc_exit,
 183         .napi_add               = qlcnic_83xx_napi_add,
 184         .napi_del               = qlcnic_83xx_napi_del,
 185         .config_ipaddr          = qlcnic_83xx_config_ipaddr,
 186         .clear_legacy_intr      = qlcnic_83xx_clear_legacy_intr,
 187 };
 188
 189 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
 190 {
 191         ahw->hw_ops             = &qlcnic_83xx_hw_ops;
 192         ahw->reg_tbl            = (u32 *)qlcnic_83xx_reg_tbl;
 193         ahw->ext_reg_tbl        = (u32 *)qlcnic_83xx_ext_reg_tbl;
 194 }
 195
 196 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
 197 {
 198         u32 fw_major, fw_minor, fw_build;
 199         struct pci_dev *pdev = adapter->pdev;
 200
 201         fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
 202         fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
 203         fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
 204         adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
 205
 206         dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
 207                  QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
 208
 209         return adapter->fw_version;
 210 }
 211
 212 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
 213 {
 214         void __iomem *base;
 215         u32 val;
 216
 217         base = adapter->ahw->pci_base0 +
 218                QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
 219         writel(addr, base);
 220         val = readl(base);
 221         if (val != addr)
 222                 return -EIO;
 223
 224         return 0;
 225 }
 226
 227 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr)
 228 {
 229         int ret;
 230         struct qlcnic_hardware_context *ahw = adapter->ahw;
 231
 232         ret = __qlcnic_set_win_base(adapter, (u32) addr);
 233         if (!ret) {
 234                 return QLCRDX(ahw, QLCNIC_WILDCARD);
 235         } else {
 236                 dev_err(&adapter->pdev->dev,
 237                         "%s failed, addr = 0x%x\n", __func__, (int)addr);
 238                 return -EIO;
 239         }
 240 }
 241
 242 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 243                                  u32 data)
 244 {
 245         int err;
 246         struct qlcnic_hardware_context *ahw = adapter->ahw;
 247
 248         err = __qlcnic_set_win_base(adapter, (u32) addr);
 249         if (!err) {
 250                 QLCWRX(ahw, QLCNIC_WILDCARD, data);
 251                 return 0;
 252         } else {
 253                 dev_err(&adapter->pdev->dev,
 254                         "%s failed, addr = 0x%x data = 0x%x\n",
 255                         __func__, (int)addr, data);
 256                 return err;
 257         }
 258 }
 259
 260 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr)
 261 {
 262         int err, i, num_msix;
 263         struct qlcnic_hardware_context *ahw = adapter->ahw;
 264
 265         if (!num_intr)
 266                 num_intr = QLCNIC_DEF_NUM_STS_DESC_RINGS;
 267         num_msix = rounddown_pow_of_two(min_t(int, num_online_cpus(),
 268                                               num_intr));
 269         /* account for AEN interrupt MSI-X based interrupts */
 270         num_msix += 1;
 271
 272         if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
 273                 num_msix += adapter->max_drv_tx_rings;
 274
 275         err = qlcnic_enable_msix(adapter, num_msix);
 276         if (err == -ENOMEM)
 277                 return err;
 278         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 279                 num_msix = adapter->ahw->num_msix;
 280         else {
 281                 if (qlcnic_sriov_vf_check(adapter))
 282                         return -EINVAL;
 283                 num_msix = 1;
 284         }
 285         /* setup interrupt mapping table for fw */
 286         ahw->intr_tbl = vzalloc(num_msix *
 287                                 sizeof(struct qlcnic_intrpt_config));
 288         if (!ahw->intr_tbl)
 289                 return -ENOMEM;
 290         if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
 291                 /* MSI-X enablement failed, use legacy interrupt */
 292                 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
 293                 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
 294                 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
 295                 adapter->msix_entries[0].vector = adapter->pdev->irq;
 296                 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
 297         }
 298
 299         for (i = 0; i < num_msix; i++) {
 300                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
 301                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
 302                 else
 303                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
 304                 ahw->intr_tbl[i].id = i;
 305                 ahw->intr_tbl[i].src = 0;
 306         }
 307         return 0;
 308 }
 309
 310 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
 311 {
 312         writel(0, adapter->tgt_mask_reg);
 313 }
 314
 315 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
 316 {
 317         writel(1, adapter->tgt_mask_reg);
 318 }
 319
 320 /* Enable MSI-x and INT-x interrupts */
 321 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
 322                              struct qlcnic_host_sds_ring *sds_ring)
 323 {
 324         writel(0, sds_ring->crb_intr_mask);
 325 }
 326
 327 /* Disable MSI-x and INT-x interrupts */
 328 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
 329                               struct qlcnic_host_sds_ring *sds_ring)
 330 {
 331         writel(1, sds_ring->crb_intr_mask);
 332 }
 333
 334 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
 335                                                     *adapter)
 336 {
 337         u32 mask;
 338
 339         /* Mailbox in MSI-x mode and Legacy Interrupt share the same
 340          * source register. We could be here before contexts are created
 341          * and sds_ring->crb_intr_mask has not been initialized, calculate
 342          * BAR offset for Interrupt Source Register
 343          */
 344         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 345         writel(0, adapter->ahw->pci_base0 + mask);
 346 }
 347
 348 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
 349 {
 350         u32 mask;
 351
 352         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 353         writel(1, adapter->ahw->pci_base0 + mask);
 354         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
 355 }
 356
 357 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
 358                                      struct qlcnic_cmd_args *cmd)
 359 {
 360         int i;
 361         for (i = 0; i < cmd->rsp.num; i++)
 362                 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
 363 }
 364
 365 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
 366 {
 367         u32 intr_val;
 368         struct qlcnic_hardware_context *ahw = adapter->ahw;
 369         int retries = 0;
 370
 371         intr_val = readl(adapter->tgt_status_reg);
 372
 373         if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
 374                 return IRQ_NONE;
 375
 376         if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
 377                 adapter->stats.spurious_intr++;
 378                 return IRQ_NONE;
 379         }
 380         /* The barrier is required to ensure writes to the registers */
 381         wmb();
 382
 383         /* clear the interrupt trigger control register */
 384         writel(0, adapter->isr_int_vec);
 385         intr_val = readl(adapter->isr_int_vec);
 386         do {
 387                 intr_val = readl(adapter->tgt_status_reg);
 388                 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
 389                         break;
 390                 retries++;
 391         } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
 392                  (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
 393
 394         return IRQ_HANDLED;
 395 }
 396
 397 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
 398 {
 399         u32 resp, event;
 400         unsigned long flags;
 401
 402         spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
 403
 404         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
 405         if (!(resp & QLCNIC_SET_OWNER))
 406                 goto out;
 407
 408         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
 409         if (event &  QLCNIC_MBX_ASYNC_EVENT)
 410                 __qlcnic_83xx_process_aen(adapter);
 411
 412 out:
 413         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 414         spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
 415 }
 416
 417 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
 418 {
 419         struct qlcnic_adapter *adapter = data;
 420         struct qlcnic_host_sds_ring *sds_ring;
 421         struct qlcnic_hardware_context *ahw = adapter->ahw;
 422
 423         if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
 424                 return IRQ_NONE;
 425
 426         qlcnic_83xx_poll_process_aen(adapter);
 427
 428         if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
 429                 ahw->diag_cnt++;
 430                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 431                 return IRQ_HANDLED;
 432         }
 433
 434         if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
 435                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 436         } else {
 437                 sds_ring = &adapter->recv_ctx->sds_rings[0];
 438                 napi_schedule(&sds_ring->napi);
 439         }
 440
 441         return IRQ_HANDLED;
 442 }
 443
 444 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
 445 {
 446         struct qlcnic_host_sds_ring *sds_ring = data;
 447         struct qlcnic_adapter *adapter = sds_ring->adapter;
 448
 449         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 450                 goto done;
 451
 452         if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
 453                 return IRQ_NONE;
 454
 455 done:
 456         adapter->ahw->diag_cnt++;
 457         qlcnic_83xx_enable_intr(adapter, sds_ring);
 458
 459         return IRQ_HANDLED;
 460 }
 461
 462 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
 463 {
 464         u32 num_msix;
 465
 466         if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
 467                 qlcnic_83xx_set_legacy_intr_mask(adapter);
 468
 469         qlcnic_83xx_disable_mbx_intr(adapter);
 470
 471         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 472                 num_msix = adapter->ahw->num_msix - 1;
 473         else
 474                 num_msix = 0;
 475
 476         msleep(20);
 477         synchronize_irq(adapter->msix_entries[num_msix].vector);
 478         free_irq(adapter->msix_entries[num_msix].vector, adapter);
 479 }
 480
 481 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
 482 {
 483         irq_handler_t handler;
 484         u32 val;
 485         int err = 0;
 486         unsigned long flags = 0;
 487
 488         if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
 489             !(adapter->flags & QLCNIC_MSIX_ENABLED))
 490                 flags |= IRQF_SHARED;
 491
 492         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 493                 handler = qlcnic_83xx_handle_aen;
 494                 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
 495                 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
 496                 if (err) {
 497                         dev_err(&adapter->pdev->dev,
 498                                 "failed to register MBX interrupt\n");
 499                         return err;
 500                 }
 501         } else {
 502                 handler = qlcnic_83xx_intr;
 503                 val = adapter->msix_entries[0].vector;
 504                 err = request_irq(val, handler, flags, "qlcnic", adapter);
 505                 if (err) {
 506                         dev_err(&adapter->pdev->dev,
 507                                 "failed to register INTx interrupt\n");
 508                         return err;
 509                 }
 510                 qlcnic_83xx_clear_legacy_intr_mask(adapter);
 511         }
 512
 513         /* Enable mailbox interrupt */
 514         qlcnic_83xx_enable_mbx_intrpt(adapter);
 515
 516         return err;
 517 }
 518
 519 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
 520 {
 521         u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
 522         adapter->ahw->pci_func = (val >> 24) & 0xff;
 523 }
 524
 525 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
 526 {
 527         void __iomem *addr;
 528         u32 val, limit = 0;
 529
 530         struct qlcnic_hardware_context *ahw = adapter->ahw;
 531
 532         addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
 533         do {
 534                 val = readl(addr);
 535                 if (val) {
 536                         /* write the function number to register */
 537                         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
 538                                             ahw->pci_func);
 539                         return 0;
 540                 }
 541                 usleep_range(1000, 2000);
 542         } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
 543
 544         return -EIO;
 545 }
 546
 547 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
 548 {
 549         void __iomem *addr;
 550         u32 val;
 551         struct qlcnic_hardware_context *ahw = adapter->ahw;
 552
 553         addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
 554         val = readl(addr);
 555 }
 556
 557 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
 558                           loff_t offset, size_t size)
 559 {
 560         int ret;
 561         u32 data;
 562
 563         if (qlcnic_api_lock(adapter)) {
 564                 dev_err(&adapter->pdev->dev,
 565                         "%s: failed to acquire lock. addr offset 0x%x\n",
 566                         __func__, (u32)offset);
 567                 return;
 568         }
 569
 570         ret = qlcnic_83xx_rd_reg_indirect(adapter, (u32) offset);
 571         qlcnic_api_unlock(adapter);
 572
 573         if (ret == -EIO) {
 574                 dev_err(&adapter->pdev->dev,
 575                         "%s: failed. addr offset 0x%x\n",
 576                         __func__, (u32)offset);
 577                 return;
 578         }
 579         data = ret;
 580         memcpy(buf, &data, size);
 581 }
 582
 583 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
 584                            loff_t offset, size_t size)
 585 {
 586         u32 data;
 587
 588         memcpy(&data, buf, size);
 589         qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
 590 }
 591
 592 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
 593 {
 594         int status;
 595
 596         status = qlcnic_83xx_get_port_config(adapter);
 597         if (status) {
 598                 dev_err(&adapter->pdev->dev,
 599                         "Get Port Info failed\n");
 600         } else {
 601                 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
 602                         adapter->ahw->port_type = QLCNIC_XGBE;
 603                 else
 604                         adapter->ahw->port_type = QLCNIC_GBE;
 605
 606                 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
 607                         adapter->ahw->link_autoneg = AUTONEG_ENABLE;
 608         }
 609         return status;
 610 }
 611
 612 void qlcnic_83xx_enable_mbx_intrpt(struct qlcnic_adapter *adapter)
 613 {
 614         u32 val;
 615
 616         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 617                 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
 618         else
 619                 val = BIT_2;
 620
 621         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
 622         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 623 }
 624
 625 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
 626                           const struct pci_device_id *ent)
 627 {
 628         u32 op_mode, priv_level;
 629         struct qlcnic_hardware_context *ahw = adapter->ahw;
 630
 631         ahw->fw_hal_version = 2;
 632         qlcnic_get_func_no(adapter);
 633
 634         if (qlcnic_sriov_vf_check(adapter)) {
 635                 qlcnic_sriov_vf_set_ops(adapter);
 636                 return;
 637         }
 638
 639         /* Determine function privilege level */
 640         op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
 641         if (op_mode == QLC_83XX_DEFAULT_OPMODE)
 642                 priv_level = QLCNIC_MGMT_FUNC;
 643         else
 644                 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
 645                                                          ahw->pci_func);
 646
 647         if (priv_level == QLCNIC_NON_PRIV_FUNC) {
 648                 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
 649                 dev_info(&adapter->pdev->dev,
 650                          "HAL Version: %d Non Privileged function\n",
 651                          ahw->fw_hal_version);
 652                 adapter->nic_ops = &qlcnic_vf_ops;
 653         } else {
 654                 if (pci_find_ext_capability(adapter->pdev,
 655                                             PCI_EXT_CAP_ID_SRIOV))
 656                         set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
 657                 adapter->nic_ops = &qlcnic_83xx_ops;
 658         }
 659 }
 660
 661 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
 662                                         u32 data[]);
 663 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 664                                             u32 data[]);
 665
 666 static void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
 667                             struct qlcnic_cmd_args *cmd)
 668 {
 669         int i;
 670
 671         dev_info(&adapter->pdev->dev,
 672                  "Host MBX regs(%d)\n", cmd->req.num);
 673         for (i = 0; i < cmd->req.num; i++) {
 674                 if (i && !(i % 8))
 675                         pr_info("\n");
 676                 pr_info("%08x ", cmd->req.arg[i]);
 677         }
 678         pr_info("\n");
 679         dev_info(&adapter->pdev->dev,
 680                  "FW MBX regs(%d)\n", cmd->rsp.num);
 681         for (i = 0; i < cmd->rsp.num; i++) {
 682                 if (i && !(i % 8))
 683                         pr_info("\n");
 684                 pr_info("%08x ", cmd->rsp.arg[i]);
 685         }
 686         pr_info("\n");
 687 }
 688
 689 /* Mailbox response for mac rcode */
 690 u32 qlcnic_83xx_mac_rcode(struct qlcnic_adapter *adapter)
 691 {
 692         u32 fw_data;
 693         u8 mac_cmd_rcode;
 694
 695         fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
 696         mac_cmd_rcode = (u8)fw_data;
 697         if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
 698             mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
 699             mac_cmd_rcode == QLC_83XX_MAC_ABSENT)
 700                 return QLCNIC_RCODE_SUCCESS;
 701         return 1;
 702 }
 703
 704 u32 qlcnic_83xx_mbx_poll(struct qlcnic_adapter *adapter, u32 *wait_time)
 705 {
 706         u32 data;
 707         struct qlcnic_hardware_context *ahw = adapter->ahw;
 708         /* wait for mailbox completion */
 709         do {
 710                 data = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
 711                 if (++(*wait_time) > QLCNIC_MBX_TIMEOUT) {
 712                         data = QLCNIC_RCODE_TIMEOUT;
 713                         break;
 714                 }
 715                 mdelay(1);
 716         } while (!data);
 717         return data;
 718 }
 719
 720 int qlcnic_83xx_mbx_op(struct qlcnic_adapter *adapter,
 721                        struct qlcnic_cmd_args *cmd)
 722 {
 723         int i;
 724         u16 opcode;
 725         u8 mbx_err_code;
 726         unsigned long flags;
 727         struct qlcnic_hardware_context *ahw = adapter->ahw;
 728         u32 rsp, mbx_val, fw_data, rsp_num, mbx_cmd, wait_time = 0;
 729
 730         opcode = LSW(cmd->req.arg[0]);
 731         if (!test_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status)) {
 732                 dev_info(&adapter->pdev->dev,
 733                          "Mailbox cmd attempted, 0x%x\n", opcode);
 734                 dev_info(&adapter->pdev->dev, "Mailbox detached\n");
 735                 return 0;
 736         }
 737
 738         spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
 739         mbx_val = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
 740
 741         if (mbx_val) {
 742                 QLCDB(adapter, DRV,
 743                       "Mailbox cmd attempted, 0x%x\n", opcode);
 744                 QLCDB(adapter, DRV,
 745                       "Mailbox not available, 0x%x, collect FW dump\n",
 746                       mbx_val);
 747                 cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
 748                 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
 749                 return cmd->rsp.arg[0];
 750         }
 751
 752         /* Fill in mailbox registers */
 753         mbx_cmd = cmd->req.arg[0];
 754         writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
 755         for (i = 1; i < cmd->req.num; i++)
 756                 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
 757
 758         /* Signal FW about the impending command */
 759         QLCWRX(ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
 760 poll:
 761         rsp = qlcnic_83xx_mbx_poll(adapter, &wait_time);
 762         if (rsp != QLCNIC_RCODE_TIMEOUT) {
 763                 /* Get the FW response data */
 764                 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
 765                 if (fw_data &  QLCNIC_MBX_ASYNC_EVENT) {
 766                         __qlcnic_83xx_process_aen(adapter);
 767                         goto poll;
 768                 }
 769                 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
 770                 rsp_num = QLCNIC_MBX_NUM_REGS(fw_data);
 771                 opcode = QLCNIC_MBX_RSP(fw_data);
 772                 qlcnic_83xx_get_mbx_data(adapter, cmd);
 773
 774                 switch (mbx_err_code) {
 775                 case QLCNIC_MBX_RSP_OK:
 776                 case QLCNIC_MBX_PORT_RSP_OK:
 777                         rsp = QLCNIC_RCODE_SUCCESS;
 778                         break;
 779                 default:
 780                         if (opcode == QLCNIC_CMD_CONFIG_MAC_VLAN) {
 781                                 rsp = qlcnic_83xx_mac_rcode(adapter);
 782                                 if (!rsp)
 783                                         goto out;
 784                         }
 785                         dev_err(&adapter->pdev->dev,
 786                                 "MBX command 0x%x failed with err:0x%x\n",
 787                                 opcode, mbx_err_code);
 788                         rsp = mbx_err_code;
 789                         qlcnic_dump_mbx(adapter, cmd);
 790                         break;
 791                 }
 792                 goto out;
 793         }
 794
 795         dev_err(&adapter->pdev->dev, "MBX command 0x%x timed out\n",
 796                 QLCNIC_MBX_RSP(mbx_cmd));
 797         rsp = QLCNIC_RCODE_TIMEOUT;
 798 out:
 799         /* clear fw mbx control register */
 800         QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
 801         spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
 802         return rsp;
 803 }
 804
 805 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
 806                                struct qlcnic_adapter *adapter, u32 type)
 807 {
 808         int i, size;
 809         u32 temp;
 810         const struct qlcnic_mailbox_metadata *mbx_tbl;
 811
 812         mbx_tbl = qlcnic_83xx_mbx_tbl;
 813         size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
 814         for (i = 0; i < size; i++) {
 815                 if (type == mbx_tbl[i].cmd) {
 816                         mbx->op_type = QLC_83XX_FW_MBX_CMD;
 817                         mbx->req.num = mbx_tbl[i].in_args;
 818                         mbx->rsp.num = mbx_tbl[i].out_args;
 819                         mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
 820                                                GFP_ATOMIC);
 821                         if (!mbx->req.arg)
 822                                 return -ENOMEM;
 823                         mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
 824                                                GFP_ATOMIC);
 825                         if (!mbx->rsp.arg) {
 826                                 kfree(mbx->req.arg);
 827                                 mbx->req.arg = NULL;
 828                                 return -ENOMEM;
 829                         }
 830                         memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
 831                         memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
 832                         temp = adapter->ahw->fw_hal_version << 29;
 833                         mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
 834                         return 0;
 835                 }
 836         }
 837         return -EINVAL;
 838 }
 839
 840 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
 841 {
 842         struct qlcnic_adapter *adapter;
 843         struct qlcnic_cmd_args cmd;
 844         int i, err = 0;
 845
 846         adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
 847         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
 848         if (err)
 849                 return;
 850
 851         for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
 852                 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
 853
 854         err = qlcnic_issue_cmd(adapter, &cmd);
 855         if (err)
 856                 dev_info(&adapter->pdev->dev,
 857                          "%s: Mailbox IDC ACK failed.\n", __func__);
 858         qlcnic_free_mbx_args(&cmd);
 859 }
 860
 861 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 862                                             u32 data[])
 863 {
 864         dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
 865                 QLCNIC_MBX_RSP(data[0]));
 866         clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
 867         return;
 868 }
 869
 870 void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 871 {
 872         u32 event[QLC_83XX_MBX_AEN_CNT];
 873         int i;
 874         struct qlcnic_hardware_context *ahw = adapter->ahw;
 875
 876         for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 877                 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
 878
 879         switch (QLCNIC_MBX_RSP(event[0])) {
 880
 881         case QLCNIC_MBX_LINK_EVENT:
 882                 qlcnic_83xx_handle_link_aen(adapter, event);
 883                 break;
 884         case QLCNIC_MBX_COMP_EVENT:
 885                 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
 886                 break;
 887         case QLCNIC_MBX_REQUEST_EVENT:
 888                 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 889                         adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
 890                 queue_delayed_work(adapter->qlcnic_wq,
 891                                    &adapter->idc_aen_work, 0);
 892                 break;
 893         case QLCNIC_MBX_TIME_EXTEND_EVENT:
 894                 break;
 895         case QLCNIC_MBX_BC_EVENT:
 896                 qlcnic_sriov_handle_bc_event(adapter, event[1]);
 897                 break;
 898         case QLCNIC_MBX_SFP_INSERT_EVENT:
 899                 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
 900                          QLCNIC_MBX_RSP(event[0]));
 901                 break;
 902         case QLCNIC_MBX_SFP_REMOVE_EVENT:
 903                 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
 904                          QLCNIC_MBX_RSP(event[0]));
 905                 break;
 906         default:
 907                 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
 908                         QLCNIC_MBX_RSP(event[0]));
 909                 break;
 910         }
 911
 912         QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
 913 }
 914
 915 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 916 {
 917         struct qlcnic_hardware_context *ahw = adapter->ahw;
 918         u32 resp, event;
 919         unsigned long flags;
 920
 921         spin_lock_irqsave(&ahw->mbx_lock, flags);
 922
 923         resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
 924         if (resp & QLCNIC_SET_OWNER) {
 925                 event = readl(QLCNIC_MBX_FW(ahw, 0));
 926                 if (event &  QLCNIC_MBX_ASYNC_EVENT)
 927                         __qlcnic_83xx_process_aen(adapter);
 928         }
 929
 930         spin_unlock_irqrestore(&ahw->mbx_lock, flags);
 931 }
 932
 933 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
 934 {
 935         struct qlcnic_adapter *adapter;
 936
 937         adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
 938
 939         if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 940                 return;
 941
 942         qlcnic_83xx_process_aen(adapter);
 943         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
 944                            (HZ / 10));
 945 }
 946
 947 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
 948 {
 949         if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 950                 return;
 951
 952         INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
 953 }
 954
 955 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
 956 {
 957         if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
 958                 return;
 959         cancel_delayed_work_sync(&adapter->mbx_poll_work);
 960 }
 961
 962 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
 963 {
 964         int index, i, err, sds_mbx_size;
 965         u32 *buf, intrpt_id, intr_mask;
 966         u16 context_id;
 967         u8 num_sds;
 968         struct qlcnic_cmd_args cmd;
 969         struct qlcnic_host_sds_ring *sds;
 970         struct qlcnic_sds_mbx sds_mbx;
 971         struct qlcnic_add_rings_mbx_out *mbx_out;
 972         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
 973         struct qlcnic_hardware_context *ahw = adapter->ahw;
 974
 975         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
 976         context_id = recv_ctx->context_id;
 977         num_sds = (adapter->max_sds_rings - QLCNIC_MAX_RING_SETS);
 978         ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
 979                                     QLCNIC_CMD_ADD_RCV_RINGS);
 980         cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
 981
 982         /* set up status rings, mbx 2-81 */
 983         index = 2;
 984         for (i = 8; i < adapter->max_sds_rings; i++) {
 985                 memset(&sds_mbx, 0, sds_mbx_size);
 986                 sds = &recv_ctx->sds_rings[i];
 987                 sds->consumer = 0;
 988                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
 989                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
 990                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
 991                 sds_mbx.sds_ring_size = sds->num_desc;
 992
 993                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
 994                         intrpt_id = ahw->intr_tbl[i].id;
 995                 else
 996                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
 997
 998                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
 999                         sds_mbx.intrpt_id = intrpt_id;
1000                 else
1001                         sds_mbx.intrpt_id = 0xffff;
1002                 sds_mbx.intrpt_val = 0;
1003                 buf = &cmd.req.arg[index];
1004                 memcpy(buf, &sds_mbx, sds_mbx_size);
1005                 index += sds_mbx_size / sizeof(u32);
1006         }
1007
1008         /* send the mailbox command */
1009         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1010         if (err) {
1011                 dev_err(&adapter->pdev->dev,
1012                         "Failed to add rings %d\n", err);
1013                 goto out;
1014         }
1015
1016         mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1017         index = 0;
1018         /* status descriptor ring */
1019         for (i = 8; i < adapter->max_sds_rings; i++) {
1020                 sds = &recv_ctx->sds_rings[i];
1021                 sds->crb_sts_consumer = ahw->pci_base0 +
1022                                         mbx_out->host_csmr[index];
1023                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1024                         intr_mask = ahw->intr_tbl[i].src;
1025                 else
1026                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1027
1028                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1029                 index++;
1030         }
1031 out:
1032         qlcnic_free_mbx_args(&cmd);
1033         return err;
1034 }
1035
1036 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1037 {
1038         int err;
1039         u32 temp = 0;
1040         struct qlcnic_cmd_args cmd;
1041         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1042
1043         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1044                 return;
1045
1046         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1047                 cmd.req.arg[0] |= (0x3 << 29);
1048
1049         if (qlcnic_sriov_pf_check(adapter))
1050                 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1051
1052         cmd.req.arg[1] = recv_ctx->context_id | temp;
1053         err = qlcnic_issue_cmd(adapter, &cmd);
1054         if (err)
1055                 dev_err(&adapter->pdev->dev,
1056                         "Failed to destroy rx ctx in firmware\n");
1057
1058         recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1059         qlcnic_free_mbx_args(&cmd);
1060 }
1061
1062 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1063 {
1064         int i, err, index, sds_mbx_size, rds_mbx_size;
1065         u8 num_sds, num_rds;
1066         u32 *buf, intrpt_id, intr_mask, cap = 0;
1067         struct qlcnic_host_sds_ring *sds;
1068         struct qlcnic_host_rds_ring *rds;
1069         struct qlcnic_sds_mbx sds_mbx;
1070         struct qlcnic_rds_mbx rds_mbx;
1071         struct qlcnic_cmd_args cmd;
1072         struct qlcnic_rcv_mbx_out *mbx_out;
1073         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1074         struct qlcnic_hardware_context *ahw = adapter->ahw;
1075         num_rds = adapter->max_rds_rings;
1076
1077         if (adapter->max_sds_rings <= QLCNIC_MAX_RING_SETS)
1078                 num_sds = adapter->max_sds_rings;
1079         else
1080                 num_sds = QLCNIC_MAX_RING_SETS;
1081
1082         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1083         rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1084         cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1085
1086         if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1087                 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1088
1089         /* set mailbox hdr and capabilities */
1090         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1091                                     QLCNIC_CMD_CREATE_RX_CTX);
1092         if (err)
1093                 return err;
1094
1095         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1096                 cmd.req.arg[0] |= (0x3 << 29);
1097
1098         cmd.req.arg[1] = cap;
1099         cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1100                          (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1101
1102         if (qlcnic_sriov_pf_check(adapter))
1103                 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1104                                                          &cmd.req.arg[6]);
1105         /* set up status rings, mbx 8-57/87 */
1106         index = QLC_83XX_HOST_SDS_MBX_IDX;
1107         for (i = 0; i < num_sds; i++) {
1108                 memset(&sds_mbx, 0, sds_mbx_size);
1109                 sds = &recv_ctx->sds_rings[i];
1110                 sds->consumer = 0;
1111                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1112                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1113                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1114                 sds_mbx.sds_ring_size = sds->num_desc;
1115                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1116                         intrpt_id = ahw->intr_tbl[i].id;
1117                 else
1118                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1119                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1120                         sds_mbx.intrpt_id = intrpt_id;
1121                 else
1122                         sds_mbx.intrpt_id = 0xffff;
1123                 sds_mbx.intrpt_val = 0;
1124                 buf = &cmd.req.arg[index];
1125                 memcpy(buf, &sds_mbx, sds_mbx_size);
1126                 index += sds_mbx_size / sizeof(u32);
1127         }
1128         /* set up receive rings, mbx 88-111/135 */
1129         index = QLCNIC_HOST_RDS_MBX_IDX;
1130         rds = &recv_ctx->rds_rings[0];
1131         rds->producer = 0;
1132         memset(&rds_mbx, 0, rds_mbx_size);
1133         rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1134         rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1135         rds_mbx.reg_ring_sz = rds->dma_size;
1136         rds_mbx.reg_ring_len = rds->num_desc;
1137         /* Jumbo ring */
1138         rds = &recv_ctx->rds_rings[1];
1139         rds->producer = 0;
1140         rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1141         rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1142         rds_mbx.jmb_ring_sz = rds->dma_size;
1143         rds_mbx.jmb_ring_len = rds->num_desc;
1144         buf = &cmd.req.arg[index];
1145         memcpy(buf, &rds_mbx, rds_mbx_size);
1146
1147         /* send the mailbox command */
1148         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1149         if (err) {
1150                 dev_err(&adapter->pdev->dev,
1151                         "Failed to create Rx ctx in firmware%d\n", err);
1152                 goto out;
1153         }
1154         mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1155         recv_ctx->context_id = mbx_out->ctx_id;
1156         recv_ctx->state = mbx_out->state;
1157         recv_ctx->virt_port = mbx_out->vport_id;
1158         dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1159                  recv_ctx->context_id, recv_ctx->state);
1160         /* Receive descriptor ring */
1161         /* Standard ring */
1162         rds = &recv_ctx->rds_rings[0];
1163         rds->crb_rcv_producer = ahw->pci_base0 +
1164                                 mbx_out->host_prod[0].reg_buf;
1165         /* Jumbo ring */
1166         rds = &recv_ctx->rds_rings[1];
1167         rds->crb_rcv_producer = ahw->pci_base0 +
1168                                 mbx_out->host_prod[0].jmb_buf;
1169         /* status descriptor ring */
1170         for (i = 0; i < num_sds; i++) {
1171                 sds = &recv_ctx->sds_rings[i];
1172                 sds->crb_sts_consumer = ahw->pci_base0 +
1173                                         mbx_out->host_csmr[i];
1174                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1175                         intr_mask = ahw->intr_tbl[i].src;
1176                 else
1177                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1178                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1179         }
1180
1181         if (adapter->max_sds_rings > QLCNIC_MAX_RING_SETS)
1182                 err = qlcnic_83xx_add_rings(adapter);
1183 out:
1184         qlcnic_free_mbx_args(&cmd);
1185         return err;
1186 }
1187
1188 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1189                             struct qlcnic_host_tx_ring *tx_ring)
1190 {
1191         struct qlcnic_cmd_args cmd;
1192         u32 temp = 0;
1193
1194         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1195                 return;
1196
1197         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1198                 cmd.req.arg[0] |= (0x3 << 29);
1199
1200         if (qlcnic_sriov_pf_check(adapter))
1201                 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1202
1203         cmd.req.arg[1] = tx_ring->ctx_id | temp;
1204         if (qlcnic_issue_cmd(adapter, &cmd))
1205                 dev_err(&adapter->pdev->dev,
1206                         "Failed to destroy tx ctx in firmware\n");
1207         qlcnic_free_mbx_args(&cmd);
1208 }
1209
1210 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1211                               struct qlcnic_host_tx_ring *tx, int ring)
1212 {
1213         int err;
1214         u16 msix_id;
1215         u32 *buf, intr_mask, temp = 0;
1216         struct qlcnic_cmd_args cmd;
1217         struct qlcnic_tx_mbx mbx;
1218         struct qlcnic_tx_mbx_out *mbx_out;
1219         struct qlcnic_hardware_context *ahw = adapter->ahw;
1220         u32 msix_vector;
1221
1222         /* Reset host resources */
1223         tx->producer = 0;
1224         tx->sw_consumer = 0;
1225         *(tx->hw_consumer) = 0;
1226
1227         memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1228
1229         /* setup mailbox inbox registerss */
1230         mbx.phys_addr_low = LSD(tx->phys_addr);
1231         mbx.phys_addr_high = MSD(tx->phys_addr);
1232         mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1233         mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1234         mbx.size = tx->num_desc;
1235         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1236                 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1237                         msix_vector = adapter->max_sds_rings + ring;
1238                 else
1239                         msix_vector = adapter->max_sds_rings - 1;
1240                 msix_id = ahw->intr_tbl[msix_vector].id;
1241         } else {
1242                 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1243         }
1244
1245         if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1246                 mbx.intr_id = msix_id;
1247         else
1248                 mbx.intr_id = 0xffff;
1249         mbx.src = 0;
1250
1251         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1252         if (err)
1253                 return err;
1254
1255         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1256                 cmd.req.arg[0] |= (0x3 << 29);
1257
1258         if (qlcnic_sriov_pf_check(adapter))
1259                 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1260
1261         cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1262         cmd.req.arg[5] = QLCNIC_MAX_TX_QUEUES | temp;
1263         buf = &cmd.req.arg[6];
1264         memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1265         /* send the mailbox command*/
1266         err = qlcnic_issue_cmd(adapter, &cmd);
1267         if (err) {
1268                 dev_err(&adapter->pdev->dev,
1269                         "Failed to create Tx ctx in firmware 0x%x\n", err);
1270                 goto out;
1271         }
1272         mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1273         tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1274         tx->ctx_id = mbx_out->ctx_id;
1275         if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1276             !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1277                 intr_mask = ahw->intr_tbl[adapter->max_sds_rings + ring].src;
1278                 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1279         }
1280         dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1281                  tx->ctx_id, mbx_out->state);
1282 out:
1283         qlcnic_free_mbx_args(&cmd);
1284         return err;
1285 }
1286
1287 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1288                                       int num_sds_ring)
1289 {
1290         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1291         struct qlcnic_host_sds_ring *sds_ring;
1292         struct qlcnic_host_rds_ring *rds_ring;
1293         u16 adapter_state = adapter->is_up;
1294         u8 ring;
1295         int ret;
1296
1297         netif_device_detach(netdev);
1298
1299         if (netif_running(netdev))
1300                 __qlcnic_down(adapter, netdev);
1301
1302         qlcnic_detach(adapter);
1303
1304         adapter->max_sds_rings = 1;
1305         adapter->ahw->diag_test = test;
1306         adapter->ahw->linkup = 0;
1307
1308         ret = qlcnic_attach(adapter);
1309         if (ret) {
1310                 netif_device_attach(netdev);
1311                 return ret;
1312         }
1313
1314         ret = qlcnic_fw_create_ctx(adapter);
1315         if (ret) {
1316                 qlcnic_detach(adapter);
1317                 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1318                         adapter->max_sds_rings = num_sds_ring;
1319                         qlcnic_attach(adapter);
1320                 }
1321                 netif_device_attach(netdev);
1322                 return ret;
1323         }
1324
1325         for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1326                 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1327                 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1328         }
1329
1330         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1331                 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1332                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1333                         qlcnic_83xx_enable_intr(adapter, sds_ring);
1334                 }
1335         }
1336
1337         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1338                 /* disable and free mailbox interrupt */
1339                 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1340                         qlcnic_83xx_free_mbx_intr(adapter);
1341                 adapter->ahw->loopback_state = 0;
1342                 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1343         }
1344
1345         set_bit(__QLCNIC_DEV_UP, &adapter->state);
1346         return 0;
1347 }
1348
1349 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1350                                         int max_sds_rings)
1351 {
1352         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1353         struct qlcnic_host_sds_ring *sds_ring;
1354         int ring, err;
1355
1356         clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1357         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1358                 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1359                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1360                         qlcnic_83xx_disable_intr(adapter, sds_ring);
1361                 }
1362         }
1363
1364         qlcnic_fw_destroy_ctx(adapter);
1365         qlcnic_detach(adapter);
1366
1367         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1368                 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1369                         err = qlcnic_83xx_setup_mbx_intr(adapter);
1370                         if (err) {
1371                                 dev_err(&adapter->pdev->dev,
1372                                         "%s: failed to setup mbx interrupt\n",
1373                                         __func__);
1374                                 goto out;
1375                         }
1376                 }
1377         }
1378         adapter->ahw->diag_test = 0;
1379         adapter->max_sds_rings = max_sds_rings;
1380
1381         if (qlcnic_attach(adapter))
1382                 goto out;
1383
1384         if (netif_running(netdev))
1385                 __qlcnic_up(adapter, netdev);
1386 out:
1387         netif_device_attach(netdev);
1388 }
1389
1390 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1391                            u32 beacon)
1392 {
1393         struct qlcnic_cmd_args cmd;
1394         u32 mbx_in;
1395         int i, status = 0;
1396
1397         if (state) {
1398                 /* Get LED configuration */
1399                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1400                                                QLCNIC_CMD_GET_LED_CONFIG);
1401                 if (status)
1402                         return status;
1403
1404                 status = qlcnic_issue_cmd(adapter, &cmd);
1405                 if (status) {
1406                         dev_err(&adapter->pdev->dev,
1407                                 "Get led config failed.\n");
1408                         goto mbx_err;
1409                 } else {
1410                         for (i = 0; i < 4; i++)
1411                                 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1412                 }
1413                 qlcnic_free_mbx_args(&cmd);
1414                 /* Set LED Configuration */
1415                 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1416                           LSW(QLC_83XX_LED_CONFIG);
1417                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1418                                                QLCNIC_CMD_SET_LED_CONFIG);
1419                 if (status)
1420                         return status;
1421
1422                 cmd.req.arg[1] = mbx_in;
1423                 cmd.req.arg[2] = mbx_in;
1424                 cmd.req.arg[3] = mbx_in;
1425                 if (beacon)
1426                         cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1427                 status = qlcnic_issue_cmd(adapter, &cmd);
1428                 if (status) {
1429                         dev_err(&adapter->pdev->dev,
1430                                 "Set led config failed.\n");
1431                 }
1432 mbx_err:
1433                 qlcnic_free_mbx_args(&cmd);
1434                 return status;
1435
1436         } else {
1437                 /* Restoring default LED configuration */
1438                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1439                                                QLCNIC_CMD_SET_LED_CONFIG);
1440                 if (status)
1441                         return status;
1442
1443                 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1444                 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1445                 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1446                 if (beacon)
1447                         cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1448                 status = qlcnic_issue_cmd(adapter, &cmd);
1449                 if (status)
1450                         dev_err(&adapter->pdev->dev,
1451                                 "Restoring led config failed.\n");
1452                 qlcnic_free_mbx_args(&cmd);
1453                 return status;
1454         }
1455 }
1456
1457 int  qlcnic_83xx_set_led(struct net_device *netdev,
1458                          enum ethtool_phys_id_state state)
1459 {
1460         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1461         int err = -EIO, active = 1;
1462
1463         if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1464                 netdev_warn(netdev,
1465                             "LED test is not supported in non-privileged mode\n");
1466                 return -EOPNOTSUPP;
1467         }
1468
1469         switch (state) {
1470         case ETHTOOL_ID_ACTIVE:
1471                 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1472                         return -EBUSY;
1473
1474                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1475                         break;
1476
1477                 err = qlcnic_83xx_config_led(adapter, active, 0);
1478                 if (err)
1479                         netdev_err(netdev, "Failed to set LED blink state\n");
1480                 break;
1481         case ETHTOOL_ID_INACTIVE:
1482                 active = 0;
1483
1484                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1485                         break;
1486
1487                 err = qlcnic_83xx_config_led(adapter, active, 0);
1488                 if (err)
1489                         netdev_err(netdev, "Failed to reset LED blink state\n");
1490                 break;
1491
1492         default:
1493                 return -EINVAL;
1494         }
1495
1496         if (!active || err)
1497                 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1498
1499         return err;
1500 }
1501
1502 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter,
1503                                        int enable)
1504 {
1505         struct qlcnic_cmd_args cmd;
1506         int status;
1507
1508         if (qlcnic_sriov_vf_check(adapter))
1509                 return;
1510
1511         if (enable) {
1512                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1513                                                QLCNIC_CMD_INIT_NIC_FUNC);
1514                 if (status)
1515                         return;
1516
1517                 cmd.req.arg[1] = BIT_0 | BIT_31;
1518         } else {
1519                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1520                                                QLCNIC_CMD_STOP_NIC_FUNC);
1521                 if (status)
1522                         return;
1523
1524                 cmd.req.arg[1] = BIT_0 | BIT_31;
1525         }
1526         status = qlcnic_issue_cmd(adapter, &cmd);
1527         if (status)
1528                 dev_err(&adapter->pdev->dev,
1529                         "Failed to %s in NIC IDC function event.\n",
1530                         (enable ? "register" : "unregister"));
1531
1532         qlcnic_free_mbx_args(&cmd);
1533 }
1534
1535 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1536 {
1537         struct qlcnic_cmd_args cmd;
1538         int err;
1539
1540         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1541         if (err)
1542                 return err;
1543
1544         cmd.req.arg[1] = adapter->ahw->port_config;
1545         err = qlcnic_issue_cmd(adapter, &cmd);
1546         if (err)
1547                 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1548         qlcnic_free_mbx_args(&cmd);
1549         return err;
1550 }
1551
1552 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1553 {
1554         struct qlcnic_cmd_args cmd;
1555         int err;
1556
1557         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1558         if (err)
1559                 return err;
1560
1561         err = qlcnic_issue_cmd(adapter, &cmd);
1562         if (err)
1563                 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1564         else
1565                 adapter->ahw->port_config = cmd.rsp.arg[1];
1566         qlcnic_free_mbx_args(&cmd);
1567         return err;
1568 }
1569
1570 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1571 {
1572         int err;
1573         u32 temp;
1574         struct qlcnic_cmd_args cmd;
1575
1576         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1577         if (err)
1578                 return err;
1579
1580         temp = adapter->recv_ctx->context_id << 16;
1581         cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1582         err = qlcnic_issue_cmd(adapter, &cmd);
1583         if (err)
1584                 dev_info(&adapter->pdev->dev,
1585                          "Setup linkevent mailbox failed\n");
1586         qlcnic_free_mbx_args(&cmd);
1587         return err;
1588 }
1589
1590 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1591                                                  u32 *interface_id)
1592 {
1593         if (qlcnic_sriov_pf_check(adapter)) {
1594                 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1595         } else {
1596                 if (!qlcnic_sriov_vf_check(adapter))
1597                         *interface_id = adapter->recv_ctx->context_id << 16;
1598         }
1599 }
1600
1601 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1602 {
1603         int err;
1604         u32 temp = 0;
1605         struct qlcnic_cmd_args cmd;
1606
1607         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1608                 return -EIO;
1609
1610         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1611                                     QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1612         if (err)
1613                 return err;
1614
1615         qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1616         cmd.req.arg[1] = (mode ? 1 : 0) | temp;
1617         err = qlcnic_issue_cmd(adapter, &cmd);
1618         if (err)
1619                 dev_info(&adapter->pdev->dev,
1620                          "Promiscous mode config failed\n");
1621
1622         qlcnic_free_mbx_args(&cmd);
1623         return err;
1624 }
1625
1626 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1627 {
1628         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1629         struct qlcnic_hardware_context *ahw = adapter->ahw;
1630         int ret = 0, loop = 0, max_sds_rings = adapter->max_sds_rings;
1631
1632         if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1633                 netdev_warn(netdev,
1634                             "Loopback test not supported in non privileged mode\n");
1635                 return ret;
1636         }
1637
1638         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1639                 netdev_info(netdev, "Device is resetting\n");
1640                 return -EBUSY;
1641         }
1642
1643         if (qlcnic_get_diag_lock(adapter)) {
1644                 netdev_info(netdev, "Device is in diagnostics mode\n");
1645                 return -EBUSY;
1646         }
1647
1648         netdev_info(netdev, "%s loopback test in progress\n",
1649                     mode == QLCNIC_ILB_MODE ? "internal" : "external");
1650
1651         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1652                                          max_sds_rings);
1653         if (ret)
1654                 goto fail_diag_alloc;
1655
1656         ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1657         if (ret)
1658                 goto free_diag_res;
1659
1660         /* Poll for link up event before running traffic */
1661         do {
1662                 msleep(500);
1663                 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1664                         qlcnic_83xx_process_aen(adapter);
1665
1666                 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1667                         dev_info(&adapter->pdev->dev,
1668                                  "Firmware didn't sent link up event to loopback request\n");
1669                         ret = -QLCNIC_FW_NOT_RESPOND;
1670                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1671                         goto free_diag_res;
1672                 }
1673         } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1674
1675         /* Make sure carrier is off and queue is stopped during loopback */
1676         if (netif_running(netdev)) {
1677                 netif_carrier_off(netdev);
1678                 netif_stop_queue(netdev);
1679         }
1680
1681         ret = qlcnic_do_lb_test(adapter, mode);
1682
1683         qlcnic_83xx_clear_lb_mode(adapter, mode);
1684
1685 free_diag_res:
1686         qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
1687
1688 fail_diag_alloc:
1689         adapter->max_sds_rings = max_sds_rings;
1690         qlcnic_release_diag_lock(adapter);
1691         return ret;
1692 }
1693
1694 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1695 {
1696         struct qlcnic_hardware_context *ahw = adapter->ahw;
1697         int status = 0, loop = 0;
1698         u32 config;
1699
1700         status = qlcnic_83xx_get_port_config(adapter);
1701         if (status)
1702                 return status;
1703
1704         config = ahw->port_config;
1705         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1706
1707         if (mode == QLCNIC_ILB_MODE)
1708                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1709         if (mode == QLCNIC_ELB_MODE)
1710                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1711
1712         status = qlcnic_83xx_set_port_config(adapter);
1713         if (status) {
1714                 dev_err(&adapter->pdev->dev,
1715                         "Failed to Set Loopback Mode = 0x%x.\n",
1716                         ahw->port_config);
1717                 ahw->port_config = config;
1718                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1719                 return status;
1720         }
1721
1722         /* Wait for Link and IDC Completion AEN */
1723         do {
1724                 msleep(300);
1725                 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1726                         qlcnic_83xx_process_aen(adapter);
1727
1728                 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1729                         dev_err(&adapter->pdev->dev,
1730                                 "FW did not generate IDC completion AEN\n");
1731                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1732                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1733                         return -EIO;
1734                 }
1735         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1736
1737         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1738                                   QLCNIC_MAC_ADD);
1739         return status;
1740 }
1741
1742 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1743 {
1744         struct qlcnic_hardware_context *ahw = adapter->ahw;
1745         int status = 0, loop = 0;
1746         u32 config = ahw->port_config;
1747
1748         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1749         if (mode == QLCNIC_ILB_MODE)
1750                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1751         if (mode == QLCNIC_ELB_MODE)
1752                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1753
1754         status = qlcnic_83xx_set_port_config(adapter);
1755         if (status) {
1756                 dev_err(&adapter->pdev->dev,
1757                         "Failed to Clear Loopback Mode = 0x%x.\n",
1758                         ahw->port_config);
1759                 ahw->port_config = config;
1760                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1761                 return status;
1762         }
1763
1764         /* Wait for Link and IDC Completion AEN */
1765         do {
1766                 msleep(300);
1767                 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1768                         qlcnic_83xx_process_aen(adapter);
1769
1770                 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1771                         dev_err(&adapter->pdev->dev,
1772                                 "Firmware didn't sent IDC completion AEN\n");
1773                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1774                         return -EIO;
1775                 }
1776         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1777
1778         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1779                                   QLCNIC_MAC_DEL);
1780         return status;
1781 }
1782
1783 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1784                                                 u32 *interface_id)
1785 {
1786         if (qlcnic_sriov_pf_check(adapter)) {
1787                 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1788         } else {
1789                 if (!qlcnic_sriov_vf_check(adapter))
1790                         *interface_id = adapter->recv_ctx->context_id << 16;
1791         }
1792 }
1793
1794 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1795                                int mode)
1796 {
1797         int err;
1798         u32 temp = 0, temp_ip;
1799         struct qlcnic_cmd_args cmd;
1800
1801         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1802                                     QLCNIC_CMD_CONFIGURE_IP_ADDR);
1803         if (err)
1804                 return;
1805
1806         qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1807
1808         if (mode == QLCNIC_IP_UP)
1809                 cmd.req.arg[1] = 1 | temp;
1810         else
1811                 cmd.req.arg[1] = 2 | temp;
1812
1813         /*
1814          * Adapter needs IP address in network byte order.
1815          * But hardware mailbox registers go through writel(), hence IP address
1816          * gets swapped on big endian architecture.
1817          * To negate swapping of writel() on big endian architecture
1818          * use swab32(value).
1819          */
1820
1821         temp_ip = swab32(ntohl(ip));
1822         memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1823         err = qlcnic_issue_cmd(adapter, &cmd);
1824         if (err != QLCNIC_RCODE_SUCCESS)
1825                 dev_err(&adapter->netdev->dev,
1826                         "could not notify %s IP 0x%x request\n",
1827                         (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1828
1829         qlcnic_free_mbx_args(&cmd);
1830 }
1831
1832 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1833 {
1834         int err;
1835         u32 temp, arg1;
1836         struct qlcnic_cmd_args cmd;
1837         int lro_bit_mask;
1838
1839         lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1840
1841         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1842                 return 0;
1843
1844         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1845         if (err)
1846                 return err;
1847
1848         temp = adapter->recv_ctx->context_id << 16;
1849         arg1 = lro_bit_mask | temp;
1850         cmd.req.arg[1] = arg1;
1851
1852         err = qlcnic_issue_cmd(adapter, &cmd);
1853         if (err)
1854                 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1855         qlcnic_free_mbx_args(&cmd);
1856
1857         return err;
1858 }
1859
1860 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1861 {
1862         int err;
1863         u32 word;
1864         struct qlcnic_cmd_args cmd;
1865         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1866                             0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1867                             0x255b0ec26d5a56daULL };
1868
1869         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1870         if (err)
1871                 return err;
1872         /*
1873          * RSS request:
1874          * bits 3-0: Rsvd
1875          *      5-4: hash_type_ipv4
1876          *      7-6: hash_type_ipv6
1877          *        8: enable
1878          *        9: use indirection table
1879          *    16-31: indirection table mask
1880          */
1881         word =  ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1882                 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1883                 ((u32)(enable & 0x1) << 8) |
1884                 ((0x7ULL) << 16);
1885         cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1886         cmd.req.arg[2] = word;
1887         memcpy(&cmd.req.arg[4], key, sizeof(key));
1888
1889         err = qlcnic_issue_cmd(adapter, &cmd);
1890
1891         if (err)
1892                 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1893         qlcnic_free_mbx_args(&cmd);
1894
1895         return err;
1896
1897 }
1898
1899 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1900                                                  u32 *interface_id)
1901 {
1902         if (qlcnic_sriov_pf_check(adapter)) {
1903                 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1904         } else {
1905                 if (!qlcnic_sriov_vf_check(adapter))
1906                         *interface_id = adapter->recv_ctx->context_id << 16;
1907         }
1908 }
1909
1910 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1911                                    u16 vlan_id, u8 op)
1912 {
1913         int err;
1914         u32 *buf, temp = 0;
1915         struct qlcnic_cmd_args cmd;
1916         struct qlcnic_macvlan_mbx mv;
1917
1918         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1919                 return -EIO;
1920
1921         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
1922         if (err)
1923                 return err;
1924
1925         if (vlan_id)
1926                 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
1927                      QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
1928
1929         cmd.req.arg[1] = op | (1 << 8);
1930         qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
1931         cmd.req.arg[1] |= temp;
1932         mv.vlan = vlan_id;
1933         mv.mac_addr0 = addr[0];
1934         mv.mac_addr1 = addr[1];
1935         mv.mac_addr2 = addr[2];
1936         mv.mac_addr3 = addr[3];
1937         mv.mac_addr4 = addr[4];
1938         mv.mac_addr5 = addr[5];
1939         buf = &cmd.req.arg[2];
1940         memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
1941         err = qlcnic_issue_cmd(adapter, &cmd);
1942         if (err)
1943                 dev_err(&adapter->pdev->dev,
1944                         "MAC-VLAN %s to CAM failed, err=%d.\n",
1945                         ((op == 1) ? "add " : "delete "), err);
1946         qlcnic_free_mbx_args(&cmd);
1947         return err;
1948 }
1949
1950 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
1951                                   u16 vlan_id)
1952 {
1953         u8 mac[ETH_ALEN];
1954         memcpy(&mac, addr, ETH_ALEN);
1955         qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
1956 }
1957
1958 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
1959                                u8 type, struct qlcnic_cmd_args *cmd)
1960 {
1961         switch (type) {
1962         case QLCNIC_SET_STATION_MAC:
1963         case QLCNIC_SET_FAC_DEF_MAC:
1964                 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
1965                 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
1966                 break;
1967         }
1968         cmd->req.arg[1] = type;
1969 }
1970
1971 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
1972 {
1973         int err, i;
1974         struct qlcnic_cmd_args cmd;
1975         u32 mac_low, mac_high;
1976
1977         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
1978         if (err)
1979                 return err;
1980
1981         qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
1982         err = qlcnic_issue_cmd(adapter, &cmd);
1983
1984         if (err == QLCNIC_RCODE_SUCCESS) {
1985                 mac_low = cmd.rsp.arg[1];
1986                 mac_high = cmd.rsp.arg[2];
1987
1988                 for (i = 0; i < 2; i++)
1989                         mac[i] = (u8) (mac_high >> ((1 - i) * 8));
1990                 for (i = 2; i < 6; i++)
1991                         mac[i] = (u8) (mac_low >> ((5 - i) * 8));
1992         } else {
1993                 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
1994                         err);
1995                 err = -EIO;
1996         }
1997         qlcnic_free_mbx_args(&cmd);
1998         return err;
1999 }
2000
2001 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2002 {
2003         int err;
2004         u16 temp;
2005         struct qlcnic_cmd_args cmd;
2006         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2007
2008         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2009                 return;
2010
2011         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2012         if (err)
2013                 return;
2014
2015         if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2016                 temp = adapter->recv_ctx->context_id;
2017                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2018                 temp = coal->rx_time_us;
2019                 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2020         } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2021                 temp = adapter->tx_ring->ctx_id;
2022                 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2023                 temp = coal->tx_time_us;
2024                 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2025         }
2026         cmd.req.arg[3] = coal->flag;
2027         err = qlcnic_issue_cmd(adapter, &cmd);
2028         if (err != QLCNIC_RCODE_SUCCESS)
2029                 dev_info(&adapter->pdev->dev,
2030                          "Failed to send interrupt coalescence parameters\n");
2031         qlcnic_free_mbx_args(&cmd);
2032 }
2033
2034 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2035                                         u32 data[])
2036 {
2037         u8 link_status, duplex;
2038         /* link speed */
2039         link_status = LSB(data[3]) & 1;
2040         adapter->ahw->link_speed = MSW(data[2]);
2041         adapter->ahw->link_autoneg = MSB(MSW(data[3]));
2042         adapter->ahw->module_type = MSB(LSW(data[3]));
2043         duplex = LSB(MSW(data[3]));
2044         if (duplex)
2045                 adapter->ahw->link_duplex = DUPLEX_FULL;
2046         else
2047                 adapter->ahw->link_duplex = DUPLEX_HALF;
2048         adapter->ahw->has_link_events = 1;
2049         qlcnic_advert_link_change(adapter, link_status);
2050 }
2051
2052 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2053 {
2054         struct qlcnic_adapter *adapter = data;
2055         unsigned long flags;
2056         u32 mask, resp, event;
2057
2058         spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
2059         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2060         if (!(resp & QLCNIC_SET_OWNER))
2061                 goto out;
2062
2063         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2064         if (event &  QLCNIC_MBX_ASYNC_EVENT)
2065                 __qlcnic_83xx_process_aen(adapter);
2066 out:
2067         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2068         writel(0, adapter->ahw->pci_base0 + mask);
2069         spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
2070
2071         return IRQ_HANDLED;
2072 }
2073
2074 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
2075 {
2076         int err = -EIO;
2077         struct qlcnic_cmd_args cmd;
2078
2079         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2080                 dev_err(&adapter->pdev->dev,
2081                         "%s: Error, invoked by non management func\n",
2082                         __func__);
2083                 return err;
2084         }
2085
2086         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
2087         if (err)
2088                 return err;
2089
2090         cmd.req.arg[1] = (port & 0xf) | BIT_4;
2091         err = qlcnic_issue_cmd(adapter, &cmd);
2092
2093         if (err != QLCNIC_RCODE_SUCCESS) {
2094                 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
2095                         err);
2096                 err = -EIO;
2097         }
2098         qlcnic_free_mbx_args(&cmd);
2099
2100         return err;
2101
2102 }
2103
2104 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2105                              struct qlcnic_info *nic)
2106 {
2107         int i, err = -EIO;
2108         struct qlcnic_cmd_args cmd;
2109
2110         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2111                 dev_err(&adapter->pdev->dev,
2112                         "%s: Error, invoked by non management func\n",
2113                         __func__);
2114                 return err;
2115         }
2116
2117         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2118         if (err)
2119                 return err;
2120
2121         cmd.req.arg[1] = (nic->pci_func << 16);
2122         cmd.req.arg[2] = 0x1 << 16;
2123         cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2124         cmd.req.arg[4] = nic->capabilities;
2125         cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2126         cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2127         cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2128         for (i = 8; i < 32; i++)
2129                 cmd.req.arg[i] = 0;
2130
2131         err = qlcnic_issue_cmd(adapter, &cmd);
2132
2133         if (err != QLCNIC_RCODE_SUCCESS) {
2134                 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2135                         err);
2136                 err = -EIO;
2137         }
2138
2139         qlcnic_free_mbx_args(&cmd);
2140
2141         return err;
2142 }
2143
2144 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2145                              struct qlcnic_info *npar_info, u8 func_id)
2146 {
2147         int err;
2148         u32 temp;
2149         u8 op = 0;
2150         struct qlcnic_cmd_args cmd;
2151
2152         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2153         if (err)
2154                 return err;
2155
2156         if (func_id != adapter->ahw->pci_func) {
2157                 temp = func_id << 16;
2158                 cmd.req.arg[1] = op | BIT_31 | temp;
2159         } else {
2160                 cmd.req.arg[1] = adapter->ahw->pci_func << 16;
2161         }
2162         err = qlcnic_issue_cmd(adapter, &cmd);
2163         if (err) {
2164                 dev_info(&adapter->pdev->dev,
2165                          "Failed to get nic info %d\n", err);
2166                 goto out;
2167         }
2168
2169         npar_info->op_type = cmd.rsp.arg[1];
2170         npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2171         npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2172         npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2173         npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2174         npar_info->capabilities = cmd.rsp.arg[4];
2175         npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2176         npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2177         npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2178         npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2179         npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2180         npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2181         if (cmd.rsp.arg[8] & 0x1)
2182                 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2183         if (cmd.rsp.arg[8] & 0x10000) {
2184                 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2185                 npar_info->max_linkspeed_reg_offset = temp;
2186         }
2187
2188 out:
2189         qlcnic_free_mbx_args(&cmd);
2190         return err;
2191 }
2192
2193 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2194                              struct qlcnic_pci_info *pci_info)
2195 {
2196         struct qlcnic_hardware_context *ahw = adapter->ahw;
2197         struct device *dev = &adapter->pdev->dev;
2198         struct qlcnic_cmd_args cmd;
2199         int i, err = 0, j = 0;
2200         u32 temp;
2201
2202         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2203         if (err)
2204                 return err;
2205
2206         err = qlcnic_issue_cmd(adapter, &cmd);
2207
2208         ahw->act_pci_func = 0;
2209         if (err == QLCNIC_RCODE_SUCCESS) {
2210                 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2211                 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) {
2212                         pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2213                         pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2214                         i++;
2215                         pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2216                         if (pci_info->type == QLCNIC_TYPE_NIC)
2217                                 ahw->act_pci_func++;
2218                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2219                         pci_info->default_port = temp;
2220                         i++;
2221                         pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2222                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2223                         pci_info->tx_max_bw = temp;
2224                         i = i + 2;
2225                         memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2226                         i++;
2227                         memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2228                         i = i + 3;
2229                         if (ahw->op_mode == QLCNIC_MGMT_FUNC)
2230                                 dev_info(dev, "id = %d active = %d type = %d\n"
2231                                          "\tport = %d min bw = %d max bw = %d\n"
2232                                          "\tmac_addr =  %pM\n", pci_info->id,
2233                                          pci_info->active, pci_info->type,
2234                                          pci_info->default_port,
2235                                          pci_info->tx_min_bw,
2236                                          pci_info->tx_max_bw, pci_info->mac);
2237                 }
2238                 if (ahw->op_mode == QLCNIC_MGMT_FUNC)
2239                         dev_info(dev, "Max vNIC functions = %d, active vNIC functions = %d\n",
2240                                  ahw->max_pci_func, ahw->act_pci_func);
2241
2242         } else {
2243                 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2244                 err = -EIO;
2245         }
2246
2247         qlcnic_free_mbx_args(&cmd);
2248
2249         return err;
2250 }
2251
2252 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2253 {
2254         int i, index, err;
2255         u8 max_ints;
2256         u32 val, temp, type;
2257         struct qlcnic_cmd_args cmd;
2258
2259         max_ints = adapter->ahw->num_msix - 1;
2260         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2261         if (err)
2262                 return err;
2263
2264         cmd.req.arg[1] = max_ints;
2265
2266         if (qlcnic_sriov_vf_check(adapter))
2267                 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2268
2269         for (i = 0, index = 2; i < max_ints; i++) {
2270                 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2271                 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2272                 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2273                         val |= (adapter->ahw->intr_tbl[i].id << 16);
2274                 cmd.req.arg[index++] = val;
2275         }
2276         err = qlcnic_issue_cmd(adapter, &cmd);
2277         if (err) {
2278                 dev_err(&adapter->pdev->dev,
2279                         "Failed to configure interrupts 0x%x\n", err);
2280                 goto out;
2281         }
2282
2283         max_ints = cmd.rsp.arg[1];
2284         for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2285                 val = cmd.rsp.arg[index];
2286                 if (LSB(val)) {
2287                         dev_info(&adapter->pdev->dev,
2288                                  "Can't configure interrupt %d\n",
2289                                  adapter->ahw->intr_tbl[i].id);
2290                         continue;
2291                 }
2292                 if (op_type) {
2293                         adapter->ahw->intr_tbl[i].id = MSW(val);
2294                         adapter->ahw->intr_tbl[i].enabled = 1;
2295                         temp = cmd.rsp.arg[index + 1];
2296                         adapter->ahw->intr_tbl[i].src = temp;
2297                 } else {
2298                         adapter->ahw->intr_tbl[i].id = i;
2299                         adapter->ahw->intr_tbl[i].enabled = 0;
2300                         adapter->ahw->intr_tbl[i].src = 0;
2301                 }
2302         }
2303 out:
2304         qlcnic_free_mbx_args(&cmd);
2305         return err;
2306 }
2307
2308 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2309 {
2310         int id, timeout = 0;
2311         u32 status = 0;
2312
2313         while (status == 0) {
2314                 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2315                 if (status)
2316                         break;
2317
2318                 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2319                         id = QLC_SHARED_REG_RD32(adapter,
2320                                                  QLCNIC_FLASH_LOCK_OWNER);
2321                         dev_err(&adapter->pdev->dev,
2322                                 "%s: failed, lock held by %d\n", __func__, id);
2323                         return -EIO;
2324                 }
2325                 usleep_range(1000, 2000);
2326         }
2327
2328         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2329         return 0;
2330 }
2331
2332 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2333 {
2334         QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2335         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2336 }
2337
2338 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2339                                       u32 flash_addr, u8 *p_data,
2340                                       int count)
2341 {
2342         int i, ret;
2343         u32 word, range, flash_offset, addr = flash_addr;
2344         ulong indirect_add, direct_window;
2345
2346         flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2347         if (addr & 0x3) {
2348                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2349                 return -EIO;
2350         }
2351
2352         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2353                                      (addr));
2354
2355         range = flash_offset + (count * sizeof(u32));
2356         /* Check if data is spread across multiple sectors */
2357         if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2358
2359                 /* Multi sector read */
2360                 for (i = 0; i < count; i++) {
2361                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2362                         ret = qlcnic_83xx_rd_reg_indirect(adapter,
2363                                                           indirect_add);
2364                         if (ret == -EIO)
2365                                 return -EIO;
2366
2367                         word = ret;
2368                         *(u32 *)p_data  = word;
2369                         p_data = p_data + 4;
2370                         addr = addr + 4;
2371                         flash_offset = flash_offset + 4;
2372
2373                         if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2374                                 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2375                                 /* This write is needed once for each sector */
2376                                 qlcnic_83xx_wrt_reg_indirect(adapter,
2377                                                              direct_window,
2378                                                              (addr));
2379                                 flash_offset = 0;
2380                         }
2381                 }
2382         } else {
2383                 /* Single sector read */
2384                 for (i = 0; i < count; i++) {
2385                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2386                         ret = qlcnic_83xx_rd_reg_indirect(adapter,
2387                                                           indirect_add);
2388                         if (ret == -EIO)
2389                                 return -EIO;
2390
2391                         word = ret;
2392                         *(u32 *)p_data  = word;
2393                         p_data = p_data + 4;
2394                         addr = addr + 4;
2395                 }
2396         }
2397
2398         return 0;
2399 }
2400
2401 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2402 {
2403         u32 status;
2404         int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2405
2406         do {
2407                 status = qlcnic_83xx_rd_reg_indirect(adapter,
2408                                                      QLC_83XX_FLASH_STATUS);
2409                 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2410                     QLC_83XX_FLASH_STATUS_READY)
2411                         break;
2412
2413                 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2414         } while (--retries);
2415
2416         if (!retries)
2417                 return -EIO;
2418
2419         return 0;
2420 }
2421
2422 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2423 {
2424         int ret;
2425         u32 cmd;
2426         cmd = adapter->ahw->fdt.write_statusreg_cmd;
2427         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2428                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2429         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2430                                      adapter->ahw->fdt.write_enable_bits);
2431         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2432                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2433         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2434         if (ret)
2435                 return -EIO;
2436
2437         return 0;
2438 }
2439
2440 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2441 {
2442         int ret;
2443
2444         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2445                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2446                                      adapter->ahw->fdt.write_statusreg_cmd));
2447         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2448                                      adapter->ahw->fdt.write_disable_bits);
2449         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2450                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2451         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2452         if (ret)
2453                 return -EIO;
2454
2455         return 0;
2456 }
2457
2458 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2459 {
2460         int ret, mfg_id;
2461
2462         if (qlcnic_83xx_lock_flash(adapter))
2463                 return -EIO;
2464
2465         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2466                                      QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2467         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2468                                      QLC_83XX_FLASH_READ_CTRL);
2469         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2470         if (ret) {
2471                 qlcnic_83xx_unlock_flash(adapter);
2472                 return -EIO;
2473         }
2474
2475         mfg_id = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
2476         if (mfg_id == -EIO)
2477                 return -EIO;
2478
2479         adapter->flash_mfg_id = (mfg_id & 0xFF);
2480         qlcnic_83xx_unlock_flash(adapter);
2481
2482         return 0;
2483 }
2484
2485 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2486 {
2487         int count, fdt_size, ret = 0;
2488
2489         fdt_size = sizeof(struct qlcnic_fdt);
2490         count = fdt_size / sizeof(u32);
2491
2492         if (qlcnic_83xx_lock_flash(adapter))
2493                 return -EIO;
2494
2495         memset(&adapter->ahw->fdt, 0, fdt_size);
2496         ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2497                                                 (u8 *)&adapter->ahw->fdt,
2498                                                 count);
2499
2500         qlcnic_83xx_unlock_flash(adapter);
2501         return ret;
2502 }
2503
2504 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2505                                    u32 sector_start_addr)
2506 {
2507         u32 reversed_addr, addr1, addr2, cmd;
2508         int ret = -EIO;
2509
2510         if (qlcnic_83xx_lock_flash(adapter) != 0)
2511                 return -EIO;
2512
2513         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2514                 ret = qlcnic_83xx_enable_flash_write(adapter);
2515                 if (ret) {
2516                         qlcnic_83xx_unlock_flash(adapter);
2517                         dev_err(&adapter->pdev->dev,
2518                                 "%s failed at %d\n",
2519                                 __func__, __LINE__);
2520                         return ret;
2521                 }
2522         }
2523
2524         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2525         if (ret) {
2526                 qlcnic_83xx_unlock_flash(adapter);
2527                 dev_err(&adapter->pdev->dev,
2528                         "%s: failed at %d\n", __func__, __LINE__);
2529                 return -EIO;
2530         }
2531
2532         addr1 = (sector_start_addr & 0xFF) << 16;
2533         addr2 = (sector_start_addr & 0xFF0000) >> 16;
2534         reversed_addr = addr1 | addr2;
2535
2536         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2537                                      reversed_addr);
2538         cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2539         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2540                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2541         else
2542                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2543                                              QLC_83XX_FLASH_OEM_ERASE_SIG);
2544         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2545                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2546
2547         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2548         if (ret) {
2549                 qlcnic_83xx_unlock_flash(adapter);
2550                 dev_err(&adapter->pdev->dev,
2551                         "%s: failed at %d\n", __func__, __LINE__);
2552                 return -EIO;
2553         }
2554
2555         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2556                 ret = qlcnic_83xx_disable_flash_write(adapter);
2557                 if (ret) {
2558                         qlcnic_83xx_unlock_flash(adapter);
2559                         dev_err(&adapter->pdev->dev,
2560                                 "%s: failed at %d\n", __func__, __LINE__);
2561                         return ret;
2562                 }
2563         }
2564
2565         qlcnic_83xx_unlock_flash(adapter);
2566
2567         return 0;
2568 }
2569
2570 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2571                               u32 *p_data)
2572 {
2573         int ret = -EIO;
2574         u32 addr1 = 0x00800000 | (addr >> 2);
2575
2576         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2577         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2578         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2579                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2580         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2581         if (ret) {
2582                 dev_err(&adapter->pdev->dev,
2583                         "%s: failed at %d\n", __func__, __LINE__);
2584                 return -EIO;
2585         }
2586
2587         return 0;
2588 }
2589
2590 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2591                                  u32 *p_data, int count)
2592 {
2593         u32 temp;
2594         int ret = -EIO;
2595
2596         if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2597             (count > QLC_83XX_FLASH_WRITE_MAX)) {
2598                 dev_err(&adapter->pdev->dev,
2599                         "%s: Invalid word count\n", __func__);
2600                 return -EIO;
2601         }
2602
2603         temp = qlcnic_83xx_rd_reg_indirect(adapter,
2604                                            QLC_83XX_FLASH_SPI_CONTROL);
2605         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2606                                      (temp | QLC_83XX_FLASH_SPI_CTRL));
2607         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2608                                      QLC_83XX_FLASH_ADDR_TEMP_VAL);
2609
2610         /* First DWORD write */
2611         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2612         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2613                                      QLC_83XX_FLASH_FIRST_MS_PATTERN);
2614         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2615         if (ret) {
2616                 dev_err(&adapter->pdev->dev,
2617                         "%s: failed at %d\n", __func__, __LINE__);
2618                 return -EIO;
2619         }
2620
2621         count--;
2622         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2623                                      QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2624         /* Second to N-1 DWORD writes */
2625         while (count != 1) {
2626                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2627                                              *p_data++);
2628                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2629                                              QLC_83XX_FLASH_SECOND_MS_PATTERN);
2630                 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2631                 if (ret) {
2632                         dev_err(&adapter->pdev->dev,
2633                                 "%s: failed at %d\n", __func__, __LINE__);
2634                         return -EIO;
2635                 }
2636                 count--;
2637         }
2638
2639         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2640                                      QLC_83XX_FLASH_ADDR_TEMP_VAL |
2641                                      (addr >> 2));
2642         /* Last DWORD write */
2643         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2644         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2645                                      QLC_83XX_FLASH_LAST_MS_PATTERN);
2646         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2647         if (ret) {
2648                 dev_err(&adapter->pdev->dev,
2649                         "%s: failed at %d\n", __func__, __LINE__);
2650                 return -EIO;
2651         }
2652
2653         ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_SPI_STATUS);
2654         if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2655                 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2656                         __func__, __LINE__);
2657                 /* Operation failed, clear error bit */
2658                 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2659                                                    QLC_83XX_FLASH_SPI_CONTROL);
2660                 qlcnic_83xx_wrt_reg_indirect(adapter,
2661                                              QLC_83XX_FLASH_SPI_CONTROL,
2662                                              (temp | QLC_83XX_FLASH_SPI_CTRL));
2663         }
2664
2665         return 0;
2666 }
2667
2668 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2669 {
2670         u32 val, id;
2671
2672         val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2673
2674         /* Check if recovery need to be performed by the calling function */
2675         if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2676                 val = val & ~0x3F;
2677                 val = val | ((adapter->portnum << 2) |
2678                              QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2679                 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2680                 dev_info(&adapter->pdev->dev,
2681                          "%s: lock recovery initiated\n", __func__);
2682                 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2683                 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2684                 id = ((val >> 2) & 0xF);
2685                 if (id == adapter->portnum) {
2686                         val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2687                         val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2688                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2689                         /* Force release the lock */
2690                         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2691                         /* Clear recovery bits */
2692                         val = val & ~0x3F;
2693                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2694                         dev_info(&adapter->pdev->dev,
2695                                  "%s: lock recovery completed\n", __func__);
2696                 } else {
2697                         dev_info(&adapter->pdev->dev,
2698                                  "%s: func %d to resume lock recovery process\n",
2699                                  __func__, id);
2700                 }
2701         } else {
2702                 dev_info(&adapter->pdev->dev,
2703                          "%s: lock recovery initiated by other functions\n",
2704                          __func__);
2705         }
2706 }
2707
2708 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2709 {
2710         u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2711         int max_attempt = 0;
2712
2713         while (status == 0) {
2714                 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2715                 if (status)
2716                         break;
2717
2718                 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2719                 i++;
2720
2721                 if (i == 1)
2722                         temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2723
2724                 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2725                         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2726                         if (val == temp) {
2727                                 id = val & 0xFF;
2728                                 dev_info(&adapter->pdev->dev,
2729                                          "%s: lock to be recovered from %d\n",
2730                                          __func__, id);
2731                                 qlcnic_83xx_recover_driver_lock(adapter);
2732                                 i = 0;
2733                                 max_attempt++;
2734                         } else {
2735                                 dev_err(&adapter->pdev->dev,
2736                                         "%s: failed to get lock\n", __func__);
2737                                 return -EIO;
2738                         }
2739                 }
2740
2741                 /* Force exit from while loop after few attempts */
2742                 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2743                         dev_err(&adapter->pdev->dev,
2744                                 "%s: failed to get lock\n", __func__);
2745                         return -EIO;
2746                 }
2747         }
2748
2749         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2750         lock_alive_counter = val >> 8;
2751         lock_alive_counter++;
2752         val = lock_alive_counter << 8 | adapter->portnum;
2753         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2754
2755         return 0;
2756 }
2757
2758 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2759 {
2760         u32 val, lock_alive_counter, id;
2761
2762         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2763         id = val & 0xFF;
2764         lock_alive_counter = val >> 8;
2765
2766         if (id != adapter->portnum)
2767                 dev_err(&adapter->pdev->dev,
2768                         "%s:Warning func %d is unlocking lock owned by %d\n",
2769                         __func__, adapter->portnum, id);
2770
2771         val = (lock_alive_counter << 8) | 0xFF;
2772         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2773         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2774 }
2775
2776 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2777                                 u32 *data, u32 count)
2778 {
2779         int i, j, ret = 0;
2780         u32 temp;
2781
2782         /* Check alignment */
2783         if (addr & 0xF)
2784                 return -EIO;
2785
2786         mutex_lock(&adapter->ahw->mem_lock);
2787         qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2788
2789         for (i = 0; i < count; i++, addr += 16) {
2790                 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2791                                      QLCNIC_ADDR_QDR_NET_MAX)) ||
2792                       (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2793                                      QLCNIC_ADDR_DDR_NET_MAX)))) {
2794                         mutex_unlock(&adapter->ahw->mem_lock);
2795                         return -EIO;
2796                 }
2797
2798                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2799                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2800                                              *data++);
2801                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2802                                              *data++);
2803                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2804                                              *data++);
2805                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2806                                              *data++);
2807                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2808                                              QLCNIC_TA_WRITE_ENABLE);
2809                 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2810                                              QLCNIC_TA_WRITE_START);
2811
2812                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2813                         temp = qlcnic_83xx_rd_reg_indirect(adapter,
2814                                                            QLCNIC_MS_CTRL);
2815                         if ((temp & TA_CTL_BUSY) == 0)
2816                                 break;
2817                 }
2818
2819                 /* Status check failure */
2820                 if (j >= MAX_CTL_CHECK) {
2821                         printk_ratelimited(KERN_WARNING
2822                                            "MS memory write failed\n");
2823                         mutex_unlock(&adapter->ahw->mem_lock);
2824                         return -EIO;
2825                 }
2826         }
2827
2828         mutex_unlock(&adapter->ahw->mem_lock);
2829
2830         return ret;
2831 }
2832
2833 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2834                              u8 *p_data, int count)
2835 {
2836         int i, ret;
2837         u32 word, addr = flash_addr;
2838         ulong  indirect_addr;
2839
2840         if (qlcnic_83xx_lock_flash(adapter) != 0)
2841                 return -EIO;
2842
2843         if (addr & 0x3) {
2844                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2845                 qlcnic_83xx_unlock_flash(adapter);
2846                 return -EIO;
2847         }
2848
2849         for (i = 0; i < count; i++) {
2850                 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2851                                                  QLC_83XX_FLASH_DIRECT_WINDOW,
2852                                                  (addr))) {
2853                         qlcnic_83xx_unlock_flash(adapter);
2854                         return -EIO;
2855                 }
2856
2857                 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2858                 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2859                                                   indirect_addr);
2860                 if (ret == -EIO)
2861                         return -EIO;
2862                 word = ret;
2863                 *(u32 *)p_data  = word;
2864                 p_data = p_data + 4;
2865                 addr = addr + 4;
2866         }
2867
2868         qlcnic_83xx_unlock_flash(adapter);
2869
2870         return 0;
2871 }
2872
2873 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2874 {
2875         u8 pci_func;
2876         int err;
2877         u32 config = 0, state;
2878         struct qlcnic_cmd_args cmd;
2879         struct qlcnic_hardware_context *ahw = adapter->ahw;
2880
2881         if (qlcnic_sriov_vf_check(adapter))
2882                 pci_func = adapter->portnum;
2883         else
2884                 pci_func = ahw->pci_func;
2885
2886         state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
2887         if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
2888                 dev_info(&adapter->pdev->dev, "link state down\n");
2889                 return config;
2890         }
2891
2892         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
2893         if (err)
2894                 return err;
2895
2896         err = qlcnic_issue_cmd(adapter, &cmd);
2897         if (err) {
2898                 dev_info(&adapter->pdev->dev,
2899                          "Get Link Status Command failed: 0x%x\n", err);
2900                 goto out;
2901         } else {
2902                 config = cmd.rsp.arg[1];
2903                 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
2904                 case QLC_83XX_10M_LINK:
2905                         ahw->link_speed = SPEED_10;
2906                         break;
2907                 case QLC_83XX_100M_LINK:
2908                         ahw->link_speed = SPEED_100;
2909                         break;
2910                 case QLC_83XX_1G_LINK:
2911                         ahw->link_speed = SPEED_1000;
2912                         break;
2913                 case QLC_83XX_10G_LINK:
2914                         ahw->link_speed = SPEED_10000;
2915                         break;
2916                 default:
2917                         ahw->link_speed = 0;
2918                         break;
2919                 }
2920                 config = cmd.rsp.arg[3];
2921                 if (QLC_83XX_SFP_PRESENT(config)) {
2922                         switch (ahw->module_type) {
2923                         case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
2924                         case LINKEVENT_MODULE_OPTICAL_SRLR:
2925                         case LINKEVENT_MODULE_OPTICAL_LRM:
2926                         case LINKEVENT_MODULE_OPTICAL_SFP_1G:
2927                                 ahw->supported_type = PORT_FIBRE;
2928                                 break;
2929                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
2930                         case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
2931                         case LINKEVENT_MODULE_TWINAX:
2932                                 ahw->supported_type = PORT_TP;
2933                                 break;
2934                         default:
2935                                 ahw->supported_type = PORT_OTHER;
2936                         }
2937                 }
2938                 if (config & 1)
2939                         err = 1;
2940         }
2941 out:
2942         qlcnic_free_mbx_args(&cmd);
2943         return config;
2944 }
2945
2946 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
2947                              struct ethtool_cmd *ecmd)
2948 {
2949         u32 config = 0;
2950         int status = 0;
2951         struct qlcnic_hardware_context *ahw = adapter->ahw;
2952
2953         /* Get port configuration info */
2954         status = qlcnic_83xx_get_port_info(adapter);
2955         /* Get Link Status related info */
2956         config = qlcnic_83xx_test_link(adapter);
2957         ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
2958         /* hard code until there is a way to get it from flash */
2959         ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
2960
2961         if (netif_running(adapter->netdev) && ahw->has_link_events) {
2962                 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
2963                 ecmd->duplex = ahw->link_duplex;
2964                 ecmd->autoneg = ahw->link_autoneg;
2965         } else {
2966                 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
2967                 ecmd->duplex = DUPLEX_UNKNOWN;
2968                 ecmd->autoneg = AUTONEG_DISABLE;
2969         }
2970
2971         if (ahw->port_type == QLCNIC_XGBE) {
2972                 ecmd->supported = SUPPORTED_1000baseT_Full;
2973                 ecmd->advertising = ADVERTISED_1000baseT_Full;
2974         } else {
2975                 ecmd->supported = (SUPPORTED_10baseT_Half |
2976                                    SUPPORTED_10baseT_Full |
2977                                    SUPPORTED_100baseT_Half |
2978                                    SUPPORTED_100baseT_Full |
2979                                    SUPPORTED_1000baseT_Half |
2980                                    SUPPORTED_1000baseT_Full);
2981                 ecmd->advertising = (ADVERTISED_100baseT_Half |
2982                                      ADVERTISED_100baseT_Full |
2983                                      ADVERTISED_1000baseT_Half |
2984                                      ADVERTISED_1000baseT_Full);
2985         }
2986
2987         switch (ahw->supported_type) {
2988         case PORT_FIBRE:
2989                 ecmd->supported |= SUPPORTED_FIBRE;
2990                 ecmd->advertising |= ADVERTISED_FIBRE;
2991                 ecmd->port = PORT_FIBRE;
2992                 ecmd->transceiver = XCVR_EXTERNAL;
2993                 break;
2994         case PORT_TP:
2995                 ecmd->supported |= SUPPORTED_TP;
2996                 ecmd->advertising |= ADVERTISED_TP;
2997                 ecmd->port = PORT_TP;
2998                 ecmd->transceiver = XCVR_INTERNAL;
2999                 break;
3000         default:
3001                 ecmd->supported |= SUPPORTED_FIBRE;
3002                 ecmd->advertising |= ADVERTISED_FIBRE;
3003                 ecmd->port = PORT_OTHER;
3004                 ecmd->transceiver = XCVR_EXTERNAL;
3005                 break;
3006         }
3007         ecmd->phy_address = ahw->physical_port;
3008         return status;
3009 }
3010
3011 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3012                              struct ethtool_cmd *ecmd)
3013 {
3014         int status = 0;
3015         u32 config = adapter->ahw->port_config;
3016
3017         if (ecmd->autoneg)
3018                 adapter->ahw->port_config |= BIT_15;
3019
3020         switch (ethtool_cmd_speed(ecmd)) {
3021         case SPEED_10:
3022                 adapter->ahw->port_config |= BIT_8;
3023                 break;
3024         case SPEED_100:
3025                 adapter->ahw->port_config |= BIT_9;
3026                 break;
3027         case SPEED_1000:
3028                 adapter->ahw->port_config |= BIT_10;
3029                 break;
3030         case SPEED_10000:
3031                 adapter->ahw->port_config |= BIT_11;
3032                 break;
3033         default:
3034                 return -EINVAL;
3035         }
3036
3037         status = qlcnic_83xx_set_port_config(adapter);
3038         if (status) {
3039                 dev_info(&adapter->pdev->dev,
3040                          "Faild to Set Link Speed and autoneg.\n");
3041                 adapter->ahw->port_config = config;
3042         }
3043         return status;
3044 }
3045
3046 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3047                                           u64 *data, int index)
3048 {
3049         u32 low, hi;
3050         u64 val;
3051
3052         low = cmd->rsp.arg[index];
3053         hi = cmd->rsp.arg[index + 1];
3054         val = (((u64) low) | (((u64) hi) << 32));
3055         *data++ = val;
3056         return data;
3057 }
3058
3059 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3060                                    struct qlcnic_cmd_args *cmd, u64 *data,
3061                                    int type, int *ret)
3062 {
3063         int err, k, total_regs;
3064
3065         *ret = 0;
3066         err = qlcnic_issue_cmd(adapter, cmd);
3067         if (err != QLCNIC_RCODE_SUCCESS) {
3068                 dev_info(&adapter->pdev->dev,
3069                          "Error in get statistics mailbox command\n");
3070                 *ret = -EIO;
3071                 return data;
3072         }
3073         total_regs = cmd->rsp.num;
3074         switch (type) {
3075         case QLC_83XX_STAT_MAC:
3076                 /* fill in MAC tx counters */
3077                 for (k = 2; k < 28; k += 2)
3078                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3079                 /* skip 24 bytes of reserved area */
3080                 /* fill in MAC rx counters */
3081                 for (k += 6; k < 60; k += 2)
3082                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3083                 /* skip 24 bytes of reserved area */
3084                 /* fill in MAC rx frame stats */
3085                 for (k += 6; k < 80; k += 2)
3086                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3087                 /* fill in eSwitch stats */
3088                 for (; k < total_regs; k += 2)
3089                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3090                 break;
3091         case QLC_83XX_STAT_RX:
3092                 for (k = 2; k < 8; k += 2)
3093                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3094                 /* skip 8 bytes of reserved data */
3095                 for (k += 2; k < 24; k += 2)
3096                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3097                 /* skip 8 bytes containing RE1FBQ error data */
3098                 for (k += 2; k < total_regs; k += 2)
3099                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3100                 break;
3101         case QLC_83XX_STAT_TX:
3102                 for (k = 2; k < 10; k += 2)
3103                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3104                 /* skip 8 bytes of reserved data */
3105                 for (k += 2; k < total_regs; k += 2)
3106                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3107                 break;
3108         default:
3109                 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3110                 *ret = -EIO;
3111         }
3112         return data;
3113 }
3114
3115 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3116 {
3117         struct qlcnic_cmd_args cmd;
3118         struct net_device *netdev = adapter->netdev;
3119         int ret = 0;
3120
3121         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3122         if (ret)
3123                 return;
3124         /* Get Tx stats */
3125         cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3126         cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3127         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3128                                       QLC_83XX_STAT_TX, &ret);
3129         if (ret) {
3130                 netdev_err(netdev, "Error getting Tx stats\n");
3131                 goto out;
3132         }
3133         /* Get MAC stats */
3134         cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3135         cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3136         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3137         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3138                                       QLC_83XX_STAT_MAC, &ret);
3139         if (ret) {
3140                 netdev_err(netdev, "Error getting MAC stats\n");
3141                 goto out;
3142         }
3143         /* Get Rx stats */
3144         cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3145         cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3146         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3147         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3148                                       QLC_83XX_STAT_RX, &ret);
3149         if (ret)
3150                 netdev_err(netdev, "Error getting Rx stats\n");
3151 out:
3152         qlcnic_free_mbx_args(&cmd);
3153 }
3154
3155 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3156 {
3157         u32 major, minor, sub;
3158
3159         major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3160         minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3161         sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3162
3163         if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3164                 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3165                          __func__);
3166                 return 1;
3167         }
3168         return 0;
3169 }
3170
3171 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3172 {
3173         return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3174                 sizeof(adapter->ahw->ext_reg_tbl)) +
3175                 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) +
3176                 sizeof(adapter->ahw->reg_tbl));
3177 }
3178
3179 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3180 {
3181         int i, j = 0;
3182
3183         for (i = QLCNIC_DEV_INFO_SIZE + 1;
3184              j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3185                 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3186
3187         for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3188                 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3189         return i;
3190 }
3191
3192 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3193 {
3194         struct qlcnic_adapter *adapter = netdev_priv(netdev);
3195         struct qlcnic_hardware_context *ahw = adapter->ahw;
3196         struct qlcnic_cmd_args cmd;
3197         u32 data;
3198         u16 intrpt_id, id;
3199         u8 val;
3200         int ret, max_sds_rings = adapter->max_sds_rings;
3201
3202         if (qlcnic_get_diag_lock(adapter)) {
3203                 netdev_info(netdev, "Device in diagnostics mode\n");
3204                 return -EBUSY;
3205         }
3206
3207         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3208                                          max_sds_rings);
3209         if (ret)
3210                 goto fail_diag_irq;
3211
3212         ahw->diag_cnt = 0;
3213         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3214         if (ret)
3215                 goto fail_diag_irq;
3216
3217         if (adapter->flags & QLCNIC_MSIX_ENABLED)
3218                 intrpt_id = ahw->intr_tbl[0].id;
3219         else
3220                 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3221
3222         cmd.req.arg[1] = 1;
3223         cmd.req.arg[2] = intrpt_id;
3224         cmd.req.arg[3] = BIT_0;
3225
3226         ret = qlcnic_issue_cmd(adapter, &cmd);
3227         data = cmd.rsp.arg[2];
3228         id = LSW(data);
3229         val = LSB(MSW(data));
3230         if (id != intrpt_id)
3231                 dev_info(&adapter->pdev->dev,
3232                          "Interrupt generated: 0x%x, requested:0x%x\n",
3233                          id, intrpt_id);
3234         if (val)
3235                 dev_err(&adapter->pdev->dev,
3236                          "Interrupt test error: 0x%x\n", val);
3237         if (ret)
3238                 goto done;
3239
3240         msleep(20);
3241         ret = !ahw->diag_cnt;
3242
3243 done:
3244         qlcnic_free_mbx_args(&cmd);
3245         qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
3246
3247 fail_diag_irq:
3248         adapter->max_sds_rings = max_sds_rings;
3249         qlcnic_release_diag_lock(adapter);
3250         return ret;
3251 }
3252
3253 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3254                                 struct ethtool_pauseparam *pause)
3255 {
3256         struct qlcnic_hardware_context *ahw = adapter->ahw;
3257         int status = 0;
3258         u32 config;
3259
3260         status = qlcnic_83xx_get_port_config(adapter);
3261         if (status) {
3262                 dev_err(&adapter->pdev->dev,
3263                         "%s: Get Pause Config failed\n", __func__);
3264                 return;
3265         }
3266         config = ahw->port_config;
3267         if (config & QLC_83XX_CFG_STD_PAUSE) {
3268                 if (config & QLC_83XX_CFG_STD_TX_PAUSE)
3269                         pause->tx_pause = 1;
3270                 if (config & QLC_83XX_CFG_STD_RX_PAUSE)
3271                         pause->rx_pause = 1;
3272         }
3273
3274         if (QLC_83XX_AUTONEG(config))
3275                 pause->autoneg = 1;
3276 }
3277
3278 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3279                                struct ethtool_pauseparam *pause)
3280 {
3281         struct qlcnic_hardware_context *ahw = adapter->ahw;
3282         int status = 0;
3283         u32 config;
3284
3285         status = qlcnic_83xx_get_port_config(adapter);
3286         if (status) {
3287                 dev_err(&adapter->pdev->dev,
3288                         "%s: Get Pause Config failed.\n", __func__);
3289                 return status;
3290         }
3291         config = ahw->port_config;
3292
3293         if (ahw->port_type == QLCNIC_GBE) {
3294                 if (pause->autoneg)
3295                         ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3296                 if (!pause->autoneg)
3297                         ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3298         } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3299                 return -EOPNOTSUPP;
3300         }
3301
3302         if (!(config & QLC_83XX_CFG_STD_PAUSE))
3303                 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3304
3305         if (pause->rx_pause && pause->tx_pause) {
3306                 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3307         } else if (pause->rx_pause && !pause->tx_pause) {
3308                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3309                 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3310         } else if (pause->tx_pause && !pause->rx_pause) {
3311                 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3312                 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3313         } else if (!pause->rx_pause && !pause->tx_pause) {
3314                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_RX_PAUSE;
3315         }
3316         status = qlcnic_83xx_set_port_config(adapter);
3317         if (status) {
3318                 dev_err(&adapter->pdev->dev,
3319                         "%s: Set Pause Config failed.\n", __func__);
3320                 ahw->port_config = config;
3321         }
3322         return status;
3323 }
3324
3325 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3326 {
3327         int ret;
3328
3329         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3330                                      QLC_83XX_FLASH_OEM_READ_SIG);
3331         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3332                                      QLC_83XX_FLASH_READ_CTRL);
3333         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3334         if (ret)
3335                 return -EIO;
3336
3337         ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
3338         return ret & 0xFF;
3339 }
3340
3341 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3342 {
3343         int status;
3344
3345         status = qlcnic_83xx_read_flash_status_reg(adapter);
3346         if (status == -EIO) {
3347                 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3348                          __func__);
3349                 return 1;
3350         }
3351         return 0;
3352 }