2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/timer.h>
28 #include <linux/vmalloc.h>
31 #include <asm/byteorder.h>
32 #include <linux/bitops.h>
33 #include <linux/if_vlan.h>
35 #include "qlcnic_hdr.h"
37 #define _QLCNIC_LINUX_MAJOR 5
38 #define _QLCNIC_LINUX_MINOR 0
39 #define _QLCNIC_LINUX_SUBVERSION 28
40 #define QLCNIC_LINUX_VERSIONID "5.0.28"
41 #define QLCNIC_DRV_IDC_VER 0x01
42 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
43 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
45 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
46 #define _major(v) (((v) >> 24) & 0xff)
47 #define _minor(v) (((v) >> 16) & 0xff)
48 #define _build(v) ((v) & 0xffff)
50 /* version in image has weird encoding:
53 * 31:16 - build (little endian)
55 #define QLCNIC_DECODE_VERSION(v) \
56 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
58 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
59 #define QLCNIC_NUM_FLASH_SECTORS (64)
60 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
61 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
62 * QLCNIC_FLASH_SECTOR_SIZE)
64 #define RCV_DESC_RINGSIZE(rds_ring) \
65 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
66 #define RCV_BUFF_RINGSIZE(rds_ring) \
67 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
68 #define STATUS_DESC_RINGSIZE(sds_ring) \
69 (sizeof(struct status_desc) * (sds_ring)->num_desc)
70 #define TX_BUFF_RINGSIZE(tx_ring) \
71 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
72 #define TX_DESC_RINGSIZE(tx_ring) \
73 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
75 #define QLCNIC_P3P_A0 0x50
76 #define QLCNIC_P3P_C0 0x58
78 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
80 #define FIRST_PAGE_GROUP_START 0
81 #define FIRST_PAGE_GROUP_END 0x100000
83 #define P3P_MAX_MTU (9600)
84 #define P3P_MIN_MTU (68)
85 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
87 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
88 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
89 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
90 #define QLCNIC_LRO_BUFFER_EXTRA 2048
92 /* Opcodes to be used with the commands */
93 #define TX_ETHER_PKT 0x01
94 #define TX_TCP_PKT 0x02
95 #define TX_UDP_PKT 0x03
96 #define TX_IP_PKT 0x04
97 #define TX_TCP_LSO 0x05
98 #define TX_TCP_LSO6 0x06
99 #define TX_TCPV6_PKT 0x0b
100 #define TX_UDPV6_PKT 0x0c
103 #define QLCNIC_MAX_FRAGS_PER_TX 14
104 #define MAX_TSO_HEADER_DESC 2
105 #define MGMT_CMD_DESC_RESV 4
106 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
107 + MGMT_CMD_DESC_RESV)
108 #define QLCNIC_MAX_TX_TIMEOUTS 2
111 * Following are the states of the Phantom. Phantom will set them and
112 * Host will read to check if the fields are correct.
114 #define PHAN_INITIALIZE_FAILED 0xffff
115 #define PHAN_INITIALIZE_COMPLETE 0xff01
117 /* Host writes the following to notify that it has done the init-handshake */
118 #define PHAN_INITIALIZE_ACK 0xf00f
119 #define PHAN_PEG_RCV_INITIALIZED 0xff01
121 #define NUM_RCV_DESC_RINGS 3
123 #define RCV_RING_NORMAL 0
124 #define RCV_RING_JUMBO 1
126 #define MIN_CMD_DESCRIPTORS 64
127 #define MIN_RCV_DESCRIPTORS 64
128 #define MIN_JUMBO_DESCRIPTORS 32
130 #define MAX_CMD_DESCRIPTORS 1024
131 #define MAX_RCV_DESCRIPTORS_1G 4096
132 #define MAX_RCV_DESCRIPTORS_10G 8192
133 #define MAX_RCV_DESCRIPTORS_VF 2048
134 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
135 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
137 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
138 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
139 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
140 #define MAX_RDS_RINGS 2
142 #define get_next_index(index, length) \
143 (((index) + 1) & ((length) - 1))
146 * Following data structures describe the descriptors that will be used.
147 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
148 * we are doing LSO (above the 1500 size packet) only.
151 #define FLAGS_VLAN_TAGGED 0x10
152 #define FLAGS_VLAN_OOB 0x40
154 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
155 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
156 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
157 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
158 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
159 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
161 #define qlcnic_set_tx_port(_desc, _port) \
162 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
164 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
165 ((_desc)->flags_opcode |= \
166 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
168 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
169 ((_desc)->nfrags__length = \
170 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
172 struct cmd_desc_type0 {
173 u8 tcp_hdr_offset; /* For LSO only */
174 u8 ip_hdr_offset; /* For LSO only */
175 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
176 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
180 __le16 reference_handle;
182 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
183 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
184 __le16 conn_id; /* IPSec offoad only */
189 __le16 buffer_length[4];
193 u8 eth_addr[ETH_ALEN];
196 } __attribute__ ((aligned(64)));
198 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
200 __le16 reference_handle;
202 __le32 buffer_length; /* allocated buffer length (usually 2K) */
206 /* opcode field in status_desc */
207 #define QLCNIC_SYN_OFFLOAD 0x03
208 #define QLCNIC_RXPKT_DESC 0x04
209 #define QLCNIC_OLD_RXPKT_DESC 0x3f
210 #define QLCNIC_RESPONSE_DESC 0x05
211 #define QLCNIC_LRO_DESC 0x12
213 /* for status field in status_desc */
214 #define STATUS_CKSUM_LOOP 0
215 #define STATUS_CKSUM_OK 2
217 /* owner bits of status_desc */
218 #define STATUS_OWNER_HOST (0x1ULL << 56)
219 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
221 /* Status descriptor:
222 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
223 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
224 53-55 desc_cnt, 56-57 owner, 58-63 opcode
226 #define qlcnic_get_sts_port(sts_data) \
228 #define qlcnic_get_sts_status(sts_data) \
229 (((sts_data) >> 4) & 0x0F)
230 #define qlcnic_get_sts_type(sts_data) \
231 (((sts_data) >> 8) & 0x0F)
232 #define qlcnic_get_sts_totallength(sts_data) \
233 (((sts_data) >> 12) & 0xFFFF)
234 #define qlcnic_get_sts_refhandle(sts_data) \
235 (((sts_data) >> 28) & 0xFFFF)
236 #define qlcnic_get_sts_prot(sts_data) \
237 (((sts_data) >> 44) & 0x0F)
238 #define qlcnic_get_sts_pkt_offset(sts_data) \
239 (((sts_data) >> 48) & 0x1F)
240 #define qlcnic_get_sts_desc_cnt(sts_data) \
241 (((sts_data) >> 53) & 0x7)
242 #define qlcnic_get_sts_opcode(sts_data) \
243 (((sts_data) >> 58) & 0x03F)
245 #define qlcnic_get_lro_sts_refhandle(sts_data) \
246 ((sts_data) & 0x0FFFF)
247 #define qlcnic_get_lro_sts_length(sts_data) \
248 (((sts_data) >> 16) & 0x0FFFF)
249 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
250 (((sts_data) >> 32) & 0x0FF)
251 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
252 (((sts_data) >> 40) & 0x0FF)
253 #define qlcnic_get_lro_sts_timestamp(sts_data) \
254 (((sts_data) >> 48) & 0x1)
255 #define qlcnic_get_lro_sts_type(sts_data) \
256 (((sts_data) >> 49) & 0x7)
257 #define qlcnic_get_lro_sts_push_flag(sts_data) \
258 (((sts_data) >> 52) & 0x1)
259 #define qlcnic_get_lro_sts_seq_number(sts_data) \
260 ((sts_data) & 0x0FFFFFFFF)
264 __le64 status_desc_data[2];
265 } __attribute__ ((aligned(16)));
267 /* UNIFIED ROMIMAGE */
268 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
269 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
270 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
271 #define QLCNIC_UNI_DIR_SECT_FW 0x7
274 #define QLCNIC_UNI_CHIP_REV_OFF 10
275 #define QLCNIC_UNI_FLAGS_OFF 11
276 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
277 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
278 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
280 struct uni_table_desc{
287 struct uni_data_desc{
293 /* Flash Defines and Structures */
294 #define QLCNIC_FLT_LOCATION 0x3F1000
295 #define QLCNIC_B0_FW_IMAGE_REGION 0x74
296 #define QLCNIC_C0_FW_IMAGE_REGION 0x97
297 #define QLCNIC_BOOTLD_REGION 0X72
298 struct qlcnic_flt_header {
305 struct qlcnic_flt_entry {
315 /* Magic number to let user know flash is programmed */
316 #define QLCNIC_BDINFO_MAGIC 0x12345678
318 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
319 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
320 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
321 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
322 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
323 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
324 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
325 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
326 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
327 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
328 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
329 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
330 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
331 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
333 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
335 /* Flash memory map */
336 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
337 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
338 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
339 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
341 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
342 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
343 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
344 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
346 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
347 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
349 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
350 #define QLCNIC_UNIFIED_ROMIMAGE 0
351 #define QLCNIC_FLASH_ROMIMAGE 1
352 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
354 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
355 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
357 extern char qlcnic_driver_name[];
359 /* Number of status descriptors to handle per interrupt */
360 #define MAX_STATUS_HANDLE (64)
363 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
364 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
366 struct qlcnic_skb_frag {
371 /* Following defines are for the state of the buffers */
372 #define QLCNIC_BUFFER_FREE 0
373 #define QLCNIC_BUFFER_BUSY 1
376 * There will be one qlcnic_buffer per skb packet. These will be
377 * used to save the dma info for pci_unmap_page()
379 struct qlcnic_cmd_buffer {
381 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
385 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
386 struct qlcnic_rx_buffer {
389 struct list_head list;
394 #define QLCNIC_GBE 0x01
395 #define QLCNIC_XGBE 0x02
398 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
399 * adjusted based on configured MTU.
401 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
402 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
404 #define QLCNIC_INTR_DEFAULT 0x04
405 #define QLCNIC_CONFIG_INTR_COALESCE 3
407 struct qlcnic_nic_intr_coalesce {
416 struct qlcnic_dump_template_hdr {
427 __le32 saved_state[16];
432 struct qlcnic_fw_dump {
433 u8 clr; /* flag to indicate if dump is cleared */
434 u8 enable; /* enable/disable dump */
435 u32 size; /* total size of the dump */
436 void *data; /* dump data area */
437 struct qlcnic_dump_template_hdr *tmpl_hdr;
441 * One hardware_context{} per adapter
442 * contains interrupt info as well shared hardware info.
444 struct qlcnic_hardware_context {
445 void __iomem *pci_base0;
446 void __iomem *ocm_win_crb;
448 unsigned long pci_len0;
451 struct mutex mem_lock;
462 struct qlcnic_nic_intr_coalesce coal;
463 struct qlcnic_fw_dump fw_dump;
466 struct qlcnic_adapter_stats {
480 u64 skb_alloc_failure;
482 u64 rx_dma_map_error;
483 u64 tx_dma_map_error;
487 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
488 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
490 struct qlcnic_host_rds_ring {
491 void __iomem *crb_rcv_producer;
492 struct rcv_desc *desc_head;
493 struct qlcnic_rx_buffer *rx_buf_arr;
499 struct list_head free_list;
501 dma_addr_t phys_addr;
502 } ____cacheline_internodealigned_in_smp;
504 struct qlcnic_host_sds_ring {
507 void __iomem *crb_sts_consumer;
509 struct status_desc *desc_head;
510 struct qlcnic_adapter *adapter;
511 struct napi_struct napi;
512 struct list_head free_list[NUM_RCV_DESC_RINGS];
514 void __iomem *crb_intr_mask;
517 dma_addr_t phys_addr;
518 char name[IFNAMSIZ+4];
519 } ____cacheline_internodealigned_in_smp;
521 struct qlcnic_host_tx_ring {
525 void __iomem *crb_cmd_producer;
526 struct cmd_desc_type0 *desc_head;
527 struct qlcnic_cmd_buffer *cmd_buf_arr;
530 dma_addr_t phys_addr;
531 dma_addr_t hw_cons_phys_addr;
532 struct netdev_queue *txq;
533 } ____cacheline_internodealigned_in_smp;
536 * Receive context. There is one such structure per instance of the
537 * receive processing. Any state information that is relevant to
538 * the receive, and is must be in this structure. The global data may be
541 struct qlcnic_recv_context {
542 struct qlcnic_host_rds_ring *rds_rings;
543 struct qlcnic_host_sds_ring *sds_rings;
550 /* HW context creation */
552 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
553 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
554 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
556 #define QLCNIC_CDRP_CMD_BIT 0x80000000
559 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
560 * in the crb QLCNIC_CDRP_CRB_OFFSET.
562 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
563 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
565 #define QLCNIC_CDRP_RSP_OK 0x00000001
566 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
567 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
570 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
571 * the crb QLCNIC_CDRP_CRB_OFFSET.
573 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
574 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
576 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
577 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
578 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
579 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
580 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
581 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
582 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
583 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
584 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
585 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
586 #define QLCNIC_CDRP_CMD_INTRPT_TEST 0x00000011
587 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
588 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
589 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
590 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
591 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
592 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
593 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
594 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
595 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
597 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
598 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
599 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
600 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
601 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
602 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
603 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
604 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
605 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
606 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
607 #define QLCNIC_CDRP_CMD_CONFIG_PORT 0x0000002E
608 #define QLCNIC_CDRP_CMD_TEMP_SIZE 0x0000002f
609 #define QLCNIC_CDRP_CMD_GET_TEMP_HDR 0x00000030
610 #define QLCNIC_CDRP_CMD_GET_MAC_STATS 0x00000037
612 #define QLCNIC_RCODE_SUCCESS 0
613 #define QLCNIC_RCODE_NOT_SUPPORTED 9
614 #define QLCNIC_RCODE_TIMEOUT 17
615 #define QLCNIC_DESTROY_CTX_RESET 0
618 * Capabilities Announced
620 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
621 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
622 #define QLCNIC_CAP0_LSO (1 << 6)
623 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
624 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
625 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
630 #define QLCNIC_HOST_CTX_STATE_FREED 0
631 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
637 struct qlcnic_hostrq_sds_ring {
638 __le64 host_phys_addr; /* Ring base addr */
639 __le32 ring_size; /* Ring entries */
641 __le16 rsvd; /* Padding */
644 struct qlcnic_hostrq_rds_ring {
645 __le64 host_phys_addr; /* Ring base addr */
646 __le64 buff_size; /* Packet buffer size */
647 __le32 ring_size; /* Ring entries */
648 __le32 ring_kind; /* Class of ring */
651 struct qlcnic_hostrq_rx_ctx {
652 __le64 host_rsp_dma_addr; /* Response dma'd here */
653 __le32 capabilities[4]; /* Flag bit vector */
654 __le32 host_int_crb_mode; /* Interrupt crb usage */
655 __le32 host_rds_crb_mode; /* RDS crb usage */
656 /* These ring offsets are relative to data[0] below */
657 __le32 rds_ring_offset; /* Offset to RDS config */
658 __le32 sds_ring_offset; /* Offset to SDS config */
659 __le16 num_rds_rings; /* Count of RDS rings */
660 __le16 num_sds_rings; /* Count of SDS rings */
661 __le16 valid_field_offset;
664 u8 reserved[128]; /* reserve space for future expansion*/
665 /* MUST BE 64-bit aligned.
666 The following is packed:
668 - N hostrq_sds_rings */
672 struct qlcnic_cardrsp_rds_ring{
673 __le32 host_producer_crb; /* Crb to use */
674 __le32 rsvd1; /* Padding */
677 struct qlcnic_cardrsp_sds_ring {
678 __le32 host_consumer_crb; /* Crb to use */
679 __le32 interrupt_crb; /* Crb to use */
682 struct qlcnic_cardrsp_rx_ctx {
683 /* These ring offsets are relative to data[0] below */
684 __le32 rds_ring_offset; /* Offset to RDS config */
685 __le32 sds_ring_offset; /* Offset to SDS config */
686 __le32 host_ctx_state; /* Starting State */
687 __le32 num_fn_per_port; /* How many PCI fn share the port */
688 __le16 num_rds_rings; /* Count of RDS rings */
689 __le16 num_sds_rings; /* Count of SDS rings */
690 __le16 context_id; /* Handle for context */
691 u8 phys_port; /* Physical id of port */
692 u8 virt_port; /* Virtual/Logical id of port */
693 u8 reserved[128]; /* save space for future expansion */
694 /* MUST BE 64-bit aligned.
695 The following is packed:
696 - N cardrsp_rds_rings
697 - N cardrs_sds_rings */
701 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
702 (sizeof(HOSTRQ_RX) + \
703 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
704 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
706 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
707 (sizeof(CARDRSP_RX) + \
708 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
709 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
715 struct qlcnic_hostrq_cds_ring {
716 __le64 host_phys_addr; /* Ring base addr */
717 __le32 ring_size; /* Ring entries */
718 __le32 rsvd; /* Padding */
721 struct qlcnic_hostrq_tx_ctx {
722 __le64 host_rsp_dma_addr; /* Response dma'd here */
723 __le64 cmd_cons_dma_addr; /* */
724 __le64 dummy_dma_addr; /* */
725 __le32 capabilities[4]; /* Flag bit vector */
726 __le32 host_int_crb_mode; /* Interrupt crb usage */
727 __le32 rsvd1; /* Padding */
728 __le16 rsvd2; /* Padding */
729 __le16 interrupt_ctl;
731 __le16 rsvd3; /* Padding */
732 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
733 u8 reserved[128]; /* future expansion */
736 struct qlcnic_cardrsp_cds_ring {
737 __le32 host_producer_crb; /* Crb to use */
738 __le32 interrupt_crb; /* Crb to use */
741 struct qlcnic_cardrsp_tx_ctx {
742 __le32 host_ctx_state; /* Starting state */
743 __le16 context_id; /* Handle for context */
744 u8 phys_port; /* Physical id of port */
745 u8 virt_port; /* Virtual/Logical id of port */
746 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
747 u8 reserved[128]; /* future expansion */
750 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
751 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
755 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
756 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
757 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
758 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
760 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
761 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
762 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
763 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
764 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
769 #define MC_COUNT_P3P 38
771 #define QLCNIC_MAC_NOOP 0
772 #define QLCNIC_MAC_ADD 1
773 #define QLCNIC_MAC_DEL 2
774 #define QLCNIC_MAC_VLAN_ADD 3
775 #define QLCNIC_MAC_VLAN_DEL 4
777 struct qlcnic_mac_list_s {
778 struct list_head list;
779 uint8_t mac_addr[ETH_ALEN+2];
782 #define QLCNIC_HOST_REQUEST 0x13
783 #define QLCNIC_REQUEST 0x14
785 #define QLCNIC_MAC_EVENT 0x1
787 #define QLCNIC_IP_UP 2
788 #define QLCNIC_IP_DOWN 3
790 #define QLCNIC_ILB_MODE 0x1
791 #define QLCNIC_ELB_MODE 0x2
793 #define QLCNIC_LINKEVENT 0x1
794 #define QLCNIC_LB_RESPONSE 0x2
795 #define QLCNIC_IS_LB_CONFIGURED(VAL) \
796 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
799 * Driver --> Firmware
801 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
802 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
803 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
804 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
805 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
806 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
808 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
809 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
810 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
811 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13
814 * Firmware --> Driver
817 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f
818 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
820 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
821 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
822 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
824 #define QLCNIC_LRO_REQUEST_CLEANUP 4
826 /* Capabilites received */
827 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
828 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
829 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
830 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
831 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27
834 #define LINKEVENT_MODULE_NOT_PRESENT 1
835 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
836 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
837 #define LINKEVENT_MODULE_OPTICAL_LRM 4
838 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
839 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
840 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
841 #define LINKEVENT_MODULE_TWINAX 8
843 #define LINKSPEED_10GBPS 10000
844 #define LINKSPEED_1GBPS 1000
845 #define LINKSPEED_100MBPS 100
846 #define LINKSPEED_10MBPS 10
848 #define LINKSPEED_ENCODED_10MBPS 0
849 #define LINKSPEED_ENCODED_100MBPS 1
850 #define LINKSPEED_ENCODED_1GBPS 2
852 #define LINKEVENT_AUTONEG_DISABLED 0
853 #define LINKEVENT_AUTONEG_ENABLED 1
855 #define LINKEVENT_HALF_DUPLEX 0
856 #define LINKEVENT_FULL_DUPLEX 1
858 #define LINKEVENT_LINKSPEED_MBPS 0
859 #define LINKEVENT_LINKSPEED_ENCODED 1
861 /* firmware response header:
862 * 63:58 - message type
866 * 47:40 - completion id
871 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
872 ((msg_hdr >> 32) & 0xFF)
874 struct qlcnic_fw_msg {
884 struct qlcnic_nic_req {
890 struct qlcnic_mac_req {
896 struct qlcnic_vlan_req {
901 struct qlcnic_ipaddr {
906 #define QLCNIC_MSI_ENABLED 0x02
907 #define QLCNIC_MSIX_ENABLED 0x04
908 #define QLCNIC_LRO_ENABLED 0x08
909 #define QLCNIC_LRO_DISABLED 0x00
910 #define QLCNIC_BRIDGE_ENABLED 0X10
911 #define QLCNIC_DIAG_ENABLED 0x20
912 #define QLCNIC_ESWITCH_ENABLED 0x40
913 #define QLCNIC_ADAPTER_INITIALIZED 0x80
914 #define QLCNIC_TAGGING_ENABLED 0x100
915 #define QLCNIC_MACSPOOF 0x200
916 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
917 #define QLCNIC_PROMISC_DISABLED 0x800
918 #define QLCNIC_NEED_FLR 0x1000
919 #define QLCNIC_FW_RESET_OWNER 0x2000
920 #define QLCNIC_FW_HANG 0x4000
921 #define QLCNIC_IS_MSI_FAMILY(adapter) \
922 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
924 #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4
925 #define QLCNIC_MSIX_TBL_SPACE 8192
926 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
927 #define QLCNIC_MSIX_TBL_PGSIZE 4096
929 #define QLCNIC_NETDEV_WEIGHT 128
930 #define QLCNIC_ADAPTER_UP_MAGIC 777
932 #define __QLCNIC_FW_ATTACHED 0
933 #define __QLCNIC_DEV_UP 1
934 #define __QLCNIC_RESETTING 2
935 #define __QLCNIC_START_FW 4
936 #define __QLCNIC_AER 5
937 #define __QLCNIC_DIAG_RES_ALLOC 6
938 #define __QLCNIC_LED_ENABLE 7
940 #define QLCNIC_INTERRUPT_TEST 1
941 #define QLCNIC_LOOPBACK_TEST 2
942 #define QLCNIC_LED_TEST 3
944 #define QLCNIC_FILTER_AGE 80
945 #define QLCNIC_READD_AGE 20
946 #define QLCNIC_LB_MAX_FILTERS 64
948 /* QLCNIC Driver Error Code */
949 #define QLCNIC_FW_NOT_RESPOND 51
950 #define QLCNIC_TEST_IN_PROGRESS 52
951 #define QLCNIC_UNDEFINED_ERROR 53
952 #define QLCNIC_LB_CABLE_NOT_CONN 54
954 struct qlcnic_filter {
955 struct hlist_node fnode;
961 struct qlcnic_filter_hash {
962 struct hlist_head *fhead;
967 struct qlcnic_adapter {
968 struct qlcnic_hardware_context *ahw;
969 struct qlcnic_recv_context *recv_ctx;
970 struct qlcnic_host_tx_ring *tx_ring;
971 struct net_device *netdev;
972 struct pci_dev *pdev;
1030 u8 mac_addr[ETH_ALEN];
1034 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
1036 struct qlcnic_npar_info *npars;
1037 struct qlcnic_eswitch *eswitch;
1038 struct qlcnic_nic_template *nic_ops;
1040 struct qlcnic_adapter_stats stats;
1041 struct list_head mac_list;
1043 void __iomem *tgt_mask_reg;
1044 void __iomem *tgt_status_reg;
1045 void __iomem *crb_int_state_reg;
1046 void __iomem *isr_int_vec;
1048 struct msix_entry *msix_entries;
1050 struct delayed_work fw_work;
1053 struct qlcnic_filter_hash fhash;
1055 spinlock_t tx_clean_lock;
1056 spinlock_t mac_learn_lock;
1057 __le32 file_prd_off; /*File fw product offset*/
1059 const struct firmware *fw;
1062 struct qlcnic_info {
1064 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1066 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1068 __le32 capabilities;
1080 struct qlcnic_pci_info {
1081 __le16 id; /* pci function id */
1082 __le16 active; /* 1 = Enabled */
1083 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1084 __le16 default_port; /* default port number */
1086 __le16 tx_min_bw; /* Multiple of 100mbpc */
1088 __le16 reserved1[2];
1094 struct qlcnic_npar_info {
1110 struct qlcnic_eswitch {
1114 u8 active_ucast_filters;
1115 u8 max_ucast_filters;
1116 u8 max_active_vlans;
1119 #define QLCNIC_SWITCH_ENABLE BIT_1
1120 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1121 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1122 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1126 /* Return codes for Error handling */
1127 #define QL_STATUS_INVALID_PARAM -1
1129 #define MAX_BW 100 /* % of link speed */
1130 #define MAX_VLAN_ID 4095
1131 #define MIN_VLAN_ID 2
1132 #define DEFAULT_MAC_LEARN 1
1134 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1135 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1137 struct qlcnic_pci_func_cfg {
1147 struct qlcnic_npar_func_cfg {
1158 struct qlcnic_pm_func_cfg {
1165 struct qlcnic_esw_func_cfg {
1179 #define QLCNIC_STATS_VERSION 1
1180 #define QLCNIC_STATS_PORT 1
1181 #define QLCNIC_STATS_ESWITCH 2
1182 #define QLCNIC_QUERY_RX_COUNTER 0
1183 #define QLCNIC_QUERY_TX_COUNTER 1
1184 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL
1185 #define QLCNIC_FILL_STATS(VAL1) \
1186 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1)
1187 #define QLCNIC_MAC_STATS 1
1188 #define QLCNIC_ESW_STATS 2
1190 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1192 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \
1193 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1195 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \
1196 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1200 struct qlcnic_mac_statistics{
1201 __le64 mac_tx_frames;
1202 __le64 mac_tx_bytes;
1203 __le64 mac_tx_mcast_pkts;
1204 __le64 mac_tx_bcast_pkts;
1205 __le64 mac_tx_pause_cnt;
1206 __le64 mac_tx_ctrl_pkt;
1207 __le64 mac_tx_lt_64b_pkts;
1208 __le64 mac_tx_lt_127b_pkts;
1209 __le64 mac_tx_lt_255b_pkts;
1210 __le64 mac_tx_lt_511b_pkts;
1211 __le64 mac_tx_lt_1023b_pkts;
1212 __le64 mac_tx_lt_1518b_pkts;
1213 __le64 mac_tx_gt_1518b_pkts;
1216 __le64 mac_rx_frames;
1217 __le64 mac_rx_bytes;
1218 __le64 mac_rx_mcast_pkts;
1219 __le64 mac_rx_bcast_pkts;
1220 __le64 mac_rx_pause_cnt;
1221 __le64 mac_rx_ctrl_pkt;
1222 __le64 mac_rx_lt_64b_pkts;
1223 __le64 mac_rx_lt_127b_pkts;
1224 __le64 mac_rx_lt_255b_pkts;
1225 __le64 mac_rx_lt_511b_pkts;
1226 __le64 mac_rx_lt_1023b_pkts;
1227 __le64 mac_rx_lt_1518b_pkts;
1228 __le64 mac_rx_gt_1518b_pkts;
1231 __le64 mac_rx_length_error;
1232 __le64 mac_rx_length_small;
1233 __le64 mac_rx_length_large;
1234 __le64 mac_rx_jabber;
1235 __le64 mac_rx_dropped;
1236 __le64 mac_rx_crc_error;
1237 __le64 mac_align_error;
1240 struct __qlcnic_esw_statistics {
1245 __le64 unicast_frames;
1246 __le64 multicast_frames;
1247 __le64 broadcast_frames;
1248 __le64 dropped_frames;
1250 __le64 local_frames;
1255 struct qlcnic_esw_statistics {
1256 struct __qlcnic_esw_statistics rx;
1257 struct __qlcnic_esw_statistics tx;
1260 struct qlcnic_common_entry_hdr {
1297 __le16 init_tag_val;
1303 u8 read_addr_stride;
1314 __le32 read_addr_stride;
1342 u8 read_addr_stride;
1347 struct qlcnic_dump_entry {
1348 struct qlcnic_common_entry_hdr hdr;
1351 struct __cache cache;
1361 QLCNIC_DUMP_NOP = 0,
1362 QLCNIC_DUMP_READ_CRB = 1,
1363 QLCNIC_DUMP_READ_MUX = 2,
1364 QLCNIC_DUMP_QUEUE = 3,
1365 QLCNIC_DUMP_BRD_CONFIG = 4,
1366 QLCNIC_DUMP_READ_OCM = 6,
1367 QLCNIC_DUMP_PEG_REG = 7,
1368 QLCNIC_DUMP_L1_DTAG = 8,
1369 QLCNIC_DUMP_L1_ITAG = 9,
1370 QLCNIC_DUMP_L1_DATA = 11,
1371 QLCNIC_DUMP_L1_INST = 12,
1372 QLCNIC_DUMP_L2_DTAG = 21,
1373 QLCNIC_DUMP_L2_ITAG = 22,
1374 QLCNIC_DUMP_L2_DATA = 23,
1375 QLCNIC_DUMP_L2_INST = 24,
1376 QLCNIC_DUMP_READ_ROM = 71,
1377 QLCNIC_DUMP_READ_MEM = 72,
1378 QLCNIC_DUMP_READ_CTRL = 98,
1379 QLCNIC_DUMP_TLHDR = 99,
1380 QLCNIC_DUMP_RDEND = 255
1383 #define QLCNIC_DUMP_WCRB BIT_0
1384 #define QLCNIC_DUMP_RWCRB BIT_1
1385 #define QLCNIC_DUMP_ANDCRB BIT_2
1386 #define QLCNIC_DUMP_ORCRB BIT_3
1387 #define QLCNIC_DUMP_POLLCRB BIT_4
1388 #define QLCNIC_DUMP_RD_SAVE BIT_5
1389 #define QLCNIC_DUMP_WRT_SAVED BIT_6
1390 #define QLCNIC_DUMP_MOD_SAVE_ST BIT_7
1391 #define QLCNIC_DUMP_SKIP BIT_7
1393 #define QLCNIC_DUMP_MASK_MIN 3
1394 #define QLCNIC_DUMP_MASK_DEF 0x1f
1395 #define QLCNIC_DUMP_MASK_MAX 0xff
1396 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1397 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1398 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
1399 #define QLCNIC_FORCE_FW_RESET 0xdeaddead
1400 #define QLCNIC_SET_QUIESCENT 0xadd00010
1401 #define QLCNIC_RESET_QUIESCENT 0xadd00020
1403 struct qlcnic_dump_operations {
1404 enum op_codes opcode;
1405 u32 (*handler)(struct qlcnic_adapter *,
1406 struct qlcnic_dump_entry *, u32 *);
1416 struct qlcnic_cmd_args {
1417 struct _cdrp_cmd req;
1418 struct _cdrp_cmd rsp;
1421 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
1422 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
1424 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1425 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1426 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1427 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1428 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1429 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1431 #define ADDR_IN_RANGE(addr, low, high) \
1432 (((addr) < (high)) && ((addr) >= (low)))
1434 #define QLCRD32(adapter, off) \
1435 (qlcnic_hw_read_wx_2M(adapter, off))
1436 #define QLCWR32(adapter, off, val) \
1437 (qlcnic_hw_write_wx_2M(adapter, off, val))
1439 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1440 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1442 #define qlcnic_rom_lock(a) \
1443 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1444 #define qlcnic_rom_unlock(a) \
1445 qlcnic_pcie_sem_unlock((a), 2)
1446 #define qlcnic_phy_lock(a) \
1447 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1448 #define qlcnic_phy_unlock(a) \
1449 qlcnic_pcie_sem_unlock((a), 3)
1450 #define qlcnic_api_lock(a) \
1451 qlcnic_pcie_sem_lock((a), 5, 0)
1452 #define qlcnic_api_unlock(a) \
1453 qlcnic_pcie_sem_unlock((a), 5)
1454 #define qlcnic_sw_lock(a) \
1455 qlcnic_pcie_sem_lock((a), 6, 0)
1456 #define qlcnic_sw_unlock(a) \
1457 qlcnic_pcie_sem_unlock((a), 6)
1458 #define crb_win_lock(a) \
1459 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1460 #define crb_win_unlock(a) \
1461 qlcnic_pcie_sem_unlock((a), 7)
1463 #define __QLCNIC_MAX_LED_RATE 0xf
1464 #define __QLCNIC_MAX_LED_STATE 0x2
1466 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1467 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1468 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1469 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1470 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1471 int qlcnic_dump_fw(struct qlcnic_adapter *);
1473 /* Functions from qlcnic_init.c */
1474 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1475 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1476 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1477 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1478 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1479 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1480 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1482 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
1483 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1484 u8 *bytes, size_t size);
1485 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1486 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1488 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1490 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1491 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1493 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1494 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1496 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1497 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1498 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1500 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1501 void qlcnic_watchdog_task(struct work_struct *work);
1502 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1503 struct qlcnic_host_rds_ring *rds_ring);
1504 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1505 void qlcnic_set_multi(struct net_device *netdev);
1506 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1507 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1508 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1509 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1510 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd);
1511 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1512 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1514 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1515 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1516 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1517 netdev_features_t features);
1518 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features);
1519 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1520 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1521 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1522 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1523 struct qlcnic_host_tx_ring *tx_ring);
1524 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1525 void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
1526 void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter);
1527 int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode);
1529 /* Functions from qlcnic_ethtool.c */
1530 int qlcnic_check_loopback_buff(unsigned char *data, u8 mac[]);
1532 /* Functions from qlcnic_main.c */
1533 int qlcnic_reset_context(struct qlcnic_adapter *);
1534 void qlcnic_issue_cmd(struct qlcnic_adapter *adapter, struct qlcnic_cmd_args *);
1535 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1536 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1537 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1538 int qlcnic_validate_max_rss(struct net_device *netdev, u8 max_hw, u8 val);
1539 int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data);
1540 void qlcnic_dev_request_reset(struct qlcnic_adapter *);
1541 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter);
1543 /* Management functions */
1544 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1545 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1546 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1547 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1549 /* eSwitch management functions */
1550 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1551 struct qlcnic_esw_func_cfg *);
1552 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1553 struct qlcnic_esw_func_cfg *);
1554 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1555 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1556 struct __qlcnic_esw_statistics *);
1557 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1558 struct __qlcnic_esw_statistics *);
1559 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1560 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *);
1561 extern int qlcnic_config_tso;
1564 * QLOGIC Board information
1567 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1568 struct qlcnic_brdinfo {
1569 unsigned short vendor;
1570 unsigned short device;
1571 unsigned short sub_vendor;
1572 unsigned short sub_device;
1573 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1576 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1577 {0x1077, 0x8020, 0x1077, 0x203,
1578 "8200 Series Single Port 10GbE Converged Network Adapter "
1579 "(TCP/IP Networking)"},
1580 {0x1077, 0x8020, 0x1077, 0x207,
1581 "8200 Series Dual Port 10GbE Converged Network Adapter "
1582 "(TCP/IP Networking)"},
1583 {0x1077, 0x8020, 0x1077, 0x20b,
1584 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1585 {0x1077, 0x8020, 0x1077, 0x20c,
1586 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1587 {0x1077, 0x8020, 0x1077, 0x20f,
1588 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1589 {0x1077, 0x8020, 0x103c, 0x3733,
1590 "NC523SFP 10Gb 2-port Server Adapter"},
1591 {0x1077, 0x8020, 0x103c, 0x3346,
1592 "CN1000Q Dual Port Converged Network Adapter"},
1593 {0x1077, 0x8020, 0x1077, 0x210,
1594 "QME8242-k 10GbE Dual Port Mezzanine Card"},
1595 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1598 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1600 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1602 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1603 return tx_ring->sw_consumer - tx_ring->producer;
1605 return tx_ring->sw_consumer + tx_ring->num_desc -
1609 extern const struct ethtool_ops qlcnic_ethtool_ops;
1610 extern const struct ethtool_ops qlcnic_ethtool_failed_ops;
1612 struct qlcnic_nic_template {
1613 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1614 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1615 int (*start_firmware) (struct qlcnic_adapter *);
1618 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1619 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1620 printk(KERN_INFO "%s: %s: " _fmt, \
1621 dev_name(&adapter->pdev->dev), \
1622 __func__, ##_args); \
1625 #endif /* __QLCNIC_H_ */