Pileus Git - ~andy/linux/blob - drivers/net/ethernet/nvidia/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42
  43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  44
  45 #define FORCEDETH_VERSION               "0.64"
  46 #define DRV_NAME                        "forcedeth"
  47
  48 #include <linux/module.h>
  49 #include <linux/types.h>
  50 #include <linux/pci.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/etherdevice.h>
  54 #include <linux/delay.h>
  55 #include <linux/sched.h>
  56 #include <linux/spinlock.h>
  57 #include <linux/ethtool.h>
  58 #include <linux/timer.h>
  59 #include <linux/skbuff.h>
  60 #include <linux/mii.h>
  61 #include <linux/random.h>
  62 #include <linux/init.h>
  63 #include <linux/if_vlan.h>
  64 #include <linux/dma-mapping.h>
  65 #include <linux/slab.h>
  66 #include <linux/uaccess.h>
  67 #include <linux/prefetch.h>
  68 #include <linux/u64_stats_sync.h>
  69 #include <linux/io.h>
  70
  71 #include <asm/irq.h>
  72 #include <asm/system.h>
  73
  74 #define TX_WORK_PER_LOOP  64
  75 #define RX_WORK_PER_LOOP  64
  76
  77 /*
  78  * Hardware access:
  79  */
  80
  81 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
  82 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
  83 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
  84 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
  85 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
  86 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
  87 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
  88 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
  89 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
  90 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
  91 #define DEV_HAS_STATISTICS_V2      0x0000400  /* device supports hw statistics version 2 */
  92 #define DEV_HAS_STATISTICS_V3      0x0000800  /* device supports hw statistics version 3 */
  93 #define DEV_HAS_STATISTICS_V12     0x0000600  /* device supports hw statistics version 1 and 2 */
  94 #define DEV_HAS_STATISTICS_V123    0x0000e00  /* device supports hw statistics version 1, 2, and 3 */
  95 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
  96 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
  97 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
  98 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
  99 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
 100 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
 101 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
 102 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
 103 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
 104 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
 105 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
 106 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
 107 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
 108
 109 enum {
 110         NvRegIrqStatus = 0x000,
 111 #define NVREG_IRQSTAT_MIIEVENT  0x040
 112 #define NVREG_IRQSTAT_MASK              0x83ff
 113         NvRegIrqMask = 0x004,
 114 #define NVREG_IRQ_RX_ERROR              0x0001
 115 #define NVREG_IRQ_RX                    0x0002
 116 #define NVREG_IRQ_RX_NOBUF              0x0004
 117 #define NVREG_IRQ_TX_ERR                0x0008
 118 #define NVREG_IRQ_TX_OK                 0x0010
 119 #define NVREG_IRQ_TIMER                 0x0020
 120 #define NVREG_IRQ_LINK                  0x0040
 121 #define NVREG_IRQ_RX_FORCED             0x0080
 122 #define NVREG_IRQ_TX_FORCED             0x0100
 123 #define NVREG_IRQ_RECOVER_ERROR         0x8200
 124 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 125 #define NVREG_IRQMASK_CPU               0x0060
 126 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 127 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 128 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 129
 130         NvRegUnknownSetupReg6 = 0x008,
 131 #define NVREG_UNKSETUP6_VAL             3
 132
 133 /*
 134  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 135  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 136  */
 137         NvRegPollingInterval = 0x00c,
 138 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
 139 #define NVREG_POLL_DEFAULT_CPU  13
 140         NvRegMSIMap0 = 0x020,
 141         NvRegMSIMap1 = 0x024,
 142         NvRegMSIIrqMask = 0x030,
 143 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 144         NvRegMisc1 = 0x080,
 145 #define NVREG_MISC1_PAUSE_TX    0x01
 146 #define NVREG_MISC1_HD          0x02
 147 #define NVREG_MISC1_FORCE       0x3b0f3c
 148
 149         NvRegMacReset = 0x34,
 150 #define NVREG_MAC_RESET_ASSERT  0x0F3
 151         NvRegTransmitterControl = 0x084,
 152 #define NVREG_XMITCTL_START     0x01
 153 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 154 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 155 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 156 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 157 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 158 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 159 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 160 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 161 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 162 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 163 #define NVREG_XMITCTL_DATA_START        0x00100000
 164 #define NVREG_XMITCTL_DATA_READY        0x00010000
 165 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
 166         NvRegTransmitterStatus = 0x088,
 167 #define NVREG_XMITSTAT_BUSY     0x01
 168
 169         NvRegPacketFilterFlags = 0x8c,
 170 #define NVREG_PFF_PAUSE_RX      0x08
 171 #define NVREG_PFF_ALWAYS        0x7F0000
 172 #define NVREG_PFF_PROMISC       0x80
 173 #define NVREG_PFF_MYADDR        0x20
 174 #define NVREG_PFF_LOOPBACK      0x10
 175
 176         NvRegOffloadConfig = 0x90,
 177 #define NVREG_OFFLOAD_HOMEPHY   0x601
 178 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 179         NvRegReceiverControl = 0x094,
 180 #define NVREG_RCVCTL_START      0x01
 181 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 182         NvRegReceiverStatus = 0x98,
 183 #define NVREG_RCVSTAT_BUSY      0x01
 184
 185         NvRegSlotTime = 0x9c,
 186 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 187 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 188 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 189 #define NVREG_SLOTTIME_HALF             0x0000ff00
 190 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 191 #define NVREG_SLOTTIME_MASK             0x000000ff
 192
 193         NvRegTxDeferral = 0xA0,
 194 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 195 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 196 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 198 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 199 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 200         NvRegRxDeferral = 0xA4,
 201 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 202         NvRegMacAddrA = 0xA8,
 203         NvRegMacAddrB = 0xAC,
 204         NvRegMulticastAddrA = 0xB0,
 205 #define NVREG_MCASTADDRA_FORCE  0x01
 206         NvRegMulticastAddrB = 0xB4,
 207         NvRegMulticastMaskA = 0xB8,
 208 #define NVREG_MCASTMASKA_NONE           0xffffffff
 209         NvRegMulticastMaskB = 0xBC,
 210 #define NVREG_MCASTMASKB_NONE           0xffff
 211
 212         NvRegPhyInterface = 0xC0,
 213 #define PHY_RGMII               0x10000000
 214         NvRegBackOffControl = 0xC4,
 215 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 216 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 217 #define NVREG_BKOFFCTRL_SELECT                  24
 218 #define NVREG_BKOFFCTRL_GEAR                    12
 219
 220         NvRegTxRingPhysAddr = 0x100,
 221         NvRegRxRingPhysAddr = 0x104,
 222         NvRegRingSizes = 0x108,
 223 #define NVREG_RINGSZ_TXSHIFT 0
 224 #define NVREG_RINGSZ_RXSHIFT 16
 225         NvRegTransmitPoll = 0x10c,
 226 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 227         NvRegLinkSpeed = 0x110,
 228 #define NVREG_LINKSPEED_FORCE 0x10000
 229 #define NVREG_LINKSPEED_10      1000
 230 #define NVREG_LINKSPEED_100     100
 231 #define NVREG_LINKSPEED_1000    50
 232 #define NVREG_LINKSPEED_MASK    (0xFFF)
 233         NvRegUnknownSetupReg5 = 0x130,
 234 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 235         NvRegTxWatermark = 0x13c,
 236 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 237 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 238 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 239         NvRegTxRxControl = 0x144,
 240 #define NVREG_TXRXCTL_KICK      0x0001
 241 #define NVREG_TXRXCTL_BIT1      0x0002
 242 #define NVREG_TXRXCTL_BIT2      0x0004
 243 #define NVREG_TXRXCTL_IDLE      0x0008
 244 #define NVREG_TXRXCTL_RESET     0x0010
 245 #define NVREG_TXRXCTL_RXCHECK   0x0400
 246 #define NVREG_TXRXCTL_DESC_1    0
 247 #define NVREG_TXRXCTL_DESC_2    0x002100
 248 #define NVREG_TXRXCTL_DESC_3    0xc02200
 249 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 250 #define NVREG_TXRXCTL_VLANINS   0x00080
 251         NvRegTxRingPhysAddrHigh = 0x148,
 252         NvRegRxRingPhysAddrHigh = 0x14C,
 253         NvRegTxPauseFrame = 0x170,
 254 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 255 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 256 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 257 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 258         NvRegTxPauseFrameLimit = 0x174,
 259 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 260         NvRegMIIStatus = 0x180,
 261 #define NVREG_MIISTAT_ERROR             0x0001
 262 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 263 #define NVREG_MIISTAT_MASK_RW           0x0007
 264 #define NVREG_MIISTAT_MASK_ALL          0x000f
 265         NvRegMIIMask = 0x184,
 266 #define NVREG_MII_LINKCHANGE            0x0008
 267
 268         NvRegAdapterControl = 0x188,
 269 #define NVREG_ADAPTCTL_START    0x02
 270 #define NVREG_ADAPTCTL_LINKUP   0x04
 271 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 272 #define NVREG_ADAPTCTL_RUNNING  0x100000
 273 #define NVREG_ADAPTCTL_PHYSHIFT 24
 274         NvRegMIISpeed = 0x18c,
 275 #define NVREG_MIISPEED_BIT8     (1<<8)
 276 #define NVREG_MIIDELAY  5
 277         NvRegMIIControl = 0x190,
 278 #define NVREG_MIICTL_INUSE      0x08000
 279 #define NVREG_MIICTL_WRITE      0x00400
 280 #define NVREG_MIICTL_ADDRSHIFT  5
 281         NvRegMIIData = 0x194,
 282         NvRegTxUnicast = 0x1a0,
 283         NvRegTxMulticast = 0x1a4,
 284         NvRegTxBroadcast = 0x1a8,
 285         NvRegWakeUpFlags = 0x200,
 286 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 287 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 288 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 289 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 290 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 291 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 292 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 293 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 294 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 295 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 296 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 297
 298         NvRegMgmtUnitGetVersion = 0x204,
 299 #define NVREG_MGMTUNITGETVERSION        0x01
 300         NvRegMgmtUnitVersion = 0x208,
 301 #define NVREG_MGMTUNITVERSION           0x08
 302         NvRegPowerCap = 0x268,
 303 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 304 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 305 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 306         NvRegPowerState = 0x26c,
 307 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 308 #define NVREG_POWERSTATE_VALID          0x0100
 309 #define NVREG_POWERSTATE_MASK           0x0003
 310 #define NVREG_POWERSTATE_D0             0x0000
 311 #define NVREG_POWERSTATE_D1             0x0001
 312 #define NVREG_POWERSTATE_D2             0x0002
 313 #define NVREG_POWERSTATE_D3             0x0003
 314         NvRegMgmtUnitControl = 0x278,
 315 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
 316         NvRegTxCnt = 0x280,
 317         NvRegTxZeroReXmt = 0x284,
 318         NvRegTxOneReXmt = 0x288,
 319         NvRegTxManyReXmt = 0x28c,
 320         NvRegTxLateCol = 0x290,
 321         NvRegTxUnderflow = 0x294,
 322         NvRegTxLossCarrier = 0x298,
 323         NvRegTxExcessDef = 0x29c,
 324         NvRegTxRetryErr = 0x2a0,
 325         NvRegRxFrameErr = 0x2a4,
 326         NvRegRxExtraByte = 0x2a8,
 327         NvRegRxLateCol = 0x2ac,
 328         NvRegRxRunt = 0x2b0,
 329         NvRegRxFrameTooLong = 0x2b4,
 330         NvRegRxOverflow = 0x2b8,
 331         NvRegRxFCSErr = 0x2bc,
 332         NvRegRxFrameAlignErr = 0x2c0,
 333         NvRegRxLenErr = 0x2c4,
 334         NvRegRxUnicast = 0x2c8,
 335         NvRegRxMulticast = 0x2cc,
 336         NvRegRxBroadcast = 0x2d0,
 337         NvRegTxDef = 0x2d4,
 338         NvRegTxFrame = 0x2d8,
 339         NvRegRxCnt = 0x2dc,
 340         NvRegTxPause = 0x2e0,
 341         NvRegRxPause = 0x2e4,
 342         NvRegRxDropFrame = 0x2e8,
 343         NvRegVlanControl = 0x300,
 344 #define NVREG_VLANCONTROL_ENABLE        0x2000
 345         NvRegMSIXMap0 = 0x3e0,
 346         NvRegMSIXMap1 = 0x3e4,
 347         NvRegMSIXIrqStatus = 0x3f0,
 348
 349         NvRegPowerState2 = 0x600,
 350 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 351 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 352 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 353 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
 354 };
 355
 356 /* Big endian: should work, but is untested */
 357 struct ring_desc {
 358         __le32 buf;
 359         __le32 flaglen;
 360 };
 361
 362 struct ring_desc_ex {
 363         __le32 bufhigh;
 364         __le32 buflow;
 365         __le32 txvlan;
 366         __le32 flaglen;
 367 };
 368
 369 union ring_type {
 370         struct ring_desc *orig;
 371         struct ring_desc_ex *ex;
 372 };
 373
 374 #define FLAG_MASK_V1 0xffff0000
 375 #define FLAG_MASK_V2 0xffffc000
 376 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 377 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 378
 379 #define NV_TX_LASTPACKET        (1<<16)
 380 #define NV_TX_RETRYERROR        (1<<19)
 381 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 382 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 383 #define NV_TX_DEFERRED          (1<<26)
 384 #define NV_TX_CARRIERLOST       (1<<27)
 385 #define NV_TX_LATECOLLISION     (1<<28)
 386 #define NV_TX_UNDERFLOW         (1<<29)
 387 #define NV_TX_ERROR             (1<<30)
 388 #define NV_TX_VALID             (1<<31)
 389
 390 #define NV_TX2_LASTPACKET       (1<<29)
 391 #define NV_TX2_RETRYERROR       (1<<18)
 392 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 393 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 394 #define NV_TX2_DEFERRED         (1<<25)
 395 #define NV_TX2_CARRIERLOST      (1<<26)
 396 #define NV_TX2_LATECOLLISION    (1<<27)
 397 #define NV_TX2_UNDERFLOW        (1<<28)
 398 /* error and valid are the same for both */
 399 #define NV_TX2_ERROR            (1<<30)
 400 #define NV_TX2_VALID            (1<<31)
 401 #define NV_TX2_TSO              (1<<28)
 402 #define NV_TX2_TSO_SHIFT        14
 403 #define NV_TX2_TSO_MAX_SHIFT    14
 404 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 405 #define NV_TX2_CHECKSUM_L3      (1<<27)
 406 #define NV_TX2_CHECKSUM_L4      (1<<26)
 407
 408 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 409
 410 #define NV_RX_DESCRIPTORVALID   (1<<16)
 411 #define NV_RX_MISSEDFRAME       (1<<17)
 412 #define NV_RX_SUBSTRACT1        (1<<18)
 413 #define NV_RX_ERROR1            (1<<23)
 414 #define NV_RX_ERROR2            (1<<24)
 415 #define NV_RX_ERROR3            (1<<25)
 416 #define NV_RX_ERROR4            (1<<26)
 417 #define NV_RX_CRCERR            (1<<27)
 418 #define NV_RX_OVERFLOW          (1<<28)
 419 #define NV_RX_FRAMINGERR        (1<<29)
 420 #define NV_RX_ERROR             (1<<30)
 421 #define NV_RX_AVAIL             (1<<31)
 422 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 423
 424 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 425 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 426 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 427 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 428 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 429 #define NV_RX2_SUBSTRACT1       (1<<25)
 430 #define NV_RX2_ERROR1           (1<<18)
 431 #define NV_RX2_ERROR2           (1<<19)
 432 #define NV_RX2_ERROR3           (1<<20)
 433 #define NV_RX2_ERROR4           (1<<21)
 434 #define NV_RX2_CRCERR           (1<<22)
 435 #define NV_RX2_OVERFLOW         (1<<23)
 436 #define NV_RX2_FRAMINGERR       (1<<24)
 437 /* error and avail are the same for both */
 438 #define NV_RX2_ERROR            (1<<30)
 439 #define NV_RX2_AVAIL            (1<<31)
 440 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 441
 442 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 443 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 444
 445 /* Miscellaneous hardware related defines: */
 446 #define NV_PCI_REGSZ_VER1       0x270
 447 #define NV_PCI_REGSZ_VER2       0x2d4
 448 #define NV_PCI_REGSZ_VER3       0x604
 449 #define NV_PCI_REGSZ_MAX        0x604
 450
 451 /* various timeout delays: all in usec */
 452 #define NV_TXRX_RESET_DELAY     4
 453 #define NV_TXSTOP_DELAY1        10
 454 #define NV_TXSTOP_DELAY1MAX     500000
 455 #define NV_TXSTOP_DELAY2        100
 456 #define NV_RXSTOP_DELAY1        10
 457 #define NV_RXSTOP_DELAY1MAX     500000
 458 #define NV_RXSTOP_DELAY2        100
 459 #define NV_SETUP5_DELAY         5
 460 #define NV_SETUP5_DELAYMAX      50000
 461 #define NV_POWERUP_DELAY        5
 462 #define NV_POWERUP_DELAYMAX     5000
 463 #define NV_MIIBUSY_DELAY        50
 464 #define NV_MIIPHY_DELAY 10
 465 #define NV_MIIPHY_DELAYMAX      10000
 466 #define NV_MAC_RESET_DELAY      64
 467
 468 #define NV_WAKEUPPATTERNS       5
 469 #define NV_WAKEUPMASKENTRIES    4
 470
 471 /* General driver defaults */
 472 #define NV_WATCHDOG_TIMEO       (5*HZ)
 473
 474 #define RX_RING_DEFAULT         512
 475 #define TX_RING_DEFAULT         256
 476 #define RX_RING_MIN             128
 477 #define TX_RING_MIN             64
 478 #define RING_MAX_DESC_VER_1     1024
 479 #define RING_MAX_DESC_VER_2_3   16384
 480
 481 /* rx/tx mac addr + type + vlan + align + slack*/
 482 #define NV_RX_HEADERS           (64)
 483 /* even more slack. */
 484 #define NV_RX_ALLOC_PAD         (64)
 485
 486 /* maximum mtu size */
 487 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 488 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 489
 490 #define OOM_REFILL      (1+HZ/20)
 491 #define POLL_WAIT       (1+HZ/100)
 492 #define LINK_TIMEOUT    (3*HZ)
 493 #define STATS_INTERVAL  (10*HZ)
 494
 495 /*
 496  * desc_ver values:
 497  * The nic supports three different descriptor types:
 498  * - DESC_VER_1: Original
 499  * - DESC_VER_2: support for jumbo frames.
 500  * - DESC_VER_3: 64-bit format.
 501  */
 502 #define DESC_VER_1      1
 503 #define DESC_VER_2      2
 504 #define DESC_VER_3      3
 505
 506 /* PHY defines */
 507 #define PHY_OUI_MARVELL         0x5043
 508 #define PHY_OUI_CICADA          0x03f1
 509 #define PHY_OUI_VITESSE         0x01c1
 510 #define PHY_OUI_REALTEK         0x0732
 511 #define PHY_OUI_REALTEK2        0x0020
 512 #define PHYID1_OUI_MASK 0x03ff
 513 #define PHYID1_OUI_SHFT 6
 514 #define PHYID2_OUI_MASK 0xfc00
 515 #define PHYID2_OUI_SHFT 10
 516 #define PHYID2_MODEL_MASK               0x03f0
 517 #define PHY_MODEL_REALTEK_8211          0x0110
 518 #define PHY_REV_MASK                    0x0001
 519 #define PHY_REV_REALTEK_8211B           0x0000
 520 #define PHY_REV_REALTEK_8211C           0x0001
 521 #define PHY_MODEL_REALTEK_8201          0x0200
 522 #define PHY_MODEL_MARVELL_E3016         0x0220
 523 #define PHY_MARVELL_E3016_INITMASK      0x0300
 524 #define PHY_CICADA_INIT1        0x0f000
 525 #define PHY_CICADA_INIT2        0x0e00
 526 #define PHY_CICADA_INIT3        0x01000
 527 #define PHY_CICADA_INIT4        0x0200
 528 #define PHY_CICADA_INIT5        0x0004
 529 #define PHY_CICADA_INIT6        0x02000
 530 #define PHY_VITESSE_INIT_REG1   0x1f
 531 #define PHY_VITESSE_INIT_REG2   0x10
 532 #define PHY_VITESSE_INIT_REG3   0x11
 533 #define PHY_VITESSE_INIT_REG4   0x12
 534 #define PHY_VITESSE_INIT_MSK1   0xc
 535 #define PHY_VITESSE_INIT_MSK2   0x0180
 536 #define PHY_VITESSE_INIT1       0x52b5
 537 #define PHY_VITESSE_INIT2       0xaf8a
 538 #define PHY_VITESSE_INIT3       0x8
 539 #define PHY_VITESSE_INIT4       0x8f8a
 540 #define PHY_VITESSE_INIT5       0xaf86
 541 #define PHY_VITESSE_INIT6       0x8f86
 542 #define PHY_VITESSE_INIT7       0xaf82
 543 #define PHY_VITESSE_INIT8       0x0100
 544 #define PHY_VITESSE_INIT9       0x8f82
 545 #define PHY_VITESSE_INIT10      0x0
 546 #define PHY_REALTEK_INIT_REG1   0x1f
 547 #define PHY_REALTEK_INIT_REG2   0x19
 548 #define PHY_REALTEK_INIT_REG3   0x13
 549 #define PHY_REALTEK_INIT_REG4   0x14
 550 #define PHY_REALTEK_INIT_REG5   0x18
 551 #define PHY_REALTEK_INIT_REG6   0x11
 552 #define PHY_REALTEK_INIT_REG7   0x01
 553 #define PHY_REALTEK_INIT1       0x0000
 554 #define PHY_REALTEK_INIT2       0x8e00
 555 #define PHY_REALTEK_INIT3       0x0001
 556 #define PHY_REALTEK_INIT4       0xad17
 557 #define PHY_REALTEK_INIT5       0xfb54
 558 #define PHY_REALTEK_INIT6       0xf5c7
 559 #define PHY_REALTEK_INIT7       0x1000
 560 #define PHY_REALTEK_INIT8       0x0003
 561 #define PHY_REALTEK_INIT9       0x0008
 562 #define PHY_REALTEK_INIT10      0x0005
 563 #define PHY_REALTEK_INIT11      0x0200
 564 #define PHY_REALTEK_INIT_MSK1   0x0003
 565
 566 #define PHY_GIGABIT     0x0100
 567
 568 #define PHY_TIMEOUT     0x1
 569 #define PHY_ERROR       0x2
 570
 571 #define PHY_100 0x1
 572 #define PHY_1000        0x2
 573 #define PHY_HALF        0x100
 574
 575 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 576 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 577 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 578 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 579 #define NV_PAUSEFRAME_RX_REQ     0x0010
 580 #define NV_PAUSEFRAME_TX_REQ     0x0020
 581 #define NV_PAUSEFRAME_AUTONEG    0x0040
 582
 583 /* MSI/MSI-X defines */
 584 #define NV_MSI_X_MAX_VECTORS  8
 585 #define NV_MSI_X_VECTORS_MASK 0x000f
 586 #define NV_MSI_CAPABLE        0x0010
 587 #define NV_MSI_X_CAPABLE      0x0020
 588 #define NV_MSI_ENABLED        0x0040
 589 #define NV_MSI_X_ENABLED      0x0080
 590
 591 #define NV_MSI_X_VECTOR_ALL   0x0
 592 #define NV_MSI_X_VECTOR_RX    0x0
 593 #define NV_MSI_X_VECTOR_TX    0x1
 594 #define NV_MSI_X_VECTOR_OTHER 0x2
 595
 596 #define NV_MSI_PRIV_OFFSET 0x68
 597 #define NV_MSI_PRIV_VALUE  0xffffffff
 598
 599 #define NV_RESTART_TX         0x1
 600 #define NV_RESTART_RX         0x2
 601
 602 #define NV_TX_LIMIT_COUNT     16
 603
 604 #define NV_DYNAMIC_THRESHOLD        4
 605 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
 606
 607 /* statistics */
 608 struct nv_ethtool_str {
 609         char name[ETH_GSTRING_LEN];
 610 };
 611
 612 static const struct nv_ethtool_str nv_estats_str[] = {
 613         { "tx_bytes" }, /* includes Ethernet FCS CRC */
 614         { "tx_zero_rexmt" },
 615         { "tx_one_rexmt" },
 616         { "tx_many_rexmt" },
 617         { "tx_late_collision" },
 618         { "tx_fifo_errors" },
 619         { "tx_carrier_errors" },
 620         { "tx_excess_deferral" },
 621         { "tx_retry_error" },
 622         { "rx_frame_error" },
 623         { "rx_extra_byte" },
 624         { "rx_late_collision" },
 625         { "rx_runt" },
 626         { "rx_frame_too_long" },
 627         { "rx_over_errors" },
 628         { "rx_crc_errors" },
 629         { "rx_frame_align_error" },
 630         { "rx_length_error" },
 631         { "rx_unicast" },
 632         { "rx_multicast" },
 633         { "rx_broadcast" },
 634         { "rx_packets" },
 635         { "rx_errors_total" },
 636         { "tx_errors_total" },
 637
 638         /* version 2 stats */
 639         { "tx_deferral" },
 640         { "tx_packets" },
 641         { "rx_bytes" }, /* includes Ethernet FCS CRC */
 642         { "tx_pause" },
 643         { "rx_pause" },
 644         { "rx_drop_frame" },
 645
 646         /* version 3 stats */
 647         { "tx_unicast" },
 648         { "tx_multicast" },
 649         { "tx_broadcast" }
 650 };
 651
 652 struct nv_ethtool_stats {
 653         u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */
 654         u64 tx_zero_rexmt;
 655         u64 tx_one_rexmt;
 656         u64 tx_many_rexmt;
 657         u64 tx_late_collision;
 658         u64 tx_fifo_errors;
 659         u64 tx_carrier_errors;
 660         u64 tx_excess_deferral;
 661         u64 tx_retry_error;
 662         u64 rx_frame_error;
 663         u64 rx_extra_byte;
 664         u64 rx_late_collision;
 665         u64 rx_runt;
 666         u64 rx_frame_too_long;
 667         u64 rx_over_errors;
 668         u64 rx_crc_errors;
 669         u64 rx_frame_align_error;
 670         u64 rx_length_error;
 671         u64 rx_unicast;
 672         u64 rx_multicast;
 673         u64 rx_broadcast;
 674         u64 rx_packets; /* should be ifconfig->rx_packets */
 675         u64 rx_errors_total;
 676         u64 tx_errors_total;
 677
 678         /* version 2 stats */
 679         u64 tx_deferral;
 680         u64 tx_packets; /* should be ifconfig->tx_packets */
 681         u64 rx_bytes;   /* should be ifconfig->rx_bytes + 4*rx_packets */
 682         u64 tx_pause;
 683         u64 rx_pause;
 684         u64 rx_drop_frame;
 685
 686         /* version 3 stats */
 687         u64 tx_unicast;
 688         u64 tx_multicast;
 689         u64 tx_broadcast;
 690 };
 691
 692 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 693 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 694 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 695
 696 /* diagnostics */
 697 #define NV_TEST_COUNT_BASE 3
 698 #define NV_TEST_COUNT_EXTENDED 4
 699
 700 static const struct nv_ethtool_str nv_etests_str[] = {
 701         { "link      (online/offline)" },
 702         { "register  (offline)       " },
 703         { "interrupt (offline)       " },
 704         { "loopback  (offline)       " }
 705 };
 706
 707 struct register_test {
 708         __u32 reg;
 709         __u32 mask;
 710 };
 711
 712 static const struct register_test nv_registers_test[] = {
 713         { NvRegUnknownSetupReg6, 0x01 },
 714         { NvRegMisc1, 0x03c },
 715         { NvRegOffloadConfig, 0x03ff },
 716         { NvRegMulticastAddrA, 0xffffffff },
 717         { NvRegTxWatermark, 0x0ff },
 718         { NvRegWakeUpFlags, 0x07777 },
 719         { 0, 0 }
 720 };
 721
 722 struct nv_skb_map {
 723         struct sk_buff *skb;
 724         dma_addr_t dma;
 725         unsigned int dma_len:31;
 726         unsigned int dma_single:1;
 727         struct ring_desc_ex *first_tx_desc;
 728         struct nv_skb_map *next_tx_ctx;
 729 };
 730
 731 /*
 732  * SMP locking:
 733  * All hardware access under netdev_priv(dev)->lock, except the performance
 734  * critical parts:
 735  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 736  *      by the arch code for interrupts.
 737  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 738  *      needs netdev_priv(dev)->lock :-(
 739  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 740  *
 741  * Hardware stats updates are protected by hwstats_lock:
 742  * - updated by nv_do_stats_poll (timer). This is meant to avoid
 743  *   integer wraparound in the NIC stats registers, at low frequency
 744  *   (0.1 Hz)
 745  * - updated by nv_get_ethtool_stats + nv_get_stats64
 746  *
 747  * Software stats are accessed only through 64b synchronization points
 748  * and are not subject to other synchronization techniques (single
 749  * update thread on the TX or RX paths).
 750  */
 751
 752 /* in dev: base, irq */
 753 struct fe_priv {
 754         spinlock_t lock;
 755
 756         struct net_device *dev;
 757         struct napi_struct napi;
 758
 759         /* hardware stats are updated in syscall and timer */
 760         spinlock_t hwstats_lock;
 761         struct nv_ethtool_stats estats;
 762
 763         int in_shutdown;
 764         u32 linkspeed;
 765         int duplex;
 766         int autoneg;
 767         int fixed_mode;
 768         int phyaddr;
 769         int wolenabled;
 770         unsigned int phy_oui;
 771         unsigned int phy_model;
 772         unsigned int phy_rev;
 773         u16 gigabit;
 774         int intr_test;
 775         int recover_error;
 776         int quiet_count;
 777
 778         /* General data: RO fields */
 779         dma_addr_t ring_addr;
 780         struct pci_dev *pci_dev;
 781         u32 orig_mac[2];
 782         u32 events;
 783         u32 irqmask;
 784         u32 desc_ver;
 785         u32 txrxctl_bits;
 786         u32 vlanctl_bits;
 787         u32 driver_data;
 788         u32 device_id;
 789         u32 register_size;
 790         u32 mac_in_use;
 791         int mgmt_version;
 792         int mgmt_sema;
 793
 794         void __iomem *base;
 795
 796         /* rx specific fields.
 797          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 798          */
 799         union ring_type get_rx, put_rx, first_rx, last_rx;
 800         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 801         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 802         struct nv_skb_map *rx_skb;
 803
 804         union ring_type rx_ring;
 805         unsigned int rx_buf_sz;
 806         unsigned int pkt_limit;
 807         struct timer_list oom_kick;
 808         struct timer_list nic_poll;
 809         struct timer_list stats_poll;
 810         u32 nic_poll_irq;
 811         int rx_ring_size;
 812
 813         /* RX software stats */
 814         struct u64_stats_sync swstats_rx_syncp;
 815         u64 stat_rx_packets;
 816         u64 stat_rx_bytes; /* not always available in HW */
 817         u64 stat_rx_missed_errors;
 818         u64 stat_rx_dropped;
 819
 820         /* media detection workaround.
 821          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 822          */
 823         int need_linktimer;
 824         unsigned long link_timeout;
 825         /*
 826          * tx specific fields.
 827          */
 828         union ring_type get_tx, put_tx, first_tx, last_tx;
 829         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 830         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 831         struct nv_skb_map *tx_skb;
 832
 833         union ring_type tx_ring;
 834         u32 tx_flags;
 835         int tx_ring_size;
 836         int tx_limit;
 837         u32 tx_pkts_in_progress;
 838         struct nv_skb_map *tx_change_owner;
 839         struct nv_skb_map *tx_end_flip;
 840         int tx_stop;
 841
 842         /* TX software stats */
 843         struct u64_stats_sync swstats_tx_syncp;
 844         u64 stat_tx_packets; /* not always available in HW */
 845         u64 stat_tx_bytes;
 846         u64 stat_tx_dropped;
 847
 848         /* msi/msi-x fields */
 849         u32 msi_flags;
 850         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 851
 852         /* flow control */
 853         u32 pause_flags;
 854
 855         /* power saved state */
 856         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 857
 858         /* for different msi-x irq type */
 859         char name_rx[IFNAMSIZ + 3];       /* -rx    */
 860         char name_tx[IFNAMSIZ + 3];       /* -tx    */
 861         char name_other[IFNAMSIZ + 6];    /* -other */
 862 };
 863
 864 /*
 865  * Maximum number of loops until we assume that a bit in the irq mask
 866  * is stuck. Overridable with module param.
 867  */
 868 static int max_interrupt_work = 4;
 869
 870 /*
 871  * Optimization can be either throuput mode or cpu mode
 872  *
 873  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 874  * CPU Mode: Interrupts are controlled by a timer.
 875  */
 876 enum {
 877         NV_OPTIMIZATION_MODE_THROUGHPUT,
 878         NV_OPTIMIZATION_MODE_CPU,
 879         NV_OPTIMIZATION_MODE_DYNAMIC
 880 };
 881 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
 882
 883 /*
 884  * Poll interval for timer irq
 885  *
 886  * This interval determines how frequent an interrupt is generated.
 887  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 888  * Min = 0, and Max = 65535
 889  */
 890 static int poll_interval = -1;
 891
 892 /*
 893  * MSI interrupts
 894  */
 895 enum {
 896         NV_MSI_INT_DISABLED,
 897         NV_MSI_INT_ENABLED
 898 };
 899 static int msi = NV_MSI_INT_ENABLED;
 900
 901 /*
 902  * MSIX interrupts
 903  */
 904 enum {
 905         NV_MSIX_INT_DISABLED,
 906         NV_MSIX_INT_ENABLED
 907 };
 908 static int msix = NV_MSIX_INT_ENABLED;
 909
 910 /*
 911  * DMA 64bit
 912  */
 913 enum {
 914         NV_DMA_64BIT_DISABLED,
 915         NV_DMA_64BIT_ENABLED
 916 };
 917 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 918
 919 /*
 920  * Debug output control for tx_timeout
 921  */
 922 static bool debug_tx_timeout = false;
 923
 924 /*
 925  * Crossover Detection
 926  * Realtek 8201 phy + some OEM boards do not work properly.
 927  */
 928 enum {
 929         NV_CROSSOVER_DETECTION_DISABLED,
 930         NV_CROSSOVER_DETECTION_ENABLED
 931 };
 932 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 933
 934 /*
 935  * Power down phy when interface is down (persists through reboot;
 936  * older Linux and other OSes may not power it up again)
 937  */
 938 static int phy_power_down;
 939
 940 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 941 {
 942         return netdev_priv(dev);
 943 }
 944
 945 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 946 {
 947         return ((struct fe_priv *)netdev_priv(dev))->base;
 948 }
 949
 950 static inline void pci_push(u8 __iomem *base)
 951 {
 952         /* force out pending posted writes */
 953         readl(base);
 954 }
 955
 956 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 957 {
 958         return le32_to_cpu(prd->flaglen)
 959                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 960 }
 961
 962 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 963 {
 964         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 965 }
 966
 967 static bool nv_optimized(struct fe_priv *np)
 968 {
 969         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 970                 return false;
 971         return true;
 972 }
 973
 974 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 975                      int delay, int delaymax)
 976 {
 977         u8 __iomem *base = get_hwbase(dev);
 978
 979         pci_push(base);
 980         do {
 981                 udelay(delay);
 982                 delaymax -= delay;
 983                 if (delaymax < 0)
 984                         return 1;
 985         } while ((readl(base + offset) & mask) != target);
 986         return 0;
 987 }
 988
 989 #define NV_SETUP_RX_RING 0x01
 990 #define NV_SETUP_TX_RING 0x02
 991
 992 static inline u32 dma_low(dma_addr_t addr)
 993 {
 994         return addr;
 995 }
 996
 997 static inline u32 dma_high(dma_addr_t addr)
 998 {
 999         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
1000 }
1001
1002 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
1003 {
1004         struct fe_priv *np = get_nvpriv(dev);
1005         u8 __iomem *base = get_hwbase(dev);
1006
1007         if (!nv_optimized(np)) {
1008                 if (rxtx_flags & NV_SETUP_RX_RING)
1009                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1010                 if (rxtx_flags & NV_SETUP_TX_RING)
1011                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1012         } else {
1013                 if (rxtx_flags & NV_SETUP_RX_RING) {
1014                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1015                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
1016                 }
1017                 if (rxtx_flags & NV_SETUP_TX_RING) {
1018                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1019                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
1020                 }
1021         }
1022 }
1023
1024 static void free_rings(struct net_device *dev)
1025 {
1026         struct fe_priv *np = get_nvpriv(dev);
1027
1028         if (!nv_optimized(np)) {
1029                 if (np->rx_ring.orig)
1030                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1031                                             np->rx_ring.orig, np->ring_addr);
1032         } else {
1033                 if (np->rx_ring.ex)
1034                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1035                                             np->rx_ring.ex, np->ring_addr);
1036         }
1037         kfree(np->rx_skb);
1038         kfree(np->tx_skb);
1039 }
1040
1041 static int using_multi_irqs(struct net_device *dev)
1042 {
1043         struct fe_priv *np = get_nvpriv(dev);
1044
1045         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1046             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1047              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1048                 return 0;
1049         else
1050                 return 1;
1051 }
1052
1053 static void nv_txrx_gate(struct net_device *dev, bool gate)
1054 {
1055         struct fe_priv *np = get_nvpriv(dev);
1056         u8 __iomem *base = get_hwbase(dev);
1057         u32 powerstate;
1058
1059         if (!np->mac_in_use &&
1060             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1061                 powerstate = readl(base + NvRegPowerState2);
1062                 if (gate)
1063                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1064                 else
1065                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1066                 writel(powerstate, base + NvRegPowerState2);
1067         }
1068 }
1069
1070 static void nv_enable_irq(struct net_device *dev)
1071 {
1072         struct fe_priv *np = get_nvpriv(dev);
1073
1074         if (!using_multi_irqs(dev)) {
1075                 if (np->msi_flags & NV_MSI_X_ENABLED)
1076                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1077                 else
1078                         enable_irq(np->pci_dev->irq);
1079         } else {
1080                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1081                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1082                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1083         }
1084 }
1085
1086 static void nv_disable_irq(struct net_device *dev)
1087 {
1088         struct fe_priv *np = get_nvpriv(dev);
1089
1090         if (!using_multi_irqs(dev)) {
1091                 if (np->msi_flags & NV_MSI_X_ENABLED)
1092                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1093                 else
1094                         disable_irq(np->pci_dev->irq);
1095         } else {
1096                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1097                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1098                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1099         }
1100 }
1101
1102 /* In MSIX mode, a write to irqmask behaves as XOR */
1103 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1104 {
1105         u8 __iomem *base = get_hwbase(dev);
1106
1107         writel(mask, base + NvRegIrqMask);
1108 }
1109
1110 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1111 {
1112         struct fe_priv *np = get_nvpriv(dev);
1113         u8 __iomem *base = get_hwbase(dev);
1114
1115         if (np->msi_flags & NV_MSI_X_ENABLED) {
1116                 writel(mask, base + NvRegIrqMask);
1117         } else {
1118                 if (np->msi_flags & NV_MSI_ENABLED)
1119                         writel(0, base + NvRegMSIIrqMask);
1120                 writel(0, base + NvRegIrqMask);
1121         }
1122 }
1123
1124 static void nv_napi_enable(struct net_device *dev)
1125 {
1126         struct fe_priv *np = get_nvpriv(dev);
1127
1128         napi_enable(&np->napi);
1129 }
1130
1131 static void nv_napi_disable(struct net_device *dev)
1132 {
1133         struct fe_priv *np = get_nvpriv(dev);
1134
1135         napi_disable(&np->napi);
1136 }
1137
1138 #define MII_READ        (-1)
1139 /* mii_rw: read/write a register on the PHY.
1140  *
1141  * Caller must guarantee serialization
1142  */
1143 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1144 {
1145         u8 __iomem *base = get_hwbase(dev);
1146         u32 reg;
1147         int retval;
1148
1149         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1150
1151         reg = readl(base + NvRegMIIControl);
1152         if (reg & NVREG_MIICTL_INUSE) {
1153                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1154                 udelay(NV_MIIBUSY_DELAY);
1155         }
1156
1157         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1158         if (value != MII_READ) {
1159                 writel(value, base + NvRegMIIData);
1160                 reg |= NVREG_MIICTL_WRITE;
1161         }
1162         writel(reg, base + NvRegMIIControl);
1163
1164         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1165                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1166                 retval = -1;
1167         } else if (value != MII_READ) {
1168                 /* it was a write operation - fewer failures are detectable */
1169                 retval = 0;
1170         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1171                 retval = -1;
1172         } else {
1173                 retval = readl(base + NvRegMIIData);
1174         }
1175
1176         return retval;
1177 }
1178
1179 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1180 {
1181         struct fe_priv *np = netdev_priv(dev);
1182         u32 miicontrol;
1183         unsigned int tries = 0;
1184
1185         miicontrol = BMCR_RESET | bmcr_setup;
1186         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1187                 return -1;
1188
1189         /* wait for 500ms */
1190         msleep(500);
1191
1192         /* must wait till reset is deasserted */
1193         while (miicontrol & BMCR_RESET) {
1194                 usleep_range(10000, 20000);
1195                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1196                 /* FIXME: 100 tries seem excessive */
1197                 if (tries++ > 100)
1198                         return -1;
1199         }
1200         return 0;
1201 }
1202
1203 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1204 {
1205         static const struct {
1206                 int reg;
1207                 int init;
1208         } ri[] = {
1209                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1210                 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1211                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1212                 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1213                 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1214                 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1215                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1216         };
1217         int i;
1218
1219         for (i = 0; i < ARRAY_SIZE(ri); i++) {
1220                 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1221                         return PHY_ERROR;
1222         }
1223
1224         return 0;
1225 }
1226
1227 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1228 {
1229         u32 reg;
1230         u8 __iomem *base = get_hwbase(dev);
1231         u32 powerstate = readl(base + NvRegPowerState2);
1232
1233         /* need to perform hw phy reset */
1234         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1235         writel(powerstate, base + NvRegPowerState2);
1236         msleep(25);
1237
1238         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1239         writel(powerstate, base + NvRegPowerState2);
1240         msleep(25);
1241
1242         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1243         reg |= PHY_REALTEK_INIT9;
1244         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1245                 return PHY_ERROR;
1246         if (mii_rw(dev, np->phyaddr,
1247                    PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1248                 return PHY_ERROR;
1249         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1250         if (!(reg & PHY_REALTEK_INIT11)) {
1251                 reg |= PHY_REALTEK_INIT11;
1252                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1253                         return PHY_ERROR;
1254         }
1255         if (mii_rw(dev, np->phyaddr,
1256                    PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1257                 return PHY_ERROR;
1258
1259         return 0;
1260 }
1261
1262 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1263 {
1264         u32 phy_reserved;
1265
1266         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1267                 phy_reserved = mii_rw(dev, np->phyaddr,
1268                                       PHY_REALTEK_INIT_REG6, MII_READ);
1269                 phy_reserved |= PHY_REALTEK_INIT7;
1270                 if (mii_rw(dev, np->phyaddr,
1271                            PHY_REALTEK_INIT_REG6, phy_reserved))
1272                         return PHY_ERROR;
1273         }
1274
1275         return 0;
1276 }
1277
1278 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1279 {
1280         u32 phy_reserved;
1281
1282         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1283                 if (mii_rw(dev, np->phyaddr,
1284                            PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1285                         return PHY_ERROR;
1286                 phy_reserved = mii_rw(dev, np->phyaddr,
1287                                       PHY_REALTEK_INIT_REG2, MII_READ);
1288                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1289                 phy_reserved |= PHY_REALTEK_INIT3;
1290                 if (mii_rw(dev, np->phyaddr,
1291                            PHY_REALTEK_INIT_REG2, phy_reserved))
1292                         return PHY_ERROR;
1293                 if (mii_rw(dev, np->phyaddr,
1294                            PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1295                         return PHY_ERROR;
1296         }
1297
1298         return 0;
1299 }
1300
1301 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1302                        u32 phyinterface)
1303 {
1304         u32 phy_reserved;
1305
1306         if (phyinterface & PHY_RGMII) {
1307                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1308                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1309                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1310                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1311                         return PHY_ERROR;
1312                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1313                 phy_reserved |= PHY_CICADA_INIT5;
1314                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1315                         return PHY_ERROR;
1316         }
1317         phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1318         phy_reserved |= PHY_CICADA_INIT6;
1319         if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1320                 return PHY_ERROR;
1321
1322         return 0;
1323 }
1324
1325 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1326 {
1327         u32 phy_reserved;
1328
1329         if (mii_rw(dev, np->phyaddr,
1330                    PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1331                 return PHY_ERROR;
1332         if (mii_rw(dev, np->phyaddr,
1333                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1334                 return PHY_ERROR;
1335         phy_reserved = mii_rw(dev, np->phyaddr,
1336                               PHY_VITESSE_INIT_REG4, MII_READ);
1337         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1338                 return PHY_ERROR;
1339         phy_reserved = mii_rw(dev, np->phyaddr,
1340                               PHY_VITESSE_INIT_REG3, MII_READ);
1341         phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1342         phy_reserved |= PHY_VITESSE_INIT3;
1343         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1344                 return PHY_ERROR;
1345         if (mii_rw(dev, np->phyaddr,
1346                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1347                 return PHY_ERROR;
1348         if (mii_rw(dev, np->phyaddr,
1349                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1350                 return PHY_ERROR;
1351         phy_reserved = mii_rw(dev, np->phyaddr,
1352                               PHY_VITESSE_INIT_REG4, MII_READ);
1353         phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1354         phy_reserved |= PHY_VITESSE_INIT3;
1355         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1356                 return PHY_ERROR;
1357         phy_reserved = mii_rw(dev, np->phyaddr,
1358                               PHY_VITESSE_INIT_REG3, MII_READ);
1359         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1360                 return PHY_ERROR;
1361         if (mii_rw(dev, np->phyaddr,
1362                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1363                 return PHY_ERROR;
1364         if (mii_rw(dev, np->phyaddr,
1365                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1366                 return PHY_ERROR;
1367         phy_reserved = mii_rw(dev, np->phyaddr,
1368                               PHY_VITESSE_INIT_REG4, MII_READ);
1369         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1370                 return PHY_ERROR;
1371         phy_reserved = mii_rw(dev, np->phyaddr,
1372                               PHY_VITESSE_INIT_REG3, MII_READ);
1373         phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1374         phy_reserved |= PHY_VITESSE_INIT8;
1375         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1376                 return PHY_ERROR;
1377         if (mii_rw(dev, np->phyaddr,
1378                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1379                 return PHY_ERROR;
1380         if (mii_rw(dev, np->phyaddr,
1381                    PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1382                 return PHY_ERROR;
1383
1384         return 0;
1385 }
1386
1387 static int phy_init(struct net_device *dev)
1388 {
1389         struct fe_priv *np = get_nvpriv(dev);
1390         u8 __iomem *base = get_hwbase(dev);
1391         u32 phyinterface;
1392         u32 mii_status, mii_control, mii_control_1000, reg;
1393
1394         /* phy errata for E3016 phy */
1395         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1396                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1397                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1398                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1399                         netdev_info(dev, "%s: phy write to errata reg failed\n",
1400                                     pci_name(np->pci_dev));
1401                         return PHY_ERROR;
1402                 }
1403         }
1404         if (np->phy_oui == PHY_OUI_REALTEK) {
1405                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1406                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1407                         if (init_realtek_8211b(dev, np)) {
1408                                 netdev_info(dev, "%s: phy init failed\n",
1409                                             pci_name(np->pci_dev));
1410                                 return PHY_ERROR;
1411                         }
1412                 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1413                            np->phy_rev == PHY_REV_REALTEK_8211C) {
1414                         if (init_realtek_8211c(dev, np)) {
1415                                 netdev_info(dev, "%s: phy init failed\n",
1416                                             pci_name(np->pci_dev));
1417                                 return PHY_ERROR;
1418                         }
1419                 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1420                         if (init_realtek_8201(dev, np)) {
1421                                 netdev_info(dev, "%s: phy init failed\n",
1422                                             pci_name(np->pci_dev));
1423                                 return PHY_ERROR;
1424                         }
1425                 }
1426         }
1427
1428         /* set advertise register */
1429         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1430         reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1431                 ADVERTISE_100HALF | ADVERTISE_100FULL |
1432                 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1433         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1434                 netdev_info(dev, "%s: phy write to advertise failed\n",
1435                             pci_name(np->pci_dev));
1436                 return PHY_ERROR;
1437         }
1438
1439         /* get phy interface type */
1440         phyinterface = readl(base + NvRegPhyInterface);
1441
1442         /* see if gigabit phy */
1443         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1444         if (mii_status & PHY_GIGABIT) {
1445                 np->gigabit = PHY_GIGABIT;
1446                 mii_control_1000 = mii_rw(dev, np->phyaddr,
1447                                           MII_CTRL1000, MII_READ);
1448                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1449                 if (phyinterface & PHY_RGMII)
1450                         mii_control_1000 |= ADVERTISE_1000FULL;
1451                 else
1452                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1453
1454                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1455                         netdev_info(dev, "%s: phy init failed\n",
1456                                     pci_name(np->pci_dev));
1457                         return PHY_ERROR;
1458                 }
1459         } else
1460                 np->gigabit = 0;
1461
1462         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1463         mii_control |= BMCR_ANENABLE;
1464
1465         if (np->phy_oui == PHY_OUI_REALTEK &&
1466             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1467             np->phy_rev == PHY_REV_REALTEK_8211C) {
1468                 /* start autoneg since we already performed hw reset above */
1469                 mii_control |= BMCR_ANRESTART;
1470                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1471                         netdev_info(dev, "%s: phy init failed\n",
1472                                     pci_name(np->pci_dev));
1473                         return PHY_ERROR;
1474                 }
1475         } else {
1476                 /* reset the phy
1477                  * (certain phys need bmcr to be setup with reset)
1478                  */
1479                 if (phy_reset(dev, mii_control)) {
1480                         netdev_info(dev, "%s: phy reset failed\n",
1481                                     pci_name(np->pci_dev));
1482                         return PHY_ERROR;
1483                 }
1484         }
1485
1486         /* phy vendor specific configuration */
1487         if ((np->phy_oui == PHY_OUI_CICADA)) {
1488                 if (init_cicada(dev, np, phyinterface)) {
1489                         netdev_info(dev, "%s: phy init failed\n",
1490                                     pci_name(np->pci_dev));
1491                         return PHY_ERROR;
1492                 }
1493         } else if (np->phy_oui == PHY_OUI_VITESSE) {
1494                 if (init_vitesse(dev, np)) {
1495                         netdev_info(dev, "%s: phy init failed\n",
1496                                     pci_name(np->pci_dev));
1497                         return PHY_ERROR;
1498                 }
1499         } else if (np->phy_oui == PHY_OUI_REALTEK) {
1500                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1501                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1502                         /* reset could have cleared these out, set them back */
1503                         if (init_realtek_8211b(dev, np)) {
1504                                 netdev_info(dev, "%s: phy init failed\n",
1505                                             pci_name(np->pci_dev));
1506                                 return PHY_ERROR;
1507                         }
1508                 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1509                         if (init_realtek_8201(dev, np) ||
1510                             init_realtek_8201_cross(dev, np)) {
1511                                 netdev_info(dev, "%s: phy init failed\n",
1512                                             pci_name(np->pci_dev));
1513                                 return PHY_ERROR;
1514                         }
1515                 }
1516         }
1517
1518         /* some phys clear out pause advertisement on reset, set it back */
1519         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1520
1521         /* restart auto negotiation, power down phy */
1522         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1523         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1524         if (phy_power_down)
1525                 mii_control |= BMCR_PDOWN;
1526         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1527                 return PHY_ERROR;
1528
1529         return 0;
1530 }
1531
1532 static void nv_start_rx(struct net_device *dev)
1533 {
1534         struct fe_priv *np = netdev_priv(dev);
1535         u8 __iomem *base = get_hwbase(dev);
1536         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1537
1538         /* Already running? Stop it. */
1539         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1540                 rx_ctrl &= ~NVREG_RCVCTL_START;
1541                 writel(rx_ctrl, base + NvRegReceiverControl);
1542                 pci_push(base);
1543         }
1544         writel(np->linkspeed, base + NvRegLinkSpeed);
1545         pci_push(base);
1546         rx_ctrl |= NVREG_RCVCTL_START;
1547         if (np->mac_in_use)
1548                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1549         writel(rx_ctrl, base + NvRegReceiverControl);
1550         pci_push(base);
1551 }
1552
1553 static void nv_stop_rx(struct net_device *dev)
1554 {
1555         struct fe_priv *np = netdev_priv(dev);
1556         u8 __iomem *base = get_hwbase(dev);
1557         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1558
1559         if (!np->mac_in_use)
1560                 rx_ctrl &= ~NVREG_RCVCTL_START;
1561         else
1562                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1563         writel(rx_ctrl, base + NvRegReceiverControl);
1564         if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1565                       NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1566                 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1567                             __func__);
1568
1569         udelay(NV_RXSTOP_DELAY2);
1570         if (!np->mac_in_use)
1571                 writel(0, base + NvRegLinkSpeed);
1572 }
1573
1574 static void nv_start_tx(struct net_device *dev)
1575 {
1576         struct fe_priv *np = netdev_priv(dev);
1577         u8 __iomem *base = get_hwbase(dev);
1578         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1579
1580         tx_ctrl |= NVREG_XMITCTL_START;
1581         if (np->mac_in_use)
1582                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1583         writel(tx_ctrl, base + NvRegTransmitterControl);
1584         pci_push(base);
1585 }
1586
1587 static void nv_stop_tx(struct net_device *dev)
1588 {
1589         struct fe_priv *np = netdev_priv(dev);
1590         u8 __iomem *base = get_hwbase(dev);
1591         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1592
1593         if (!np->mac_in_use)
1594                 tx_ctrl &= ~NVREG_XMITCTL_START;
1595         else
1596                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1597         writel(tx_ctrl, base + NvRegTransmitterControl);
1598         if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1599                       NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1600                 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1601                             __func__);
1602
1603         udelay(NV_TXSTOP_DELAY2);
1604         if (!np->mac_in_use)
1605                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1606                        base + NvRegTransmitPoll);
1607 }
1608
1609 static void nv_start_rxtx(struct net_device *dev)
1610 {
1611         nv_start_rx(dev);
1612         nv_start_tx(dev);
1613 }
1614
1615 static void nv_stop_rxtx(struct net_device *dev)
1616 {
1617         nv_stop_rx(dev);
1618         nv_stop_tx(dev);
1619 }
1620
1621 static void nv_txrx_reset(struct net_device *dev)
1622 {
1623         struct fe_priv *np = netdev_priv(dev);
1624         u8 __iomem *base = get_hwbase(dev);
1625
1626         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1627         pci_push(base);
1628         udelay(NV_TXRX_RESET_DELAY);
1629         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1630         pci_push(base);
1631 }
1632
1633 static void nv_mac_reset(struct net_device *dev)
1634 {
1635         struct fe_priv *np = netdev_priv(dev);
1636         u8 __iomem *base = get_hwbase(dev);
1637         u32 temp1, temp2, temp3;
1638
1639         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1640         pci_push(base);
1641
1642         /* save registers since they will be cleared on reset */
1643         temp1 = readl(base + NvRegMacAddrA);
1644         temp2 = readl(base + NvRegMacAddrB);
1645         temp3 = readl(base + NvRegTransmitPoll);
1646
1647         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1648         pci_push(base);
1649         udelay(NV_MAC_RESET_DELAY);
1650         writel(0, base + NvRegMacReset);
1651         pci_push(base);
1652         udelay(NV_MAC_RESET_DELAY);
1653
1654         /* restore saved registers */
1655         writel(temp1, base + NvRegMacAddrA);
1656         writel(temp2, base + NvRegMacAddrB);
1657         writel(temp3, base + NvRegTransmitPoll);
1658
1659         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1660         pci_push(base);
1661 }
1662
1663 /* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */
1664 static void nv_update_stats(struct net_device *dev)
1665 {
1666         struct fe_priv *np = netdev_priv(dev);
1667         u8 __iomem *base = get_hwbase(dev);
1668
1669         /* If it happens that this is run in top-half context, then
1670          * replace the spin_lock of hwstats_lock with
1671          * spin_lock_irqsave() in calling functions. */
1672         WARN_ONCE(in_irq(), "forcedeth: estats spin_lock(_bh) from top-half");
1673         assert_spin_locked(&np->hwstats_lock);
1674
1675         /* query hardware */
1676         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1677         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1678         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1679         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1680         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1681         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1682         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1683         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1684         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1685         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1686         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1687         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1688         np->estats.rx_runt += readl(base + NvRegRxRunt);
1689         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1690         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1691         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1692         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1693         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1694         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1695         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1696         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1697         np->estats.rx_packets =
1698                 np->estats.rx_unicast +
1699                 np->estats.rx_multicast +
1700                 np->estats.rx_broadcast;
1701         np->estats.rx_errors_total =
1702                 np->estats.rx_crc_errors +
1703                 np->estats.rx_over_errors +
1704                 np->estats.rx_frame_error +
1705                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1706                 np->estats.rx_late_collision +
1707                 np->estats.rx_runt +
1708                 np->estats.rx_frame_too_long;
1709         np->estats.tx_errors_total =
1710                 np->estats.tx_late_collision +
1711                 np->estats.tx_fifo_errors +
1712                 np->estats.tx_carrier_errors +
1713                 np->estats.tx_excess_deferral +
1714                 np->estats.tx_retry_error;
1715
1716         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1717                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1718                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1719                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1720                 np->estats.tx_pause += readl(base + NvRegTxPause);
1721                 np->estats.rx_pause += readl(base + NvRegRxPause);
1722                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1723                 np->estats.rx_errors_total += np->estats.rx_drop_frame;
1724         }
1725
1726         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1727                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1728                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1729                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1730         }
1731 }
1732
1733 /*
1734  * nv_get_stats64: dev->ndo_get_stats64 function
1735  * Get latest stats value from the nic.
1736  * Called with read_lock(&dev_base_lock) held for read -
1737  * only synchronized against unregister_netdevice.
1738  */
1739 static struct rtnl_link_stats64*
1740 nv_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *storage)
1741         __acquires(&netdev_priv(dev)->hwstats_lock)
1742         __releases(&netdev_priv(dev)->hwstats_lock)
1743 {
1744         struct fe_priv *np = netdev_priv(dev);
1745         unsigned int syncp_start;
1746
1747         /*
1748          * Note: because HW stats are not always available and for
1749          * consistency reasons, the following ifconfig stats are
1750          * managed by software: rx_bytes, tx_bytes, rx_packets and
1751          * tx_packets. The related hardware stats reported by ethtool
1752          * should be equivalent to these ifconfig stats, with 4
1753          * additional bytes per packet (Ethernet FCS CRC), except for
1754          * tx_packets when TSO kicks in.
1755          */
1756
1757         /* software stats */
1758         do {
1759                 syncp_start = u64_stats_fetch_begin_bh(&np->swstats_rx_syncp);
1760                 storage->rx_packets       = np->stat_rx_packets;
1761                 storage->rx_bytes         = np->stat_rx_bytes;
1762                 storage->rx_dropped       = np->stat_rx_dropped;
1763                 storage->rx_missed_errors = np->stat_rx_missed_errors;
1764         } while (u64_stats_fetch_retry_bh(&np->swstats_rx_syncp, syncp_start));
1765
1766         do {
1767                 syncp_start = u64_stats_fetch_begin_bh(&np->swstats_tx_syncp);
1768                 storage->tx_packets = np->stat_tx_packets;
1769                 storage->tx_bytes   = np->stat_tx_bytes;
1770                 storage->tx_dropped = np->stat_tx_dropped;
1771         } while (u64_stats_fetch_retry_bh(&np->swstats_tx_syncp, syncp_start));
1772
1773         /* If the nic supports hw counters then retrieve latest values */
1774         if (np->driver_data & DEV_HAS_STATISTICS_V123) {
1775                 spin_lock_bh(&np->hwstats_lock);
1776
1777                 nv_update_stats(dev);
1778
1779                 /* generic stats */
1780                 storage->rx_errors = np->estats.rx_errors_total;
1781                 storage->tx_errors = np->estats.tx_errors_total;
1782
1783                 /* meaningful only when NIC supports stats v3 */
1784                 storage->multicast = np->estats.rx_multicast;
1785
1786                 /* detailed rx_errors */
1787                 storage->rx_length_errors = np->estats.rx_length_error;
1788                 storage->rx_over_errors   = np->estats.rx_over_errors;
1789                 storage->rx_crc_errors    = np->estats.rx_crc_errors;
1790                 storage->rx_frame_errors  = np->estats.rx_frame_align_error;
1791                 storage->rx_fifo_errors   = np->estats.rx_drop_frame;
1792
1793                 /* detailed tx_errors */
1794                 storage->tx_carrier_errors = np->estats.tx_carrier_errors;
1795                 storage->tx_fifo_errors    = np->estats.tx_fifo_errors;
1796
1797                 spin_unlock_bh(&np->hwstats_lock);
1798         }
1799
1800         return storage;
1801 }
1802
1803 /*
1804  * nv_alloc_rx: fill rx ring entries.
1805  * Return 1 if the allocations for the skbs failed and the
1806  * rx engine is without Available descriptors
1807  */
1808 static int nv_alloc_rx(struct net_device *dev)
1809 {
1810         struct fe_priv *np = netdev_priv(dev);
1811         struct ring_desc *less_rx;
1812
1813         less_rx = np->get_rx.orig;
1814         if (less_rx-- == np->first_rx.orig)
1815                 less_rx = np->last_rx.orig;
1816
1817         while (np->put_rx.orig != less_rx) {
1818                 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1819                 if (skb) {
1820                         np->put_rx_ctx->skb = skb;
1821                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1822                                                              skb->data,
1823                                                              skb_tailroom(skb),
1824                                                              PCI_DMA_FROMDEVICE);
1825                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1826                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1827                         wmb();
1828                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1829                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1830                                 np->put_rx.orig = np->first_rx.orig;
1831                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1832                                 np->put_rx_ctx = np->first_rx_ctx;
1833                 } else {
1834                         u64_stats_update_begin(&np->swstats_rx_syncp);
1835                         np->stat_rx_dropped++;
1836                         u64_stats_update_end(&np->swstats_rx_syncp);
1837                         return 1;
1838                 }
1839         }
1840         return 0;
1841 }
1842
1843 static int nv_alloc_rx_optimized(struct net_device *dev)
1844 {
1845         struct fe_priv *np = netdev_priv(dev);
1846         struct ring_desc_ex *less_rx;
1847
1848         less_rx = np->get_rx.ex;
1849         if (less_rx-- == np->first_rx.ex)
1850                 less_rx = np->last_rx.ex;
1851
1852         while (np->put_rx.ex != less_rx) {
1853                 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1854                 if (skb) {
1855                         np->put_rx_ctx->skb = skb;
1856                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1857                                                              skb->data,
1858                                                              skb_tailroom(skb),
1859                                                              PCI_DMA_FROMDEVICE);
1860                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1861                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1862                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1863                         wmb();
1864                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1865                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1866                                 np->put_rx.ex = np->first_rx.ex;
1867                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1868                                 np->put_rx_ctx = np->first_rx_ctx;
1869                 } else {
1870                         u64_stats_update_begin(&np->swstats_rx_syncp);
1871                         np->stat_rx_dropped++;
1872                         u64_stats_update_end(&np->swstats_rx_syncp);
1873                         return 1;
1874                 }
1875         }
1876         return 0;
1877 }
1878
1879 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1880 static void nv_do_rx_refill(unsigned long data)
1881 {
1882         struct net_device *dev = (struct net_device *) data;
1883         struct fe_priv *np = netdev_priv(dev);
1884
1885         /* Just reschedule NAPI rx processing */
1886         napi_schedule(&np->napi);
1887 }
1888
1889 static void nv_init_rx(struct net_device *dev)
1890 {
1891         struct fe_priv *np = netdev_priv(dev);
1892         int i;
1893
1894         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1895
1896         if (!nv_optimized(np))
1897                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1898         else
1899                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1900         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1901         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1902
1903         for (i = 0; i < np->rx_ring_size; i++) {
1904                 if (!nv_optimized(np)) {
1905                         np->rx_ring.orig[i].flaglen = 0;
1906                         np->rx_ring.orig[i].buf = 0;
1907                 } else {
1908                         np->rx_ring.ex[i].flaglen = 0;
1909                         np->rx_ring.ex[i].txvlan = 0;
1910                         np->rx_ring.ex[i].bufhigh = 0;
1911                         np->rx_ring.ex[i].buflow = 0;
1912                 }
1913                 np->rx_skb[i].skb = NULL;
1914                 np->rx_skb[i].dma = 0;
1915         }
1916 }
1917
1918 static void nv_init_tx(struct net_device *dev)
1919 {
1920         struct fe_priv *np = netdev_priv(dev);
1921         int i;
1922
1923         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1924
1925         if (!nv_optimized(np))
1926                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1927         else
1928                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1929         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1930         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1931         netdev_reset_queue(np->dev);
1932         np->tx_pkts_in_progress = 0;
1933         np->tx_change_owner = NULL;
1934         np->tx_end_flip = NULL;
1935         np->tx_stop = 0;
1936
1937         for (i = 0; i < np->tx_ring_size; i++) {
1938                 if (!nv_optimized(np)) {
1939                         np->tx_ring.orig[i].flaglen = 0;
1940                         np->tx_ring.orig[i].buf = 0;
1941                 } else {
1942                         np->tx_ring.ex[i].flaglen = 0;
1943                         np->tx_ring.ex[i].txvlan = 0;
1944                         np->tx_ring.ex[i].bufhigh = 0;
1945                         np->tx_ring.ex[i].buflow = 0;
1946                 }
1947                 np->tx_skb[i].skb = NULL;
1948                 np->tx_skb[i].dma = 0;
1949                 np->tx_skb[i].dma_len = 0;
1950                 np->tx_skb[i].dma_single = 0;
1951                 np->tx_skb[i].first_tx_desc = NULL;
1952                 np->tx_skb[i].next_tx_ctx = NULL;
1953         }
1954 }
1955
1956 static int nv_init_ring(struct net_device *dev)
1957 {
1958         struct fe_priv *np = netdev_priv(dev);
1959
1960         nv_init_tx(dev);
1961         nv_init_rx(dev);
1962
1963         if (!nv_optimized(np))
1964                 return nv_alloc_rx(dev);
1965         else
1966                 return nv_alloc_rx_optimized(dev);
1967 }
1968
1969 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1970 {
1971         if (tx_skb->dma) {
1972                 if (tx_skb->dma_single)
1973                         pci_unmap_single(np->pci_dev, tx_skb->dma,
1974                                          tx_skb->dma_len,
1975                                          PCI_DMA_TODEVICE);
1976                 else
1977                         pci_unmap_page(np->pci_dev, tx_skb->dma,
1978                                        tx_skb->dma_len,
1979                                        PCI_DMA_TODEVICE);
1980                 tx_skb->dma = 0;
1981         }
1982 }
1983
1984 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1985 {
1986         nv_unmap_txskb(np, tx_skb);
1987         if (tx_skb->skb) {
1988                 dev_kfree_skb_any(tx_skb->skb);
1989                 tx_skb->skb = NULL;
1990                 return 1;
1991         }
1992         return 0;
1993 }
1994
1995 static void nv_drain_tx(struct net_device *dev)
1996 {
1997         struct fe_priv *np = netdev_priv(dev);
1998         unsigned int i;
1999
2000         for (i = 0; i < np->tx_ring_size; i++) {
2001                 if (!nv_optimized(np)) {
2002                         np->tx_ring.orig[i].flaglen = 0;
2003                         np->tx_ring.orig[i].buf = 0;
2004                 } else {
2005                         np->tx_ring.ex[i].flaglen = 0;
2006                         np->tx_ring.ex[i].txvlan = 0;
2007                         np->tx_ring.ex[i].bufhigh = 0;
2008                         np->tx_ring.ex[i].buflow = 0;
2009                 }
2010                 if (nv_release_txskb(np, &np->tx_skb[i])) {
2011                         u64_stats_update_begin(&np->swstats_tx_syncp);
2012                         np->stat_tx_dropped++;
2013                         u64_stats_update_end(&np->swstats_tx_syncp);
2014                 }
2015                 np->tx_skb[i].dma = 0;
2016                 np->tx_skb[i].dma_len = 0;
2017                 np->tx_skb[i].dma_single = 0;
2018                 np->tx_skb[i].first_tx_desc = NULL;
2019                 np->tx_skb[i].next_tx_ctx = NULL;
2020         }
2021         np->tx_pkts_in_progress = 0;
2022         np->tx_change_owner = NULL;
2023         np->tx_end_flip = NULL;
2024 }
2025
2026 static void nv_drain_rx(struct net_device *dev)
2027 {
2028         struct fe_priv *np = netdev_priv(dev);
2029         int i;
2030
2031         for (i = 0; i < np->rx_ring_size; i++) {
2032                 if (!nv_optimized(np)) {
2033                         np->rx_ring.orig[i].flaglen = 0;
2034                         np->rx_ring.orig[i].buf = 0;
2035                 } else {
2036                         np->rx_ring.ex[i].flaglen = 0;
2037                         np->rx_ring.ex[i].txvlan = 0;
2038                         np->rx_ring.ex[i].bufhigh = 0;
2039                         np->rx_ring.ex[i].buflow = 0;
2040                 }
2041                 wmb();
2042                 if (np->rx_skb[i].skb) {
2043                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
2044                                          (skb_end_pointer(np->rx_skb[i].skb) -
2045                                           np->rx_skb[i].skb->data),
2046                                          PCI_DMA_FROMDEVICE);
2047                         dev_kfree_skb(np->rx_skb[i].skb);
2048                         np->rx_skb[i].skb = NULL;
2049                 }
2050         }
2051 }
2052
2053 static void nv_drain_rxtx(struct net_device *dev)
2054 {
2055         nv_drain_tx(dev);
2056         nv_drain_rx(dev);
2057 }
2058
2059 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2060 {
2061         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2062 }
2063
2064 static void nv_legacybackoff_reseed(struct net_device *dev)
2065 {
2066         u8 __iomem *base = get_hwbase(dev);
2067         u32 reg;
2068         u32 low;
2069         int tx_status = 0;
2070
2071         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2072         get_random_bytes(&low, sizeof(low));
2073         reg |= low & NVREG_SLOTTIME_MASK;
2074
2075         /* Need to stop tx before change takes effect.
2076          * Caller has already gained np->lock.
2077          */
2078         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2079         if (tx_status)
2080                 nv_stop_tx(dev);
2081         nv_stop_rx(dev);
2082         writel(reg, base + NvRegSlotTime);
2083         if (tx_status)
2084                 nv_start_tx(dev);
2085         nv_start_rx(dev);
2086 }
2087
2088 /* Gear Backoff Seeds */
2089 #define BACKOFF_SEEDSET_ROWS    8
2090 #define BACKOFF_SEEDSET_LFSRS   15
2091
2092 /* Known Good seed sets */
2093 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2094         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2095         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2096         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2097         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2098         {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2099         {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2100         {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2101         {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2102
2103 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2104         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2105         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2106         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2107         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2108         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2109         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2110         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2111         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2112
2113 static void nv_gear_backoff_reseed(struct net_device *dev)
2114 {
2115         u8 __iomem *base = get_hwbase(dev);
2116         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2117         u32 temp, seedset, combinedSeed;
2118         int i;
2119
2120         /* Setup seed for free running LFSR */
2121         /* We are going to read the time stamp counter 3 times
2122            and swizzle bits around to increase randomness */
2123         get_random_bytes(&miniseed1, sizeof(miniseed1));
2124         miniseed1 &= 0x0fff;
2125         if (miniseed1 == 0)
2126                 miniseed1 = 0xabc;
2127
2128         get_random_bytes(&miniseed2, sizeof(miniseed2));
2129         miniseed2 &= 0x0fff;
2130         if (miniseed2 == 0)
2131                 miniseed2 = 0xabc;
2132         miniseed2_reversed =
2133                 ((miniseed2 & 0xF00) >> 8) |
2134                  (miniseed2 & 0x0F0) |
2135                  ((miniseed2 & 0x00F) << 8);
2136
2137         get_random_bytes(&miniseed3, sizeof(miniseed3));
2138         miniseed3 &= 0x0fff;
2139         if (miniseed3 == 0)
2140                 miniseed3 = 0xabc;
2141         miniseed3_reversed =
2142                 ((miniseed3 & 0xF00) >> 8) |
2143                  (miniseed3 & 0x0F0) |
2144                  ((miniseed3 & 0x00F) << 8);
2145
2146         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2147                        (miniseed2 ^ miniseed3_reversed);
2148
2149         /* Seeds can not be zero */
2150         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2151                 combinedSeed |= 0x08;
2152         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2153                 combinedSeed |= 0x8000;
2154
2155         /* No need to disable tx here */
2156         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2157         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2158         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2159         writel(temp, base + NvRegBackOffControl);
2160
2161         /* Setup seeds for all gear LFSRs. */
2162         get_random_bytes(&seedset, sizeof(seedset));
2163         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2164         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2165                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2166                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2167                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2168                 writel(temp, base + NvRegBackOffControl);
2169         }
2170 }
2171
2172 /*
2173  * nv_start_xmit: dev->hard_start_xmit function
2174  * Called with netif_tx_lock held.
2175  */
2176 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2177 {
2178         struct fe_priv *np = netdev_priv(dev);
2179         u32 tx_flags = 0;
2180         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2181         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2182         unsigned int i;
2183         u32 offset = 0;
2184         u32 bcnt;
2185         u32 size = skb_headlen(skb);
2186         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2187         u32 empty_slots;
2188         struct ring_desc *put_tx;
2189         struct ring_desc *start_tx;
2190         struct ring_desc *prev_tx;
2191         struct nv_skb_map *prev_tx_ctx;
2192         unsigned long flags;
2193
2194         /* add fragments to entries count */
2195         for (i = 0; i < fragments; i++) {
2196                 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2197
2198                 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2199                            ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2200         }
2201
2202         spin_lock_irqsave(&np->lock, flags);
2203         empty_slots = nv_get_empty_tx_slots(np);
2204         if (unlikely(empty_slots <= entries)) {
2205                 netif_stop_queue(dev);
2206                 np->tx_stop = 1;
2207                 spin_unlock_irqrestore(&np->lock, flags);
2208                 return NETDEV_TX_BUSY;
2209         }
2210         spin_unlock_irqrestore(&np->lock, flags);
2211
2212         start_tx = put_tx = np->put_tx.orig;
2213
2214         /* setup the header buffer */
2215         do {
2216                 prev_tx = put_tx;
2217                 prev_tx_ctx = np->put_tx_ctx;
2218                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2219                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2220                                                 PCI_DMA_TODEVICE);
2221                 np->put_tx_ctx->dma_len = bcnt;
2222                 np->put_tx_ctx->dma_single = 1;
2223                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2224                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2225
2226                 tx_flags = np->tx_flags;
2227                 offset += bcnt;
2228                 size -= bcnt;
2229                 if (unlikely(put_tx++ == np->last_tx.orig))
2230                         put_tx = np->first_tx.orig;
2231                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2232                         np->put_tx_ctx = np->first_tx_ctx;
2233         } while (size);
2234
2235         /* setup the fragments */
2236         for (i = 0; i < fragments; i++) {
2237                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2238                 u32 frag_size = skb_frag_size(frag);
2239                 offset = 0;
2240
2241                 do {
2242                         prev_tx = put_tx;
2243                         prev_tx_ctx = np->put_tx_ctx;
2244                         bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2245                         np->put_tx_ctx->dma = skb_frag_dma_map(
2246                                                         &np->pci_dev->dev,
2247                                                         frag, offset,
2248                                                         bcnt,
2249                                                         DMA_TO_DEVICE);
2250                         np->put_tx_ctx->dma_len = bcnt;
2251                         np->put_tx_ctx->dma_single = 0;
2252                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2253                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2254
2255                         offset += bcnt;
2256                         frag_size -= bcnt;
2257                         if (unlikely(put_tx++ == np->last_tx.orig))
2258                                 put_tx = np->first_tx.orig;
2259                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2260                                 np->put_tx_ctx = np->first_tx_ctx;
2261                 } while (frag_size);
2262         }
2263
2264         /* set last fragment flag  */
2265         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2266
2267         /* save skb in this slot's context area */
2268         prev_tx_ctx->skb = skb;
2269
2270         if (skb_is_gso(skb))
2271                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2272         else
2273                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2274                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2275
2276         spin_lock_irqsave(&np->lock, flags);
2277
2278         /* set tx flags */
2279         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2280
2281         netdev_sent_queue(np->dev, skb->len);
2282
2283         np->put_tx.orig = put_tx;
2284
2285         spin_unlock_irqrestore(&np->lock, flags);
2286
2287         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2288         return NETDEV_TX_OK;
2289 }
2290
2291 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2292                                            struct net_device *dev)
2293 {
2294         struct fe_priv *np = netdev_priv(dev);
2295         u32 tx_flags = 0;
2296         u32 tx_flags_extra;
2297         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2298         unsigned int i;
2299         u32 offset = 0;
2300         u32 bcnt;
2301         u32 size = skb_headlen(skb);
2302         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2303         u32 empty_slots;
2304         struct ring_desc_ex *put_tx;
2305         struct ring_desc_ex *start_tx;
2306         struct ring_desc_ex *prev_tx;
2307         struct nv_skb_map *prev_tx_ctx;
2308         struct nv_skb_map *start_tx_ctx;
2309         unsigned long flags;
2310
2311         /* add fragments to entries count */
2312         for (i = 0; i < fragments; i++) {
2313                 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2314
2315                 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2316                            ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2317         }
2318
2319         spin_lock_irqsave(&np->lock, flags);
2320         empty_slots = nv_get_empty_tx_slots(np);
2321         if (unlikely(empty_slots <= entries)) {
2322                 netif_stop_queue(dev);
2323                 np->tx_stop = 1;
2324                 spin_unlock_irqrestore(&np->lock, flags);
2325                 return NETDEV_TX_BUSY;
2326         }
2327         spin_unlock_irqrestore(&np->lock, flags);
2328
2329         start_tx = put_tx = np->put_tx.ex;
2330         start_tx_ctx = np->put_tx_ctx;
2331
2332         /* setup the header buffer */
2333         do {
2334                 prev_tx = put_tx;
2335                 prev_tx_ctx = np->put_tx_ctx;
2336                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2337                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2338                                                 PCI_DMA_TODEVICE);
2339                 np->put_tx_ctx->dma_len = bcnt;
2340                 np->put_tx_ctx->dma_single = 1;
2341                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2342                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2343                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2344
2345                 tx_flags = NV_TX2_VALID;
2346                 offset += bcnt;
2347                 size -= bcnt;
2348                 if (unlikely(put_tx++ == np->last_tx.ex))
2349                         put_tx = np->first_tx.ex;
2350                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2351                         np->put_tx_ctx = np->first_tx_ctx;
2352         } while (size);
2353
2354         /* setup the fragments */
2355         for (i = 0; i < fragments; i++) {
2356                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2357                 u32 frag_size = skb_frag_size(frag);
2358                 offset = 0;
2359
2360                 do {
2361                         prev_tx = put_tx;
2362                         prev_tx_ctx = np->put_tx_ctx;
2363                         bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2364                         np->put_tx_ctx->dma = skb_frag_dma_map(
2365                                                         &np->pci_dev->dev,
2366                                                         frag, offset,
2367                                                         bcnt,
2368                                                         DMA_TO_DEVICE);
2369                         np->put_tx_ctx->dma_len = bcnt;
2370                         np->put_tx_ctx->dma_single = 0;
2371                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2372                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2373                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2374
2375                         offset += bcnt;
2376                         frag_size -= bcnt;
2377                         if (unlikely(put_tx++ == np->last_tx.ex))
2378                                 put_tx = np->first_tx.ex;
2379                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2380                                 np->put_tx_ctx = np->first_tx_ctx;
2381                 } while (frag_size);
2382         }
2383
2384         /* set last fragment flag  */
2385         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2386
2387         /* save skb in this slot's context area */
2388         prev_tx_ctx->skb = skb;
2389
2390         if (skb_is_gso(skb))
2391                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2392         else
2393                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2394                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2395
2396         /* vlan tag */
2397         if (vlan_tx_tag_present(skb))
2398                 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2399                                         vlan_tx_tag_get(skb));
2400         else
2401                 start_tx->txvlan = 0;
2402
2403         spin_lock_irqsave(&np->lock, flags);
2404
2405         if (np->tx_limit) {
2406                 /* Limit the number of outstanding tx. Setup all fragments, but
2407                  * do not set the VALID bit on the first descriptor. Save a pointer
2408                  * to that descriptor and also for next skb_map element.
2409                  */
2410
2411                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2412                         if (!np->tx_change_owner)
2413                                 np->tx_change_owner = start_tx_ctx;
2414
2415                         /* remove VALID bit */
2416                         tx_flags &= ~NV_TX2_VALID;
2417                         start_tx_ctx->first_tx_desc = start_tx;
2418                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2419                         np->tx_end_flip = np->put_tx_ctx;
2420                 } else {
2421                         np->tx_pkts_in_progress++;
2422                 }
2423         }
2424
2425         /* set tx flags */
2426         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2427
2428         netdev_sent_queue(np->dev, skb->len);
2429
2430         np->put_tx.ex = put_tx;
2431
2432         spin_unlock_irqrestore(&np->lock, flags);
2433
2434         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2435         return NETDEV_TX_OK;
2436 }
2437
2438 static inline void nv_tx_flip_ownership(struct net_device *dev)
2439 {
2440         struct fe_priv *np = netdev_priv(dev);
2441
2442         np->tx_pkts_in_progress--;
2443         if (np->tx_change_owner) {
2444                 np->tx_change_owner->first_tx_desc->flaglen |=
2445                         cpu_to_le32(NV_TX2_VALID);
2446                 np->tx_pkts_in_progress++;
2447
2448                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2449                 if (np->tx_change_owner == np->tx_end_flip)
2450                         np->tx_change_owner = NULL;
2451
2452                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2453         }
2454 }
2455
2456 /*
2457  * nv_tx_done: check for completed packets, release the skbs.
2458  *
2459  * Caller must own np->lock.
2460  */
2461 static int nv_tx_done(struct net_device *dev, int limit)
2462 {
2463         struct fe_priv *np = netdev_priv(dev);
2464         u32 flags;
2465         int tx_work = 0;
2466         struct ring_desc *orig_get_tx = np->get_tx.orig;
2467         unsigned int bytes_compl = 0;
2468
2469         while ((np->get_tx.orig != np->put_tx.orig) &&
2470                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2471                (tx_work < limit)) {
2472
2473                 nv_unmap_txskb(np, np->get_tx_ctx);
2474
2475                 if (np->desc_ver == DESC_VER_1) {
2476                         if (flags & NV_TX_LASTPACKET) {
2477                                 if (flags & NV_TX_ERROR) {
2478                                         if ((flags & NV_TX_RETRYERROR)
2479                                             && !(flags & NV_TX_RETRYCOUNT_MASK))
2480                                                 nv_legacybackoff_reseed(dev);
2481                                 } else {
2482                                         u64_stats_update_begin(&np->swstats_tx_syncp);
2483                                         np->stat_tx_packets++;
2484                                         np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2485                                         u64_stats_update_end(&np->swstats_tx_syncp);
2486                                 }
2487                                 bytes_compl += np->get_tx_ctx->skb->len;
2488                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2489                                 np->get_tx_ctx->skb = NULL;
2490                                 tx_work++;
2491                         }
2492                 } else {
2493                         if (flags & NV_TX2_LASTPACKET) {
2494                                 if (flags & NV_TX2_ERROR) {
2495                                         if ((flags & NV_TX2_RETRYERROR)
2496                                             && !(flags & NV_TX2_RETRYCOUNT_MASK))
2497                                                 nv_legacybackoff_reseed(dev);
2498                                 } else {
2499                                         u64_stats_update_begin(&np->swstats_tx_syncp);
2500                                         np->stat_tx_packets++;
2501                                         np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2502                                         u64_stats_update_end(&np->swstats_tx_syncp);
2503                                 }
2504                                 bytes_compl += np->get_tx_ctx->skb->len;
2505                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2506                                 np->get_tx_ctx->skb = NULL;
2507                                 tx_work++;
2508                         }
2509                 }
2510                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2511                         np->get_tx.orig = np->first_tx.orig;
2512                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2513                         np->get_tx_ctx = np->first_tx_ctx;
2514         }
2515
2516         netdev_completed_queue(np->dev, tx_work, bytes_compl);
2517
2518         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2519                 np->tx_stop = 0;
2520                 netif_wake_queue(dev);
2521         }
2522         return tx_work;
2523 }
2524
2525 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2526 {
2527         struct fe_priv *np = netdev_priv(dev);
2528         u32 flags;
2529         int tx_work = 0;
2530         struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2531         unsigned long bytes_cleaned = 0;
2532
2533         while ((np->get_tx.ex != np->put_tx.ex) &&
2534                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2535                (tx_work < limit)) {
2536
2537                 nv_unmap_txskb(np, np->get_tx_ctx);
2538
2539                 if (flags & NV_TX2_LASTPACKET) {
2540                         if (flags & NV_TX2_ERROR) {
2541                                 if ((flags & NV_TX2_RETRYERROR)
2542                                     && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2543                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2544                                                 nv_gear_backoff_reseed(dev);
2545                                         else
2546                                                 nv_legacybackoff_reseed(dev);
2547                                 }
2548                         } else {
2549                                 u64_stats_update_begin(&np->swstats_tx_syncp);
2550                                 np->stat_tx_packets++;
2551                                 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2552                                 u64_stats_update_end(&np->swstats_tx_syncp);
2553                         }
2554
2555                         bytes_cleaned += np->get_tx_ctx->skb->len;
2556                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2557                         np->get_tx_ctx->skb = NULL;
2558                         tx_work++;
2559
2560                         if (np->tx_limit)
2561                                 nv_tx_flip_ownership(dev);
2562                 }
2563
2564                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2565                         np->get_tx.ex = np->first_tx.ex;
2566                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2567                         np->get_tx_ctx = np->first_tx_ctx;
2568         }
2569
2570         netdev_completed_queue(np->dev, tx_work, bytes_cleaned);
2571
2572         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2573                 np->tx_stop = 0;
2574                 netif_wake_queue(dev);
2575         }
2576         return tx_work;
2577 }
2578
2579 /*
2580  * nv_tx_timeout: dev->tx_timeout function
2581  * Called with netif_tx_lock held.
2582  */
2583 static void nv_tx_timeout(struct net_device *dev)
2584 {
2585         struct fe_priv *np = netdev_priv(dev);
2586         u8 __iomem *base = get_hwbase(dev);
2587         u32 status;
2588         union ring_type put_tx;
2589         int saved_tx_limit;
2590
2591         if (np->msi_flags & NV_MSI_X_ENABLED)
2592                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2593         else
2594                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2595
2596         netdev_warn(dev, "Got tx_timeout. irq status: %08x\n", status);
2597
2598         if (unlikely(debug_tx_timeout)) {
2599                 int i;
2600
2601                 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2602                 netdev_info(dev, "Dumping tx registers\n");
2603                 for (i = 0; i <= np->register_size; i += 32) {
2604                         netdev_info(dev,
2605                                     "%3x: %08x %08x %08x %08x "
2606                                     "%08x %08x %08x %08x\n",
2607                                     i,
2608                                     readl(base + i + 0), readl(base + i + 4),
2609                                     readl(base + i + 8), readl(base + i + 12),
2610                                     readl(base + i + 16), readl(base + i + 20),
2611                                     readl(base + i + 24), readl(base + i + 28));
2612                 }
2613                 netdev_info(dev, "Dumping tx ring\n");
2614                 for (i = 0; i < np->tx_ring_size; i += 4) {
2615                         if (!nv_optimized(np)) {
2616                                 netdev_info(dev,
2617                                             "%03x: %08x %08x // %08x %08x "
2618                                             "// %08x %08x // %08x %08x\n",
2619                                             i,
2620                                             le32_to_cpu(np->tx_ring.orig[i].buf),
2621                                             le32_to_cpu(np->tx_ring.orig[i].flaglen),
2622                                             le32_to_cpu(np->tx_ring.orig[i+1].buf),
2623                                             le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2624                                             le32_to_cpu(np->tx_ring.orig[i+2].buf),
2625                                             le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2626                                             le32_to_cpu(np->tx_ring.orig[i+3].buf),
2627                                             le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2628                         } else {
2629                                 netdev_info(dev,
2630                                             "%03x: %08x %08x %08x "
2631                                             "// %08x %08x %08x "
2632                                             "// %08x %08x %08x "
2633                                             "// %08x %08x %08x\n",
2634                                             i,
2635                                             le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2636                                             le32_to_cpu(np->tx_ring.ex[i].buflow),
2637                                             le32_to_cpu(np->tx_ring.ex[i].flaglen),
2638                                             le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2639                                             le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2640                                             le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2641                                             le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2642                                             le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2643                                             le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2644                                             le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2645                                             le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2646                                             le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2647                         }
2648                 }
2649         }
2650
2651         spin_lock_irq(&np->lock);
2652
2653         /* 1) stop tx engine */
2654         nv_stop_tx(dev);
2655
2656         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2657         saved_tx_limit = np->tx_limit;
2658         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2659         np->tx_stop = 0;  /* prevent waking tx queue */
2660         if (!nv_optimized(np))
2661                 nv_tx_done(dev, np->tx_ring_size);
2662         else
2663                 nv_tx_done_optimized(dev, np->tx_ring_size);
2664
2665         /* save current HW position */
2666         if (np->tx_change_owner)
2667                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2668         else
2669                 put_tx = np->put_tx;
2670
2671         /* 3) clear all tx state */
2672         nv_drain_tx(dev);
2673         nv_init_tx(dev);
2674
2675         /* 4) restore state to current HW position */
2676         np->get_tx = np->put_tx = put_tx;
2677         np->tx_limit = saved_tx_limit;
2678
2679         /* 5) restart tx engine */
2680         nv_start_tx(dev);
2681         netif_wake_queue(dev);
2682         spin_unlock_irq(&np->lock);
2683 }
2684
2685 /*
2686  * Called when the nic notices a mismatch between the actual data len on the
2687  * wire and the len indicated in the 802 header
2688  */
2689 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2690 {
2691         int hdrlen;     /* length of the 802 header */
2692         int protolen;   /* length as stored in the proto field */
2693
2694         /* 1) calculate len according to header */
2695         if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2696                 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2697                 hdrlen = VLAN_HLEN;
2698         } else {
2699                 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2700                 hdrlen = ETH_HLEN;
2701         }
2702         if (protolen > ETH_DATA_LEN)
2703                 return datalen; /* Value in proto field not a len, no checks possible */
2704
2705         protolen += hdrlen;
2706         /* consistency checks: */
2707         if (datalen > ETH_ZLEN) {
2708                 if (datalen >= protolen) {
2709                         /* more data on wire than in 802 header, trim of
2710                          * additional data.
2711                          */
2712                         return protolen;
2713                 } else {
2714                         /* less data on wire than mentioned in header.
2715                          * Discard the packet.
2716                          */
2717                         return -1;
2718                 }
2719         } else {
2720                 /* short packet. Accept only if 802 values are also short */
2721                 if (protolen > ETH_ZLEN) {
2722                         return -1;
2723                 }
2724                 return datalen;
2725         }
2726 }
2727
2728 static int nv_rx_process(struct net_device *dev, int limit)
2729 {
2730         struct fe_priv *np = netdev_priv(dev);
2731         u32 flags;
2732         int rx_work = 0;
2733         struct sk_buff *skb;
2734         int len;
2735
2736         while ((np->get_rx.orig != np->put_rx.orig) &&
2737               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2738                 (rx_work < limit)) {
2739
2740                 /*
2741                  * the packet is for us - immediately tear down the pci mapping.
2742                  * TODO: check if a prefetch of the first cacheline improves
2743                  * the performance.
2744                  */
2745                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2746                                 np->get_rx_ctx->dma_len,
2747                                 PCI_DMA_FROMDEVICE);
2748                 skb = np->get_rx_ctx->skb;
2749                 np->get_rx_ctx->skb = NULL;
2750
2751                 /* look at what we actually got: */
2752                 if (np->desc_ver == DESC_VER_1) {
2753                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2754                                 len = flags & LEN_MASK_V1;
2755                                 if (unlikely(flags & NV_RX_ERROR)) {
2756                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2757                                                 len = nv_getlen(dev, skb->data, len);
2758                                                 if (len < 0) {
2759                                                         dev_kfree_skb(skb);
2760                                                         goto next_pkt;
2761                                                 }
2762                                         }
2763                                         /* framing errors are soft errors */
2764                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2765                                                 if (flags & NV_RX_SUBSTRACT1)
2766                                                         len--;
2767                                         }
2768                                         /* the rest are hard errors */
2769                                         else {
2770                                                 if (flags & NV_RX_MISSEDFRAME) {
2771                                                         u64_stats_update_begin(&np->swstats_rx_syncp);
2772                                                         np->stat_rx_missed_errors++;
2773                                                         u64_stats_update_end(&np->swstats_rx_syncp);
2774                                                 }
2775                                                 dev_kfree_skb(skb);
2776                                                 goto next_pkt;
2777                                         }
2778                                 }
2779                         } else {
2780                                 dev_kfree_skb(skb);
2781                                 goto next_pkt;
2782                         }
2783                 } else {
2784                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2785                                 len = flags & LEN_MASK_V2;
2786                                 if (unlikely(flags & NV_RX2_ERROR)) {
2787                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2788                                                 len = nv_getlen(dev, skb->data, len);
2789                                                 if (len < 0) {
2790                                                         dev_kfree_skb(skb);
2791                                                         goto next_pkt;
2792                                                 }
2793                                         }
2794                                         /* framing errors are soft errors */
2795                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2796                                                 if (flags & NV_RX2_SUBSTRACT1)
2797                                                         len--;
2798                                         }
2799                                         /* the rest are hard errors */
2800                                         else {
2801                                                 dev_kfree_skb(skb);
2802                                                 goto next_pkt;
2803                                         }
2804                                 }
2805                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2806                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2807                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2808                         } else {
2809                                 dev_kfree_skb(skb);
2810                                 goto next_pkt;
2811                         }
2812                 }
2813                 /* got a valid packet - forward it to the network core */
2814                 skb_put(skb, len);
2815                 skb->protocol = eth_type_trans(skb, dev);
2816                 napi_gro_receive(&np->napi, skb);
2817                 u64_stats_update_begin(&np->swstats_rx_syncp);
2818                 np->stat_rx_packets++;
2819                 np->stat_rx_bytes += len;
2820                 u64_stats_update_end(&np->swstats_rx_syncp);
2821 next_pkt:
2822                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2823                         np->get_rx.orig = np->first_rx.orig;
2824                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2825                         np->get_rx_ctx = np->first_rx_ctx;
2826
2827                 rx_work++;
2828         }
2829
2830         return rx_work;
2831 }
2832
2833 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2834 {
2835         struct fe_priv *np = netdev_priv(dev);
2836         u32 flags;
2837         u32 vlanflags = 0;
2838         int rx_work = 0;
2839         struct sk_buff *skb;
2840         int len;
2841
2842         while ((np->get_rx.ex != np->put_rx.ex) &&
2843               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2844               (rx_work < limit)) {
2845
2846                 /*
2847                  * the packet is for us - immediately tear down the pci mapping.
2848                  * TODO: check if a prefetch of the first cacheline improves
2849                  * the performance.
2850                  */
2851                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2852                                 np->get_rx_ctx->dma_len,
2853                                 PCI_DMA_FROMDEVICE);
2854                 skb = np->get_rx_ctx->skb;
2855                 np->get_rx_ctx->skb = NULL;
2856
2857                 /* look at what we actually got: */
2858                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2859                         len = flags & LEN_MASK_V2;
2860                         if (unlikely(flags & NV_RX2_ERROR)) {
2861                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2862                                         len = nv_getlen(dev, skb->data, len);
2863                                         if (len < 0) {
2864                                                 dev_kfree_skb(skb);
2865                                                 goto next_pkt;
2866                                         }
2867                                 }
2868                                 /* framing errors are soft errors */
2869                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2870                                         if (flags & NV_RX2_SUBSTRACT1)
2871                                                 len--;
2872                                 }
2873                                 /* the rest are hard errors */
2874                                 else {
2875                                         dev_kfree_skb(skb);
2876                                         goto next_pkt;
2877                                 }
2878                         }
2879
2880                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2881                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2882                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2883
2884                         /* got a valid packet - forward it to the network core */
2885                         skb_put(skb, len);
2886                         skb->protocol = eth_type_trans(skb, dev);
2887                         prefetch(skb->data);
2888
2889                         vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2890
2891                         /*
2892                          * There's need to check for NETIF_F_HW_VLAN_RX here.
2893                          * Even if vlan rx accel is disabled,
2894                          * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
2895                          */
2896                         if (dev->features & NETIF_F_HW_VLAN_RX &&
2897                             vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2898                                 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
2899
2900                                 __vlan_hwaccel_put_tag(skb, vid);
2901                         }
2902                         napi_gro_receive(&np->napi, skb);
2903                         u64_stats_update_begin(&np->swstats_rx_syncp);
2904                         np->stat_rx_packets++;
2905                         np->stat_rx_bytes += len;
2906                         u64_stats_update_end(&np->swstats_rx_syncp);
2907                 } else {
2908                         dev_kfree_skb(skb);
2909                 }
2910 next_pkt:
2911                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2912                         np->get_rx.ex = np->first_rx.ex;
2913                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2914                         np->get_rx_ctx = np->first_rx_ctx;
2915
2916                 rx_work++;
2917         }
2918
2919         return rx_work;
2920 }
2921
2922 static void set_bufsize(struct net_device *dev)
2923 {
2924         struct fe_priv *np = netdev_priv(dev);
2925
2926         if (dev->mtu <= ETH_DATA_LEN)
2927                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2928         else
2929                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2930 }
2931
2932 /*
2933  * nv_change_mtu: dev->change_mtu function
2934  * Called with dev_base_lock held for read.
2935  */
2936 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2937 {
2938         struct fe_priv *np = netdev_priv(dev);
2939         int old_mtu;
2940
2941         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2942                 return -EINVAL;
2943
2944         old_mtu = dev->mtu;
2945         dev->mtu = new_mtu;
2946
2947         /* return early if the buffer sizes will not change */
2948         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2949                 return 0;
2950         if (old_mtu == new_mtu)
2951                 return 0;
2952
2953         /* synchronized against open : rtnl_lock() held by caller */
2954         if (netif_running(dev)) {
2955                 u8 __iomem *base = get_hwbase(dev);
2956                 /*
2957                  * It seems that the nic preloads valid ring entries into an
2958                  * internal buffer. The procedure for flushing everything is
2959                  * guessed, there is probably a simpler approach.
2960                  * Changing the MTU is a rare event, it shouldn't matter.
2961                  */
2962                 nv_disable_irq(dev);
2963                 nv_napi_disable(dev);
2964                 netif_tx_lock_bh(dev);
2965                 netif_addr_lock(dev);
2966                 spin_lock(&np->lock);
2967                 /* stop engines */
2968                 nv_stop_rxtx(dev);
2969                 nv_txrx_reset(dev);
2970                 /* drain rx queue */
2971                 nv_drain_rxtx(dev);
2972                 /* reinit driver view of the rx queue */
2973                 set_bufsize(dev);
2974                 if (nv_init_ring(dev)) {
2975                         if (!np->in_shutdown)
2976                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2977                 }
2978                 /* reinit nic view of the rx queue */
2979                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2980                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2981                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2982                         base + NvRegRingSizes);
2983                 pci_push(base);
2984                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2985                 pci_push(base);
2986
2987                 /* restart rx engine */
2988                 nv_start_rxtx(dev);
2989                 spin_unlock(&np->lock);
2990                 netif_addr_unlock(dev);
2991                 netif_tx_unlock_bh(dev);
2992                 nv_napi_enable(dev);
2993                 nv_enable_irq(dev);
2994         }
2995         return 0;
2996 }
2997
2998 static void nv_copy_mac_to_hw(struct net_device *dev)
2999 {
3000         u8 __iomem *base = get_hwbase(dev);
3001         u32 mac[2];
3002
3003         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3004                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3005         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3006
3007         writel(mac[0], base + NvRegMacAddrA);
3008         writel(mac[1], base + NvRegMacAddrB);
3009 }
3010
3011 /*
3012  * nv_set_mac_address: dev->set_mac_address function
3013  * Called with rtnl_lock() held.
3014  */
3015 static int nv_set_mac_address(struct net_device *dev, void *addr)
3016 {
3017         struct fe_priv *np = netdev_priv(dev);
3018         struct sockaddr *macaddr = (struct sockaddr *)addr;
3019
3020         if (!is_valid_ether_addr(macaddr->sa_data))
3021                 return -EADDRNOTAVAIL;
3022
3023         /* synchronized against open : rtnl_lock() held by caller */
3024         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3025         dev->addr_assign_type &= ~NET_ADDR_RANDOM;
3026
3027         if (netif_running(dev)) {
3028                 netif_tx_lock_bh(dev);
3029                 netif_addr_lock(dev);
3030                 spin_lock_irq(&np->lock);
3031
3032                 /* stop rx engine */
3033                 nv_stop_rx(dev);
3034
3035                 /* set mac address */
3036                 nv_copy_mac_to_hw(dev);
3037
3038                 /* restart rx engine */
3039                 nv_start_rx(dev);
3040                 spin_unlock_irq(&np->lock);
3041                 netif_addr_unlock(dev);
3042                 netif_tx_unlock_bh(dev);
3043         } else {
3044                 nv_copy_mac_to_hw(dev);
3045         }
3046         return 0;
3047 }
3048
3049 /*
3050  * nv_set_multicast: dev->set_multicast function
3051  * Called with netif_tx_lock held.
3052  */
3053 static void nv_set_multicast(struct net_device *dev)
3054 {
3055         struct fe_priv *np = netdev_priv(dev);
3056         u8 __iomem *base = get_hwbase(dev);
3057         u32 addr[2];
3058         u32 mask[2];
3059         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3060
3061         memset(addr, 0, sizeof(addr));
3062         memset(mask, 0, sizeof(mask));
3063
3064         if (dev->flags & IFF_PROMISC) {
3065                 pff |= NVREG_PFF_PROMISC;
3066         } else {
3067                 pff |= NVREG_PFF_MYADDR;
3068
3069                 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3070                         u32 alwaysOff[2];
3071                         u32 alwaysOn[2];
3072
3073                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3074                         if (dev->flags & IFF_ALLMULTI) {
3075                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3076                         } else {
3077                                 struct netdev_hw_addr *ha;
3078
3079                                 netdev_for_each_mc_addr(ha, dev) {
3080                                         unsigned char *hw_addr = ha->addr;
3081                                         u32 a, b;
3082
3083                                         a = le32_to_cpu(*(__le32 *) hw_addr);
3084                                         b = le16_to_cpu(*(__le16 *) (&hw_addr[4]));
3085                                         alwaysOn[0] &= a;
3086                                         alwaysOff[0] &= ~a;
3087                                         alwaysOn[1] &= b;
3088                                         alwaysOff[1] &= ~b;
3089                                 }
3090                         }
3091                         addr[0] = alwaysOn[0];
3092                         addr[1] = alwaysOn[1];
3093                         mask[0] = alwaysOn[0] | alwaysOff[0];
3094                         mask[1] = alwaysOn[1] | alwaysOff[1];
3095                 } else {
3096                         mask[0] = NVREG_MCASTMASKA_NONE;
3097                         mask[1] = NVREG_MCASTMASKB_NONE;
3098                 }
3099         }
3100         addr[0] |= NVREG_MCASTADDRA_FORCE;
3101         pff |= NVREG_PFF_ALWAYS;
3102         spin_lock_irq(&np->lock);
3103         nv_stop_rx(dev);
3104         writel(addr[0], base + NvRegMulticastAddrA);
3105         writel(addr[1], base + NvRegMulticastAddrB);
3106         writel(mask[0], base + NvRegMulticastMaskA);
3107         writel(mask[1], base + NvRegMulticastMaskB);
3108         writel(pff, base + NvRegPacketFilterFlags);
3109         nv_start_rx(dev);
3110         spin_unlock_irq(&np->lock);
3111 }
3112
3113 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3114 {
3115         struct fe_priv *np = netdev_priv(dev);
3116         u8 __iomem *base = get_hwbase(dev);
3117
3118         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3119
3120         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3121                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3122                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3123                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3124                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3125                 } else {
3126                         writel(pff, base + NvRegPacketFilterFlags);
3127                 }
3128         }
3129         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3130                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3131                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3132                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3133                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3134                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3135                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3136                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3137                                 /* limit the number of tx pause frames to a default of 8 */
3138                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3139                         }
3140                         writel(pause_enable,  base + NvRegTxPauseFrame);
3141                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3142                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3143                 } else {
3144                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3145                         writel(regmisc, base + NvRegMisc1);
3146                 }
3147         }
3148 }
3149
3150 static void nv_force_linkspeed(struct net_device *dev, int speed, int duplex)
3151 {
3152         struct fe_priv *np = netdev_priv(dev);
3153         u8 __iomem *base = get_hwbase(dev);
3154         u32 phyreg, txreg;
3155         int mii_status;
3156
3157         np->linkspeed = NVREG_LINKSPEED_FORCE|speed;
3158         np->duplex = duplex;
3159
3160         /* see if gigabit phy */
3161         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3162         if (mii_status & PHY_GIGABIT) {
3163                 np->gigabit = PHY_GIGABIT;
3164                 phyreg = readl(base + NvRegSlotTime);
3165                 phyreg &= ~(0x3FF00);
3166                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
3167                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3168                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
3169                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3170                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3171                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3172                 writel(phyreg, base + NvRegSlotTime);
3173         }
3174
3175         phyreg = readl(base + NvRegPhyInterface);
3176         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3177         if (np->duplex == 0)
3178                 phyreg |= PHY_HALF;
3179         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3180                 phyreg |= PHY_100;
3181         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3182                                                         NVREG_LINKSPEED_1000)
3183                 phyreg |= PHY_1000;
3184         writel(phyreg, base + NvRegPhyInterface);
3185
3186         if (phyreg & PHY_RGMII) {
3187                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3188                                                         NVREG_LINKSPEED_1000)
3189                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3190                 else
3191                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3192         } else {
3193                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3194         }
3195         writel(txreg, base + NvRegTxDeferral);
3196
3197         if (np->desc_ver == DESC_VER_1) {
3198                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3199         } else {
3200                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3201                                          NVREG_LINKSPEED_1000)
3202                         txreg = NVREG_TX_WM_DESC2_3_1000;
3203                 else
3204                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3205         }
3206         writel(txreg, base + NvRegTxWatermark);
3207
3208         writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3209                         base + NvRegMisc1);
3210         pci_push(base);
3211         writel(np->linkspeed, base + NvRegLinkSpeed);
3212         pci_push(base);
3213
3214         return;
3215 }
3216
3217 /**
3218  * nv_update_linkspeed: Setup the MAC according to the link partner
3219  * @dev: Network device to be configured
3220  *
3221  * The function queries the PHY and checks if there is a link partner.
3222  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3223  * set to 10 MBit HD.
3224  *
3225  * The function returns 0 if there is no link partner and 1 if there is
3226  * a good link partner.
3227  */
3228 static int nv_update_linkspeed(struct net_device *dev)
3229 {
3230         struct fe_priv *np = netdev_priv(dev);
3231         u8 __iomem *base = get_hwbase(dev);
3232         int adv = 0;
3233         int lpa = 0;
3234         int adv_lpa, adv_pause, lpa_pause;
3235         int newls = np->linkspeed;
3236         int newdup = np->duplex;
3237         int mii_status;
3238         u32 bmcr;
3239         int retval = 0;
3240         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3241         u32 txrxFlags = 0;
3242         u32 phy_exp;
3243
3244         /* If device loopback is enabled, set carrier on and enable max link
3245          * speed.
3246          */
3247         bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3248         if (bmcr & BMCR_LOOPBACK) {
3249                 if (netif_running(dev)) {
3250                         nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, 1);
3251                         if (!netif_carrier_ok(dev))
3252                                 netif_carrier_on(dev);
3253                 }
3254                 return 1;
3255         }
3256
3257         /* BMSR_LSTATUS is latched, read it twice:
3258          * we want the current value.
3259          */
3260         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3261         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3262
3263         if (!(mii_status & BMSR_LSTATUS)) {
3264                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3265                 newdup = 0;
3266                 retval = 0;
3267                 goto set_speed;
3268         }
3269
3270         if (np->autoneg == 0) {
3271                 if (np->fixed_mode & LPA_100FULL) {
3272                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3273                         newdup = 1;
3274                 } else if (np->fixed_mode & LPA_100HALF) {
3275                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3276                         newdup = 0;
3277                 } else if (np->fixed_mode & LPA_10FULL) {
3278                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3279                         newdup = 1;
3280                 } else {
3281                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3282                         newdup = 0;
3283                 }
3284                 retval = 1;
3285                 goto set_speed;
3286         }
3287         /* check auto negotiation is complete */
3288         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3289                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3290                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3291                 newdup = 0;
3292                 retval = 0;
3293                 goto set_speed;
3294         }
3295
3296         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3297         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3298
3299         retval = 1;
3300         if (np->gigabit == PHY_GIGABIT) {
3301                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3302                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3303
3304                 if ((control_1000 & ADVERTISE_1000FULL) &&
3305                         (status_1000 & LPA_1000FULL)) {
3306                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3307                         newdup = 1;
3308                         goto set_speed;
3309                 }
3310         }
3311
3312         /* FIXME: handle parallel detection properly */
3313         adv_lpa = lpa & adv;
3314         if (adv_lpa & LPA_100FULL) {
3315                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3316                 newdup = 1;
3317         } else if (adv_lpa & LPA_100HALF) {
3318                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3319                 newdup = 0;
3320         } else if (adv_lpa & LPA_10FULL) {
3321                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3322                 newdup = 1;
3323         } else if (adv_lpa & LPA_10HALF) {
3324                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3325                 newdup = 0;
3326         } else {
3327                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3328                 newdup = 0;
3329         }
3330
3331 set_speed:
3332         if (np->duplex == newdup && np->linkspeed == newls)
3333                 return retval;
3334
3335         np->duplex = newdup;
3336         np->linkspeed = newls;
3337
3338         /* The transmitter and receiver must be restarted for safe update */
3339         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3340                 txrxFlags |= NV_RESTART_TX;
3341                 nv_stop_tx(dev);
3342         }
3343         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3344                 txrxFlags |= NV_RESTART_RX;
3345                 nv_stop_rx(dev);
3346         }
3347
3348         if (np->gigabit == PHY_GIGABIT) {
3349                 phyreg = readl(base + NvRegSlotTime);
3350                 phyreg &= ~(0x3FF00);
3351                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3352                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3353                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3354                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3355                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3356                 writel(phyreg, base + NvRegSlotTime);
3357         }
3358
3359         phyreg = readl(base + NvRegPhyInterface);
3360         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3361         if (np->duplex == 0)
3362                 phyreg |= PHY_HALF;
3363         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3364                 phyreg |= PHY_100;
3365         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3366                 phyreg |= PHY_1000;
3367         writel(phyreg, base + NvRegPhyInterface);
3368
3369         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3370         if (phyreg & PHY_RGMII) {
3371                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3372                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3373                 } else {
3374                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3375                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3376                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3377                                 else
3378                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3379                         } else {
3380                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3381                         }
3382                 }
3383         } else {
3384                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3385                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3386                 else
3387                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3388         }
3389         writel(txreg, base + NvRegTxDeferral);
3390
3391         if (np->desc_ver == DESC_VER_1) {
3392                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3393         } else {
3394                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3395                         txreg = NVREG_TX_WM_DESC2_3_1000;
3396                 else
3397                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3398         }
3399         writel(txreg, base + NvRegTxWatermark);
3400
3401         writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3402                 base + NvRegMisc1);
3403         pci_push(base);
3404         writel(np->linkspeed, base + NvRegLinkSpeed);
3405         pci_push(base);
3406
3407         pause_flags = 0;
3408         /* setup pause frame */
3409         if (np->duplex != 0) {
3410                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3411                         adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3412                         lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3413
3414                         switch (adv_pause) {
3415                         case ADVERTISE_PAUSE_CAP:
3416                                 if (lpa_pause & LPA_PAUSE_CAP) {
3417                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3418                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3419                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3420                                 }
3421                                 break;
3422                         case ADVERTISE_PAUSE_ASYM:
3423                                 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3424                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3425                                 break;
3426                         case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3427                                 if (lpa_pause & LPA_PAUSE_CAP) {
3428                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3429                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3430                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3431                                 }
3432                                 if (lpa_pause == LPA_PAUSE_ASYM)
3433                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3434                                 break;
3435                         }
3436                 } else {
3437                         pause_flags = np->pause_flags;
3438                 }
3439         }
3440         nv_update_pause(dev, pause_flags);
3441
3442         if (txrxFlags & NV_RESTART_TX)
3443                 nv_start_tx(dev);
3444         if (txrxFlags & NV_RESTART_RX)
3445                 nv_start_rx(dev);
3446
3447         return retval;
3448 }
3449
3450 static void nv_linkchange(struct net_device *dev)
3451 {
3452         if (nv_update_linkspeed(dev)) {
3453                 if (!netif_carrier_ok(dev)) {
3454                         netif_carrier_on(dev);
3455                         netdev_info(dev, "link up\n");
3456                         nv_txrx_gate(dev, false);
3457                         nv_start_rx(dev);
3458                 }
3459         } else {
3460                 if (netif_carrier_ok(dev)) {
3461                         netif_carrier_off(dev);
3462                         netdev_info(dev, "link down\n");
3463                         nv_txrx_gate(dev, true);
3464                         nv_stop_rx(dev);
3465                 }
3466         }
3467 }
3468
3469 static void nv_link_irq(struct net_device *dev)
3470 {
3471         u8 __iomem *base = get_hwbase(dev);
3472         u32 miistat;
3473
3474         miistat = readl(base + NvRegMIIStatus);
3475         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3476
3477         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3478                 nv_linkchange(dev);
3479 }
3480
3481 static void nv_msi_workaround(struct fe_priv *np)
3482 {
3483
3484         /* Need to toggle the msi irq mask within the ethernet device,
3485          * otherwise, future interrupts will not be detected.
3486          */
3487         if (np->msi_flags & NV_MSI_ENABLED) {
3488                 u8 __iomem *base = np->base;
3489
3490                 writel(0, base + NvRegMSIIrqMask);
3491                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3492         }
3493 }
3494
3495 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3496 {
3497         struct fe_priv *np = netdev_priv(dev);
3498
3499         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3500                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3501                         /* transition to poll based interrupts */
3502                         np->quiet_count = 0;
3503                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3504                                 np->irqmask = NVREG_IRQMASK_CPU;
3505                                 return 1;
3506                         }
3507                 } else {
3508                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3509                                 np->quiet_count++;
3510                         } else {
3511                                 /* reached a period of low activity, switch
3512                                    to per tx/rx packet interrupts */
3513                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3514                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3515                                         return 1;
3516                                 }
3517                         }
3518                 }
3519         }
3520         return 0;
3521 }
3522
3523 static irqreturn_t nv_nic_irq(int foo, void *data)
3524 {
3525         struct net_device *dev = (struct net_device *) data;
3526         struct fe_priv *np = netdev_priv(dev);
3527         u8 __iomem *base = get_hwbase(dev);
3528
3529         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3530                 np->events = readl(base + NvRegIrqStatus);
3531                 writel(np->events, base + NvRegIrqStatus);
3532         } else {
3533                 np->events = readl(base + NvRegMSIXIrqStatus);
3534                 writel(np->events, base + NvRegMSIXIrqStatus);
3535         }
3536         if (!(np->events & np->irqmask))
3537                 return IRQ_NONE;
3538
3539         nv_msi_workaround(np);
3540
3541         if (napi_schedule_prep(&np->napi)) {
3542                 /*
3543                  * Disable further irq's (msix not enabled with napi)
3544                  */
3545                 writel(0, base + NvRegIrqMask);
3546                 __napi_schedule(&np->napi);
3547         }
3548
3549         return IRQ_HANDLED;
3550 }
3551
3552 /**
3553  * All _optimized functions are used to help increase performance
3554  * (reduce CPU and increase throughput). They use descripter version 3,
3555  * compiler directives, and reduce memory accesses.
3556  */
3557 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3558 {
3559         struct net_device *dev = (struct net_device *) data;
3560         struct fe_priv *np = netdev_priv(dev);
3561         u8 __iomem *base = get_hwbase(dev);
3562
3563         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3564                 np->events = readl(base + NvRegIrqStatus);
3565                 writel(np->events, base + NvRegIrqStatus);
3566         } else {
3567                 np->events = readl(base + NvRegMSIXIrqStatus);
3568                 writel(np->events, base + NvRegMSIXIrqStatus);
3569         }
3570         if (!(np->events & np->irqmask))
3571                 return IRQ_NONE;
3572
3573         nv_msi_workaround(np);
3574
3575         if (napi_schedule_prep(&np->napi)) {
3576                 /*
3577                  * Disable further irq's (msix not enabled with napi)
3578                  */
3579                 writel(0, base + NvRegIrqMask);
3580                 __napi_schedule(&np->napi);
3581         }
3582
3583         return IRQ_HANDLED;
3584 }
3585
3586 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3587 {
3588         struct net_device *dev = (struct net_device *) data;
3589         struct fe_priv *np = netdev_priv(dev);
3590         u8 __iomem *base = get_hwbase(dev);
3591         u32 events;
3592         int i;
3593         unsigned long flags;
3594
3595         for (i = 0;; i++) {
3596                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3597                 writel(events, base + NvRegMSIXIrqStatus);
3598                 netdev_dbg(dev, "tx irq events: %08x\n", events);
3599                 if (!(events & np->irqmask))
3600                         break;
3601
3602                 spin_lock_irqsave(&np->lock, flags);
3603                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3604                 spin_unlock_irqrestore(&np->lock, flags);
3605
3606                 if (unlikely(i > max_interrupt_work)) {
3607                         spin_lock_irqsave(&np->lock, flags);
3608                         /* disable interrupts on the nic */
3609                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3610                         pci_push(base);
3611
3612                         if (!np->in_shutdown) {
3613                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3614                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3615                         }
3616                         spin_unlock_irqrestore(&np->lock, flags);
3617                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3618                                    __func__, i);
3619                         break;
3620                 }
3621
3622         }
3623
3624         return IRQ_RETVAL(i);
3625 }
3626
3627 static int nv_napi_poll(struct napi_struct *napi, int budget)
3628 {
3629         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3630         struct net_device *dev = np->dev;
3631         u8 __iomem *base = get_hwbase(dev);
3632         unsigned long flags;
3633         int retcode;
3634         int rx_count, tx_work = 0, rx_work = 0;
3635
3636         do {
3637                 if (!nv_optimized(np)) {
3638                         spin_lock_irqsave(&np->lock, flags);
3639                         tx_work += nv_tx_done(dev, np->tx_ring_size);
3640                         spin_unlock_irqrestore(&np->lock, flags);
3641
3642                         rx_count = nv_rx_process(dev, budget - rx_work);
3643                         retcode = nv_alloc_rx(dev);
3644                 } else {
3645                         spin_lock_irqsave(&np->lock, flags);
3646                         tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3647                         spin_unlock_irqrestore(&np->lock, flags);
3648
3649                         rx_count = nv_rx_process_optimized(dev,
3650                             budget - rx_work);
3651                         retcode = nv_alloc_rx_optimized(dev);
3652                 }
3653         } while (retcode == 0 &&
3654                  rx_count > 0 && (rx_work += rx_count) < budget);
3655
3656         if (retcode) {
3657                 spin_lock_irqsave(&np->lock, flags);
3658                 if (!np->in_shutdown)
3659                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3660                 spin_unlock_irqrestore(&np->lock, flags);
3661         }
3662
3663         nv_change_interrupt_mode(dev, tx_work + rx_work);
3664
3665         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3666                 spin_lock_irqsave(&np->lock, flags);
3667                 nv_link_irq(dev);
3668                 spin_unlock_irqrestore(&np->lock, flags);
3669         }
3670         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3671                 spin_lock_irqsave(&np->lock, flags);
3672                 nv_linkchange(dev);
3673                 spin_unlock_irqrestore(&np->lock, flags);
3674                 np->link_timeout = jiffies + LINK_TIMEOUT;
3675         }
3676         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3677                 spin_lock_irqsave(&np->lock, flags);
3678                 if (!np->in_shutdown) {
3679                         np->nic_poll_irq = np->irqmask;
3680                         np->recover_error = 1;
3681                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3682                 }
3683                 spin_unlock_irqrestore(&np->lock, flags);
3684                 napi_complete(napi);
3685                 return rx_work;
3686         }
3687
3688         if (rx_work < budget) {
3689                 /* re-enable interrupts
3690                    (msix not enabled in napi) */
3691                 napi_complete(napi);
3692
3693                 writel(np->irqmask, base + NvRegIrqMask);
3694         }
3695         return rx_work;
3696 }
3697
3698 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3699 {
3700         struct net_device *dev = (struct net_device *) data;
3701         struct fe_priv *np = netdev_priv(dev);
3702         u8 __iomem *base = get_hwbase(dev);
3703         u32 events;
3704         int i;
3705         unsigned long flags;
3706
3707         for (i = 0;; i++) {
3708                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3709                 writel(events, base + NvRegMSIXIrqStatus);
3710                 netdev_dbg(dev, "rx irq events: %08x\n", events);
3711                 if (!(events & np->irqmask))
3712                         break;
3713
3714                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3715                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3716                                 spin_lock_irqsave(&np->lock, flags);
3717                                 if (!np->in_shutdown)
3718                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3719                                 spin_unlock_irqrestore(&np->lock, flags);
3720                         }
3721                 }
3722
3723                 if (unlikely(i > max_interrupt_work)) {
3724                         spin_lock_irqsave(&np->lock, flags);
3725                         /* disable interrupts on the nic */
3726                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3727                         pci_push(base);
3728
3729                         if (!np->in_shutdown) {
3730                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3731                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3732                         }
3733                         spin_unlock_irqrestore(&np->lock, flags);
3734                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3735                                    __func__, i);
3736                         break;
3737                 }
3738         }
3739
3740         return IRQ_RETVAL(i);
3741 }
3742
3743 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3744 {
3745         struct net_device *dev = (struct net_device *) data;
3746         struct fe_priv *np = netdev_priv(dev);
3747         u8 __iomem *base = get_hwbase(dev);
3748         u32 events;
3749         int i;
3750         unsigned long flags;
3751
3752         for (i = 0;; i++) {
3753                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3754                 writel(events, base + NvRegMSIXIrqStatus);
3755                 netdev_dbg(dev, "irq events: %08x\n", events);
3756                 if (!(events & np->irqmask))
3757                         break;
3758
3759                 /* check tx in case we reached max loop limit in tx isr */
3760                 spin_lock_irqsave(&np->lock, flags);
3761                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3762                 spin_unlock_irqrestore(&np->lock, flags);
3763
3764                 if (events & NVREG_IRQ_LINK) {
3765                         spin_lock_irqsave(&np->lock, flags);
3766                         nv_link_irq(dev);
3767                         spin_unlock_irqrestore(&np->lock, flags);
3768                 }
3769                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3770                         spin_lock_irqsave(&np->lock, flags);
3771                         nv_linkchange(dev);
3772                         spin_unlock_irqrestore(&np->lock, flags);
3773                         np->link_timeout = jiffies + LINK_TIMEOUT;
3774                 }
3775                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3776                         spin_lock_irq(&np->lock);
3777                         /* disable interrupts on the nic */
3778                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3779                         pci_push(base);
3780
3781                         if (!np->in_shutdown) {
3782                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3783                                 np->recover_error = 1;
3784                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3785                         }
3786                         spin_unlock_irq(&np->lock);
3787                         break;
3788                 }
3789                 if (unlikely(i > max_interrupt_work)) {
3790                         spin_lock_irqsave(&np->lock, flags);
3791                         /* disable interrupts on the nic */
3792                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3793                         pci_push(base);
3794
3795                         if (!np->in_shutdown) {
3796                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3797                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3798                         }
3799                         spin_unlock_irqrestore(&np->lock, flags);
3800                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3801                                    __func__, i);
3802                         break;
3803                 }
3804
3805         }
3806
3807         return IRQ_RETVAL(i);
3808 }
3809
3810 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3811 {
3812         struct net_device *dev = (struct net_device *) data;
3813         struct fe_priv *np = netdev_priv(dev);
3814         u8 __iomem *base = get_hwbase(dev);
3815         u32 events;
3816
3817         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3818                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3819                 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3820         } else {
3821                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3822                 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3823         }
3824         pci_push(base);
3825         if (!(events & NVREG_IRQ_TIMER))
3826                 return IRQ_RETVAL(0);
3827
3828         nv_msi_workaround(np);
3829
3830         spin_lock(&np->lock);
3831         np->intr_test = 1;
3832         spin_unlock(&np->lock);
3833
3834         return IRQ_RETVAL(1);
3835 }
3836
3837 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3838 {
3839         u8 __iomem *base = get_hwbase(dev);
3840         int i;
3841         u32 msixmap = 0;
3842
3843         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3844          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3845          * the remaining 8 interrupts.
3846          */
3847         for (i = 0; i < 8; i++) {
3848                 if ((irqmask >> i) & 0x1)
3849                         msixmap |= vector << (i << 2);
3850         }
3851         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3852
3853         msixmap = 0;
3854         for (i = 0; i < 8; i++) {
3855                 if ((irqmask >> (i + 8)) & 0x1)
3856                         msixmap |= vector << (i << 2);
3857         }
3858         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3859 }
3860
3861 static int nv_request_irq(struct net_device *dev, int intr_test)
3862 {
3863         struct fe_priv *np = get_nvpriv(dev);
3864         u8 __iomem *base = get_hwbase(dev);
3865         int ret = 1;
3866         int i;
3867         irqreturn_t (*handler)(int foo, void *data);
3868
3869         if (intr_test) {
3870                 handler = nv_nic_irq_test;
3871         } else {
3872                 if (nv_optimized(np))
3873                         handler = nv_nic_irq_optimized;
3874                 else
3875                         handler = nv_nic_irq;
3876         }
3877
3878         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3879                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3880                         np->msi_x_entry[i].entry = i;
3881                 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3882                 if (ret == 0) {
3883                         np->msi_flags |= NV_MSI_X_ENABLED;
3884                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3885                                 /* Request irq for rx handling */
3886                                 sprintf(np->name_rx, "%s-rx", dev->name);
3887                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3888                                                 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3889                                         netdev_info(dev,
3890                                                     "request_irq failed for rx %d\n",
3891                                                     ret);
3892                                         pci_disable_msix(np->pci_dev);
3893                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3894                                         goto out_err;
3895                                 }
3896                                 /* Request irq for tx handling */
3897                                 sprintf(np->name_tx, "%s-tx", dev->name);
3898                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3899                                                 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3900                                         netdev_info(dev,
3901                                                     "request_irq failed for tx %d\n",
3902                                                     ret);
3903                                         pci_disable_msix(np->pci_dev);
3904                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3905                                         goto out_free_rx;
3906                                 }
3907                                 /* Request irq for link and timer handling */
3908                                 sprintf(np->name_other, "%s-other", dev->name);
3909                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3910                                                 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3911                                         netdev_info(dev,
3912                                                     "request_irq failed for link %d\n",
3913                                                     ret);
3914                                         pci_disable_msix(np->pci_dev);
3915                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3916                                         goto out_free_tx;
3917                                 }
3918                                 /* map interrupts to their respective vector */
3919                                 writel(0, base + NvRegMSIXMap0);
3920                                 writel(0, base + NvRegMSIXMap1);
3921                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3922                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3923                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3924                         } else {
3925                                 /* Request irq for all interrupts */
3926                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3927                                         netdev_info(dev,
3928                                                     "request_irq failed %d\n",
3929                                                     ret);
3930                                         pci_disable_msix(np->pci_dev);
3931                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3932                                         goto out_err;
3933                                 }
3934
3935                                 /* map interrupts to vector 0 */
3936                                 writel(0, base + NvRegMSIXMap0);
3937                                 writel(0, base + NvRegMSIXMap1);
3938                         }
3939                         netdev_info(dev, "MSI-X enabled\n");
3940                 }
3941         }
3942         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3943                 ret = pci_enable_msi(np->pci_dev);
3944                 if (ret == 0) {
3945                         np->msi_flags |= NV_MSI_ENABLED;
3946                         dev->irq = np->pci_dev->irq;
3947                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3948                                 netdev_info(dev, "request_irq failed %d\n",
3949                                             ret);
3950                                 pci_disable_msi(np->pci_dev);
3951                                 np->msi_flags &= ~NV_MSI_ENABLED;
3952                                 dev->irq = np->pci_dev->irq;
3953                                 goto out_err;
3954                         }
3955
3956                         /* map interrupts to vector 0 */
3957                         writel(0, base + NvRegMSIMap0);
3958                         writel(0, base + NvRegMSIMap1);
3959                         /* enable msi vector 0 */
3960                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3961                         netdev_info(dev, "MSI enabled\n");
3962                 }
3963         }
3964         if (ret != 0) {
3965                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3966                         goto out_err;
3967
3968         }
3969
3970         return 0;
3971 out_free_tx:
3972         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3973 out_free_rx:
3974         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3975 out_err:
3976         return 1;
3977 }
3978
3979 static void nv_free_irq(struct net_device *dev)
3980 {
3981         struct fe_priv *np = get_nvpriv(dev);
3982         int i;
3983
3984         if (np->msi_flags & NV_MSI_X_ENABLED) {
3985                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3986                         free_irq(np->msi_x_entry[i].vector, dev);
3987                 pci_disable_msix(np->pci_dev);
3988                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3989         } else {
3990                 free_irq(np->pci_dev->irq, dev);
3991                 if (np->msi_flags & NV_MSI_ENABLED) {
3992                         pci_disable_msi(np->pci_dev);
3993                         np->msi_flags &= ~NV_MSI_ENABLED;
3994                 }
3995         }
3996 }
3997
3998 static void nv_do_nic_poll(unsigned long data)
3999 {
4000         struct net_device *dev = (struct net_device *) data;
4001         struct fe_priv *np = netdev_priv(dev);
4002         u8 __iomem *base = get_hwbase(dev);
4003         u32 mask = 0;
4004
4005         /*
4006          * First disable irq(s) and then
4007          * reenable interrupts on the nic, we have to do this before calling
4008          * nv_nic_irq because that may decide to do otherwise
4009          */
4010
4011         if (!using_multi_irqs(dev)) {
4012                 if (np->msi_flags & NV_MSI_X_ENABLED)
4013                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4014                 else
4015                         disable_irq_lockdep(np->pci_dev->irq);
4016                 mask = np->irqmask;
4017         } else {
4018                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4019                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4020                         mask |= NVREG_IRQ_RX_ALL;
4021                 }
4022                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4023                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4024                         mask |= NVREG_IRQ_TX_ALL;
4025                 }
4026                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4027                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4028                         mask |= NVREG_IRQ_OTHER;
4029                 }
4030         }
4031         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4032
4033         if (np->recover_error) {
4034                 np->recover_error = 0;
4035                 netdev_info(dev, "MAC in recoverable error state\n");
4036                 if (netif_running(dev)) {
4037                         netif_tx_lock_bh(dev);
4038                         netif_addr_lock(dev);
4039                         spin_lock(&np->lock);
4040                         /* stop engines */
4041                         nv_stop_rxtx(dev);
4042                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4043                                 nv_mac_reset(dev);
4044                         nv_txrx_reset(dev);
4045                         /* drain rx queue */
4046                         nv_drain_rxtx(dev);
4047                         /* reinit driver view of the rx queue */
4048                         set_bufsize(dev);
4049                         if (nv_init_ring(dev)) {
4050                                 if (!np->in_shutdown)
4051                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4052                         }
4053                         /* reinit nic view of the rx queue */
4054                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4055                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4056                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4057                                 base + NvRegRingSizes);
4058                         pci_push(base);
4059                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4060                         pci_push(base);
4061                         /* clear interrupts */
4062                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4063                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4064                         else
4065                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4066
4067                         /* restart rx engine */
4068                         nv_start_rxtx(dev);
4069                         spin_unlock(&np->lock);
4070                         netif_addr_unlock(dev);
4071                         netif_tx_unlock_bh(dev);
4072                 }
4073         }
4074
4075         writel(mask, base + NvRegIrqMask);
4076         pci_push(base);
4077
4078         if (!using_multi_irqs(dev)) {
4079                 np->nic_poll_irq = 0;
4080                 if (nv_optimized(np))
4081                         nv_nic_irq_optimized(0, dev);
4082                 else
4083                         nv_nic_irq(0, dev);
4084                 if (np->msi_flags & NV_MSI_X_ENABLED)
4085                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4086                 else
4087                         enable_irq_lockdep(np->pci_dev->irq);
4088         } else {
4089                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4090                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4091                         nv_nic_irq_rx(0, dev);
4092                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4093                 }
4094                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4095                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4096                         nv_nic_irq_tx(0, dev);
4097                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4098                 }
4099                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4100                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4101                         nv_nic_irq_other(0, dev);
4102                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4103                 }
4104         }
4105
4106 }
4107
4108 #ifdef CONFIG_NET_POLL_CONTROLLER
4109 static void nv_poll_controller(struct net_device *dev)
4110 {
4111         nv_do_nic_poll((unsigned long) dev);
4112 }
4113 #endif
4114
4115 static void nv_do_stats_poll(unsigned long data)
4116         __acquires(&netdev_priv(dev)->hwstats_lock)
4117         __releases(&netdev_priv(dev)->hwstats_lock)
4118 {
4119         struct net_device *dev = (struct net_device *) data;
4120         struct fe_priv *np = netdev_priv(dev);
4121
4122         /* If lock is currently taken, the stats are being refreshed
4123          * and hence fresh enough */
4124         if (spin_trylock(&np->hwstats_lock)) {
4125                 nv_update_stats(dev);
4126                 spin_unlock(&np->hwstats_lock);
4127         }
4128
4129         if (!np->in_shutdown)
4130                 mod_timer(&np->stats_poll,
4131                         round_jiffies(jiffies + STATS_INTERVAL));
4132 }
4133
4134 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4135 {
4136         struct fe_priv *np = netdev_priv(dev);
4137         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
4138         strlcpy(info->version, FORCEDETH_VERSION, sizeof(info->version));
4139         strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
4140 }
4141
4142 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4143 {
4144         struct fe_priv *np = netdev_priv(dev);
4145         wolinfo->supported = WAKE_MAGIC;
4146
4147         spin_lock_irq(&np->lock);
4148         if (np->wolenabled)
4149                 wolinfo->wolopts = WAKE_MAGIC;
4150         spin_unlock_irq(&np->lock);
4151 }
4152
4153 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4154 {
4155         struct fe_priv *np = netdev_priv(dev);
4156         u8 __iomem *base = get_hwbase(dev);
4157         u32 flags = 0;
4158
4159         if (wolinfo->wolopts == 0) {
4160                 np->wolenabled = 0;
4161         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4162                 np->wolenabled = 1;
4163                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4164         }
4165         if (netif_running(dev)) {
4166                 spin_lock_irq(&np->lock);
4167                 writel(flags, base + NvRegWakeUpFlags);
4168                 spin_unlock_irq(&np->lock);
4169         }
4170         device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
4171         return 0;
4172 }
4173
4174 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4175 {
4176         struct fe_priv *np = netdev_priv(dev);
4177         u32 speed;
4178         int adv;
4179
4180         spin_lock_irq(&np->lock);
4181         ecmd->port = PORT_MII;
4182         if (!netif_running(dev)) {
4183                 /* We do not track link speed / duplex setting if the
4184                  * interface is disabled. Force a link check */
4185                 if (nv_update_linkspeed(dev)) {
4186                         if (!netif_carrier_ok(dev))
4187                                 netif_carrier_on(dev);
4188                 } else {
4189                         if (netif_carrier_ok(dev))
4190                                 netif_carrier_off(dev);
4191                 }
4192         }
4193
4194         if (netif_carrier_ok(dev)) {
4195                 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4196                 case NVREG_LINKSPEED_10:
4197                         speed = SPEED_10;
4198                         break;
4199                 case NVREG_LINKSPEED_100:
4200                         speed = SPEED_100;
4201                         break;
4202                 case NVREG_LINKSPEED_1000:
4203                         speed = SPEED_1000;
4204                         break;
4205                 default:
4206                         speed = -1;
4207                         break;
4208                 }
4209                 ecmd->duplex = DUPLEX_HALF;
4210                 if (np->duplex)
4211                         ecmd->duplex = DUPLEX_FULL;
4212         } else {
4213                 speed = -1;
4214                 ecmd->duplex = -1;
4215         }
4216         ethtool_cmd_speed_set(ecmd, speed);
4217         ecmd->autoneg = np->autoneg;
4218
4219         ecmd->advertising = ADVERTISED_MII;
4220         if (np->autoneg) {
4221                 ecmd->advertising |= ADVERTISED_Autoneg;
4222                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4223                 if (adv & ADVERTISE_10HALF)
4224                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4225                 if (adv & ADVERTISE_10FULL)
4226                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4227                 if (adv & ADVERTISE_100HALF)
4228                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4229                 if (adv & ADVERTISE_100FULL)
4230                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4231                 if (np->gigabit == PHY_GIGABIT) {
4232                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4233                         if (adv & ADVERTISE_1000FULL)
4234                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4235                 }
4236         }
4237         ecmd->supported = (SUPPORTED_Autoneg |
4238                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4239                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4240                 SUPPORTED_MII);
4241         if (np->gigabit == PHY_GIGABIT)
4242                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4243
4244         ecmd->phy_address = np->phyaddr;
4245         ecmd->transceiver = XCVR_EXTERNAL;
4246
4247         /* ignore maxtxpkt, maxrxpkt for now */
4248         spin_unlock_irq(&np->lock);
4249         return 0;
4250 }
4251
4252 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4253 {
4254         struct fe_priv *np = netdev_priv(dev);
4255         u32 speed = ethtool_cmd_speed(ecmd);
4256
4257         if (ecmd->port != PORT_MII)
4258                 return -EINVAL;
4259         if (ecmd->transceiver != XCVR_EXTERNAL)
4260                 return -EINVAL;
4261         if (ecmd->phy_address != np->phyaddr) {
4262                 /* TODO: support switching between multiple phys. Should be
4263                  * trivial, but not enabled due to lack of test hardware. */
4264                 return -EINVAL;
4265         }
4266         if (ecmd->autoneg == AUTONEG_ENABLE) {
4267                 u32 mask;
4268
4269                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4270                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4271                 if (np->gigabit == PHY_GIGABIT)
4272                         mask |= ADVERTISED_1000baseT_Full;
4273
4274                 if ((ecmd->advertising & mask) == 0)
4275                         return -EINVAL;
4276
4277         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4278                 /* Note: autonegotiation disable, speed 1000 intentionally
4279                  * forbidden - no one should need that. */
4280
4281                 if (speed != SPEED_10 && speed != SPEED_100)
4282                         return -EINVAL;
4283                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4284                         return -EINVAL;
4285         } else {
4286                 return -EINVAL;
4287         }
4288
4289         netif_carrier_off(dev);
4290         if (netif_running(dev)) {
4291                 unsigned long flags;
4292
4293                 nv_disable_irq(dev);
4294                 netif_tx_lock_bh(dev);
4295                 netif_addr_lock(dev);
4296                 /* with plain spinlock lockdep complains */
4297                 spin_lock_irqsave(&np->lock, flags);
4298                 /* stop engines */
4299                 /* FIXME:
4300                  * this can take some time, and interrupts are disabled
4301                  * due to spin_lock_irqsave, but let's hope no daemon
4302                  * is going to change the settings very often...
4303                  * Worst case:
4304                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4305                  * + some minor delays, which is up to a second approximately
4306                  */
4307                 nv_stop_rxtx(dev);
4308                 spin_unlock_irqrestore(&np->lock, flags);
4309                 netif_addr_unlock(dev);
4310                 netif_tx_unlock_bh(dev);
4311         }
4312
4313         if (ecmd->autoneg == AUTONEG_ENABLE) {
4314                 int adv, bmcr;
4315
4316                 np->autoneg = 1;
4317
4318                 /* advertise only what has been requested */
4319                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4320                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4321                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4322                         adv |= ADVERTISE_10HALF;
4323                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4324                         adv |= ADVERTISE_10FULL;
4325                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4326                         adv |= ADVERTISE_100HALF;
4327                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4328                         adv |= ADVERTISE_100FULL;
4329                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisements but disable tx pause */
4330                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4331                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4332                         adv |=  ADVERTISE_PAUSE_ASYM;
4333                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4334
4335                 if (np->gigabit == PHY_GIGABIT) {
4336                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4337                         adv &= ~ADVERTISE_1000FULL;
4338                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4339                                 adv |= ADVERTISE_1000FULL;
4340                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4341                 }
4342
4343                 if (netif_running(dev))
4344                         netdev_info(dev, "link down\n");
4345                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4346                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4347                         bmcr |= BMCR_ANENABLE;
4348                         /* reset the phy in order for settings to stick,
4349                          * and cause autoneg to start */
4350                         if (phy_reset(dev, bmcr)) {
4351                                 netdev_info(dev, "phy reset failed\n");
4352                                 return -EINVAL;
4353                         }
4354                 } else {
4355                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4356                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4357                 }
4358         } else {
4359                 int adv, bmcr;
4360
4361                 np->autoneg = 0;
4362
4363                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4364                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4365                 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4366                         adv |= ADVERTISE_10HALF;
4367                 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4368                         adv |= ADVERTISE_10FULL;
4369                 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4370                         adv |= ADVERTISE_100HALF;
4371                 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4372                         adv |= ADVERTISE_100FULL;
4373                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4374                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4375                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4376                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4377                 }
4378                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4379                         adv |=  ADVERTISE_PAUSE_ASYM;
4380                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4381                 }
4382                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4383                 np->fixed_mode = adv;
4384
4385                 if (np->gigabit == PHY_GIGABIT) {
4386                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4387                         adv &= ~ADVERTISE_1000FULL;
4388                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4389                 }
4390
4391                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4392                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4393                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4394                         bmcr |= BMCR_FULLDPLX;
4395                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4396                         bmcr |= BMCR_SPEED100;
4397                 if (np->phy_oui == PHY_OUI_MARVELL) {
4398                         /* reset the phy in order for forced mode settings to stick */
4399                         if (phy_reset(dev, bmcr)) {
4400                                 netdev_info(dev, "phy reset failed\n");
4401                                 return -EINVAL;
4402                         }
4403                 } else {
4404                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4405                         if (netif_running(dev)) {
4406                                 /* Wait a bit and then reconfigure the nic. */
4407                                 udelay(10);
4408                                 nv_linkchange(dev);
4409                         }
4410                 }
4411         }
4412
4413         if (netif_running(dev)) {
4414                 nv_start_rxtx(dev);
4415                 nv_enable_irq(dev);
4416         }
4417
4418         return 0;
4419 }
4420
4421 #define FORCEDETH_REGS_VER      1
4422
4423 static int nv_get_regs_len(struct net_device *dev)
4424 {
4425         struct fe_priv *np = netdev_priv(dev);
4426         return np->register_size;
4427 }
4428
4429 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4430 {
4431         struct fe_priv *np = netdev_priv(dev);
4432         u8 __iomem *base = get_hwbase(dev);
4433         u32 *rbuf = buf;
4434         int i;
4435
4436         regs->version = FORCEDETH_REGS_VER;
4437         spin_lock_irq(&np->lock);
4438         for (i = 0; i <= np->register_size/sizeof(u32); i++)
4439                 rbuf[i] = readl(base + i*sizeof(u32));
4440         spin_unlock_irq(&np->lock);
4441 }
4442
4443 static int nv_nway_reset(struct net_device *dev)
4444 {
4445         struct fe_priv *np = netdev_priv(dev);
4446         int ret;
4447
4448         if (np->autoneg) {
4449                 int bmcr;
4450
4451                 netif_carrier_off(dev);
4452                 if (netif_running(dev)) {
4453                         nv_disable_irq(dev);
4454                         netif_tx_lock_bh(dev);
4455                         netif_addr_lock(dev);
4456                         spin_lock(&np->lock);
4457                         /* stop engines */
4458                         nv_stop_rxtx(dev);
4459                         spin_unlock(&np->lock);
4460                         netif_addr_unlock(dev);
4461                         netif_tx_unlock_bh(dev);
4462                         netdev_info(dev, "link down\n");
4463                 }
4464
4465                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4466                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4467                         bmcr |= BMCR_ANENABLE;
4468                         /* reset the phy in order for settings to stick*/
4469                         if (phy_reset(dev, bmcr)) {
4470                                 netdev_info(dev, "phy reset failed\n");
4471                                 return -EINVAL;
4472                         }
4473                 } else {
4474                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4475                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4476                 }
4477
4478                 if (netif_running(dev)) {
4479                         nv_start_rxtx(dev);
4480                         nv_enable_irq(dev);
4481                 }
4482                 ret = 0;
4483         } else {
4484                 ret = -EINVAL;
4485         }
4486
4487         return ret;
4488 }
4489
4490 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4491 {
4492         struct fe_priv *np = netdev_priv(dev);
4493
4494         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4495         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4496
4497         ring->rx_pending = np->rx_ring_size;
4498         ring->tx_pending = np->tx_ring_size;
4499 }
4500
4501 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4502 {
4503         struct fe_priv *np = netdev_priv(dev);
4504         u8 __iomem *base = get_hwbase(dev);
4505         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4506         dma_addr_t ring_addr;
4507
4508         if (ring->rx_pending < RX_RING_MIN ||
4509             ring->tx_pending < TX_RING_MIN ||
4510             ring->rx_mini_pending != 0 ||
4511             ring->rx_jumbo_pending != 0 ||
4512             (np->desc_ver == DESC_VER_1 &&
4513              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4514               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4515             (np->desc_ver != DESC_VER_1 &&
4516              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4517               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4518                 return -EINVAL;
4519         }
4520
4521         /* allocate new rings */
4522         if (!nv_optimized(np)) {
4523                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4524                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4525                                             &ring_addr);
4526         } else {
4527                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4528                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4529                                             &ring_addr);
4530         }
4531         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4532         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4533         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4534                 /* fall back to old rings */
4535                 if (!nv_optimized(np)) {
4536                         if (rxtx_ring)
4537                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4538                                                     rxtx_ring, ring_addr);
4539                 } else {
4540                         if (rxtx_ring)
4541                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4542                                                     rxtx_ring, ring_addr);
4543                 }
4544
4545                 kfree(rx_skbuff);
4546                 kfree(tx_skbuff);
4547                 goto exit;
4548         }
4549
4550         if (netif_running(dev)) {
4551                 nv_disable_irq(dev);
4552                 nv_napi_disable(dev);
4553                 netif_tx_lock_bh(dev);
4554                 netif_addr_lock(dev);
4555                 spin_lock(&np->lock);
4556                 /* stop engines */
4557                 nv_stop_rxtx(dev);
4558                 nv_txrx_reset(dev);
4559                 /* drain queues */
4560                 nv_drain_rxtx(dev);
4561                 /* delete queues */
4562                 free_rings(dev);
4563         }
4564
4565         /* set new values */
4566         np->rx_ring_size = ring->rx_pending;
4567         np->tx_ring_size = ring->tx_pending;
4568
4569         if (!nv_optimized(np)) {
4570                 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4571                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4572         } else {
4573                 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4574                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4575         }
4576         np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4577         np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4578         np->ring_addr = ring_addr;
4579
4580         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4581         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4582
4583         if (netif_running(dev)) {
4584                 /* reinit driver view of the queues */
4585                 set_bufsize(dev);
4586                 if (nv_init_ring(dev)) {
4587                         if (!np->in_shutdown)
4588                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4589                 }
4590
4591                 /* reinit nic view of the queues */
4592                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4593                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4594                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4595                         base + NvRegRingSizes);
4596                 pci_push(base);
4597                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4598                 pci_push(base);
4599
4600                 /* restart engines */
4601                 nv_start_rxtx(dev);
4602                 spin_unlock(&np->lock);
4603                 netif_addr_unlock(dev);
4604                 netif_tx_unlock_bh(dev);
4605                 nv_napi_enable(dev);
4606                 nv_enable_irq(dev);
4607         }
4608         return 0;
4609 exit:
4610         return -ENOMEM;
4611 }
4612
4613 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4614 {
4615         struct fe_priv *np = netdev_priv(dev);
4616
4617         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4618         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4619         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4620 }
4621
4622 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4623 {
4624         struct fe_priv *np = netdev_priv(dev);
4625         int adv, bmcr;
4626
4627         if ((!np->autoneg && np->duplex == 0) ||
4628             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4629                 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4630                 return -EINVAL;
4631         }
4632         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4633                 netdev_info(dev, "hardware does not support tx pause frames\n");
4634                 return -EINVAL;
4635         }
4636
4637         netif_carrier_off(dev);
4638         if (netif_running(dev)) {
4639                 nv_disable_irq(dev);
4640                 netif_tx_lock_bh(dev);
4641                 netif_addr_lock(dev);
4642                 spin_lock(&np->lock);
4643                 /* stop engines */
4644                 nv_stop_rxtx(dev);
4645                 spin_unlock(&np->lock);
4646                 netif_addr_unlock(dev);
4647                 netif_tx_unlock_bh(dev);
4648         }
4649
4650         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4651         if (pause->rx_pause)
4652                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4653         if (pause->tx_pause)
4654                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4655
4656         if (np->autoneg && pause->autoneg) {
4657                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4658
4659                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4660                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4661                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4662                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4663                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4664                         adv |=  ADVERTISE_PAUSE_ASYM;
4665                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4666
4667                 if (netif_running(dev))
4668                         netdev_info(dev, "link down\n");
4669                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4670                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4671                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4672         } else {
4673                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4674                 if (pause->rx_pause)
4675                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4676                 if (pause->tx_pause)
4677                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4678
4679                 if (!netif_running(dev))
4680                         nv_update_linkspeed(dev);
4681                 else
4682                         nv_update_pause(dev, np->pause_flags);
4683         }
4684
4685         if (netif_running(dev)) {
4686                 nv_start_rxtx(dev);
4687                 nv_enable_irq(dev);
4688         }
4689         return 0;
4690 }
4691
4692 static int nv_set_loopback(struct net_device *dev, netdev_features_t features)
4693 {
4694         struct fe_priv *np = netdev_priv(dev);
4695         unsigned long flags;
4696         u32 miicontrol;
4697         int err, retval = 0;
4698
4699         spin_lock_irqsave(&np->lock, flags);
4700         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4701         if (features & NETIF_F_LOOPBACK) {
4702                 if (miicontrol & BMCR_LOOPBACK) {
4703                         spin_unlock_irqrestore(&np->lock, flags);
4704                         netdev_info(dev, "Loopback already enabled\n");
4705                         return 0;
4706                 }
4707                 nv_disable_irq(dev);
4708                 /* Turn on loopback mode */
4709                 miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
4710                 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
4711                 if (err) {
4712                         retval = PHY_ERROR;
4713                         spin_unlock_irqrestore(&np->lock, flags);
4714                         phy_init(dev);
4715                 } else {
4716                         if (netif_running(dev)) {
4717                                 /* Force 1000 Mbps full-duplex */
4718                                 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000,
4719                                                                          1);
4720                                 /* Force link up */
4721                                 netif_carrier_on(dev);
4722                         }
4723                         spin_unlock_irqrestore(&np->lock, flags);
4724                         netdev_info(dev,
4725                                 "Internal PHY loopback mode enabled.\n");
4726                 }
4727         } else {
4728                 if (!(miicontrol & BMCR_LOOPBACK)) {
4729                         spin_unlock_irqrestore(&np->lock, flags);
4730                         netdev_info(dev, "Loopback already disabled\n");
4731                         return 0;
4732                 }
4733                 nv_disable_irq(dev);
4734                 /* Turn off loopback */
4735                 spin_unlock_irqrestore(&np->lock, flags);
4736                 netdev_info(dev, "Internal PHY loopback mode disabled.\n");
4737                 phy_init(dev);
4738         }
4739         msleep(500);
4740         spin_lock_irqsave(&np->lock, flags);
4741         nv_enable_irq(dev);
4742         spin_unlock_irqrestore(&np->lock, flags);
4743
4744         return retval;
4745 }
4746
4747 static netdev_features_t nv_fix_features(struct net_device *dev,
4748         netdev_features_t features)
4749 {
4750         /* vlan is dependent on rx checksum offload */
4751         if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4752                 features |= NETIF_F_RXCSUM;
4753
4754         return features;
4755 }
4756
4757 static void nv_vlan_mode(struct net_device *dev, netdev_features_t features)
4758 {
4759         struct fe_priv *np = get_nvpriv(dev);
4760
4761         spin_lock_irq(&np->lock);
4762
4763         if (features & NETIF_F_HW_VLAN_RX)
4764                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4765         else
4766                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4767
4768         if (features & NETIF_F_HW_VLAN_TX)
4769                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4770         else
4771                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4772
4773         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4774
4775         spin_unlock_irq(&np->lock);
4776 }
4777
4778 static int nv_set_features(struct net_device *dev, netdev_features_t features)
4779 {
4780         struct fe_priv *np = netdev_priv(dev);
4781         u8 __iomem *base = get_hwbase(dev);
4782         netdev_features_t changed = dev->features ^ features;
4783         int retval;
4784
4785         if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) {
4786                 retval = nv_set_loopback(dev, features);
4787                 if (retval != 0)
4788                         return retval;
4789         }
4790
4791         if (changed & NETIF_F_RXCSUM) {
4792                 spin_lock_irq(&np->lock);
4793
4794                 if (features & NETIF_F_RXCSUM)
4795                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4796                 else
4797                         np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4798
4799                 if (netif_running(dev))
4800                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4801
4802                 spin_unlock_irq(&np->lock);
4803         }
4804
4805         if (changed & (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX))
4806                 nv_vlan_mode(dev, features);
4807
4808         return 0;
4809 }
4810
4811 static int nv_get_sset_count(struct net_device *dev, int sset)
4812 {
4813         struct fe_priv *np = netdev_priv(dev);
4814
4815         switch (sset) {
4816         case ETH_SS_TEST:
4817                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4818                         return NV_TEST_COUNT_EXTENDED;
4819                 else
4820                         return NV_TEST_COUNT_BASE;
4821         case ETH_SS_STATS:
4822                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4823                         return NV_DEV_STATISTICS_V3_COUNT;
4824                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4825                         return NV_DEV_STATISTICS_V2_COUNT;
4826                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4827                         return NV_DEV_STATISTICS_V1_COUNT;
4828                 else
4829                         return 0;
4830         default:
4831                 return -EOPNOTSUPP;
4832         }
4833 }
4834
4835 static void nv_get_ethtool_stats(struct net_device *dev,
4836                                  struct ethtool_stats *estats, u64 *buffer)
4837         __acquires(&netdev_priv(dev)->hwstats_lock)
4838         __releases(&netdev_priv(dev)->hwstats_lock)
4839 {
4840         struct fe_priv *np = netdev_priv(dev);
4841
4842         spin_lock_bh(&np->hwstats_lock);
4843         nv_update_stats(dev);
4844         memcpy(buffer, &np->estats,
4845                nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4846         spin_unlock_bh(&np->hwstats_lock);
4847 }
4848
4849 static int nv_link_test(struct net_device *dev)
4850 {
4851         struct fe_priv *np = netdev_priv(dev);
4852         int mii_status;
4853
4854         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4855         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4856
4857         /* check phy link status */
4858         if (!(mii_status & BMSR_LSTATUS))
4859                 return 0;
4860         else
4861                 return 1;
4862 }
4863
4864 static int nv_register_test(struct net_device *dev)
4865 {
4866         u8 __iomem *base = get_hwbase(dev);
4867         int i = 0;
4868         u32 orig_read, new_read;
4869
4870         do {
4871                 orig_read = readl(base + nv_registers_test[i].reg);
4872
4873                 /* xor with mask to toggle bits */
4874                 orig_read ^= nv_registers_test[i].mask;
4875
4876                 writel(orig_read, base + nv_registers_test[i].reg);
4877
4878                 new_read = readl(base + nv_registers_test[i].reg);
4879
4880                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4881                         return 0;
4882
4883                 /* restore original value */
4884                 orig_read ^= nv_registers_test[i].mask;
4885                 writel(orig_read, base + nv_registers_test[i].reg);
4886
4887         } while (nv_registers_test[++i].reg != 0);
4888
4889         return 1;
4890 }
4891
4892 static int nv_interrupt_test(struct net_device *dev)
4893 {
4894         struct fe_priv *np = netdev_priv(dev);
4895         u8 __iomem *base = get_hwbase(dev);
4896         int ret = 1;
4897         int testcnt;
4898         u32 save_msi_flags, save_poll_interval = 0;
4899
4900         if (netif_running(dev)) {
4901                 /* free current irq */
4902                 nv_free_irq(dev);
4903                 save_poll_interval = readl(base+NvRegPollingInterval);
4904         }
4905
4906         /* flag to test interrupt handler */
4907         np->intr_test = 0;
4908
4909         /* setup test irq */
4910         save_msi_flags = np->msi_flags;
4911         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4912         np->msi_flags |= 0x001; /* setup 1 vector */
4913         if (nv_request_irq(dev, 1))
4914                 return 0;
4915
4916         /* setup timer interrupt */
4917         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4918         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4919
4920         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4921
4922         /* wait for at least one interrupt */
4923         msleep(100);
4924
4925         spin_lock_irq(&np->lock);
4926
4927         /* flag should be set within ISR */
4928         testcnt = np->intr_test;
4929         if (!testcnt)
4930                 ret = 2;
4931
4932         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4933         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4934                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4935         else
4936                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4937
4938         spin_unlock_irq(&np->lock);
4939
4940         nv_free_irq(dev);
4941
4942         np->msi_flags = save_msi_flags;
4943
4944         if (netif_running(dev)) {
4945                 writel(save_poll_interval, base + NvRegPollingInterval);
4946                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4947                 /* restore original irq */
4948                 if (nv_request_irq(dev, 0))
4949                         return 0;
4950         }
4951
4952         return ret;
4953 }
4954
4955 static int nv_loopback_test(struct net_device *dev)
4956 {
4957         struct fe_priv *np = netdev_priv(dev);
4958         u8 __iomem *base = get_hwbase(dev);
4959         struct sk_buff *tx_skb, *rx_skb;
4960         dma_addr_t test_dma_addr;
4961         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4962         u32 flags;
4963         int len, i, pkt_len;
4964         u8 *pkt_data;
4965         u32 filter_flags = 0;
4966         u32 misc1_flags = 0;
4967         int ret = 1;
4968
4969         if (netif_running(dev)) {
4970                 nv_disable_irq(dev);
4971                 filter_flags = readl(base + NvRegPacketFilterFlags);
4972                 misc1_flags = readl(base + NvRegMisc1);
4973         } else {
4974                 nv_txrx_reset(dev);
4975         }
4976
4977         /* reinit driver view of the rx queue */
4978         set_bufsize(dev);
4979         nv_init_ring(dev);
4980
4981         /* setup hardware for loopback */
4982         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4983         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4984
4985         /* reinit nic view of the rx queue */
4986         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4987         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4988         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4989                 base + NvRegRingSizes);
4990         pci_push(base);
4991
4992         /* restart rx engine */
4993         nv_start_rxtx(dev);
4994
4995         /* setup packet for tx */
4996         pkt_len = ETH_DATA_LEN;
4997         tx_skb = netdev_alloc_skb(dev, pkt_len);
4998         if (!tx_skb) {
4999                 netdev_err(dev, "netdev_alloc_skb() failed during loopback test\n");
5000                 ret = 0;
5001                 goto out;
5002         }
5003         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5004                                        skb_tailroom(tx_skb),
5005                                        PCI_DMA_FROMDEVICE);
5006         pkt_data = skb_put(tx_skb, pkt_len);
5007         for (i = 0; i < pkt_len; i++)
5008                 pkt_data[i] = (u8)(i & 0xff);
5009
5010         if (!nv_optimized(np)) {
5011                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5012                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5013         } else {
5014                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5015                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5016                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5017         }
5018         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5019         pci_push(get_hwbase(dev));
5020
5021         msleep(500);
5022
5023         /* check for rx of the packet */
5024         if (!nv_optimized(np)) {
5025                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5026                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5027
5028         } else {
5029                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5030                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5031         }
5032
5033         if (flags & NV_RX_AVAIL) {
5034                 ret = 0;
5035         } else if (np->desc_ver == DESC_VER_1) {
5036                 if (flags & NV_RX_ERROR)
5037                         ret = 0;
5038         } else {
5039                 if (flags & NV_RX2_ERROR)
5040                         ret = 0;
5041         }
5042
5043         if (ret) {
5044                 if (len != pkt_len) {
5045                         ret = 0;
5046                 } else {
5047                         rx_skb = np->rx_skb[0].skb;
5048                         for (i = 0; i < pkt_len; i++) {
5049                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5050                                         ret = 0;
5051                                         break;
5052                                 }
5053                         }
5054                 }
5055         }
5056
5057         pci_unmap_single(np->pci_dev, test_dma_addr,
5058                        (skb_end_pointer(tx_skb) - tx_skb->data),
5059                        PCI_DMA_TODEVICE);
5060         dev_kfree_skb_any(tx_skb);
5061  out:
5062         /* stop engines */
5063         nv_stop_rxtx(dev);
5064         nv_txrx_reset(dev);
5065         /* drain rx queue */
5066         nv_drain_rxtx(dev);
5067
5068         if (netif_running(dev)) {
5069                 writel(misc1_flags, base + NvRegMisc1);
5070                 writel(filter_flags, base + NvRegPacketFilterFlags);
5071                 nv_enable_irq(dev);
5072         }
5073
5074         return ret;
5075 }
5076
5077 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5078 {
5079         struct fe_priv *np = netdev_priv(dev);
5080         u8 __iomem *base = get_hwbase(dev);
5081         int result;
5082         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5083
5084         if (!nv_link_test(dev)) {
5085                 test->flags |= ETH_TEST_FL_FAILED;
5086                 buffer[0] = 1;
5087         }
5088
5089         if (test->flags & ETH_TEST_FL_OFFLINE) {
5090                 if (netif_running(dev)) {
5091                         netif_stop_queue(dev);
5092                         nv_napi_disable(dev);
5093                         netif_tx_lock_bh(dev);
5094                         netif_addr_lock(dev);
5095                         spin_lock_irq(&np->lock);
5096                         nv_disable_hw_interrupts(dev, np->irqmask);
5097                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
5098                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5099                         else
5100                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5101                         /* stop engines */
5102                         nv_stop_rxtx(dev);
5103                         nv_txrx_reset(dev);
5104                         /* drain rx queue */
5105                         nv_drain_rxtx(dev);
5106                         spin_unlock_irq(&np->lock);
5107                         netif_addr_unlock(dev);
5108                         netif_tx_unlock_bh(dev);
5109                 }
5110
5111                 if (!nv_register_test(dev)) {
5112                         test->flags |= ETH_TEST_FL_FAILED;
5113                         buffer[1] = 1;
5114                 }
5115
5116                 result = nv_interrupt_test(dev);
5117                 if (result != 1) {
5118                         test->flags |= ETH_TEST_FL_FAILED;
5119                         buffer[2] = 1;
5120                 }
5121                 if (result == 0) {
5122                         /* bail out */
5123                         return;
5124                 }
5125
5126                 if (!nv_loopback_test(dev)) {
5127                         test->flags |= ETH_TEST_FL_FAILED;
5128                         buffer[3] = 1;
5129                 }
5130
5131                 if (netif_running(dev)) {
5132                         /* reinit driver view of the rx queue */
5133                         set_bufsize(dev);
5134                         if (nv_init_ring(dev)) {
5135                                 if (!np->in_shutdown)
5136                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5137                         }
5138                         /* reinit nic view of the rx queue */
5139                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5140                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5141                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5142                                 base + NvRegRingSizes);
5143                         pci_push(base);
5144                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5145                         pci_push(base);
5146                         /* restart rx engine */
5147                         nv_start_rxtx(dev);
5148                         netif_start_queue(dev);
5149                         nv_napi_enable(dev);
5150                         nv_enable_hw_interrupts(dev, np->irqmask);
5151                 }
5152         }
5153 }
5154
5155 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5156 {
5157         switch (stringset) {
5158         case ETH_SS_STATS:
5159                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5160                 break;
5161         case ETH_SS_TEST:
5162                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5163                 break;
5164         }
5165 }
5166
5167 static const struct ethtool_ops ops = {
5168         .get_drvinfo = nv_get_drvinfo,
5169         .get_link = ethtool_op_get_link,
5170         .get_wol = nv_get_wol,
5171         .set_wol = nv_set_wol,
5172         .get_settings = nv_get_settings,
5173         .set_settings = nv_set_settings,
5174         .get_regs_len = nv_get_regs_len,
5175         .get_regs = nv_get_regs,
5176         .nway_reset = nv_nway_reset,
5177         .get_ringparam = nv_get_ringparam,
5178         .set_ringparam = nv_set_ringparam,
5179         .get_pauseparam = nv_get_pauseparam,
5180         .set_pauseparam = nv_set_pauseparam,
5181         .get_strings = nv_get_strings,
5182         .get_ethtool_stats = nv_get_ethtool_stats,
5183         .get_sset_count = nv_get_sset_count,
5184         .self_test = nv_self_test,
5185 };
5186
5187 /* The mgmt unit and driver use a semaphore to access the phy during init */
5188 static int nv_mgmt_acquire_sema(struct net_device *dev)
5189 {
5190         struct fe_priv *np = netdev_priv(dev);
5191         u8 __iomem *base = get_hwbase(dev);
5192         int i;
5193         u32 tx_ctrl, mgmt_sema;
5194
5195         for (i = 0; i < 10; i++) {
5196                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5197                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5198                         break;
5199                 msleep(500);
5200         }
5201
5202         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5203                 return 0;
5204
5205         for (i = 0; i < 2; i++) {
5206                 tx_ctrl = readl(base + NvRegTransmitterControl);
5207                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5208                 writel(tx_ctrl, base + NvRegTransmitterControl);
5209
5210                 /* verify that semaphore was acquired */
5211                 tx_ctrl = readl(base + NvRegTransmitterControl);
5212                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5213                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5214                         np->mgmt_sema = 1;
5215                         return 1;
5216                 } else
5217                         udelay(50);
5218         }
5219
5220         return 0;
5221 }
5222
5223 static void nv_mgmt_release_sema(struct net_device *dev)
5224 {
5225         struct fe_priv *np = netdev_priv(dev);
5226         u8 __iomem *base = get_hwbase(dev);
5227         u32 tx_ctrl;
5228
5229         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5230                 if (np->mgmt_sema) {
5231                         tx_ctrl = readl(base + NvRegTransmitterControl);
5232                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5233                         writel(tx_ctrl, base + NvRegTransmitterControl);
5234                 }
5235         }
5236 }
5237
5238
5239 static int nv_mgmt_get_version(struct net_device *dev)
5240 {
5241         struct fe_priv *np = netdev_priv(dev);
5242         u8 __iomem *base = get_hwbase(dev);
5243         u32 data_ready = readl(base + NvRegTransmitterControl);
5244         u32 data_ready2 = 0;
5245         unsigned long start;
5246         int ready = 0;
5247
5248         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5249         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5250         start = jiffies;
5251         while (time_before(jiffies, start + 5*HZ)) {
5252                 data_ready2 = readl(base + NvRegTransmitterControl);
5253                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5254                         ready = 1;
5255                         break;
5256                 }
5257                 schedule_timeout_uninterruptible(1);
5258         }
5259
5260         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5261                 return 0;
5262
5263         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5264
5265         return 1;
5266 }
5267
5268 static int nv_open(struct net_device *dev)
5269 {
5270         struct fe_priv *np = netdev_priv(dev);
5271         u8 __iomem *base = get_hwbase(dev);
5272         int ret = 1;
5273         int oom, i;
5274         u32 low;
5275
5276         /* power up phy */
5277         mii_rw(dev, np->phyaddr, MII_BMCR,
5278                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5279
5280         nv_txrx_gate(dev, false);
5281         /* erase previous misconfiguration */
5282         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5283                 nv_mac_reset(dev);
5284         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5285         writel(0, base + NvRegMulticastAddrB);
5286         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5287         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5288         writel(0, base + NvRegPacketFilterFlags);
5289
5290         writel(0, base + NvRegTransmitterControl);
5291         writel(0, base + NvRegReceiverControl);
5292
5293         writel(0, base + NvRegAdapterControl);
5294
5295         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5296                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5297
5298         /* initialize descriptor rings */
5299         set_bufsize(dev);
5300         oom = nv_init_ring(dev);
5301
5302         writel(0, base + NvRegLinkSpeed);
5303         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5304         nv_txrx_reset(dev);
5305         writel(0, base + NvRegUnknownSetupReg6);
5306
5307         np->in_shutdown = 0;
5308
5309         /* give hw rings */
5310         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5311         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5312                 base + NvRegRingSizes);
5313
5314         writel(np->linkspeed, base + NvRegLinkSpeed);
5315         if (np->desc_ver == DESC_VER_1)
5316                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5317         else
5318                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5319         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5320         writel(np->vlanctl_bits, base + NvRegVlanControl);
5321         pci_push(base);
5322         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5323         if (reg_delay(dev, NvRegUnknownSetupReg5,
5324                       NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5325                       NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5326                 netdev_info(dev,
5327                             "%s: SetupReg5, Bit 31 remained off\n", __func__);
5328
5329         writel(0, base + NvRegMIIMask);
5330         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5331         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5332
5333         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5334         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5335         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5336         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5337
5338         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5339
5340         get_random_bytes(&low, sizeof(low));
5341         low &= NVREG_SLOTTIME_MASK;
5342         if (np->desc_ver == DESC_VER_1) {
5343                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5344         } else {
5345                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5346                         /* setup legacy backoff */
5347                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5348                 } else {
5349                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5350                         nv_gear_backoff_reseed(dev);
5351                 }
5352         }
5353         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5354         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5355         if (poll_interval == -1) {
5356                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5357                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5358                 else
5359                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5360         } else
5361                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5362         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5363         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5364                         base + NvRegAdapterControl);
5365         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5366         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5367         if (np->wolenabled)
5368                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5369
5370         i = readl(base + NvRegPowerState);
5371         if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5372                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5373
5374         pci_push(base);
5375         udelay(10);
5376         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5377
5378         nv_disable_hw_interrupts(dev, np->irqmask);
5379         pci_push(base);
5380         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5381         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5382         pci_push(base);
5383
5384         if (nv_request_irq(dev, 0))
5385                 goto out_drain;
5386
5387         /* ask for interrupts */
5388         nv_enable_hw_interrupts(dev, np->irqmask);
5389
5390         spin_lock_irq(&np->lock);
5391         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5392         writel(0, base + NvRegMulticastAddrB);
5393         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5394         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5395         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5396         /* One manual link speed update: Interrupts are enabled, future link
5397          * speed changes cause interrupts and are handled by nv_link_irq().
5398          */
5399         {
5400                 u32 miistat;
5401                 miistat = readl(base + NvRegMIIStatus);
5402                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5403         }
5404         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5405          * to init hw */
5406         np->linkspeed = 0;
5407         ret = nv_update_linkspeed(dev);
5408         nv_start_rxtx(dev);
5409         netif_start_queue(dev);
5410         nv_napi_enable(dev);
5411
5412         if (ret) {
5413                 netif_carrier_on(dev);
5414         } else {
5415                 netdev_info(dev, "no link during initialization\n");
5416                 netif_carrier_off(dev);
5417         }
5418         if (oom)
5419                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5420
5421         /* start statistics timer */
5422         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5423                 mod_timer(&np->stats_poll,
5424                         round_jiffies(jiffies + STATS_INTERVAL));
5425
5426         spin_unlock_irq(&np->lock);
5427
5428         /* If the loopback feature was set while the device was down, make sure
5429          * that it's set correctly now.
5430          */
5431         if (dev->features & NETIF_F_LOOPBACK)
5432                 nv_set_loopback(dev, dev->features);
5433
5434         return 0;
5435 out_drain:
5436         nv_drain_rxtx(dev);
5437         return ret;
5438 }
5439
5440 static int nv_close(struct net_device *dev)
5441 {
5442         struct fe_priv *np = netdev_priv(dev);
5443         u8 __iomem *base;
5444
5445         spin_lock_irq(&np->lock);
5446         np->in_shutdown = 1;
5447         spin_unlock_irq(&np->lock);
5448         nv_napi_disable(dev);
5449         synchronize_irq(np->pci_dev->irq);
5450
5451         del_timer_sync(&np->oom_kick);
5452         del_timer_sync(&np->nic_poll);
5453         del_timer_sync(&np->stats_poll);
5454
5455         netif_stop_queue(dev);
5456         spin_lock_irq(&np->lock);
5457         nv_stop_rxtx(dev);
5458         nv_txrx_reset(dev);
5459
5460         /* disable interrupts on the nic or we will lock up */
5461         base = get_hwbase(dev);
5462         nv_disable_hw_interrupts(dev, np->irqmask);
5463         pci_push(base);
5464
5465         spin_unlock_irq(&np->lock);
5466
5467         nv_free_irq(dev);
5468
5469         nv_drain_rxtx(dev);
5470
5471         if (np->wolenabled || !phy_power_down) {
5472                 nv_txrx_gate(dev, false);
5473                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5474                 nv_start_rx(dev);
5475         } else {
5476                 /* power down phy */
5477                 mii_rw(dev, np->phyaddr, MII_BMCR,
5478                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5479                 nv_txrx_gate(dev, true);
5480         }
5481
5482         /* FIXME: power down nic */
5483
5484         return 0;
5485 }
5486
5487 static const struct net_device_ops nv_netdev_ops = {
5488         .ndo_open               = nv_open,
5489         .ndo_stop               = nv_close,
5490         .ndo_get_stats64        = nv_get_stats64,
5491         .ndo_start_xmit         = nv_start_xmit,
5492         .ndo_tx_timeout         = nv_tx_timeout,
5493         .ndo_change_mtu         = nv_change_mtu,
5494         .ndo_fix_features       = nv_fix_features,
5495         .ndo_set_features       = nv_set_features,
5496         .ndo_validate_addr      = eth_validate_addr,
5497         .ndo_set_mac_address    = nv_set_mac_address,
5498         .ndo_set_rx_mode        = nv_set_multicast,
5499 #ifdef CONFIG_NET_POLL_CONTROLLER
5500         .ndo_poll_controller    = nv_poll_controller,
5501 #endif
5502 };
5503
5504 static const struct net_device_ops nv_netdev_ops_optimized = {
5505         .ndo_open               = nv_open,
5506         .ndo_stop               = nv_close,
5507         .ndo_get_stats64        = nv_get_stats64,
5508         .ndo_start_xmit         = nv_start_xmit_optimized,
5509         .ndo_tx_timeout         = nv_tx_timeout,
5510         .ndo_change_mtu         = nv_change_mtu,
5511         .ndo_fix_features       = nv_fix_features,
5512         .ndo_set_features       = nv_set_features,
5513         .ndo_validate_addr      = eth_validate_addr,
5514         .ndo_set_mac_address    = nv_set_mac_address,
5515         .ndo_set_rx_mode        = nv_set_multicast,
5516 #ifdef CONFIG_NET_POLL_CONTROLLER
5517         .ndo_poll_controller    = nv_poll_controller,
5518 #endif
5519 };
5520
5521 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5522 {
5523         struct net_device *dev;
5524         struct fe_priv *np;
5525         unsigned long addr;
5526         u8 __iomem *base;
5527         int err, i;
5528         u32 powerstate, txreg;
5529         u32 phystate_orig = 0, phystate;
5530         int phyinitialized = 0;
5531         static int printed_version;
5532
5533         if (!printed_version++)
5534                 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5535                         FORCEDETH_VERSION);
5536
5537         dev = alloc_etherdev(sizeof(struct fe_priv));
5538         err = -ENOMEM;
5539         if (!dev)
5540                 goto out;
5541
5542         np = netdev_priv(dev);
5543         np->dev = dev;
5544         np->pci_dev = pci_dev;
5545         spin_lock_init(&np->lock);
5546         spin_lock_init(&np->hwstats_lock);
5547         SET_NETDEV_DEV(dev, &pci_dev->dev);
5548
5549         init_timer(&np->oom_kick);
5550         np->oom_kick.data = (unsigned long) dev;
5551         np->oom_kick.function = nv_do_rx_refill;        /* timer handler */
5552         init_timer(&np->nic_poll);
5553         np->nic_poll.data = (unsigned long) dev;
5554         np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5555         init_timer_deferrable(&np->stats_poll);
5556         np->stats_poll.data = (unsigned long) dev;
5557         np->stats_poll.function = nv_do_stats_poll;     /* timer handler */
5558
5559         err = pci_enable_device(pci_dev);
5560         if (err)
5561                 goto out_free;
5562
5563         pci_set_master(pci_dev);
5564
5565         err = pci_request_regions(pci_dev, DRV_NAME);
5566         if (err < 0)
5567                 goto out_disable;
5568
5569         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5570                 np->register_size = NV_PCI_REGSZ_VER3;
5571         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5572                 np->register_size = NV_PCI_REGSZ_VER2;
5573         else
5574                 np->register_size = NV_PCI_REGSZ_VER1;
5575
5576         err = -EINVAL;
5577         addr = 0;
5578         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5579                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5580                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5581                         addr = pci_resource_start(pci_dev, i);
5582                         break;
5583                 }
5584         }
5585         if (i == DEVICE_COUNT_RESOURCE) {
5586                 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5587                 goto out_relreg;
5588         }
5589
5590         /* copy of driver data */
5591         np->driver_data = id->driver_data;
5592         /* copy of device id */
5593         np->device_id = id->device;
5594
5595         /* handle different descriptor versions */
5596         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5597                 /* packet format 3: supports 40-bit addressing */
5598                 np->desc_ver = DESC_VER_3;
5599                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5600                 if (dma_64bit) {
5601                         if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5602                                 dev_info(&pci_dev->dev,
5603                                          "64-bit DMA failed, using 32-bit addressing\n");
5604                         else
5605                                 dev->features |= NETIF_F_HIGHDMA;
5606                         if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5607                                 dev_info(&pci_dev->dev,
5608                                          "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5609                         }
5610                 }
5611         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5612                 /* packet format 2: supports jumbo frames */
5613                 np->desc_ver = DESC_VER_2;
5614                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5615         } else {
5616                 /* original packet format */
5617                 np->desc_ver = DESC_VER_1;
5618                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5619         }
5620
5621         np->pkt_limit = NV_PKTLIMIT_1;
5622         if (id->driver_data & DEV_HAS_LARGEDESC)
5623                 np->pkt_limit = NV_PKTLIMIT_2;
5624
5625         if (id->driver_data & DEV_HAS_CHECKSUM) {
5626                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5627                 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5628                         NETIF_F_TSO | NETIF_F_RXCSUM;
5629         }
5630
5631         np->vlanctl_bits = 0;
5632         if (id->driver_data & DEV_HAS_VLAN) {
5633                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5634                 dev->hw_features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5635         }
5636
5637         dev->features |= dev->hw_features;
5638
5639         /* Add loopback capability to the device. */
5640         dev->hw_features |= NETIF_F_LOOPBACK;
5641
5642         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5643         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5644             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5645             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5646                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5647         }
5648
5649         err = -ENOMEM;
5650         np->base = ioremap(addr, np->register_size);
5651         if (!np->base)
5652                 goto out_relreg;
5653         dev->base_addr = (unsigned long)np->base;
5654
5655         dev->irq = pci_dev->irq;
5656
5657         np->rx_ring_size = RX_RING_DEFAULT;
5658         np->tx_ring_size = TX_RING_DEFAULT;
5659
5660         if (!nv_optimized(np)) {
5661                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5662                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5663                                         &np->ring_addr);
5664                 if (!np->rx_ring.orig)
5665                         goto out_unmap;
5666                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5667         } else {
5668                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5669                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5670                                         &np->ring_addr);
5671                 if (!np->rx_ring.ex)
5672                         goto out_unmap;
5673                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5674         }
5675         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5676         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5677         if (!np->rx_skb || !np->tx_skb)
5678                 goto out_freering;
5679
5680         if (!nv_optimized(np))
5681                 dev->netdev_ops = &nv_netdev_ops;
5682         else
5683                 dev->netdev_ops = &nv_netdev_ops_optimized;
5684
5685         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5686         SET_ETHTOOL_OPS(dev, &ops);
5687         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5688
5689         pci_set_drvdata(pci_dev, dev);
5690
5691         /* read the mac address */
5692         base = get_hwbase(dev);
5693         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5694         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5695
5696         /* check the workaround bit for correct mac address order */
5697         txreg = readl(base + NvRegTransmitPoll);
5698         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5699                 /* mac address is already in correct order */
5700                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5701                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5702                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5703                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5704                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5705                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5706         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5707                 /* mac address is already in correct order */
5708                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5709                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5710                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5711                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5712                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5713                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5714                 /*
5715                  * Set orig mac address back to the reversed version.
5716                  * This flag will be cleared during low power transition.
5717                  * Therefore, we should always put back the reversed address.
5718                  */
5719                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5720                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5721                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5722         } else {
5723                 /* need to reverse mac address to correct order */
5724                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5725                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5726                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5727                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5728                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5729                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5730                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5731                 dev_dbg(&pci_dev->dev,
5732                         "%s: set workaround bit for reversed mac addr\n",
5733                         __func__);
5734         }
5735         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5736
5737         if (!is_valid_ether_addr(dev->perm_addr)) {
5738                 /*
5739                  * Bad mac address. At least one bios sets the mac address
5740                  * to 01:23:45:67:89:ab
5741                  */
5742                 dev_err(&pci_dev->dev,
5743                         "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5744                         dev->dev_addr);
5745                 eth_hw_addr_random(dev);
5746                 dev_err(&pci_dev->dev,
5747                         "Using random MAC address: %pM\n", dev->dev_addr);
5748         }
5749
5750         /* set mac address */
5751         nv_copy_mac_to_hw(dev);
5752
5753         /* disable WOL */
5754         writel(0, base + NvRegWakeUpFlags);
5755         np->wolenabled = 0;
5756         device_set_wakeup_enable(&pci_dev->dev, false);
5757
5758         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5759
5760                 /* take phy and nic out of low power mode */
5761                 powerstate = readl(base + NvRegPowerState2);
5762                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5763                 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5764                     pci_dev->revision >= 0xA3)
5765                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5766                 writel(powerstate, base + NvRegPowerState2);
5767         }
5768
5769         if (np->desc_ver == DESC_VER_1)
5770                 np->tx_flags = NV_TX_VALID;
5771         else
5772                 np->tx_flags = NV_TX2_VALID;
5773
5774         np->msi_flags = 0;
5775         if ((id->driver_data & DEV_HAS_MSI) && msi)
5776                 np->msi_flags |= NV_MSI_CAPABLE;
5777
5778         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5779                 /* msix has had reported issues when modifying irqmask
5780                    as in the case of napi, therefore, disable for now
5781                 */
5782 #if 0
5783                 np->msi_flags |= NV_MSI_X_CAPABLE;
5784 #endif
5785         }
5786
5787         if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5788                 np->irqmask = NVREG_IRQMASK_CPU;
5789                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5790                         np->msi_flags |= 0x0001;
5791         } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5792                    !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5793                 /* start off in throughput mode */
5794                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5795                 /* remove support for msix mode */
5796                 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5797         } else {
5798                 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5799                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5800                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5801                         np->msi_flags |= 0x0003;
5802         }
5803
5804         if (id->driver_data & DEV_NEED_TIMERIRQ)
5805                 np->irqmask |= NVREG_IRQ_TIMER;
5806         if (id->driver_data & DEV_NEED_LINKTIMER) {
5807                 np->need_linktimer = 1;
5808                 np->link_timeout = jiffies + LINK_TIMEOUT;
5809         } else {
5810                 np->need_linktimer = 0;
5811         }
5812
5813         /* Limit the number of tx's outstanding for hw bug */
5814         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5815                 np->tx_limit = 1;
5816                 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5817                     pci_dev->revision >= 0xA2)
5818                         np->tx_limit = 0;
5819         }
5820
5821         /* clear phy state and temporarily halt phy interrupts */
5822         writel(0, base + NvRegMIIMask);
5823         phystate = readl(base + NvRegAdapterControl);
5824         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5825                 phystate_orig = 1;
5826                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5827                 writel(phystate, base + NvRegAdapterControl);
5828         }
5829         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5830
5831         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5832                 /* management unit running on the mac? */
5833                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5834                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5835                     nv_mgmt_acquire_sema(dev) &&
5836                     nv_mgmt_get_version(dev)) {
5837                         np->mac_in_use = 1;
5838                         if (np->mgmt_version > 0)
5839                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5840                         /* management unit setup the phy already? */
5841                         if (np->mac_in_use &&
5842                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5843                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5844                                 /* phy is inited by mgmt unit */
5845                                 phyinitialized = 1;
5846                         } else {
5847                                 /* we need to init the phy */
5848                         }
5849                 }
5850         }
5851
5852         /* find a suitable phy */
5853         for (i = 1; i <= 32; i++) {
5854                 int id1, id2;
5855                 int phyaddr = i & 0x1F;
5856
5857                 spin_lock_irq(&np->lock);
5858                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5859                 spin_unlock_irq(&np->lock);
5860                 if (id1 < 0 || id1 == 0xffff)
5861                         continue;
5862                 spin_lock_irq(&np->lock);
5863                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5864                 spin_unlock_irq(&np->lock);
5865                 if (id2 < 0 || id2 == 0xffff)
5866                         continue;
5867
5868                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5869                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5870                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5871                 np->phyaddr = phyaddr;
5872                 np->phy_oui = id1 | id2;
5873
5874                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5875                 if (np->phy_oui == PHY_OUI_REALTEK2)
5876                         np->phy_oui = PHY_OUI_REALTEK;
5877                 /* Setup phy revision for Realtek */
5878                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5879                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5880
5881                 break;
5882         }
5883         if (i == 33) {
5884                 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5885                 goto out_error;
5886         }
5887
5888         if (!phyinitialized) {
5889                 /* reset it */
5890                 phy_init(dev);
5891         } else {
5892                 /* see if it is a gigabit phy */
5893                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5894                 if (mii_status & PHY_GIGABIT)
5895                         np->gigabit = PHY_GIGABIT;
5896         }
5897
5898         /* set default link speed settings */
5899         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5900         np->duplex = 0;
5901         np->autoneg = 1;
5902
5903         err = register_netdev(dev);
5904         if (err) {
5905                 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5906                 goto out_error;
5907         }
5908
5909         if (id->driver_data & DEV_HAS_VLAN)
5910                 nv_vlan_mode(dev, dev->features);
5911
5912         netif_carrier_off(dev);
5913
5914         dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5915                  dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5916
5917         dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5918                  dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5919                  dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5920                         "csum " : "",
5921                  dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5922                         "vlan " : "",
5923                  dev->features & (NETIF_F_LOOPBACK) ?
5924                         "loopback " : "",
5925                  id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5926                  id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5927                  id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5928                  np->gigabit == PHY_GIGABIT ? "gbit " : "",
5929                  np->need_linktimer ? "lnktim " : "",
5930                  np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5931                  np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5932                  np->desc_ver);
5933
5934         return 0;
5935
5936 out_error:
5937         if (phystate_orig)
5938                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5939         pci_set_drvdata(pci_dev, NULL);
5940 out_freering:
5941         free_rings(dev);
5942 out_unmap:
5943         iounmap(get_hwbase(dev));
5944 out_relreg:
5945         pci_release_regions(pci_dev);
5946 out_disable:
5947         pci_disable_device(pci_dev);
5948 out_free:
5949         free_netdev(dev);
5950 out:
5951         return err;
5952 }
5953
5954 static void nv_restore_phy(struct net_device *dev)
5955 {
5956         struct fe_priv *np = netdev_priv(dev);
5957         u16 phy_reserved, mii_control;
5958
5959         if (np->phy_oui == PHY_OUI_REALTEK &&
5960             np->phy_model == PHY_MODEL_REALTEK_8201 &&
5961             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5962                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5963                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5964                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5965                 phy_reserved |= PHY_REALTEK_INIT8;
5966                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5967                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5968
5969                 /* restart auto negotiation */
5970                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5971                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5972                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5973         }
5974 }
5975
5976 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5977 {
5978         struct net_device *dev = pci_get_drvdata(pci_dev);
5979         struct fe_priv *np = netdev_priv(dev);
5980         u8 __iomem *base = get_hwbase(dev);
5981
5982         /* special op: write back the misordered MAC address - otherwise
5983          * the next nv_probe would see a wrong address.
5984          */
5985         writel(np->orig_mac[0], base + NvRegMacAddrA);
5986         writel(np->orig_mac[1], base + NvRegMacAddrB);
5987         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5988                base + NvRegTransmitPoll);
5989 }
5990
5991 static void __devexit nv_remove(struct pci_dev *pci_dev)
5992 {
5993         struct net_device *dev = pci_get_drvdata(pci_dev);
5994
5995         unregister_netdev(dev);
5996
5997         nv_restore_mac_addr(pci_dev);
5998
5999         /* restore any phy related changes */
6000         nv_restore_phy(dev);
6001
6002         nv_mgmt_release_sema(dev);
6003
6004         /* free all structures */
6005         free_rings(dev);
6006         iounmap(get_hwbase(dev));
6007         pci_release_regions(pci_dev);
6008         pci_disable_device(pci_dev);
6009         free_netdev(dev);
6010         pci_set_drvdata(pci_dev, NULL);
6011 }
6012
6013 #ifdef CONFIG_PM_SLEEP
6014 static int nv_suspend(struct device *device)
6015 {
6016         struct pci_dev *pdev = to_pci_dev(device);
6017         struct net_device *dev = pci_get_drvdata(pdev);
6018         struct fe_priv *np = netdev_priv(dev);
6019         u8 __iomem *base = get_hwbase(dev);
6020         int i;
6021
6022         if (netif_running(dev)) {
6023                 /* Gross. */
6024                 nv_close(dev);
6025         }
6026         netif_device_detach(dev);
6027
6028         /* save non-pci configuration space */
6029         for (i = 0; i <= np->register_size/sizeof(u32); i++)
6030                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6031
6032         return 0;
6033 }
6034
6035 static int nv_resume(struct device *device)
6036 {
6037         struct pci_dev *pdev = to_pci_dev(device);
6038         struct net_device *dev = pci_get_drvdata(pdev);
6039         struct fe_priv *np = netdev_priv(dev);
6040         u8 __iomem *base = get_hwbase(dev);
6041         int i, rc = 0;
6042
6043         /* restore non-pci configuration space */
6044         for (i = 0; i <= np->register_size/sizeof(u32); i++)
6045                 writel(np->saved_config_space[i], base+i*sizeof(u32));
6046
6047         if (np->driver_data & DEV_NEED_MSI_FIX)
6048                 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6049
6050         /* restore phy state, including autoneg */
6051         phy_init(dev);
6052
6053         netif_device_attach(dev);
6054         if (netif_running(dev)) {
6055                 rc = nv_open(dev);
6056                 nv_set_multicast(dev);
6057         }
6058         return rc;
6059 }
6060
6061 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
6062 #define NV_PM_OPS (&nv_pm_ops)
6063
6064 #else
6065 #define NV_PM_OPS NULL
6066 #endif /* CONFIG_PM_SLEEP */
6067
6068 #ifdef CONFIG_PM
6069 static void nv_shutdown(struct pci_dev *pdev)
6070 {
6071         struct net_device *dev = pci_get_drvdata(pdev);
6072         struct fe_priv *np = netdev_priv(dev);
6073
6074         if (netif_running(dev))
6075                 nv_close(dev);
6076
6077         /*
6078          * Restore the MAC so a kernel started by kexec won't get confused.
6079          * If we really go for poweroff, we must not restore the MAC,
6080          * otherwise the MAC for WOL will be reversed at least on some boards.
6081          */
6082         if (system_state != SYSTEM_POWER_OFF)
6083                 nv_restore_mac_addr(pdev);
6084
6085         pci_disable_device(pdev);
6086         /*
6087          * Apparently it is not possible to reinitialise from D3 hot,
6088          * only put the device into D3 if we really go for poweroff.
6089          */
6090         if (system_state == SYSTEM_POWER_OFF) {
6091                 pci_wake_from_d3(pdev, np->wolenabled);
6092                 pci_set_power_state(pdev, PCI_D3hot);
6093         }
6094 }
6095 #else
6096 #define nv_shutdown NULL
6097 #endif /* CONFIG_PM */
6098
6099 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
6100         {       /* nForce Ethernet Controller */
6101                 PCI_DEVICE(0x10DE, 0x01C3),
6102                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6103         },
6104         {       /* nForce2 Ethernet Controller */
6105                 PCI_DEVICE(0x10DE, 0x0066),
6106                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6107         },
6108         {       /* nForce3 Ethernet Controller */
6109                 PCI_DEVICE(0x10DE, 0x00D6),
6110                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6111         },
6112         {       /* nForce3 Ethernet Controller */
6113                 PCI_DEVICE(0x10DE, 0x0086),
6114                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6115         },
6116         {       /* nForce3 Ethernet Controller */
6117                 PCI_DEVICE(0x10DE, 0x008C),
6118                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6119         },
6120         {       /* nForce3 Ethernet Controller */
6121                 PCI_DEVICE(0x10DE, 0x00E6),
6122                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6123         },
6124         {       /* nForce3 Ethernet Controller */
6125                 PCI_DEVICE(0x10DE, 0x00DF),
6126                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6127         },
6128         {       /* CK804 Ethernet Controller */
6129                 PCI_DEVICE(0x10DE, 0x0056),
6130                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6131         },
6132         {       /* CK804 Ethernet Controller */
6133                 PCI_DEVICE(0x10DE, 0x0057),
6134                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6135         },
6136         {       /* MCP04 Ethernet Controller */
6137                 PCI_DEVICE(0x10DE, 0x0037),
6138                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6139         },
6140         {       /* MCP04 Ethernet Controller */
6141                 PCI_DEVICE(0x10DE, 0x0038),
6142                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6143         },
6144         {       /* MCP51 Ethernet Controller */
6145                 PCI_DEVICE(0x10DE, 0x0268),
6146                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6147         },
6148         {       /* MCP51 Ethernet Controller */
6149                 PCI_DEVICE(0x10DE, 0x0269),
6150                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6151         },
6152         {       /* MCP55 Ethernet Controller */
6153                 PCI_DEVICE(0x10DE, 0x0372),
6154                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6155         },
6156         {       /* MCP55 Ethernet Controller */
6157                 PCI_DEVICE(0x10DE, 0x0373),
6158                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6159         },
6160         {       /* MCP61 Ethernet Controller */
6161                 PCI_DEVICE(0x10DE, 0x03E5),
6162                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6163         },
6164         {       /* MCP61 Ethernet Controller */
6165                 PCI_DEVICE(0x10DE, 0x03E6),
6166                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6167         },
6168         {       /* MCP61 Ethernet Controller */
6169                 PCI_DEVICE(0x10DE, 0x03EE),
6170                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6171         },
6172         {       /* MCP61 Ethernet Controller */
6173                 PCI_DEVICE(0x10DE, 0x03EF),
6174                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6175         },
6176         {       /* MCP65 Ethernet Controller */
6177                 PCI_DEVICE(0x10DE, 0x0450),
6178                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6179         },
6180         {       /* MCP65 Ethernet Controller */
6181                 PCI_DEVICE(0x10DE, 0x0451),
6182                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6183         },
6184         {       /* MCP65 Ethernet Controller */
6185                 PCI_DEVICE(0x10DE, 0x0452),
6186                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6187         },
6188         {       /* MCP65 Ethernet Controller */
6189                 PCI_DEVICE(0x10DE, 0x0453),
6190                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6191         },
6192         {       /* MCP67 Ethernet Controller */
6193                 PCI_DEVICE(0x10DE, 0x054C),
6194                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6195         },
6196         {       /* MCP67 Ethernet Controller */
6197                 PCI_DEVICE(0x10DE, 0x054D),
6198                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6199         },
6200         {       /* MCP67 Ethernet Controller */
6201                 PCI_DEVICE(0x10DE, 0x054E),
6202                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6203         },
6204         {       /* MCP67 Ethernet Controller */
6205                 PCI_DEVICE(0x10DE, 0x054F),
6206                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6207         },
6208         {       /* MCP73 Ethernet Controller */
6209                 PCI_DEVICE(0x10DE, 0x07DC),
6210                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6211         },
6212         {       /* MCP73 Ethernet Controller */
6213                 PCI_DEVICE(0x10DE, 0x07DD),
6214                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6215         },
6216         {       /* MCP73 Ethernet Controller */
6217                 PCI_DEVICE(0x10DE, 0x07DE),
6218                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6219         },
6220         {       /* MCP73 Ethernet Controller */
6221                 PCI_DEVICE(0x10DE, 0x07DF),
6222                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6223         },
6224         {       /* MCP77 Ethernet Controller */
6225                 PCI_DEVICE(0x10DE, 0x0760),
6226                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6227         },
6228         {       /* MCP77 Ethernet Controller */
6229                 PCI_DEVICE(0x10DE, 0x0761),
6230                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6231         },
6232         {       /* MCP77 Ethernet Controller */
6233                 PCI_DEVICE(0x10DE, 0x0762),
6234                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6235         },
6236         {       /* MCP77 Ethernet Controller */
6237                 PCI_DEVICE(0x10DE, 0x0763),
6238                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6239         },
6240         {       /* MCP79 Ethernet Controller */
6241                 PCI_DEVICE(0x10DE, 0x0AB0),
6242                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6243         },
6244         {       /* MCP79 Ethernet Controller */
6245                 PCI_DEVICE(0x10DE, 0x0AB1),
6246                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6247         },
6248         {       /* MCP79 Ethernet Controller */
6249                 PCI_DEVICE(0x10DE, 0x0AB2),
6250                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6251         },
6252         {       /* MCP79 Ethernet Controller */
6253                 PCI_DEVICE(0x10DE, 0x0AB3),
6254                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6255         },
6256         {       /* MCP89 Ethernet Controller */
6257                 PCI_DEVICE(0x10DE, 0x0D7D),
6258                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6259         },
6260         {0,},
6261 };
6262
6263 static struct pci_driver driver = {
6264         .name           = DRV_NAME,
6265         .id_table       = pci_tbl,
6266         .probe          = nv_probe,
6267         .remove         = __devexit_p(nv_remove),
6268         .shutdown       = nv_shutdown,
6269         .driver.pm      = NV_PM_OPS,
6270 };
6271
6272 static int __init init_nic(void)
6273 {
6274         return pci_register_driver(&driver);
6275 }
6276
6277 static void __exit exit_nic(void)
6278 {
6279         pci_unregister_driver(&driver);
6280 }
6281
6282 module_param(max_interrupt_work, int, 0);
6283 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6284 module_param(optimization_mode, int, 0);
6285 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6286 module_param(poll_interval, int, 0);
6287 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6288 module_param(msi, int, 0);
6289 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6290 module_param(msix, int, 0);
6291 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6292 module_param(dma_64bit, int, 0);
6293 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6294 module_param(phy_cross, int, 0);
6295 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6296 module_param(phy_power_down, int, 0);
6297 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6298 module_param(debug_tx_timeout, bool, 0);
6299 MODULE_PARM_DESC(debug_tx_timeout,
6300                  "Dump tx related registers and ring when tx_timeout happens");
6301
6302 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6303 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6304 MODULE_LICENSE("GPL");
6305
6306 MODULE_DEVICE_TABLE(pci, pci_tbl);
6307
6308 module_init(init_nic);
6309 module_exit(exit_nic);