2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/driver.h>
49 #include <linux/mlx4/doorbell.h>
50 #include <linux/mlx4/cmd.h>
52 #define DRV_NAME "mlx4_core"
53 #define PFX DRV_NAME ": "
54 #define DRV_VERSION "1.1"
55 #define DRV_RELDATE "Dec, 2011"
57 #define MLX4_FS_UDP_UC_EN (1 << 1)
58 #define MLX4_FS_TCP_UC_EN (1 << 2)
59 #define MLX4_FS_NUM_OF_L2_ADDR 8
60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61 #define MLX4_FS_NUM_MCG (1 << 17)
65 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
66 #define MLX4_RATELIMIT_DEFAULT 0xffff
68 struct mlx4_set_port_prio2tc_context {
72 struct mlx4_port_scheduler_tc_cfg_be {
75 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
79 struct mlx4_set_port_scheduler_context {
80 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
84 MLX4_HCR_BASE = 0x80680,
85 MLX4_HCR_SIZE = 0x0001c,
86 MLX4_CLR_INT_SIZE = 0x00008,
87 MLX4_SLAVE_COMM_BASE = 0x0,
88 MLX4_COMM_PAGESIZE = 0x1000
92 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
93 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
94 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
95 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
96 MLX4_MTT_ENTRY_PER_SEG = 8,
100 MLX4_NUM_PDS = 1 << 15
104 MLX4_CMPT_TYPE_QP = 0,
105 MLX4_CMPT_TYPE_SRQ = 1,
106 MLX4_CMPT_TYPE_CQ = 2,
107 MLX4_CMPT_TYPE_EQ = 3,
112 MLX4_CMPT_SHIFT = 24,
113 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
117 MLX4_MR_DISABLED = 0,
122 #define MLX4_COMM_TIME 10000
128 MLX4_COMM_CMD_VHCR_EN,
129 MLX4_COMM_CMD_VHCR_POST,
130 MLX4_COMM_CMD_FLR = 254
133 /*The flag indicates that the slave should delay the RESET cmd*/
134 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
135 /*indicates how many retries will be done if we are in the middle of FLR*/
136 #define NUM_OF_RESET_RETRIES 10
137 #define SLEEP_TIME_IN_RESET (2 * 1000)
150 MLX4_NUM_OF_RESOURCE_TYPE
153 enum mlx4_alloc_mode {
155 RES_OP_RESERVE_AND_MAP,
159 enum mlx4_res_tracker_free_type {
161 RES_TR_FREE_SLAVES_ONLY,
162 RES_TR_FREE_STRUCTS_ONLY,
166 *Virtual HCR structures.
167 * mlx4_vhcr is the sw representation, in machine endianess
169 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
170 * to FW to go through communication channel.
171 * It is big endian, and has the same structure as the physical HCR
172 * used by command interface
185 struct mlx4_vhcr_cmd {
196 struct mlx4_cmd_info {
201 bool encode_slave_id;
202 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
203 struct mlx4_cmd_mailbox *inbox);
204 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
205 struct mlx4_cmd_mailbox *inbox,
206 struct mlx4_cmd_mailbox *outbox,
207 struct mlx4_cmd_info *cmd);
210 #ifdef CONFIG_MLX4_DEBUG
211 extern int mlx4_debug_level;
212 #else /* CONFIG_MLX4_DEBUG */
213 #define mlx4_debug_level (0)
214 #endif /* CONFIG_MLX4_DEBUG */
216 #define mlx4_dbg(mdev, format, arg...) \
218 if (mlx4_debug_level) \
219 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
222 #define mlx4_err(mdev, format, arg...) \
223 dev_err(&mdev->pdev->dev, format, ##arg)
224 #define mlx4_info(mdev, format, arg...) \
225 dev_info(&mdev->pdev->dev, format, ##arg)
226 #define mlx4_warn(mdev, format, arg...) \
227 dev_warn(&mdev->pdev->dev, format, ##arg)
229 extern int mlx4_log_num_mgm_entry_size;
230 extern int log_mtts_per_seg;
232 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
233 #define ALL_SLAVES 0xff
243 unsigned long *table;
247 unsigned long **bits;
248 unsigned int *num_free;
255 struct mlx4_icm_table {
263 struct mlx4_icm **icm;
267 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
269 struct mlx4_mpt_entry {
283 __be32 first_byte_offset;
287 * Must be packed because start is 64 bits but only aligned to 32 bits.
289 struct mlx4_eq_context {
303 __be32 mtt_base_addr_l;
305 __be32 consumer_index;
306 __be32 producer_index;
310 struct mlx4_cq_context {
314 __be32 logsize_usrpage;
322 __be32 mtt_base_addr_l;
323 __be32 last_notified_index;
324 __be32 solicit_producer_index;
325 __be32 consumer_index;
326 __be32 producer_index;
331 struct mlx4_srq_context {
332 __be32 state_logsize_srqn;
336 __be32 pg_offset_cqn;
341 __be32 mtt_base_addr_l;
343 __be16 limit_watermark;
352 struct mlx4_dev *dev;
353 void __iomem *doorbell;
359 struct mlx4_buf_list *page_list;
363 struct mlx4_slave_eqe {
369 struct mlx4_slave_event_eq_info {
374 struct mlx4_profile {
388 struct mlx4_icm *fw_icm;
389 struct mlx4_icm *aux_icm;
403 MLX4_MCAST_CONFIG = 0,
404 MLX4_MCAST_DISABLE = 1,
405 MLX4_MCAST_ENABLE = 2,
408 #define VLAN_FLTR_SIZE 128
410 struct mlx4_vlan_fltr {
411 __be32 entry[VLAN_FLTR_SIZE];
414 struct mlx4_mcast_entry {
415 struct list_head list;
419 struct mlx4_promisc_qp {
420 struct list_head list;
424 struct mlx4_steer_index {
425 struct list_head list;
427 struct list_head duplicates;
430 #define MLX4_EVENT_TYPES_NUM 64
432 struct mlx4_slave_state {
439 u16 mtu[MLX4_MAX_PORTS + 1];
440 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
441 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
442 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
443 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
444 /* event type to eq number lookup */
445 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
449 /*initialized via the kzalloc*/
450 u8 is_slave_going_down;
452 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
457 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
460 struct mlx4_resource_tracker {
462 /* tree for each resources */
463 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
464 /* num_of_slave's lists, one per slave */
465 struct slave_list *slave_list;
468 #define SLAVE_EVENT_EQ_SIZE 128
469 struct mlx4_slave_event_eq {
473 spinlock_t event_lock;
474 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
477 struct mlx4_master_qp0_state {
478 int proxy_qp0_active;
483 struct mlx4_mfunc_master_ctx {
484 struct mlx4_slave_state *slave_state;
485 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
486 int init_port_ref[MLX4_MAX_PORTS + 1];
487 u16 max_mtu[MLX4_MAX_PORTS + 1];
488 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
489 struct mlx4_resource_tracker res_tracker;
490 struct workqueue_struct *comm_wq;
491 struct work_struct comm_work;
492 struct work_struct slave_event_work;
493 struct work_struct slave_flr_event_work;
494 spinlock_t slave_state_lock;
495 __be32 comm_arm_bit_vector[4];
496 struct mlx4_eqe cmd_eqe;
497 struct mlx4_slave_event_eq slave_eq;
498 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
502 struct mlx4_comm __iomem *comm;
503 struct mlx4_vhcr_cmd *vhcr;
506 struct mlx4_mfunc_master_ctx master;
510 struct pci_pool *pool;
512 struct mutex hcr_mutex;
513 struct mutex slave_cmd_mutex;
514 struct semaphore poll_sem;
515 struct semaphore event_sem;
517 spinlock_t context_lock;
519 struct mlx4_cmd_context *context;
526 struct mlx4_uar_table {
527 struct mlx4_bitmap bitmap;
530 struct mlx4_mr_table {
531 struct mlx4_bitmap mpt_bitmap;
532 struct mlx4_buddy mtt_buddy;
535 struct mlx4_icm_table mtt_table;
536 struct mlx4_icm_table dmpt_table;
539 struct mlx4_cq_table {
540 struct mlx4_bitmap bitmap;
542 struct radix_tree_root tree;
543 struct mlx4_icm_table table;
544 struct mlx4_icm_table cmpt_table;
547 struct mlx4_eq_table {
548 struct mlx4_bitmap bitmap;
550 void __iomem *clr_int;
551 void __iomem **uar_map;
554 struct mlx4_icm_table table;
555 struct mlx4_icm_table cmpt_table;
560 struct mlx4_srq_table {
561 struct mlx4_bitmap bitmap;
563 struct radix_tree_root tree;
564 struct mlx4_icm_table table;
565 struct mlx4_icm_table cmpt_table;
568 struct mlx4_qp_table {
569 struct mlx4_bitmap bitmap;
573 struct mlx4_icm_table qp_table;
574 struct mlx4_icm_table auxc_table;
575 struct mlx4_icm_table altc_table;
576 struct mlx4_icm_table rdmarc_table;
577 struct mlx4_icm_table cmpt_table;
580 struct mlx4_mcg_table {
582 struct mlx4_bitmap bitmap;
583 struct mlx4_icm_table table;
586 struct mlx4_catas_err {
588 struct timer_list timer;
589 struct list_head list;
592 #define MLX4_MAX_MAC_NUM 128
593 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
595 struct mlx4_mac_table {
596 __be64 entries[MLX4_MAX_MAC_NUM];
597 int refs[MLX4_MAX_MAC_NUM];
603 #define MLX4_MAX_VLAN_NUM 128
604 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
606 struct mlx4_vlan_table {
607 __be32 entries[MLX4_MAX_VLAN_NUM];
608 int refs[MLX4_MAX_VLAN_NUM];
614 #define SET_PORT_GEN_ALL_VALID 0x7
615 #define SET_PORT_PROMISC_SHIFT 31
616 #define SET_PORT_MC_PROMISC_SHIFT 30
619 MCAST_DIRECT_ONLY = 0,
625 struct mlx4_set_port_general_context {
638 struct mlx4_set_port_rqp_calc_context {
656 struct mlx4_port_info {
657 struct mlx4_dev *dev;
660 struct device_attribute port_attr;
661 enum mlx4_port_type tmp_type;
662 char dev_mtu_name[16];
663 struct device_attribute port_mtu_attr;
664 struct mlx4_mac_table mac_table;
665 struct mlx4_vlan_table vlan_table;
670 struct mlx4_dev *dev;
671 u8 do_sense_port[MLX4_MAX_PORTS + 1];
672 u8 sense_allowed[MLX4_MAX_PORTS + 1];
673 struct delayed_work sense_poll;
676 struct mlx4_msix_ctl {
678 struct mutex pool_lock;
682 struct list_head promisc_qps[MLX4_NUM_STEERS];
683 struct list_head steer_entries[MLX4_NUM_STEERS];
686 struct mlx4_net_trans_rule_hw_ctrl {
696 struct mlx4_net_trans_rule_hw_ib {
707 struct mlx4_net_trans_rule_hw_eth {
720 u8 ether_type_enable;
726 struct mlx4_net_trans_rule_hw_tcp_udp {
740 struct mlx4_net_trans_rule_hw_ipv4 {
758 struct mlx4_net_trans_rule_hw_eth eth;
759 struct mlx4_net_trans_rule_hw_ib ib;
760 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
761 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
766 MLX4_PCI_DEV_IS_VF = 1 << 0,
767 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
773 struct list_head dev_list;
774 struct list_head ctx_list;
779 struct list_head pgdir_list;
780 struct mutex pgdir_mutex;
784 struct mlx4_mfunc mfunc;
786 struct mlx4_bitmap pd_bitmap;
787 struct mlx4_bitmap xrcd_bitmap;
788 struct mlx4_uar_table uar_table;
789 struct mlx4_mr_table mr_table;
790 struct mlx4_cq_table cq_table;
791 struct mlx4_eq_table eq_table;
792 struct mlx4_srq_table srq_table;
793 struct mlx4_qp_table qp_table;
794 struct mlx4_mcg_table mcg_table;
795 struct mlx4_bitmap counters_bitmap;
797 struct mlx4_catas_err catas_err;
799 void __iomem *clr_base;
801 struct mlx4_uar driver_uar;
803 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
804 struct mlx4_sense sense;
805 struct mutex port_mutex;
806 struct mlx4_msix_ctl msix_ctl;
807 struct mlx4_steer *steer;
808 struct list_head bf_list;
809 struct mutex bf_mutex;
810 struct io_mapping *bf_mapping;
813 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
814 __be64 slave_node_guids[MLX4_MFUNC_MAX];
818 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
820 return container_of(dev, struct mlx4_priv, dev);
823 #define MLX4_SENSE_RANGE (HZ * 3)
825 extern struct workqueue_struct *mlx4_wq;
827 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
828 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
829 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
830 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
831 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
832 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
833 u32 reserved_bot, u32 resetrved_top);
834 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
836 int mlx4_reset(struct mlx4_dev *dev);
838 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
839 void mlx4_free_eq_table(struct mlx4_dev *dev);
841 int mlx4_init_pd_table(struct mlx4_dev *dev);
842 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
843 int mlx4_init_uar_table(struct mlx4_dev *dev);
844 int mlx4_init_mr_table(struct mlx4_dev *dev);
845 int mlx4_init_eq_table(struct mlx4_dev *dev);
846 int mlx4_init_cq_table(struct mlx4_dev *dev);
847 int mlx4_init_qp_table(struct mlx4_dev *dev);
848 int mlx4_init_srq_table(struct mlx4_dev *dev);
849 int mlx4_init_mcg_table(struct mlx4_dev *dev);
851 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
852 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
853 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
854 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
855 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
856 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
857 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
858 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
859 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
860 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
861 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
862 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
863 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
864 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
865 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
866 int __mlx4_mr_reserve(struct mlx4_dev *dev);
867 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
868 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
869 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
870 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
871 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
873 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
874 struct mlx4_vhcr *vhcr,
875 struct mlx4_cmd_mailbox *inbox,
876 struct mlx4_cmd_mailbox *outbox,
877 struct mlx4_cmd_info *cmd);
878 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
879 struct mlx4_vhcr *vhcr,
880 struct mlx4_cmd_mailbox *inbox,
881 struct mlx4_cmd_mailbox *outbox,
882 struct mlx4_cmd_info *cmd);
883 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
884 struct mlx4_vhcr *vhcr,
885 struct mlx4_cmd_mailbox *inbox,
886 struct mlx4_cmd_mailbox *outbox,
887 struct mlx4_cmd_info *cmd);
888 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
889 struct mlx4_vhcr *vhcr,
890 struct mlx4_cmd_mailbox *inbox,
891 struct mlx4_cmd_mailbox *outbox,
892 struct mlx4_cmd_info *cmd);
893 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
894 struct mlx4_vhcr *vhcr,
895 struct mlx4_cmd_mailbox *inbox,
896 struct mlx4_cmd_mailbox *outbox,
897 struct mlx4_cmd_info *cmd);
898 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
899 struct mlx4_vhcr *vhcr,
900 struct mlx4_cmd_mailbox *inbox,
901 struct mlx4_cmd_mailbox *outbox,
902 struct mlx4_cmd_info *cmd);
903 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
904 struct mlx4_vhcr *vhcr,
905 struct mlx4_cmd_mailbox *inbox,
906 struct mlx4_cmd_mailbox *outbox,
907 struct mlx4_cmd_info *cmd);
908 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
910 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
911 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
912 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
913 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
914 int start_index, int npages, u64 *page_list);
915 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
916 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
917 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
918 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
920 void mlx4_start_catas_poll(struct mlx4_dev *dev);
921 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
922 void mlx4_catas_init(void);
923 int mlx4_restart_one(struct pci_dev *pdev);
924 int mlx4_register_device(struct mlx4_dev *dev);
925 void mlx4_unregister_device(struct mlx4_dev *dev);
926 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
927 unsigned long param);
930 struct mlx4_init_hca_param;
932 u64 mlx4_make_profile(struct mlx4_dev *dev,
933 struct mlx4_profile *request,
934 struct mlx4_dev_cap *dev_cap,
935 struct mlx4_init_hca_param *init_hca);
936 void mlx4_master_comm_channel(struct work_struct *work);
937 void mlx4_gen_slave_eqe(struct work_struct *work);
938 void mlx4_master_handle_slave_flr(struct work_struct *work);
940 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
941 struct mlx4_vhcr *vhcr,
942 struct mlx4_cmd_mailbox *inbox,
943 struct mlx4_cmd_mailbox *outbox,
944 struct mlx4_cmd_info *cmd);
945 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
946 struct mlx4_vhcr *vhcr,
947 struct mlx4_cmd_mailbox *inbox,
948 struct mlx4_cmd_mailbox *outbox,
949 struct mlx4_cmd_info *cmd);
950 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
951 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
952 struct mlx4_cmd_mailbox *outbox,
953 struct mlx4_cmd_info *cmd);
954 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
955 struct mlx4_vhcr *vhcr,
956 struct mlx4_cmd_mailbox *inbox,
957 struct mlx4_cmd_mailbox *outbox,
958 struct mlx4_cmd_info *cmd);
959 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
960 struct mlx4_vhcr *vhcr,
961 struct mlx4_cmd_mailbox *inbox,
962 struct mlx4_cmd_mailbox *outbox,
963 struct mlx4_cmd_info *cmd);
964 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
965 struct mlx4_vhcr *vhcr,
966 struct mlx4_cmd_mailbox *inbox,
967 struct mlx4_cmd_mailbox *outbox,
968 struct mlx4_cmd_info *cmd);
969 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
970 struct mlx4_vhcr *vhcr,
971 struct mlx4_cmd_mailbox *inbox,
972 struct mlx4_cmd_mailbox *outbox,
973 struct mlx4_cmd_info *cmd);
974 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
975 struct mlx4_vhcr *vhcr,
976 struct mlx4_cmd_mailbox *inbox,
977 struct mlx4_cmd_mailbox *outbox,
978 struct mlx4_cmd_info *cmd);
979 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
980 struct mlx4_vhcr *vhcr,
981 struct mlx4_cmd_mailbox *inbox,
982 struct mlx4_cmd_mailbox *outbox,
983 struct mlx4_cmd_info *cmd);
984 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
985 struct mlx4_vhcr *vhcr,
986 struct mlx4_cmd_mailbox *inbox,
987 struct mlx4_cmd_mailbox *outbox,
988 struct mlx4_cmd_info *cmd);
989 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
990 struct mlx4_vhcr *vhcr,
991 struct mlx4_cmd_mailbox *inbox,
992 struct mlx4_cmd_mailbox *outbox,
993 struct mlx4_cmd_info *cmd);
994 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
995 struct mlx4_vhcr *vhcr,
996 struct mlx4_cmd_mailbox *inbox,
997 struct mlx4_cmd_mailbox *outbox,
998 struct mlx4_cmd_info *cmd);
999 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1000 struct mlx4_vhcr *vhcr,
1001 struct mlx4_cmd_mailbox *inbox,
1002 struct mlx4_cmd_mailbox *outbox,
1003 struct mlx4_cmd_info *cmd);
1004 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1005 struct mlx4_vhcr *vhcr,
1006 struct mlx4_cmd_mailbox *inbox,
1007 struct mlx4_cmd_mailbox *outbox,
1008 struct mlx4_cmd_info *cmd);
1009 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1010 struct mlx4_vhcr *vhcr,
1011 struct mlx4_cmd_mailbox *inbox,
1012 struct mlx4_cmd_mailbox *outbox,
1013 struct mlx4_cmd_info *cmd);
1014 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1015 struct mlx4_vhcr *vhcr,
1016 struct mlx4_cmd_mailbox *inbox,
1017 struct mlx4_cmd_mailbox *outbox,
1018 struct mlx4_cmd_info *cmd);
1019 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1020 struct mlx4_vhcr *vhcr,
1021 struct mlx4_cmd_mailbox *inbox,
1022 struct mlx4_cmd_mailbox *outbox,
1023 struct mlx4_cmd_info *cmd);
1024 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1025 struct mlx4_vhcr *vhcr,
1026 struct mlx4_cmd_mailbox *inbox,
1027 struct mlx4_cmd_mailbox *outbox,
1028 struct mlx4_cmd_info *cmd);
1029 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1030 struct mlx4_vhcr *vhcr,
1031 struct mlx4_cmd_mailbox *inbox,
1032 struct mlx4_cmd_mailbox *outbox,
1033 struct mlx4_cmd_info *cmd);
1034 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1035 struct mlx4_vhcr *vhcr,
1036 struct mlx4_cmd_mailbox *inbox,
1037 struct mlx4_cmd_mailbox *outbox,
1038 struct mlx4_cmd_info *cmd);
1039 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1040 struct mlx4_vhcr *vhcr,
1041 struct mlx4_cmd_mailbox *inbox,
1042 struct mlx4_cmd_mailbox *outbox,
1043 struct mlx4_cmd_info *cmd);
1044 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1045 struct mlx4_vhcr *vhcr,
1046 struct mlx4_cmd_mailbox *inbox,
1047 struct mlx4_cmd_mailbox *outbox,
1048 struct mlx4_cmd_info *cmd);
1049 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1050 struct mlx4_vhcr *vhcr,
1051 struct mlx4_cmd_mailbox *inbox,
1052 struct mlx4_cmd_mailbox *outbox,
1053 struct mlx4_cmd_info *cmd);
1054 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1055 struct mlx4_vhcr *vhcr,
1056 struct mlx4_cmd_mailbox *inbox,
1057 struct mlx4_cmd_mailbox *outbox,
1058 struct mlx4_cmd_info *cmd);
1059 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1060 struct mlx4_vhcr *vhcr,
1061 struct mlx4_cmd_mailbox *inbox,
1062 struct mlx4_cmd_mailbox *outbox,
1063 struct mlx4_cmd_info *cmd);
1064 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1065 struct mlx4_vhcr *vhcr,
1066 struct mlx4_cmd_mailbox *inbox,
1067 struct mlx4_cmd_mailbox *outbox,
1068 struct mlx4_cmd_info *cmd);
1069 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1070 struct mlx4_vhcr *vhcr,
1071 struct mlx4_cmd_mailbox *inbox,
1072 struct mlx4_cmd_mailbox *outbox,
1073 struct mlx4_cmd_info *cmd);
1075 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1077 int mlx4_cmd_init(struct mlx4_dev *dev);
1078 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1079 int mlx4_multi_func_init(struct mlx4_dev *dev);
1080 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1081 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1082 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1083 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1085 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1086 unsigned long timeout);
1088 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1089 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1091 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1093 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1095 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1097 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1098 enum mlx4_port_type *type);
1099 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1100 enum mlx4_port_type *stype,
1101 enum mlx4_port_type *defaults);
1102 void mlx4_start_sense(struct mlx4_dev *dev);
1103 void mlx4_stop_sense(struct mlx4_dev *dev);
1104 void mlx4_sense_init(struct mlx4_dev *dev);
1105 int mlx4_check_port_params(struct mlx4_dev *dev,
1106 enum mlx4_port_type *port_type);
1107 int mlx4_change_port_types(struct mlx4_dev *dev,
1108 enum mlx4_port_type *port_types);
1110 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1111 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1113 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1114 /* resource tracker functions*/
1115 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1116 enum mlx4_resource resource_type,
1117 u64 resource_id, int *slave);
1118 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1119 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1121 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1122 enum mlx4_res_tracker_free_type type);
1124 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1125 struct mlx4_vhcr *vhcr,
1126 struct mlx4_cmd_mailbox *inbox,
1127 struct mlx4_cmd_mailbox *outbox,
1128 struct mlx4_cmd_info *cmd);
1129 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1130 struct mlx4_vhcr *vhcr,
1131 struct mlx4_cmd_mailbox *inbox,
1132 struct mlx4_cmd_mailbox *outbox,
1133 struct mlx4_cmd_info *cmd);
1134 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1135 struct mlx4_vhcr *vhcr,
1136 struct mlx4_cmd_mailbox *inbox,
1137 struct mlx4_cmd_mailbox *outbox,
1138 struct mlx4_cmd_info *cmd);
1139 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1140 struct mlx4_vhcr *vhcr,
1141 struct mlx4_cmd_mailbox *inbox,
1142 struct mlx4_cmd_mailbox *outbox,
1143 struct mlx4_cmd_info *cmd);
1144 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1145 struct mlx4_vhcr *vhcr,
1146 struct mlx4_cmd_mailbox *inbox,
1147 struct mlx4_cmd_mailbox *outbox,
1148 struct mlx4_cmd_info *cmd);
1149 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1150 struct mlx4_vhcr *vhcr,
1151 struct mlx4_cmd_mailbox *inbox,
1152 struct mlx4_cmd_mailbox *outbox,
1153 struct mlx4_cmd_info *cmd);
1154 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1156 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1157 int *gid_tbl_len, int *pkey_tbl_len);
1159 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1160 struct mlx4_vhcr *vhcr,
1161 struct mlx4_cmd_mailbox *inbox,
1162 struct mlx4_cmd_mailbox *outbox,
1163 struct mlx4_cmd_info *cmd);
1165 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1166 struct mlx4_vhcr *vhcr,
1167 struct mlx4_cmd_mailbox *inbox,
1168 struct mlx4_cmd_mailbox *outbox,
1169 struct mlx4_cmd_info *cmd);
1170 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1171 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1172 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1173 int block_mcast_loopback, enum mlx4_protocol prot,
1174 enum mlx4_steer_type steer);
1175 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1176 struct mlx4_vhcr *vhcr,
1177 struct mlx4_cmd_mailbox *inbox,
1178 struct mlx4_cmd_mailbox *outbox,
1179 struct mlx4_cmd_info *cmd);
1180 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1181 struct mlx4_vhcr *vhcr,
1182 struct mlx4_cmd_mailbox *inbox,
1183 struct mlx4_cmd_mailbox *outbox,
1184 struct mlx4_cmd_info *cmd);
1185 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1186 int port, void *buf);
1187 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1188 struct mlx4_cmd_mailbox *outbox);
1189 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1190 struct mlx4_vhcr *vhcr,
1191 struct mlx4_cmd_mailbox *inbox,
1192 struct mlx4_cmd_mailbox *outbox,
1193 struct mlx4_cmd_info *cmd);
1194 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1195 struct mlx4_vhcr *vhcr,
1196 struct mlx4_cmd_mailbox *inbox,
1197 struct mlx4_cmd_mailbox *outbox,
1198 struct mlx4_cmd_info *cmd);
1199 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1200 struct mlx4_vhcr *vhcr,
1201 struct mlx4_cmd_mailbox *inbox,
1202 struct mlx4_cmd_mailbox *outbox,
1203 struct mlx4_cmd_info *cmd);
1204 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1205 struct mlx4_vhcr *vhcr,
1206 struct mlx4_cmd_mailbox *inbox,
1207 struct mlx4_cmd_mailbox *outbox,
1208 struct mlx4_cmd_info *cmd);
1209 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1210 struct mlx4_vhcr *vhcr,
1211 struct mlx4_cmd_mailbox *inbox,
1212 struct mlx4_cmd_mailbox *outbox,
1213 struct mlx4_cmd_info *cmd);
1215 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1216 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1218 static inline void set_param_l(u64 *arg, u32 val)
1220 *((u32 *)arg) = val;
1223 static inline void set_param_h(u64 *arg, u32 val)
1225 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1228 static inline u32 get_param_l(u64 *arg)
1230 return (u32) (*arg & 0xffffffff);
1233 static inline u32 get_param_h(u64 *arg)
1235 return (u32)(*arg >> 32);
1238 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1240 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1243 #define NOT_MASKED_PD_BITS 17