Pileus Git - ~andy/linux/blob - drivers/net/ethernet/mellanox/mlx4/main.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/init.h>
  38 #include <linux/errno.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/io-mapping.h>
  43 #include <linux/delay.h>
  44 #include <linux/netdevice.h>
  45 #include <linux/kmod.h>
  46
  47 #include <linux/mlx4/device.h>
  48 #include <linux/mlx4/doorbell.h>
  49
  50 #include "mlx4.h"
  51 #include "fw.h"
  52 #include "icm.h"
  53
  54 MODULE_AUTHOR("Roland Dreier");
  55 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  56 MODULE_LICENSE("Dual BSD/GPL");
  57 MODULE_VERSION(DRV_VERSION);
  58
  59 struct workqueue_struct *mlx4_wq;
  60
  61 #ifdef CONFIG_MLX4_DEBUG
  62
  63 int mlx4_debug_level = 0;
  64 module_param_named(debug_level, mlx4_debug_level, int, 0644);
  65 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  66
  67 #endif /* CONFIG_MLX4_DEBUG */
  68
  69 #ifdef CONFIG_PCI_MSI
  70
  71 static int msi_x = 1;
  72 module_param(msi_x, int, 0444);
  73 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  74
  75 #else /* CONFIG_PCI_MSI */
  76
  77 #define msi_x (0)
  78
  79 #endif /* CONFIG_PCI_MSI */
  80
  81 static int num_vfs;
  82 module_param(num_vfs, int, 0444);
  83 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
  84
  85 static int probe_vf;
  86 module_param(probe_vf, int, 0644);
  87 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
  88
  89 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
  90 module_param_named(log_num_mgm_entry_size,
  91                         mlx4_log_num_mgm_entry_size, int, 0444);
  92 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
  93                                          " of qp per mcg, for example:"
  94                                          " 10 gives 248.range: 7 <="
  95                                          " log_num_mgm_entry_size <= 12."
  96                                          " To activate device managed"
  97                                          " flow steering when available, set to -1");
  98
  99 static bool enable_64b_cqe_eqe = true;
 100 module_param(enable_64b_cqe_eqe, bool, 0444);
 101 MODULE_PARM_DESC(enable_64b_cqe_eqe,
 102                  "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
 103
 104 #define HCA_GLOBAL_CAP_MASK            0
 105
 106 #define PF_CONTEXT_BEHAVIOUR_MASK       MLX4_FUNC_CAP_64B_EQE_CQE
 107
 108 static char mlx4_version[] =
 109         DRV_NAME ": Mellanox ConnectX core driver v"
 110         DRV_VERSION " (" DRV_RELDATE ")\n";
 111
 112 static struct mlx4_profile default_profile = {
 113         .num_qp         = 1 << 18,
 114         .num_srq        = 1 << 16,
 115         .rdmarc_per_qp  = 1 << 4,
 116         .num_cq         = 1 << 16,
 117         .num_mcg        = 1 << 13,
 118         .num_mpt        = 1 << 19,
 119         .num_mtt        = 1 << 20, /* It is really num mtt segements */
 120 };
 121
 122 static int log_num_mac = 7;
 123 module_param_named(log_num_mac, log_num_mac, int, 0444);
 124 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
 125
 126 static int log_num_vlan;
 127 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
 128 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
 129 /* Log2 max number of VLANs per ETH port (0-7) */
 130 #define MLX4_LOG_NUM_VLANS 7
 131
 132 static bool use_prio;
 133 module_param_named(use_prio, use_prio, bool, 0444);
 134 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
 135                   "(0/1, default 0)");
 136
 137 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
 138 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
 139 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
 140
 141 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
 142 static int arr_argc = 2;
 143 module_param_array(port_type_array, int, &arr_argc, 0444);
 144 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
 145                                 "1 for IB, 2 for Ethernet");
 146
 147 struct mlx4_port_config {
 148         struct list_head list;
 149         enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
 150         struct pci_dev *pdev;
 151 };
 152
 153 int mlx4_check_port_params(struct mlx4_dev *dev,
 154                            enum mlx4_port_type *port_type)
 155 {
 156         int i;
 157
 158         for (i = 0; i < dev->caps.num_ports - 1; i++) {
 159                 if (port_type[i] != port_type[i + 1]) {
 160                         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 161                                 mlx4_err(dev, "Only same port types supported "
 162                                          "on this HCA, aborting.\n");
 163                                 return -EINVAL;
 164                         }
 165                 }
 166         }
 167
 168         for (i = 0; i < dev->caps.num_ports; i++) {
 169                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
 170                         mlx4_err(dev, "Requested port type for port %d is not "
 171                                       "supported on this HCA\n", i + 1);
 172                         return -EINVAL;
 173                 }
 174         }
 175         return 0;
 176 }
 177
 178 static void mlx4_set_port_mask(struct mlx4_dev *dev)
 179 {
 180         int i;
 181
 182         for (i = 1; i <= dev->caps.num_ports; ++i)
 183                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 184 }
 185
 186 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 187 {
 188         int err;
 189         int i;
 190
 191         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
 192         if (err) {
 193                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 194                 return err;
 195         }
 196
 197         if (dev_cap->min_page_sz > PAGE_SIZE) {
 198                 mlx4_err(dev, "HCA minimum page size of %d bigger than "
 199                          "kernel PAGE_SIZE of %ld, aborting.\n",
 200                          dev_cap->min_page_sz, PAGE_SIZE);
 201                 return -ENODEV;
 202         }
 203         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
 204                 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
 205                          "aborting.\n",
 206                          dev_cap->num_ports, MLX4_MAX_PORTS);
 207                 return -ENODEV;
 208         }
 209
 210         if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
 211                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
 212                          "PCI resource 2 size of 0x%llx, aborting.\n",
 213                          dev_cap->uar_size,
 214                          (unsigned long long) pci_resource_len(dev->pdev, 2));
 215                 return -ENODEV;
 216         }
 217
 218         dev->caps.num_ports          = dev_cap->num_ports;
 219         dev->phys_caps.num_phys_eqs  = MLX4_MAX_EQ_NUM;
 220         for (i = 1; i <= dev->caps.num_ports; ++i) {
 221                 dev->caps.vl_cap[i]         = dev_cap->max_vl[i];
 222                 dev->caps.ib_mtu_cap[i]     = dev_cap->ib_mtu[i];
 223                 dev->phys_caps.gid_phys_table_len[i]  = dev_cap->max_gids[i];
 224                 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
 225                 /* set gid and pkey table operating lengths by default
 226                  * to non-sriov values */
 227                 dev->caps.gid_table_len[i]  = dev_cap->max_gids[i];
 228                 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
 229                 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
 230                 dev->caps.eth_mtu_cap[i]    = dev_cap->eth_mtu[i];
 231                 dev->caps.def_mac[i]        = dev_cap->def_mac[i];
 232                 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
 233                 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
 234                 dev->caps.default_sense[i] = dev_cap->default_sense[i];
 235                 dev->caps.trans_type[i]     = dev_cap->trans_type[i];
 236                 dev->caps.vendor_oui[i]     = dev_cap->vendor_oui[i];
 237                 dev->caps.wavelength[i]     = dev_cap->wavelength[i];
 238                 dev->caps.trans_code[i]     = dev_cap->trans_code[i];
 239         }
 240
 241         dev->caps.uar_page_size      = PAGE_SIZE;
 242         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
 243         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
 244         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
 245         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
 246         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
 247         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
 248         dev->caps.max_wqes           = dev_cap->max_qp_sz;
 249         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
 250         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
 251         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
 252         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
 253         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
 254         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
 255         /*
 256          * Subtract 1 from the limit because we need to allocate a
 257          * spare CQE so the HCA HW can tell the difference between an
 258          * empty CQ and a full CQ.
 259          */
 260         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
 261         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
 262         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
 263         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
 264         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
 265
 266         /* The first 128 UARs are used for EQ doorbells */
 267         dev->caps.reserved_uars      = max_t(int, 128, dev_cap->reserved_uars);
 268         dev->caps.reserved_pds       = dev_cap->reserved_pds;
 269         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 270                                         dev_cap->reserved_xrcds : 0;
 271         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 272                                         dev_cap->max_xrcds : 0;
 273         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
 274
 275         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
 276         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
 277         dev->caps.flags              = dev_cap->flags;
 278         dev->caps.flags2             = dev_cap->flags2;
 279         dev->caps.bmme_flags         = dev_cap->bmme_flags;
 280         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
 281         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
 282         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
 283         dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
 284
 285         /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
 286         if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
 287                 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 288         /* Don't do sense port on multifunction devices (for now at least) */
 289         if (mlx4_is_mfunc(dev))
 290                 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 291
 292         dev->caps.log_num_macs  = log_num_mac;
 293         dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
 294         dev->caps.log_num_prios = use_prio ? 3 : 0;
 295
 296         for (i = 1; i <= dev->caps.num_ports; ++i) {
 297                 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
 298                 if (dev->caps.supported_type[i]) {
 299                         /* if only ETH is supported - assign ETH */
 300                         if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
 301                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
 302                         /* if only IB is supported, assign IB */
 303                         else if (dev->caps.supported_type[i] ==
 304                                  MLX4_PORT_TYPE_IB)
 305                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
 306                         else {
 307                                 /* if IB and ETH are supported, we set the port
 308                                  * type according to user selection of port type;
 309                                  * if user selected none, take the FW hint */
 310                                 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
 311                                         dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
 312                                                 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
 313                                 else
 314                                         dev->caps.port_type[i] = port_type_array[i - 1];
 315                         }
 316                 }
 317                 /*
 318                  * Link sensing is allowed on the port if 3 conditions are true:
 319                  * 1. Both protocols are supported on the port.
 320                  * 2. Different types are supported on the port
 321                  * 3. FW declared that it supports link sensing
 322                  */
 323                 mlx4_priv(dev)->sense.sense_allowed[i] =
 324                         ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
 325                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 326                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
 327
 328                 /*
 329                  * If "default_sense" bit is set, we move the port to "AUTO" mode
 330                  * and perform sense_port FW command to try and set the correct
 331                  * port type from beginning
 332                  */
 333                 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
 334                         enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
 335                         dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
 336                         mlx4_SENSE_PORT(dev, i, &sensed_port);
 337                         if (sensed_port != MLX4_PORT_TYPE_NONE)
 338                                 dev->caps.port_type[i] = sensed_port;
 339                 } else {
 340                         dev->caps.possible_type[i] = dev->caps.port_type[i];
 341                 }
 342
 343                 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
 344                         dev->caps.log_num_macs = dev_cap->log_max_macs[i];
 345                         mlx4_warn(dev, "Requested number of MACs is too much "
 346                                   "for port %d, reducing to %d.\n",
 347                                   i, 1 << dev->caps.log_num_macs);
 348                 }
 349                 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
 350                         dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
 351                         mlx4_warn(dev, "Requested number of VLANs is too much "
 352                                   "for port %d, reducing to %d.\n",
 353                                   i, 1 << dev->caps.log_num_vlans);
 354                 }
 355         }
 356
 357         dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
 358
 359         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
 360         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
 361                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
 362                 (1 << dev->caps.log_num_macs) *
 363                 (1 << dev->caps.log_num_vlans) *
 364                 (1 << dev->caps.log_num_prios) *
 365                 dev->caps.num_ports;
 366         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
 367
 368         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
 369                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
 370                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
 371                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
 372
 373         dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
 374
 375         if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
 376                 if (dev_cap->flags &
 377                     (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
 378                         mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
 379                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 380                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 381                 }
 382         }
 383
 384         if ((dev->caps.flags &
 385             (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
 386             mlx4_is_master(dev))
 387                 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
 388
 389         return 0;
 390 }
 391 /*The function checks if there are live vf, return the num of them*/
 392 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
 393 {
 394         struct mlx4_priv *priv = mlx4_priv(dev);
 395         struct mlx4_slave_state *s_state;
 396         int i;
 397         int ret = 0;
 398
 399         for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
 400                 s_state = &priv->mfunc.master.slave_state[i];
 401                 if (s_state->active && s_state->last_cmd !=
 402                     MLX4_COMM_CMD_RESET) {
 403                         mlx4_warn(dev, "%s: slave: %d is still active\n",
 404                                   __func__, i);
 405                         ret++;
 406                 }
 407         }
 408         return ret;
 409 }
 410
 411 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
 412 {
 413         u32 qk = MLX4_RESERVED_QKEY_BASE;
 414
 415         if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
 416             qpn < dev->phys_caps.base_proxy_sqpn)
 417                 return -EINVAL;
 418
 419         if (qpn >= dev->phys_caps.base_tunnel_sqpn)
 420                 /* tunnel qp */
 421                 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
 422         else
 423                 qk += qpn - dev->phys_caps.base_proxy_sqpn;
 424         *qkey = qk;
 425         return 0;
 426 }
 427 EXPORT_SYMBOL(mlx4_get_parav_qkey);
 428
 429 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
 430 {
 431         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 432
 433         if (!mlx4_is_master(dev))
 434                 return;
 435
 436         priv->virt2phys_pkey[slave][port - 1][i] = val;
 437 }
 438 EXPORT_SYMBOL(mlx4_sync_pkey_table);
 439
 440 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
 441 {
 442         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 443
 444         if (!mlx4_is_master(dev))
 445                 return;
 446
 447         priv->slave_node_guids[slave] = guid;
 448 }
 449 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
 450
 451 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
 452 {
 453         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 454
 455         if (!mlx4_is_master(dev))
 456                 return 0;
 457
 458         return priv->slave_node_guids[slave];
 459 }
 460 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
 461
 462 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
 463 {
 464         struct mlx4_priv *priv = mlx4_priv(dev);
 465         struct mlx4_slave_state *s_slave;
 466
 467         if (!mlx4_is_master(dev))
 468                 return 0;
 469
 470         s_slave = &priv->mfunc.master.slave_state[slave];
 471         return !!s_slave->active;
 472 }
 473 EXPORT_SYMBOL(mlx4_is_slave_active);
 474
 475 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
 476                                        struct mlx4_dev_cap *dev_cap,
 477                                        struct mlx4_init_hca_param *hca_param)
 478 {
 479         dev->caps.steering_mode = hca_param->steering_mode;
 480         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
 481                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
 482                 dev->caps.fs_log_max_ucast_qp_range_size =
 483                         dev_cap->fs_log_max_ucast_qp_range_size;
 484         } else
 485                 dev->caps.num_qp_per_mgm =
 486                         4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
 487
 488         mlx4_dbg(dev, "Steering mode is: %s\n",
 489                  mlx4_steering_mode_str(dev->caps.steering_mode));
 490 }
 491
 492 static int mlx4_slave_cap(struct mlx4_dev *dev)
 493 {
 494         int                        err;
 495         u32                        page_size;
 496         struct mlx4_dev_cap        dev_cap;
 497         struct mlx4_func_cap       func_cap;
 498         struct mlx4_init_hca_param hca_param;
 499         int                        i;
 500
 501         memset(&hca_param, 0, sizeof(hca_param));
 502         err = mlx4_QUERY_HCA(dev, &hca_param);
 503         if (err) {
 504                 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
 505                 return err;
 506         }
 507
 508         /*fail if the hca has an unknown capability */
 509         if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
 510             HCA_GLOBAL_CAP_MASK) {
 511                 mlx4_err(dev, "Unknown hca global capabilities\n");
 512                 return -ENOSYS;
 513         }
 514
 515         mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
 516
 517         dev->caps.hca_core_clock = hca_param.hca_core_clock;
 518
 519         memset(&dev_cap, 0, sizeof(dev_cap));
 520         dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
 521         err = mlx4_dev_cap(dev, &dev_cap);
 522         if (err) {
 523                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 524                 return err;
 525         }
 526
 527         err = mlx4_QUERY_FW(dev);
 528         if (err)
 529                 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
 530
 531         page_size = ~dev->caps.page_size_cap + 1;
 532         mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
 533         if (page_size > PAGE_SIZE) {
 534                 mlx4_err(dev, "HCA minimum page size of %d bigger than "
 535                          "kernel PAGE_SIZE of %ld, aborting.\n",
 536                          page_size, PAGE_SIZE);
 537                 return -ENODEV;
 538         }
 539
 540         /* slave gets uar page size from QUERY_HCA fw command */
 541         dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
 542
 543         /* TODO: relax this assumption */
 544         if (dev->caps.uar_page_size != PAGE_SIZE) {
 545                 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
 546                          dev->caps.uar_page_size, PAGE_SIZE);
 547                 return -ENODEV;
 548         }
 549
 550         memset(&func_cap, 0, sizeof(func_cap));
 551         err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
 552         if (err) {
 553                 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
 554                           err);
 555                 return err;
 556         }
 557
 558         if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
 559             PF_CONTEXT_BEHAVIOUR_MASK) {
 560                 mlx4_err(dev, "Unknown pf context behaviour\n");
 561                 return -ENOSYS;
 562         }
 563
 564         dev->caps.num_ports             = func_cap.num_ports;
 565         dev->quotas.qp                  = func_cap.qp_quota;
 566         dev->quotas.srq                 = func_cap.srq_quota;
 567         dev->quotas.cq                  = func_cap.cq_quota;
 568         dev->quotas.mpt                 = func_cap.mpt_quota;
 569         dev->quotas.mtt                 = func_cap.mtt_quota;
 570         dev->caps.num_qps               = 1 << hca_param.log_num_qps;
 571         dev->caps.num_srqs              = 1 << hca_param.log_num_srqs;
 572         dev->caps.num_cqs               = 1 << hca_param.log_num_cqs;
 573         dev->caps.num_mpts              = 1 << hca_param.log_mpt_sz;
 574         dev->caps.num_eqs               = func_cap.max_eq;
 575         dev->caps.reserved_eqs          = func_cap.reserved_eq;
 576         dev->caps.num_pds               = MLX4_NUM_PDS;
 577         dev->caps.num_mgms              = 0;
 578         dev->caps.num_amgms             = 0;
 579
 580         if (dev->caps.num_ports > MLX4_MAX_PORTS) {
 581                 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
 582                          "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
 583                 return -ENODEV;
 584         }
 585
 586         dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 587         dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 588         dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 589         dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 590
 591         if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
 592             !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
 593                 err = -ENOMEM;
 594                 goto err_mem;
 595         }
 596
 597         for (i = 1; i <= dev->caps.num_ports; ++i) {
 598                 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
 599                 if (err) {
 600                         mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
 601                                  " port %d, aborting (%d).\n", i, err);
 602                         goto err_mem;
 603                 }
 604                 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
 605                 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
 606                 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
 607                 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
 608                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 609                 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
 610                 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
 611                                                     &dev->caps.gid_table_len[i],
 612                                                     &dev->caps.pkey_table_len[i]))
 613                         goto err_mem;
 614         }
 615
 616         if (dev->caps.uar_page_size * (dev->caps.num_uars -
 617                                        dev->caps.reserved_uars) >
 618                                        pci_resource_len(dev->pdev, 2)) {
 619                 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
 620                          "PCI resource 2 size of 0x%llx, aborting.\n",
 621                          dev->caps.uar_page_size * dev->caps.num_uars,
 622                          (unsigned long long) pci_resource_len(dev->pdev, 2));
 623                 goto err_mem;
 624         }
 625
 626         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
 627                 dev->caps.eqe_size   = 64;
 628                 dev->caps.eqe_factor = 1;
 629         } else {
 630                 dev->caps.eqe_size   = 32;
 631                 dev->caps.eqe_factor = 0;
 632         }
 633
 634         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
 635                 dev->caps.cqe_size   = 64;
 636                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
 637         } else {
 638                 dev->caps.cqe_size   = 32;
 639         }
 640
 641         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
 642         mlx4_warn(dev, "Timestamping is not supported in slave mode.\n");
 643
 644         slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
 645
 646         return 0;
 647
 648 err_mem:
 649         kfree(dev->caps.qp0_tunnel);
 650         kfree(dev->caps.qp0_proxy);
 651         kfree(dev->caps.qp1_tunnel);
 652         kfree(dev->caps.qp1_proxy);
 653         dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
 654                 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
 655
 656         return err;
 657 }
 658
 659 static void mlx4_request_modules(struct mlx4_dev *dev)
 660 {
 661         int port;
 662         int has_ib_port = false;
 663         int has_eth_port = false;
 664 #define EN_DRV_NAME     "mlx4_en"
 665 #define IB_DRV_NAME     "mlx4_ib"
 666
 667         for (port = 1; port <= dev->caps.num_ports; port++) {
 668                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
 669                         has_ib_port = true;
 670                 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
 671                         has_eth_port = true;
 672         }
 673
 674         if (has_ib_port)
 675                 request_module_nowait(IB_DRV_NAME);
 676         if (has_eth_port)
 677                 request_module_nowait(EN_DRV_NAME);
 678 }
 679
 680 /*
 681  * Change the port configuration of the device.
 682  * Every user of this function must hold the port mutex.
 683  */
 684 int mlx4_change_port_types(struct mlx4_dev *dev,
 685                            enum mlx4_port_type *port_types)
 686 {
 687         int err = 0;
 688         int change = 0;
 689         int port;
 690
 691         for (port = 0; port <  dev->caps.num_ports; port++) {
 692                 /* Change the port type only if the new type is different
 693                  * from the current, and not set to Auto */
 694                 if (port_types[port] != dev->caps.port_type[port + 1])
 695                         change = 1;
 696         }
 697         if (change) {
 698                 mlx4_unregister_device(dev);
 699                 for (port = 1; port <= dev->caps.num_ports; port++) {
 700                         mlx4_CLOSE_PORT(dev, port);
 701                         dev->caps.port_type[port] = port_types[port - 1];
 702                         err = mlx4_SET_PORT(dev, port, -1);
 703                         if (err) {
 704                                 mlx4_err(dev, "Failed to set port %d, "
 705                                               "aborting\n", port);
 706                                 goto out;
 707                         }
 708                 }
 709                 mlx4_set_port_mask(dev);
 710                 err = mlx4_register_device(dev);
 711                 if (err) {
 712                         mlx4_err(dev, "Failed to register device\n");
 713                         goto out;
 714                 }
 715                 mlx4_request_modules(dev);
 716         }
 717
 718 out:
 719         return err;
 720 }
 721
 722 static ssize_t show_port_type(struct device *dev,
 723                               struct device_attribute *attr,
 724                               char *buf)
 725 {
 726         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 727                                                    port_attr);
 728         struct mlx4_dev *mdev = info->dev;
 729         char type[8];
 730
 731         sprintf(type, "%s",
 732                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
 733                 "ib" : "eth");
 734         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
 735                 sprintf(buf, "auto (%s)\n", type);
 736         else
 737                 sprintf(buf, "%s\n", type);
 738
 739         return strlen(buf);
 740 }
 741
 742 static ssize_t set_port_type(struct device *dev,
 743                              struct device_attribute *attr,
 744                              const char *buf, size_t count)
 745 {
 746         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 747                                                    port_attr);
 748         struct mlx4_dev *mdev = info->dev;
 749         struct mlx4_priv *priv = mlx4_priv(mdev);
 750         enum mlx4_port_type types[MLX4_MAX_PORTS];
 751         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
 752         int i;
 753         int err = 0;
 754
 755         if (!strcmp(buf, "ib\n"))
 756                 info->tmp_type = MLX4_PORT_TYPE_IB;
 757         else if (!strcmp(buf, "eth\n"))
 758                 info->tmp_type = MLX4_PORT_TYPE_ETH;
 759         else if (!strcmp(buf, "auto\n"))
 760                 info->tmp_type = MLX4_PORT_TYPE_AUTO;
 761         else {
 762                 mlx4_err(mdev, "%s is not supported port type\n", buf);
 763                 return -EINVAL;
 764         }
 765
 766         mlx4_stop_sense(mdev);
 767         mutex_lock(&priv->port_mutex);
 768         /* Possible type is always the one that was delivered */
 769         mdev->caps.possible_type[info->port] = info->tmp_type;
 770
 771         for (i = 0; i < mdev->caps.num_ports; i++) {
 772                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
 773                                         mdev->caps.possible_type[i+1];
 774                 if (types[i] == MLX4_PORT_TYPE_AUTO)
 775                         types[i] = mdev->caps.port_type[i+1];
 776         }
 777
 778         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 779             !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
 780                 for (i = 1; i <= mdev->caps.num_ports; i++) {
 781                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
 782                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
 783                                 err = -EINVAL;
 784                         }
 785                 }
 786         }
 787         if (err) {
 788                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
 789                                "Set only 'eth' or 'ib' for both ports "
 790                                "(should be the same)\n");
 791                 goto out;
 792         }
 793
 794         mlx4_do_sense_ports(mdev, new_types, types);
 795
 796         err = mlx4_check_port_params(mdev, new_types);
 797         if (err)
 798                 goto out;
 799
 800         /* We are about to apply the changes after the configuration
 801          * was verified, no need to remember the temporary types
 802          * any more */
 803         for (i = 0; i < mdev->caps.num_ports; i++)
 804                 priv->port[i + 1].tmp_type = 0;
 805
 806         err = mlx4_change_port_types(mdev, new_types);
 807
 808 out:
 809         mlx4_start_sense(mdev);
 810         mutex_unlock(&priv->port_mutex);
 811         return err ? err : count;
 812 }
 813
 814 enum ibta_mtu {
 815         IB_MTU_256  = 1,
 816         IB_MTU_512  = 2,
 817         IB_MTU_1024 = 3,
 818         IB_MTU_2048 = 4,
 819         IB_MTU_4096 = 5
 820 };
 821
 822 static inline int int_to_ibta_mtu(int mtu)
 823 {
 824         switch (mtu) {
 825         case 256:  return IB_MTU_256;
 826         case 512:  return IB_MTU_512;
 827         case 1024: return IB_MTU_1024;
 828         case 2048: return IB_MTU_2048;
 829         case 4096: return IB_MTU_4096;
 830         default: return -1;
 831         }
 832 }
 833
 834 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
 835 {
 836         switch (mtu) {
 837         case IB_MTU_256:  return  256;
 838         case IB_MTU_512:  return  512;
 839         case IB_MTU_1024: return 1024;
 840         case IB_MTU_2048: return 2048;
 841         case IB_MTU_4096: return 4096;
 842         default: return -1;
 843         }
 844 }
 845
 846 static ssize_t show_port_ib_mtu(struct device *dev,
 847                              struct device_attribute *attr,
 848                              char *buf)
 849 {
 850         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 851                                                    port_mtu_attr);
 852         struct mlx4_dev *mdev = info->dev;
 853
 854         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
 855                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
 856
 857         sprintf(buf, "%d\n",
 858                         ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
 859         return strlen(buf);
 860 }
 861
 862 static ssize_t set_port_ib_mtu(struct device *dev,
 863                              struct device_attribute *attr,
 864                              const char *buf, size_t count)
 865 {
 866         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 867                                                    port_mtu_attr);
 868         struct mlx4_dev *mdev = info->dev;
 869         struct mlx4_priv *priv = mlx4_priv(mdev);
 870         int err, port, mtu, ibta_mtu = -1;
 871
 872         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
 873                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
 874                 return -EINVAL;
 875         }
 876
 877         err = kstrtoint(buf, 0, &mtu);
 878         if (!err)
 879                 ibta_mtu = int_to_ibta_mtu(mtu);
 880
 881         if (err || ibta_mtu < 0) {
 882                 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
 883                 return -EINVAL;
 884         }
 885
 886         mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
 887
 888         mlx4_stop_sense(mdev);
 889         mutex_lock(&priv->port_mutex);
 890         mlx4_unregister_device(mdev);
 891         for (port = 1; port <= mdev->caps.num_ports; port++) {
 892                 mlx4_CLOSE_PORT(mdev, port);
 893                 err = mlx4_SET_PORT(mdev, port, -1);
 894                 if (err) {
 895                         mlx4_err(mdev, "Failed to set port %d, "
 896                                       "aborting\n", port);
 897                         goto err_set_port;
 898                 }
 899         }
 900         err = mlx4_register_device(mdev);
 901 err_set_port:
 902         mutex_unlock(&priv->port_mutex);
 903         mlx4_start_sense(mdev);
 904         return err ? err : count;
 905 }
 906
 907 static int mlx4_load_fw(struct mlx4_dev *dev)
 908 {
 909         struct mlx4_priv *priv = mlx4_priv(dev);
 910         int err;
 911
 912         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
 913                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
 914         if (!priv->fw.fw_icm) {
 915                 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
 916                 return -ENOMEM;
 917         }
 918
 919         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
 920         if (err) {
 921                 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
 922                 goto err_free;
 923         }
 924
 925         err = mlx4_RUN_FW(dev);
 926         if (err) {
 927                 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
 928                 goto err_unmap_fa;
 929         }
 930
 931         return 0;
 932
 933 err_unmap_fa:
 934         mlx4_UNMAP_FA(dev);
 935
 936 err_free:
 937         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
 938         return err;
 939 }
 940
 941 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
 942                                 int cmpt_entry_sz)
 943 {
 944         struct mlx4_priv *priv = mlx4_priv(dev);
 945         int err;
 946         int num_eqs;
 947
 948         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
 949                                   cmpt_base +
 950                                   ((u64) (MLX4_CMPT_TYPE_QP *
 951                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 952                                   cmpt_entry_sz, dev->caps.num_qps,
 953                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 954                                   0, 0);
 955         if (err)
 956                 goto err;
 957
 958         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
 959                                   cmpt_base +
 960                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
 961                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 962                                   cmpt_entry_sz, dev->caps.num_srqs,
 963                                   dev->caps.reserved_srqs, 0, 0);
 964         if (err)
 965                 goto err_qp;
 966
 967         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
 968                                   cmpt_base +
 969                                   ((u64) (MLX4_CMPT_TYPE_CQ *
 970                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 971                                   cmpt_entry_sz, dev->caps.num_cqs,
 972                                   dev->caps.reserved_cqs, 0, 0);
 973         if (err)
 974                 goto err_srq;
 975
 976         num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
 977                   dev->caps.num_eqs;
 978         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
 979                                   cmpt_base +
 980                                   ((u64) (MLX4_CMPT_TYPE_EQ *
 981                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 982                                   cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
 983         if (err)
 984                 goto err_cq;
 985
 986         return 0;
 987
 988 err_cq:
 989         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
 990
 991 err_srq:
 992         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
 993
 994 err_qp:
 995         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
 996
 997 err:
 998         return err;
 999 }
1000
1001 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1002                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
1003 {
1004         struct mlx4_priv *priv = mlx4_priv(dev);
1005         u64 aux_pages;
1006         int num_eqs;
1007         int err;
1008
1009         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1010         if (err) {
1011                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
1012                 return err;
1013         }
1014
1015         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
1016                  (unsigned long long) icm_size >> 10,
1017                  (unsigned long long) aux_pages << 2);
1018
1019         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1020                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
1021         if (!priv->fw.aux_icm) {
1022                 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
1023                 return -ENOMEM;
1024         }
1025
1026         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1027         if (err) {
1028                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
1029                 goto err_free_aux;
1030         }
1031
1032         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1033         if (err) {
1034                 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1035                 goto err_unmap_aux;
1036         }
1037
1038
1039         num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1040                    dev->caps.num_eqs;
1041         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1042                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
1043                                   num_eqs, num_eqs, 0, 0);
1044         if (err) {
1045                 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1046                 goto err_unmap_cmpt;
1047         }
1048
1049         /*
1050          * Reserved MTT entries must be aligned up to a cacheline
1051          * boundary, since the FW will write to them, while the driver
1052          * writes to all other MTT entries. (The variable
1053          * dev->caps.mtt_entry_sz below is really the MTT segment
1054          * size, not the raw entry size)
1055          */
1056         dev->caps.reserved_mtts =
1057                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1058                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1059
1060         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1061                                   init_hca->mtt_base,
1062                                   dev->caps.mtt_entry_sz,
1063                                   dev->caps.num_mtts,
1064                                   dev->caps.reserved_mtts, 1, 0);
1065         if (err) {
1066                 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1067                 goto err_unmap_eq;
1068         }
1069
1070         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1071                                   init_hca->dmpt_base,
1072                                   dev_cap->dmpt_entry_sz,
1073                                   dev->caps.num_mpts,
1074                                   dev->caps.reserved_mrws, 1, 1);
1075         if (err) {
1076                 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1077                 goto err_unmap_mtt;
1078         }
1079
1080         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1081                                   init_hca->qpc_base,
1082                                   dev_cap->qpc_entry_sz,
1083                                   dev->caps.num_qps,
1084                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1085                                   0, 0);
1086         if (err) {
1087                 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1088                 goto err_unmap_dmpt;
1089         }
1090
1091         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1092                                   init_hca->auxc_base,
1093                                   dev_cap->aux_entry_sz,
1094                                   dev->caps.num_qps,
1095                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1096                                   0, 0);
1097         if (err) {
1098                 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1099                 goto err_unmap_qp;
1100         }
1101
1102         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1103                                   init_hca->altc_base,
1104                                   dev_cap->altc_entry_sz,
1105                                   dev->caps.num_qps,
1106                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1107                                   0, 0);
1108         if (err) {
1109                 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1110                 goto err_unmap_auxc;
1111         }
1112
1113         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1114                                   init_hca->rdmarc_base,
1115                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1116                                   dev->caps.num_qps,
1117                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1118                                   0, 0);
1119         if (err) {
1120                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1121                 goto err_unmap_altc;
1122         }
1123
1124         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1125                                   init_hca->cqc_base,
1126                                   dev_cap->cqc_entry_sz,
1127                                   dev->caps.num_cqs,
1128                                   dev->caps.reserved_cqs, 0, 0);
1129         if (err) {
1130                 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1131                 goto err_unmap_rdmarc;
1132         }
1133
1134         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1135                                   init_hca->srqc_base,
1136                                   dev_cap->srq_entry_sz,
1137                                   dev->caps.num_srqs,
1138                                   dev->caps.reserved_srqs, 0, 0);
1139         if (err) {
1140                 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1141                 goto err_unmap_cq;
1142         }
1143
1144         /*
1145          * For flow steering device managed mode it is required to use
1146          * mlx4_init_icm_table. For B0 steering mode it's not strictly
1147          * required, but for simplicity just map the whole multicast
1148          * group table now.  The table isn't very big and it's a lot
1149          * easier than trying to track ref counts.
1150          */
1151         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1152                                   init_hca->mc_base,
1153                                   mlx4_get_mgm_entry_size(dev),
1154                                   dev->caps.num_mgms + dev->caps.num_amgms,
1155                                   dev->caps.num_mgms + dev->caps.num_amgms,
1156                                   0, 0);
1157         if (err) {
1158                 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1159                 goto err_unmap_srq;
1160         }
1161
1162         return 0;
1163
1164 err_unmap_srq:
1165         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1166
1167 err_unmap_cq:
1168         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1169
1170 err_unmap_rdmarc:
1171         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1172
1173 err_unmap_altc:
1174         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1175
1176 err_unmap_auxc:
1177         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1178
1179 err_unmap_qp:
1180         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1181
1182 err_unmap_dmpt:
1183         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1184
1185 err_unmap_mtt:
1186         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1187
1188 err_unmap_eq:
1189         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1190
1191 err_unmap_cmpt:
1192         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1193         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1194         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1195         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1196
1197 err_unmap_aux:
1198         mlx4_UNMAP_ICM_AUX(dev);
1199
1200 err_free_aux:
1201         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1202
1203         return err;
1204 }
1205
1206 static void mlx4_free_icms(struct mlx4_dev *dev)
1207 {
1208         struct mlx4_priv *priv = mlx4_priv(dev);
1209
1210         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1211         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1212         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1213         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1214         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1215         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1216         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1217         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1218         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1219         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1220         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1221         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1222         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1223         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1224
1225         mlx4_UNMAP_ICM_AUX(dev);
1226         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1227 }
1228
1229 static void mlx4_slave_exit(struct mlx4_dev *dev)
1230 {
1231         struct mlx4_priv *priv = mlx4_priv(dev);
1232
1233         mutex_lock(&priv->cmd.slave_cmd_mutex);
1234         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1235                 mlx4_warn(dev, "Failed to close slave function.\n");
1236         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1237 }
1238
1239 static int map_bf_area(struct mlx4_dev *dev)
1240 {
1241         struct mlx4_priv *priv = mlx4_priv(dev);
1242         resource_size_t bf_start;
1243         resource_size_t bf_len;
1244         int err = 0;
1245
1246         if (!dev->caps.bf_reg_size)
1247                 return -ENXIO;
1248
1249         bf_start = pci_resource_start(dev->pdev, 2) +
1250                         (dev->caps.num_uars << PAGE_SHIFT);
1251         bf_len = pci_resource_len(dev->pdev, 2) -
1252                         (dev->caps.num_uars << PAGE_SHIFT);
1253         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1254         if (!priv->bf_mapping)
1255                 err = -ENOMEM;
1256
1257         return err;
1258 }
1259
1260 static void unmap_bf_area(struct mlx4_dev *dev)
1261 {
1262         if (mlx4_priv(dev)->bf_mapping)
1263                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1264 }
1265
1266 cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1267 {
1268         u32 clockhi, clocklo, clockhi1;
1269         cycle_t cycles;
1270         int i;
1271         struct mlx4_priv *priv = mlx4_priv(dev);
1272
1273         for (i = 0; i < 10; i++) {
1274                 clockhi = swab32(readl(priv->clock_mapping));
1275                 clocklo = swab32(readl(priv->clock_mapping + 4));
1276                 clockhi1 = swab32(readl(priv->clock_mapping));
1277                 if (clockhi == clockhi1)
1278                         break;
1279         }
1280
1281         cycles = (u64) clockhi << 32 | (u64) clocklo;
1282
1283         return cycles;
1284 }
1285 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1286
1287
1288 static int map_internal_clock(struct mlx4_dev *dev)
1289 {
1290         struct mlx4_priv *priv = mlx4_priv(dev);
1291
1292         priv->clock_mapping =
1293                 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1294                         priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1295
1296         if (!priv->clock_mapping)
1297                 return -ENOMEM;
1298
1299         return 0;
1300 }
1301
1302 static void unmap_internal_clock(struct mlx4_dev *dev)
1303 {
1304         struct mlx4_priv *priv = mlx4_priv(dev);
1305
1306         if (priv->clock_mapping)
1307                 iounmap(priv->clock_mapping);
1308 }
1309
1310 static void mlx4_close_hca(struct mlx4_dev *dev)
1311 {
1312         unmap_internal_clock(dev);
1313         unmap_bf_area(dev);
1314         if (mlx4_is_slave(dev))
1315                 mlx4_slave_exit(dev);
1316         else {
1317                 mlx4_CLOSE_HCA(dev, 0);
1318                 mlx4_free_icms(dev);
1319                 mlx4_UNMAP_FA(dev);
1320                 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1321         }
1322 }
1323
1324 static int mlx4_init_slave(struct mlx4_dev *dev)
1325 {
1326         struct mlx4_priv *priv = mlx4_priv(dev);
1327         u64 dma = (u64) priv->mfunc.vhcr_dma;
1328         int ret_from_reset = 0;
1329         u32 slave_read;
1330         u32 cmd_channel_ver;
1331
1332         mutex_lock(&priv->cmd.slave_cmd_mutex);
1333         priv->cmd.max_cmds = 1;
1334         mlx4_warn(dev, "Sending reset\n");
1335         ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1336                                        MLX4_COMM_TIME);
1337         /* if we are in the middle of flr the slave will try
1338          * NUM_OF_RESET_RETRIES times before leaving.*/
1339         if (ret_from_reset) {
1340                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1341                         mlx4_warn(dev, "slave is currently in the "
1342                                   "middle of FLR. Deferring probe.\n");
1343                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1344                         return -EPROBE_DEFER;
1345                 } else
1346                         goto err;
1347         }
1348
1349         /* check the driver version - the slave I/F revision
1350          * must match the master's */
1351         slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1352         cmd_channel_ver = mlx4_comm_get_version();
1353
1354         if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1355                 MLX4_COMM_GET_IF_REV(slave_read)) {
1356                 mlx4_err(dev, "slave driver version is not supported"
1357                          " by the master\n");
1358                 goto err;
1359         }
1360
1361         mlx4_warn(dev, "Sending vhcr0\n");
1362         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1363                                                     MLX4_COMM_TIME))
1364                 goto err;
1365         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1366                                                     MLX4_COMM_TIME))
1367                 goto err;
1368         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1369                                                     MLX4_COMM_TIME))
1370                 goto err;
1371         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1372                 goto err;
1373
1374         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1375         return 0;
1376
1377 err:
1378         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1379         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1380         return -EIO;
1381 }
1382
1383 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1384 {
1385         int i;
1386
1387         for (i = 1; i <= dev->caps.num_ports; i++) {
1388                 dev->caps.gid_table_len[i] = 1;
1389                 dev->caps.pkey_table_len[i] =
1390                         dev->phys_caps.pkey_phys_table_len[i] - 1;
1391         }
1392 }
1393
1394 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1395 {
1396         int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1397
1398         for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1399               i++) {
1400                 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1401                         break;
1402         }
1403
1404         return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1405 }
1406
1407 static void choose_steering_mode(struct mlx4_dev *dev,
1408                                  struct mlx4_dev_cap *dev_cap)
1409 {
1410         if (mlx4_log_num_mgm_entry_size == -1 &&
1411             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1412             (!mlx4_is_mfunc(dev) ||
1413              (dev_cap->fs_max_num_qp_per_entry >= (num_vfs + 1))) &&
1414             choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1415                 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1416                 dev->oper_log_mgm_entry_size =
1417                         choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1418                 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1419                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1420                 dev->caps.fs_log_max_ucast_qp_range_size =
1421                         dev_cap->fs_log_max_ucast_qp_range_size;
1422         } else {
1423                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1424                     dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1425                         dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1426                 else {
1427                         dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1428
1429                         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1430                             dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1431                                 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1432                                           "set to use B0 steering. Falling back to A0 steering mode.\n");
1433                 }
1434                 dev->oper_log_mgm_entry_size =
1435                         mlx4_log_num_mgm_entry_size > 0 ?
1436                         mlx4_log_num_mgm_entry_size :
1437                         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1438                 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1439         }
1440         mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1441                  "modparam log_num_mgm_entry_size = %d\n",
1442                  mlx4_steering_mode_str(dev->caps.steering_mode),
1443                  dev->oper_log_mgm_entry_size,
1444                  mlx4_log_num_mgm_entry_size);
1445 }
1446
1447 static int mlx4_init_hca(struct mlx4_dev *dev)
1448 {
1449         struct mlx4_priv          *priv = mlx4_priv(dev);
1450         struct mlx4_adapter        adapter;
1451         struct mlx4_dev_cap        dev_cap;
1452         struct mlx4_mod_stat_cfg   mlx4_cfg;
1453         struct mlx4_profile        profile;
1454         struct mlx4_init_hca_param init_hca;
1455         u64 icm_size;
1456         int err;
1457
1458         if (!mlx4_is_slave(dev)) {
1459                 err = mlx4_QUERY_FW(dev);
1460                 if (err) {
1461                         if (err == -EACCES)
1462                                 mlx4_info(dev, "non-primary physical function, skipping.\n");
1463                         else
1464                                 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1465                         return err;
1466                 }
1467
1468                 err = mlx4_load_fw(dev);
1469                 if (err) {
1470                         mlx4_err(dev, "Failed to start FW, aborting.\n");
1471                         return err;
1472                 }
1473
1474                 mlx4_cfg.log_pg_sz_m = 1;
1475                 mlx4_cfg.log_pg_sz = 0;
1476                 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1477                 if (err)
1478                         mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1479
1480                 err = mlx4_dev_cap(dev, &dev_cap);
1481                 if (err) {
1482                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1483                         goto err_stop_fw;
1484                 }
1485
1486                 choose_steering_mode(dev, &dev_cap);
1487
1488                 err = mlx4_get_phys_port_id(dev);
1489                 if (err)
1490                         mlx4_err(dev, "Fail to get physical port id\n");
1491
1492                 if (mlx4_is_master(dev))
1493                         mlx4_parav_master_pf_caps(dev);
1494
1495                 profile = default_profile;
1496                 if (dev->caps.steering_mode ==
1497                     MLX4_STEERING_MODE_DEVICE_MANAGED)
1498                         profile.num_mcg = MLX4_FS_NUM_MCG;
1499
1500                 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1501                                              &init_hca);
1502                 if ((long long) icm_size < 0) {
1503                         err = icm_size;
1504                         goto err_stop_fw;
1505                 }
1506
1507                 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1508
1509                 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1510                 init_hca.uar_page_sz = PAGE_SHIFT - 12;
1511                 init_hca.mw_enabled = 0;
1512                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1513                     dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1514                         init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
1515
1516                 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1517                 if (err)
1518                         goto err_stop_fw;
1519
1520                 err = mlx4_INIT_HCA(dev, &init_hca);
1521                 if (err) {
1522                         mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1523                         goto err_free_icm;
1524                 }
1525                 /*
1526                  * If TS is supported by FW
1527                  * read HCA frequency by QUERY_HCA command
1528                  */
1529                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1530                         memset(&init_hca, 0, sizeof(init_hca));
1531                         err = mlx4_QUERY_HCA(dev, &init_hca);
1532                         if (err) {
1533                                 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
1534                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1535                         } else {
1536                                 dev->caps.hca_core_clock =
1537                                         init_hca.hca_core_clock;
1538                         }
1539
1540                         /* In case we got HCA frequency 0 - disable timestamping
1541                          * to avoid dividing by zero
1542                          */
1543                         if (!dev->caps.hca_core_clock) {
1544                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1545                                 mlx4_err(dev,
1546                                          "HCA frequency is 0. Timestamping is not supported.");
1547                         } else if (map_internal_clock(dev)) {
1548                                 /*
1549                                  * Map internal clock,
1550                                  * in case of failure disable timestamping
1551                                  */
1552                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1553                                 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
1554                         }
1555                 }
1556         } else {
1557                 err = mlx4_init_slave(dev);
1558                 if (err) {
1559                         if (err != -EPROBE_DEFER)
1560                                 mlx4_err(dev, "Failed to initialize slave\n");
1561                         return err;
1562                 }
1563
1564                 err = mlx4_slave_cap(dev);
1565                 if (err) {
1566                         mlx4_err(dev, "Failed to obtain slave caps\n");
1567                         goto err_close;
1568                 }
1569         }
1570
1571         if (map_bf_area(dev))
1572                 mlx4_dbg(dev, "Failed to map blue flame area\n");
1573
1574         /*Only the master set the ports, all the rest got it from it.*/
1575         if (!mlx4_is_slave(dev))
1576                 mlx4_set_port_mask(dev);
1577
1578         err = mlx4_QUERY_ADAPTER(dev, &adapter);
1579         if (err) {
1580                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1581                 goto unmap_bf;
1582         }
1583
1584         priv->eq_table.inta_pin = adapter.inta_pin;
1585         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
1586
1587         return 0;
1588
1589 unmap_bf:
1590         unmap_internal_clock(dev);
1591         unmap_bf_area(dev);
1592
1593 err_close:
1594         if (mlx4_is_slave(dev))
1595                 mlx4_slave_exit(dev);
1596         else
1597                 mlx4_CLOSE_HCA(dev, 0);
1598
1599 err_free_icm:
1600         if (!mlx4_is_slave(dev))
1601                 mlx4_free_icms(dev);
1602
1603 err_stop_fw:
1604         if (!mlx4_is_slave(dev)) {
1605                 mlx4_UNMAP_FA(dev);
1606                 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1607         }
1608         return err;
1609 }
1610
1611 static int mlx4_init_counters_table(struct mlx4_dev *dev)
1612 {
1613         struct mlx4_priv *priv = mlx4_priv(dev);
1614         int nent;
1615
1616         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1617                 return -ENOENT;
1618
1619         nent = dev->caps.max_counters;
1620         return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1621 }
1622
1623 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1624 {
1625         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1626 }
1627
1628 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1629 {
1630         struct mlx4_priv *priv = mlx4_priv(dev);
1631
1632         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1633                 return -ENOENT;
1634
1635         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1636         if (*idx == -1)
1637                 return -ENOMEM;
1638
1639         return 0;
1640 }
1641
1642 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1643 {
1644         u64 out_param;
1645         int err;
1646
1647         if (mlx4_is_mfunc(dev)) {
1648                 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1649                                    RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1650                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1651                 if (!err)
1652                         *idx = get_param_l(&out_param);
1653
1654                 return err;
1655         }
1656         return __mlx4_counter_alloc(dev, idx);
1657 }
1658 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1659
1660 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1661 {
1662         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
1663         return;
1664 }
1665
1666 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1667 {
1668         u64 in_param = 0;
1669
1670         if (mlx4_is_mfunc(dev)) {
1671                 set_param_l(&in_param, idx);
1672                 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1673                          MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1674                          MLX4_CMD_WRAPPED);
1675                 return;
1676         }
1677         __mlx4_counter_free(dev, idx);
1678 }
1679 EXPORT_SYMBOL_GPL(mlx4_counter_free);
1680
1681 static int mlx4_setup_hca(struct mlx4_dev *dev)
1682 {
1683         struct mlx4_priv *priv = mlx4_priv(dev);
1684         int err;
1685         int port;
1686         __be32 ib_port_default_caps;
1687
1688         err = mlx4_init_uar_table(dev);
1689         if (err) {
1690                 mlx4_err(dev, "Failed to initialize "
1691                          "user access region table, aborting.\n");
1692                 return err;
1693         }
1694
1695         err = mlx4_uar_alloc(dev, &priv->driver_uar);
1696         if (err) {
1697                 mlx4_err(dev, "Failed to allocate driver access region, "
1698                          "aborting.\n");
1699                 goto err_uar_table_free;
1700         }
1701
1702         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1703         if (!priv->kar) {
1704                 mlx4_err(dev, "Couldn't map kernel access region, "
1705                          "aborting.\n");
1706                 err = -ENOMEM;
1707                 goto err_uar_free;
1708         }
1709
1710         err = mlx4_init_pd_table(dev);
1711         if (err) {
1712                 mlx4_err(dev, "Failed to initialize "
1713                          "protection domain table, aborting.\n");
1714                 goto err_kar_unmap;
1715         }
1716
1717         err = mlx4_init_xrcd_table(dev);
1718         if (err) {
1719                 mlx4_err(dev, "Failed to initialize "
1720                          "reliable connection domain table, aborting.\n");
1721                 goto err_pd_table_free;
1722         }
1723
1724         err = mlx4_init_mr_table(dev);
1725         if (err) {
1726                 mlx4_err(dev, "Failed to initialize "
1727                          "memory region table, aborting.\n");
1728                 goto err_xrcd_table_free;
1729         }
1730
1731         if (!mlx4_is_slave(dev)) {
1732                 err = mlx4_init_mcg_table(dev);
1733                 if (err) {
1734                         mlx4_err(dev, "Failed to initialize multicast group table, aborting.\n");
1735                         goto err_mr_table_free;
1736                 }
1737         }
1738
1739         err = mlx4_init_eq_table(dev);
1740         if (err) {
1741                 mlx4_err(dev, "Failed to initialize "
1742                          "event queue table, aborting.\n");
1743                 goto err_mcg_table_free;
1744         }
1745
1746         err = mlx4_cmd_use_events(dev);
1747         if (err) {
1748                 mlx4_err(dev, "Failed to switch to event-driven "
1749                          "firmware commands, aborting.\n");
1750                 goto err_eq_table_free;
1751         }
1752
1753         err = mlx4_NOP(dev);
1754         if (err) {
1755                 if (dev->flags & MLX4_FLAG_MSI_X) {
1756                         mlx4_warn(dev, "NOP command failed to generate MSI-X "
1757                                   "interrupt IRQ %d).\n",
1758                                   priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1759                         mlx4_warn(dev, "Trying again without MSI-X.\n");
1760                 } else {
1761                         mlx4_err(dev, "NOP command failed to generate interrupt "
1762                                  "(IRQ %d), aborting.\n",
1763                                  priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1764                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
1765                 }
1766
1767                 goto err_cmd_poll;
1768         }
1769
1770         mlx4_dbg(dev, "NOP command IRQ test passed\n");
1771
1772         err = mlx4_init_cq_table(dev);
1773         if (err) {
1774                 mlx4_err(dev, "Failed to initialize "
1775                          "completion queue table, aborting.\n");
1776                 goto err_cmd_poll;
1777         }
1778
1779         err = mlx4_init_srq_table(dev);
1780         if (err) {
1781                 mlx4_err(dev, "Failed to initialize "
1782                          "shared receive queue table, aborting.\n");
1783                 goto err_cq_table_free;
1784         }
1785
1786         err = mlx4_init_qp_table(dev);
1787         if (err) {
1788                 mlx4_err(dev, "Failed to initialize "
1789                          "queue pair table, aborting.\n");
1790                 goto err_srq_table_free;
1791         }
1792
1793         err = mlx4_init_counters_table(dev);
1794         if (err && err != -ENOENT) {
1795                 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1796                 goto err_qp_table_free;
1797         }
1798
1799         if (!mlx4_is_slave(dev)) {
1800                 for (port = 1; port <= dev->caps.num_ports; port++) {
1801                         ib_port_default_caps = 0;
1802                         err = mlx4_get_port_ib_caps(dev, port,
1803                                                     &ib_port_default_caps);
1804                         if (err)
1805                                 mlx4_warn(dev, "failed to get port %d default "
1806                                           "ib capabilities (%d). Continuing "
1807                                           "with caps = 0\n", port, err);
1808                         dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1809
1810                         /* initialize per-slave default ib port capabilities */
1811                         if (mlx4_is_master(dev)) {
1812                                 int i;
1813                                 for (i = 0; i < dev->num_slaves; i++) {
1814                                         if (i == mlx4_master_func_num(dev))
1815                                                 continue;
1816                                         priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1817                                                         ib_port_default_caps;
1818                                 }
1819                         }
1820
1821                         if (mlx4_is_mfunc(dev))
1822                                 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1823                         else
1824                                 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
1825
1826                         err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1827                                             dev->caps.pkey_table_len[port] : -1);
1828                         if (err) {
1829                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
1830                                         port);
1831                                 goto err_counters_table_free;
1832                         }
1833                 }
1834         }
1835
1836         return 0;
1837
1838 err_counters_table_free:
1839         mlx4_cleanup_counters_table(dev);
1840
1841 err_qp_table_free:
1842         mlx4_cleanup_qp_table(dev);
1843
1844 err_srq_table_free:
1845         mlx4_cleanup_srq_table(dev);
1846
1847 err_cq_table_free:
1848         mlx4_cleanup_cq_table(dev);
1849
1850 err_cmd_poll:
1851         mlx4_cmd_use_polling(dev);
1852
1853 err_eq_table_free:
1854         mlx4_cleanup_eq_table(dev);
1855
1856 err_mcg_table_free:
1857         if (!mlx4_is_slave(dev))
1858                 mlx4_cleanup_mcg_table(dev);
1859
1860 err_mr_table_free:
1861         mlx4_cleanup_mr_table(dev);
1862
1863 err_xrcd_table_free:
1864         mlx4_cleanup_xrcd_table(dev);
1865
1866 err_pd_table_free:
1867         mlx4_cleanup_pd_table(dev);
1868
1869 err_kar_unmap:
1870         iounmap(priv->kar);
1871
1872 err_uar_free:
1873         mlx4_uar_free(dev, &priv->driver_uar);
1874
1875 err_uar_table_free:
1876         mlx4_cleanup_uar_table(dev);
1877         return err;
1878 }
1879
1880 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1881 {
1882         struct mlx4_priv *priv = mlx4_priv(dev);
1883         struct msix_entry *entries;
1884         int nreq = min_t(int, dev->caps.num_ports *
1885                          min_t(int, netif_get_num_default_rss_queues() + 1,
1886                                MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
1887         int err;
1888         int i;
1889
1890         if (msi_x) {
1891                 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1892                              nreq);
1893
1894                 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1895                 if (!entries)
1896                         goto no_msi;
1897
1898                 for (i = 0; i < nreq; ++i)
1899                         entries[i].entry = i;
1900
1901         retry:
1902                 err = pci_enable_msix(dev->pdev, entries, nreq);
1903                 if (err) {
1904                         /* Try again if at least 2 vectors are available */
1905                         if (err > 1) {
1906                                 mlx4_info(dev, "Requested %d vectors, "
1907                                           "but only %d MSI-X vectors available, "
1908                                           "trying again\n", nreq, err);
1909                                 nreq = err;
1910                                 goto retry;
1911                         }
1912                         kfree(entries);
1913                         goto no_msi;
1914                 }
1915
1916                 if (nreq <
1917                     MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1918                         /*Working in legacy mode , all EQ's shared*/
1919                         dev->caps.comp_pool           = 0;
1920                         dev->caps.num_comp_vectors = nreq - 1;
1921                 } else {
1922                         dev->caps.comp_pool           = nreq - MSIX_LEGACY_SZ;
1923                         dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1924                 }
1925                 for (i = 0; i < nreq; ++i)
1926                         priv->eq_table.eq[i].irq = entries[i].vector;
1927
1928                 dev->flags |= MLX4_FLAG_MSI_X;
1929
1930                 kfree(entries);
1931                 return;
1932         }
1933
1934 no_msi:
1935         dev->caps.num_comp_vectors = 1;
1936         dev->caps.comp_pool        = 0;
1937
1938         for (i = 0; i < 2; ++i)
1939                 priv->eq_table.eq[i].irq = dev->pdev->irq;
1940 }
1941
1942 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1943 {
1944         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1945         int err = 0;
1946
1947         info->dev = dev;
1948         info->port = port;
1949         if (!mlx4_is_slave(dev)) {
1950                 mlx4_init_mac_table(dev, &info->mac_table);
1951                 mlx4_init_vlan_table(dev, &info->vlan_table);
1952                 info->base_qpn = mlx4_get_base_qpn(dev, port);
1953         }
1954
1955         sprintf(info->dev_name, "mlx4_port%d", port);
1956         info->port_attr.attr.name = info->dev_name;
1957         if (mlx4_is_mfunc(dev))
1958                 info->port_attr.attr.mode = S_IRUGO;
1959         else {
1960                 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1961                 info->port_attr.store     = set_port_type;
1962         }
1963         info->port_attr.show      = show_port_type;
1964         sysfs_attr_init(&info->port_attr.attr);
1965
1966         err = device_create_file(&dev->pdev->dev, &info->port_attr);
1967         if (err) {
1968                 mlx4_err(dev, "Failed to create file for port %d\n", port);
1969                 info->port = -1;
1970         }
1971
1972         sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
1973         info->port_mtu_attr.attr.name = info->dev_mtu_name;
1974         if (mlx4_is_mfunc(dev))
1975                 info->port_mtu_attr.attr.mode = S_IRUGO;
1976         else {
1977                 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
1978                 info->port_mtu_attr.store     = set_port_ib_mtu;
1979         }
1980         info->port_mtu_attr.show      = show_port_ib_mtu;
1981         sysfs_attr_init(&info->port_mtu_attr.attr);
1982
1983         err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
1984         if (err) {
1985                 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
1986                 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1987                 info->port = -1;
1988         }
1989
1990         return err;
1991 }
1992
1993 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1994 {
1995         if (info->port < 0)
1996                 return;
1997
1998         device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1999         device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2000 }
2001
2002 static int mlx4_init_steering(struct mlx4_dev *dev)
2003 {
2004         struct mlx4_priv *priv = mlx4_priv(dev);
2005         int num_entries = dev->caps.num_ports;
2006         int i, j;
2007
2008         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2009         if (!priv->steer)
2010                 return -ENOMEM;
2011
2012         for (i = 0; i < num_entries; i++)
2013                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2014                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2015                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2016                 }
2017         return 0;
2018 }
2019
2020 static void mlx4_clear_steering(struct mlx4_dev *dev)
2021 {
2022         struct mlx4_priv *priv = mlx4_priv(dev);
2023         struct mlx4_steer_index *entry, *tmp_entry;
2024         struct mlx4_promisc_qp *pqp, *tmp_pqp;
2025         int num_entries = dev->caps.num_ports;
2026         int i, j;
2027
2028         for (i = 0; i < num_entries; i++) {
2029                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2030                         list_for_each_entry_safe(pqp, tmp_pqp,
2031                                                  &priv->steer[i].promisc_qps[j],
2032                                                  list) {
2033                                 list_del(&pqp->list);
2034                                 kfree(pqp);
2035                         }
2036                         list_for_each_entry_safe(entry, tmp_entry,
2037                                                  &priv->steer[i].steer_entries[j],
2038                                                  list) {
2039                                 list_del(&entry->list);
2040                                 list_for_each_entry_safe(pqp, tmp_pqp,
2041                                                          &entry->duplicates,
2042                                                          list) {
2043                                         list_del(&pqp->list);
2044                                         kfree(pqp);
2045                                 }
2046                                 kfree(entry);
2047                         }
2048                 }
2049         }
2050         kfree(priv->steer);
2051 }
2052
2053 static int extended_func_num(struct pci_dev *pdev)
2054 {
2055         return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2056 }
2057
2058 #define MLX4_OWNER_BASE 0x8069c
2059 #define MLX4_OWNER_SIZE 4
2060
2061 static int mlx4_get_ownership(struct mlx4_dev *dev)
2062 {
2063         void __iomem *owner;
2064         u32 ret;
2065
2066         if (pci_channel_offline(dev->pdev))
2067                 return -EIO;
2068
2069         owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2070                         MLX4_OWNER_SIZE);
2071         if (!owner) {
2072                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2073                 return -ENOMEM;
2074         }
2075
2076         ret = readl(owner);
2077         iounmap(owner);
2078         return (int) !!ret;
2079 }
2080
2081 static void mlx4_free_ownership(struct mlx4_dev *dev)
2082 {
2083         void __iomem *owner;
2084
2085         if (pci_channel_offline(dev->pdev))
2086                 return;
2087
2088         owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2089                         MLX4_OWNER_SIZE);
2090         if (!owner) {
2091                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2092                 return;
2093         }
2094         writel(0, owner);
2095         msleep(1000);
2096         iounmap(owner);
2097 }
2098
2099 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
2100 {
2101         struct mlx4_priv *priv;
2102         struct mlx4_dev *dev;
2103         int err;
2104         int port;
2105
2106         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2107
2108         err = pci_enable_device(pdev);
2109         if (err) {
2110                 dev_err(&pdev->dev, "Cannot enable PCI device, "
2111                         "aborting.\n");
2112                 return err;
2113         }
2114
2115         /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2116          * per port, we must limit the number of VFs to 63 (since their are
2117          * 128 MACs)
2118          */
2119         if (num_vfs >= MLX4_MAX_NUM_VF) {
2120                 dev_err(&pdev->dev,
2121                         "Requested more VF's (%d) than allowed (%d)\n",
2122                         num_vfs, MLX4_MAX_NUM_VF - 1);
2123                 return -EINVAL;
2124         }
2125
2126         if (num_vfs < 0) {
2127                 pr_err("num_vfs module parameter cannot be negative\n");
2128                 return -EINVAL;
2129         }
2130         /*
2131          * Check for BARs.
2132          */
2133         if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
2134             !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2135                 dev_err(&pdev->dev, "Missing DCS, aborting."
2136                         "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2137                         pci_dev_data, pci_resource_flags(pdev, 0));
2138                 err = -ENODEV;
2139                 goto err_disable_pdev;
2140         }
2141         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2142                 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
2143                 err = -ENODEV;
2144                 goto err_disable_pdev;
2145         }
2146
2147         err = pci_request_regions(pdev, DRV_NAME);
2148         if (err) {
2149                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
2150                 goto err_disable_pdev;
2151         }
2152
2153         pci_set_master(pdev);
2154
2155         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2156         if (err) {
2157                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
2158                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2159                 if (err) {
2160                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
2161                         goto err_release_regions;
2162                 }
2163         }
2164         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2165         if (err) {
2166                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
2167                          "consistent PCI DMA mask.\n");
2168                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2169                 if (err) {
2170                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
2171                                 "aborting.\n");
2172                         goto err_release_regions;
2173                 }
2174         }
2175
2176         /* Allow large DMA segments, up to the firmware limit of 1 GB */
2177         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2178
2179         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2180         if (!priv) {
2181                 err = -ENOMEM;
2182                 goto err_release_regions;
2183         }
2184
2185         dev       = &priv->dev;
2186         dev->pdev = pdev;
2187         INIT_LIST_HEAD(&priv->ctx_list);
2188         spin_lock_init(&priv->ctx_lock);
2189
2190         mutex_init(&priv->port_mutex);
2191
2192         INIT_LIST_HEAD(&priv->pgdir_list);
2193         mutex_init(&priv->pgdir_mutex);
2194
2195         INIT_LIST_HEAD(&priv->bf_list);
2196         mutex_init(&priv->bf_mutex);
2197
2198         dev->rev_id = pdev->revision;
2199         dev->numa_node = dev_to_node(&pdev->dev);
2200         /* Detect if this device is a virtual function */
2201         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2202                 /* When acting as pf, we normally skip vfs unless explicitly
2203                  * requested to probe them. */
2204                 if (num_vfs && extended_func_num(pdev) > probe_vf) {
2205                         mlx4_warn(dev, "Skipping virtual function:%d\n",
2206                                                 extended_func_num(pdev));
2207                         err = -ENODEV;
2208                         goto err_free_dev;
2209                 }
2210                 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2211                 dev->flags |= MLX4_FLAG_SLAVE;
2212         } else {
2213                 /* We reset the device and enable SRIOV only for physical
2214                  * devices.  Try to claim ownership on the device;
2215                  * if already taken, skip -- do not allow multiple PFs */
2216                 err = mlx4_get_ownership(dev);
2217                 if (err) {
2218                         if (err < 0)
2219                                 goto err_free_dev;
2220                         else {
2221                                 mlx4_warn(dev, "Multiple PFs not yet supported."
2222                                           " Skipping PF.\n");
2223                                 err = -EINVAL;
2224                                 goto err_free_dev;
2225                         }
2226                 }
2227
2228                 if (num_vfs) {
2229                         mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", num_vfs);
2230                         err = pci_enable_sriov(pdev, num_vfs);
2231                         if (err) {
2232                                 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2233                                          err);
2234                                 err = 0;
2235                         } else {
2236                                 mlx4_warn(dev, "Running in master mode\n");
2237                                 dev->flags |= MLX4_FLAG_SRIOV |
2238                                               MLX4_FLAG_MASTER;
2239                                 dev->num_vfs = num_vfs;
2240                         }
2241                 }
2242
2243                 atomic_set(&priv->opreq_count, 0);
2244                 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2245
2246                 /*
2247                  * Now reset the HCA before we touch the PCI capabilities or
2248                  * attempt a firmware command, since a boot ROM may have left
2249                  * the HCA in an undefined state.
2250                  */
2251                 err = mlx4_reset(dev);
2252                 if (err) {
2253                         mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2254                         goto err_rel_own;
2255                 }
2256         }
2257
2258 slave_start:
2259         err = mlx4_cmd_init(dev);
2260         if (err) {
2261                 mlx4_err(dev, "Failed to init command interface, aborting.\n");
2262                 goto err_sriov;
2263         }
2264
2265         /* In slave functions, the communication channel must be initialized
2266          * before posting commands. Also, init num_slaves before calling
2267          * mlx4_init_hca */
2268         if (mlx4_is_mfunc(dev)) {
2269                 if (mlx4_is_master(dev))
2270                         dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2271                 else {
2272                         dev->num_slaves = 0;
2273                         err = mlx4_multi_func_init(dev);
2274                         if (err) {
2275                                 mlx4_err(dev, "Failed to init slave mfunc"
2276                                          " interface, aborting.\n");
2277                                 goto err_cmd;
2278                         }
2279                 }
2280         }
2281
2282         err = mlx4_init_hca(dev);
2283         if (err) {
2284                 if (err == -EACCES) {
2285                         /* Not primary Physical function
2286                          * Running in slave mode */
2287                         mlx4_cmd_cleanup(dev);
2288                         dev->flags |= MLX4_FLAG_SLAVE;
2289                         dev->flags &= ~MLX4_FLAG_MASTER;
2290                         goto slave_start;
2291                 } else
2292                         goto err_mfunc;
2293         }
2294
2295         /* In master functions, the communication channel must be initialized
2296          * after obtaining its address from fw */
2297         if (mlx4_is_master(dev)) {
2298                 err = mlx4_multi_func_init(dev);
2299                 if (err) {
2300                         mlx4_err(dev, "Failed to init master mfunc"
2301                                  "interface, aborting.\n");
2302                         goto err_close;
2303                 }
2304         }
2305
2306         err = mlx4_alloc_eq_table(dev);
2307         if (err)
2308                 goto err_master_mfunc;
2309
2310         priv->msix_ctl.pool_bm = 0;
2311         mutex_init(&priv->msix_ctl.pool_lock);
2312
2313         mlx4_enable_msi_x(dev);
2314         if ((mlx4_is_mfunc(dev)) &&
2315             !(dev->flags & MLX4_FLAG_MSI_X)) {
2316                 err = -ENOSYS;
2317                 mlx4_err(dev, "INTx is not supported in multi-function mode."
2318                          " aborting.\n");
2319                 goto err_free_eq;
2320         }
2321
2322         if (!mlx4_is_slave(dev)) {
2323                 err = mlx4_init_steering(dev);
2324                 if (err)
2325                         goto err_free_eq;
2326         }
2327
2328         err = mlx4_setup_hca(dev);
2329         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2330             !mlx4_is_mfunc(dev)) {
2331                 dev->flags &= ~MLX4_FLAG_MSI_X;
2332                 dev->caps.num_comp_vectors = 1;
2333                 dev->caps.comp_pool        = 0;
2334                 pci_disable_msix(pdev);
2335                 err = mlx4_setup_hca(dev);
2336         }
2337
2338         if (err)
2339                 goto err_steer;
2340
2341         mlx4_init_quotas(dev);
2342
2343         for (port = 1; port <= dev->caps.num_ports; port++) {
2344                 err = mlx4_init_port_info(dev, port);
2345                 if (err)
2346                         goto err_port;
2347         }
2348
2349         err = mlx4_register_device(dev);
2350         if (err)
2351                 goto err_port;
2352
2353         mlx4_request_modules(dev);
2354
2355         mlx4_sense_init(dev);
2356         mlx4_start_sense(dev);
2357
2358         priv->pci_dev_data = pci_dev_data;
2359         pci_set_drvdata(pdev, dev);
2360
2361         return 0;
2362
2363 err_port:
2364         for (--port; port >= 1; --port)
2365                 mlx4_cleanup_port_info(&priv->port[port]);
2366
2367         mlx4_cleanup_counters_table(dev);
2368         mlx4_cleanup_qp_table(dev);
2369         mlx4_cleanup_srq_table(dev);
2370         mlx4_cleanup_cq_table(dev);
2371         mlx4_cmd_use_polling(dev);
2372         mlx4_cleanup_eq_table(dev);
2373         mlx4_cleanup_mcg_table(dev);
2374         mlx4_cleanup_mr_table(dev);
2375         mlx4_cleanup_xrcd_table(dev);
2376         mlx4_cleanup_pd_table(dev);
2377         mlx4_cleanup_uar_table(dev);
2378
2379 err_steer:
2380         if (!mlx4_is_slave(dev))
2381                 mlx4_clear_steering(dev);
2382
2383 err_free_eq:
2384         mlx4_free_eq_table(dev);
2385
2386 err_master_mfunc:
2387         if (mlx4_is_master(dev))
2388                 mlx4_multi_func_cleanup(dev);
2389
2390 err_close:
2391         if (dev->flags & MLX4_FLAG_MSI_X)
2392                 pci_disable_msix(pdev);
2393
2394         mlx4_close_hca(dev);
2395
2396 err_mfunc:
2397         if (mlx4_is_slave(dev))
2398                 mlx4_multi_func_cleanup(dev);
2399
2400 err_cmd:
2401         mlx4_cmd_cleanup(dev);
2402
2403 err_sriov:
2404         if (dev->flags & MLX4_FLAG_SRIOV)
2405                 pci_disable_sriov(pdev);
2406
2407 err_rel_own:
2408         if (!mlx4_is_slave(dev))
2409                 mlx4_free_ownership(dev);
2410
2411 err_free_dev:
2412         kfree(priv);
2413
2414 err_release_regions:
2415         pci_release_regions(pdev);
2416
2417 err_disable_pdev:
2418         pci_disable_device(pdev);
2419         pci_set_drvdata(pdev, NULL);
2420         return err;
2421 }
2422
2423 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
2424 {
2425         printk_once(KERN_INFO "%s", mlx4_version);
2426
2427         return __mlx4_init_one(pdev, id->driver_data);
2428 }
2429
2430 static void mlx4_remove_one(struct pci_dev *pdev)
2431 {
2432         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
2433         struct mlx4_priv *priv = mlx4_priv(dev);
2434         int p;
2435
2436         if (dev) {
2437                 /* in SRIOV it is not allowed to unload the pf's
2438                  * driver while there are alive vf's */
2439                 if (mlx4_is_master(dev)) {
2440                         if (mlx4_how_many_lives_vf(dev))
2441                                 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2442                 }
2443                 mlx4_stop_sense(dev);
2444                 mlx4_unregister_device(dev);
2445
2446                 for (p = 1; p <= dev->caps.num_ports; p++) {
2447                         mlx4_cleanup_port_info(&priv->port[p]);
2448                         mlx4_CLOSE_PORT(dev, p);
2449                 }
2450
2451                 if (mlx4_is_master(dev))
2452                         mlx4_free_resource_tracker(dev,
2453                                                    RES_TR_FREE_SLAVES_ONLY);
2454
2455                 mlx4_cleanup_counters_table(dev);
2456                 mlx4_cleanup_qp_table(dev);
2457                 mlx4_cleanup_srq_table(dev);
2458                 mlx4_cleanup_cq_table(dev);
2459                 mlx4_cmd_use_polling(dev);
2460                 mlx4_cleanup_eq_table(dev);
2461                 mlx4_cleanup_mcg_table(dev);
2462                 mlx4_cleanup_mr_table(dev);
2463                 mlx4_cleanup_xrcd_table(dev);
2464                 mlx4_cleanup_pd_table(dev);
2465
2466                 if (mlx4_is_master(dev))
2467                         mlx4_free_resource_tracker(dev,
2468                                                    RES_TR_FREE_STRUCTS_ONLY);
2469
2470                 iounmap(priv->kar);
2471                 mlx4_uar_free(dev, &priv->driver_uar);
2472                 mlx4_cleanup_uar_table(dev);
2473                 if (!mlx4_is_slave(dev))
2474                         mlx4_clear_steering(dev);
2475                 mlx4_free_eq_table(dev);
2476                 if (mlx4_is_master(dev))
2477                         mlx4_multi_func_cleanup(dev);
2478                 mlx4_close_hca(dev);
2479                 if (mlx4_is_slave(dev))
2480                         mlx4_multi_func_cleanup(dev);
2481                 mlx4_cmd_cleanup(dev);
2482
2483                 if (dev->flags & MLX4_FLAG_MSI_X)
2484                         pci_disable_msix(pdev);
2485                 if (dev->flags & MLX4_FLAG_SRIOV) {
2486                         mlx4_warn(dev, "Disabling SR-IOV\n");
2487                         pci_disable_sriov(pdev);
2488                 }
2489
2490                 if (!mlx4_is_slave(dev))
2491                         mlx4_free_ownership(dev);
2492
2493                 kfree(dev->caps.qp0_tunnel);
2494                 kfree(dev->caps.qp0_proxy);
2495                 kfree(dev->caps.qp1_tunnel);
2496                 kfree(dev->caps.qp1_proxy);
2497
2498                 kfree(priv);
2499                 pci_release_regions(pdev);
2500                 pci_disable_device(pdev);
2501                 pci_set_drvdata(pdev, NULL);
2502         }
2503 }
2504
2505 int mlx4_restart_one(struct pci_dev *pdev)
2506 {
2507         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
2508         struct mlx4_priv *priv = mlx4_priv(dev);
2509         int               pci_dev_data;
2510
2511         pci_dev_data = priv->pci_dev_data;
2512         mlx4_remove_one(pdev);
2513         return __mlx4_init_one(pdev, pci_dev_data);
2514 }
2515
2516 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
2517         /* MT25408 "Hermon" SDR */
2518         { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2519         /* MT25408 "Hermon" DDR */
2520         { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2521         /* MT25408 "Hermon" QDR */
2522         { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2523         /* MT25408 "Hermon" DDR PCIe gen2 */
2524         { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2525         /* MT25408 "Hermon" QDR PCIe gen2 */
2526         { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2527         /* MT25408 "Hermon" EN 10GigE */
2528         { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2529         /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2530         { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2531         /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2532         { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2533         /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2534         { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2535         /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2536         { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2537         /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2538         { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2539         /* MT26478 ConnectX2 40GigE PCIe gen2 */
2540         { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2541         /* MT25400 Family [ConnectX-2 Virtual Function] */
2542         { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
2543         /* MT27500 Family [ConnectX-3] */
2544         { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2545         /* MT27500 Family [ConnectX-3 Virtual Function] */
2546         { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
2547         { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2548         { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2549         { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2550         { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2551         { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2552         { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2553         { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2554         { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2555         { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2556         { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2557         { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2558         { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
2559         { 0, }
2560 };
2561
2562 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2563
2564 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2565                                               pci_channel_state_t state)
2566 {
2567         mlx4_remove_one(pdev);
2568
2569         return state == pci_channel_io_perm_failure ?
2570                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2571 }
2572
2573 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2574 {
2575         int ret = __mlx4_init_one(pdev, 0);
2576
2577         return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2578 }
2579
2580 static const struct pci_error_handlers mlx4_err_handler = {
2581         .error_detected = mlx4_pci_err_detected,
2582         .slot_reset     = mlx4_pci_slot_reset,
2583 };
2584
2585 static struct pci_driver mlx4_driver = {
2586         .name           = DRV_NAME,
2587         .id_table       = mlx4_pci_table,
2588         .probe          = mlx4_init_one,
2589         .remove         = mlx4_remove_one,
2590         .err_handler    = &mlx4_err_handler,
2591 };
2592
2593 static int __init mlx4_verify_params(void)
2594 {
2595         if ((log_num_mac < 0) || (log_num_mac > 7)) {
2596                 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
2597                 return -1;
2598         }
2599
2600         if (log_num_vlan != 0)
2601                 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2602                            MLX4_LOG_NUM_VLANS);
2603
2604         if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
2605                 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
2606                 return -1;
2607         }
2608
2609         /* Check if module param for ports type has legal combination */
2610         if (port_type_array[0] == false && port_type_array[1] == true) {
2611                 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2612                 port_type_array[0] = true;
2613         }
2614
2615         if (mlx4_log_num_mgm_entry_size != -1 &&
2616             (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2617              mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
2618                 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2619                            "in legal range (-1 or %d..%d)\n",
2620                            mlx4_log_num_mgm_entry_size,
2621                            MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2622                            MLX4_MAX_MGM_LOG_ENTRY_SIZE);
2623                 return -1;
2624         }
2625
2626         return 0;
2627 }
2628
2629 static int __init mlx4_init(void)
2630 {
2631         int ret;
2632
2633         if (mlx4_verify_params())
2634                 return -EINVAL;
2635
2636         mlx4_catas_init();
2637
2638         mlx4_wq = create_singlethread_workqueue("mlx4");
2639         if (!mlx4_wq)
2640                 return -ENOMEM;
2641
2642         ret = pci_register_driver(&mlx4_driver);
2643         if (ret < 0)
2644                 destroy_workqueue(mlx4_wq);
2645         return ret < 0 ? ret : 0;
2646 }
2647
2648 static void __exit mlx4_cleanup(void)
2649 {
2650         pci_unregister_driver(&mlx4_driver);
2651         destroy_workqueue(mlx4_wq);
2652 }
2653
2654 module_init(mlx4_init);
2655 module_exit(mlx4_cleanup);