2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
52 static bool enable_qos;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
56 #define MLX4_GET(dest, source, offset) \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
68 #define MLX4_PUT(dest, source, offset) \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
94 [12] = "Dual Port Different Protocol (DPDP) support",
95 [15] = "Big LSO headers",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
112 [53] = "Port ETS Scheduler support",
113 [55] = "Port link type sensing support",
114 [59] = "Port management change event support",
115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
122 if (fname[i] && (flags & (1LL << i)))
123 mlx4_dbg(dev, " %s\n", fname[i]);
126 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
128 static const char * const fname[] = {
130 [1] = "RSS Toeplitz Hash Function support",
131 [2] = "RSS XOR Hash Function support",
132 [3] = "Device manage flow steering support",
133 [4] = "Automatic MAC reassignment support",
134 [5] = "Time stamping support"
138 for (i = 0; i < ARRAY_SIZE(fname); ++i)
139 if (fname[i] && (flags & (1LL << i)))
140 mlx4_dbg(dev, " %s\n", fname[i]);
143 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
145 struct mlx4_cmd_mailbox *mailbox;
149 #define MOD_STAT_CFG_IN_SIZE 0x100
151 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
152 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
154 mailbox = mlx4_alloc_cmd_mailbox(dev);
156 return PTR_ERR(mailbox);
157 inbox = mailbox->buf;
159 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
161 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
162 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
164 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
165 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
167 mlx4_free_cmd_mailbox(dev, mailbox);
171 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
172 struct mlx4_vhcr *vhcr,
173 struct mlx4_cmd_mailbox *inbox,
174 struct mlx4_cmd_mailbox *outbox,
175 struct mlx4_cmd_info *cmd)
181 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
182 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
183 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
184 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
185 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
186 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
187 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
188 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
189 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
190 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
191 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
192 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
194 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
195 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
196 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
198 /* when opcode modifier = 1 */
199 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
200 #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8
201 #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
203 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
204 #define QUERY_FUNC_CAP_QP0_PROXY 0x14
205 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
206 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c
208 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40
209 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80
211 #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80
213 if (vhcr->op_modifier == 1) {
215 /* ensure force vlan and force mac bits are not set */
216 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
217 /* ensure that phy_wqe_gid bit is not set */
218 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
220 field = vhcr->in_modifier; /* phys-port = logical-port */
221 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
223 /* size is now the QP number */
224 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1;
225 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
228 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
230 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1;
231 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY);
234 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY);
236 } else if (vhcr->op_modifier == 0) {
237 /* enable rdma and ethernet interfaces */
238 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA);
239 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
241 field = dev->caps.num_ports;
242 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
244 size = dev->caps.function_caps; /* set PF behaviours */
245 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
247 field = 0; /* protected FMR support not available as yet */
248 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
250 size = dev->caps.num_qps;
251 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
253 size = dev->caps.num_srqs;
254 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
256 size = dev->caps.num_cqs;
257 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
259 size = dev->caps.num_eqs;
260 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
262 size = dev->caps.reserved_eqs;
263 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
265 size = dev->caps.num_mpts;
266 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
268 size = dev->caps.num_mtts;
269 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
271 size = dev->caps.num_mgms + dev->caps.num_amgms;
272 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
280 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
281 struct mlx4_func_cap *func_cap)
283 struct mlx4_cmd_mailbox *mailbox;
285 u8 field, op_modifier;
289 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
291 mailbox = mlx4_alloc_cmd_mailbox(dev);
293 return PTR_ERR(mailbox);
295 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
296 MLX4_CMD_QUERY_FUNC_CAP,
297 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
301 outbox = mailbox->buf;
304 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
305 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
306 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
307 err = -EPROTONOSUPPORT;
310 func_cap->flags = field;
312 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
313 func_cap->num_ports = field;
315 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
316 func_cap->pf_context_behaviour = size;
318 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
319 func_cap->qp_quota = size & 0xFFFFFF;
321 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
322 func_cap->srq_quota = size & 0xFFFFFF;
324 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
325 func_cap->cq_quota = size & 0xFFFFFF;
327 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
328 func_cap->max_eq = size & 0xFFFFFF;
330 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
331 func_cap->reserved_eq = size & 0xFFFFFF;
333 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
334 func_cap->mpt_quota = size & 0xFFFFFF;
336 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
337 func_cap->mtt_quota = size & 0xFFFFFF;
339 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
340 func_cap->mcg_quota = size & 0xFFFFFF;
344 /* logical port query */
345 if (gen_or_port > dev->caps.num_ports) {
350 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
351 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
352 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) {
353 mlx4_err(dev, "VLAN is enforced on this port\n");
354 err = -EPROTONOSUPPORT;
358 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) {
359 mlx4_err(dev, "Force mac is enabled on this port\n");
360 err = -EPROTONOSUPPORT;
363 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
364 MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
365 if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) {
366 mlx4_err(dev, "phy_wqe_gid is "
367 "enforced on this ib port\n");
368 err = -EPROTONOSUPPORT;
373 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
374 func_cap->physical_port = field;
375 if (func_cap->physical_port != gen_or_port) {
380 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
381 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
383 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
384 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
386 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
387 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
389 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
390 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
392 /* All other resources are allocated by the master, but we still report
393 * 'num' and 'reserved' capabilities as follows:
394 * - num remains the maximum resource index
395 * - 'num - reserved' is the total available objects of a resource, but
396 * resource indices may be less than 'reserved'
397 * TODO: set per-resource quotas */
400 mlx4_free_cmd_mailbox(dev, mailbox);
405 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
407 struct mlx4_cmd_mailbox *mailbox;
410 u32 field32, flags, ext_flags;
416 #define QUERY_DEV_CAP_OUT_SIZE 0x100
417 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
418 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
419 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
420 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
421 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
422 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
423 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
424 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
425 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
426 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
427 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
428 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
429 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
430 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
431 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
432 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
433 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
434 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
435 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
436 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
437 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
438 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
439 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
440 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
441 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
442 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
443 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
444 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
445 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
446 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
447 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
448 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
449 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
450 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
451 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
452 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
453 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
454 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
455 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
456 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
457 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
458 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
459 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
460 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
461 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
462 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
463 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
464 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
465 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
466 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
467 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
468 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
469 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
470 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
471 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
472 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
473 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
474 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
475 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
476 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
477 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
478 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
479 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
480 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
481 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
482 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
483 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
484 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
485 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
486 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
489 mailbox = mlx4_alloc_cmd_mailbox(dev);
491 return PTR_ERR(mailbox);
492 outbox = mailbox->buf;
494 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
495 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
499 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
500 dev_cap->reserved_qps = 1 << (field & 0xf);
501 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
502 dev_cap->max_qps = 1 << (field & 0x1f);
503 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
504 dev_cap->reserved_srqs = 1 << (field >> 4);
505 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
506 dev_cap->max_srqs = 1 << (field & 0x1f);
507 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
508 dev_cap->max_cq_sz = 1 << field;
509 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
510 dev_cap->reserved_cqs = 1 << (field & 0xf);
511 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
512 dev_cap->max_cqs = 1 << (field & 0x1f);
513 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
514 dev_cap->max_mpts = 1 << (field & 0x3f);
515 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
516 dev_cap->reserved_eqs = field & 0xf;
517 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
518 dev_cap->max_eqs = 1 << (field & 0xf);
519 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
520 dev_cap->reserved_mtts = 1 << (field >> 4);
521 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
522 dev_cap->max_mrw_sz = 1 << field;
523 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
524 dev_cap->reserved_mrws = 1 << (field & 0xf);
525 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
526 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
527 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
528 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
529 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
530 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
531 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
534 dev_cap->max_gso_sz = 0;
536 dev_cap->max_gso_sz = 1 << field;
538 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
540 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
542 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
545 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
546 dev_cap->max_rss_tbl_sz = 1 << field;
548 dev_cap->max_rss_tbl_sz = 0;
549 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
550 dev_cap->max_rdma_global = 1 << (field & 0x3f);
551 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
552 dev_cap->local_ca_ack_delay = field & 0x1f;
553 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
554 dev_cap->num_ports = field & 0xf;
555 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
556 dev_cap->max_msg_sz = 1 << (field & 0x1f);
557 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
559 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
560 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
561 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
562 dev_cap->fs_max_num_qp_per_entry = field;
563 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
564 dev_cap->stat_rate_support = stat_rate;
565 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
567 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
568 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
569 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
570 dev_cap->flags = flags | (u64)ext_flags << 32;
571 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
572 dev_cap->reserved_uars = field >> 4;
573 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
574 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
575 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
576 dev_cap->min_page_sz = 1 << field;
578 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
580 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
581 dev_cap->bf_reg_size = 1 << (field & 0x1f);
582 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
583 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
585 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
586 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
587 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
589 dev_cap->bf_reg_size = 0;
590 mlx4_dbg(dev, "BlueFlame not available\n");
593 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
594 dev_cap->max_sq_sg = field;
595 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
596 dev_cap->max_sq_desc_sz = size;
598 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
599 dev_cap->max_qp_per_mcg = 1 << field;
600 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
601 dev_cap->reserved_mgms = field & 0xf;
602 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
603 dev_cap->max_mcgs = 1 << field;
604 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
605 dev_cap->reserved_pds = field >> 4;
606 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
607 dev_cap->max_pds = 1 << (field & 0x3f);
608 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
609 dev_cap->reserved_xrcds = field >> 4;
610 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
611 dev_cap->max_xrcds = 1 << (field & 0x1f);
613 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
614 dev_cap->rdmarc_entry_sz = size;
615 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
616 dev_cap->qpc_entry_sz = size;
617 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
618 dev_cap->aux_entry_sz = size;
619 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
620 dev_cap->altc_entry_sz = size;
621 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
622 dev_cap->eqc_entry_sz = size;
623 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
624 dev_cap->cqc_entry_sz = size;
625 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
626 dev_cap->srq_entry_sz = size;
627 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
628 dev_cap->cmpt_entry_sz = size;
629 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
630 dev_cap->mtt_entry_sz = size;
631 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
632 dev_cap->dmpt_entry_sz = size;
634 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
635 dev_cap->max_srq_sz = 1 << field;
636 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
637 dev_cap->max_qp_sz = 1 << field;
638 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
639 dev_cap->resize_srq = field & 1;
640 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
641 dev_cap->max_rq_sg = field;
642 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
643 dev_cap->max_rq_desc_sz = size;
645 MLX4_GET(dev_cap->bmme_flags, outbox,
646 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
647 MLX4_GET(dev_cap->reserved_lkey, outbox,
648 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
649 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
651 dev_cap->flags2 |= MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN;
652 MLX4_GET(dev_cap->max_icm_sz, outbox,
653 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
654 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
655 MLX4_GET(dev_cap->max_counters, outbox,
656 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
658 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
659 for (i = 1; i <= dev_cap->num_ports; ++i) {
660 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
661 dev_cap->max_vl[i] = field >> 4;
662 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
663 dev_cap->ib_mtu[i] = field >> 4;
664 dev_cap->max_port_width[i] = field & 0xf;
665 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
666 dev_cap->max_gids[i] = 1 << (field & 0xf);
667 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
668 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
671 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
672 #define QUERY_PORT_MTU_OFFSET 0x01
673 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
674 #define QUERY_PORT_WIDTH_OFFSET 0x06
675 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
676 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
677 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
678 #define QUERY_PORT_MAC_OFFSET 0x10
679 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
680 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
681 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
683 for (i = 1; i <= dev_cap->num_ports; ++i) {
684 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
685 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
689 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
690 dev_cap->supported_port_types[i] = field & 3;
691 dev_cap->suggested_type[i] = (field >> 3) & 1;
692 dev_cap->default_sense[i] = (field >> 4) & 1;
693 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
694 dev_cap->ib_mtu[i] = field & 0xf;
695 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
696 dev_cap->max_port_width[i] = field & 0xf;
697 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
698 dev_cap->max_gids[i] = 1 << (field >> 4);
699 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
700 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
701 dev_cap->max_vl[i] = field & 0xf;
702 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
703 dev_cap->log_max_macs[i] = field & 0xf;
704 dev_cap->log_max_vlans[i] = field >> 4;
705 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
706 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
707 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
708 dev_cap->trans_type[i] = field32 >> 24;
709 dev_cap->vendor_oui[i] = field32 & 0xffffff;
710 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
711 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
715 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
716 dev_cap->bmme_flags, dev_cap->reserved_lkey);
719 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
720 * we can't use any EQs whose doorbell falls on that page,
721 * even if the EQ itself isn't reserved.
723 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
724 dev_cap->reserved_eqs);
726 mlx4_dbg(dev, "Max ICM size %lld MB\n",
727 (unsigned long long) dev_cap->max_icm_sz >> 20);
728 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
729 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
730 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
731 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
732 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
733 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
734 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
735 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
736 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
737 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
738 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
739 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
740 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
741 dev_cap->max_pds, dev_cap->reserved_mgms);
742 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
743 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
744 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
745 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
746 dev_cap->max_port_width[1]);
747 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
748 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
749 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
750 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
751 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
752 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
753 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
755 dump_dev_cap_flags(dev, dev_cap->flags);
756 dump_dev_cap_flags2(dev, dev_cap->flags2);
759 mlx4_free_cmd_mailbox(dev, mailbox);
763 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
764 struct mlx4_vhcr *vhcr,
765 struct mlx4_cmd_mailbox *inbox,
766 struct mlx4_cmd_mailbox *outbox,
767 struct mlx4_cmd_info *cmd)
774 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
775 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
779 /* add port mng change event capability and disable mw type 1
780 * unconditionally to slaves
782 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
783 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
784 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
785 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
787 /* For guests, report Blueflame disabled */
788 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
790 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
792 /* For guests, disable mw type 2 */
793 MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
794 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
795 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
797 /* turn off device-managed steering capability if not enabled */
798 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
799 MLX4_GET(field, outbox->buf,
800 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
802 MLX4_PUT(outbox->buf, field,
803 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
808 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
809 struct mlx4_vhcr *vhcr,
810 struct mlx4_cmd_mailbox *inbox,
811 struct mlx4_cmd_mailbox *outbox,
812 struct mlx4_cmd_info *cmd)
819 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
820 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
821 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
823 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
824 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
827 if (!err && dev->caps.function != slave) {
828 /* set slave default_mac address */
829 MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
830 def_mac += slave << 8;
831 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
833 /* get port type - currently only eth is enabled */
834 MLX4_GET(port_type, outbox->buf,
835 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
837 /* No link sensing allowed */
838 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
839 /* set port type to currently operating port type */
840 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
842 MLX4_PUT(outbox->buf, port_type,
843 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
845 short_field = 1; /* slave max gids */
846 MLX4_PUT(outbox->buf, short_field,
847 QUERY_PORT_CUR_MAX_GID_OFFSET);
849 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
850 MLX4_PUT(outbox->buf, short_field,
851 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
857 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
858 int *gid_tbl_len, int *pkey_tbl_len)
860 struct mlx4_cmd_mailbox *mailbox;
865 mailbox = mlx4_alloc_cmd_mailbox(dev);
867 return PTR_ERR(mailbox);
869 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
870 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
875 outbox = mailbox->buf;
877 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
878 *gid_tbl_len = field;
880 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
881 *pkey_tbl_len = field;
884 mlx4_free_cmd_mailbox(dev, mailbox);
887 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
889 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
891 struct mlx4_cmd_mailbox *mailbox;
892 struct mlx4_icm_iter iter;
900 mailbox = mlx4_alloc_cmd_mailbox(dev);
902 return PTR_ERR(mailbox);
903 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
904 pages = mailbox->buf;
906 for (mlx4_icm_first(icm, &iter);
907 !mlx4_icm_last(&iter);
908 mlx4_icm_next(&iter)) {
910 * We have to pass pages that are aligned to their
911 * size, so find the least significant 1 in the
912 * address or size and use that as our log2 size.
914 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
915 if (lg < MLX4_ICM_PAGE_SHIFT) {
916 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
918 (unsigned long long) mlx4_icm_addr(&iter),
919 mlx4_icm_size(&iter));
924 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
926 pages[nent * 2] = cpu_to_be64(virt);
930 pages[nent * 2 + 1] =
931 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
932 (lg - MLX4_ICM_PAGE_SHIFT));
933 ts += 1 << (lg - 10);
936 if (++nent == MLX4_MAILBOX_SIZE / 16) {
937 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
938 MLX4_CMD_TIME_CLASS_B,
948 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
949 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
954 case MLX4_CMD_MAP_FA:
955 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
957 case MLX4_CMD_MAP_ICM_AUX:
958 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
960 case MLX4_CMD_MAP_ICM:
961 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
962 tc, ts, (unsigned long long) virt - (ts << 10));
967 mlx4_free_cmd_mailbox(dev, mailbox);
971 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
973 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
976 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
978 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
979 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
983 int mlx4_RUN_FW(struct mlx4_dev *dev)
985 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
986 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
989 int mlx4_QUERY_FW(struct mlx4_dev *dev)
991 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
992 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
993 struct mlx4_cmd_mailbox *mailbox;
1000 #define QUERY_FW_OUT_SIZE 0x100
1001 #define QUERY_FW_VER_OFFSET 0x00
1002 #define QUERY_FW_PPF_ID 0x09
1003 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
1004 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
1005 #define QUERY_FW_ERR_START_OFFSET 0x30
1006 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
1007 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
1009 #define QUERY_FW_SIZE_OFFSET 0x00
1010 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1011 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1013 #define QUERY_FW_COMM_BASE_OFFSET 0x40
1014 #define QUERY_FW_COMM_BAR_OFFSET 0x48
1016 #define QUERY_FW_CLOCK_OFFSET 0x50
1017 #define QUERY_FW_CLOCK_BAR 0x58
1019 mailbox = mlx4_alloc_cmd_mailbox(dev);
1020 if (IS_ERR(mailbox))
1021 return PTR_ERR(mailbox);
1022 outbox = mailbox->buf;
1024 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1025 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1029 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1031 * FW subminor version is at more significant bits than minor
1032 * version, so swap here.
1034 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1035 ((fw_ver & 0xffff0000ull) >> 16) |
1036 ((fw_ver & 0x0000ffffull) << 16);
1038 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1039 dev->caps.function = lg;
1041 if (mlx4_is_slave(dev))
1045 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
1046 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1047 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1048 mlx4_err(dev, "Installed FW has unsupported "
1049 "command interface revision %d.\n",
1051 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1052 (int) (dev->caps.fw_ver >> 32),
1053 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1054 (int) dev->caps.fw_ver & 0xffff);
1055 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
1056 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
1061 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1062 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1064 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1065 cmd->max_cmds = 1 << lg;
1067 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
1068 (int) (dev->caps.fw_ver >> 32),
1069 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1070 (int) dev->caps.fw_ver & 0xffff,
1071 cmd_if_rev, cmd->max_cmds);
1073 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1074 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1075 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1076 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1078 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1079 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1081 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1082 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1083 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1084 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1086 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1087 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1088 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1089 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1090 fw->comm_bar, fw->comm_base);
1091 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1093 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1094 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1095 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1096 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1097 fw->clock_bar, fw->clock_offset);
1100 * Round up number of system pages needed in case
1101 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1104 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1105 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1107 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1108 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1111 mlx4_free_cmd_mailbox(dev, mailbox);
1115 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1116 struct mlx4_vhcr *vhcr,
1117 struct mlx4_cmd_mailbox *inbox,
1118 struct mlx4_cmd_mailbox *outbox,
1119 struct mlx4_cmd_info *cmd)
1124 outbuf = outbox->buf;
1125 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1126 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1130 /* for slaves, set pci PPF ID to invalid and zero out everything
1131 * else except FW version */
1132 outbuf[0] = outbuf[1] = 0;
1133 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
1134 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1139 static void get_board_id(void *vsd, char *board_id)
1143 #define VSD_OFFSET_SIG1 0x00
1144 #define VSD_OFFSET_SIG2 0xde
1145 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1146 #define VSD_OFFSET_TS_BOARD_ID 0x20
1148 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1150 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1152 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1153 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1154 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1157 * The board ID is a string but the firmware byte
1158 * swaps each 4-byte word before passing it back to
1159 * us. Therefore we need to swab it before printing.
1161 for (i = 0; i < 4; ++i)
1162 ((u32 *) board_id)[i] =
1163 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1167 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1169 struct mlx4_cmd_mailbox *mailbox;
1173 #define QUERY_ADAPTER_OUT_SIZE 0x100
1174 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1175 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1177 mailbox = mlx4_alloc_cmd_mailbox(dev);
1178 if (IS_ERR(mailbox))
1179 return PTR_ERR(mailbox);
1180 outbox = mailbox->buf;
1182 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1183 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1187 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1189 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1193 mlx4_free_cmd_mailbox(dev, mailbox);
1197 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1199 struct mlx4_cmd_mailbox *mailbox;
1203 #define INIT_HCA_IN_SIZE 0x200
1204 #define INIT_HCA_VERSION_OFFSET 0x000
1205 #define INIT_HCA_VERSION 2
1206 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1207 #define INIT_HCA_FLAGS_OFFSET 0x014
1208 #define INIT_HCA_QPC_OFFSET 0x020
1209 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1210 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1211 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1212 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1213 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1214 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1215 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1216 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1217 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1218 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1219 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1220 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1221 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1222 #define INIT_HCA_MCAST_OFFSET 0x0c0
1223 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1224 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1225 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1226 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1227 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1228 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1229 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1230 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1231 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1232 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1233 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1234 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1235 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1236 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1237 #define INIT_HCA_TPT_OFFSET 0x0f0
1238 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1239 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
1240 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1241 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1242 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1243 #define INIT_HCA_UAR_OFFSET 0x120
1244 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1245 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1247 mailbox = mlx4_alloc_cmd_mailbox(dev);
1248 if (IS_ERR(mailbox))
1249 return PTR_ERR(mailbox);
1250 inbox = mailbox->buf;
1252 memset(inbox, 0, INIT_HCA_IN_SIZE);
1254 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1256 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1257 (ilog2(cache_line_size()) - 4) << 5;
1259 #if defined(__LITTLE_ENDIAN)
1260 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1261 #elif defined(__BIG_ENDIAN)
1262 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1264 #error Host endianness not defined
1266 /* Check port for UD address vector: */
1267 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1269 /* Enable IPoIB checksumming if we can: */
1270 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1271 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1273 /* Enable QoS support if module parameter set */
1275 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1277 /* enable counters */
1278 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1279 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1281 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1282 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1283 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1284 dev->caps.eqe_size = 64;
1285 dev->caps.eqe_factor = 1;
1287 dev->caps.eqe_size = 32;
1288 dev->caps.eqe_factor = 0;
1291 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1292 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1293 dev->caps.cqe_size = 64;
1294 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1296 dev->caps.cqe_size = 32;
1299 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1301 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1302 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1303 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1304 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1305 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1306 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1307 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1308 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1309 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1310 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1311 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1312 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1314 /* steering attributes */
1315 if (dev->caps.steering_mode ==
1316 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1317 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1319 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1321 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1322 MLX4_PUT(inbox, param->log_mc_entry_sz,
1323 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1324 MLX4_PUT(inbox, param->log_mc_table_sz,
1325 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1326 /* Enable Ethernet flow steering
1327 * with udp unicast and tcp unicast
1329 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1330 INIT_HCA_FS_ETH_BITS_OFFSET);
1331 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1332 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1333 /* Enable IPoIB flow steering
1334 * with udp unicast and tcp unicast
1336 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1337 INIT_HCA_FS_IB_BITS_OFFSET);
1338 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1339 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1341 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1342 MLX4_PUT(inbox, param->log_mc_entry_sz,
1343 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1344 MLX4_PUT(inbox, param->log_mc_hash_sz,
1345 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1346 MLX4_PUT(inbox, param->log_mc_table_sz,
1347 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1348 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1349 MLX4_PUT(inbox, (u8) (1 << 3),
1350 INIT_HCA_UC_STEERING_OFFSET);
1353 /* TPT attributes */
1355 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1356 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
1357 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1358 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1359 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1361 /* UAR attributes */
1363 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1364 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1366 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1370 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1372 mlx4_free_cmd_mailbox(dev, mailbox);
1376 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1377 struct mlx4_init_hca_param *param)
1379 struct mlx4_cmd_mailbox *mailbox;
1385 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1386 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
1388 mailbox = mlx4_alloc_cmd_mailbox(dev);
1389 if (IS_ERR(mailbox))
1390 return PTR_ERR(mailbox);
1391 outbox = mailbox->buf;
1393 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1395 MLX4_CMD_TIME_CLASS_B,
1396 !mlx4_is_slave(dev));
1400 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1401 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
1403 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1405 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1406 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1407 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1408 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1409 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1410 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1411 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1412 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1413 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1414 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1415 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1416 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1418 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1419 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1420 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1422 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1423 if (byte_field & 0x8)
1424 param->steering_mode = MLX4_STEERING_MODE_B0;
1426 param->steering_mode = MLX4_STEERING_MODE_A0;
1428 /* steering attributes */
1429 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
1430 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1431 MLX4_GET(param->log_mc_entry_sz, outbox,
1432 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1433 MLX4_GET(param->log_mc_table_sz, outbox,
1434 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1436 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1437 MLX4_GET(param->log_mc_entry_sz, outbox,
1438 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1439 MLX4_GET(param->log_mc_hash_sz, outbox,
1440 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1441 MLX4_GET(param->log_mc_table_sz, outbox,
1442 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1445 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1446 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1447 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1448 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1449 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1450 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1452 /* TPT attributes */
1454 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1455 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
1456 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1457 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1458 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1460 /* UAR attributes */
1462 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1463 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1466 mlx4_free_cmd_mailbox(dev, mailbox);
1471 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1472 * and real QP0 are active, so that the paravirtualized QP0 is ready
1474 static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1476 struct mlx4_priv *priv = mlx4_priv(dev);
1477 /* irrelevant if not infiniband */
1478 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1479 priv->mfunc.master.qp0_state[port].qp0_active)
1484 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1485 struct mlx4_vhcr *vhcr,
1486 struct mlx4_cmd_mailbox *inbox,
1487 struct mlx4_cmd_mailbox *outbox,
1488 struct mlx4_cmd_info *cmd)
1490 struct mlx4_priv *priv = mlx4_priv(dev);
1491 int port = vhcr->in_modifier;
1494 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1497 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1498 /* Enable port only if it was previously disabled */
1499 if (!priv->mfunc.master.init_port_ref[port]) {
1500 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1501 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1505 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1507 if (slave == mlx4_master_func_num(dev)) {
1508 if (check_qp0_state(dev, slave, port) &&
1509 !priv->mfunc.master.qp0_state[port].port_active) {
1510 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1511 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1514 priv->mfunc.master.qp0_state[port].port_active = 1;
1515 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1518 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1520 ++priv->mfunc.master.init_port_ref[port];
1524 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
1526 struct mlx4_cmd_mailbox *mailbox;
1532 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1533 #define INIT_PORT_IN_SIZE 256
1534 #define INIT_PORT_FLAGS_OFFSET 0x00
1535 #define INIT_PORT_FLAG_SIG (1 << 18)
1536 #define INIT_PORT_FLAG_NG (1 << 17)
1537 #define INIT_PORT_FLAG_G0 (1 << 16)
1538 #define INIT_PORT_VL_SHIFT 4
1539 #define INIT_PORT_PORT_WIDTH_SHIFT 8
1540 #define INIT_PORT_MTU_OFFSET 0x04
1541 #define INIT_PORT_MAX_GID_OFFSET 0x06
1542 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1543 #define INIT_PORT_GUID0_OFFSET 0x10
1544 #define INIT_PORT_NODE_GUID_OFFSET 0x18
1545 #define INIT_PORT_SI_GUID_OFFSET 0x20
1547 mailbox = mlx4_alloc_cmd_mailbox(dev);
1548 if (IS_ERR(mailbox))
1549 return PTR_ERR(mailbox);
1550 inbox = mailbox->buf;
1552 memset(inbox, 0, INIT_PORT_IN_SIZE);
1555 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1556 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1557 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
1559 field = 128 << dev->caps.ib_mtu_cap[port];
1560 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1561 field = dev->caps.gid_table_len[port];
1562 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1563 field = dev->caps.pkey_table_len[port];
1564 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
1566 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
1567 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1569 mlx4_free_cmd_mailbox(dev, mailbox);
1571 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1572 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1576 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1578 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1579 struct mlx4_vhcr *vhcr,
1580 struct mlx4_cmd_mailbox *inbox,
1581 struct mlx4_cmd_mailbox *outbox,
1582 struct mlx4_cmd_info *cmd)
1584 struct mlx4_priv *priv = mlx4_priv(dev);
1585 int port = vhcr->in_modifier;
1588 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1592 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1593 if (priv->mfunc.master.init_port_ref[port] == 1) {
1594 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1595 1000, MLX4_CMD_NATIVE);
1599 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1601 /* infiniband port */
1602 if (slave == mlx4_master_func_num(dev)) {
1603 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1604 priv->mfunc.master.qp0_state[port].port_active) {
1605 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1606 1000, MLX4_CMD_NATIVE);
1609 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1610 priv->mfunc.master.qp0_state[port].port_active = 0;
1613 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1615 --priv->mfunc.master.init_port_ref[port];
1619 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1621 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1624 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1626 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1628 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1632 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1634 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1635 MLX4_CMD_SET_ICM_SIZE,
1636 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1641 * Round up number of system pages needed in case
1642 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1644 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1645 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1650 int mlx4_NOP(struct mlx4_dev *dev)
1652 /* Input modifier of 0x1f means "finish as soon as possible." */
1653 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
1656 #define MLX4_WOL_SETUP_MODE (5 << 28)
1657 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1659 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1661 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
1662 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1665 EXPORT_SYMBOL_GPL(mlx4_wol_read);
1667 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1669 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1671 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
1672 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1674 EXPORT_SYMBOL_GPL(mlx4_wol_write);