2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/init.h>
35 #include <linux/interrupt.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/mlx4/cmd.h>
42 #include <linux/cpu_rmap.h>
48 MLX4_IRQNAME_SIZE = 32
52 MLX4_NUM_ASYNC_EQE = 0x100,
53 MLX4_NUM_SPARE_EQE = 0x80,
54 MLX4_EQ_ENTRY_SIZE = 0x20
57 #define MLX4_EQ_STATUS_OK ( 0 << 28)
58 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
59 #define MLX4_EQ_OWNER_SW ( 0 << 24)
60 #define MLX4_EQ_OWNER_HW ( 1 << 24)
61 #define MLX4_EQ_FLAG_EC ( 1 << 18)
62 #define MLX4_EQ_FLAG_OI ( 1 << 17)
63 #define MLX4_EQ_STATE_ARMED ( 9 << 8)
64 #define MLX4_EQ_STATE_FIRED (10 << 8)
65 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
67 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
68 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
69 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
70 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
71 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
72 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
73 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
74 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
75 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
76 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
77 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
78 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
79 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
80 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
81 (1ull << MLX4_EVENT_TYPE_CMD) | \
82 (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \
83 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \
84 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \
85 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
87 static u64 get_async_ev_mask(struct mlx4_dev *dev)
89 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK;
90 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
91 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT);
96 static void eq_set_ci(struct mlx4_eq *eq, int req_not)
98 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
101 /* We still want ordering, just not swabbing, so add a barrier */
105 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor)
107 /* (entry & (eq->nent - 1)) gives us a cyclic array */
108 unsigned long offset = (entry & (eq->nent - 1)) * (MLX4_EQ_ENTRY_SIZE << eqe_factor);
109 /* CX3 is capable of extending the EQE from 32 to 64 bytes.
110 * When this feature is enabled, the first (in the lower addresses)
111 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes
112 * contain the legacy EQE information.
114 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE;
117 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor)
119 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor);
120 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
123 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq)
125 struct mlx4_eqe *eqe =
126 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)];
127 return (!!(eqe->owner & 0x80) ^
128 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ?
132 void mlx4_gen_slave_eqe(struct work_struct *work)
134 struct mlx4_mfunc_master_ctx *master =
135 container_of(work, struct mlx4_mfunc_master_ctx,
137 struct mlx4_mfunc *mfunc =
138 container_of(master, struct mlx4_mfunc, master);
139 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc);
140 struct mlx4_dev *dev = &priv->dev;
141 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq;
142 struct mlx4_eqe *eqe;
146 for (eqe = next_slave_event_eqe(slave_eq); eqe;
147 eqe = next_slave_event_eqe(slave_eq)) {
148 slave = eqe->slave_id;
150 /* All active slaves need to receive the event */
151 if (slave == ALL_SLAVES) {
152 for (i = 0; i < dev->num_slaves; i++) {
153 if (i != dev->caps.function &&
154 master->slave_state[i].active)
155 if (mlx4_GEN_EQE(dev, i, eqe))
156 mlx4_warn(dev, "Failed to "
158 "for slave %d\n", i);
161 if (mlx4_GEN_EQE(dev, slave, eqe))
162 mlx4_warn(dev, "Failed to generate event "
163 "for slave %d\n", slave);
170 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe)
172 struct mlx4_priv *priv = mlx4_priv(dev);
173 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq;
174 struct mlx4_eqe *s_eqe;
177 spin_lock_irqsave(&slave_eq->event_lock, flags);
178 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)];
179 if ((!!(s_eqe->owner & 0x80)) ^
180 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) {
181 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. "
182 "No free EQE on slave events queue\n", slave);
183 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
187 memcpy(s_eqe, eqe, dev->caps.eqe_size - 1);
188 s_eqe->slave_id = slave;
189 /* ensure all information is written before setting the ownersip bit */
191 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80;
194 queue_work(priv->mfunc.master.comm_wq,
195 &priv->mfunc.master.slave_event_work);
196 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
199 static void mlx4_slave_event(struct mlx4_dev *dev, int slave,
200 struct mlx4_eqe *eqe)
202 struct mlx4_priv *priv = mlx4_priv(dev);
203 struct mlx4_slave_state *s_slave =
204 &priv->mfunc.master.slave_state[slave];
206 if (!s_slave->active) {
207 /*mlx4_warn(dev, "Trying to pass event to inactive slave\n");*/
211 slave_event(dev, slave, eqe);
214 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port)
218 struct mlx4_priv *priv = mlx4_priv(dev);
219 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave];
221 if (!s_slave->active)
224 memset(&eqe, 0, sizeof eqe);
226 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
227 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE;
228 eqe.event.port_mgmt_change.port = port;
230 return mlx4_GEN_EQE(dev, slave, &eqe);
232 EXPORT_SYMBOL(mlx4_gen_pkey_eqe);
234 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port)
238 /*don't send if we don't have the that slave */
239 if (dev->num_vfs < slave)
241 memset(&eqe, 0, sizeof eqe);
243 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
244 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO;
245 eqe.event.port_mgmt_change.port = port;
247 return mlx4_GEN_EQE(dev, slave, &eqe);
249 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe);
251 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port,
252 u8 port_subtype_change)
256 /*don't send if we don't have the that slave */
257 if (dev->num_vfs < slave)
259 memset(&eqe, 0, sizeof eqe);
261 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE;
262 eqe.subtype = port_subtype_change;
263 eqe.event.port_change.port = cpu_to_be32(port << 28);
265 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__,
266 port_subtype_change, slave, port);
267 return mlx4_GEN_EQE(dev, slave, &eqe);
269 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe);
271 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port)
273 struct mlx4_priv *priv = mlx4_priv(dev);
274 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
275 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS) {
276 pr_err("%s: Error: asking for slave:%d, port:%d\n",
277 __func__, slave, port);
278 return SLAVE_PORT_DOWN;
280 return s_state[slave].port_state[port];
282 EXPORT_SYMBOL(mlx4_get_slave_port_state);
284 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port,
285 enum slave_port_state state)
287 struct mlx4_priv *priv = mlx4_priv(dev);
288 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
290 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS || port == 0) {
291 pr_err("%s: Error: asking for slave:%d, port:%d\n",
292 __func__, slave, port);
295 s_state[slave].port_state[port] = state;
300 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event)
303 enum slave_port_gen_event gen_event;
305 for (i = 0; i < dev->num_slaves; i++)
306 set_and_calc_slave_port_state(dev, i, port, event, &gen_event);
308 /**************************************************************************
309 The function get as input the new event to that port,
310 and according to the prev state change the slave's port state.
312 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
313 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
314 MLX4_PORT_STATE_IB_EVENT_GID_VALID
315 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
316 ***************************************************************************/
317 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave,
319 enum slave_port_gen_event *gen_event)
321 struct mlx4_priv *priv = mlx4_priv(dev);
322 struct mlx4_slave_state *ctx = NULL;
325 enum slave_port_state cur_state =
326 mlx4_get_slave_port_state(dev, slave, port);
328 *gen_event = SLAVE_PORT_GEN_EVENT_NONE;
330 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS || port == 0) {
331 pr_err("%s: Error: asking for slave:%d, port:%d\n",
332 __func__, slave, port);
336 ctx = &priv->mfunc.master.slave_state[slave];
337 spin_lock_irqsave(&ctx->lock, flags);
340 case SLAVE_PORT_DOWN:
341 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event)
342 mlx4_set_slave_port_state(dev, slave, port,
345 case SLAVE_PENDING_UP:
346 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event)
347 mlx4_set_slave_port_state(dev, slave, port,
349 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) {
350 mlx4_set_slave_port_state(dev, slave, port,
352 *gen_event = SLAVE_PORT_GEN_EVENT_UP;
356 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) {
357 mlx4_set_slave_port_state(dev, slave, port,
359 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
360 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID ==
362 mlx4_set_slave_port_state(dev, slave, port,
364 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
368 pr_err("%s: BUG!!! UNKNOWN state: "
369 "slave:%d, port:%d\n", __func__, slave, port);
372 ret = mlx4_get_slave_port_state(dev, slave, port);
375 spin_unlock_irqrestore(&ctx->lock, flags);
379 EXPORT_SYMBOL(set_and_calc_slave_port_state);
381 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr)
385 memset(&eqe, 0, sizeof eqe);
387 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
388 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO;
389 eqe.event.port_mgmt_change.port = port;
390 eqe.event.port_mgmt_change.params.port_info.changed_attr =
391 cpu_to_be32((u32) attr);
393 slave_event(dev, ALL_SLAVES, &eqe);
396 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev);
398 void mlx4_master_handle_slave_flr(struct work_struct *work)
400 struct mlx4_mfunc_master_ctx *master =
401 container_of(work, struct mlx4_mfunc_master_ctx,
402 slave_flr_event_work);
403 struct mlx4_mfunc *mfunc =
404 container_of(master, struct mlx4_mfunc, master);
405 struct mlx4_priv *priv =
406 container_of(mfunc, struct mlx4_priv, mfunc);
407 struct mlx4_dev *dev = &priv->dev;
408 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
413 mlx4_dbg(dev, "mlx4_handle_slave_flr\n");
415 for (i = 0 ; i < dev->num_slaves; i++) {
417 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) {
418 mlx4_dbg(dev, "mlx4_handle_slave_flr: "
419 "clean slave: %d\n", i);
421 mlx4_delete_all_resources_for_slave(dev, i);
422 /*return the slave to running mode*/
423 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
424 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET;
425 slave_state[i].is_slave_going_down = 0;
426 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
428 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
429 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
431 mlx4_warn(dev, "Failed to notify FW on "
432 "FLR done (slave:%d)\n", i);
437 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
439 struct mlx4_priv *priv = mlx4_priv(dev);
440 struct mlx4_eqe *eqe;
448 u8 update_slave_state;
450 enum slave_port_gen_event gen_event;
452 struct mlx4_vport_state *s_info;
454 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor))) {
456 * Make sure we read EQ entry contents after we've
457 * checked the ownership bit.
462 case MLX4_EVENT_TYPE_COMP:
463 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
464 mlx4_cq_completion(dev, cqn);
467 case MLX4_EVENT_TYPE_PATH_MIG:
468 case MLX4_EVENT_TYPE_COMM_EST:
469 case MLX4_EVENT_TYPE_SQ_DRAINED:
470 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
471 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
472 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
473 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
474 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
475 mlx4_dbg(dev, "event %d arrived\n", eqe->type);
476 if (mlx4_is_master(dev)) {
477 /* forward only to slave owning the QP */
478 ret = mlx4_get_slave_from_resource_id(dev,
480 be32_to_cpu(eqe->event.qp.qpn)
482 if (ret && ret != -ENOENT) {
483 mlx4_dbg(dev, "QP event %02x(%02x) on "
484 "EQ %d at index %u: could "
485 "not get slave id (%d)\n",
486 eqe->type, eqe->subtype,
487 eq->eqn, eq->cons_index, ret);
491 if (!ret && slave != dev->caps.function) {
492 mlx4_slave_event(dev, slave, eqe);
497 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) &
498 0xffffff, eqe->type);
501 case MLX4_EVENT_TYPE_SRQ_LIMIT:
502 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n",
504 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
505 if (mlx4_is_master(dev)) {
506 /* forward only to slave owning the SRQ */
507 ret = mlx4_get_slave_from_resource_id(dev,
509 be32_to_cpu(eqe->event.srq.srqn)
512 if (ret && ret != -ENOENT) {
513 mlx4_warn(dev, "SRQ event %02x(%02x) "
514 "on EQ %d at index %u: could"
515 " not get slave id (%d)\n",
516 eqe->type, eqe->subtype,
517 eq->eqn, eq->cons_index, ret);
520 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x,"
521 " event: %02x(%02x)\n", __func__,
523 be32_to_cpu(eqe->event.srq.srqn),
524 eqe->type, eqe->subtype);
526 if (!ret && slave != dev->caps.function) {
527 mlx4_warn(dev, "%s: sending event "
528 "%02x(%02x) to slave:%d\n",
530 eqe->subtype, slave);
531 mlx4_slave_event(dev, slave, eqe);
535 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) &
536 0xffffff, eqe->type);
539 case MLX4_EVENT_TYPE_CMD:
541 be16_to_cpu(eqe->event.cmd.token),
542 eqe->event.cmd.status,
543 be64_to_cpu(eqe->event.cmd.out_param));
546 case MLX4_EVENT_TYPE_PORT_CHANGE:
547 port = be32_to_cpu(eqe->event.port_change.port) >> 28;
548 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
549 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
551 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
552 if (!mlx4_is_master(dev))
554 for (i = 0; i < dev->num_slaves; i++) {
555 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
556 if (i == mlx4_master_func_num(dev))
558 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN"
559 " to slave: %d, port:%d\n",
561 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state;
562 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state)
563 mlx4_slave_event(dev, i, eqe);
564 } else { /* IB port */
565 set_and_calc_slave_port_state(dev, i, port,
566 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
568 /*we can be in pending state, then do not send port_down event*/
569 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) {
570 if (i == mlx4_master_func_num(dev))
572 mlx4_slave_event(dev, i, eqe);
577 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port);
579 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
581 if (!mlx4_is_master(dev))
583 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
584 for (i = 0; i < dev->num_slaves; i++) {
585 if (i == mlx4_master_func_num(dev))
587 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state;
588 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state)
589 mlx4_slave_event(dev, i, eqe);
592 /* port-up event will be sent to a slave when the
593 * slave's alias-guid is set. This is done in alias_GUID.c
595 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP);
599 case MLX4_EVENT_TYPE_CQ_ERROR:
600 mlx4_warn(dev, "CQ %s on CQN %06x\n",
601 eqe->event.cq_err.syndrome == 1 ?
602 "overrun" : "access violation",
603 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
604 if (mlx4_is_master(dev)) {
605 ret = mlx4_get_slave_from_resource_id(dev,
607 be32_to_cpu(eqe->event.cq_err.cqn)
609 if (ret && ret != -ENOENT) {
610 mlx4_dbg(dev, "CQ event %02x(%02x) on "
611 "EQ %d at index %u: could "
612 "not get slave id (%d)\n",
613 eqe->type, eqe->subtype,
614 eq->eqn, eq->cons_index, ret);
618 if (!ret && slave != dev->caps.function) {
619 mlx4_slave_event(dev, slave, eqe);
624 be32_to_cpu(eqe->event.cq_err.cqn)
629 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
630 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
633 case MLX4_EVENT_TYPE_OP_REQUIRED:
634 atomic_inc(&priv->opreq_count);
635 /* FW commands can't be executed from interrupt context
636 * working in deferred task
638 queue_work(mlx4_wq, &priv->opreq_task);
641 case MLX4_EVENT_TYPE_COMM_CHANNEL:
642 if (!mlx4_is_master(dev)) {
643 mlx4_warn(dev, "Received comm channel event "
644 "for non master device\n");
647 memcpy(&priv->mfunc.master.comm_arm_bit_vector,
648 eqe->event.comm_channel_arm.bit_vec,
649 sizeof eqe->event.comm_channel_arm.bit_vec);
650 queue_work(priv->mfunc.master.comm_wq,
651 &priv->mfunc.master.comm_work);
654 case MLX4_EVENT_TYPE_FLR_EVENT:
655 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id);
656 if (!mlx4_is_master(dev)) {
657 mlx4_warn(dev, "Non-master function received"
662 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave);
664 if (flr_slave >= dev->num_slaves) {
666 "Got FLR for unknown function: %d\n",
668 update_slave_state = 0;
670 update_slave_state = 1;
672 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
673 if (update_slave_state) {
674 priv->mfunc.master.slave_state[flr_slave].active = false;
675 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR;
676 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1;
678 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
679 queue_work(priv->mfunc.master.comm_wq,
680 &priv->mfunc.master.slave_flr_event_work);
683 case MLX4_EVENT_TYPE_FATAL_WARNING:
684 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) {
685 if (mlx4_is_master(dev))
686 for (i = 0; i < dev->num_slaves; i++) {
687 mlx4_dbg(dev, "%s: Sending "
688 "MLX4_FATAL_WARNING_SUBTYPE_WARMING"
689 " to slave: %d\n", __func__, i);
690 if (i == dev->caps.function)
692 mlx4_slave_event(dev, i, eqe);
694 mlx4_err(dev, "Temperature Threshold was reached! "
695 "Threshold: %d celsius degrees; "
696 "Current Temperature: %d\n",
697 be16_to_cpu(eqe->event.warming.warning_threshold),
698 be16_to_cpu(eqe->event.warming.current_temperature));
700 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), "
701 "subtype %02x on EQ %d at index %u. owner=%x, "
702 "nent=0x%x, slave=%x, ownership=%s\n",
703 eqe->type, eqe->subtype, eq->eqn,
704 eq->cons_index, eqe->owner, eq->nent,
706 !!(eqe->owner & 0x80) ^
707 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
711 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT:
712 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE,
713 (unsigned long) eqe);
716 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
717 case MLX4_EVENT_TYPE_ECC_DETECT:
719 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at "
720 "index %u. owner=%x, nent=0x%x, slave=%x, "
722 eqe->type, eqe->subtype, eq->eqn,
723 eq->cons_index, eqe->owner, eq->nent,
725 !!(eqe->owner & 0x80) ^
726 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
735 * The HCA will think the queue has overflowed if we
736 * don't tell it we've been processing events. We
737 * create our EQs with MLX4_NUM_SPARE_EQE extra
738 * entries, so we must update our consumer index at
741 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
752 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
754 struct mlx4_dev *dev = dev_ptr;
755 struct mlx4_priv *priv = mlx4_priv(dev);
759 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
761 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
762 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
764 return IRQ_RETVAL(work);
767 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
769 struct mlx4_eq *eq = eq_ptr;
770 struct mlx4_dev *dev = eq->dev;
772 mlx4_eq_int(dev, eq);
774 /* MSI-X vectors always belong to us */
778 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
779 struct mlx4_vhcr *vhcr,
780 struct mlx4_cmd_mailbox *inbox,
781 struct mlx4_cmd_mailbox *outbox,
782 struct mlx4_cmd_info *cmd)
784 struct mlx4_priv *priv = mlx4_priv(dev);
785 struct mlx4_slave_event_eq_info *event_eq =
786 priv->mfunc.master.slave_state[slave].event_eq;
787 u32 in_modifier = vhcr->in_modifier;
788 u32 eqn = in_modifier & 0x3FF;
789 u64 in_param = vhcr->in_param;
793 if (slave == dev->caps.function)
794 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
795 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
798 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i)
799 if (in_param & (1LL << i))
800 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn;
805 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
808 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
809 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
813 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
816 return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
817 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A,
821 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
824 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num,
825 0, MLX4_CMD_HW2SW_EQ, MLX4_CMD_TIME_CLASS_A,
829 static int mlx4_num_eq_uar(struct mlx4_dev *dev)
832 * Each UAR holds 4 EQ doorbells. To figure out how many UARs
833 * we need to map, take the difference of highest index and
834 * the lowest index we'll use and add 1.
836 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs +
837 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1;
840 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
842 struct mlx4_priv *priv = mlx4_priv(dev);
845 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
847 if (!priv->eq_table.uar_map[index]) {
848 priv->eq_table.uar_map[index] =
849 ioremap(pci_resource_start(dev->pdev, 2) +
850 ((eq->eqn / 4) << PAGE_SHIFT),
852 if (!priv->eq_table.uar_map[index]) {
853 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
859 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
862 static void mlx4_unmap_uar(struct mlx4_dev *dev)
864 struct mlx4_priv *priv = mlx4_priv(dev);
867 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
868 if (priv->eq_table.uar_map[i]) {
869 iounmap(priv->eq_table.uar_map[i]);
870 priv->eq_table.uar_map[i] = NULL;
874 static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
875 u8 intr, struct mlx4_eq *eq)
877 struct mlx4_priv *priv = mlx4_priv(dev);
878 struct mlx4_cmd_mailbox *mailbox;
879 struct mlx4_eq_context *eq_context;
881 u64 *dma_list = NULL;
888 eq->nent = roundup_pow_of_two(max(nent, 2));
889 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes */
890 npages = PAGE_ALIGN(eq->nent * (MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor)) / PAGE_SIZE;
892 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
897 for (i = 0; i < npages; ++i)
898 eq->page_list[i].buf = NULL;
900 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
904 mailbox = mlx4_alloc_cmd_mailbox(dev);
907 eq_context = mailbox->buf;
909 for (i = 0; i < npages; ++i) {
910 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
911 PAGE_SIZE, &t, GFP_KERNEL);
912 if (!eq->page_list[i].buf)
913 goto err_out_free_pages;
916 eq->page_list[i].map = t;
918 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
921 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
923 goto err_out_free_pages;
925 eq->doorbell = mlx4_get_eq_uar(dev, eq);
928 goto err_out_free_eq;
931 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
933 goto err_out_free_eq;
935 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
937 goto err_out_free_mtt;
939 memset(eq_context, 0, sizeof *eq_context);
940 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
941 MLX4_EQ_STATE_ARMED);
942 eq_context->log_eq_size = ilog2(eq->nent);
943 eq_context->intr = intr;
944 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
946 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
947 eq_context->mtt_base_addr_h = mtt_addr >> 32;
948 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
950 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
952 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
953 goto err_out_free_mtt;
957 mlx4_free_cmd_mailbox(dev, mailbox);
964 mlx4_mtt_cleanup(dev, &eq->mtt);
967 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
970 for (i = 0; i < npages; ++i)
971 if (eq->page_list[i].buf)
972 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
973 eq->page_list[i].buf,
974 eq->page_list[i].map);
976 mlx4_free_cmd_mailbox(dev, mailbox);
979 kfree(eq->page_list);
986 static void mlx4_free_eq(struct mlx4_dev *dev,
989 struct mlx4_priv *priv = mlx4_priv(dev);
990 struct mlx4_cmd_mailbox *mailbox;
993 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes */
994 int npages = PAGE_ALIGN((MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor) * eq->nent) / PAGE_SIZE;
996 mailbox = mlx4_alloc_cmd_mailbox(dev);
1000 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
1002 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
1005 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
1006 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
1008 pr_cont("[%02x] ", i * 4);
1009 pr_cont(" %08x", be32_to_cpup(mailbox->buf + i * 4));
1010 if ((i + 1) % 4 == 0)
1015 mlx4_mtt_cleanup(dev, &eq->mtt);
1016 for (i = 0; i < npages; ++i)
1017 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
1018 eq->page_list[i].buf,
1019 eq->page_list[i].map);
1021 kfree(eq->page_list);
1022 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
1023 mlx4_free_cmd_mailbox(dev, mailbox);
1026 static void mlx4_free_irqs(struct mlx4_dev *dev)
1028 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
1029 struct mlx4_priv *priv = mlx4_priv(dev);
1032 if (eq_table->have_irq)
1033 free_irq(dev->pdev->irq, dev);
1035 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1036 if (eq_table->eq[i].have_irq) {
1037 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
1038 eq_table->eq[i].have_irq = 0;
1041 for (i = 0; i < dev->caps.comp_pool; i++) {
1043 * Freeing the assigned irq's
1044 * all bits should be 0, but we need to validate
1046 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1047 /* NO need protecting*/
1048 vec = dev->caps.num_comp_vectors + 1 + i;
1049 free_irq(priv->eq_table.eq[vec].irq,
1050 &priv->eq_table.eq[vec]);
1055 kfree(eq_table->irq_names);
1058 static int mlx4_map_clr_int(struct mlx4_dev *dev)
1060 struct mlx4_priv *priv = mlx4_priv(dev);
1062 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
1063 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
1064 if (!priv->clr_base) {
1065 mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
1072 static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
1074 struct mlx4_priv *priv = mlx4_priv(dev);
1076 iounmap(priv->clr_base);
1079 int mlx4_alloc_eq_table(struct mlx4_dev *dev)
1081 struct mlx4_priv *priv = mlx4_priv(dev);
1083 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
1084 sizeof *priv->eq_table.eq, GFP_KERNEL);
1085 if (!priv->eq_table.eq)
1091 void mlx4_free_eq_table(struct mlx4_dev *dev)
1093 kfree(mlx4_priv(dev)->eq_table.eq);
1096 int mlx4_init_eq_table(struct mlx4_dev *dev)
1098 struct mlx4_priv *priv = mlx4_priv(dev);
1102 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev),
1103 sizeof *priv->eq_table.uar_map,
1105 if (!priv->eq_table.uar_map) {
1110 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
1111 dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0);
1115 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
1116 priv->eq_table.uar_map[i] = NULL;
1118 if (!mlx4_is_slave(dev)) {
1119 err = mlx4_map_clr_int(dev);
1121 goto err_out_bitmap;
1123 priv->eq_table.clr_mask =
1124 swab32(1 << (priv->eq_table.inta_pin & 31));
1125 priv->eq_table.clr_int = priv->clr_base +
1126 (priv->eq_table.inta_pin < 32 ? 4 : 0);
1129 priv->eq_table.irq_names =
1130 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 +
1131 dev->caps.comp_pool),
1133 if (!priv->eq_table.irq_names) {
1135 goto err_out_bitmap;
1138 for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
1139 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1140 dev->caps.reserved_cqs +
1142 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1143 &priv->eq_table.eq[i]);
1150 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
1151 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
1152 &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1156 /*if additional completion vectors poolsize is 0 this loop will not run*/
1157 for (i = dev->caps.num_comp_vectors + 1;
1158 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) {
1160 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1161 dev->caps.reserved_cqs +
1163 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1164 &priv->eq_table.eq[i]);
1172 if (dev->flags & MLX4_FLAG_MSI_X) {
1173 const char *eq_name;
1175 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
1176 if (i < dev->caps.num_comp_vectors) {
1177 snprintf(priv->eq_table.irq_names +
1178 i * MLX4_IRQNAME_SIZE,
1180 "mlx4-comp-%d@pci:%s", i,
1181 pci_name(dev->pdev));
1183 snprintf(priv->eq_table.irq_names +
1184 i * MLX4_IRQNAME_SIZE,
1186 "mlx4-async@pci:%s",
1187 pci_name(dev->pdev));
1190 eq_name = priv->eq_table.irq_names +
1191 i * MLX4_IRQNAME_SIZE;
1192 err = request_irq(priv->eq_table.eq[i].irq,
1193 mlx4_msi_x_interrupt, 0, eq_name,
1194 priv->eq_table.eq + i);
1198 priv->eq_table.eq[i].have_irq = 1;
1201 snprintf(priv->eq_table.irq_names,
1204 pci_name(dev->pdev));
1205 err = request_irq(dev->pdev->irq, mlx4_interrupt,
1206 IRQF_SHARED, priv->eq_table.irq_names, dev);
1210 priv->eq_table.have_irq = 1;
1213 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1214 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1216 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
1217 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
1219 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1220 eq_set_ci(&priv->eq_table.eq[i], 1);
1225 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1228 i = dev->caps.num_comp_vectors - 1;
1232 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1235 if (!mlx4_is_slave(dev))
1236 mlx4_unmap_clr_int(dev);
1237 mlx4_free_irqs(dev);
1240 mlx4_unmap_uar(dev);
1241 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1244 kfree(priv->eq_table.uar_map);
1249 void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
1251 struct mlx4_priv *priv = mlx4_priv(dev);
1254 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1,
1255 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1257 mlx4_free_irqs(dev);
1259 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i)
1260 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1262 if (!mlx4_is_slave(dev))
1263 mlx4_unmap_clr_int(dev);
1265 mlx4_unmap_uar(dev);
1266 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1268 kfree(priv->eq_table.uar_map);
1271 /* A test that verifies that we can accept interrupts on all
1272 * the irq vectors of the device.
1273 * Interrupts are checked using the NOP command.
1275 int mlx4_test_interrupts(struct mlx4_dev *dev)
1277 struct mlx4_priv *priv = mlx4_priv(dev);
1281 err = mlx4_NOP(dev);
1282 /* When not in MSI_X, there is only one irq to check */
1283 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev))
1286 /* A loop over all completion vectors, for each vector we will check
1287 * whether it works by mapping command completions to that vector
1288 * and performing a NOP command
1290 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) {
1291 /* Temporary use polling for command completions */
1292 mlx4_cmd_use_polling(dev);
1294 /* Map the new eq to handle all asynchronous events */
1295 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1296 priv->eq_table.eq[i].eqn);
1298 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1299 mlx4_cmd_use_events(dev);
1303 /* Go back to using events */
1304 mlx4_cmd_use_events(dev);
1305 err = mlx4_NOP(dev);
1308 /* Return to default */
1309 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1310 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1313 EXPORT_SYMBOL(mlx4_test_interrupts);
1315 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1319 struct mlx4_priv *priv = mlx4_priv(dev);
1320 int vec = 0, err = 0, i;
1322 mutex_lock(&priv->msix_ctl.pool_lock);
1323 for (i = 0; !vec && i < dev->caps.comp_pool; i++) {
1324 if (~priv->msix_ctl.pool_bm & 1ULL << i) {
1325 priv->msix_ctl.pool_bm |= 1ULL << i;
1326 vec = dev->caps.num_comp_vectors + 1 + i;
1327 snprintf(priv->eq_table.irq_names +
1328 vec * MLX4_IRQNAME_SIZE,
1329 MLX4_IRQNAME_SIZE, "%s", name);
1330 #ifdef CONFIG_RFS_ACCEL
1332 err = irq_cpu_rmap_add(rmap,
1333 priv->eq_table.eq[vec].irq);
1335 mlx4_warn(dev, "Failed adding irq rmap\n");
1338 err = request_irq(priv->eq_table.eq[vec].irq,
1339 mlx4_msi_x_interrupt, 0,
1340 &priv->eq_table.irq_names[vec<<5],
1341 priv->eq_table.eq + vec);
1343 /*zero out bit by fliping it*/
1344 priv->msix_ctl.pool_bm ^= 1 << i;
1347 /*we dont want to break here*/
1349 eq_set_ci(&priv->eq_table.eq[vec], 1);
1352 mutex_unlock(&priv->msix_ctl.pool_lock);
1358 err = (i == dev->caps.comp_pool) ? -ENOSPC : err;
1362 EXPORT_SYMBOL(mlx4_assign_eq);
1364 void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1366 struct mlx4_priv *priv = mlx4_priv(dev);
1368 int i = vec - dev->caps.num_comp_vectors - 1;
1370 if (likely(i >= 0)) {
1371 /*sanity check , making sure were not trying to free irq's
1372 Belonging to a legacy EQ*/
1373 mutex_lock(&priv->msix_ctl.pool_lock);
1374 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1375 free_irq(priv->eq_table.eq[vec].irq,
1376 &priv->eq_table.eq[vec]);
1377 priv->msix_ctl.pool_bm &= ~(1ULL << i);
1379 mutex_unlock(&priv->msix_ctl.pool_lock);
1383 EXPORT_SYMBOL(mlx4_release_eq);