Pileus Git - ~andy/linux/blob - drivers/net/ethernet/mellanox/mlx4/en_rx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <net/ll_poll.h>
  35 #include <linux/mlx4/cq.h>
  36 #include <linux/slab.h>
  37 #include <linux/mlx4/qp.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/rculist.h>
  40 #include <linux/if_ether.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/vmalloc.h>
  43
  44 #include "mlx4_en.h"
  45
  46 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
  47                                struct mlx4_en_rx_desc *rx_desc,
  48                                struct mlx4_en_rx_alloc *frags,
  49                                struct mlx4_en_rx_alloc *ring_alloc)
  50 {
  51         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
  52         struct mlx4_en_frag_info *frag_info;
  53         struct page *page;
  54         dma_addr_t dma;
  55         int i;
  56
  57         for (i = 0; i < priv->num_frags; i++) {
  58                 frag_info = &priv->frag_info[i];
  59                 if (ring_alloc[i].offset == frag_info->last_offset) {
  60                         page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
  61                                         MLX4_EN_ALLOC_ORDER);
  62                         if (!page)
  63                                 goto out;
  64                         dma = dma_map_page(priv->ddev, page, 0,
  65                                 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
  66                         if (dma_mapping_error(priv->ddev, dma)) {
  67                                 put_page(page);
  68                                 goto out;
  69                         }
  70                         page_alloc[i].page = page;
  71                         page_alloc[i].dma = dma;
  72                         page_alloc[i].offset = frag_info->frag_align;
  73                 } else {
  74                         page_alloc[i].page = ring_alloc[i].page;
  75                         get_page(ring_alloc[i].page);
  76                         page_alloc[i].dma = ring_alloc[i].dma;
  77                         page_alloc[i].offset = ring_alloc[i].offset +
  78                                                 frag_info->frag_stride;
  79                 }
  80         }
  81
  82         for (i = 0; i < priv->num_frags; i++) {
  83                 frags[i] = ring_alloc[i];
  84                 dma = ring_alloc[i].dma + ring_alloc[i].offset;
  85                 ring_alloc[i] = page_alloc[i];
  86                 rx_desc->data[i].addr = cpu_to_be64(dma);
  87         }
  88
  89         return 0;
  90
  91
  92 out:
  93         while (i--) {
  94                 frag_info = &priv->frag_info[i];
  95                 if (ring_alloc[i].offset == frag_info->last_offset)
  96                         dma_unmap_page(priv->ddev, page_alloc[i].dma,
  97                                 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
  98                 put_page(page_alloc[i].page);
  99         }
 100         return -ENOMEM;
 101 }
 102
 103 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
 104                               struct mlx4_en_rx_alloc *frags,
 105                               int i)
 106 {
 107         struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 108
 109         if (frags[i].offset == frag_info->last_offset) {
 110                 dma_unmap_page(priv->ddev, frags[i].dma, MLX4_EN_ALLOC_SIZE,
 111                                          PCI_DMA_FROMDEVICE);
 112         }
 113         if (frags[i].page)
 114                 put_page(frags[i].page);
 115 }
 116
 117 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
 118                                   struct mlx4_en_rx_ring *ring)
 119 {
 120         struct mlx4_en_rx_alloc *page_alloc;
 121         int i;
 122
 123         for (i = 0; i < priv->num_frags; i++) {
 124                 page_alloc = &ring->page_alloc[i];
 125                 page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
 126                                                MLX4_EN_ALLOC_ORDER);
 127                 if (!page_alloc->page)
 128                         goto out;
 129
 130                 page_alloc->dma = dma_map_page(priv->ddev, page_alloc->page, 0,
 131                                         MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
 132                 if (dma_mapping_error(priv->ddev, page_alloc->dma)) {
 133                         put_page(page_alloc->page);
 134                         page_alloc->page = NULL;
 135                         goto out;
 136                 }
 137                 page_alloc->offset = priv->frag_info[i].frag_align;
 138                 en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n",
 139                        i, page_alloc->page);
 140         }
 141         return 0;
 142
 143 out:
 144         while (i--) {
 145                 page_alloc = &ring->page_alloc[i];
 146                 dma_unmap_page(priv->ddev, page_alloc->dma,
 147                                 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
 148                 put_page(page_alloc->page);
 149                 page_alloc->page = NULL;
 150         }
 151         return -ENOMEM;
 152 }
 153
 154 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
 155                                       struct mlx4_en_rx_ring *ring)
 156 {
 157         struct mlx4_en_rx_alloc *page_alloc;
 158         int i;
 159
 160         for (i = 0; i < priv->num_frags; i++) {
 161                 page_alloc = &ring->page_alloc[i];
 162                 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
 163                        i, page_count(page_alloc->page));
 164
 165                 dma_unmap_page(priv->ddev, page_alloc->dma,
 166                                 MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
 167                 put_page(page_alloc->page);
 168                 page_alloc->page = NULL;
 169         }
 170 }
 171
 172 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
 173                                  struct mlx4_en_rx_ring *ring, int index)
 174 {
 175         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
 176         int possible_frags;
 177         int i;
 178
 179         /* Set size and memtype fields */
 180         for (i = 0; i < priv->num_frags; i++) {
 181                 rx_desc->data[i].byte_count =
 182                         cpu_to_be32(priv->frag_info[i].frag_size);
 183                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
 184         }
 185
 186         /* If the number of used fragments does not fill up the ring stride,
 187          * remaining (unused) fragments must be padded with null address/size
 188          * and a special memory key */
 189         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
 190         for (i = priv->num_frags; i < possible_frags; i++) {
 191                 rx_desc->data[i].byte_count = 0;
 192                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
 193                 rx_desc->data[i].addr = 0;
 194         }
 195 }
 196
 197 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 198                                    struct mlx4_en_rx_ring *ring, int index)
 199 {
 200         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
 201         struct mlx4_en_rx_alloc *frags = ring->rx_info +
 202                                         (index << priv->log_rx_info);
 203
 204         return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc);
 205 }
 206
 207 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 208 {
 209         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 210 }
 211
 212 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
 213                                  struct mlx4_en_rx_ring *ring,
 214                                  int index)
 215 {
 216         struct mlx4_en_rx_alloc *frags;
 217         int nr;
 218
 219         frags = ring->rx_info + (index << priv->log_rx_info);
 220         for (nr = 0; nr < priv->num_frags; nr++) {
 221                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
 222                 mlx4_en_free_frag(priv, frags, nr);
 223         }
 224 }
 225
 226 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 227 {
 228         struct mlx4_en_rx_ring *ring;
 229         int ring_ind;
 230         int buf_ind;
 231         int new_size;
 232
 233         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 234                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 235                         ring = &priv->rx_ring[ring_ind];
 236
 237                         if (mlx4_en_prepare_rx_desc(priv, ring,
 238                                                     ring->actual_size)) {
 239                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
 240                                         en_err(priv, "Failed to allocate "
 241                                                      "enough rx buffers\n");
 242                                         return -ENOMEM;
 243                                 } else {
 244                                         new_size = rounddown_pow_of_two(ring->actual_size);
 245                                         en_warn(priv, "Only %d buffers allocated "
 246                                                       "reducing ring size to %d",
 247                                                 ring->actual_size, new_size);
 248                                         goto reduce_rings;
 249                                 }
 250                         }
 251                         ring->actual_size++;
 252                         ring->prod++;
 253                 }
 254         }
 255         return 0;
 256
 257 reduce_rings:
 258         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 259                 ring = &priv->rx_ring[ring_ind];
 260                 while (ring->actual_size > new_size) {
 261                         ring->actual_size--;
 262                         ring->prod--;
 263                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
 264                 }
 265         }
 266
 267         return 0;
 268 }
 269
 270 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 271                                 struct mlx4_en_rx_ring *ring)
 272 {
 273         int index;
 274
 275         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 276                ring->cons, ring->prod);
 277
 278         /* Unmap and free Rx buffers */
 279         BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
 280         while (ring->cons != ring->prod) {
 281                 index = ring->cons & ring->size_mask;
 282                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 283                 mlx4_en_free_rx_desc(priv, ring, index);
 284                 ++ring->cons;
 285         }
 286 }
 287
 288 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 289                            struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
 290 {
 291         struct mlx4_en_dev *mdev = priv->mdev;
 292         int err = -ENOMEM;
 293         int tmp;
 294
 295         ring->prod = 0;
 296         ring->cons = 0;
 297         ring->size = size;
 298         ring->size_mask = size - 1;
 299         ring->stride = stride;
 300         ring->log_stride = ffs(ring->stride) - 1;
 301         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 302
 303         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
 304                                         sizeof(struct mlx4_en_rx_alloc));
 305         ring->rx_info = vmalloc(tmp);
 306         if (!ring->rx_info)
 307                 return -ENOMEM;
 308
 309         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
 310                  ring->rx_info, tmp);
 311
 312         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
 313                                  ring->buf_size, 2 * PAGE_SIZE);
 314         if (err)
 315                 goto err_ring;
 316
 317         err = mlx4_en_map_buffer(&ring->wqres.buf);
 318         if (err) {
 319                 en_err(priv, "Failed to map RX buffer\n");
 320                 goto err_hwq;
 321         }
 322         ring->buf = ring->wqres.buf.direct.buf;
 323
 324         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
 325
 326         return 0;
 327
 328 err_hwq:
 329         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 330 err_ring:
 331         vfree(ring->rx_info);
 332         ring->rx_info = NULL;
 333         return err;
 334 }
 335
 336 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 337 {
 338         struct mlx4_en_rx_ring *ring;
 339         int i;
 340         int ring_ind;
 341         int err;
 342         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 343                                         DS_SIZE * priv->num_frags);
 344
 345         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 346                 ring = &priv->rx_ring[ring_ind];
 347
 348                 ring->prod = 0;
 349                 ring->cons = 0;
 350                 ring->actual_size = 0;
 351                 ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
 352
 353                 ring->stride = stride;
 354                 if (ring->stride <= TXBB_SIZE)
 355                         ring->buf += TXBB_SIZE;
 356
 357                 ring->log_stride = ffs(ring->stride) - 1;
 358                 ring->buf_size = ring->size * ring->stride;
 359
 360                 memset(ring->buf, 0, ring->buf_size);
 361                 mlx4_en_update_rx_prod_db(ring);
 362
 363                 /* Initialize all descriptors */
 364                 for (i = 0; i < ring->size; i++)
 365                         mlx4_en_init_rx_desc(priv, ring, i);
 366
 367                 /* Initialize page allocators */
 368                 err = mlx4_en_init_allocator(priv, ring);
 369                 if (err) {
 370                         en_err(priv, "Failed initializing ring allocator\n");
 371                         if (ring->stride <= TXBB_SIZE)
 372                                 ring->buf -= TXBB_SIZE;
 373                         ring_ind--;
 374                         goto err_allocator;
 375                 }
 376         }
 377         err = mlx4_en_fill_rx_buffers(priv);
 378         if (err)
 379                 goto err_buffers;
 380
 381         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 382                 ring = &priv->rx_ring[ring_ind];
 383
 384                 ring->size_mask = ring->actual_size - 1;
 385                 mlx4_en_update_rx_prod_db(ring);
 386         }
 387
 388         return 0;
 389
 390 err_buffers:
 391         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 392                 mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
 393
 394         ring_ind = priv->rx_ring_num - 1;
 395 err_allocator:
 396         while (ring_ind >= 0) {
 397                 if (priv->rx_ring[ring_ind].stride <= TXBB_SIZE)
 398                         priv->rx_ring[ring_ind].buf -= TXBB_SIZE;
 399                 mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]);
 400                 ring_ind--;
 401         }
 402         return err;
 403 }
 404
 405 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 406                              struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
 407 {
 408         struct mlx4_en_dev *mdev = priv->mdev;
 409
 410         mlx4_en_unmap_buffer(&ring->wqres.buf);
 411         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 412         vfree(ring->rx_info);
 413         ring->rx_info = NULL;
 414 #ifdef CONFIG_RFS_ACCEL
 415         mlx4_en_cleanup_filters(priv, ring);
 416 #endif
 417 }
 418
 419 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 420                                 struct mlx4_en_rx_ring *ring)
 421 {
 422         mlx4_en_free_rx_buf(priv, ring);
 423         if (ring->stride <= TXBB_SIZE)
 424                 ring->buf -= TXBB_SIZE;
 425         mlx4_en_destroy_allocator(priv, ring);
 426 }
 427
 428
 429 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
 430                                     struct mlx4_en_rx_desc *rx_desc,
 431                                     struct mlx4_en_rx_alloc *frags,
 432                                     struct sk_buff *skb,
 433                                     int length)
 434 {
 435         struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
 436         struct mlx4_en_frag_info *frag_info;
 437         int nr;
 438         dma_addr_t dma;
 439
 440         /* Collect used fragments while replacing them in the HW descriptors */
 441         for (nr = 0; nr < priv->num_frags; nr++) {
 442                 frag_info = &priv->frag_info[nr];
 443                 if (length <= frag_info->frag_prefix_size)
 444                         break;
 445                 if (!frags[nr].page)
 446                         goto fail;
 447
 448                 dma = be64_to_cpu(rx_desc->data[nr].addr);
 449                 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
 450                                         DMA_FROM_DEVICE);
 451
 452                 /* Save page reference in skb */
 453                 get_page(frags[nr].page);
 454                 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
 455                 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
 456                 skb_frags_rx[nr].page_offset = frags[nr].offset;
 457                 skb->truesize += frag_info->frag_stride;
 458         }
 459         /* Adjust size of last fragment to match actual length */
 460         if (nr > 0)
 461                 skb_frag_size_set(&skb_frags_rx[nr - 1],
 462                         length - priv->frag_info[nr - 1].frag_prefix_size);
 463         return nr;
 464
 465 fail:
 466         while (nr > 0) {
 467                 nr--;
 468                 __skb_frag_unref(&skb_frags_rx[nr]);
 469         }
 470         return 0;
 471 }
 472
 473
 474 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
 475                                       struct mlx4_en_rx_desc *rx_desc,
 476                                       struct mlx4_en_rx_alloc *frags,
 477                                       unsigned int length)
 478 {
 479         struct sk_buff *skb;
 480         void *va;
 481         int used_frags;
 482         dma_addr_t dma;
 483
 484         skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
 485         if (!skb) {
 486                 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
 487                 return NULL;
 488         }
 489         skb_reserve(skb, NET_IP_ALIGN);
 490         skb->len = length;
 491
 492         /* Get pointer to first fragment so we could copy the headers into the
 493          * (linear part of the) skb */
 494         va = page_address(frags[0].page) + frags[0].offset;
 495
 496         if (length <= SMALL_PACKET_SIZE) {
 497                 /* We are copying all relevant data to the skb - temporarily
 498                  * sync buffers for the copy */
 499                 dma = be64_to_cpu(rx_desc->data[0].addr);
 500                 dma_sync_single_for_cpu(priv->ddev, dma, length,
 501                                         DMA_FROM_DEVICE);
 502                 skb_copy_to_linear_data(skb, va, length);
 503                 skb->tail += length;
 504         } else {
 505                 /* Move relevant fragments to skb */
 506                 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
 507                                                         skb, length);
 508                 if (unlikely(!used_frags)) {
 509                         kfree_skb(skb);
 510                         return NULL;
 511                 }
 512                 skb_shinfo(skb)->nr_frags = used_frags;
 513
 514                 /* Copy headers into the skb linear buffer */
 515                 memcpy(skb->data, va, HEADER_COPY_SIZE);
 516                 skb->tail += HEADER_COPY_SIZE;
 517
 518                 /* Skip headers in first fragment */
 519                 skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
 520
 521                 /* Adjust size of first fragment */
 522                 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE);
 523                 skb->data_len = length - HEADER_COPY_SIZE;
 524         }
 525         return skb;
 526 }
 527
 528 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
 529 {
 530         int i;
 531         int offset = ETH_HLEN;
 532
 533         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
 534                 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
 535                         goto out_loopback;
 536         }
 537         /* Loopback found */
 538         priv->loopback_ok = 1;
 539
 540 out_loopback:
 541         dev_kfree_skb_any(skb);
 542 }
 543
 544 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
 545                                      struct mlx4_en_rx_ring *ring)
 546 {
 547         int index = ring->prod & ring->size_mask;
 548
 549         while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
 550                 if (mlx4_en_prepare_rx_desc(priv, ring, index))
 551                         break;
 552                 ring->prod++;
 553                 index = ring->prod & ring->size_mask;
 554         }
 555 }
 556
 557 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 558 {
 559         struct mlx4_en_priv *priv = netdev_priv(dev);
 560         struct mlx4_en_dev *mdev = priv->mdev;
 561         struct mlx4_cqe *cqe;
 562         struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
 563         struct mlx4_en_rx_alloc *frags;
 564         struct mlx4_en_rx_desc *rx_desc;
 565         struct sk_buff *skb;
 566         int index;
 567         int nr;
 568         unsigned int length;
 569         int polled = 0;
 570         int ip_summed;
 571         int factor = priv->cqe_factor;
 572         u64 timestamp;
 573
 574         if (!priv->port_up)
 575                 return 0;
 576
 577         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 578          * descriptor offset can be deduced from the CQE index instead of
 579          * reading 'cqe->index' */
 580         index = cq->mcq.cons_index & ring->size_mask;
 581         cqe = &cq->buf[(index << factor) + factor];
 582
 583         /* Process all completed CQEs */
 584         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 585                     cq->mcq.cons_index & cq->size)) {
 586
 587                 frags = ring->rx_info + (index << priv->log_rx_info);
 588                 rx_desc = ring->buf + (index << ring->log_stride);
 589
 590                 /*
 591                  * make sure we read the CQE after we read the ownership bit
 592                  */
 593                 rmb();
 594
 595                 /* Drop packet on bad receive or bad checksum */
 596                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 597                                                 MLX4_CQE_OPCODE_ERROR)) {
 598                         en_err(priv, "CQE completed in error - vendor "
 599                                   "syndrom:%d syndrom:%d\n",
 600                                   ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
 601                                   ((struct mlx4_err_cqe *) cqe)->syndrome);
 602                         goto next;
 603                 }
 604                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 605                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 606                         goto next;
 607                 }
 608
 609                 /* Check if we need to drop the packet if SRIOV is not enabled
 610                  * and not performing the selftest or flb disabled
 611                  */
 612                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
 613                         struct ethhdr *ethh;
 614                         dma_addr_t dma;
 615                         /* Get pointer to first fragment since we haven't
 616                          * skb yet and cast it to ethhdr struct
 617                          */
 618                         dma = be64_to_cpu(rx_desc->data[0].addr);
 619                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
 620                                                 DMA_FROM_DEVICE);
 621                         ethh = (struct ethhdr *)(page_address(frags[0].page) +
 622                                                  frags[0].offset);
 623
 624                         if (is_multicast_ether_addr(ethh->h_dest)) {
 625                                 struct mlx4_mac_entry *entry;
 626                                 struct hlist_head *bucket;
 627                                 unsigned int mac_hash;
 628
 629                                 /* Drop the packet, since HW loopback-ed it */
 630                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
 631                                 bucket = &priv->mac_hash[mac_hash];
 632                                 rcu_read_lock();
 633                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
 634                                         if (ether_addr_equal_64bits(entry->mac,
 635                                                                     ethh->h_source)) {
 636                                                 rcu_read_unlock();
 637                                                 goto next;
 638                                         }
 639                                 }
 640                                 rcu_read_unlock();
 641                         }
 642                 }
 643
 644                 /*
 645                  * Packet is OK - process it.
 646                  */
 647                 length = be32_to_cpu(cqe->byte_cnt);
 648                 length -= ring->fcs_del;
 649                 ring->bytes += length;
 650                 ring->packets++;
 651
 652                 if (likely(dev->features & NETIF_F_RXCSUM)) {
 653                         if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 654                             (cqe->checksum == cpu_to_be16(0xffff))) {
 655                                 ring->csum_ok++;
 656                                 /* This packet is eligible for GRO if it is:
 657                                  * - DIX Ethernet (type interpretation)
 658                                  * - TCP/IP (v4)
 659                                  * - without IP options
 660                                  * - not an IP fragment
 661                                  * - no LLS polling in progress
 662                                  */
 663                                 if (!mlx4_en_cq_ll_polling(cq) &&
 664                                     (dev->features & NETIF_F_GRO)) {
 665                                         struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
 666                                         if (!gro_skb)
 667                                                 goto next;
 668
 669                                         nr = mlx4_en_complete_rx_desc(priv,
 670                                                 rx_desc, frags, gro_skb,
 671                                                 length);
 672                                         if (!nr)
 673                                                 goto next;
 674
 675                                         skb_shinfo(gro_skb)->nr_frags = nr;
 676                                         gro_skb->len = length;
 677                                         gro_skb->data_len = length;
 678                                         gro_skb->ip_summed = CHECKSUM_UNNECESSARY;
 679
 680                                         if ((cqe->vlan_my_qpn &
 681                                             cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) &&
 682                                             (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
 683                                                 u16 vid = be16_to_cpu(cqe->sl_vid);
 684
 685                                                 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
 686                                         }
 687
 688                                         if (dev->features & NETIF_F_RXHASH)
 689                                                 gro_skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
 690
 691                                         skb_record_rx_queue(gro_skb, cq->ring);
 692
 693                                         if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
 694                                                 timestamp = mlx4_en_get_cqe_ts(cqe);
 695                                                 mlx4_en_fill_hwtstamps(mdev,
 696                                                                        skb_hwtstamps(gro_skb),
 697                                                                        timestamp);
 698                                         }
 699
 700                                         napi_gro_frags(&cq->napi);
 701                                         goto next;
 702                                 }
 703
 704                                 /* GRO not possible, complete processing here */
 705                                 ip_summed = CHECKSUM_UNNECESSARY;
 706                         } else {
 707                                 ip_summed = CHECKSUM_NONE;
 708                                 ring->csum_none++;
 709                         }
 710                 } else {
 711                         ip_summed = CHECKSUM_NONE;
 712                         ring->csum_none++;
 713                 }
 714
 715                 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
 716                 if (!skb) {
 717                         priv->stats.rx_dropped++;
 718                         goto next;
 719                 }
 720
 721                 if (unlikely(priv->validate_loopback)) {
 722                         validate_loopback(priv, skb);
 723                         goto next;
 724                 }
 725
 726                 skb->ip_summed = ip_summed;
 727                 skb->protocol = eth_type_trans(skb, dev);
 728                 skb_record_rx_queue(skb, cq->ring);
 729
 730                 if (dev->features & NETIF_F_RXHASH)
 731                         skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
 732
 733                 if ((be32_to_cpu(cqe->vlan_my_qpn) &
 734                     MLX4_CQE_VLAN_PRESENT_MASK) &&
 735                     (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
 736                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
 737
 738                 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
 739                         timestamp = mlx4_en_get_cqe_ts(cqe);
 740                         mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
 741                                                timestamp);
 742                 }
 743
 744                 skb_mark_ll(skb, &cq->napi);
 745
 746                 /* Push it up the stack */
 747                 netif_receive_skb(skb);
 748
 749 next:
 750                 for (nr = 0; nr < priv->num_frags; nr++)
 751                         mlx4_en_free_frag(priv, frags, nr);
 752
 753                 ++cq->mcq.cons_index;
 754                 index = (cq->mcq.cons_index) & ring->size_mask;
 755                 cqe = &cq->buf[(index << factor) + factor];
 756                 if (++polled == budget)
 757                         goto out;
 758         }
 759
 760 out:
 761         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
 762         mlx4_cq_set_ci(&cq->mcq);
 763         wmb(); /* ensure HW sees CQ consumer before we post new buffers */
 764         ring->cons = cq->mcq.cons_index;
 765         mlx4_en_refill_rx_buffers(priv, ring);
 766         mlx4_en_update_rx_prod_db(ring);
 767         return polled;
 768 }
 769
 770
 771 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
 772 {
 773         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 774         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 775
 776         if (priv->port_up)
 777                 napi_schedule(&cq->napi);
 778         else
 779                 mlx4_en_arm_cq(priv, cq);
 780 }
 781
 782 /* Rx CQ polling - called by NAPI */
 783 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
 784 {
 785         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
 786         struct net_device *dev = cq->dev;
 787         struct mlx4_en_priv *priv = netdev_priv(dev);
 788         int done;
 789
 790         if (!mlx4_en_cq_lock_napi(cq))
 791                 return budget;
 792
 793         done = mlx4_en_process_rx_cq(dev, cq, budget);
 794
 795         mlx4_en_cq_unlock_napi(cq);
 796
 797         /* If we used up all the quota - we're probably not done yet... */
 798         if (done == budget)
 799                 INC_PERF_COUNTER(priv->pstats.napi_quota);
 800         else {
 801                 /* Done for now */
 802                 napi_complete(napi);
 803                 mlx4_en_arm_cq(priv, cq);
 804         }
 805         return done;
 806 }
 807
 808
 809 /* Calculate the last offset position that accommodates a full fragment
 810  * (assuming fagment size = stride-align) */
 811 static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align)
 812 {
 813         u16 res = MLX4_EN_ALLOC_SIZE % stride;
 814         u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align;
 815
 816         en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d "
 817                             "res:%d offset:%d\n", stride, align, res, offset);
 818         return offset;
 819 }
 820
 821
 822 static int frag_sizes[] = {
 823         FRAG_SZ0,
 824         FRAG_SZ1,
 825         FRAG_SZ2,
 826         FRAG_SZ3
 827 };
 828
 829 void mlx4_en_calc_rx_buf(struct net_device *dev)
 830 {
 831         struct mlx4_en_priv *priv = netdev_priv(dev);
 832         int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
 833         int buf_size = 0;
 834         int i = 0;
 835
 836         while (buf_size < eff_mtu) {
 837                 priv->frag_info[i].frag_size =
 838                         (eff_mtu > buf_size + frag_sizes[i]) ?
 839                                 frag_sizes[i] : eff_mtu - buf_size;
 840                 priv->frag_info[i].frag_prefix_size = buf_size;
 841                 if (!i) {
 842                         priv->frag_info[i].frag_align = NET_IP_ALIGN;
 843                         priv->frag_info[i].frag_stride =
 844                                 ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
 845                 } else {
 846                         priv->frag_info[i].frag_align = 0;
 847                         priv->frag_info[i].frag_stride =
 848                                 ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
 849                 }
 850                 priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset(
 851                                                 priv, priv->frag_info[i].frag_stride,
 852                                                 priv->frag_info[i].frag_align);
 853                 buf_size += priv->frag_info[i].frag_size;
 854                 i++;
 855         }
 856
 857         priv->num_frags = i;
 858         priv->rx_skb_size = eff_mtu;
 859         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
 860
 861         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
 862                   "num_frags:%d):\n", eff_mtu, priv->num_frags);
 863         for (i = 0; i < priv->num_frags; i++) {
 864                 en_dbg(DRV, priv, "  frag:%d - size:%d prefix:%d align:%d "
 865                                 "stride:%d last_offset:%d\n", i,
 866                                 priv->frag_info[i].frag_size,
 867                                 priv->frag_info[i].frag_prefix_size,
 868                                 priv->frag_info[i].frag_align,
 869                                 priv->frag_info[i].frag_stride,
 870                                 priv->frag_info[i].last_offset);
 871         }
 872 }
 873
 874 /* RSS related functions */
 875
 876 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
 877                                  struct mlx4_en_rx_ring *ring,
 878                                  enum mlx4_qp_state *state,
 879                                  struct mlx4_qp *qp)
 880 {
 881         struct mlx4_en_dev *mdev = priv->mdev;
 882         struct mlx4_qp_context *context;
 883         int err = 0;
 884
 885         context = kmalloc(sizeof(*context), GFP_KERNEL);
 886         if (!context)
 887                 return -ENOMEM;
 888
 889         err = mlx4_qp_alloc(mdev->dev, qpn, qp);
 890         if (err) {
 891                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
 892                 goto out;
 893         }
 894         qp->event = mlx4_en_sqp_event;
 895
 896         memset(context, 0, sizeof *context);
 897         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
 898                                 qpn, ring->cqn, -1, context);
 899         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
 900
 901         /* Cancel FCS removal if FW allows */
 902         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
 903                 context->param3 |= cpu_to_be32(1 << 29);
 904                 ring->fcs_del = ETH_FCS_LEN;
 905         } else
 906                 ring->fcs_del = 0;
 907
 908         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
 909         if (err) {
 910                 mlx4_qp_remove(mdev->dev, qp);
 911                 mlx4_qp_free(mdev->dev, qp);
 912         }
 913         mlx4_en_update_rx_prod_db(ring);
 914 out:
 915         kfree(context);
 916         return err;
 917 }
 918
 919 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
 920 {
 921         int err;
 922         u32 qpn;
 923
 924         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn);
 925         if (err) {
 926                 en_err(priv, "Failed reserving drop qpn\n");
 927                 return err;
 928         }
 929         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp);
 930         if (err) {
 931                 en_err(priv, "Failed allocating drop qp\n");
 932                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
 933                 return err;
 934         }
 935
 936         return 0;
 937 }
 938
 939 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
 940 {
 941         u32 qpn;
 942
 943         qpn = priv->drop_qp.qpn;
 944         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
 945         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
 946         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
 947 }
 948
 949 /* Allocate rx qp's and configure them according to rss map */
 950 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
 951 {
 952         struct mlx4_en_dev *mdev = priv->mdev;
 953         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
 954         struct mlx4_qp_context context;
 955         struct mlx4_rss_context *rss_context;
 956         int rss_rings;
 957         void *ptr;
 958         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
 959                         MLX4_RSS_TCP_IPV6);
 960         int i, qpn;
 961         int err = 0;
 962         int good_qps = 0;
 963         static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC,
 964                                 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD,
 965                                 0x593D56D9, 0xF3253C06, 0x2ADC1FFC};
 966
 967         en_dbg(DRV, priv, "Configuring rss steering\n");
 968         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
 969                                     priv->rx_ring_num,
 970                                     &rss_map->base_qpn);
 971         if (err) {
 972                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
 973                 return err;
 974         }
 975
 976         for (i = 0; i < priv->rx_ring_num; i++) {
 977                 qpn = rss_map->base_qpn + i;
 978                 err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i],
 979                                             &rss_map->state[i],
 980                                             &rss_map->qps[i]);
 981                 if (err)
 982                         goto rss_err;
 983
 984                 ++good_qps;
 985         }
 986
 987         /* Configure RSS indirection qp */
 988         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
 989         if (err) {
 990                 en_err(priv, "Failed to allocate RSS indirection QP\n");
 991                 goto rss_err;
 992         }
 993         rss_map->indir_qp.event = mlx4_en_sqp_event;
 994         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
 995                                 priv->rx_ring[0].cqn, -1, &context);
 996
 997         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
 998                 rss_rings = priv->rx_ring_num;
 999         else
1000                 rss_rings = priv->prof->rss_rings;
1001
1002         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1003                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1004         rss_context = ptr;
1005         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1006                                             (rss_map->base_qpn));
1007         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1008         if (priv->mdev->profile.udp_rss) {
1009                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1010                 rss_context->base_qpn_udp = rss_context->default_qpn;
1011         }
1012         rss_context->flags = rss_mask;
1013         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1014         for (i = 0; i < 10; i++)
1015                 rss_context->rss_key[i] = cpu_to_be32(rsskey[i]);
1016
1017         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1018                                &rss_map->indir_qp, &rss_map->indir_state);
1019         if (err)
1020                 goto indir_err;
1021
1022         return 0;
1023
1024 indir_err:
1025         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1026                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1027         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1028         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1029 rss_err:
1030         for (i = 0; i < good_qps; i++) {
1031                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1032                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1033                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1034                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1035         }
1036         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1037         return err;
1038 }
1039
1040 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1041 {
1042         struct mlx4_en_dev *mdev = priv->mdev;
1043         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1044         int i;
1045
1046         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1047                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1048         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1049         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1050
1051         for (i = 0; i < priv->rx_ring_num; i++) {
1052                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1053                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1054                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1055                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1056         }
1057         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1058 }