2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/init.h>
38 #include <linux/hardirq.h>
39 #include <linux/export.h>
41 #include <linux/mlx4/cmd.h>
42 #include <linux/mlx4/cq.h>
47 #define MLX4_CQ_STATUS_OK ( 0 << 28)
48 #define MLX4_CQ_STATUS_OVERFLOW ( 9 << 28)
49 #define MLX4_CQ_STATUS_WRITE_FAIL (10 << 28)
50 #define MLX4_CQ_FLAG_CC ( 1 << 18)
51 #define MLX4_CQ_FLAG_OI ( 1 << 17)
52 #define MLX4_CQ_STATE_ARMED ( 9 << 8)
53 #define MLX4_CQ_STATE_ARMED_SOL ( 6 << 8)
54 #define MLX4_EQ_STATE_FIRED (10 << 8)
56 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn)
60 cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree,
61 cqn & (dev->caps.num_cqs - 1));
63 mlx4_dbg(dev, "Completion event for bogus CQ %08x\n", cqn);
72 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type)
74 struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
77 spin_lock(&cq_table->lock);
79 cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1));
81 atomic_inc(&cq->refcount);
83 spin_unlock(&cq_table->lock);
86 mlx4_warn(dev, "Async event for bogus CQ %08x\n", cqn);
90 cq->event(cq, event_type);
92 if (atomic_dec_and_test(&cq->refcount))
96 static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
99 return mlx4_cmd(dev, mailbox->dma, cq_num, 0,
100 MLX4_CMD_SW2HW_CQ, MLX4_CMD_TIME_CLASS_A,
104 static int mlx4_MODIFY_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
105 int cq_num, u32 opmod)
107 return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
108 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
111 static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
114 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
115 cq_num, mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ,
116 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
119 int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
120 u16 count, u16 period)
122 struct mlx4_cmd_mailbox *mailbox;
123 struct mlx4_cq_context *cq_context;
126 mailbox = mlx4_alloc_cmd_mailbox(dev);
128 return PTR_ERR(mailbox);
130 cq_context = mailbox->buf;
131 memset(cq_context, 0, sizeof *cq_context);
133 cq_context->cq_max_count = cpu_to_be16(count);
134 cq_context->cq_period = cpu_to_be16(period);
136 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1);
138 mlx4_free_cmd_mailbox(dev, mailbox);
141 EXPORT_SYMBOL_GPL(mlx4_cq_modify);
143 int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq,
144 int entries, struct mlx4_mtt *mtt)
146 struct mlx4_cmd_mailbox *mailbox;
147 struct mlx4_cq_context *cq_context;
151 mailbox = mlx4_alloc_cmd_mailbox(dev);
153 return PTR_ERR(mailbox);
155 cq_context = mailbox->buf;
156 memset(cq_context, 0, sizeof *cq_context);
158 cq_context->logsize_usrpage = cpu_to_be32(ilog2(entries) << 24);
159 cq_context->log_page_size = mtt->page_shift - 12;
160 mtt_addr = mlx4_mtt_addr(dev, mtt);
161 cq_context->mtt_base_addr_h = mtt_addr >> 32;
162 cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
164 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 0);
166 mlx4_free_cmd_mailbox(dev, mailbox);
169 EXPORT_SYMBOL_GPL(mlx4_cq_resize);
171 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn)
173 struct mlx4_priv *priv = mlx4_priv(dev);
174 struct mlx4_cq_table *cq_table = &priv->cq_table;
177 *cqn = mlx4_bitmap_alloc(&cq_table->bitmap);
181 err = mlx4_table_get(dev, &cq_table->table, *cqn);
185 err = mlx4_table_get(dev, &cq_table->cmpt_table, *cqn);
191 mlx4_table_put(dev, &cq_table->table, *cqn);
194 mlx4_bitmap_free(&cq_table->bitmap, *cqn);
198 static int mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn)
203 if (mlx4_is_mfunc(dev)) {
204 err = mlx4_cmd_imm(dev, 0, &out_param, RES_CQ,
205 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
206 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
210 *cqn = get_param_l(&out_param);
214 return __mlx4_cq_alloc_icm(dev, cqn);
217 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
219 struct mlx4_priv *priv = mlx4_priv(dev);
220 struct mlx4_cq_table *cq_table = &priv->cq_table;
222 mlx4_table_put(dev, &cq_table->cmpt_table, cqn);
223 mlx4_table_put(dev, &cq_table->table, cqn);
224 mlx4_bitmap_free(&cq_table->bitmap, cqn);
227 static void mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
232 if (mlx4_is_mfunc(dev)) {
233 set_param_l(&in_param, cqn);
234 err = mlx4_cmd(dev, in_param, RES_CQ, RES_OP_RESERVE_AND_MAP,
236 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
238 mlx4_warn(dev, "Failed freeing cq:%d\n", cqn);
240 __mlx4_cq_free_icm(dev, cqn);
243 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent,
244 struct mlx4_mtt *mtt, struct mlx4_uar *uar, u64 db_rec,
245 struct mlx4_cq *cq, unsigned vector, int collapsed,
248 struct mlx4_priv *priv = mlx4_priv(dev);
249 struct mlx4_cq_table *cq_table = &priv->cq_table;
250 struct mlx4_cmd_mailbox *mailbox;
251 struct mlx4_cq_context *cq_context;
255 if (vector > dev->caps.num_comp_vectors + dev->caps.comp_pool)
260 err = mlx4_cq_alloc_icm(dev, &cq->cqn);
264 spin_lock_irq(&cq_table->lock);
265 err = radix_tree_insert(&cq_table->tree, cq->cqn, cq);
266 spin_unlock_irq(&cq_table->lock);
270 mailbox = mlx4_alloc_cmd_mailbox(dev);
271 if (IS_ERR(mailbox)) {
272 err = PTR_ERR(mailbox);
276 cq_context = mailbox->buf;
277 memset(cq_context, 0, sizeof *cq_context);
279 cq_context->flags = cpu_to_be32(!!collapsed << 18);
281 cq_context->flags |= cpu_to_be32(1 << 19);
283 cq_context->logsize_usrpage = cpu_to_be32((ilog2(nent) << 24) | uar->index);
284 cq_context->comp_eqn = priv->eq_table.eq[vector].eqn;
285 cq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
287 mtt_addr = mlx4_mtt_addr(dev, mtt);
288 cq_context->mtt_base_addr_h = mtt_addr >> 32;
289 cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
290 cq_context->db_rec_addr = cpu_to_be64(db_rec);
292 err = mlx4_SW2HW_CQ(dev, mailbox, cq->cqn);
293 mlx4_free_cmd_mailbox(dev, mailbox);
300 atomic_set(&cq->refcount, 1);
301 init_completion(&cq->free);
306 spin_lock_irq(&cq_table->lock);
307 radix_tree_delete(&cq_table->tree, cq->cqn);
308 spin_unlock_irq(&cq_table->lock);
311 mlx4_cq_free_icm(dev, cq->cqn);
315 EXPORT_SYMBOL_GPL(mlx4_cq_alloc);
317 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq)
319 struct mlx4_priv *priv = mlx4_priv(dev);
320 struct mlx4_cq_table *cq_table = &priv->cq_table;
323 err = mlx4_HW2SW_CQ(dev, NULL, cq->cqn);
325 mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn);
327 synchronize_irq(priv->eq_table.eq[cq->vector].irq);
329 spin_lock_irq(&cq_table->lock);
330 radix_tree_delete(&cq_table->tree, cq->cqn);
331 spin_unlock_irq(&cq_table->lock);
333 if (atomic_dec_and_test(&cq->refcount))
335 wait_for_completion(&cq->free);
337 mlx4_cq_free_icm(dev, cq->cqn);
339 EXPORT_SYMBOL_GPL(mlx4_cq_free);
341 int mlx4_init_cq_table(struct mlx4_dev *dev)
343 struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
346 spin_lock_init(&cq_table->lock);
347 INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
348 if (mlx4_is_slave(dev))
351 err = mlx4_bitmap_init(&cq_table->bitmap, dev->caps.num_cqs,
352 dev->caps.num_cqs - 1, dev->caps.reserved_cqs, 0);
359 void mlx4_cleanup_cq_table(struct mlx4_dev *dev)
361 if (mlx4_is_slave(dev))
363 /* Nothing to do to clean up radix_tree */
364 mlx4_bitmap_cleanup(&mlx4_priv(dev)->cq_table.bitmap);