2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/skbuff.h>
19 #include <linux/inetdevice.h>
20 #include <linux/mbus.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/of_address.h>
30 #include <linux/phy.h>
31 #include <linux/clk.h>
34 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
35 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
36 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
37 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
38 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
39 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
40 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
41 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
42 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
43 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
44 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
45 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
46 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
47 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
48 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
49 #define MVNETA_PORT_RX_RESET 0x1cc0
50 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
51 #define MVNETA_PHY_ADDR 0x2000
52 #define MVNETA_PHY_ADDR_MASK 0x1f
53 #define MVNETA_MBUS_RETRY 0x2010
54 #define MVNETA_UNIT_INTR_CAUSE 0x2080
55 #define MVNETA_UNIT_CONTROL 0x20B0
56 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
57 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
58 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
59 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
60 #define MVNETA_BASE_ADDR_ENABLE 0x2290
61 #define MVNETA_PORT_CONFIG 0x2400
62 #define MVNETA_UNI_PROMISC_MODE BIT(0)
63 #define MVNETA_DEF_RXQ(q) ((q) << 1)
64 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
65 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
66 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
67 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
68 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
69 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
70 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
71 MVNETA_DEF_RXQ_ARP(q) | \
72 MVNETA_DEF_RXQ_TCP(q) | \
73 MVNETA_DEF_RXQ_UDP(q) | \
74 MVNETA_DEF_RXQ_BPDU(q) | \
75 MVNETA_TX_UNSET_ERR_SUM | \
76 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
77 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
78 #define MVNETA_MAC_ADDR_LOW 0x2414
79 #define MVNETA_MAC_ADDR_HIGH 0x2418
80 #define MVNETA_SDMA_CONFIG 0x241c
81 #define MVNETA_SDMA_BRST_SIZE_16 4
82 #define MVNETA_NO_DESC_SWAP 0x0
83 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
84 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
85 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
86 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
87 #define MVNETA_PORT_STATUS 0x2444
88 #define MVNETA_TX_IN_PRGRS BIT(1)
89 #define MVNETA_TX_FIFO_EMPTY BIT(8)
90 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
91 #define MVNETA_SGMII_SERDES_CFG 0x24A0
92 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
93 #define MVNETA_TYPE_PRIO 0x24bc
94 #define MVNETA_FORCE_UNI BIT(21)
95 #define MVNETA_TXQ_CMD_1 0x24e4
96 #define MVNETA_TXQ_CMD 0x2448
97 #define MVNETA_TXQ_DISABLE_SHIFT 8
98 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
99 #define MVNETA_ACC_MODE 0x2500
100 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
101 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
102 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
103 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
104 #define MVNETA_INTR_NEW_CAUSE 0x25a0
105 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
106 #define MVNETA_INTR_NEW_MASK 0x25a4
107 #define MVNETA_INTR_OLD_CAUSE 0x25a8
108 #define MVNETA_INTR_OLD_MASK 0x25ac
109 #define MVNETA_INTR_MISC_CAUSE 0x25b0
110 #define MVNETA_INTR_MISC_MASK 0x25b4
111 #define MVNETA_INTR_ENABLE 0x25b8
112 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
113 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000
114 #define MVNETA_RXQ_CMD 0x2680
115 #define MVNETA_RXQ_DISABLE_SHIFT 8
116 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
117 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
118 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
119 #define MVNETA_GMAC_CTRL_0 0x2c00
120 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
121 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
122 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
123 #define MVNETA_GMAC_CTRL_2 0x2c08
124 #define MVNETA_GMAC2_PSC_ENABLE BIT(3)
125 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
126 #define MVNETA_GMAC2_PORT_RESET BIT(6)
127 #define MVNETA_GMAC_STATUS 0x2c10
128 #define MVNETA_GMAC_LINK_UP BIT(0)
129 #define MVNETA_GMAC_SPEED_1000 BIT(1)
130 #define MVNETA_GMAC_SPEED_100 BIT(2)
131 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
132 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
133 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
134 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
135 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
136 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
137 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
138 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
139 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
140 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
141 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
142 #define MVNETA_MIB_COUNTERS_BASE 0x3080
143 #define MVNETA_MIB_LATE_COLLISION 0x7c
144 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
145 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
146 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
147 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
148 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
149 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
150 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
151 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
152 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
153 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
154 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
155 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
156 #define MVNETA_PORT_TX_RESET 0x3cf0
157 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
158 #define MVNETA_TX_MTU 0x3e0c
159 #define MVNETA_TX_TOKEN_SIZE 0x3e14
160 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
161 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
162 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
164 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
166 /* Descriptor ring Macros */
167 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
168 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
170 /* Various constants */
173 #define MVNETA_TXDONE_COAL_PKTS 16
174 #define MVNETA_RX_COAL_PKTS 32
175 #define MVNETA_RX_COAL_USEC 100
178 #define MVNETA_TX_DONE_TIMER_PERIOD 10
180 /* Napi polling weight */
181 #define MVNETA_RX_POLL_WEIGHT 64
183 /* The two bytes Marvell header. Either contains a special value used
184 * by Marvell switches when a specific hardware mode is enabled (not
185 * supported by this driver) or is filled automatically by zeroes on
186 * the RX side. Those two bytes being at the front of the Ethernet
187 * header, they allow to have the IP header aligned on a 4 bytes
188 * boundary automatically: the hardware skips those two bytes on its
191 #define MVNETA_MH_SIZE 2
193 #define MVNETA_VLAN_TAG_LEN 4
195 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
196 #define MVNETA_TX_CSUM_MAX_SIZE 9800
197 #define MVNETA_ACC_MODE_EXT 1
199 /* Timeout constants */
200 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
201 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
202 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
204 #define MVNETA_TX_MTU_MAX 0x3ffff
206 /* Max number of Rx descriptors */
207 #define MVNETA_MAX_RXD 128
209 /* Max number of Tx descriptors */
210 #define MVNETA_MAX_TXD 532
212 /* descriptor aligned size */
213 #define MVNETA_DESC_ALIGNED_SIZE 32
215 #define MVNETA_RX_PKT_SIZE(mtu) \
216 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
217 ETH_HLEN + ETH_FCS_LEN, \
218 MVNETA_CPU_D_CACHE_LINE_SIZE)
220 #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
222 struct mvneta_stats {
223 struct u64_stats_sync syncp;
231 struct mvneta_rx_queue *rxqs;
232 struct mvneta_tx_queue *txqs;
233 struct timer_list tx_done_timer;
234 struct net_device *dev;
237 struct napi_struct napi;
241 #define MVNETA_F_TX_DONE_TIMER_BIT 0
251 struct mvneta_stats tx_stats;
252 struct mvneta_stats rx_stats;
254 struct mii_bus *mii_bus;
255 struct phy_device *phy_dev;
256 phy_interface_t phy_interface;
257 struct device_node *phy_node;
263 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
264 * layout of the transmit and reception DMA descriptors, and their
265 * layout is therefore defined by the hardware design
267 struct mvneta_tx_desc {
268 u32 command; /* Options used by HW for packet transmitting.*/
269 #define MVNETA_TX_L3_OFF_SHIFT 0
270 #define MVNETA_TX_IP_HLEN_SHIFT 8
271 #define MVNETA_TX_L4_UDP BIT(16)
272 #define MVNETA_TX_L3_IP6 BIT(17)
273 #define MVNETA_TXD_IP_CSUM BIT(18)
274 #define MVNETA_TXD_Z_PAD BIT(19)
275 #define MVNETA_TXD_L_DESC BIT(20)
276 #define MVNETA_TXD_F_DESC BIT(21)
277 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
278 MVNETA_TXD_L_DESC | \
280 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
281 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
283 u16 reserverd1; /* csum_l4 (for future use) */
284 u16 data_size; /* Data size of transmitted packet in bytes */
285 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
286 u32 reserved2; /* hw_cmd - (for future use, PMT) */
287 u32 reserved3[4]; /* Reserved - (for future use) */
290 struct mvneta_rx_desc {
291 u32 status; /* Info about received packet */
292 #define MVNETA_RXD_ERR_CRC 0x0
293 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
294 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
295 #define MVNETA_RXD_ERR_LEN BIT(18)
296 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
297 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
298 #define MVNETA_RXD_L3_IP4 BIT(25)
299 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
300 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
302 u16 reserved1; /* pnc_info - (for future use, PnC) */
303 u16 data_size; /* Size of received packet in bytes */
304 u32 buf_phys_addr; /* Physical address of the buffer */
305 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
306 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
307 u16 reserved3; /* prefetch_cmd, for future use */
308 u16 reserved4; /* csum_l4 - (for future use, PnC) */
309 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
310 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
313 struct mvneta_tx_queue {
314 /* Number of this TX queue, in the range 0-7 */
317 /* Number of TX DMA descriptors in the descriptor ring */
320 /* Number of currently used TX DMA descriptor in the
325 /* Array of transmitted skb */
326 struct sk_buff **tx_skb;
328 /* Index of last TX DMA descriptor that was inserted */
331 /* Index of the TX DMA descriptor to be cleaned up */
336 /* Virtual address of the TX DMA descriptors array */
337 struct mvneta_tx_desc *descs;
339 /* DMA address of the TX DMA descriptors array */
340 dma_addr_t descs_phys;
342 /* Index of the last TX DMA descriptor */
345 /* Index of the next TX DMA descriptor to process */
346 int next_desc_to_proc;
349 struct mvneta_rx_queue {
350 /* rx queue number, in the range 0-7 */
353 /* num of rx descriptors in the rx descriptor ring */
356 /* counter of times when mvneta_refill() failed */
362 /* Virtual address of the RX DMA descriptors array */
363 struct mvneta_rx_desc *descs;
365 /* DMA address of the RX DMA descriptors array */
366 dma_addr_t descs_phys;
368 /* Index of the last RX DMA descriptor */
371 /* Index of the next RX DMA descriptor to process */
372 int next_desc_to_proc;
375 static int rxq_number = 8;
376 static int txq_number = 8;
380 #define MVNETA_DRIVER_NAME "mvneta"
381 #define MVNETA_DRIVER_VERSION "1.0"
383 /* Utility/helper methods */
385 /* Write helper method */
386 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
388 writel(data, pp->base + offset);
391 /* Read helper method */
392 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
394 return readl(pp->base + offset);
397 /* Increment txq get counter */
398 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
400 txq->txq_get_index++;
401 if (txq->txq_get_index == txq->size)
402 txq->txq_get_index = 0;
405 /* Increment txq put counter */
406 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
408 txq->txq_put_index++;
409 if (txq->txq_put_index == txq->size)
410 txq->txq_put_index = 0;
414 /* Clear all MIB counters */
415 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
420 /* Perform dummy reads from MIB counters */
421 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
422 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
425 /* Get System Network Statistics */
426 struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev,
427 struct rtnl_link_stats64 *stats)
429 struct mvneta_port *pp = netdev_priv(dev);
432 memset(stats, 0, sizeof(struct rtnl_link_stats64));
435 start = u64_stats_fetch_begin_bh(&pp->rx_stats.syncp);
436 stats->rx_packets = pp->rx_stats.packets;
437 stats->rx_bytes = pp->rx_stats.bytes;
438 } while (u64_stats_fetch_retry_bh(&pp->rx_stats.syncp, start));
442 start = u64_stats_fetch_begin_bh(&pp->tx_stats.syncp);
443 stats->tx_packets = pp->tx_stats.packets;
444 stats->tx_bytes = pp->tx_stats.bytes;
445 } while (u64_stats_fetch_retry_bh(&pp->tx_stats.syncp, start));
447 stats->rx_errors = dev->stats.rx_errors;
448 stats->rx_dropped = dev->stats.rx_dropped;
450 stats->tx_dropped = dev->stats.tx_dropped;
455 /* Rx descriptors helper methods */
457 /* Checks whether the given RX descriptor is both the first and the
458 * last descriptor for the RX packet. Each RX packet is currently
459 * received through a single RX descriptor, so not having each RX
460 * descriptor with its first and last bits set is an error
462 static int mvneta_rxq_desc_is_first_last(struct mvneta_rx_desc *desc)
464 return (desc->status & MVNETA_RXD_FIRST_LAST_DESC) ==
465 MVNETA_RXD_FIRST_LAST_DESC;
468 /* Add number of descriptors ready to receive new packets */
469 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
470 struct mvneta_rx_queue *rxq,
473 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
476 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
477 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
478 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
479 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
480 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
483 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
484 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
487 /* Get number of RX descriptors occupied by received packets */
488 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
489 struct mvneta_rx_queue *rxq)
493 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
494 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
497 /* Update num of rx desc called upon return from rx path or
498 * from mvneta_rxq_drop_pkts().
500 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
501 struct mvneta_rx_queue *rxq,
502 int rx_done, int rx_filled)
506 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
508 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
509 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
513 /* Only 255 descriptors can be added at once */
514 while ((rx_done > 0) || (rx_filled > 0)) {
515 if (rx_done <= 0xff) {
522 if (rx_filled <= 0xff) {
523 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
526 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
529 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
533 /* Get pointer to next RX descriptor to be processed by SW */
534 static struct mvneta_rx_desc *
535 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
537 int rx_desc = rxq->next_desc_to_proc;
539 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
540 return rxq->descs + rx_desc;
543 /* Change maximum receive size of the port. */
544 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
548 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
549 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
550 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
551 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
552 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
556 /* Set rx queue offset */
557 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
558 struct mvneta_rx_queue *rxq,
563 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
564 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
567 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
568 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
572 /* Tx descriptors helper methods */
574 /* Update HW with number of TX descriptors to be sent */
575 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
576 struct mvneta_tx_queue *txq,
581 /* Only 255 descriptors can be added at once ; Assume caller
582 * process TX desriptors in quanta less than 256
585 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
588 /* Get pointer to next TX descriptor to be processed (send) by HW */
589 static struct mvneta_tx_desc *
590 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
592 int tx_desc = txq->next_desc_to_proc;
594 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
595 return txq->descs + tx_desc;
598 /* Release the last allocated TX descriptor. Useful to handle DMA
599 * mapping failures in the TX path.
601 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
603 if (txq->next_desc_to_proc == 0)
604 txq->next_desc_to_proc = txq->last_desc - 1;
606 txq->next_desc_to_proc--;
609 /* Set rxq buf size */
610 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
611 struct mvneta_rx_queue *rxq,
616 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
618 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
619 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
621 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
624 /* Disable buffer management (BM) */
625 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
626 struct mvneta_rx_queue *rxq)
630 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
631 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
632 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
637 /* Sets the RGMII Enable bit (RGMIIEn) in port MAC control register */
638 static void mvneta_gmac_rgmii_set(struct mvneta_port *pp, int enable)
642 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
645 val |= MVNETA_GMAC2_PORT_RGMII;
647 val &= ~MVNETA_GMAC2_PORT_RGMII;
649 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
652 /* Config SGMII port */
653 static void mvneta_port_sgmii_config(struct mvneta_port *pp)
657 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
658 val |= MVNETA_GMAC2_PSC_ENABLE;
659 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
661 mvreg_write(pp, MVNETA_SGMII_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
664 /* Start the Ethernet port RX and TX activity */
665 static void mvneta_port_up(struct mvneta_port *pp)
670 /* Enable all initialized TXs. */
671 mvneta_mib_counters_clear(pp);
673 for (queue = 0; queue < txq_number; queue++) {
674 struct mvneta_tx_queue *txq = &pp->txqs[queue];
675 if (txq->descs != NULL)
676 q_map |= (1 << queue);
678 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
680 /* Enable all initialized RXQs. */
682 for (queue = 0; queue < rxq_number; queue++) {
683 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
684 if (rxq->descs != NULL)
685 q_map |= (1 << queue);
688 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
691 /* Stop the Ethernet port activity */
692 static void mvneta_port_down(struct mvneta_port *pp)
697 /* Stop Rx port activity. Check port Rx activity. */
698 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
700 /* Issue stop command for active channels only */
702 mvreg_write(pp, MVNETA_RXQ_CMD,
703 val << MVNETA_RXQ_DISABLE_SHIFT);
705 /* Wait for all Rx activity to terminate. */
708 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
710 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
716 val = mvreg_read(pp, MVNETA_RXQ_CMD);
717 } while (val & 0xff);
719 /* Stop Tx port activity. Check port Tx activity. Issue stop
720 * command for active channels only
722 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
725 mvreg_write(pp, MVNETA_TXQ_CMD,
726 (val << MVNETA_TXQ_DISABLE_SHIFT));
728 /* Wait for all Tx activity to terminate. */
731 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
733 "TIMEOUT for TX stopped status=0x%08x\n",
739 /* Check TX Command reg that all Txqs are stopped */
740 val = mvreg_read(pp, MVNETA_TXQ_CMD);
742 } while (val & 0xff);
744 /* Double check to verify that TX FIFO is empty */
747 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
749 "TX FIFO empty timeout status=0x08%x\n",
755 val = mvreg_read(pp, MVNETA_PORT_STATUS);
756 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
757 (val & MVNETA_TX_IN_PRGRS));
762 /* Enable the port by setting the port enable bit of the MAC control register */
763 static void mvneta_port_enable(struct mvneta_port *pp)
768 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
769 val |= MVNETA_GMAC0_PORT_ENABLE;
770 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
773 /* Disable the port and wait for about 200 usec before retuning */
774 static void mvneta_port_disable(struct mvneta_port *pp)
778 /* Reset the Enable bit in the Serial Control Register */
779 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
780 val &= ~MVNETA_GMAC0_PORT_ENABLE;
781 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
786 /* Multicast tables methods */
788 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
789 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
797 val = 0x1 | (queue << 1);
798 val |= (val << 24) | (val << 16) | (val << 8);
801 for (offset = 0; offset <= 0xc; offset += 4)
802 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
805 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
806 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
814 val = 0x1 | (queue << 1);
815 val |= (val << 24) | (val << 16) | (val << 8);
818 for (offset = 0; offset <= 0xfc; offset += 4)
819 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
823 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
824 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
830 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
833 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
834 val = 0x1 | (queue << 1);
835 val |= (val << 24) | (val << 16) | (val << 8);
838 for (offset = 0; offset <= 0xfc; offset += 4)
839 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
842 /* This method sets defaults to the NETA port:
843 * Clears interrupt Cause and Mask registers.
844 * Clears all MAC tables.
845 * Sets defaults to all registers.
846 * Resets RX and TX descriptor rings.
848 * This method can be called after mvneta_port_down() to return the port
849 * settings to defaults.
851 static void mvneta_defaults_set(struct mvneta_port *pp)
857 /* Clear all Cause registers */
858 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
859 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
860 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
862 /* Mask all interrupts */
863 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
864 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
865 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
866 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
868 /* Enable MBUS Retry bit16 */
869 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
871 /* Set CPU queue access map - all CPUs have access to all RX
872 * queues and to all TX queues
874 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
875 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
876 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
877 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
879 /* Reset RX and TX DMAs */
880 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
881 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
883 /* Disable Legacy WRR, Disable EJP, Release from reset */
884 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
885 for (queue = 0; queue < txq_number; queue++) {
886 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
887 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
890 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
891 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
893 /* Set Port Acceleration Mode */
894 val = MVNETA_ACC_MODE_EXT;
895 mvreg_write(pp, MVNETA_ACC_MODE, val);
897 /* Update val of portCfg register accordingly with all RxQueue types */
898 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
899 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
902 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
903 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
905 /* Build PORT_SDMA_CONFIG_REG */
908 /* Default burst size */
909 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
910 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
912 val |= (MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP |
913 MVNETA_NO_DESC_SWAP);
915 /* Assign port SDMA configuration */
916 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
918 mvneta_set_ucast_table(pp, -1);
919 mvneta_set_special_mcast_table(pp, -1);
920 mvneta_set_other_mcast_table(pp, -1);
922 /* Set port interrupt enable register - default enable all */
923 mvreg_write(pp, MVNETA_INTR_ENABLE,
924 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
925 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
928 /* Set max sizes for tx queues */
929 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
935 mtu = max_tx_size * 8;
936 if (mtu > MVNETA_TX_MTU_MAX)
937 mtu = MVNETA_TX_MTU_MAX;
940 val = mvreg_read(pp, MVNETA_TX_MTU);
941 val &= ~MVNETA_TX_MTU_MAX;
943 mvreg_write(pp, MVNETA_TX_MTU, val);
945 /* TX token size and all TXQs token size must be larger that MTU */
946 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
948 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
951 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
953 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
955 for (queue = 0; queue < txq_number; queue++) {
956 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
958 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
961 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
963 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
968 /* Set unicast address */
969 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
972 unsigned int unicast_reg;
973 unsigned int tbl_offset;
974 unsigned int reg_offset;
976 /* Locate the Unicast table entry */
977 last_nibble = (0xf & last_nibble);
979 /* offset from unicast tbl base */
980 tbl_offset = (last_nibble / 4) * 4;
982 /* offset within the above reg */
983 reg_offset = last_nibble % 4;
985 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
988 /* Clear accepts frame bit at specified unicast DA tbl entry */
989 unicast_reg &= ~(0xff << (8 * reg_offset));
991 unicast_reg &= ~(0xff << (8 * reg_offset));
992 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
995 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
998 /* Set mac address */
999 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1006 mac_l = (addr[4] << 8) | (addr[5]);
1007 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1008 (addr[2] << 8) | (addr[3] << 0);
1010 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1011 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1014 /* Accept frames of this address */
1015 mvneta_set_ucast_addr(pp, addr[5], queue);
1018 /* Set the number of packets that will be received before RX interrupt
1019 * will be generated by HW.
1021 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1022 struct mvneta_rx_queue *rxq, u32 value)
1024 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1025 value | MVNETA_RXQ_NON_OCCUPIED(0));
1026 rxq->pkts_coal = value;
1029 /* Set the time delay in usec before RX interrupt will be generated by
1032 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1033 struct mvneta_rx_queue *rxq, u32 value)
1036 unsigned long clk_rate;
1038 clk_rate = clk_get_rate(pp->clk);
1039 val = (clk_rate / 1000000) * value;
1041 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1042 rxq->time_coal = value;
1045 /* Set threshold for TX_DONE pkts coalescing */
1046 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1047 struct mvneta_tx_queue *txq, u32 value)
1051 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1053 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1054 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1056 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1058 txq->done_pkts_coal = value;
1061 /* Trigger tx done timer in MVNETA_TX_DONE_TIMER_PERIOD msecs */
1062 static void mvneta_add_tx_done_timer(struct mvneta_port *pp)
1064 if (test_and_set_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags) == 0) {
1065 pp->tx_done_timer.expires = jiffies +
1066 msecs_to_jiffies(MVNETA_TX_DONE_TIMER_PERIOD);
1067 add_timer(&pp->tx_done_timer);
1072 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1073 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1074 u32 phys_addr, u32 cookie)
1076 rx_desc->buf_cookie = cookie;
1077 rx_desc->buf_phys_addr = phys_addr;
1080 /* Decrement sent descriptors counter */
1081 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1082 struct mvneta_tx_queue *txq,
1087 /* Only 255 TX descriptors can be updated at once */
1088 while (sent_desc > 0xff) {
1089 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1090 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1091 sent_desc = sent_desc - 0xff;
1094 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1095 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1098 /* Get number of TX descriptors already sent by HW */
1099 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1100 struct mvneta_tx_queue *txq)
1105 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1106 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1107 MVNETA_TXQ_SENT_DESC_SHIFT;
1112 /* Get number of sent descriptors and decrement counter.
1113 * The number of sent descriptors is returned.
1115 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1116 struct mvneta_tx_queue *txq)
1120 /* Get number of sent descriptors */
1121 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1123 /* Decrement sent descriptors counter */
1125 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1130 /* Set TXQ descriptors fields relevant for CSUM calculation */
1131 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1132 int ip_hdr_len, int l4_proto)
1136 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1137 * G_L4_chk, L4_type; required only for checksum
1140 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1141 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1143 if (l3_proto == swab16(ETH_P_IP))
1144 command |= MVNETA_TXD_IP_CSUM;
1146 command |= MVNETA_TX_L3_IP6;
1148 if (l4_proto == IPPROTO_TCP)
1149 command |= MVNETA_TX_L4_CSUM_FULL;
1150 else if (l4_proto == IPPROTO_UDP)
1151 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1153 command |= MVNETA_TX_L4_CSUM_NOT;
1159 /* Display more error info */
1160 static void mvneta_rx_error(struct mvneta_port *pp,
1161 struct mvneta_rx_desc *rx_desc)
1163 u32 status = rx_desc->status;
1165 if (!mvneta_rxq_desc_is_first_last(rx_desc)) {
1167 "bad rx status %08x (buffer oversize), size=%d\n",
1168 rx_desc->status, rx_desc->data_size);
1172 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1173 case MVNETA_RXD_ERR_CRC:
1174 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1175 status, rx_desc->data_size);
1177 case MVNETA_RXD_ERR_OVERRUN:
1178 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1179 status, rx_desc->data_size);
1181 case MVNETA_RXD_ERR_LEN:
1182 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1183 status, rx_desc->data_size);
1185 case MVNETA_RXD_ERR_RESOURCE:
1186 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1187 status, rx_desc->data_size);
1192 /* Handle RX checksum offload */
1193 static void mvneta_rx_csum(struct mvneta_port *pp,
1194 struct mvneta_rx_desc *rx_desc,
1195 struct sk_buff *skb)
1197 if ((rx_desc->status & MVNETA_RXD_L3_IP4) &&
1198 (rx_desc->status & MVNETA_RXD_L4_CSUM_OK)) {
1200 skb->ip_summed = CHECKSUM_UNNECESSARY;
1204 skb->ip_summed = CHECKSUM_NONE;
1207 /* Return tx queue pointer (find last set bit) according to causeTxDone reg */
1208 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1211 int queue = fls(cause) - 1;
1213 return (queue < 0 || queue >= txq_number) ? NULL : &pp->txqs[queue];
1216 /* Free tx queue skbuffs */
1217 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1218 struct mvneta_tx_queue *txq, int num)
1222 for (i = 0; i < num; i++) {
1223 struct mvneta_tx_desc *tx_desc = txq->descs +
1225 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1227 mvneta_txq_inc_get(txq);
1232 dma_unmap_single(pp->dev->dev.parent, tx_desc->buf_phys_addr,
1233 tx_desc->data_size, DMA_TO_DEVICE);
1234 dev_kfree_skb_any(skb);
1238 /* Handle end of transmission */
1239 static int mvneta_txq_done(struct mvneta_port *pp,
1240 struct mvneta_tx_queue *txq)
1242 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1245 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1248 mvneta_txq_bufs_free(pp, txq, tx_done);
1250 txq->count -= tx_done;
1252 if (netif_tx_queue_stopped(nq)) {
1253 if (txq->size - txq->count >= MAX_SKB_FRAGS + 1)
1254 netif_tx_wake_queue(nq);
1260 /* Refill processing */
1261 static int mvneta_rx_refill(struct mvneta_port *pp,
1262 struct mvneta_rx_desc *rx_desc)
1265 dma_addr_t phys_addr;
1266 struct sk_buff *skb;
1268 skb = netdev_alloc_skb(pp->dev, pp->pkt_size);
1272 phys_addr = dma_map_single(pp->dev->dev.parent, skb->head,
1273 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1275 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1280 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)skb);
1285 /* Handle tx checksum */
1286 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1288 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1292 if (skb->protocol == htons(ETH_P_IP)) {
1293 struct iphdr *ip4h = ip_hdr(skb);
1295 /* Calculate IPv4 checksum and L4 checksum */
1296 ip_hdr_len = ip4h->ihl;
1297 l4_proto = ip4h->protocol;
1298 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1299 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1301 /* Read l4_protocol from one of IPv6 extra headers */
1302 if (skb_network_header_len(skb) > 0)
1303 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1304 l4_proto = ip6h->nexthdr;
1306 return MVNETA_TX_L4_CSUM_NOT;
1308 return mvneta_txq_desc_csum(skb_network_offset(skb),
1309 skb->protocol, ip_hdr_len, l4_proto);
1312 return MVNETA_TX_L4_CSUM_NOT;
1315 /* Returns rx queue pointer (find last set bit) according to causeRxTx
1318 static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp,
1321 int queue = fls(cause >> 8) - 1;
1323 return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue];
1326 /* Drop packets received by the RXQ and free buffers */
1327 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1328 struct mvneta_rx_queue *rxq)
1332 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1333 for (i = 0; i < rxq->size; i++) {
1334 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1335 struct sk_buff *skb = (struct sk_buff *)rx_desc->buf_cookie;
1337 dev_kfree_skb_any(skb);
1338 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1339 rx_desc->data_size, DMA_FROM_DEVICE);
1343 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1346 /* Main rx processing */
1347 static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
1348 struct mvneta_rx_queue *rxq)
1350 struct net_device *dev = pp->dev;
1351 int rx_done, rx_filled;
1353 /* Get number of received packets */
1354 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1356 if (rx_todo > rx_done)
1362 /* Fairness NAPI loop */
1363 while (rx_done < rx_todo) {
1364 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1365 struct sk_buff *skb;
1372 rx_status = rx_desc->status;
1373 skb = (struct sk_buff *)rx_desc->buf_cookie;
1375 if (!mvneta_rxq_desc_is_first_last(rx_desc) ||
1376 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1377 dev->stats.rx_errors++;
1378 mvneta_rx_error(pp, rx_desc);
1379 mvneta_rx_desc_fill(rx_desc, rx_desc->buf_phys_addr,
1384 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1385 rx_desc->data_size, DMA_FROM_DEVICE);
1387 rx_bytes = rx_desc->data_size -
1388 (ETH_FCS_LEN + MVNETA_MH_SIZE);
1389 u64_stats_update_begin(&pp->rx_stats.syncp);
1390 pp->rx_stats.packets++;
1391 pp->rx_stats.bytes += rx_bytes;
1392 u64_stats_update_end(&pp->rx_stats.syncp);
1394 /* Linux processing */
1395 skb_reserve(skb, MVNETA_MH_SIZE);
1396 skb_put(skb, rx_bytes);
1398 skb->protocol = eth_type_trans(skb, dev);
1400 mvneta_rx_csum(pp, rx_desc, skb);
1402 napi_gro_receive(&pp->napi, skb);
1404 /* Refill processing */
1405 err = mvneta_rx_refill(pp, rx_desc);
1407 netdev_err(pp->dev, "Linux processing - Can't refill\n");
1413 /* Update rxq management counters */
1414 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_filled);
1419 /* Handle tx fragmentation processing */
1420 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
1421 struct mvneta_tx_queue *txq)
1423 struct mvneta_tx_desc *tx_desc;
1426 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1427 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1428 void *addr = page_address(frag->page.p) + frag->page_offset;
1430 tx_desc = mvneta_txq_next_desc_get(txq);
1431 tx_desc->data_size = frag->size;
1433 tx_desc->buf_phys_addr =
1434 dma_map_single(pp->dev->dev.parent, addr,
1435 tx_desc->data_size, DMA_TO_DEVICE);
1437 if (dma_mapping_error(pp->dev->dev.parent,
1438 tx_desc->buf_phys_addr)) {
1439 mvneta_txq_desc_put(txq);
1443 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
1444 /* Last descriptor */
1445 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
1447 txq->tx_skb[txq->txq_put_index] = skb;
1449 mvneta_txq_inc_put(txq);
1451 /* Descriptor in the middle: Not First, Not Last */
1452 tx_desc->command = 0;
1454 txq->tx_skb[txq->txq_put_index] = NULL;
1455 mvneta_txq_inc_put(txq);
1462 /* Release all descriptors that were used to map fragments of
1463 * this packet, as well as the corresponding DMA mappings
1465 for (i = i - 1; i >= 0; i--) {
1466 tx_desc = txq->descs + i;
1467 dma_unmap_single(pp->dev->dev.parent,
1468 tx_desc->buf_phys_addr,
1471 mvneta_txq_desc_put(txq);
1477 /* Main tx processing */
1478 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
1480 struct mvneta_port *pp = netdev_priv(dev);
1481 u16 txq_id = skb_get_queue_mapping(skb);
1482 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
1483 struct mvneta_tx_desc *tx_desc;
1484 struct netdev_queue *nq;
1488 if (!netif_running(dev))
1491 frags = skb_shinfo(skb)->nr_frags + 1;
1492 nq = netdev_get_tx_queue(dev, txq_id);
1494 /* Get a descriptor for the first part of the packet */
1495 tx_desc = mvneta_txq_next_desc_get(txq);
1497 tx_cmd = mvneta_skb_tx_csum(pp, skb);
1499 tx_desc->data_size = skb_headlen(skb);
1501 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
1504 if (unlikely(dma_mapping_error(dev->dev.parent,
1505 tx_desc->buf_phys_addr))) {
1506 mvneta_txq_desc_put(txq);
1512 /* First and Last descriptor */
1513 tx_cmd |= MVNETA_TXD_FLZ_DESC;
1514 tx_desc->command = tx_cmd;
1515 txq->tx_skb[txq->txq_put_index] = skb;
1516 mvneta_txq_inc_put(txq);
1518 /* First but not Last */
1519 tx_cmd |= MVNETA_TXD_F_DESC;
1520 txq->tx_skb[txq->txq_put_index] = NULL;
1521 mvneta_txq_inc_put(txq);
1522 tx_desc->command = tx_cmd;
1523 /* Continue with other skb fragments */
1524 if (mvneta_tx_frag_process(pp, skb, txq)) {
1525 dma_unmap_single(dev->dev.parent,
1526 tx_desc->buf_phys_addr,
1529 mvneta_txq_desc_put(txq);
1535 txq->count += frags;
1536 mvneta_txq_pend_desc_add(pp, txq, frags);
1538 if (txq->size - txq->count < MAX_SKB_FRAGS + 1)
1539 netif_tx_stop_queue(nq);
1543 u64_stats_update_begin(&pp->tx_stats.syncp);
1544 pp->tx_stats.packets++;
1545 pp->tx_stats.bytes += skb->len;
1546 u64_stats_update_end(&pp->tx_stats.syncp);
1549 dev->stats.tx_dropped++;
1550 dev_kfree_skb_any(skb);
1553 if (txq->count >= MVNETA_TXDONE_COAL_PKTS)
1554 mvneta_txq_done(pp, txq);
1556 /* If after calling mvneta_txq_done, count equals
1557 * frags, we need to set the timer
1559 if (txq->count == frags && frags > 0)
1560 mvneta_add_tx_done_timer(pp);
1562 return NETDEV_TX_OK;
1566 /* Free tx resources, when resetting a port */
1567 static void mvneta_txq_done_force(struct mvneta_port *pp,
1568 struct mvneta_tx_queue *txq)
1571 int tx_done = txq->count;
1573 mvneta_txq_bufs_free(pp, txq, tx_done);
1577 txq->txq_put_index = 0;
1578 txq->txq_get_index = 0;
1581 /* handle tx done - called from tx done timer callback */
1582 static u32 mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done,
1585 struct mvneta_tx_queue *txq;
1587 struct netdev_queue *nq;
1590 while (cause_tx_done != 0) {
1591 txq = mvneta_tx_done_policy(pp, cause_tx_done);
1595 nq = netdev_get_tx_queue(pp->dev, txq->id);
1596 __netif_tx_lock(nq, smp_processor_id());
1599 tx_done += mvneta_txq_done(pp, txq);
1600 *tx_todo += txq->count;
1603 __netif_tx_unlock(nq);
1604 cause_tx_done &= ~((1 << txq->id));
1610 /* Compute crc8 of the specified address, using a unique algorithm ,
1611 * according to hw spec, different than generic crc8 algorithm
1613 static int mvneta_addr_crc(unsigned char *addr)
1618 for (i = 0; i < ETH_ALEN; i++) {
1621 crc = (crc ^ addr[i]) << 8;
1622 for (j = 7; j >= 0; j--) {
1623 if (crc & (0x100 << j))
1631 /* This method controls the net device special MAC multicast support.
1632 * The Special Multicast Table for MAC addresses supports MAC of the form
1633 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1634 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1635 * Table entries in the DA-Filter table. This method set the Special
1636 * Multicast Table appropriate entry.
1638 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
1639 unsigned char last_byte,
1642 unsigned int smc_table_reg;
1643 unsigned int tbl_offset;
1644 unsigned int reg_offset;
1646 /* Register offset from SMC table base */
1647 tbl_offset = (last_byte / 4);
1648 /* Entry offset within the above reg */
1649 reg_offset = last_byte % 4;
1651 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
1655 smc_table_reg &= ~(0xff << (8 * reg_offset));
1657 smc_table_reg &= ~(0xff << (8 * reg_offset));
1658 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1661 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
1665 /* This method controls the network device Other MAC multicast support.
1666 * The Other Multicast Table is used for multicast of another type.
1667 * A CRC-8 is used as an index to the Other Multicast Table entries
1668 * in the DA-Filter table.
1669 * The method gets the CRC-8 value from the calling routine and
1670 * sets the Other Multicast Table appropriate entry according to the
1673 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
1677 unsigned int omc_table_reg;
1678 unsigned int tbl_offset;
1679 unsigned int reg_offset;
1681 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1682 reg_offset = crc8 % 4; /* Entry offset within the above reg */
1684 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
1687 /* Clear accepts frame bit at specified Other DA table entry */
1688 omc_table_reg &= ~(0xff << (8 * reg_offset));
1690 omc_table_reg &= ~(0xff << (8 * reg_offset));
1691 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1694 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
1697 /* The network device supports multicast using two tables:
1698 * 1) Special Multicast Table for MAC addresses of the form
1699 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1700 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1701 * Table entries in the DA-Filter table.
1702 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
1703 * is used as an index to the Other Multicast Table entries in the
1706 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
1709 unsigned char crc_result = 0;
1711 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
1712 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
1716 crc_result = mvneta_addr_crc(p_addr);
1718 if (pp->mcast_count[crc_result] == 0) {
1719 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
1724 pp->mcast_count[crc_result]--;
1725 if (pp->mcast_count[crc_result] != 0) {
1726 netdev_info(pp->dev,
1727 "After delete there are %d valid Mcast for crc8=0x%02x\n",
1728 pp->mcast_count[crc_result], crc_result);
1732 pp->mcast_count[crc_result]++;
1734 mvneta_set_other_mcast_addr(pp, crc_result, queue);
1739 /* Configure Fitering mode of Ethernet port */
1740 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
1743 u32 port_cfg_reg, val;
1745 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
1747 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
1749 /* Set / Clear UPM bit in port configuration register */
1751 /* Accept all Unicast addresses */
1752 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
1753 val |= MVNETA_FORCE_UNI;
1754 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
1755 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
1757 /* Reject all Unicast addresses */
1758 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
1759 val &= ~MVNETA_FORCE_UNI;
1762 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
1763 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
1766 /* register unicast and multicast addresses */
1767 static void mvneta_set_rx_mode(struct net_device *dev)
1769 struct mvneta_port *pp = netdev_priv(dev);
1770 struct netdev_hw_addr *ha;
1772 if (dev->flags & IFF_PROMISC) {
1773 /* Accept all: Multicast + Unicast */
1774 mvneta_rx_unicast_promisc_set(pp, 1);
1775 mvneta_set_ucast_table(pp, rxq_def);
1776 mvneta_set_special_mcast_table(pp, rxq_def);
1777 mvneta_set_other_mcast_table(pp, rxq_def);
1779 /* Accept single Unicast */
1780 mvneta_rx_unicast_promisc_set(pp, 0);
1781 mvneta_set_ucast_table(pp, -1);
1782 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
1784 if (dev->flags & IFF_ALLMULTI) {
1785 /* Accept all multicast */
1786 mvneta_set_special_mcast_table(pp, rxq_def);
1787 mvneta_set_other_mcast_table(pp, rxq_def);
1789 /* Accept only initialized multicast */
1790 mvneta_set_special_mcast_table(pp, -1);
1791 mvneta_set_other_mcast_table(pp, -1);
1793 if (!netdev_mc_empty(dev)) {
1794 netdev_for_each_mc_addr(ha, dev) {
1795 mvneta_mcast_addr_set(pp, ha->addr,
1803 /* Interrupt handling - the callback for request_irq() */
1804 static irqreturn_t mvneta_isr(int irq, void *dev_id)
1806 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
1808 /* Mask all interrupts */
1809 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1811 napi_schedule(&pp->napi);
1817 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
1818 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
1819 * Bits 8 -15 of the cause Rx Tx register indicate that are received
1820 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
1821 * Each CPU has its own causeRxTx register
1823 static int mvneta_poll(struct napi_struct *napi, int budget)
1827 unsigned long flags;
1828 struct mvneta_port *pp = netdev_priv(napi->dev);
1830 if (!netif_running(pp->dev)) {
1831 napi_complete(napi);
1835 /* Read cause register */
1836 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE) &
1837 MVNETA_RX_INTR_MASK(rxq_number);
1839 /* For the case where the last mvneta_poll did not process all
1842 cause_rx_tx |= pp->cause_rx_tx;
1843 if (rxq_number > 1) {
1844 while ((cause_rx_tx != 0) && (budget > 0)) {
1846 struct mvneta_rx_queue *rxq;
1847 /* get rx queue number from cause_rx_tx */
1848 rxq = mvneta_rx_policy(pp, cause_rx_tx);
1852 /* process the packet in that rx queue */
1853 count = mvneta_rx(pp, budget, rxq);
1857 /* set off the rx bit of the
1858 * corresponding bit in the cause rx
1859 * tx register, so that next iteration
1860 * will find the next rx queue where
1861 * packets are received on
1863 cause_rx_tx &= ~((1 << rxq->id) << 8);
1867 rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]);
1873 napi_complete(napi);
1874 local_irq_save(flags);
1875 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1876 MVNETA_RX_INTR_MASK(rxq_number));
1877 local_irq_restore(flags);
1880 pp->cause_rx_tx = cause_rx_tx;
1884 /* tx done timer callback */
1885 static void mvneta_tx_done_timer_callback(unsigned long data)
1887 struct net_device *dev = (struct net_device *)data;
1888 struct mvneta_port *pp = netdev_priv(dev);
1889 int tx_done = 0, tx_todo = 0;
1891 if (!netif_running(dev))
1894 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
1896 tx_done = mvneta_tx_done_gbe(pp,
1897 (((1 << txq_number) - 1) &
1898 MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK),
1901 mvneta_add_tx_done_timer(pp);
1904 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
1905 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
1908 struct net_device *dev = pp->dev;
1911 for (i = 0; i < num; i++) {
1912 struct sk_buff *skb;
1913 struct mvneta_rx_desc *rx_desc;
1914 unsigned long phys_addr;
1916 skb = dev_alloc_skb(pp->pkt_size);
1918 netdev_err(dev, "%s:rxq %d, %d of %d buffs filled\n",
1919 __func__, rxq->id, i, num);
1923 rx_desc = rxq->descs + i;
1924 memset(rx_desc, 0, sizeof(struct mvneta_rx_desc));
1925 phys_addr = dma_map_single(dev->dev.parent, skb->head,
1926 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1928 if (unlikely(dma_mapping_error(dev->dev.parent, phys_addr))) {
1933 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)skb);
1936 /* Add this number of RX descriptors as non occupied (ready to
1939 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
1944 /* Free all packets pending transmit from all TXQs and reset TX port */
1945 static void mvneta_tx_reset(struct mvneta_port *pp)
1949 /* free the skb's in the hal tx ring */
1950 for (queue = 0; queue < txq_number; queue++)
1951 mvneta_txq_done_force(pp, &pp->txqs[queue]);
1953 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1954 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1957 static void mvneta_rx_reset(struct mvneta_port *pp)
1959 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1960 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1963 /* Rx/Tx queue initialization/cleanup methods */
1965 /* Create a specified RX queue */
1966 static int mvneta_rxq_init(struct mvneta_port *pp,
1967 struct mvneta_rx_queue *rxq)
1970 rxq->size = pp->rx_ring_size;
1972 /* Allocate memory for RX descriptors */
1973 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
1974 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
1975 &rxq->descs_phys, GFP_KERNEL);
1976 if (rxq->descs == NULL)
1979 BUG_ON(rxq->descs !=
1980 PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
1982 rxq->last_desc = rxq->size - 1;
1984 /* Set Rx descriptors queue starting address */
1985 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
1986 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
1989 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
1991 /* Set coalescing pkts and time */
1992 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
1993 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
1995 /* Fill RXQ with buffers from RX pool */
1996 mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
1997 mvneta_rxq_bm_disable(pp, rxq);
1998 mvneta_rxq_fill(pp, rxq, rxq->size);
2003 /* Cleanup Rx queue */
2004 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2005 struct mvneta_rx_queue *rxq)
2007 mvneta_rxq_drop_pkts(pp, rxq);
2010 dma_free_coherent(pp->dev->dev.parent,
2011 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2017 rxq->next_desc_to_proc = 0;
2018 rxq->descs_phys = 0;
2021 /* Create and initialize a tx queue */
2022 static int mvneta_txq_init(struct mvneta_port *pp,
2023 struct mvneta_tx_queue *txq)
2025 txq->size = pp->tx_ring_size;
2027 /* Allocate memory for TX descriptors */
2028 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2029 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2030 &txq->descs_phys, GFP_KERNEL);
2031 if (txq->descs == NULL)
2034 /* Make sure descriptor address is cache line size aligned */
2035 BUG_ON(txq->descs !=
2036 PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2038 txq->last_desc = txq->size - 1;
2040 /* Set maximum bandwidth for enabled TXQs */
2041 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2042 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2044 /* Set Tx descriptors queue starting address */
2045 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2046 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2048 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2049 if (txq->tx_skb == NULL) {
2050 dma_free_coherent(pp->dev->dev.parent,
2051 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2052 txq->descs, txq->descs_phys);
2055 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2060 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2061 static void mvneta_txq_deinit(struct mvneta_port *pp,
2062 struct mvneta_tx_queue *txq)
2067 dma_free_coherent(pp->dev->dev.parent,
2068 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2069 txq->descs, txq->descs_phys);
2073 txq->next_desc_to_proc = 0;
2074 txq->descs_phys = 0;
2076 /* Set minimum bandwidth for disabled TXQs */
2077 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2078 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2080 /* Set Tx descriptors queue starting address and size */
2081 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2082 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2085 /* Cleanup all Tx queues */
2086 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2090 for (queue = 0; queue < txq_number; queue++)
2091 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2094 /* Cleanup all Rx queues */
2095 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2099 for (queue = 0; queue < rxq_number; queue++)
2100 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2104 /* Init all Rx queues */
2105 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2109 for (queue = 0; queue < rxq_number; queue++) {
2110 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
2112 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2114 mvneta_cleanup_rxqs(pp);
2122 /* Init all tx queues */
2123 static int mvneta_setup_txqs(struct mvneta_port *pp)
2127 for (queue = 0; queue < txq_number; queue++) {
2128 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2130 netdev_err(pp->dev, "%s: can't create txq=%d\n",
2132 mvneta_cleanup_txqs(pp);
2140 static void mvneta_start_dev(struct mvneta_port *pp)
2142 mvneta_max_rx_size_set(pp, pp->pkt_size);
2143 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2145 /* start the Rx/Tx activity */
2146 mvneta_port_enable(pp);
2148 /* Enable polling on the port */
2149 napi_enable(&pp->napi);
2151 /* Unmask interrupts */
2152 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2153 MVNETA_RX_INTR_MASK(rxq_number));
2155 phy_start(pp->phy_dev);
2156 netif_tx_start_all_queues(pp->dev);
2159 static void mvneta_stop_dev(struct mvneta_port *pp)
2161 phy_stop(pp->phy_dev);
2163 napi_disable(&pp->napi);
2165 netif_carrier_off(pp->dev);
2167 mvneta_port_down(pp);
2168 netif_tx_stop_all_queues(pp->dev);
2170 /* Stop the port activity */
2171 mvneta_port_disable(pp);
2173 /* Clear all ethernet port interrupts */
2174 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2175 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
2177 /* Mask all ethernet port interrupts */
2178 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2179 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2180 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2182 mvneta_tx_reset(pp);
2183 mvneta_rx_reset(pp);
2186 /* tx timeout callback - display a message and stop/start the network device */
2187 static void mvneta_tx_timeout(struct net_device *dev)
2189 struct mvneta_port *pp = netdev_priv(dev);
2191 netdev_info(dev, "tx timeout\n");
2192 mvneta_stop_dev(pp);
2193 mvneta_start_dev(pp);
2196 /* Return positive if MTU is valid */
2197 static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
2200 netdev_err(dev, "cannot change mtu to less than 68\n");
2204 /* 9676 == 9700 - 20 and rounding to 8 */
2206 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
2210 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
2211 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
2212 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
2213 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
2219 /* Change the device mtu */
2220 static int mvneta_change_mtu(struct net_device *dev, int mtu)
2222 struct mvneta_port *pp = netdev_priv(dev);
2225 mtu = mvneta_check_mtu_valid(dev, mtu);
2231 if (!netif_running(dev))
2234 /* The interface is running, so we have to force a
2235 * reallocation of the RXQs
2237 mvneta_stop_dev(pp);
2239 mvneta_cleanup_txqs(pp);
2240 mvneta_cleanup_rxqs(pp);
2242 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2244 ret = mvneta_setup_rxqs(pp);
2246 netdev_err(pp->dev, "unable to setup rxqs after MTU change\n");
2250 mvneta_setup_txqs(pp);
2252 mvneta_start_dev(pp);
2258 /* Get mac address */
2259 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
2261 u32 mac_addr_l, mac_addr_h;
2263 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
2264 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
2265 addr[0] = (mac_addr_h >> 24) & 0xFF;
2266 addr[1] = (mac_addr_h >> 16) & 0xFF;
2267 addr[2] = (mac_addr_h >> 8) & 0xFF;
2268 addr[3] = mac_addr_h & 0xFF;
2269 addr[4] = (mac_addr_l >> 8) & 0xFF;
2270 addr[5] = mac_addr_l & 0xFF;
2273 /* Handle setting mac address */
2274 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
2276 struct mvneta_port *pp = netdev_priv(dev);
2280 if (netif_running(dev))
2283 /* Remove previous address table entry */
2284 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
2286 /* Set new addr in hw */
2287 mvneta_mac_addr_set(pp, mac, rxq_def);
2289 /* Set addr in the device */
2290 for (i = 0; i < ETH_ALEN; i++)
2291 dev->dev_addr[i] = mac[i];
2296 static void mvneta_adjust_link(struct net_device *ndev)
2298 struct mvneta_port *pp = netdev_priv(ndev);
2299 struct phy_device *phydev = pp->phy_dev;
2300 int status_change = 0;
2303 if ((pp->speed != phydev->speed) ||
2304 (pp->duplex != phydev->duplex)) {
2307 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2308 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
2309 MVNETA_GMAC_CONFIG_GMII_SPEED |
2310 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
2313 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
2315 if (phydev->speed == SPEED_1000)
2316 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
2318 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
2320 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2322 pp->duplex = phydev->duplex;
2323 pp->speed = phydev->speed;
2327 if (phydev->link != pp->link) {
2328 if (!phydev->link) {
2333 pp->link = phydev->link;
2337 if (status_change) {
2339 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2340 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
2341 MVNETA_GMAC_FORCE_LINK_DOWN);
2342 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2344 netdev_info(pp->dev, "link up\n");
2346 mvneta_port_down(pp);
2347 netdev_info(pp->dev, "link down\n");
2352 static int mvneta_mdio_probe(struct mvneta_port *pp)
2354 struct phy_device *phy_dev;
2356 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
2359 netdev_err(pp->dev, "could not find the PHY\n");
2363 phy_dev->supported &= PHY_GBIT_FEATURES;
2364 phy_dev->advertising = phy_dev->supported;
2366 pp->phy_dev = phy_dev;
2374 static void mvneta_mdio_remove(struct mvneta_port *pp)
2376 phy_disconnect(pp->phy_dev);
2380 static int mvneta_open(struct net_device *dev)
2382 struct mvneta_port *pp = netdev_priv(dev);
2385 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
2387 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2389 ret = mvneta_setup_rxqs(pp);
2393 ret = mvneta_setup_txqs(pp);
2395 goto err_cleanup_rxqs;
2397 /* Connect to port interrupt line */
2398 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
2399 MVNETA_DRIVER_NAME, pp);
2401 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
2402 goto err_cleanup_txqs;
2405 /* In default link is down */
2406 netif_carrier_off(pp->dev);
2408 ret = mvneta_mdio_probe(pp);
2410 netdev_err(dev, "cannot probe MDIO bus\n");
2414 mvneta_start_dev(pp);
2419 free_irq(pp->dev->irq, pp);
2421 mvneta_cleanup_txqs(pp);
2423 mvneta_cleanup_rxqs(pp);
2427 /* Stop the port, free port interrupt line */
2428 static int mvneta_stop(struct net_device *dev)
2430 struct mvneta_port *pp = netdev_priv(dev);
2432 mvneta_stop_dev(pp);
2433 mvneta_mdio_remove(pp);
2434 free_irq(dev->irq, pp);
2435 mvneta_cleanup_rxqs(pp);
2436 mvneta_cleanup_txqs(pp);
2437 del_timer(&pp->tx_done_timer);
2438 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
2443 /* Ethtool methods */
2445 /* Get settings (phy address, speed) for ethtools */
2446 int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2448 struct mvneta_port *pp = netdev_priv(dev);
2453 return phy_ethtool_gset(pp->phy_dev, cmd);
2456 /* Set settings (phy address, speed) for ethtools */
2457 int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2459 struct mvneta_port *pp = netdev_priv(dev);
2464 return phy_ethtool_sset(pp->phy_dev, cmd);
2467 /* Set interrupt coalescing for ethtools */
2468 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
2469 struct ethtool_coalesce *c)
2471 struct mvneta_port *pp = netdev_priv(dev);
2474 for (queue = 0; queue < rxq_number; queue++) {
2475 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2476 rxq->time_coal = c->rx_coalesce_usecs;
2477 rxq->pkts_coal = c->rx_max_coalesced_frames;
2478 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2479 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2482 for (queue = 0; queue < txq_number; queue++) {
2483 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2484 txq->done_pkts_coal = c->tx_max_coalesced_frames;
2485 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2491 /* get coalescing for ethtools */
2492 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
2493 struct ethtool_coalesce *c)
2495 struct mvneta_port *pp = netdev_priv(dev);
2497 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
2498 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
2500 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
2505 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
2506 struct ethtool_drvinfo *drvinfo)
2508 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
2509 sizeof(drvinfo->driver));
2510 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
2511 sizeof(drvinfo->version));
2512 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
2513 sizeof(drvinfo->bus_info));
2517 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
2518 struct ethtool_ringparam *ring)
2520 struct mvneta_port *pp = netdev_priv(netdev);
2522 ring->rx_max_pending = MVNETA_MAX_RXD;
2523 ring->tx_max_pending = MVNETA_MAX_TXD;
2524 ring->rx_pending = pp->rx_ring_size;
2525 ring->tx_pending = pp->tx_ring_size;
2528 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
2529 struct ethtool_ringparam *ring)
2531 struct mvneta_port *pp = netdev_priv(dev);
2533 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
2535 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
2536 ring->rx_pending : MVNETA_MAX_RXD;
2537 pp->tx_ring_size = ring->tx_pending < MVNETA_MAX_TXD ?
2538 ring->tx_pending : MVNETA_MAX_TXD;
2540 if (netif_running(dev)) {
2542 if (mvneta_open(dev)) {
2544 "error on opening device after ring param change\n");
2552 static const struct net_device_ops mvneta_netdev_ops = {
2553 .ndo_open = mvneta_open,
2554 .ndo_stop = mvneta_stop,
2555 .ndo_start_xmit = mvneta_tx,
2556 .ndo_set_rx_mode = mvneta_set_rx_mode,
2557 .ndo_set_mac_address = mvneta_set_mac_addr,
2558 .ndo_change_mtu = mvneta_change_mtu,
2559 .ndo_tx_timeout = mvneta_tx_timeout,
2560 .ndo_get_stats64 = mvneta_get_stats64,
2563 const struct ethtool_ops mvneta_eth_tool_ops = {
2564 .get_link = ethtool_op_get_link,
2565 .get_settings = mvneta_ethtool_get_settings,
2566 .set_settings = mvneta_ethtool_set_settings,
2567 .set_coalesce = mvneta_ethtool_set_coalesce,
2568 .get_coalesce = mvneta_ethtool_get_coalesce,
2569 .get_drvinfo = mvneta_ethtool_get_drvinfo,
2570 .get_ringparam = mvneta_ethtool_get_ringparam,
2571 .set_ringparam = mvneta_ethtool_set_ringparam,
2575 static int mvneta_init(struct mvneta_port *pp, int phy_addr)
2580 mvneta_port_disable(pp);
2582 /* Set port default values */
2583 mvneta_defaults_set(pp);
2585 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
2590 /* Initialize TX descriptor rings */
2591 for (queue = 0; queue < txq_number; queue++) {
2592 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2594 txq->size = pp->tx_ring_size;
2595 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
2598 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
2605 /* Create Rx descriptor rings */
2606 for (queue = 0; queue < rxq_number; queue++) {
2607 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2609 rxq->size = pp->rx_ring_size;
2610 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
2611 rxq->time_coal = MVNETA_RX_COAL_USEC;
2617 static void mvneta_deinit(struct mvneta_port *pp)
2623 /* platform glue : initialize decoding windows */
2624 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
2625 const struct mbus_dram_target_info *dram)
2631 for (i = 0; i < 6; i++) {
2632 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
2633 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
2636 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
2642 for (i = 0; i < dram->num_cs; i++) {
2643 const struct mbus_dram_window *cs = dram->cs + i;
2644 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
2645 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
2647 mvreg_write(pp, MVNETA_WIN_SIZE(i),
2648 (cs->size - 1) & 0xffff0000);
2650 win_enable &= ~(1 << i);
2651 win_protect |= 3 << (2 * i);
2654 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
2657 /* Power up the port */
2658 static void mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
2662 /* MAC Cause register should be cleared */
2663 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
2665 if (phy_mode == PHY_INTERFACE_MODE_SGMII)
2666 mvneta_port_sgmii_config(pp);
2668 mvneta_gmac_rgmii_set(pp, 1);
2670 /* Cancel Port Reset */
2671 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
2672 val &= ~MVNETA_GMAC2_PORT_RESET;
2673 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
2675 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
2676 MVNETA_GMAC2_PORT_RESET) != 0)
2680 /* Device initialization routine */
2681 static int mvneta_probe(struct platform_device *pdev)
2683 const struct mbus_dram_target_info *dram_target_info;
2684 struct device_node *dn = pdev->dev.of_node;
2685 struct device_node *phy_node;
2687 struct mvneta_port *pp;
2688 struct net_device *dev;
2689 const char *dt_mac_addr;
2690 char hw_mac_addr[ETH_ALEN];
2691 const char *mac_from;
2695 /* Our multiqueue support is not complete, so for now, only
2696 * allow the usage of the first RX queue
2699 dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def);
2703 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
2707 dev->irq = irq_of_parse_and_map(dn, 0);
2708 if (dev->irq == 0) {
2710 goto err_free_netdev;
2713 phy_node = of_parse_phandle(dn, "phy", 0);
2715 dev_err(&pdev->dev, "no associated PHY\n");
2720 phy_mode = of_get_phy_mode(dn);
2722 dev_err(&pdev->dev, "incorrect phy-mode\n");
2727 dev->tx_queue_len = MVNETA_MAX_TXD;
2728 dev->watchdog_timeo = 5 * HZ;
2729 dev->netdev_ops = &mvneta_netdev_ops;
2731 SET_ETHTOOL_OPS(dev, &mvneta_eth_tool_ops);
2733 pp = netdev_priv(dev);
2735 pp->weight = MVNETA_RX_POLL_WEIGHT;
2736 pp->phy_node = phy_node;
2737 pp->phy_interface = phy_mode;
2739 pp->clk = devm_clk_get(&pdev->dev, NULL);
2740 if (IS_ERR(pp->clk)) {
2741 err = PTR_ERR(pp->clk);
2745 clk_prepare_enable(pp->clk);
2747 pp->base = of_iomap(dn, 0);
2748 if (pp->base == NULL) {
2753 dt_mac_addr = of_get_mac_address(dn);
2754 if (dt_mac_addr && is_valid_ether_addr(dt_mac_addr)) {
2755 mac_from = "device tree";
2756 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
2758 mvneta_get_mac_addr(pp, hw_mac_addr);
2759 if (is_valid_ether_addr(hw_mac_addr)) {
2760 mac_from = "hardware";
2761 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
2763 mac_from = "random";
2764 eth_hw_addr_random(dev);
2768 pp->tx_done_timer.data = (unsigned long)dev;
2769 pp->tx_done_timer.function = mvneta_tx_done_timer_callback;
2770 init_timer(&pp->tx_done_timer);
2771 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
2773 pp->tx_ring_size = MVNETA_MAX_TXD;
2774 pp->rx_ring_size = MVNETA_MAX_RXD;
2777 SET_NETDEV_DEV(dev, &pdev->dev);
2779 err = mvneta_init(pp, phy_addr);
2781 dev_err(&pdev->dev, "can't init eth hal\n");
2784 mvneta_port_power_up(pp, phy_mode);
2786 dram_target_info = mv_mbus_dram_info();
2787 if (dram_target_info)
2788 mvneta_conf_mbus_windows(pp, dram_target_info);
2790 netif_napi_add(dev, &pp->napi, mvneta_poll, pp->weight);
2792 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2793 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2794 dev->vlan_features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2795 dev->priv_flags |= IFF_UNICAST_FLT;
2797 err = register_netdev(dev);
2799 dev_err(&pdev->dev, "failed to register\n");
2803 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
2806 platform_set_drvdata(pdev, pp->dev);
2815 clk_disable_unprepare(pp->clk);
2817 irq_dispose_mapping(dev->irq);
2823 /* Device removal routine */
2824 static int mvneta_remove(struct platform_device *pdev)
2826 struct net_device *dev = platform_get_drvdata(pdev);
2827 struct mvneta_port *pp = netdev_priv(dev);
2829 unregister_netdev(dev);
2831 clk_disable_unprepare(pp->clk);
2833 irq_dispose_mapping(dev->irq);
2839 static const struct of_device_id mvneta_match[] = {
2840 { .compatible = "marvell,armada-370-neta" },
2843 MODULE_DEVICE_TABLE(of, mvneta_match);
2845 static struct platform_driver mvneta_driver = {
2846 .probe = mvneta_probe,
2847 .remove = mvneta_remove,
2849 .name = MVNETA_DRIVER_NAME,
2850 .of_match_table = mvneta_match,
2854 module_platform_driver(mvneta_driver);
2856 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
2857 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
2858 MODULE_LICENSE("GPL");
2860 module_param(rxq_number, int, S_IRUGO);
2861 module_param(txq_number, int, S_IRUGO);
2863 module_param(rxq_def, int, S_IRUGO);