Pileus Git - ~andy/linux/blob - drivers/net/ethernet/intel/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29
  30 #include <linux/module.h>
  31 #include <linux/types.h>
  32 #include <linux/init.h>
  33 #include <linux/bitops.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/ipv6.h>
  38 #include <linux/slab.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/net_tstamp.h>
  42 #include <linux/mii.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/pci.h>
  47 #include <linux/pci-aspm.h>
  48 #include <linux/delay.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/ip.h>
  51 #include <linux/tcp.h>
  52 #include <linux/sctp.h>
  53 #include <linux/if_ether.h>
  54 #include <linux/aer.h>
  55 #include <linux/prefetch.h>
  56 #include <linux/pm_runtime.h>
  57 #ifdef CONFIG_IGB_DCA
  58 #include <linux/dca.h>
  59 #endif
  60 #include "igb.h"
  61
  62 #define MAJ 4
  63 #define MIN 0
  64 #define BUILD 17
  65 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  66 __stringify(BUILD) "-k"
  67 char igb_driver_name[] = "igb";
  68 char igb_driver_version[] = DRV_VERSION;
  69 static const char igb_driver_string[] =
  70                                 "Intel(R) Gigabit Ethernet Network Driver";
  71 static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation.";
  72
  73 static const struct e1000_info *igb_info_tbl[] = {
  74         [board_82575] = &e1000_82575_info,
  75 };
  76
  77 static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
  78         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
  79         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
  80         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
  81         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
  82         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
  83         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
  84         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
  85         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
  86         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
  87         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
  88         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
  89         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
  90         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
  91         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
  92         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
  93         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
  94         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
  95         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
  96         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
  97         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  98         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  99         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
 100         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
 101         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
 102         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
 103         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
 104         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
 105         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
 106         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
 107         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
 108         /* required last entry */
 109         {0, }
 110 };
 111
 112 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
 113
 114 void igb_reset(struct igb_adapter *);
 115 static int igb_setup_all_tx_resources(struct igb_adapter *);
 116 static int igb_setup_all_rx_resources(struct igb_adapter *);
 117 static void igb_free_all_tx_resources(struct igb_adapter *);
 118 static void igb_free_all_rx_resources(struct igb_adapter *);
 119 static void igb_setup_mrqc(struct igb_adapter *);
 120 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
 121 static void __devexit igb_remove(struct pci_dev *pdev);
 122 static int igb_sw_init(struct igb_adapter *);
 123 static int igb_open(struct net_device *);
 124 static int igb_close(struct net_device *);
 125 static void igb_configure_tx(struct igb_adapter *);
 126 static void igb_configure_rx(struct igb_adapter *);
 127 static void igb_clean_all_tx_rings(struct igb_adapter *);
 128 static void igb_clean_all_rx_rings(struct igb_adapter *);
 129 static void igb_clean_tx_ring(struct igb_ring *);
 130 static void igb_clean_rx_ring(struct igb_ring *);
 131 static void igb_set_rx_mode(struct net_device *);
 132 static void igb_update_phy_info(unsigned long);
 133 static void igb_watchdog(unsigned long);
 134 static void igb_watchdog_task(struct work_struct *);
 135 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
 136 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
 137                                                  struct rtnl_link_stats64 *stats);
 138 static int igb_change_mtu(struct net_device *, int);
 139 static int igb_set_mac(struct net_device *, void *);
 140 static void igb_set_uta(struct igb_adapter *adapter);
 141 static irqreturn_t igb_intr(int irq, void *);
 142 static irqreturn_t igb_intr_msi(int irq, void *);
 143 static irqreturn_t igb_msix_other(int irq, void *);
 144 static irqreturn_t igb_msix_ring(int irq, void *);
 145 #ifdef CONFIG_IGB_DCA
 146 static void igb_update_dca(struct igb_q_vector *);
 147 static void igb_setup_dca(struct igb_adapter *);
 148 #endif /* CONFIG_IGB_DCA */
 149 static int igb_poll(struct napi_struct *, int);
 150 static bool igb_clean_tx_irq(struct igb_q_vector *);
 151 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
 152 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 153 static void igb_tx_timeout(struct net_device *);
 154 static void igb_reset_task(struct work_struct *);
 155 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
 156 static int igb_vlan_rx_add_vid(struct net_device *, u16);
 157 static int igb_vlan_rx_kill_vid(struct net_device *, u16);
 158 static void igb_restore_vlan(struct igb_adapter *);
 159 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
 160 static void igb_ping_all_vfs(struct igb_adapter *);
 161 static void igb_msg_task(struct igb_adapter *);
 162 static void igb_vmm_control(struct igb_adapter *);
 163 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
 164 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 165 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
 166 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
 167                                int vf, u16 vlan, u8 qos);
 168 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
 169 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
 170                                  struct ifla_vf_info *ivi);
 171 static void igb_check_vf_rate_limit(struct igb_adapter *);
 172
 173 #ifdef CONFIG_PCI_IOV
 174 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
 175 static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
 176 #endif
 177
 178 #ifdef CONFIG_PM
 179 #ifdef CONFIG_PM_SLEEP
 180 static int igb_suspend(struct device *);
 181 #endif
 182 static int igb_resume(struct device *);
 183 #ifdef CONFIG_PM_RUNTIME
 184 static int igb_runtime_suspend(struct device *dev);
 185 static int igb_runtime_resume(struct device *dev);
 186 static int igb_runtime_idle(struct device *dev);
 187 #endif
 188 static const struct dev_pm_ops igb_pm_ops = {
 189         SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
 190         SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
 191                         igb_runtime_idle)
 192 };
 193 #endif
 194 static void igb_shutdown(struct pci_dev *);
 195 #ifdef CONFIG_IGB_DCA
 196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 197 static struct notifier_block dca_notifier = {
 198         .notifier_call  = igb_notify_dca,
 199         .next           = NULL,
 200         .priority       = 0
 201 };
 202 #endif
 203 #ifdef CONFIG_NET_POLL_CONTROLLER
 204 /* for netdump / net console */
 205 static void igb_netpoll(struct net_device *);
 206 #endif
 207 #ifdef CONFIG_PCI_IOV
 208 static unsigned int max_vfs = 0;
 209 module_param(max_vfs, uint, 0);
 210 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 211                  "per physical function");
 212 #endif /* CONFIG_PCI_IOV */
 213
 214 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 215                      pci_channel_state_t);
 216 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 217 static void igb_io_resume(struct pci_dev *);
 218
 219 static const struct pci_error_handlers igb_err_handler = {
 220         .error_detected = igb_io_error_detected,
 221         .slot_reset = igb_io_slot_reset,
 222         .resume = igb_io_resume,
 223 };
 224
 225 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
 226
 227 static struct pci_driver igb_driver = {
 228         .name     = igb_driver_name,
 229         .id_table = igb_pci_tbl,
 230         .probe    = igb_probe,
 231         .remove   = __devexit_p(igb_remove),
 232 #ifdef CONFIG_PM
 233         .driver.pm = &igb_pm_ops,
 234 #endif
 235         .shutdown = igb_shutdown,
 236         .err_handler = &igb_err_handler
 237 };
 238
 239 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 240 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 241 MODULE_LICENSE("GPL");
 242 MODULE_VERSION(DRV_VERSION);
 243
 244 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
 245 static int debug = -1;
 246 module_param(debug, int, 0);
 247 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 248
 249 struct igb_reg_info {
 250         u32 ofs;
 251         char *name;
 252 };
 253
 254 static const struct igb_reg_info igb_reg_info_tbl[] = {
 255
 256         /* General Registers */
 257         {E1000_CTRL, "CTRL"},
 258         {E1000_STATUS, "STATUS"},
 259         {E1000_CTRL_EXT, "CTRL_EXT"},
 260
 261         /* Interrupt Registers */
 262         {E1000_ICR, "ICR"},
 263
 264         /* RX Registers */
 265         {E1000_RCTL, "RCTL"},
 266         {E1000_RDLEN(0), "RDLEN"},
 267         {E1000_RDH(0), "RDH"},
 268         {E1000_RDT(0), "RDT"},
 269         {E1000_RXDCTL(0), "RXDCTL"},
 270         {E1000_RDBAL(0), "RDBAL"},
 271         {E1000_RDBAH(0), "RDBAH"},
 272
 273         /* TX Registers */
 274         {E1000_TCTL, "TCTL"},
 275         {E1000_TDBAL(0), "TDBAL"},
 276         {E1000_TDBAH(0), "TDBAH"},
 277         {E1000_TDLEN(0), "TDLEN"},
 278         {E1000_TDH(0), "TDH"},
 279         {E1000_TDT(0), "TDT"},
 280         {E1000_TXDCTL(0), "TXDCTL"},
 281         {E1000_TDFH, "TDFH"},
 282         {E1000_TDFT, "TDFT"},
 283         {E1000_TDFHS, "TDFHS"},
 284         {E1000_TDFPC, "TDFPC"},
 285
 286         /* List Terminator */
 287         {}
 288 };
 289
 290 /*
 291  * igb_regdump - register printout routine
 292  */
 293 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
 294 {
 295         int n = 0;
 296         char rname[16];
 297         u32 regs[8];
 298
 299         switch (reginfo->ofs) {
 300         case E1000_RDLEN(0):
 301                 for (n = 0; n < 4; n++)
 302                         regs[n] = rd32(E1000_RDLEN(n));
 303                 break;
 304         case E1000_RDH(0):
 305                 for (n = 0; n < 4; n++)
 306                         regs[n] = rd32(E1000_RDH(n));
 307                 break;
 308         case E1000_RDT(0):
 309                 for (n = 0; n < 4; n++)
 310                         regs[n] = rd32(E1000_RDT(n));
 311                 break;
 312         case E1000_RXDCTL(0):
 313                 for (n = 0; n < 4; n++)
 314                         regs[n] = rd32(E1000_RXDCTL(n));
 315                 break;
 316         case E1000_RDBAL(0):
 317                 for (n = 0; n < 4; n++)
 318                         regs[n] = rd32(E1000_RDBAL(n));
 319                 break;
 320         case E1000_RDBAH(0):
 321                 for (n = 0; n < 4; n++)
 322                         regs[n] = rd32(E1000_RDBAH(n));
 323                 break;
 324         case E1000_TDBAL(0):
 325                 for (n = 0; n < 4; n++)
 326                         regs[n] = rd32(E1000_RDBAL(n));
 327                 break;
 328         case E1000_TDBAH(0):
 329                 for (n = 0; n < 4; n++)
 330                         regs[n] = rd32(E1000_TDBAH(n));
 331                 break;
 332         case E1000_TDLEN(0):
 333                 for (n = 0; n < 4; n++)
 334                         regs[n] = rd32(E1000_TDLEN(n));
 335                 break;
 336         case E1000_TDH(0):
 337                 for (n = 0; n < 4; n++)
 338                         regs[n] = rd32(E1000_TDH(n));
 339                 break;
 340         case E1000_TDT(0):
 341                 for (n = 0; n < 4; n++)
 342                         regs[n] = rd32(E1000_TDT(n));
 343                 break;
 344         case E1000_TXDCTL(0):
 345                 for (n = 0; n < 4; n++)
 346                         regs[n] = rd32(E1000_TXDCTL(n));
 347                 break;
 348         default:
 349                 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
 350                 return;
 351         }
 352
 353         snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
 354         pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
 355                 regs[2], regs[3]);
 356 }
 357
 358 /*
 359  * igb_dump - Print registers, tx-rings and rx-rings
 360  */
 361 static void igb_dump(struct igb_adapter *adapter)
 362 {
 363         struct net_device *netdev = adapter->netdev;
 364         struct e1000_hw *hw = &adapter->hw;
 365         struct igb_reg_info *reginfo;
 366         struct igb_ring *tx_ring;
 367         union e1000_adv_tx_desc *tx_desc;
 368         struct my_u0 { u64 a; u64 b; } *u0;
 369         struct igb_ring *rx_ring;
 370         union e1000_adv_rx_desc *rx_desc;
 371         u32 staterr;
 372         u16 i, n;
 373
 374         if (!netif_msg_hw(adapter))
 375                 return;
 376
 377         /* Print netdevice Info */
 378         if (netdev) {
 379                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 380                 pr_info("Device Name     state            trans_start      "
 381                         "last_rx\n");
 382                 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
 383                         netdev->state, netdev->trans_start, netdev->last_rx);
 384         }
 385
 386         /* Print Registers */
 387         dev_info(&adapter->pdev->dev, "Register Dump\n");
 388         pr_info(" Register Name   Value\n");
 389         for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
 390              reginfo->name; reginfo++) {
 391                 igb_regdump(hw, reginfo);
 392         }
 393
 394         /* Print TX Ring Summary */
 395         if (!netdev || !netif_running(netdev))
 396                 goto exit;
 397
 398         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 399         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 400         for (n = 0; n < adapter->num_tx_queues; n++) {
 401                 struct igb_tx_buffer *buffer_info;
 402                 tx_ring = adapter->tx_ring[n];
 403                 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 404                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 405                         n, tx_ring->next_to_use, tx_ring->next_to_clean,
 406                         (u64)dma_unmap_addr(buffer_info, dma),
 407                         dma_unmap_len(buffer_info, len),
 408                         buffer_info->next_to_watch,
 409                         (u64)buffer_info->time_stamp);
 410         }
 411
 412         /* Print TX Rings */
 413         if (!netif_msg_tx_done(adapter))
 414                 goto rx_ring_summary;
 415
 416         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 417
 418         /* Transmit Descriptor Formats
 419          *
 420          * Advanced Transmit Descriptor
 421          *   +--------------------------------------------------------------+
 422          * 0 |         Buffer Address [63:0]                                |
 423          *   +--------------------------------------------------------------+
 424          * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
 425          *   +--------------------------------------------------------------+
 426          *   63      46 45    40 39 38 36 35 32 31   24             15       0
 427          */
 428
 429         for (n = 0; n < adapter->num_tx_queues; n++) {
 430                 tx_ring = adapter->tx_ring[n];
 431                 pr_info("------------------------------------\n");
 432                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 433                 pr_info("------------------------------------\n");
 434                 pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] "
 435                         "[bi->dma       ] leng  ntw timestamp        "
 436                         "bi->skb\n");
 437
 438                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 439                         const char *next_desc;
 440                         struct igb_tx_buffer *buffer_info;
 441                         tx_desc = IGB_TX_DESC(tx_ring, i);
 442                         buffer_info = &tx_ring->tx_buffer_info[i];
 443                         u0 = (struct my_u0 *)tx_desc;
 444                         if (i == tx_ring->next_to_use &&
 445                             i == tx_ring->next_to_clean)
 446                                 next_desc = " NTC/U";
 447                         else if (i == tx_ring->next_to_use)
 448                                 next_desc = " NTU";
 449                         else if (i == tx_ring->next_to_clean)
 450                                 next_desc = " NTC";
 451                         else
 452                                 next_desc = "";
 453
 454                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 455                                 " %04X  %p %016llX %p%s\n", i,
 456                                 le64_to_cpu(u0->a),
 457                                 le64_to_cpu(u0->b),
 458                                 (u64)dma_unmap_addr(buffer_info, dma),
 459                                 dma_unmap_len(buffer_info, len),
 460                                 buffer_info->next_to_watch,
 461                                 (u64)buffer_info->time_stamp,
 462                                 buffer_info->skb, next_desc);
 463
 464                         if (netif_msg_pktdata(adapter) && buffer_info->skb)
 465                                 print_hex_dump(KERN_INFO, "",
 466                                         DUMP_PREFIX_ADDRESS,
 467                                         16, 1, buffer_info->skb->data,
 468                                         dma_unmap_len(buffer_info, len),
 469                                         true);
 470                 }
 471         }
 472
 473         /* Print RX Rings Summary */
 474 rx_ring_summary:
 475         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 476         pr_info("Queue [NTU] [NTC]\n");
 477         for (n = 0; n < adapter->num_rx_queues; n++) {
 478                 rx_ring = adapter->rx_ring[n];
 479                 pr_info(" %5d %5X %5X\n",
 480                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 481         }
 482
 483         /* Print RX Rings */
 484         if (!netif_msg_rx_status(adapter))
 485                 goto exit;
 486
 487         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 488
 489         /* Advanced Receive Descriptor (Read) Format
 490          *    63                                           1        0
 491          *    +-----------------------------------------------------+
 492          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 493          *    +----------------------------------------------+------+
 494          *  8 |       Header Buffer Address [63:1]           |  DD  |
 495          *    +-----------------------------------------------------+
 496          *
 497          *
 498          * Advanced Receive Descriptor (Write-Back) Format
 499          *
 500          *   63       48 47    32 31  30      21 20 17 16   4 3     0
 501          *   +------------------------------------------------------+
 502          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 503          *   | Checksum   Ident  |   |           |    | Type | Type |
 504          *   +------------------------------------------------------+
 505          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 506          *   +------------------------------------------------------+
 507          *   63       48 47    32 31            20 19               0
 508          */
 509
 510         for (n = 0; n < adapter->num_rx_queues; n++) {
 511                 rx_ring = adapter->rx_ring[n];
 512                 pr_info("------------------------------------\n");
 513                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 514                 pr_info("------------------------------------\n");
 515                 pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] "
 516                         "[bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
 517                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] -----"
 518                         "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
 519
 520                 for (i = 0; i < rx_ring->count; i++) {
 521                         const char *next_desc;
 522                         struct igb_rx_buffer *buffer_info;
 523                         buffer_info = &rx_ring->rx_buffer_info[i];
 524                         rx_desc = IGB_RX_DESC(rx_ring, i);
 525                         u0 = (struct my_u0 *)rx_desc;
 526                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 527
 528                         if (i == rx_ring->next_to_use)
 529                                 next_desc = " NTU";
 530                         else if (i == rx_ring->next_to_clean)
 531                                 next_desc = " NTC";
 532                         else
 533                                 next_desc = "";
 534
 535                         if (staterr & E1000_RXD_STAT_DD) {
 536                                 /* Descriptor Done */
 537                                 pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
 538                                         "RWB", i,
 539                                         le64_to_cpu(u0->a),
 540                                         le64_to_cpu(u0->b),
 541                                         next_desc);
 542                         } else {
 543                                 pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
 544                                         "R  ", i,
 545                                         le64_to_cpu(u0->a),
 546                                         le64_to_cpu(u0->b),
 547                                         (u64)buffer_info->dma,
 548                                         next_desc);
 549
 550                                 if (netif_msg_pktdata(adapter) &&
 551                                     buffer_info->dma && buffer_info->page) {
 552                                         print_hex_dump(KERN_INFO, "",
 553                                           DUMP_PREFIX_ADDRESS,
 554                                           16, 1,
 555                                           page_address(buffer_info->page) +
 556                                                       buffer_info->page_offset,
 557                                           IGB_RX_BUFSZ, true);
 558                                 }
 559                         }
 560                 }
 561         }
 562
 563 exit:
 564         return;
 565 }
 566
 567 /**
 568  * igb_get_hw_dev - return device
 569  * used by hardware layer to print debugging information
 570  **/
 571 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
 572 {
 573         struct igb_adapter *adapter = hw->back;
 574         return adapter->netdev;
 575 }
 576
 577 /**
 578  * igb_init_module - Driver Registration Routine
 579  *
 580  * igb_init_module is the first routine called when the driver is
 581  * loaded. All it does is register with the PCI subsystem.
 582  **/
 583 static int __init igb_init_module(void)
 584 {
 585         int ret;
 586         pr_info("%s - version %s\n",
 587                igb_driver_string, igb_driver_version);
 588
 589         pr_info("%s\n", igb_copyright);
 590
 591 #ifdef CONFIG_IGB_DCA
 592         dca_register_notify(&dca_notifier);
 593 #endif
 594         ret = pci_register_driver(&igb_driver);
 595         return ret;
 596 }
 597
 598 module_init(igb_init_module);
 599
 600 /**
 601  * igb_exit_module - Driver Exit Cleanup Routine
 602  *
 603  * igb_exit_module is called just before the driver is removed
 604  * from memory.
 605  **/
 606 static void __exit igb_exit_module(void)
 607 {
 608 #ifdef CONFIG_IGB_DCA
 609         dca_unregister_notify(&dca_notifier);
 610 #endif
 611         pci_unregister_driver(&igb_driver);
 612 }
 613
 614 module_exit(igb_exit_module);
 615
 616 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 617 /**
 618  * igb_cache_ring_register - Descriptor ring to register mapping
 619  * @adapter: board private structure to initialize
 620  *
 621  * Once we know the feature-set enabled for the device, we'll cache
 622  * the register offset the descriptor ring is assigned to.
 623  **/
 624 static void igb_cache_ring_register(struct igb_adapter *adapter)
 625 {
 626         int i = 0, j = 0;
 627         u32 rbase_offset = adapter->vfs_allocated_count;
 628
 629         switch (adapter->hw.mac.type) {
 630         case e1000_82576:
 631                 /* The queues are allocated for virtualization such that VF 0
 632                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 633                  * In order to avoid collision we start at the first free queue
 634                  * and continue consuming queues in the same sequence
 635                  */
 636                 if (adapter->vfs_allocated_count) {
 637                         for (; i < adapter->rss_queues; i++)
 638                                 adapter->rx_ring[i]->reg_idx = rbase_offset +
 639                                                                Q_IDX_82576(i);
 640                 }
 641         case e1000_82575:
 642         case e1000_82580:
 643         case e1000_i350:
 644         case e1000_i210:
 645         case e1000_i211:
 646         default:
 647                 for (; i < adapter->num_rx_queues; i++)
 648                         adapter->rx_ring[i]->reg_idx = rbase_offset + i;
 649                 for (; j < adapter->num_tx_queues; j++)
 650                         adapter->tx_ring[j]->reg_idx = rbase_offset + j;
 651                 break;
 652         }
 653 }
 654
 655 /**
 656  *  igb_write_ivar - configure ivar for given MSI-X vector
 657  *  @hw: pointer to the HW structure
 658  *  @msix_vector: vector number we are allocating to a given ring
 659  *  @index: row index of IVAR register to write within IVAR table
 660  *  @offset: column offset of in IVAR, should be multiple of 8
 661  *
 662  *  This function is intended to handle the writing of the IVAR register
 663  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
 664  *  each containing an cause allocation for an Rx and Tx ring, and a
 665  *  variable number of rows depending on the number of queues supported.
 666  **/
 667 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
 668                            int index, int offset)
 669 {
 670         u32 ivar = array_rd32(E1000_IVAR0, index);
 671
 672         /* clear any bits that are currently set */
 673         ivar &= ~((u32)0xFF << offset);
 674
 675         /* write vector and valid bit */
 676         ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
 677
 678         array_wr32(E1000_IVAR0, index, ivar);
 679 }
 680
 681 #define IGB_N0_QUEUE -1
 682 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
 683 {
 684         struct igb_adapter *adapter = q_vector->adapter;
 685         struct e1000_hw *hw = &adapter->hw;
 686         int rx_queue = IGB_N0_QUEUE;
 687         int tx_queue = IGB_N0_QUEUE;
 688         u32 msixbm = 0;
 689
 690         if (q_vector->rx.ring)
 691                 rx_queue = q_vector->rx.ring->reg_idx;
 692         if (q_vector->tx.ring)
 693                 tx_queue = q_vector->tx.ring->reg_idx;
 694
 695         switch (hw->mac.type) {
 696         case e1000_82575:
 697                 /* The 82575 assigns vectors using a bitmask, which matches the
 698                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 699                    or more queues to a vector, we write the appropriate bits
 700                    into the MSIXBM register for that vector. */
 701                 if (rx_queue > IGB_N0_QUEUE)
 702                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 703                 if (tx_queue > IGB_N0_QUEUE)
 704                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 705                 if (!adapter->msix_entries && msix_vector == 0)
 706                         msixbm |= E1000_EIMS_OTHER;
 707                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 708                 q_vector->eims_value = msixbm;
 709                 break;
 710         case e1000_82576:
 711                 /*
 712                  * 82576 uses a table that essentially consists of 2 columns
 713                  * with 8 rows.  The ordering is column-major so we use the
 714                  * lower 3 bits as the row index, and the 4th bit as the
 715                  * column offset.
 716                  */
 717                 if (rx_queue > IGB_N0_QUEUE)
 718                         igb_write_ivar(hw, msix_vector,
 719                                        rx_queue & 0x7,
 720                                        (rx_queue & 0x8) << 1);
 721                 if (tx_queue > IGB_N0_QUEUE)
 722                         igb_write_ivar(hw, msix_vector,
 723                                        tx_queue & 0x7,
 724                                        ((tx_queue & 0x8) << 1) + 8);
 725                 q_vector->eims_value = 1 << msix_vector;
 726                 break;
 727         case e1000_82580:
 728         case e1000_i350:
 729         case e1000_i210:
 730         case e1000_i211:
 731                 /*
 732                  * On 82580 and newer adapters the scheme is similar to 82576
 733                  * however instead of ordering column-major we have things
 734                  * ordered row-major.  So we traverse the table by using
 735                  * bit 0 as the column offset, and the remaining bits as the
 736                  * row index.
 737                  */
 738                 if (rx_queue > IGB_N0_QUEUE)
 739                         igb_write_ivar(hw, msix_vector,
 740                                        rx_queue >> 1,
 741                                        (rx_queue & 0x1) << 4);
 742                 if (tx_queue > IGB_N0_QUEUE)
 743                         igb_write_ivar(hw, msix_vector,
 744                                        tx_queue >> 1,
 745                                        ((tx_queue & 0x1) << 4) + 8);
 746                 q_vector->eims_value = 1 << msix_vector;
 747                 break;
 748         default:
 749                 BUG();
 750                 break;
 751         }
 752
 753         /* add q_vector eims value to global eims_enable_mask */
 754         adapter->eims_enable_mask |= q_vector->eims_value;
 755
 756         /* configure q_vector to set itr on first interrupt */
 757         q_vector->set_itr = 1;
 758 }
 759
 760 /**
 761  * igb_configure_msix - Configure MSI-X hardware
 762  *
 763  * igb_configure_msix sets up the hardware to properly
 764  * generate MSI-X interrupts.
 765  **/
 766 static void igb_configure_msix(struct igb_adapter *adapter)
 767 {
 768         u32 tmp;
 769         int i, vector = 0;
 770         struct e1000_hw *hw = &adapter->hw;
 771
 772         adapter->eims_enable_mask = 0;
 773
 774         /* set vector for other causes, i.e. link changes */
 775         switch (hw->mac.type) {
 776         case e1000_82575:
 777                 tmp = rd32(E1000_CTRL_EXT);
 778                 /* enable MSI-X PBA support*/
 779                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 780
 781                 /* Auto-Mask interrupts upon ICR read. */
 782                 tmp |= E1000_CTRL_EXT_EIAME;
 783                 tmp |= E1000_CTRL_EXT_IRCA;
 784
 785                 wr32(E1000_CTRL_EXT, tmp);
 786
 787                 /* enable msix_other interrupt */
 788                 array_wr32(E1000_MSIXBM(0), vector++,
 789                                       E1000_EIMS_OTHER);
 790                 adapter->eims_other = E1000_EIMS_OTHER;
 791
 792                 break;
 793
 794         case e1000_82576:
 795         case e1000_82580:
 796         case e1000_i350:
 797         case e1000_i210:
 798         case e1000_i211:
 799                 /* Turn on MSI-X capability first, or our settings
 800                  * won't stick.  And it will take days to debug. */
 801                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 802                                 E1000_GPIE_PBA | E1000_GPIE_EIAME |
 803                                 E1000_GPIE_NSICR);
 804
 805                 /* enable msix_other interrupt */
 806                 adapter->eims_other = 1 << vector;
 807                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 808
 809                 wr32(E1000_IVAR_MISC, tmp);
 810                 break;
 811         default:
 812                 /* do nothing, since nothing else supports MSI-X */
 813                 break;
 814         } /* switch (hw->mac.type) */
 815
 816         adapter->eims_enable_mask |= adapter->eims_other;
 817
 818         for (i = 0; i < adapter->num_q_vectors; i++)
 819                 igb_assign_vector(adapter->q_vector[i], vector++);
 820
 821         wrfl();
 822 }
 823
 824 /**
 825  * igb_request_msix - Initialize MSI-X interrupts
 826  *
 827  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 828  * kernel.
 829  **/
 830 static int igb_request_msix(struct igb_adapter *adapter)
 831 {
 832         struct net_device *netdev = adapter->netdev;
 833         struct e1000_hw *hw = &adapter->hw;
 834         int i, err = 0, vector = 0;
 835
 836         err = request_irq(adapter->msix_entries[vector].vector,
 837                           igb_msix_other, 0, netdev->name, adapter);
 838         if (err)
 839                 goto out;
 840         vector++;
 841
 842         for (i = 0; i < adapter->num_q_vectors; i++) {
 843                 struct igb_q_vector *q_vector = adapter->q_vector[i];
 844
 845                 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
 846
 847                 if (q_vector->rx.ring && q_vector->tx.ring)
 848                         sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
 849                                 q_vector->rx.ring->queue_index);
 850                 else if (q_vector->tx.ring)
 851                         sprintf(q_vector->name, "%s-tx-%u", netdev->name,
 852                                 q_vector->tx.ring->queue_index);
 853                 else if (q_vector->rx.ring)
 854                         sprintf(q_vector->name, "%s-rx-%u", netdev->name,
 855                                 q_vector->rx.ring->queue_index);
 856                 else
 857                         sprintf(q_vector->name, "%s-unused", netdev->name);
 858
 859                 err = request_irq(adapter->msix_entries[vector].vector,
 860                                   igb_msix_ring, 0, q_vector->name,
 861                                   q_vector);
 862                 if (err)
 863                         goto out;
 864                 vector++;
 865         }
 866
 867         igb_configure_msix(adapter);
 868         return 0;
 869 out:
 870         return err;
 871 }
 872
 873 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 874 {
 875         if (adapter->msix_entries) {
 876                 pci_disable_msix(adapter->pdev);
 877                 kfree(adapter->msix_entries);
 878                 adapter->msix_entries = NULL;
 879         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
 880                 pci_disable_msi(adapter->pdev);
 881         }
 882 }
 883
 884 /**
 885  * igb_free_q_vector - Free memory allocated for specific interrupt vector
 886  * @adapter: board private structure to initialize
 887  * @v_idx: Index of vector to be freed
 888  *
 889  * This function frees the memory allocated to the q_vector.  In addition if
 890  * NAPI is enabled it will delete any references to the NAPI struct prior
 891  * to freeing the q_vector.
 892  **/
 893 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
 894 {
 895         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
 896
 897         if (q_vector->tx.ring)
 898                 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
 899
 900         if (q_vector->rx.ring)
 901                 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
 902
 903         adapter->q_vector[v_idx] = NULL;
 904         netif_napi_del(&q_vector->napi);
 905
 906         /*
 907          * ixgbe_get_stats64() might access the rings on this vector,
 908          * we must wait a grace period before freeing it.
 909          */
 910         kfree_rcu(q_vector, rcu);
 911 }
 912
 913 /**
 914  * igb_free_q_vectors - Free memory allocated for interrupt vectors
 915  * @adapter: board private structure to initialize
 916  *
 917  * This function frees the memory allocated to the q_vectors.  In addition if
 918  * NAPI is enabled it will delete any references to the NAPI struct prior
 919  * to freeing the q_vector.
 920  **/
 921 static void igb_free_q_vectors(struct igb_adapter *adapter)
 922 {
 923         int v_idx = adapter->num_q_vectors;
 924
 925         adapter->num_tx_queues = 0;
 926         adapter->num_rx_queues = 0;
 927         adapter->num_q_vectors = 0;
 928
 929         while (v_idx--)
 930                 igb_free_q_vector(adapter, v_idx);
 931 }
 932
 933 /**
 934  * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
 935  *
 936  * This function resets the device so that it has 0 rx queues, tx queues, and
 937  * MSI-X interrupts allocated.
 938  */
 939 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
 940 {
 941         igb_free_q_vectors(adapter);
 942         igb_reset_interrupt_capability(adapter);
 943 }
 944
 945 /**
 946  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 947  *
 948  * Attempt to configure interrupts using the best available
 949  * capabilities of the hardware and kernel.
 950  **/
 951 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 952 {
 953         int err;
 954         int numvecs, i;
 955
 956         /* Number of supported queues. */
 957         adapter->num_rx_queues = adapter->rss_queues;
 958         if (adapter->vfs_allocated_count)
 959                 adapter->num_tx_queues = 1;
 960         else
 961                 adapter->num_tx_queues = adapter->rss_queues;
 962
 963         /* start with one vector for every rx queue */
 964         numvecs = adapter->num_rx_queues;
 965
 966         /* if tx handler is separate add 1 for every tx queue */
 967         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
 968                 numvecs += adapter->num_tx_queues;
 969
 970         /* store the number of vectors reserved for queues */
 971         adapter->num_q_vectors = numvecs;
 972
 973         /* add 1 vector for link status interrupts */
 974         numvecs++;
 975         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 976                                         GFP_KERNEL);
 977
 978         if (!adapter->msix_entries)
 979                 goto msi_only;
 980
 981         for (i = 0; i < numvecs; i++)
 982                 adapter->msix_entries[i].entry = i;
 983
 984         err = pci_enable_msix(adapter->pdev,
 985                               adapter->msix_entries,
 986                               numvecs);
 987         if (err == 0)
 988                 return;
 989
 990         igb_reset_interrupt_capability(adapter);
 991
 992         /* If we can't do MSI-X, try MSI */
 993 msi_only:
 994 #ifdef CONFIG_PCI_IOV
 995         /* disable SR-IOV for non MSI-X configurations */
 996         if (adapter->vf_data) {
 997                 struct e1000_hw *hw = &adapter->hw;
 998                 /* disable iov and allow time for transactions to clear */
 999                 pci_disable_sriov(adapter->pdev);
1000                 msleep(500);
1001
1002                 kfree(adapter->vf_data);
1003                 adapter->vf_data = NULL;
1004                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1005                 wrfl();
1006                 msleep(100);
1007                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1008         }
1009 #endif
1010         adapter->vfs_allocated_count = 0;
1011         adapter->rss_queues = 1;
1012         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1013         adapter->num_rx_queues = 1;
1014         adapter->num_tx_queues = 1;
1015         adapter->num_q_vectors = 1;
1016         if (!pci_enable_msi(adapter->pdev))
1017                 adapter->flags |= IGB_FLAG_HAS_MSI;
1018 }
1019
1020 static void igb_add_ring(struct igb_ring *ring,
1021                          struct igb_ring_container *head)
1022 {
1023         head->ring = ring;
1024         head->count++;
1025 }
1026
1027 /**
1028  * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1029  * @adapter: board private structure to initialize
1030  * @v_count: q_vectors allocated on adapter, used for ring interleaving
1031  * @v_idx: index of vector in adapter struct
1032  * @txr_count: total number of Tx rings to allocate
1033  * @txr_idx: index of first Tx ring to allocate
1034  * @rxr_count: total number of Rx rings to allocate
1035  * @rxr_idx: index of first Rx ring to allocate
1036  *
1037  * We allocate one q_vector.  If allocation fails we return -ENOMEM.
1038  **/
1039 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1040                               int v_count, int v_idx,
1041                               int txr_count, int txr_idx,
1042                               int rxr_count, int rxr_idx)
1043 {
1044         struct igb_q_vector *q_vector;
1045         struct igb_ring *ring;
1046         int ring_count, size;
1047
1048         /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1049         if (txr_count > 1 || rxr_count > 1)
1050                 return -ENOMEM;
1051
1052         ring_count = txr_count + rxr_count;
1053         size = sizeof(struct igb_q_vector) +
1054                (sizeof(struct igb_ring) * ring_count);
1055
1056         /* allocate q_vector and rings */
1057         q_vector = kzalloc(size, GFP_KERNEL);
1058         if (!q_vector)
1059                 return -ENOMEM;
1060
1061         /* initialize NAPI */
1062         netif_napi_add(adapter->netdev, &q_vector->napi,
1063                        igb_poll, 64);
1064
1065         /* tie q_vector and adapter together */
1066         adapter->q_vector[v_idx] = q_vector;
1067         q_vector->adapter = adapter;
1068
1069         /* initialize work limits */
1070         q_vector->tx.work_limit = adapter->tx_work_limit;
1071
1072         /* initialize ITR configuration */
1073         q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1074         q_vector->itr_val = IGB_START_ITR;
1075
1076         /* initialize pointer to rings */
1077         ring = q_vector->ring;
1078
1079         if (txr_count) {
1080                 /* assign generic ring traits */
1081                 ring->dev = &adapter->pdev->dev;
1082                 ring->netdev = adapter->netdev;
1083
1084                 /* configure backlink on ring */
1085                 ring->q_vector = q_vector;
1086
1087                 /* update q_vector Tx values */
1088                 igb_add_ring(ring, &q_vector->tx);
1089
1090                 /* For 82575, context index must be unique per ring. */
1091                 if (adapter->hw.mac.type == e1000_82575)
1092                         set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1093
1094                 /* apply Tx specific ring traits */
1095                 ring->count = adapter->tx_ring_count;
1096                 ring->queue_index = txr_idx;
1097
1098                 /* assign ring to adapter */
1099                 adapter->tx_ring[txr_idx] = ring;
1100
1101                 /* push pointer to next ring */
1102                 ring++;
1103         }
1104
1105         if (rxr_count) {
1106                 /* assign generic ring traits */
1107                 ring->dev = &adapter->pdev->dev;
1108                 ring->netdev = adapter->netdev;
1109
1110                 /* configure backlink on ring */
1111                 ring->q_vector = q_vector;
1112
1113                 /* update q_vector Rx values */
1114                 igb_add_ring(ring, &q_vector->rx);
1115
1116                 /* set flag indicating ring supports SCTP checksum offload */
1117                 if (adapter->hw.mac.type >= e1000_82576)
1118                         set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1119
1120                 /*
1121                  * On i350, i210, and i211, loopback VLAN packets
1122                  * have the tag byte-swapped.
1123                  * */
1124                 if (adapter->hw.mac.type >= e1000_i350)
1125                         set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1126
1127                 /* apply Rx specific ring traits */
1128                 ring->count = adapter->rx_ring_count;
1129                 ring->queue_index = rxr_idx;
1130
1131                 /* assign ring to adapter */
1132                 adapter->rx_ring[rxr_idx] = ring;
1133         }
1134
1135         return 0;
1136 }
1137
1138
1139 /**
1140  * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1141  * @adapter: board private structure to initialize
1142  *
1143  * We allocate one q_vector per queue interrupt.  If allocation fails we
1144  * return -ENOMEM.
1145  **/
1146 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1147 {
1148         int q_vectors = adapter->num_q_vectors;
1149         int rxr_remaining = adapter->num_rx_queues;
1150         int txr_remaining = adapter->num_tx_queues;
1151         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1152         int err;
1153
1154         if (q_vectors >= (rxr_remaining + txr_remaining)) {
1155                 for (; rxr_remaining; v_idx++) {
1156                         err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1157                                                  0, 0, 1, rxr_idx);
1158
1159                         if (err)
1160                                 goto err_out;
1161
1162                         /* update counts and index */
1163                         rxr_remaining--;
1164                         rxr_idx++;
1165                 }
1166         }
1167
1168         for (; v_idx < q_vectors; v_idx++) {
1169                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1170                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1171                 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1172                                          tqpv, txr_idx, rqpv, rxr_idx);
1173
1174                 if (err)
1175                         goto err_out;
1176
1177                 /* update counts and index */
1178                 rxr_remaining -= rqpv;
1179                 txr_remaining -= tqpv;
1180                 rxr_idx++;
1181                 txr_idx++;
1182         }
1183
1184         return 0;
1185
1186 err_out:
1187         adapter->num_tx_queues = 0;
1188         adapter->num_rx_queues = 0;
1189         adapter->num_q_vectors = 0;
1190
1191         while (v_idx--)
1192                 igb_free_q_vector(adapter, v_idx);
1193
1194         return -ENOMEM;
1195 }
1196
1197 /**
1198  * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1199  *
1200  * This function initializes the interrupts and allocates all of the queues.
1201  **/
1202 static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
1203 {
1204         struct pci_dev *pdev = adapter->pdev;
1205         int err;
1206
1207         igb_set_interrupt_capability(adapter);
1208
1209         err = igb_alloc_q_vectors(adapter);
1210         if (err) {
1211                 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1212                 goto err_alloc_q_vectors;
1213         }
1214
1215         igb_cache_ring_register(adapter);
1216
1217         return 0;
1218
1219 err_alloc_q_vectors:
1220         igb_reset_interrupt_capability(adapter);
1221         return err;
1222 }
1223
1224 /**
1225  * igb_request_irq - initialize interrupts
1226  *
1227  * Attempts to configure interrupts using the best available
1228  * capabilities of the hardware and kernel.
1229  **/
1230 static int igb_request_irq(struct igb_adapter *adapter)
1231 {
1232         struct net_device *netdev = adapter->netdev;
1233         struct pci_dev *pdev = adapter->pdev;
1234         int err = 0;
1235
1236         if (adapter->msix_entries) {
1237                 err = igb_request_msix(adapter);
1238                 if (!err)
1239                         goto request_done;
1240                 /* fall back to MSI */
1241                 igb_free_all_tx_resources(adapter);
1242                 igb_free_all_rx_resources(adapter);
1243                 igb_clear_interrupt_scheme(adapter);
1244                 if (!pci_enable_msi(pdev))
1245                         adapter->flags |= IGB_FLAG_HAS_MSI;
1246                 adapter->num_tx_queues = 1;
1247                 adapter->num_rx_queues = 1;
1248                 adapter->num_q_vectors = 1;
1249                 err = igb_alloc_q_vectors(adapter);
1250                 if (err) {
1251                         dev_err(&pdev->dev,
1252                                 "Unable to allocate memory for vectors\n");
1253                         goto request_done;
1254                 }
1255                 igb_setup_all_tx_resources(adapter);
1256                 igb_setup_all_rx_resources(adapter);
1257         }
1258
1259         igb_assign_vector(adapter->q_vector[0], 0);
1260
1261         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1262                 err = request_irq(pdev->irq, igb_intr_msi, 0,
1263                                   netdev->name, adapter);
1264                 if (!err)
1265                         goto request_done;
1266
1267                 /* fall back to legacy interrupts */
1268                 igb_reset_interrupt_capability(adapter);
1269                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1270         }
1271
1272         err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1273                           netdev->name, adapter);
1274
1275         if (err)
1276                 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1277                         err);
1278
1279 request_done:
1280         return err;
1281 }
1282
1283 static void igb_free_irq(struct igb_adapter *adapter)
1284 {
1285         if (adapter->msix_entries) {
1286                 int vector = 0, i;
1287
1288                 free_irq(adapter->msix_entries[vector++].vector, adapter);
1289
1290                 for (i = 0; i < adapter->num_q_vectors; i++)
1291                         free_irq(adapter->msix_entries[vector++].vector,
1292                                  adapter->q_vector[i]);
1293         } else {
1294                 free_irq(adapter->pdev->irq, adapter);
1295         }
1296 }
1297
1298 /**
1299  * igb_irq_disable - Mask off interrupt generation on the NIC
1300  * @adapter: board private structure
1301  **/
1302 static void igb_irq_disable(struct igb_adapter *adapter)
1303 {
1304         struct e1000_hw *hw = &adapter->hw;
1305
1306         /*
1307          * we need to be careful when disabling interrupts.  The VFs are also
1308          * mapped into these registers and so clearing the bits can cause
1309          * issues on the VF drivers so we only need to clear what we set
1310          */
1311         if (adapter->msix_entries) {
1312                 u32 regval = rd32(E1000_EIAM);
1313                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1314                 wr32(E1000_EIMC, adapter->eims_enable_mask);
1315                 regval = rd32(E1000_EIAC);
1316                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1317         }
1318
1319         wr32(E1000_IAM, 0);
1320         wr32(E1000_IMC, ~0);
1321         wrfl();
1322         if (adapter->msix_entries) {
1323                 int i;
1324                 for (i = 0; i < adapter->num_q_vectors; i++)
1325                         synchronize_irq(adapter->msix_entries[i].vector);
1326         } else {
1327                 synchronize_irq(adapter->pdev->irq);
1328         }
1329 }
1330
1331 /**
1332  * igb_irq_enable - Enable default interrupt generation settings
1333  * @adapter: board private structure
1334  **/
1335 static void igb_irq_enable(struct igb_adapter *adapter)
1336 {
1337         struct e1000_hw *hw = &adapter->hw;
1338
1339         if (adapter->msix_entries) {
1340                 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1341                 u32 regval = rd32(E1000_EIAC);
1342                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1343                 regval = rd32(E1000_EIAM);
1344                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1345                 wr32(E1000_EIMS, adapter->eims_enable_mask);
1346                 if (adapter->vfs_allocated_count) {
1347                         wr32(E1000_MBVFIMR, 0xFF);
1348                         ims |= E1000_IMS_VMMB;
1349                 }
1350                 wr32(E1000_IMS, ims);
1351         } else {
1352                 wr32(E1000_IMS, IMS_ENABLE_MASK |
1353                                 E1000_IMS_DRSTA);
1354                 wr32(E1000_IAM, IMS_ENABLE_MASK |
1355                                 E1000_IMS_DRSTA);
1356         }
1357 }
1358
1359 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1360 {
1361         struct e1000_hw *hw = &adapter->hw;
1362         u16 vid = adapter->hw.mng_cookie.vlan_id;
1363         u16 old_vid = adapter->mng_vlan_id;
1364
1365         if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1366                 /* add VID to filter table */
1367                 igb_vfta_set(hw, vid, true);
1368                 adapter->mng_vlan_id = vid;
1369         } else {
1370                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1371         }
1372
1373         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1374             (vid != old_vid) &&
1375             !test_bit(old_vid, adapter->active_vlans)) {
1376                 /* remove VID from filter table */
1377                 igb_vfta_set(hw, old_vid, false);
1378         }
1379 }
1380
1381 /**
1382  * igb_release_hw_control - release control of the h/w to f/w
1383  * @adapter: address of board private structure
1384  *
1385  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1386  * For ASF and Pass Through versions of f/w this means that the
1387  * driver is no longer loaded.
1388  *
1389  **/
1390 static void igb_release_hw_control(struct igb_adapter *adapter)
1391 {
1392         struct e1000_hw *hw = &adapter->hw;
1393         u32 ctrl_ext;
1394
1395         /* Let firmware take over control of h/w */
1396         ctrl_ext = rd32(E1000_CTRL_EXT);
1397         wr32(E1000_CTRL_EXT,
1398                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1399 }
1400
1401 /**
1402  * igb_get_hw_control - get control of the h/w from f/w
1403  * @adapter: address of board private structure
1404  *
1405  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1406  * For ASF and Pass Through versions of f/w this means that
1407  * the driver is loaded.
1408  *
1409  **/
1410 static void igb_get_hw_control(struct igb_adapter *adapter)
1411 {
1412         struct e1000_hw *hw = &adapter->hw;
1413         u32 ctrl_ext;
1414
1415         /* Let firmware know the driver has taken over */
1416         ctrl_ext = rd32(E1000_CTRL_EXT);
1417         wr32(E1000_CTRL_EXT,
1418                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1419 }
1420
1421 /**
1422  * igb_configure - configure the hardware for RX and TX
1423  * @adapter: private board structure
1424  **/
1425 static void igb_configure(struct igb_adapter *adapter)
1426 {
1427         struct net_device *netdev = adapter->netdev;
1428         int i;
1429
1430         igb_get_hw_control(adapter);
1431         igb_set_rx_mode(netdev);
1432
1433         igb_restore_vlan(adapter);
1434
1435         igb_setup_tctl(adapter);
1436         igb_setup_mrqc(adapter);
1437         igb_setup_rctl(adapter);
1438
1439         igb_configure_tx(adapter);
1440         igb_configure_rx(adapter);
1441
1442         igb_rx_fifo_flush_82575(&adapter->hw);
1443
1444         /* call igb_desc_unused which always leaves
1445          * at least 1 descriptor unused to make sure
1446          * next_to_use != next_to_clean */
1447         for (i = 0; i < adapter->num_rx_queues; i++) {
1448                 struct igb_ring *ring = adapter->rx_ring[i];
1449                 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1450         }
1451 }
1452
1453 /**
1454  * igb_power_up_link - Power up the phy/serdes link
1455  * @adapter: address of board private structure
1456  **/
1457 void igb_power_up_link(struct igb_adapter *adapter)
1458 {
1459         igb_reset_phy(&adapter->hw);
1460
1461         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1462                 igb_power_up_phy_copper(&adapter->hw);
1463         else
1464                 igb_power_up_serdes_link_82575(&adapter->hw);
1465 }
1466
1467 /**
1468  * igb_power_down_link - Power down the phy/serdes link
1469  * @adapter: address of board private structure
1470  */
1471 static void igb_power_down_link(struct igb_adapter *adapter)
1472 {
1473         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1474                 igb_power_down_phy_copper_82575(&adapter->hw);
1475         else
1476                 igb_shutdown_serdes_link_82575(&adapter->hw);
1477 }
1478
1479 /**
1480  * igb_up - Open the interface and prepare it to handle traffic
1481  * @adapter: board private structure
1482  **/
1483 int igb_up(struct igb_adapter *adapter)
1484 {
1485         struct e1000_hw *hw = &adapter->hw;
1486         int i;
1487
1488         /* hardware has been reset, we need to reload some things */
1489         igb_configure(adapter);
1490
1491         clear_bit(__IGB_DOWN, &adapter->state);
1492
1493         for (i = 0; i < adapter->num_q_vectors; i++)
1494                 napi_enable(&(adapter->q_vector[i]->napi));
1495
1496         if (adapter->msix_entries)
1497                 igb_configure_msix(adapter);
1498         else
1499                 igb_assign_vector(adapter->q_vector[0], 0);
1500
1501         /* Clear any pending interrupts. */
1502         rd32(E1000_ICR);
1503         igb_irq_enable(adapter);
1504
1505         /* notify VFs that reset has been completed */
1506         if (adapter->vfs_allocated_count) {
1507                 u32 reg_data = rd32(E1000_CTRL_EXT);
1508                 reg_data |= E1000_CTRL_EXT_PFRSTD;
1509                 wr32(E1000_CTRL_EXT, reg_data);
1510         }
1511
1512         netif_tx_start_all_queues(adapter->netdev);
1513
1514         /* start the watchdog. */
1515         hw->mac.get_link_status = 1;
1516         schedule_work(&adapter->watchdog_task);
1517
1518         return 0;
1519 }
1520
1521 void igb_down(struct igb_adapter *adapter)
1522 {
1523         struct net_device *netdev = adapter->netdev;
1524         struct e1000_hw *hw = &adapter->hw;
1525         u32 tctl, rctl;
1526         int i;
1527
1528         /* signal that we're down so the interrupt handler does not
1529          * reschedule our watchdog timer */
1530         set_bit(__IGB_DOWN, &adapter->state);
1531
1532         /* disable receives in the hardware */
1533         rctl = rd32(E1000_RCTL);
1534         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1535         /* flush and sleep below */
1536
1537         netif_tx_stop_all_queues(netdev);
1538
1539         /* disable transmits in the hardware */
1540         tctl = rd32(E1000_TCTL);
1541         tctl &= ~E1000_TCTL_EN;
1542         wr32(E1000_TCTL, tctl);
1543         /* flush both disables and wait for them to finish */
1544         wrfl();
1545         msleep(10);
1546
1547         for (i = 0; i < adapter->num_q_vectors; i++)
1548                 napi_disable(&(adapter->q_vector[i]->napi));
1549
1550         igb_irq_disable(adapter);
1551
1552         del_timer_sync(&adapter->watchdog_timer);
1553         del_timer_sync(&adapter->phy_info_timer);
1554
1555         netif_carrier_off(netdev);
1556
1557         /* record the stats before reset*/
1558         spin_lock(&adapter->stats64_lock);
1559         igb_update_stats(adapter, &adapter->stats64);
1560         spin_unlock(&adapter->stats64_lock);
1561
1562         adapter->link_speed = 0;
1563         adapter->link_duplex = 0;
1564
1565         if (!pci_channel_offline(adapter->pdev))
1566                 igb_reset(adapter);
1567         igb_clean_all_tx_rings(adapter);
1568         igb_clean_all_rx_rings(adapter);
1569 #ifdef CONFIG_IGB_DCA
1570
1571         /* since we reset the hardware DCA settings were cleared */
1572         igb_setup_dca(adapter);
1573 #endif
1574 }
1575
1576 void igb_reinit_locked(struct igb_adapter *adapter)
1577 {
1578         WARN_ON(in_interrupt());
1579         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1580                 msleep(1);
1581         igb_down(adapter);
1582         igb_up(adapter);
1583         clear_bit(__IGB_RESETTING, &adapter->state);
1584 }
1585
1586 void igb_reset(struct igb_adapter *adapter)
1587 {
1588         struct pci_dev *pdev = adapter->pdev;
1589         struct e1000_hw *hw = &adapter->hw;
1590         struct e1000_mac_info *mac = &hw->mac;
1591         struct e1000_fc_info *fc = &hw->fc;
1592         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1593         u16 hwm;
1594
1595         /* Repartition Pba for greater than 9k mtu
1596          * To take effect CTRL.RST is required.
1597          */
1598         switch (mac->type) {
1599         case e1000_i350:
1600         case e1000_82580:
1601                 pba = rd32(E1000_RXPBS);
1602                 pba = igb_rxpbs_adjust_82580(pba);
1603                 break;
1604         case e1000_82576:
1605                 pba = rd32(E1000_RXPBS);
1606                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1607                 break;
1608         case e1000_82575:
1609         case e1000_i210:
1610         case e1000_i211:
1611         default:
1612                 pba = E1000_PBA_34K;
1613                 break;
1614         }
1615
1616         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1617             (mac->type < e1000_82576)) {
1618                 /* adjust PBA for jumbo frames */
1619                 wr32(E1000_PBA, pba);
1620
1621                 /* To maintain wire speed transmits, the Tx FIFO should be
1622                  * large enough to accommodate two full transmit packets,
1623                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1624                  * the Rx FIFO should be large enough to accommodate at least
1625                  * one full receive packet and is similarly rounded up and
1626                  * expressed in KB. */
1627                 pba = rd32(E1000_PBA);
1628                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1629                 tx_space = pba >> 16;
1630                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1631                 pba &= 0xffff;
1632                 /* the tx fifo also stores 16 bytes of information about the tx
1633                  * but don't include ethernet FCS because hardware appends it */
1634                 min_tx_space = (adapter->max_frame_size +
1635                                 sizeof(union e1000_adv_tx_desc) -
1636                                 ETH_FCS_LEN) * 2;
1637                 min_tx_space = ALIGN(min_tx_space, 1024);
1638                 min_tx_space >>= 10;
1639                 /* software strips receive CRC, so leave room for it */
1640                 min_rx_space = adapter->max_frame_size;
1641                 min_rx_space = ALIGN(min_rx_space, 1024);
1642                 min_rx_space >>= 10;
1643
1644                 /* If current Tx allocation is less than the min Tx FIFO size,
1645                  * and the min Tx FIFO size is less than the current Rx FIFO
1646                  * allocation, take space away from current Rx allocation */
1647                 if (tx_space < min_tx_space &&
1648                     ((min_tx_space - tx_space) < pba)) {
1649                         pba = pba - (min_tx_space - tx_space);
1650
1651                         /* if short on rx space, rx wins and must trump tx
1652                          * adjustment */
1653                         if (pba < min_rx_space)
1654                                 pba = min_rx_space;
1655                 }
1656                 wr32(E1000_PBA, pba);
1657         }
1658
1659         /* flow control settings */
1660         /* The high water mark must be low enough to fit one full frame
1661          * (or the size used for early receive) above it in the Rx FIFO.
1662          * Set it to the lower of:
1663          * - 90% of the Rx FIFO size, or
1664          * - the full Rx FIFO size minus one full frame */
1665         hwm = min(((pba << 10) * 9 / 10),
1666                         ((pba << 10) - 2 * adapter->max_frame_size));
1667
1668         fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
1669         fc->low_water = fc->high_water - 16;
1670         fc->pause_time = 0xFFFF;
1671         fc->send_xon = 1;
1672         fc->current_mode = fc->requested_mode;
1673
1674         /* disable receive for all VFs and wait one second */
1675         if (adapter->vfs_allocated_count) {
1676                 int i;
1677                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1678                         adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1679
1680                 /* ping all the active vfs to let them know we are going down */
1681                 igb_ping_all_vfs(adapter);
1682
1683                 /* disable transmits and receives */
1684                 wr32(E1000_VFRE, 0);
1685                 wr32(E1000_VFTE, 0);
1686         }
1687
1688         /* Allow time for pending master requests to run */
1689         hw->mac.ops.reset_hw(hw);
1690         wr32(E1000_WUC, 0);
1691
1692         if (hw->mac.ops.init_hw(hw))
1693                 dev_err(&pdev->dev, "Hardware Error\n");
1694
1695         /*
1696          * Flow control settings reset on hardware reset, so guarantee flow
1697          * control is off when forcing speed.
1698          */
1699         if (!hw->mac.autoneg)
1700                 igb_force_mac_fc(hw);
1701
1702         igb_init_dmac(adapter, pba);
1703         if (!netif_running(adapter->netdev))
1704                 igb_power_down_link(adapter);
1705
1706         igb_update_mng_vlan(adapter);
1707
1708         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1709         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1710
1711         /* Re-enable PTP, where applicable. */
1712         igb_ptp_reset(adapter);
1713
1714         igb_get_phy_info(hw);
1715 }
1716
1717 static netdev_features_t igb_fix_features(struct net_device *netdev,
1718         netdev_features_t features)
1719 {
1720         /*
1721          * Since there is no support for separate rx/tx vlan accel
1722          * enable/disable make sure tx flag is always in same state as rx.
1723          */
1724         if (features & NETIF_F_HW_VLAN_RX)
1725                 features |= NETIF_F_HW_VLAN_TX;
1726         else
1727                 features &= ~NETIF_F_HW_VLAN_TX;
1728
1729         return features;
1730 }
1731
1732 static int igb_set_features(struct net_device *netdev,
1733         netdev_features_t features)
1734 {
1735         netdev_features_t changed = netdev->features ^ features;
1736         struct igb_adapter *adapter = netdev_priv(netdev);
1737
1738         if (changed & NETIF_F_HW_VLAN_RX)
1739                 igb_vlan_mode(netdev, features);
1740
1741         if (!(changed & NETIF_F_RXALL))
1742                 return 0;
1743
1744         netdev->features = features;
1745
1746         if (netif_running(netdev))
1747                 igb_reinit_locked(adapter);
1748         else
1749                 igb_reset(adapter);
1750
1751         return 0;
1752 }
1753
1754 static const struct net_device_ops igb_netdev_ops = {
1755         .ndo_open               = igb_open,
1756         .ndo_stop               = igb_close,
1757         .ndo_start_xmit         = igb_xmit_frame,
1758         .ndo_get_stats64        = igb_get_stats64,
1759         .ndo_set_rx_mode        = igb_set_rx_mode,
1760         .ndo_set_mac_address    = igb_set_mac,
1761         .ndo_change_mtu         = igb_change_mtu,
1762         .ndo_do_ioctl           = igb_ioctl,
1763         .ndo_tx_timeout         = igb_tx_timeout,
1764         .ndo_validate_addr      = eth_validate_addr,
1765         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1766         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1767         .ndo_set_vf_mac         = igb_ndo_set_vf_mac,
1768         .ndo_set_vf_vlan        = igb_ndo_set_vf_vlan,
1769         .ndo_set_vf_tx_rate     = igb_ndo_set_vf_bw,
1770         .ndo_get_vf_config      = igb_ndo_get_vf_config,
1771 #ifdef CONFIG_NET_POLL_CONTROLLER
1772         .ndo_poll_controller    = igb_netpoll,
1773 #endif
1774         .ndo_fix_features       = igb_fix_features,
1775         .ndo_set_features       = igb_set_features,
1776 };
1777
1778 /**
1779  * igb_set_fw_version - Configure version string for ethtool
1780  * @adapter: adapter struct
1781  *
1782  **/
1783 void igb_set_fw_version(struct igb_adapter *adapter)
1784 {
1785         struct e1000_hw *hw = &adapter->hw;
1786         struct e1000_fw_version fw;
1787
1788         igb_get_fw_version(hw, &fw);
1789
1790         switch (hw->mac.type) {
1791         case e1000_i211:
1792                 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
1793                          "%2d.%2d-%d",
1794                          fw.invm_major, fw.invm_minor, fw.invm_img_type);
1795                 break;
1796
1797         default:
1798                 /* if option is rom valid, display its version too */
1799                 if (fw.or_valid) {
1800                         snprintf(adapter->fw_version,
1801                                  sizeof(adapter->fw_version),
1802                                  "%d.%d, 0x%08x, %d.%d.%d",
1803                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
1804                                  fw.or_major, fw.or_build, fw.or_patch);
1805                 /* no option rom */
1806                 } else {
1807                         snprintf(adapter->fw_version,
1808                                  sizeof(adapter->fw_version),
1809                                  "%d.%d, 0x%08x",
1810                                  fw.eep_major, fw.eep_minor, fw.etrack_id);
1811                 }
1812                 break;
1813         }
1814         return;
1815 }
1816
1817 /**
1818  * igb_probe - Device Initialization Routine
1819  * @pdev: PCI device information struct
1820  * @ent: entry in igb_pci_tbl
1821  *
1822  * Returns 0 on success, negative on failure
1823  *
1824  * igb_probe initializes an adapter identified by a pci_dev structure.
1825  * The OS initialization, configuring of the adapter private structure,
1826  * and a hardware reset occur.
1827  **/
1828 static int __devinit igb_probe(struct pci_dev *pdev,
1829                                const struct pci_device_id *ent)
1830 {
1831         struct net_device *netdev;
1832         struct igb_adapter *adapter;
1833         struct e1000_hw *hw;
1834         u16 eeprom_data = 0;
1835         s32 ret_val;
1836         static int global_quad_port_a; /* global quad port a indication */
1837         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1838         unsigned long mmio_start, mmio_len;
1839         int err, pci_using_dac;
1840         u8 part_str[E1000_PBANUM_LENGTH];
1841
1842         /* Catch broken hardware that put the wrong VF device ID in
1843          * the PCIe SR-IOV capability.
1844          */
1845         if (pdev->is_virtfn) {
1846                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1847                         pci_name(pdev), pdev->vendor, pdev->device);
1848                 return -EINVAL;
1849         }
1850
1851         err = pci_enable_device_mem(pdev);
1852         if (err)
1853                 return err;
1854
1855         pci_using_dac = 0;
1856         err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1857         if (!err) {
1858                 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1859                 if (!err)
1860                         pci_using_dac = 1;
1861         } else {
1862                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1863                 if (err) {
1864                         err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1865                         if (err) {
1866                                 dev_err(&pdev->dev, "No usable DMA "
1867                                         "configuration, aborting\n");
1868                                 goto err_dma;
1869                         }
1870                 }
1871         }
1872
1873         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1874                                            IORESOURCE_MEM),
1875                                            igb_driver_name);
1876         if (err)
1877                 goto err_pci_reg;
1878
1879         pci_enable_pcie_error_reporting(pdev);
1880
1881         pci_set_master(pdev);
1882         pci_save_state(pdev);
1883
1884         err = -ENOMEM;
1885         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1886                                    IGB_MAX_TX_QUEUES);
1887         if (!netdev)
1888                 goto err_alloc_etherdev;
1889
1890         SET_NETDEV_DEV(netdev, &pdev->dev);
1891
1892         pci_set_drvdata(pdev, netdev);
1893         adapter = netdev_priv(netdev);
1894         adapter->netdev = netdev;
1895         adapter->pdev = pdev;
1896         hw = &adapter->hw;
1897         hw->back = adapter;
1898         adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1899
1900         mmio_start = pci_resource_start(pdev, 0);
1901         mmio_len = pci_resource_len(pdev, 0);
1902
1903         err = -EIO;
1904         hw->hw_addr = ioremap(mmio_start, mmio_len);
1905         if (!hw->hw_addr)
1906                 goto err_ioremap;
1907
1908         netdev->netdev_ops = &igb_netdev_ops;
1909         igb_set_ethtool_ops(netdev);
1910         netdev->watchdog_timeo = 5 * HZ;
1911
1912         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1913
1914         netdev->mem_start = mmio_start;
1915         netdev->mem_end = mmio_start + mmio_len;
1916
1917         /* PCI config space info */
1918         hw->vendor_id = pdev->vendor;
1919         hw->device_id = pdev->device;
1920         hw->revision_id = pdev->revision;
1921         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1922         hw->subsystem_device_id = pdev->subsystem_device;
1923
1924         /* Copy the default MAC, PHY and NVM function pointers */
1925         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1926         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1927         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1928         /* Initialize skew-specific constants */
1929         err = ei->get_invariants(hw);
1930         if (err)
1931                 goto err_sw_init;
1932
1933         /* setup the private structure */
1934         err = igb_sw_init(adapter);
1935         if (err)
1936                 goto err_sw_init;
1937
1938         igb_get_bus_info_pcie(hw);
1939
1940         hw->phy.autoneg_wait_to_complete = false;
1941
1942         /* Copper options */
1943         if (hw->phy.media_type == e1000_media_type_copper) {
1944                 hw->phy.mdix = AUTO_ALL_MODES;
1945                 hw->phy.disable_polarity_correction = false;
1946                 hw->phy.ms_type = e1000_ms_hw_default;
1947         }
1948
1949         if (igb_check_reset_block(hw))
1950                 dev_info(&pdev->dev,
1951                         "PHY reset is blocked due to SOL/IDER session.\n");
1952
1953         /*
1954          * features is initialized to 0 in allocation, it might have bits
1955          * set by igb_sw_init so we should use an or instead of an
1956          * assignment.
1957          */
1958         netdev->features |= NETIF_F_SG |
1959                             NETIF_F_IP_CSUM |
1960                             NETIF_F_IPV6_CSUM |
1961                             NETIF_F_TSO |
1962                             NETIF_F_TSO6 |
1963                             NETIF_F_RXHASH |
1964                             NETIF_F_RXCSUM |
1965                             NETIF_F_HW_VLAN_RX |
1966                             NETIF_F_HW_VLAN_TX;
1967
1968         /* copy netdev features into list of user selectable features */
1969         netdev->hw_features |= netdev->features;
1970         netdev->hw_features |= NETIF_F_RXALL;
1971
1972         /* set this bit last since it cannot be part of hw_features */
1973         netdev->features |= NETIF_F_HW_VLAN_FILTER;
1974
1975         netdev->vlan_features |= NETIF_F_TSO |
1976                                  NETIF_F_TSO6 |
1977                                  NETIF_F_IP_CSUM |
1978                                  NETIF_F_IPV6_CSUM |
1979                                  NETIF_F_SG;
1980
1981         netdev->priv_flags |= IFF_SUPP_NOFCS;
1982
1983         if (pci_using_dac) {
1984                 netdev->features |= NETIF_F_HIGHDMA;
1985                 netdev->vlan_features |= NETIF_F_HIGHDMA;
1986         }
1987
1988         if (hw->mac.type >= e1000_82576) {
1989                 netdev->hw_features |= NETIF_F_SCTP_CSUM;
1990                 netdev->features |= NETIF_F_SCTP_CSUM;
1991         }
1992
1993         netdev->priv_flags |= IFF_UNICAST_FLT;
1994
1995         adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
1996
1997         /* before reading the NVM, reset the controller to put the device in a
1998          * known good starting state */
1999         hw->mac.ops.reset_hw(hw);
2000
2001         /*
2002          * make sure the NVM is good , i211 parts have special NVM that
2003          * doesn't contain a checksum
2004          */
2005         if (hw->mac.type != e1000_i211) {
2006                 if (hw->nvm.ops.validate(hw) < 0) {
2007                         dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2008                         err = -EIO;
2009                         goto err_eeprom;
2010                 }
2011         }
2012
2013         /* copy the MAC address out of the NVM */
2014         if (hw->mac.ops.read_mac_addr(hw))
2015                 dev_err(&pdev->dev, "NVM Read Error\n");
2016
2017         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2018         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
2019
2020         if (!is_valid_ether_addr(netdev->perm_addr)) {
2021                 dev_err(&pdev->dev, "Invalid MAC Address\n");
2022                 err = -EIO;
2023                 goto err_eeprom;
2024         }
2025
2026         /* get firmware version for ethtool -i */
2027         igb_set_fw_version(adapter);
2028
2029         setup_timer(&adapter->watchdog_timer, igb_watchdog,
2030                     (unsigned long) adapter);
2031         setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2032                     (unsigned long) adapter);
2033
2034         INIT_WORK(&adapter->reset_task, igb_reset_task);
2035         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2036
2037         /* Initialize link properties that are user-changeable */
2038         adapter->fc_autoneg = true;
2039         hw->mac.autoneg = true;
2040         hw->phy.autoneg_advertised = 0x2f;
2041
2042         hw->fc.requested_mode = e1000_fc_default;
2043         hw->fc.current_mode = e1000_fc_default;
2044
2045         igb_validate_mdi_setting(hw);
2046
2047         /* By default, support wake on port A */
2048         if (hw->bus.func == 0)
2049                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2050
2051         /* Check the NVM for wake support on non-port A ports */
2052         if (hw->mac.type >= e1000_82580)
2053                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2054                                  NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2055                                  &eeprom_data);
2056         else if (hw->bus.func == 1)
2057                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2058
2059         if (eeprom_data & IGB_EEPROM_APME)
2060                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2061
2062         /* now that we have the eeprom settings, apply the special cases where
2063          * the eeprom may be wrong or the board simply won't support wake on
2064          * lan on a particular port */
2065         switch (pdev->device) {
2066         case E1000_DEV_ID_82575GB_QUAD_COPPER:
2067                 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2068                 break;
2069         case E1000_DEV_ID_82575EB_FIBER_SERDES:
2070         case E1000_DEV_ID_82576_FIBER:
2071         case E1000_DEV_ID_82576_SERDES:
2072                 /* Wake events only supported on port A for dual fiber
2073                  * regardless of eeprom setting */
2074                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2075                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2076                 break;
2077         case E1000_DEV_ID_82576_QUAD_COPPER:
2078         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2079                 /* if quad port adapter, disable WoL on all but port A */
2080                 if (global_quad_port_a != 0)
2081                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2082                 else
2083                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2084                 /* Reset for multiple quad port adapters */
2085                 if (++global_quad_port_a == 4)
2086                         global_quad_port_a = 0;
2087                 break;
2088         default:
2089                 /* If the device can't wake, don't set software support */
2090                 if (!device_can_wakeup(&adapter->pdev->dev))
2091                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2092         }
2093
2094         /* initialize the wol settings based on the eeprom settings */
2095         if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2096                 adapter->wol |= E1000_WUFC_MAG;
2097
2098         /* Some vendors want WoL disabled by default, but still supported */
2099         if ((hw->mac.type == e1000_i350) &&
2100             (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2101                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2102                 adapter->wol = 0;
2103         }
2104
2105         device_set_wakeup_enable(&adapter->pdev->dev,
2106                                  adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2107
2108         /* reset the hardware with the new settings */
2109         igb_reset(adapter);
2110
2111         /* let the f/w know that the h/w is now under the control of the
2112          * driver. */
2113         igb_get_hw_control(adapter);
2114
2115         strcpy(netdev->name, "eth%d");
2116         err = register_netdev(netdev);
2117         if (err)
2118                 goto err_register;
2119
2120         /* carrier off reporting is important to ethtool even BEFORE open */
2121         netif_carrier_off(netdev);
2122
2123 #ifdef CONFIG_IGB_DCA
2124         if (dca_add_requester(&pdev->dev) == 0) {
2125                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2126                 dev_info(&pdev->dev, "DCA enabled\n");
2127                 igb_setup_dca(adapter);
2128         }
2129
2130 #endif
2131
2132         /* do hw tstamp init after resetting */
2133         igb_ptp_init(adapter);
2134
2135         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2136         /* print bus type/speed/width info */
2137         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2138                  netdev->name,
2139                  ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2140                   (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2141                                                             "unknown"),
2142                  ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2143                   (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2144                   (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2145                    "unknown"),
2146                  netdev->dev_addr);
2147
2148         ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2149         if (ret_val)
2150                 strcpy(part_str, "Unknown");
2151         dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2152         dev_info(&pdev->dev,
2153                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2154                 adapter->msix_entries ? "MSI-X" :
2155                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2156                 adapter->num_rx_queues, adapter->num_tx_queues);
2157         switch (hw->mac.type) {
2158         case e1000_i350:
2159         case e1000_i210:
2160         case e1000_i211:
2161                 igb_set_eee_i350(hw);
2162                 break;
2163         default:
2164                 break;
2165         }
2166
2167         pm_runtime_put_noidle(&pdev->dev);
2168         return 0;
2169
2170 err_register:
2171         igb_release_hw_control(adapter);
2172 err_eeprom:
2173         if (!igb_check_reset_block(hw))
2174                 igb_reset_phy(hw);
2175
2176         if (hw->flash_address)
2177                 iounmap(hw->flash_address);
2178 err_sw_init:
2179         igb_clear_interrupt_scheme(adapter);
2180         iounmap(hw->hw_addr);
2181 err_ioremap:
2182         free_netdev(netdev);
2183 err_alloc_etherdev:
2184         pci_release_selected_regions(pdev,
2185                                      pci_select_bars(pdev, IORESOURCE_MEM));
2186 err_pci_reg:
2187 err_dma:
2188         pci_disable_device(pdev);
2189         return err;
2190 }
2191
2192 /**
2193  * igb_remove - Device Removal Routine
2194  * @pdev: PCI device information struct
2195  *
2196  * igb_remove is called by the PCI subsystem to alert the driver
2197  * that it should release a PCI device.  The could be caused by a
2198  * Hot-Plug event, or because the driver is going to be removed from
2199  * memory.
2200  **/
2201 static void __devexit igb_remove(struct pci_dev *pdev)
2202 {
2203         struct net_device *netdev = pci_get_drvdata(pdev);
2204         struct igb_adapter *adapter = netdev_priv(netdev);
2205         struct e1000_hw *hw = &adapter->hw;
2206
2207         pm_runtime_get_noresume(&pdev->dev);
2208         igb_ptp_stop(adapter);
2209
2210         /*
2211          * The watchdog timer may be rescheduled, so explicitly
2212          * disable watchdog from being rescheduled.
2213          */
2214         set_bit(__IGB_DOWN, &adapter->state);
2215         del_timer_sync(&adapter->watchdog_timer);
2216         del_timer_sync(&adapter->phy_info_timer);
2217
2218         cancel_work_sync(&adapter->reset_task);
2219         cancel_work_sync(&adapter->watchdog_task);
2220
2221 #ifdef CONFIG_IGB_DCA
2222         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2223                 dev_info(&pdev->dev, "DCA disabled\n");
2224                 dca_remove_requester(&pdev->dev);
2225                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2226                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2227         }
2228 #endif
2229
2230         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
2231          * would have already happened in close and is redundant. */
2232         igb_release_hw_control(adapter);
2233
2234         unregister_netdev(netdev);
2235
2236         igb_clear_interrupt_scheme(adapter);
2237
2238 #ifdef CONFIG_PCI_IOV
2239         /* reclaim resources allocated to VFs */
2240         if (adapter->vf_data) {
2241                 /* disable iov and allow time for transactions to clear */
2242                 if (igb_vfs_are_assigned(adapter)) {
2243                         dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n");
2244                 } else {
2245                         pci_disable_sriov(pdev);
2246                         msleep(500);
2247                 }
2248
2249                 kfree(adapter->vf_data);
2250                 adapter->vf_data = NULL;
2251                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2252                 wrfl();
2253                 msleep(100);
2254                 dev_info(&pdev->dev, "IOV Disabled\n");
2255         }
2256 #endif
2257
2258         iounmap(hw->hw_addr);
2259         if (hw->flash_address)
2260                 iounmap(hw->flash_address);
2261         pci_release_selected_regions(pdev,
2262                                      pci_select_bars(pdev, IORESOURCE_MEM));
2263
2264         kfree(adapter->shadow_vfta);
2265         free_netdev(netdev);
2266
2267         pci_disable_pcie_error_reporting(pdev);
2268
2269         pci_disable_device(pdev);
2270 }
2271
2272 /**
2273  * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2274  * @adapter: board private structure to initialize
2275  *
2276  * This function initializes the vf specific data storage and then attempts to
2277  * allocate the VFs.  The reason for ordering it this way is because it is much
2278  * mor expensive time wise to disable SR-IOV than it is to allocate and free
2279  * the memory for the VFs.
2280  **/
2281 static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2282 {
2283 #ifdef CONFIG_PCI_IOV
2284         struct pci_dev *pdev = adapter->pdev;
2285         struct e1000_hw *hw = &adapter->hw;
2286         int old_vfs = pci_num_vf(adapter->pdev);
2287         int i;
2288
2289         /* Virtualization features not supported on i210 family. */
2290         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2291                 return;
2292
2293         if (old_vfs) {
2294                 dev_info(&pdev->dev, "%d pre-allocated VFs found - override "
2295                          "max_vfs setting of %d\n", old_vfs, max_vfs);
2296                 adapter->vfs_allocated_count = old_vfs;
2297         }
2298
2299         if (!adapter->vfs_allocated_count)
2300                 return;
2301
2302         adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2303                                 sizeof(struct vf_data_storage), GFP_KERNEL);
2304
2305         /* if allocation failed then we do not support SR-IOV */
2306         if (!adapter->vf_data) {
2307                 adapter->vfs_allocated_count = 0;
2308                 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2309                         "Data Storage\n");
2310                 goto out;
2311         }
2312
2313         if (!old_vfs) {
2314                 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count))
2315                         goto err_out;
2316         }
2317         dev_info(&pdev->dev, "%d VFs allocated\n",
2318                  adapter->vfs_allocated_count);
2319         for (i = 0; i < adapter->vfs_allocated_count; i++)
2320                 igb_vf_configure(adapter, i);
2321
2322         /* DMA Coalescing is not supported in IOV mode. */
2323         adapter->flags &= ~IGB_FLAG_DMAC;
2324         goto out;
2325 err_out:
2326         kfree(adapter->vf_data);
2327         adapter->vf_data = NULL;
2328         adapter->vfs_allocated_count = 0;
2329 out:
2330         return;
2331 #endif /* CONFIG_PCI_IOV */
2332 }
2333
2334 /**
2335  * igb_sw_init - Initialize general software structures (struct igb_adapter)
2336  * @adapter: board private structure to initialize
2337  *
2338  * igb_sw_init initializes the Adapter private data structure.
2339  * Fields are initialized based on PCI device information and
2340  * OS network device settings (MTU size).
2341  **/
2342 static int __devinit igb_sw_init(struct igb_adapter *adapter)
2343 {
2344         struct e1000_hw *hw = &adapter->hw;
2345         struct net_device *netdev = adapter->netdev;
2346         struct pci_dev *pdev = adapter->pdev;
2347         u32 max_rss_queues;
2348
2349         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2350
2351         /* set default ring sizes */
2352         adapter->tx_ring_count = IGB_DEFAULT_TXD;
2353         adapter->rx_ring_count = IGB_DEFAULT_RXD;
2354
2355         /* set default ITR values */
2356         adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2357         adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2358
2359         /* set default work limits */
2360         adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2361
2362         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2363                                   VLAN_HLEN;
2364         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2365
2366         spin_lock_init(&adapter->stats64_lock);
2367 #ifdef CONFIG_PCI_IOV
2368         switch (hw->mac.type) {
2369         case e1000_82576:
2370         case e1000_i350:
2371                 if (max_vfs > 7) {
2372                         dev_warn(&pdev->dev,
2373                                  "Maximum of 7 VFs per PF, using max\n");
2374                         adapter->vfs_allocated_count = 7;
2375                 } else
2376                         adapter->vfs_allocated_count = max_vfs;
2377                 break;
2378         default:
2379                 break;
2380         }
2381 #endif /* CONFIG_PCI_IOV */
2382
2383         /* Determine the maximum number of RSS queues supported. */
2384         switch (hw->mac.type) {
2385         case e1000_i211:
2386                 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2387                 break;
2388         case e1000_82575:
2389         case e1000_i210:
2390                 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2391                 break;
2392         case e1000_i350:
2393                 /* I350 cannot do RSS and SR-IOV at the same time */
2394                 if (!!adapter->vfs_allocated_count) {
2395                         max_rss_queues = 1;
2396                         break;
2397                 }
2398                 /* fall through */
2399         case e1000_82576:
2400                 if (!!adapter->vfs_allocated_count) {
2401                         max_rss_queues = 2;
2402                         break;
2403                 }
2404                 /* fall through */
2405         case e1000_82580:
2406         default:
2407                 max_rss_queues = IGB_MAX_RX_QUEUES;
2408                 break;
2409         }
2410
2411         adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2412
2413         /* Determine if we need to pair queues. */
2414         switch (hw->mac.type) {
2415         case e1000_82575:
2416         case e1000_i211:
2417                 /* Device supports enough interrupts without queue pairing. */
2418                 break;
2419         case e1000_82576:
2420                 /*
2421                  * If VFs are going to be allocated with RSS queues then we
2422                  * should pair the queues in order to conserve interrupts due
2423                  * to limited supply.
2424                  */
2425                 if ((adapter->rss_queues > 1) &&
2426                     (adapter->vfs_allocated_count > 6))
2427                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2428                 /* fall through */
2429         case e1000_82580:
2430         case e1000_i350:
2431         case e1000_i210:
2432         default:
2433                 /*
2434                  * If rss_queues > half of max_rss_queues, pair the queues in
2435                  * order to conserve interrupts due to limited supply.
2436                  */
2437                 if (adapter->rss_queues > (max_rss_queues / 2))
2438                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2439                 break;
2440         }
2441
2442         /* Setup and initialize a copy of the hw vlan table array */
2443         adapter->shadow_vfta = kzalloc(sizeof(u32) *
2444                                 E1000_VLAN_FILTER_TBL_SIZE,
2445                                 GFP_ATOMIC);
2446
2447         /* This call may decrease the number of queues */
2448         if (igb_init_interrupt_scheme(adapter)) {
2449                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2450                 return -ENOMEM;
2451         }
2452
2453         igb_probe_vfs(adapter);
2454
2455         /* Explicitly disable IRQ since the NIC can be in any state. */
2456         igb_irq_disable(adapter);
2457
2458         if (hw->mac.type >= e1000_i350)
2459                 adapter->flags &= ~IGB_FLAG_DMAC;
2460
2461         set_bit(__IGB_DOWN, &adapter->state);
2462         return 0;
2463 }
2464
2465 /**
2466  * igb_open - Called when a network interface is made active
2467  * @netdev: network interface device structure
2468  *
2469  * Returns 0 on success, negative value on failure
2470  *
2471  * The open entry point is called when a network interface is made
2472  * active by the system (IFF_UP).  At this point all resources needed
2473  * for transmit and receive operations are allocated, the interrupt
2474  * handler is registered with the OS, the watchdog timer is started,
2475  * and the stack is notified that the interface is ready.
2476  **/
2477 static int __igb_open(struct net_device *netdev, bool resuming)
2478 {
2479         struct igb_adapter *adapter = netdev_priv(netdev);
2480         struct e1000_hw *hw = &adapter->hw;
2481         struct pci_dev *pdev = adapter->pdev;
2482         int err;
2483         int i;
2484
2485         /* disallow open during test */
2486         if (test_bit(__IGB_TESTING, &adapter->state)) {
2487                 WARN_ON(resuming);
2488                 return -EBUSY;
2489         }
2490
2491         if (!resuming)
2492                 pm_runtime_get_sync(&pdev->dev);
2493
2494         netif_carrier_off(netdev);
2495
2496         /* allocate transmit descriptors */
2497         err = igb_setup_all_tx_resources(adapter);
2498         if (err)
2499                 goto err_setup_tx;
2500
2501         /* allocate receive descriptors */
2502         err = igb_setup_all_rx_resources(adapter);
2503         if (err)
2504                 goto err_setup_rx;
2505
2506         igb_power_up_link(adapter);
2507
2508         /* before we allocate an interrupt, we must be ready to handle it.
2509          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2510          * as soon as we call pci_request_irq, so we have to setup our
2511          * clean_rx handler before we do so.  */
2512         igb_configure(adapter);
2513
2514         err = igb_request_irq(adapter);
2515         if (err)
2516                 goto err_req_irq;
2517
2518         /* Notify the stack of the actual queue counts. */
2519         err = netif_set_real_num_tx_queues(adapter->netdev,
2520                                            adapter->num_tx_queues);
2521         if (err)
2522                 goto err_set_queues;
2523
2524         err = netif_set_real_num_rx_queues(adapter->netdev,
2525                                            adapter->num_rx_queues);
2526         if (err)
2527                 goto err_set_queues;
2528
2529         /* From here on the code is the same as igb_up() */
2530         clear_bit(__IGB_DOWN, &adapter->state);
2531
2532         for (i = 0; i < adapter->num_q_vectors; i++)
2533                 napi_enable(&(adapter->q_vector[i]->napi));
2534
2535         /* Clear any pending interrupts. */
2536         rd32(E1000_ICR);
2537
2538         igb_irq_enable(adapter);
2539
2540         /* notify VFs that reset has been completed */
2541         if (adapter->vfs_allocated_count) {
2542                 u32 reg_data = rd32(E1000_CTRL_EXT);
2543                 reg_data |= E1000_CTRL_EXT_PFRSTD;
2544                 wr32(E1000_CTRL_EXT, reg_data);
2545         }
2546
2547         netif_tx_start_all_queues(netdev);
2548
2549         if (!resuming)
2550                 pm_runtime_put(&pdev->dev);
2551
2552         /* start the watchdog. */
2553         hw->mac.get_link_status = 1;
2554         schedule_work(&adapter->watchdog_task);
2555
2556         return 0;
2557
2558 err_set_queues:
2559         igb_free_irq(adapter);
2560 err_req_irq:
2561         igb_release_hw_control(adapter);
2562         igb_power_down_link(adapter);
2563         igb_free_all_rx_resources(adapter);
2564 err_setup_rx:
2565         igb_free_all_tx_resources(adapter);
2566 err_setup_tx:
2567         igb_reset(adapter);
2568         if (!resuming)
2569                 pm_runtime_put(&pdev->dev);
2570
2571         return err;
2572 }
2573
2574 static int igb_open(struct net_device *netdev)
2575 {
2576         return __igb_open(netdev, false);
2577 }
2578
2579 /**
2580  * igb_close - Disables a network interface
2581  * @netdev: network interface device structure
2582  *
2583  * Returns 0, this is not allowed to fail
2584  *
2585  * The close entry point is called when an interface is de-activated
2586  * by the OS.  The hardware is still under the driver's control, but
2587  * needs to be disabled.  A global MAC reset is issued to stop the
2588  * hardware, and all transmit and receive resources are freed.
2589  **/
2590 static int __igb_close(struct net_device *netdev, bool suspending)
2591 {
2592         struct igb_adapter *adapter = netdev_priv(netdev);
2593         struct pci_dev *pdev = adapter->pdev;
2594
2595         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2596
2597         if (!suspending)
2598                 pm_runtime_get_sync(&pdev->dev);
2599
2600         igb_down(adapter);
2601         igb_free_irq(adapter);
2602
2603         igb_free_all_tx_resources(adapter);
2604         igb_free_all_rx_resources(adapter);
2605
2606         if (!suspending)
2607                 pm_runtime_put_sync(&pdev->dev);
2608         return 0;
2609 }
2610
2611 static int igb_close(struct net_device *netdev)
2612 {
2613         return __igb_close(netdev, false);
2614 }
2615
2616 /**
2617  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2618  * @tx_ring: tx descriptor ring (for a specific queue) to setup
2619  *
2620  * Return 0 on success, negative on failure
2621  **/
2622 int igb_setup_tx_resources(struct igb_ring *tx_ring)
2623 {
2624         struct device *dev = tx_ring->dev;
2625         int size;
2626
2627         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2628
2629         tx_ring->tx_buffer_info = vzalloc(size);
2630         if (!tx_ring->tx_buffer_info)
2631                 goto err;
2632
2633         /* round up to nearest 4K */
2634         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2635         tx_ring->size = ALIGN(tx_ring->size, 4096);
2636
2637         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2638                                            &tx_ring->dma, GFP_KERNEL);
2639         if (!tx_ring->desc)
2640                 goto err;
2641
2642         tx_ring->next_to_use = 0;
2643         tx_ring->next_to_clean = 0;
2644
2645         return 0;
2646
2647 err:
2648         vfree(tx_ring->tx_buffer_info);
2649         tx_ring->tx_buffer_info = NULL;
2650         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2651         return -ENOMEM;
2652 }
2653
2654 /**
2655  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2656  *                                (Descriptors) for all queues
2657  * @adapter: board private structure
2658  *
2659  * Return 0 on success, negative on failure
2660  **/
2661 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2662 {
2663         struct pci_dev *pdev = adapter->pdev;
2664         int i, err = 0;
2665
2666         for (i = 0; i < adapter->num_tx_queues; i++) {
2667                 err = igb_setup_tx_resources(adapter->tx_ring[i]);
2668                 if (err) {
2669                         dev_err(&pdev->dev,
2670                                 "Allocation for Tx Queue %u failed\n", i);
2671                         for (i--; i >= 0; i--)
2672                                 igb_free_tx_resources(adapter->tx_ring[i]);
2673                         break;
2674                 }
2675         }
2676
2677         return err;
2678 }
2679
2680 /**
2681  * igb_setup_tctl - configure the transmit control registers
2682  * @adapter: Board private structure
2683  **/
2684 void igb_setup_tctl(struct igb_adapter *adapter)
2685 {
2686         struct e1000_hw *hw = &adapter->hw;
2687         u32 tctl;
2688
2689         /* disable queue 0 which is enabled by default on 82575 and 82576 */
2690         wr32(E1000_TXDCTL(0), 0);
2691
2692         /* Program the Transmit Control Register */
2693         tctl = rd32(E1000_TCTL);
2694         tctl &= ~E1000_TCTL_CT;
2695         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2696                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2697
2698         igb_config_collision_dist(hw);
2699
2700         /* Enable transmits */
2701         tctl |= E1000_TCTL_EN;
2702
2703         wr32(E1000_TCTL, tctl);
2704 }
2705
2706 /**
2707  * igb_configure_tx_ring - Configure transmit ring after Reset
2708  * @adapter: board private structure
2709  * @ring: tx ring to configure
2710  *
2711  * Configure a transmit ring after a reset.
2712  **/
2713 void igb_configure_tx_ring(struct igb_adapter *adapter,
2714                            struct igb_ring *ring)
2715 {
2716         struct e1000_hw *hw = &adapter->hw;
2717         u32 txdctl = 0;
2718         u64 tdba = ring->dma;
2719         int reg_idx = ring->reg_idx;
2720
2721         /* disable the queue */
2722         wr32(E1000_TXDCTL(reg_idx), 0);
2723         wrfl();
2724         mdelay(10);
2725
2726         wr32(E1000_TDLEN(reg_idx),
2727                         ring->count * sizeof(union e1000_adv_tx_desc));
2728         wr32(E1000_TDBAL(reg_idx),
2729                         tdba & 0x00000000ffffffffULL);
2730         wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2731
2732         ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2733         wr32(E1000_TDH(reg_idx), 0);
2734         writel(0, ring->tail);
2735
2736         txdctl |= IGB_TX_PTHRESH;
2737         txdctl |= IGB_TX_HTHRESH << 8;
2738         txdctl |= IGB_TX_WTHRESH << 16;
2739
2740         txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2741         wr32(E1000_TXDCTL(reg_idx), txdctl);
2742 }
2743
2744 /**
2745  * igb_configure_tx - Configure transmit Unit after Reset
2746  * @adapter: board private structure
2747  *
2748  * Configure the Tx unit of the MAC after a reset.
2749  **/
2750 static void igb_configure_tx(struct igb_adapter *adapter)
2751 {
2752         int i;
2753
2754         for (i = 0; i < adapter->num_tx_queues; i++)
2755                 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
2756 }
2757
2758 /**
2759  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
2760  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
2761  *
2762  * Returns 0 on success, negative on failure
2763  **/
2764 int igb_setup_rx_resources(struct igb_ring *rx_ring)
2765 {
2766         struct device *dev = rx_ring->dev;
2767         int size;
2768
2769         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
2770
2771         rx_ring->rx_buffer_info = vzalloc(size);
2772         if (!rx_ring->rx_buffer_info)
2773                 goto err;
2774
2775         /* Round up to nearest 4K */
2776         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
2777         rx_ring->size = ALIGN(rx_ring->size, 4096);
2778
2779         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2780                                            &rx_ring->dma, GFP_KERNEL);
2781         if (!rx_ring->desc)
2782                 goto err;
2783
2784         rx_ring->next_to_alloc = 0;
2785         rx_ring->next_to_clean = 0;
2786         rx_ring->next_to_use = 0;
2787
2788         return 0;
2789
2790 err:
2791         vfree(rx_ring->rx_buffer_info);
2792         rx_ring->rx_buffer_info = NULL;
2793         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
2794         return -ENOMEM;
2795 }
2796
2797 /**
2798  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2799  *                                (Descriptors) for all queues
2800  * @adapter: board private structure
2801  *
2802  * Return 0 on success, negative on failure
2803  **/
2804 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2805 {
2806         struct pci_dev *pdev = adapter->pdev;
2807         int i, err = 0;
2808
2809         for (i = 0; i < adapter->num_rx_queues; i++) {
2810                 err = igb_setup_rx_resources(adapter->rx_ring[i]);
2811                 if (err) {
2812                         dev_err(&pdev->dev,
2813                                 "Allocation for Rx Queue %u failed\n", i);
2814                         for (i--; i >= 0; i--)
2815                                 igb_free_rx_resources(adapter->rx_ring[i]);
2816                         break;
2817                 }
2818         }
2819
2820         return err;
2821 }
2822
2823 /**
2824  * igb_setup_mrqc - configure the multiple receive queue control registers
2825  * @adapter: Board private structure
2826  **/
2827 static void igb_setup_mrqc(struct igb_adapter *adapter)
2828 {
2829         struct e1000_hw *hw = &adapter->hw;
2830         u32 mrqc, rxcsum;
2831         u32 j, num_rx_queues, shift = 0;
2832         static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
2833                                         0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
2834                                         0xA32DCB77, 0x0CF23080, 0x3BB7426A,
2835                                         0xFA01ACBE };
2836
2837         /* Fill out hash function seeds */
2838         for (j = 0; j < 10; j++)
2839                 wr32(E1000_RSSRK(j), rsskey[j]);
2840
2841         num_rx_queues = adapter->rss_queues;
2842
2843         switch (hw->mac.type) {
2844         case e1000_82575:
2845                 shift = 6;
2846                 break;
2847         case e1000_82576:
2848                 /* 82576 supports 2 RSS queues for SR-IOV */
2849                 if (adapter->vfs_allocated_count) {
2850                         shift = 3;
2851                         num_rx_queues = 2;
2852                 }
2853                 break;
2854         default:
2855                 break;
2856         }
2857
2858         /*
2859          * Populate the indirection table 4 entries at a time.  To do this
2860          * we are generating the results for n and n+2 and then interleaving
2861          * those with the results with n+1 and n+3.
2862          */
2863         for (j = 0; j < 32; j++) {
2864                 /* first pass generates n and n+2 */
2865                 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
2866                 u32 reta = (base & 0x07800780) >> (7 - shift);
2867
2868                 /* second pass generates n+1 and n+3 */
2869                 base += 0x00010001 * num_rx_queues;
2870                 reta |= (base & 0x07800780) << (1 + shift);
2871
2872                 wr32(E1000_RETA(j), reta);
2873         }
2874
2875         /*
2876          * Disable raw packet checksumming so that RSS hash is placed in
2877          * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
2878          * offloads as they are enabled by default
2879          */
2880         rxcsum = rd32(E1000_RXCSUM);
2881         rxcsum |= E1000_RXCSUM_PCSD;
2882
2883         if (adapter->hw.mac.type >= e1000_82576)
2884                 /* Enable Receive Checksum Offload for SCTP */
2885                 rxcsum |= E1000_RXCSUM_CRCOFL;
2886
2887         /* Don't need to set TUOFL or IPOFL, they default to 1 */
2888         wr32(E1000_RXCSUM, rxcsum);
2889
2890         /* Generate RSS hash based on packet types, TCP/UDP
2891          * port numbers and/or IPv4/v6 src and dst addresses
2892          */
2893         mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
2894                E1000_MRQC_RSS_FIELD_IPV4_TCP |
2895                E1000_MRQC_RSS_FIELD_IPV6 |
2896                E1000_MRQC_RSS_FIELD_IPV6_TCP |
2897                E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
2898
2899         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2900                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2901         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2902                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2903
2904         /* If VMDq is enabled then we set the appropriate mode for that, else
2905          * we default to RSS so that an RSS hash is calculated per packet even
2906          * if we are only using one queue */
2907         if (adapter->vfs_allocated_count) {
2908                 if (hw->mac.type > e1000_82575) {
2909                         /* Set the default pool for the PF's first queue */
2910                         u32 vtctl = rd32(E1000_VT_CTL);
2911                         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2912                                    E1000_VT_CTL_DISABLE_DEF_POOL);
2913                         vtctl |= adapter->vfs_allocated_count <<
2914                                 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2915                         wr32(E1000_VT_CTL, vtctl);
2916                 }
2917                 if (adapter->rss_queues > 1)
2918                         mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2919                 else
2920                         mrqc |= E1000_MRQC_ENABLE_VMDQ;
2921         } else {
2922                 if (hw->mac.type != e1000_i211)
2923                         mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
2924         }
2925         igb_vmm_control(adapter);
2926
2927         wr32(E1000_MRQC, mrqc);
2928 }
2929
2930 /**
2931  * igb_setup_rctl - configure the receive control registers
2932  * @adapter: Board private structure
2933  **/
2934 void igb_setup_rctl(struct igb_adapter *adapter)
2935 {
2936         struct e1000_hw *hw = &adapter->hw;
2937         u32 rctl;
2938
2939         rctl = rd32(E1000_RCTL);
2940
2941         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2942         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2943
2944         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2945                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2946
2947         /*
2948          * enable stripping of CRC. It's unlikely this will break BMC
2949          * redirection as it did with e1000. Newer features require
2950          * that the HW strips the CRC.
2951          */
2952         rctl |= E1000_RCTL_SECRC;
2953
2954         /* disable store bad packets and clear size bits. */
2955         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2956
2957         /* enable LPE to prevent packets larger than max_frame_size */
2958         rctl |= E1000_RCTL_LPE;
2959
2960         /* disable queue 0 to prevent tail write w/o re-config */
2961         wr32(E1000_RXDCTL(0), 0);
2962
2963         /* Attention!!!  For SR-IOV PF driver operations you must enable
2964          * queue drop for all VF and PF queues to prevent head of line blocking
2965          * if an un-trusted VF does not provide descriptors to hardware.
2966          */
2967         if (adapter->vfs_allocated_count) {
2968                 /* set all queue drop enable bits */
2969                 wr32(E1000_QDE, ALL_QUEUES);
2970         }
2971
2972         /* This is useful for sniffing bad packets. */
2973         if (adapter->netdev->features & NETIF_F_RXALL) {
2974                 /* UPE and MPE will be handled by normal PROMISC logic
2975                  * in e1000e_set_rx_mode */
2976                 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
2977                          E1000_RCTL_BAM | /* RX All Bcast Pkts */
2978                          E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
2979
2980                 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
2981                           E1000_RCTL_DPF | /* Allow filtered pause */
2982                           E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
2983                 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
2984                  * and that breaks VLANs.
2985                  */
2986         }
2987
2988         wr32(E1000_RCTL, rctl);
2989 }
2990
2991 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2992                                    int vfn)
2993 {
2994         struct e1000_hw *hw = &adapter->hw;
2995         u32 vmolr;
2996
2997         /* if it isn't the PF check to see if VFs are enabled and
2998          * increase the size to support vlan tags */
2999         if (vfn < adapter->vfs_allocated_count &&
3000             adapter->vf_data[vfn].vlans_enabled)
3001                 size += VLAN_TAG_SIZE;
3002
3003         vmolr = rd32(E1000_VMOLR(vfn));
3004         vmolr &= ~E1000_VMOLR_RLPML_MASK;
3005         vmolr |= size | E1000_VMOLR_LPE;
3006         wr32(E1000_VMOLR(vfn), vmolr);
3007
3008         return 0;
3009 }
3010
3011 /**
3012  * igb_rlpml_set - set maximum receive packet size
3013  * @adapter: board private structure
3014  *
3015  * Configure maximum receivable packet size.
3016  **/
3017 static void igb_rlpml_set(struct igb_adapter *adapter)
3018 {
3019         u32 max_frame_size = adapter->max_frame_size;
3020         struct e1000_hw *hw = &adapter->hw;
3021         u16 pf_id = adapter->vfs_allocated_count;
3022
3023         if (pf_id) {
3024                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3025                 /*
3026                  * If we're in VMDQ or SR-IOV mode, then set global RLPML
3027                  * to our max jumbo frame size, in case we need to enable
3028                  * jumbo frames on one of the rings later.
3029                  * This will not pass over-length frames into the default
3030                  * queue because it's gated by the VMOLR.RLPML.
3031                  */
3032                 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3033         }
3034
3035         wr32(E1000_RLPML, max_frame_size);
3036 }
3037
3038 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3039                                  int vfn, bool aupe)
3040 {
3041         struct e1000_hw *hw = &adapter->hw;
3042         u32 vmolr;
3043
3044         /*
3045          * This register exists only on 82576 and newer so if we are older then
3046          * we should exit and do nothing
3047          */
3048         if (hw->mac.type < e1000_82576)
3049                 return;
3050
3051         vmolr = rd32(E1000_VMOLR(vfn));
3052         vmolr |= E1000_VMOLR_STRVLAN;      /* Strip vlan tags */
3053         if (aupe)
3054                 vmolr |= E1000_VMOLR_AUPE;        /* Accept untagged packets */
3055         else
3056                 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3057
3058         /* clear all bits that might not be set */
3059         vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3060
3061         if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3062                 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3063         /*
3064          * for VMDq only allow the VFs and pool 0 to accept broadcast and
3065          * multicast packets
3066          */
3067         if (vfn <= adapter->vfs_allocated_count)
3068                 vmolr |= E1000_VMOLR_BAM;          /* Accept broadcast */
3069
3070         wr32(E1000_VMOLR(vfn), vmolr);
3071 }
3072
3073 /**
3074  * igb_configure_rx_ring - Configure a receive ring after Reset
3075  * @adapter: board private structure
3076  * @ring: receive ring to be configured
3077  *
3078  * Configure the Rx unit of the MAC after a reset.
3079  **/
3080 void igb_configure_rx_ring(struct igb_adapter *adapter,
3081                            struct igb_ring *ring)
3082 {
3083         struct e1000_hw *hw = &adapter->hw;
3084         u64 rdba = ring->dma;
3085         int reg_idx = ring->reg_idx;
3086         u32 srrctl = 0, rxdctl = 0;
3087
3088         /* disable the queue */
3089         wr32(E1000_RXDCTL(reg_idx), 0);
3090
3091         /* Set DMA base address registers */
3092         wr32(E1000_RDBAL(reg_idx),
3093              rdba & 0x00000000ffffffffULL);
3094         wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3095         wr32(E1000_RDLEN(reg_idx),
3096                        ring->count * sizeof(union e1000_adv_rx_desc));
3097
3098         /* initialize head and tail */
3099         ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3100         wr32(E1000_RDH(reg_idx), 0);
3101         writel(0, ring->tail);
3102
3103         /* set descriptor configuration */
3104         srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3105         srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3106         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3107         if (hw->mac.type >= e1000_82580)
3108                 srrctl |= E1000_SRRCTL_TIMESTAMP;
3109         /* Only set Drop Enable if we are supporting multiple queues */
3110         if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3111                 srrctl |= E1000_SRRCTL_DROP_EN;
3112
3113         wr32(E1000_SRRCTL(reg_idx), srrctl);
3114
3115         /* set filtering for VMDQ pools */
3116         igb_set_vmolr(adapter, reg_idx & 0x7, true);
3117
3118         rxdctl |= IGB_RX_PTHRESH;
3119         rxdctl |= IGB_RX_HTHRESH << 8;
3120         rxdctl |= IGB_RX_WTHRESH << 16;
3121
3122         /* enable receive descriptor fetching */
3123         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3124         wr32(E1000_RXDCTL(reg_idx), rxdctl);
3125 }
3126
3127 /**
3128  * igb_configure_rx - Configure receive Unit after Reset
3129  * @adapter: board private structure
3130  *
3131  * Configure the Rx unit of the MAC after a reset.
3132  **/
3133 static void igb_configure_rx(struct igb_adapter *adapter)
3134 {
3135         int i;
3136
3137         /* set UTA to appropriate mode */
3138         igb_set_uta(adapter);
3139
3140         /* set the correct pool for the PF default MAC address in entry 0 */
3141         igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3142                          adapter->vfs_allocated_count);
3143
3144         /* Setup the HW Rx Head and Tail Descriptor Pointers and
3145          * the Base and Length of the Rx Descriptor Ring */
3146         for (i = 0; i < adapter->num_rx_queues; i++)
3147                 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3148 }
3149
3150 /**
3151  * igb_free_tx_resources - Free Tx Resources per Queue
3152  * @tx_ring: Tx descriptor ring for a specific queue
3153  *
3154  * Free all transmit software resources
3155  **/
3156 void igb_free_tx_resources(struct igb_ring *tx_ring)
3157 {
3158         igb_clean_tx_ring(tx_ring);
3159
3160         vfree(tx_ring->tx_buffer_info);
3161         tx_ring->tx_buffer_info = NULL;
3162
3163         /* if not set, then don't free */
3164         if (!tx_ring->desc)
3165                 return;
3166
3167         dma_free_coherent(tx_ring->dev, tx_ring->size,
3168                           tx_ring->desc, tx_ring->dma);
3169
3170         tx_ring->desc = NULL;
3171 }
3172
3173 /**
3174  * igb_free_all_tx_resources - Free Tx Resources for All Queues
3175  * @adapter: board private structure
3176  *
3177  * Free all transmit software resources
3178  **/
3179 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3180 {
3181         int i;
3182
3183         for (i = 0; i < adapter->num_tx_queues; i++)
3184                 igb_free_tx_resources(adapter->tx_ring[i]);
3185 }
3186
3187 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3188                                     struct igb_tx_buffer *tx_buffer)
3189 {
3190         if (tx_buffer->skb) {
3191                 dev_kfree_skb_any(tx_buffer->skb);
3192                 if (dma_unmap_len(tx_buffer, len))
3193                         dma_unmap_single(ring->dev,
3194                                          dma_unmap_addr(tx_buffer, dma),
3195                                          dma_unmap_len(tx_buffer, len),
3196                                          DMA_TO_DEVICE);
3197         } else if (dma_unmap_len(tx_buffer, len)) {
3198                 dma_unmap_page(ring->dev,
3199                                dma_unmap_addr(tx_buffer, dma),
3200                                dma_unmap_len(tx_buffer, len),
3201                                DMA_TO_DEVICE);
3202         }
3203         tx_buffer->next_to_watch = NULL;
3204         tx_buffer->skb = NULL;
3205         dma_unmap_len_set(tx_buffer, len, 0);
3206         /* buffer_info must be completely set up in the transmit path */
3207 }
3208
3209 /**
3210  * igb_clean_tx_ring - Free Tx Buffers
3211  * @tx_ring: ring to be cleaned
3212  **/
3213 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3214 {
3215         struct igb_tx_buffer *buffer_info;
3216         unsigned long size;
3217         u16 i;
3218
3219         if (!tx_ring->tx_buffer_info)
3220                 return;
3221         /* Free all the Tx ring sk_buffs */
3222
3223         for (i = 0; i < tx_ring->count; i++) {
3224                 buffer_info = &tx_ring->tx_buffer_info[i];
3225                 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3226         }
3227
3228         netdev_tx_reset_queue(txring_txq(tx_ring));
3229
3230         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3231         memset(tx_ring->tx_buffer_info, 0, size);
3232
3233         /* Zero out the descriptor ring */
3234         memset(tx_ring->desc, 0, tx_ring->size);
3235
3236         tx_ring->next_to_use = 0;
3237         tx_ring->next_to_clean = 0;
3238 }
3239
3240 /**
3241  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3242  * @adapter: board private structure
3243  **/
3244 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3245 {
3246         int i;
3247
3248         for (i = 0; i < adapter->num_tx_queues; i++)
3249                 igb_clean_tx_ring(adapter->tx_ring[i]);
3250 }
3251
3252 /**
3253  * igb_free_rx_resources - Free Rx Resources
3254  * @rx_ring: ring to clean the resources from
3255  *
3256  * Free all receive software resources
3257  **/
3258 void igb_free_rx_resources(struct igb_ring *rx_ring)
3259 {
3260         igb_clean_rx_ring(rx_ring);
3261
3262         vfree(rx_ring->rx_buffer_info);
3263         rx_ring->rx_buffer_info = NULL;
3264
3265         /* if not set, then don't free */
3266         if (!rx_ring->desc)
3267                 return;
3268
3269         dma_free_coherent(rx_ring->dev, rx_ring->size,
3270                           rx_ring->desc, rx_ring->dma);
3271
3272         rx_ring->desc = NULL;
3273 }
3274
3275 /**
3276  * igb_free_all_rx_resources - Free Rx Resources for All Queues
3277  * @adapter: board private structure
3278  *
3279  * Free all receive software resources
3280  **/
3281 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3282 {
3283         int i;
3284
3285         for (i = 0; i < adapter->num_rx_queues; i++)
3286                 igb_free_rx_resources(adapter->rx_ring[i]);
3287 }
3288
3289 /**
3290  * igb_clean_rx_ring - Free Rx Buffers per Queue
3291  * @rx_ring: ring to free buffers from
3292  **/
3293 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3294 {
3295         unsigned long size;
3296         u16 i;
3297
3298         if (rx_ring->skb)
3299                 dev_kfree_skb(rx_ring->skb);
3300         rx_ring->skb = NULL;
3301
3302         if (!rx_ring->rx_buffer_info)
3303                 return;
3304
3305         /* Free all the Rx ring sk_buffs */
3306         for (i = 0; i < rx_ring->count; i++) {
3307                 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3308
3309                 if (!buffer_info->page)
3310                         continue;
3311
3312                 dma_unmap_page(rx_ring->dev,
3313                                buffer_info->dma,
3314                                PAGE_SIZE,
3315                                DMA_FROM_DEVICE);
3316                 __free_page(buffer_info->page);
3317
3318                 buffer_info->page = NULL;
3319         }
3320
3321         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3322         memset(rx_ring->rx_buffer_info, 0, size);
3323
3324         /* Zero out the descriptor ring */
3325         memset(rx_ring->desc, 0, rx_ring->size);
3326
3327         rx_ring->next_to_alloc = 0;
3328         rx_ring->next_to_clean = 0;
3329         rx_ring->next_to_use = 0;
3330 }
3331
3332 /**
3333  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3334  * @adapter: board private structure
3335  **/
3336 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3337 {
3338         int i;
3339
3340         for (i = 0; i < adapter->num_rx_queues; i++)
3341                 igb_clean_rx_ring(adapter->rx_ring[i]);
3342 }
3343
3344 /**
3345  * igb_set_mac - Change the Ethernet Address of the NIC
3346  * @netdev: network interface device structure
3347  * @p: pointer to an address structure
3348  *
3349  * Returns 0 on success, negative on failure
3350  **/
3351 static int igb_set_mac(struct net_device *netdev, void *p)
3352 {
3353         struct igb_adapter *adapter = netdev_priv(netdev);
3354         struct e1000_hw *hw = &adapter->hw;
3355         struct sockaddr *addr = p;
3356
3357         if (!is_valid_ether_addr(addr->sa_data))
3358                 return -EADDRNOTAVAIL;
3359
3360         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3361         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3362
3363         /* set the correct pool for the new PF MAC address in entry 0 */
3364         igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3365                          adapter->vfs_allocated_count);
3366
3367         return 0;
3368 }
3369
3370 /**
3371  * igb_write_mc_addr_list - write multicast addresses to MTA
3372  * @netdev: network interface device structure
3373  *
3374  * Writes multicast address list to the MTA hash table.
3375  * Returns: -ENOMEM on failure
3376  *                0 on no addresses written
3377  *                X on writing X addresses to MTA
3378  **/
3379 static int igb_write_mc_addr_list(struct net_device *netdev)
3380 {
3381         struct igb_adapter *adapter = netdev_priv(netdev);
3382         struct e1000_hw *hw = &adapter->hw;
3383         struct netdev_hw_addr *ha;
3384         u8  *mta_list;
3385         int i;
3386
3387         if (netdev_mc_empty(netdev)) {
3388                 /* nothing to program, so clear mc list */
3389                 igb_update_mc_addr_list(hw, NULL, 0);
3390                 igb_restore_vf_multicasts(adapter);
3391                 return 0;
3392         }
3393
3394         mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3395         if (!mta_list)
3396                 return -ENOMEM;
3397
3398         /* The shared function expects a packed array of only addresses. */
3399         i = 0;
3400         netdev_for_each_mc_addr(ha, netdev)
3401                 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3402
3403         igb_update_mc_addr_list(hw, mta_list, i);
3404         kfree(mta_list);
3405
3406         return netdev_mc_count(netdev);
3407 }
3408
3409 /**
3410  * igb_write_uc_addr_list - write unicast addresses to RAR table
3411  * @netdev: network interface device structure
3412  *
3413  * Writes unicast address list to the RAR table.
3414  * Returns: -ENOMEM on failure/insufficient address space
3415  *                0 on no addresses written
3416  *                X on writing X addresses to the RAR table
3417  **/
3418 static int igb_write_uc_addr_list(struct net_device *netdev)
3419 {
3420         struct igb_adapter *adapter = netdev_priv(netdev);
3421         struct e1000_hw *hw = &adapter->hw;
3422         unsigned int vfn = adapter->vfs_allocated_count;
3423         unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3424         int count = 0;
3425
3426         /* return ENOMEM indicating insufficient memory for addresses */
3427         if (netdev_uc_count(netdev) > rar_entries)
3428                 return -ENOMEM;
3429
3430         if (!netdev_uc_empty(netdev) && rar_entries) {
3431                 struct netdev_hw_addr *ha;
3432
3433                 netdev_for_each_uc_addr(ha, netdev) {
3434                         if (!rar_entries)
3435                                 break;
3436                         igb_rar_set_qsel(adapter, ha->addr,
3437                                          rar_entries--,
3438                                          vfn);
3439                         count++;
3440                 }
3441         }
3442         /* write the addresses in reverse order to avoid write combining */
3443         for (; rar_entries > 0 ; rar_entries--) {
3444                 wr32(E1000_RAH(rar_entries), 0);
3445                 wr32(E1000_RAL(rar_entries), 0);
3446         }
3447         wrfl();
3448
3449         return count;
3450 }
3451
3452 /**
3453  * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3454  * @netdev: network interface device structure
3455  *
3456  * The set_rx_mode entry point is called whenever the unicast or multicast
3457  * address lists or the network interface flags are updated.  This routine is
3458  * responsible for configuring the hardware for proper unicast, multicast,
3459  * promiscuous mode, and all-multi behavior.
3460  **/
3461 static void igb_set_rx_mode(struct net_device *netdev)
3462 {
3463         struct igb_adapter *adapter = netdev_priv(netdev);
3464         struct e1000_hw *hw = &adapter->hw;
3465         unsigned int vfn = adapter->vfs_allocated_count;
3466         u32 rctl, vmolr = 0;
3467         int count;
3468
3469         /* Check for Promiscuous and All Multicast modes */
3470         rctl = rd32(E1000_RCTL);
3471
3472         /* clear the effected bits */
3473         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3474
3475         if (netdev->flags & IFF_PROMISC) {
3476                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3477                 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3478         } else {
3479                 if (netdev->flags & IFF_ALLMULTI) {
3480                         rctl |= E1000_RCTL_MPE;
3481                         vmolr |= E1000_VMOLR_MPME;
3482                 } else {
3483                         /*
3484                          * Write addresses to the MTA, if the attempt fails
3485                          * then we should just turn on promiscuous mode so
3486                          * that we can at least receive multicast traffic
3487                          */
3488                         count = igb_write_mc_addr_list(netdev);
3489                         if (count < 0) {
3490                                 rctl |= E1000_RCTL_MPE;
3491                                 vmolr |= E1000_VMOLR_MPME;
3492                         } else if (count) {
3493                                 vmolr |= E1000_VMOLR_ROMPE;
3494                         }
3495                 }
3496                 /*
3497                  * Write addresses to available RAR registers, if there is not
3498                  * sufficient space to store all the addresses then enable
3499                  * unicast promiscuous mode
3500                  */
3501                 count = igb_write_uc_addr_list(netdev);
3502                 if (count < 0) {
3503                         rctl |= E1000_RCTL_UPE;
3504                         vmolr |= E1000_VMOLR_ROPE;
3505                 }
3506                 rctl |= E1000_RCTL_VFE;
3507         }
3508         wr32(E1000_RCTL, rctl);
3509
3510         /*
3511          * In order to support SR-IOV and eventually VMDq it is necessary to set
3512          * the VMOLR to enable the appropriate modes.  Without this workaround
3513          * we will have issues with VLAN tag stripping not being done for frames
3514          * that are only arriving because we are the default pool
3515          */
3516         if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
3517                 return;
3518
3519         vmolr |= rd32(E1000_VMOLR(vfn)) &
3520                  ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3521         wr32(E1000_VMOLR(vfn), vmolr);
3522         igb_restore_vf_multicasts(adapter);
3523 }
3524
3525 static void igb_check_wvbr(struct igb_adapter *adapter)
3526 {
3527         struct e1000_hw *hw = &adapter->hw;
3528         u32 wvbr = 0;
3529
3530         switch (hw->mac.type) {
3531         case e1000_82576:
3532         case e1000_i350:
3533                 if (!(wvbr = rd32(E1000_WVBR)))
3534                         return;
3535                 break;
3536         default:
3537                 break;
3538         }
3539
3540         adapter->wvbr |= wvbr;
3541 }
3542
3543 #define IGB_STAGGERED_QUEUE_OFFSET 8
3544
3545 static void igb_spoof_check(struct igb_adapter *adapter)
3546 {
3547         int j;
3548
3549         if (!adapter->wvbr)
3550                 return;
3551
3552         for(j = 0; j < adapter->vfs_allocated_count; j++) {
3553                 if (adapter->wvbr & (1 << j) ||
3554                     adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3555                         dev_warn(&adapter->pdev->dev,
3556                                 "Spoof event(s) detected on VF %d\n", j);
3557                         adapter->wvbr &=
3558                                 ~((1 << j) |
3559                                   (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3560                 }
3561         }
3562 }
3563
3564 /* Need to wait a few seconds after link up to get diagnostic information from
3565  * the phy */
3566 static void igb_update_phy_info(unsigned long data)
3567 {
3568         struct igb_adapter *adapter = (struct igb_adapter *) data;
3569         igb_get_phy_info(&adapter->hw);
3570 }
3571
3572 /**
3573  * igb_has_link - check shared code for link and determine up/down
3574  * @adapter: pointer to driver private info
3575  **/
3576 bool igb_has_link(struct igb_adapter *adapter)
3577 {
3578         struct e1000_hw *hw = &adapter->hw;
3579         bool link_active = false;
3580         s32 ret_val = 0;
3581
3582         /* get_link_status is set on LSC (link status) interrupt or
3583          * rx sequence error interrupt.  get_link_status will stay
3584          * false until the e1000_check_for_link establishes link
3585          * for copper adapters ONLY
3586          */
3587         switch (hw->phy.media_type) {
3588         case e1000_media_type_copper:
3589                 if (hw->mac.get_link_status) {
3590                         ret_val = hw->mac.ops.check_for_link(hw);
3591                         link_active = !hw->mac.get_link_status;
3592                 } else {
3593                         link_active = true;
3594                 }
3595                 break;
3596         case e1000_media_type_internal_serdes:
3597                 ret_val = hw->mac.ops.check_for_link(hw);
3598                 link_active = hw->mac.serdes_has_link;
3599                 break;
3600         default:
3601         case e1000_media_type_unknown:
3602                 break;
3603         }
3604
3605         return link_active;
3606 }
3607
3608 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3609 {
3610         bool ret = false;
3611         u32 ctrl_ext, thstat;
3612
3613         /* check for thermal sensor event on i350 copper only */
3614         if (hw->mac.type == e1000_i350) {
3615                 thstat = rd32(E1000_THSTAT);
3616                 ctrl_ext = rd32(E1000_CTRL_EXT);
3617
3618                 if ((hw->phy.media_type == e1000_media_type_copper) &&
3619                     !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3620                         ret = !!(thstat & event);
3621                 }
3622         }
3623
3624         return ret;
3625 }
3626
3627 /**
3628  * igb_watchdog - Timer Call-back
3629  * @data: pointer to adapter cast into an unsigned long
3630  **/
3631 static void igb_watchdog(unsigned long data)
3632 {
3633         struct igb_adapter *adapter = (struct igb_adapter *)data;
3634         /* Do the rest outside of interrupt context */
3635         schedule_work(&adapter->watchdog_task);
3636 }
3637
3638 static void igb_watchdog_task(struct work_struct *work)
3639 {
3640         struct igb_adapter *adapter = container_of(work,
3641                                                    struct igb_adapter,
3642                                                    watchdog_task);
3643         struct e1000_hw *hw = &adapter->hw;
3644         struct net_device *netdev = adapter->netdev;
3645         u32 link;
3646         int i;
3647
3648         link = igb_has_link(adapter);
3649         if (link) {
3650                 /* Cancel scheduled suspend requests. */
3651                 pm_runtime_resume(netdev->dev.parent);
3652
3653                 if (!netif_carrier_ok(netdev)) {
3654                         u32 ctrl;
3655                         hw->mac.ops.get_speed_and_duplex(hw,
3656                                                          &adapter->link_speed,
3657                                                          &adapter->link_duplex);
3658
3659                         ctrl = rd32(E1000_CTRL);
3660                         /* Links status message must follow this format */
3661                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3662                                "Duplex, Flow Control: %s\n",
3663                                netdev->name,
3664                                adapter->link_speed,
3665                                adapter->link_duplex == FULL_DUPLEX ?
3666                                "Full" : "Half",
3667                                (ctrl & E1000_CTRL_TFCE) &&
3668                                (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3669                                (ctrl & E1000_CTRL_RFCE) ?  "RX" :
3670                                (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
3671
3672                         /* check for thermal sensor event */
3673                         if (igb_thermal_sensor_event(hw,
3674                             E1000_THSTAT_LINK_THROTTLE)) {
3675                                 netdev_info(netdev, "The network adapter link "
3676                                             "speed was downshifted because it "
3677                                             "overheated\n");
3678                         }
3679
3680                         /* adjust timeout factor according to speed/duplex */
3681                         adapter->tx_timeout_factor = 1;
3682                         switch (adapter->link_speed) {
3683                         case SPEED_10:
3684                                 adapter->tx_timeout_factor = 14;
3685                                 break;
3686                         case SPEED_100:
3687                                 /* maybe add some timeout factor ? */
3688                                 break;
3689                         }
3690
3691                         netif_carrier_on(netdev);
3692
3693                         igb_ping_all_vfs(adapter);
3694                         igb_check_vf_rate_limit(adapter);
3695
3696                         /* link state has changed, schedule phy info update */
3697                         if (!test_bit(__IGB_DOWN, &adapter->state))
3698                                 mod_timer(&adapter->phy_info_timer,
3699                                           round_jiffies(jiffies + 2 * HZ));
3700                 }
3701         } else {
3702                 if (netif_carrier_ok(netdev)) {
3703                         adapter->link_speed = 0;
3704                         adapter->link_duplex = 0;
3705
3706                         /* check for thermal sensor event */
3707                         if (igb_thermal_sensor_event(hw,
3708                             E1000_THSTAT_PWR_DOWN)) {
3709                                 netdev_err(netdev, "The network adapter was "
3710                                            "stopped because it overheated\n");
3711                         }
3712
3713                         /* Links status message must follow this format */
3714                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
3715                                netdev->name);
3716                         netif_carrier_off(netdev);
3717
3718                         igb_ping_all_vfs(adapter);
3719
3720                         /* link state has changed, schedule phy info update */
3721                         if (!test_bit(__IGB_DOWN, &adapter->state))
3722                                 mod_timer(&adapter->phy_info_timer,
3723                                           round_jiffies(jiffies + 2 * HZ));
3724
3725                         pm_schedule_suspend(netdev->dev.parent,
3726                                             MSEC_PER_SEC * 5);
3727                 }
3728         }
3729
3730         spin_lock(&adapter->stats64_lock);
3731         igb_update_stats(adapter, &adapter->stats64);
3732         spin_unlock(&adapter->stats64_lock);
3733
3734         for (i = 0; i < adapter->num_tx_queues; i++) {
3735                 struct igb_ring *tx_ring = adapter->tx_ring[i];
3736                 if (!netif_carrier_ok(netdev)) {
3737                         /* We've lost link, so the controller stops DMA,
3738                          * but we've got queued Tx work that's never going
3739                          * to get done, so reset controller to flush Tx.
3740                          * (Do the reset outside of interrupt context). */
3741                         if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3742                                 adapter->tx_timeout_count++;
3743                                 schedule_work(&adapter->reset_task);
3744                                 /* return immediately since reset is imminent */
3745                                 return;
3746                         }
3747                 }
3748
3749                 /* Force detection of hung controller every watchdog period */
3750                 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
3751         }
3752
3753         /* Cause software interrupt to ensure rx ring is cleaned */
3754         if (adapter->msix_entries) {
3755                 u32 eics = 0;
3756                 for (i = 0; i < adapter->num_q_vectors; i++)
3757                         eics |= adapter->q_vector[i]->eims_value;
3758                 wr32(E1000_EICS, eics);
3759         } else {
3760                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3761         }
3762
3763         igb_spoof_check(adapter);
3764
3765         /* Reset the timer */
3766         if (!test_bit(__IGB_DOWN, &adapter->state))
3767                 mod_timer(&adapter->watchdog_timer,
3768                           round_jiffies(jiffies + 2 * HZ));
3769 }
3770
3771 enum latency_range {
3772         lowest_latency = 0,
3773         low_latency = 1,
3774         bulk_latency = 2,
3775         latency_invalid = 255
3776 };
3777
3778 /**
3779  * igb_update_ring_itr - update the dynamic ITR value based on packet size
3780  *
3781  *      Stores a new ITR value based on strictly on packet size.  This
3782  *      algorithm is less sophisticated than that used in igb_update_itr,
3783  *      due to the difficulty of synchronizing statistics across multiple
3784  *      receive rings.  The divisors and thresholds used by this function
3785  *      were determined based on theoretical maximum wire speed and testing
3786  *      data, in order to minimize response time while increasing bulk
3787  *      throughput.
3788  *      This functionality is controlled by the InterruptThrottleRate module
3789  *      parameter (see igb_param.c)
3790  *      NOTE:  This function is called only when operating in a multiqueue
3791  *             receive environment.
3792  * @q_vector: pointer to q_vector
3793  **/
3794 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
3795 {
3796         int new_val = q_vector->itr_val;
3797         int avg_wire_size = 0;
3798         struct igb_adapter *adapter = q_vector->adapter;
3799         unsigned int packets;
3800
3801         /* For non-gigabit speeds, just fix the interrupt rate at 4000
3802          * ints/sec - ITR timer value of 120 ticks.
3803          */
3804         if (adapter->link_speed != SPEED_1000) {
3805                 new_val = IGB_4K_ITR;
3806                 goto set_itr_val;
3807         }
3808
3809         packets = q_vector->rx.total_packets;
3810         if (packets)
3811                 avg_wire_size = q_vector->rx.total_bytes / packets;
3812
3813         packets = q_vector->tx.total_packets;
3814         if (packets)
3815                 avg_wire_size = max_t(u32, avg_wire_size,
3816                                       q_vector->tx.total_bytes / packets);
3817
3818         /* if avg_wire_size isn't set no work was done */
3819         if (!avg_wire_size)
3820                 goto clear_counts;
3821
3822         /* Add 24 bytes to size to account for CRC, preamble, and gap */
3823         avg_wire_size += 24;
3824
3825         /* Don't starve jumbo frames */
3826         avg_wire_size = min(avg_wire_size, 3000);
3827
3828         /* Give a little boost to mid-size frames */
3829         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3830                 new_val = avg_wire_size / 3;
3831         else
3832                 new_val = avg_wire_size / 2;
3833
3834         /* conservative mode (itr 3) eliminates the lowest_latency setting */
3835         if (new_val < IGB_20K_ITR &&
3836             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3837              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3838                 new_val = IGB_20K_ITR;
3839
3840 set_itr_val:
3841         if (new_val != q_vector->itr_val) {
3842                 q_vector->itr_val = new_val;
3843                 q_vector->set_itr = 1;
3844         }
3845 clear_counts:
3846         q_vector->rx.total_bytes = 0;
3847         q_vector->rx.total_packets = 0;
3848         q_vector->tx.total_bytes = 0;
3849         q_vector->tx.total_packets = 0;
3850 }
3851
3852 /**
3853  * igb_update_itr - update the dynamic ITR value based on statistics
3854  *      Stores a new ITR value based on packets and byte
3855  *      counts during the last interrupt.  The advantage of per interrupt
3856  *      computation is faster updates and more accurate ITR for the current
3857  *      traffic pattern.  Constants in this function were computed
3858  *      based on theoretical maximum wire speed and thresholds were set based
3859  *      on testing data as well as attempting to minimize response time
3860  *      while increasing bulk throughput.
3861  *      this functionality is controlled by the InterruptThrottleRate module
3862  *      parameter (see igb_param.c)
3863  *      NOTE:  These calculations are only valid when operating in a single-
3864  *             queue environment.
3865  * @q_vector: pointer to q_vector
3866  * @ring_container: ring info to update the itr for
3867  **/
3868 static void igb_update_itr(struct igb_q_vector *q_vector,
3869                            struct igb_ring_container *ring_container)
3870 {
3871         unsigned int packets = ring_container->total_packets;
3872         unsigned int bytes = ring_container->total_bytes;
3873         u8 itrval = ring_container->itr;
3874
3875         /* no packets, exit with status unchanged */
3876         if (packets == 0)
3877                 return;
3878
3879         switch (itrval) {
3880         case lowest_latency:
3881                 /* handle TSO and jumbo frames */
3882                 if (bytes/packets > 8000)
3883                         itrval = bulk_latency;
3884                 else if ((packets < 5) && (bytes > 512))
3885                         itrval = low_latency;
3886                 break;
3887         case low_latency:  /* 50 usec aka 20000 ints/s */
3888                 if (bytes > 10000) {
3889                         /* this if handles the TSO accounting */
3890                         if (bytes/packets > 8000) {
3891                                 itrval = bulk_latency;
3892                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3893                                 itrval = bulk_latency;
3894                         } else if ((packets > 35)) {
3895                                 itrval = lowest_latency;
3896                         }
3897                 } else if (bytes/packets > 2000) {
3898                         itrval = bulk_latency;
3899                 } else if (packets <= 2 && bytes < 512) {
3900                         itrval = lowest_latency;
3901                 }
3902                 break;
3903         case bulk_latency: /* 250 usec aka 4000 ints/s */
3904                 if (bytes > 25000) {
3905                         if (packets > 35)
3906                                 itrval = low_latency;
3907                 } else if (bytes < 1500) {
3908                         itrval = low_latency;
3909                 }
3910                 break;
3911         }
3912
3913         /* clear work counters since we have the values we need */
3914         ring_container->total_bytes = 0;
3915         ring_container->total_packets = 0;
3916
3917         /* write updated itr to ring container */
3918         ring_container->itr = itrval;
3919 }
3920
3921 static void igb_set_itr(struct igb_q_vector *q_vector)
3922 {
3923         struct igb_adapter *adapter = q_vector->adapter;
3924         u32 new_itr = q_vector->itr_val;
3925         u8 current_itr = 0;
3926
3927         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3928         if (adapter->link_speed != SPEED_1000) {
3929                 current_itr = 0;
3930                 new_itr = IGB_4K_ITR;
3931                 goto set_itr_now;
3932         }
3933
3934         igb_update_itr(q_vector, &q_vector->tx);
3935         igb_update_itr(q_vector, &q_vector->rx);
3936
3937         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
3938
3939         /* conservative mode (itr 3) eliminates the lowest_latency setting */
3940         if (current_itr == lowest_latency &&
3941             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3942              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3943                 current_itr = low_latency;
3944
3945         switch (current_itr) {
3946         /* counts and packets in update_itr are dependent on these numbers */
3947         case lowest_latency:
3948                 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
3949                 break;
3950         case low_latency:
3951                 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
3952                 break;
3953         case bulk_latency:
3954                 new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
3955                 break;
3956         default:
3957                 break;
3958         }
3959
3960 set_itr_now:
3961         if (new_itr != q_vector->itr_val) {
3962                 /* this attempts to bias the interrupt rate towards Bulk
3963                  * by adding intermediate steps when interrupt rate is
3964                  * increasing */
3965                 new_itr = new_itr > q_vector->itr_val ?
3966                              max((new_itr * q_vector->itr_val) /
3967                                  (new_itr + (q_vector->itr_val >> 2)),
3968                                  new_itr) :
3969                              new_itr;
3970                 /* Don't write the value here; it resets the adapter's
3971                  * internal timer, and causes us to delay far longer than
3972                  * we should between interrupts.  Instead, we write the ITR
3973                  * value at the beginning of the next interrupt so the timing
3974                  * ends up being correct.
3975                  */
3976                 q_vector->itr_val = new_itr;
3977                 q_vector->set_itr = 1;
3978         }
3979 }
3980
3981 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
3982                             u32 type_tucmd, u32 mss_l4len_idx)
3983 {
3984         struct e1000_adv_tx_context_desc *context_desc;
3985         u16 i = tx_ring->next_to_use;
3986
3987         context_desc = IGB_TX_CTXTDESC(tx_ring, i);
3988
3989         i++;
3990         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3991
3992         /* set bits to identify this as an advanced context descriptor */
3993         type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
3994
3995         /* For 82575, context index must be unique per ring. */
3996         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
3997                 mss_l4len_idx |= tx_ring->reg_idx << 4;
3998
3999         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
4000         context_desc->seqnum_seed       = 0;
4001         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
4002         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
4003 }
4004
4005 static int igb_tso(struct igb_ring *tx_ring,
4006                    struct igb_tx_buffer *first,
4007                    u8 *hdr_len)
4008 {
4009         struct sk_buff *skb = first->skb;
4010         u32 vlan_macip_lens, type_tucmd;
4011         u32 mss_l4len_idx, l4len;
4012
4013         if (skb->ip_summed != CHECKSUM_PARTIAL)
4014                 return 0;
4015
4016         if (!skb_is_gso(skb))
4017                 return 0;
4018
4019         if (skb_header_cloned(skb)) {
4020                 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4021                 if (err)
4022                         return err;
4023         }
4024
4025         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4026         type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4027
4028         if (first->protocol == __constant_htons(ETH_P_IP)) {
4029                 struct iphdr *iph = ip_hdr(skb);
4030                 iph->tot_len = 0;
4031                 iph->check = 0;
4032                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4033                                                          iph->daddr, 0,
4034                                                          IPPROTO_TCP,
4035                                                          0);
4036                 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4037                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4038                                    IGB_TX_FLAGS_CSUM |
4039                                    IGB_TX_FLAGS_IPV4;
4040         } else if (skb_is_gso_v6(skb)) {
4041                 ipv6_hdr(skb)->payload_len = 0;
4042                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4043                                                        &ipv6_hdr(skb)->daddr,
4044                                                        0, IPPROTO_TCP, 0);
4045                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4046                                    IGB_TX_FLAGS_CSUM;
4047         }
4048
4049         /* compute header lengths */
4050         l4len = tcp_hdrlen(skb);
4051         *hdr_len = skb_transport_offset(skb) + l4len;
4052
4053         /* update gso size and bytecount with header size */
4054         first->gso_segs = skb_shinfo(skb)->gso_segs;
4055         first->bytecount += (first->gso_segs - 1) * *hdr_len;
4056
4057         /* MSS L4LEN IDX */
4058         mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4059         mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4060
4061         /* VLAN MACLEN IPLEN */
4062         vlan_macip_lens = skb_network_header_len(skb);
4063         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4064         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4065
4066         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4067
4068         return 1;
4069 }
4070
4071 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4072 {
4073         struct sk_buff *skb = first->skb;
4074         u32 vlan_macip_lens = 0;
4075         u32 mss_l4len_idx = 0;
4076         u32 type_tucmd = 0;
4077
4078         if (skb->ip_summed != CHECKSUM_PARTIAL) {
4079                 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4080                         return;
4081         } else {
4082                 u8 l4_hdr = 0;
4083                 switch (first->protocol) {
4084                 case __constant_htons(ETH_P_IP):
4085                         vlan_macip_lens |= skb_network_header_len(skb);
4086                         type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4087                         l4_hdr = ip_hdr(skb)->protocol;
4088                         break;
4089                 case __constant_htons(ETH_P_IPV6):
4090                         vlan_macip_lens |= skb_network_header_len(skb);
4091                         l4_hdr = ipv6_hdr(skb)->nexthdr;
4092                         break;
4093                 default:
4094                         if (unlikely(net_ratelimit())) {
4095                                 dev_warn(tx_ring->dev,
4096                                  "partial checksum but proto=%x!\n",
4097                                  first->protocol);
4098                         }
4099                         break;
4100                 }
4101
4102                 switch (l4_hdr) {
4103                 case IPPROTO_TCP:
4104                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4105                         mss_l4len_idx = tcp_hdrlen(skb) <<
4106                                         E1000_ADVTXD_L4LEN_SHIFT;
4107                         break;
4108                 case IPPROTO_SCTP:
4109                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4110                         mss_l4len_idx = sizeof(struct sctphdr) <<
4111                                         E1000_ADVTXD_L4LEN_SHIFT;
4112                         break;
4113                 case IPPROTO_UDP:
4114                         mss_l4len_idx = sizeof(struct udphdr) <<
4115                                         E1000_ADVTXD_L4LEN_SHIFT;
4116                         break;
4117                 default:
4118                         if (unlikely(net_ratelimit())) {
4119                                 dev_warn(tx_ring->dev,
4120                                  "partial checksum but l4 proto=%x!\n",
4121                                  l4_hdr);
4122                         }
4123                         break;
4124                 }
4125
4126                 /* update TX checksum flag */
4127                 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4128         }
4129
4130         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4131         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4132
4133         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4134 }
4135
4136 #define IGB_SET_FLAG(_input, _flag, _result) \
4137         ((_flag <= _result) ? \
4138          ((u32)(_input & _flag) * (_result / _flag)) : \
4139          ((u32)(_input & _flag) / (_flag / _result)))
4140
4141 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4142 {
4143         /* set type for advanced descriptor with frame checksum insertion */
4144         u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4145                        E1000_ADVTXD_DCMD_DEXT |
4146                        E1000_ADVTXD_DCMD_IFCS;
4147
4148         /* set HW vlan bit if vlan is present */
4149         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4150                                  (E1000_ADVTXD_DCMD_VLE));
4151
4152         /* set segmentation bits for TSO */
4153         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4154                                  (E1000_ADVTXD_DCMD_TSE));
4155
4156         /* set timestamp bit if present */
4157         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4158                                  (E1000_ADVTXD_MAC_TSTAMP));
4159
4160         /* insert frame checksum */
4161         cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4162
4163         return cmd_type;
4164 }
4165
4166 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4167                                  union e1000_adv_tx_desc *tx_desc,
4168                                  u32 tx_flags, unsigned int paylen)
4169 {
4170         u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4171
4172         /* 82575 requires a unique index per ring */
4173         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4174                 olinfo_status |= tx_ring->reg_idx << 4;
4175
4176         /* insert L4 checksum */
4177         olinfo_status |= IGB_SET_FLAG(tx_flags,
4178                                       IGB_TX_FLAGS_CSUM,
4179                                       (E1000_TXD_POPTS_TXSM << 8));
4180
4181         /* insert IPv4 checksum */
4182         olinfo_status |= IGB_SET_FLAG(tx_flags,
4183                                       IGB_TX_FLAGS_IPV4,
4184                                       (E1000_TXD_POPTS_IXSM << 8));
4185
4186         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4187 }
4188
4189 /*
4190  * The largest size we can write to the descriptor is 65535.  In order to
4191  * maintain a power of two alignment we have to limit ourselves to 32K.
4192  */
4193 #define IGB_MAX_TXD_PWR 15
4194 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
4195
4196 static void igb_tx_map(struct igb_ring *tx_ring,
4197                        struct igb_tx_buffer *first,
4198                        const u8 hdr_len)
4199 {
4200         struct sk_buff *skb = first->skb;
4201         struct igb_tx_buffer *tx_buffer;
4202         union e1000_adv_tx_desc *tx_desc;
4203         struct skb_frag_struct *frag;
4204         dma_addr_t dma;
4205         unsigned int data_len, size;
4206         u32 tx_flags = first->tx_flags;
4207         u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4208         u16 i = tx_ring->next_to_use;
4209
4210         tx_desc = IGB_TX_DESC(tx_ring, i);
4211
4212         igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4213
4214         size = skb_headlen(skb);
4215         data_len = skb->data_len;
4216
4217         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4218
4219         tx_buffer = first;
4220
4221         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4222                 if (dma_mapping_error(tx_ring->dev, dma))
4223                         goto dma_error;
4224
4225                 /* record length, and DMA address */
4226                 dma_unmap_len_set(tx_buffer, len, size);
4227                 dma_unmap_addr_set(tx_buffer, dma, dma);
4228
4229                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4230
4231                 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4232                         tx_desc->read.cmd_type_len =
4233                                 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4234
4235                         i++;
4236                         tx_desc++;
4237                         if (i == tx_ring->count) {
4238                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
4239                                 i = 0;
4240                         }
4241                         tx_desc->read.olinfo_status = 0;
4242
4243                         dma += IGB_MAX_DATA_PER_TXD;
4244                         size -= IGB_MAX_DATA_PER_TXD;
4245
4246                         tx_desc->read.buffer_addr = cpu_to_le64(dma);
4247                 }
4248
4249                 if (likely(!data_len))
4250                         break;
4251
4252                 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4253
4254                 i++;
4255                 tx_desc++;
4256                 if (i == tx_ring->count) {
4257                         tx_desc = IGB_TX_DESC(tx_ring, 0);
4258                         i = 0;
4259                 }
4260                 tx_desc->read.olinfo_status = 0;
4261
4262                 size = skb_frag_size(frag);
4263                 data_len -= size;
4264
4265                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4266                                        size, DMA_TO_DEVICE);
4267
4268                 tx_buffer = &tx_ring->tx_buffer_info[i];
4269         }
4270
4271         /* write last descriptor with RS and EOP bits */
4272         cmd_type |= size | IGB_TXD_DCMD;
4273         tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4274
4275         netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4276
4277         /* set the timestamp */
4278         first->time_stamp = jiffies;
4279
4280         /*
4281          * Force memory writes to complete before letting h/w know there
4282          * are new descriptors to fetch.  (Only applicable for weak-ordered
4283          * memory model archs, such as IA-64).
4284          *
4285          * We also need this memory barrier to make certain all of the
4286          * status bits have been updated before next_to_watch is written.
4287          */
4288         wmb();
4289
4290         /* set next_to_watch value indicating a packet is present */
4291         first->next_to_watch = tx_desc;
4292
4293         i++;
4294         if (i == tx_ring->count)
4295                 i = 0;
4296
4297         tx_ring->next_to_use = i;
4298
4299         writel(i, tx_ring->tail);
4300
4301         /* we need this if more than one processor can write to our tail
4302          * at a time, it syncronizes IO on IA64/Altix systems */
4303         mmiowb();
4304
4305         return;
4306
4307 dma_error:
4308         dev_err(tx_ring->dev, "TX DMA map failed\n");
4309
4310         /* clear dma mappings for failed tx_buffer_info map */
4311         for (;;) {
4312                 tx_buffer = &tx_ring->tx_buffer_info[i];
4313                 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4314                 if (tx_buffer == first)
4315                         break;
4316                 if (i == 0)
4317                         i = tx_ring->count;
4318                 i--;
4319         }
4320
4321         tx_ring->next_to_use = i;
4322 }
4323
4324 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4325 {
4326         struct net_device *netdev = tx_ring->netdev;
4327
4328         netif_stop_subqueue(netdev, tx_ring->queue_index);
4329
4330         /* Herbert's original patch had:
4331          *  smp_mb__after_netif_stop_queue();
4332          * but since that doesn't exist yet, just open code it. */
4333         smp_mb();
4334
4335         /* We need to check again in a case another CPU has just
4336          * made room available. */
4337         if (igb_desc_unused(tx_ring) < size)
4338                 return -EBUSY;
4339
4340         /* A reprieve! */
4341         netif_wake_subqueue(netdev, tx_ring->queue_index);
4342
4343         u64_stats_update_begin(&tx_ring->tx_syncp2);
4344         tx_ring->tx_stats.restart_queue2++;
4345         u64_stats_update_end(&tx_ring->tx_syncp2);
4346
4347         return 0;
4348 }
4349
4350 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4351 {
4352         if (igb_desc_unused(tx_ring) >= size)
4353                 return 0;
4354         return __igb_maybe_stop_tx(tx_ring, size);
4355 }
4356
4357 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4358                                 struct igb_ring *tx_ring)
4359 {
4360         struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
4361         struct igb_tx_buffer *first;
4362         int tso;
4363         u32 tx_flags = 0;
4364         __be16 protocol = vlan_get_protocol(skb);
4365         u8 hdr_len = 0;
4366
4367         /* need: 1 descriptor per page,
4368          *       + 2 desc gap to keep tail from touching head,
4369          *       + 1 desc for skb->data,
4370          *       + 1 desc for context descriptor,
4371          * otherwise try next time */
4372         if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
4373                 /* this is a hard error */
4374                 return NETDEV_TX_BUSY;
4375         }
4376
4377         /* record the location of the first descriptor for this packet */
4378         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4379         first->skb = skb;
4380         first->bytecount = skb->len;
4381         first->gso_segs = 1;
4382
4383         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4384                      !(adapter->ptp_tx_skb))) {
4385                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4386                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4387
4388                 adapter->ptp_tx_skb = skb_get(skb);
4389                 if (adapter->hw.mac.type == e1000_82576)
4390                         schedule_work(&adapter->ptp_tx_work);
4391         }
4392
4393         if (vlan_tx_tag_present(skb)) {
4394                 tx_flags |= IGB_TX_FLAGS_VLAN;
4395                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4396         }
4397
4398         /* record initial flags and protocol */
4399         first->tx_flags = tx_flags;
4400         first->protocol = protocol;
4401
4402         tso = igb_tso(tx_ring, first, &hdr_len);
4403         if (tso < 0)
4404                 goto out_drop;
4405         else if (!tso)
4406                 igb_tx_csum(tx_ring, first);
4407
4408         igb_tx_map(tx_ring, first, hdr_len);
4409
4410         /* Make sure there is space in the ring for the next send. */
4411         igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
4412
4413         return NETDEV_TX_OK;
4414
4415 out_drop:
4416         igb_unmap_and_free_tx_resource(tx_ring, first);
4417
4418         return NETDEV_TX_OK;
4419 }
4420
4421 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4422                                                     struct sk_buff *skb)
4423 {
4424         unsigned int r_idx = skb->queue_mapping;
4425
4426         if (r_idx >= adapter->num_tx_queues)
4427                 r_idx = r_idx % adapter->num_tx_queues;
4428
4429         return adapter->tx_ring[r_idx];
4430 }
4431
4432 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4433                                   struct net_device *netdev)
4434 {
4435         struct igb_adapter *adapter = netdev_priv(netdev);
4436
4437         if (test_bit(__IGB_DOWN, &adapter->state)) {
4438                 dev_kfree_skb_any(skb);
4439                 return NETDEV_TX_OK;
4440         }
4441
4442         if (skb->len <= 0) {
4443                 dev_kfree_skb_any(skb);
4444                 return NETDEV_TX_OK;
4445         }
4446
4447         /*
4448          * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4449          * in order to meet this minimum size requirement.
4450          */
4451         if (unlikely(skb->len < 17)) {
4452                 if (skb_pad(skb, 17 - skb->len))
4453                         return NETDEV_TX_OK;
4454                 skb->len = 17;
4455                 skb_set_tail_pointer(skb, 17);
4456         }
4457
4458         return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4459 }
4460
4461 /**
4462  * igb_tx_timeout - Respond to a Tx Hang
4463  * @netdev: network interface device structure
4464  **/
4465 static void igb_tx_timeout(struct net_device *netdev)
4466 {
4467         struct igb_adapter *adapter = netdev_priv(netdev);
4468         struct e1000_hw *hw = &adapter->hw;
4469
4470         /* Do the reset outside of interrupt context */
4471         adapter->tx_timeout_count++;
4472
4473         if (hw->mac.type >= e1000_82580)
4474                 hw->dev_spec._82575.global_device_reset = true;
4475
4476         schedule_work(&adapter->reset_task);
4477         wr32(E1000_EICS,
4478              (adapter->eims_enable_mask & ~adapter->eims_other));
4479 }
4480
4481 static void igb_reset_task(struct work_struct *work)
4482 {
4483         struct igb_adapter *adapter;
4484         adapter = container_of(work, struct igb_adapter, reset_task);
4485
4486         igb_dump(adapter);
4487         netdev_err(adapter->netdev, "Reset adapter\n");
4488         igb_reinit_locked(adapter);
4489 }
4490
4491 /**
4492  * igb_get_stats64 - Get System Network Statistics
4493  * @netdev: network interface device structure
4494  * @stats: rtnl_link_stats64 pointer
4495  *
4496  **/
4497 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4498                                                  struct rtnl_link_stats64 *stats)
4499 {
4500         struct igb_adapter *adapter = netdev_priv(netdev);
4501
4502         spin_lock(&adapter->stats64_lock);
4503         igb_update_stats(adapter, &adapter->stats64);
4504         memcpy(stats, &adapter->stats64, sizeof(*stats));
4505         spin_unlock(&adapter->stats64_lock);
4506
4507         return stats;
4508 }
4509
4510 /**
4511  * igb_change_mtu - Change the Maximum Transfer Unit
4512  * @netdev: network interface device structure
4513  * @new_mtu: new value for maximum frame size
4514  *
4515  * Returns 0 on success, negative on failure
4516  **/
4517 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4518 {
4519         struct igb_adapter *adapter = netdev_priv(netdev);
4520         struct pci_dev *pdev = adapter->pdev;
4521         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4522
4523         if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4524                 dev_err(&pdev->dev, "Invalid MTU setting\n");
4525                 return -EINVAL;
4526         }
4527
4528 #define MAX_STD_JUMBO_FRAME_SIZE 9238
4529         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4530                 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4531                 return -EINVAL;
4532         }
4533
4534         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4535                 msleep(1);
4536
4537         /* igb_down has a dependency on max_frame_size */
4538         adapter->max_frame_size = max_frame;
4539
4540         if (netif_running(netdev))
4541                 igb_down(adapter);
4542
4543         dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4544                  netdev->mtu, new_mtu);
4545         netdev->mtu = new_mtu;
4546
4547         if (netif_running(netdev))
4548                 igb_up(adapter);
4549         else
4550                 igb_reset(adapter);
4551
4552         clear_bit(__IGB_RESETTING, &adapter->state);
4553
4554         return 0;
4555 }
4556
4557 /**
4558  * igb_update_stats - Update the board statistics counters
4559  * @adapter: board private structure
4560  **/
4561
4562 void igb_update_stats(struct igb_adapter *adapter,
4563                       struct rtnl_link_stats64 *net_stats)
4564 {
4565         struct e1000_hw *hw = &adapter->hw;
4566         struct pci_dev *pdev = adapter->pdev;
4567         u32 reg, mpc;
4568         u16 phy_tmp;
4569         int i;
4570         u64 bytes, packets;
4571         unsigned int start;
4572         u64 _bytes, _packets;
4573
4574 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4575
4576         /*
4577          * Prevent stats update while adapter is being reset, or if the pci
4578          * connection is down.
4579          */
4580         if (adapter->link_speed == 0)
4581                 return;
4582         if (pci_channel_offline(pdev))
4583                 return;
4584
4585         bytes = 0;
4586         packets = 0;
4587         for (i = 0; i < adapter->num_rx_queues; i++) {
4588                 u32 rqdpc = rd32(E1000_RQDPC(i));
4589                 struct igb_ring *ring = adapter->rx_ring[i];
4590
4591                 if (rqdpc) {
4592                         ring->rx_stats.drops += rqdpc;
4593                         net_stats->rx_fifo_errors += rqdpc;
4594                 }
4595
4596                 do {
4597                         start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4598                         _bytes = ring->rx_stats.bytes;
4599                         _packets = ring->rx_stats.packets;
4600                 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4601                 bytes += _bytes;
4602                 packets += _packets;
4603         }
4604
4605         net_stats->rx_bytes = bytes;
4606         net_stats->rx_packets = packets;
4607
4608         bytes = 0;
4609         packets = 0;
4610         for (i = 0; i < adapter->num_tx_queues; i++) {
4611                 struct igb_ring *ring = adapter->tx_ring[i];
4612                 do {
4613                         start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4614                         _bytes = ring->tx_stats.bytes;
4615                         _packets = ring->tx_stats.packets;
4616                 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4617                 bytes += _bytes;
4618                 packets += _packets;
4619         }
4620         net_stats->tx_bytes = bytes;
4621         net_stats->tx_packets = packets;
4622
4623         /* read stats registers */
4624         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4625         adapter->stats.gprc += rd32(E1000_GPRC);
4626         adapter->stats.gorc += rd32(E1000_GORCL);
4627         rd32(E1000_GORCH); /* clear GORCL */
4628         adapter->stats.bprc += rd32(E1000_BPRC);
4629         adapter->stats.mprc += rd32(E1000_MPRC);
4630         adapter->stats.roc += rd32(E1000_ROC);
4631
4632         adapter->stats.prc64 += rd32(E1000_PRC64);
4633         adapter->stats.prc127 += rd32(E1000_PRC127);
4634         adapter->stats.prc255 += rd32(E1000_PRC255);
4635         adapter->stats.prc511 += rd32(E1000_PRC511);
4636         adapter->stats.prc1023 += rd32(E1000_PRC1023);
4637         adapter->stats.prc1522 += rd32(E1000_PRC1522);
4638         adapter->stats.symerrs += rd32(E1000_SYMERRS);
4639         adapter->stats.sec += rd32(E1000_SEC);
4640
4641         mpc = rd32(E1000_MPC);
4642         adapter->stats.mpc += mpc;
4643         net_stats->rx_fifo_errors += mpc;
4644         adapter->stats.scc += rd32(E1000_SCC);
4645         adapter->stats.ecol += rd32(E1000_ECOL);
4646         adapter->stats.mcc += rd32(E1000_MCC);
4647         adapter->stats.latecol += rd32(E1000_LATECOL);
4648         adapter->stats.dc += rd32(E1000_DC);
4649         adapter->stats.rlec += rd32(E1000_RLEC);
4650         adapter->stats.xonrxc += rd32(E1000_XONRXC);
4651         adapter->stats.xontxc += rd32(E1000_XONTXC);
4652         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4653         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4654         adapter->stats.fcruc += rd32(E1000_FCRUC);
4655         adapter->stats.gptc += rd32(E1000_GPTC);
4656         adapter->stats.gotc += rd32(E1000_GOTCL);
4657         rd32(E1000_GOTCH); /* clear GOTCL */
4658         adapter->stats.rnbc += rd32(E1000_RNBC);
4659         adapter->stats.ruc += rd32(E1000_RUC);
4660         adapter->stats.rfc += rd32(E1000_RFC);
4661         adapter->stats.rjc += rd32(E1000_RJC);
4662         adapter->stats.tor += rd32(E1000_TORH);
4663         adapter->stats.tot += rd32(E1000_TOTH);
4664         adapter->stats.tpr += rd32(E1000_TPR);
4665
4666         adapter->stats.ptc64 += rd32(E1000_PTC64);
4667         adapter->stats.ptc127 += rd32(E1000_PTC127);
4668         adapter->stats.ptc255 += rd32(E1000_PTC255);
4669         adapter->stats.ptc511 += rd32(E1000_PTC511);
4670         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4671         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4672
4673         adapter->stats.mptc += rd32(E1000_MPTC);
4674         adapter->stats.bptc += rd32(E1000_BPTC);
4675
4676         adapter->stats.tpt += rd32(E1000_TPT);
4677         adapter->stats.colc += rd32(E1000_COLC);
4678
4679         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4680         /* read internal phy specific stats */
4681         reg = rd32(E1000_CTRL_EXT);
4682         if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4683                 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4684
4685                 /* this stat has invalid values on i210/i211 */
4686                 if ((hw->mac.type != e1000_i210) &&
4687                     (hw->mac.type != e1000_i211))
4688                         adapter->stats.tncrs += rd32(E1000_TNCRS);
4689         }
4690
4691         adapter->stats.tsctc += rd32(E1000_TSCTC);
4692         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4693
4694         adapter->stats.iac += rd32(E1000_IAC);
4695         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4696         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4697         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4698         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4699         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4700         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4701         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4702         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4703
4704         /* Fill out the OS statistics structure */
4705         net_stats->multicast = adapter->stats.mprc;
4706         net_stats->collisions = adapter->stats.colc;
4707
4708         /* Rx Errors */
4709
4710         /* RLEC on some newer hardware can be incorrect so build
4711          * our own version based on RUC and ROC */
4712         net_stats->rx_errors = adapter->stats.rxerrc +
4713                 adapter->stats.crcerrs + adapter->stats.algnerrc +
4714                 adapter->stats.ruc + adapter->stats.roc +
4715                 adapter->stats.cexterr;
4716         net_stats->rx_length_errors = adapter->stats.ruc +
4717                                       adapter->stats.roc;
4718         net_stats->rx_crc_errors = adapter->stats.crcerrs;
4719         net_stats->rx_frame_errors = adapter->stats.algnerrc;
4720         net_stats->rx_missed_errors = adapter->stats.mpc;
4721
4722         /* Tx Errors */
4723         net_stats->tx_errors = adapter->stats.ecol +
4724                                adapter->stats.latecol;
4725         net_stats->tx_aborted_errors = adapter->stats.ecol;
4726         net_stats->tx_window_errors = adapter->stats.latecol;
4727         net_stats->tx_carrier_errors = adapter->stats.tncrs;
4728
4729         /* Tx Dropped needs to be maintained elsewhere */
4730
4731         /* Phy Stats */
4732         if (hw->phy.media_type == e1000_media_type_copper) {
4733                 if ((adapter->link_speed == SPEED_1000) &&
4734                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
4735                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4736                         adapter->phy_stats.idle_errors += phy_tmp;
4737                 }
4738         }
4739
4740         /* Management Stats */
4741         adapter->stats.mgptc += rd32(E1000_MGTPTC);
4742         adapter->stats.mgprc += rd32(E1000_MGTPRC);
4743         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4744
4745         /* OS2BMC Stats */
4746         reg = rd32(E1000_MANC);
4747         if (reg & E1000_MANC_EN_BMC2OS) {
4748                 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4749                 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4750                 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4751                 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4752         }
4753 }
4754
4755 static irqreturn_t igb_msix_other(int irq, void *data)
4756 {
4757         struct igb_adapter *adapter = data;
4758         struct e1000_hw *hw = &adapter->hw;
4759         u32 icr = rd32(E1000_ICR);
4760         /* reading ICR causes bit 31 of EICR to be cleared */
4761
4762         if (icr & E1000_ICR_DRSTA)
4763                 schedule_work(&adapter->reset_task);
4764
4765         if (icr & E1000_ICR_DOUTSYNC) {
4766                 /* HW is reporting DMA is out of sync */
4767                 adapter->stats.doosync++;
4768                 /* The DMA Out of Sync is also indication of a spoof event
4769                  * in IOV mode. Check the Wrong VM Behavior register to
4770                  * see if it is really a spoof event. */
4771                 igb_check_wvbr(adapter);
4772         }
4773
4774         /* Check for a mailbox event */
4775         if (icr & E1000_ICR_VMMB)
4776                 igb_msg_task(adapter);
4777
4778         if (icr & E1000_ICR_LSC) {
4779                 hw->mac.get_link_status = 1;
4780                 /* guard against interrupt when we're going down */
4781                 if (!test_bit(__IGB_DOWN, &adapter->state))
4782                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4783         }
4784
4785         if (icr & E1000_ICR_TS) {
4786                 u32 tsicr = rd32(E1000_TSICR);
4787
4788                 if (tsicr & E1000_TSICR_TXTS) {
4789                         /* acknowledge the interrupt */
4790                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
4791                         /* retrieve hardware timestamp */
4792                         schedule_work(&adapter->ptp_tx_work);
4793                 }
4794         }
4795
4796         wr32(E1000_EIMS, adapter->eims_other);
4797
4798         return IRQ_HANDLED;
4799 }
4800
4801 static void igb_write_itr(struct igb_q_vector *q_vector)
4802 {
4803         struct igb_adapter *adapter = q_vector->adapter;
4804         u32 itr_val = q_vector->itr_val & 0x7FFC;
4805
4806         if (!q_vector->set_itr)
4807                 return;
4808
4809         if (!itr_val)
4810                 itr_val = 0x4;
4811
4812         if (adapter->hw.mac.type == e1000_82575)
4813                 itr_val |= itr_val << 16;
4814         else
4815                 itr_val |= E1000_EITR_CNT_IGNR;
4816
4817         writel(itr_val, q_vector->itr_register);
4818         q_vector->set_itr = 0;
4819 }
4820
4821 static irqreturn_t igb_msix_ring(int irq, void *data)
4822 {
4823         struct igb_q_vector *q_vector = data;
4824
4825         /* Write the ITR value calculated from the previous interrupt. */
4826         igb_write_itr(q_vector);
4827
4828         napi_schedule(&q_vector->napi);
4829
4830         return IRQ_HANDLED;
4831 }
4832
4833 #ifdef CONFIG_IGB_DCA
4834 static void igb_update_tx_dca(struct igb_adapter *adapter,
4835                               struct igb_ring *tx_ring,
4836                               int cpu)
4837 {
4838         struct e1000_hw *hw = &adapter->hw;
4839         u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
4840
4841         if (hw->mac.type != e1000_82575)
4842                 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
4843
4844         /*
4845          * We can enable relaxed ordering for reads, but not writes when
4846          * DCA is enabled.  This is due to a known issue in some chipsets
4847          * which will cause the DCA tag to be cleared.
4848          */
4849         txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
4850                   E1000_DCA_TXCTRL_DATA_RRO_EN |
4851                   E1000_DCA_TXCTRL_DESC_DCA_EN;
4852
4853         wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
4854 }
4855
4856 static void igb_update_rx_dca(struct igb_adapter *adapter,
4857                               struct igb_ring *rx_ring,
4858                               int cpu)
4859 {
4860         struct e1000_hw *hw = &adapter->hw;
4861         u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
4862
4863         if (hw->mac.type != e1000_82575)
4864                 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
4865
4866         /*
4867          * We can enable relaxed ordering for reads, but not writes when
4868          * DCA is enabled.  This is due to a known issue in some chipsets
4869          * which will cause the DCA tag to be cleared.
4870          */
4871         rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
4872                   E1000_DCA_RXCTRL_DESC_DCA_EN;
4873
4874         wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
4875 }
4876
4877 static void igb_update_dca(struct igb_q_vector *q_vector)
4878 {
4879         struct igb_adapter *adapter = q_vector->adapter;
4880         int cpu = get_cpu();
4881
4882         if (q_vector->cpu == cpu)
4883                 goto out_no_update;
4884
4885         if (q_vector->tx.ring)
4886                 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
4887
4888         if (q_vector->rx.ring)
4889                 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
4890
4891         q_vector->cpu = cpu;
4892 out_no_update:
4893         put_cpu();
4894 }
4895
4896 static void igb_setup_dca(struct igb_adapter *adapter)
4897 {
4898         struct e1000_hw *hw = &adapter->hw;
4899         int i;
4900
4901         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
4902                 return;
4903
4904         /* Always use CB2 mode, difference is masked in the CB driver. */
4905         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4906
4907         for (i = 0; i < adapter->num_q_vectors; i++) {
4908                 adapter->q_vector[i]->cpu = -1;
4909                 igb_update_dca(adapter->q_vector[i]);
4910         }
4911 }
4912
4913 static int __igb_notify_dca(struct device *dev, void *data)
4914 {
4915         struct net_device *netdev = dev_get_drvdata(dev);
4916         struct igb_adapter *adapter = netdev_priv(netdev);
4917         struct pci_dev *pdev = adapter->pdev;
4918         struct e1000_hw *hw = &adapter->hw;
4919         unsigned long event = *(unsigned long *)data;
4920
4921         switch (event) {
4922         case DCA_PROVIDER_ADD:
4923                 /* if already enabled, don't do it again */
4924                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
4925                         break;
4926                 if (dca_add_requester(dev) == 0) {
4927                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
4928                         dev_info(&pdev->dev, "DCA enabled\n");
4929                         igb_setup_dca(adapter);
4930                         break;
4931                 }
4932                 /* Fall Through since DCA is disabled. */
4933         case DCA_PROVIDER_REMOVE:
4934                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
4935                         /* without this a class_device is left
4936                          * hanging around in the sysfs model */
4937                         dca_remove_requester(dev);
4938                         dev_info(&pdev->dev, "DCA disabled\n");
4939                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
4940                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
4941                 }
4942                 break;
4943         }
4944
4945         return 0;
4946 }
4947
4948 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4949                           void *p)
4950 {
4951         int ret_val;
4952
4953         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4954                                          __igb_notify_dca);
4955
4956         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4957 }
4958 #endif /* CONFIG_IGB_DCA */
4959
4960 #ifdef CONFIG_PCI_IOV
4961 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
4962 {
4963         unsigned char mac_addr[ETH_ALEN];
4964
4965         eth_random_addr(mac_addr);
4966         igb_set_vf_mac(adapter, vf, mac_addr);
4967
4968         return 0;
4969 }
4970
4971 static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
4972 {
4973         struct pci_dev *pdev = adapter->pdev;
4974         struct pci_dev *vfdev;
4975         int dev_id;
4976
4977         switch (adapter->hw.mac.type) {
4978         case e1000_82576:
4979                 dev_id = IGB_82576_VF_DEV_ID;
4980                 break;
4981         case e1000_i350:
4982                 dev_id = IGB_I350_VF_DEV_ID;
4983                 break;
4984         default:
4985                 return false;
4986         }
4987
4988         /* loop through all the VFs to see if we own any that are assigned */
4989         vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
4990         while (vfdev) {
4991                 /* if we don't own it we don't care */
4992                 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
4993                         /* if it is assigned we cannot release it */
4994                         if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
4995                                 return true;
4996                 }
4997
4998                 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
4999         }
5000
5001         return false;
5002 }
5003
5004 #endif
5005 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5006 {
5007         struct e1000_hw *hw = &adapter->hw;
5008         u32 ping;
5009         int i;
5010
5011         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5012                 ping = E1000_PF_CONTROL_MSG;
5013                 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5014                         ping |= E1000_VT_MSGTYPE_CTS;
5015                 igb_write_mbx(hw, &ping, 1, i);
5016         }
5017 }
5018
5019 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5020 {
5021         struct e1000_hw *hw = &adapter->hw;
5022         u32 vmolr = rd32(E1000_VMOLR(vf));
5023         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5024
5025         vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5026                             IGB_VF_FLAG_MULTI_PROMISC);
5027         vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5028
5029         if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5030                 vmolr |= E1000_VMOLR_MPME;
5031                 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5032                 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5033         } else {
5034                 /*
5035                  * if we have hashes and we are clearing a multicast promisc
5036                  * flag we need to write the hashes to the MTA as this step
5037                  * was previously skipped
5038                  */
5039                 if (vf_data->num_vf_mc_hashes > 30) {
5040                         vmolr |= E1000_VMOLR_MPME;
5041                 } else if (vf_data->num_vf_mc_hashes) {
5042                         int j;
5043                         vmolr |= E1000_VMOLR_ROMPE;
5044                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5045                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5046                 }
5047         }
5048
5049         wr32(E1000_VMOLR(vf), vmolr);
5050
5051         /* there are flags left unprocessed, likely not supported */
5052         if (*msgbuf & E1000_VT_MSGINFO_MASK)
5053                 return -EINVAL;
5054
5055         return 0;
5056
5057 }
5058
5059 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5060                                   u32 *msgbuf, u32 vf)
5061 {
5062         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5063         u16 *hash_list = (u16 *)&msgbuf[1];
5064         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5065         int i;
5066
5067         /* salt away the number of multicast addresses assigned
5068          * to this VF for later use to restore when the PF multi cast
5069          * list changes
5070          */
5071         vf_data->num_vf_mc_hashes = n;
5072
5073         /* only up to 30 hash values supported */
5074         if (n > 30)
5075                 n = 30;
5076
5077         /* store the hashes for later use */
5078         for (i = 0; i < n; i++)
5079                 vf_data->vf_mc_hashes[i] = hash_list[i];
5080
5081         /* Flush and reset the mta with the new values */
5082         igb_set_rx_mode(adapter->netdev);
5083
5084         return 0;
5085 }
5086
5087 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5088 {
5089         struct e1000_hw *hw = &adapter->hw;
5090         struct vf_data_storage *vf_data;
5091         int i, j;
5092
5093         for (i = 0; i < adapter->vfs_allocated_count; i++) {
5094                 u32 vmolr = rd32(E1000_VMOLR(i));
5095                 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5096
5097                 vf_data = &adapter->vf_data[i];
5098
5099                 if ((vf_data->num_vf_mc_hashes > 30) ||
5100                     (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5101                         vmolr |= E1000_VMOLR_MPME;
5102                 } else if (vf_data->num_vf_mc_hashes) {
5103                         vmolr |= E1000_VMOLR_ROMPE;
5104                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5105                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5106                 }
5107                 wr32(E1000_VMOLR(i), vmolr);
5108         }
5109 }
5110
5111 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5112 {
5113         struct e1000_hw *hw = &adapter->hw;
5114         u32 pool_mask, reg, vid;
5115         int i;
5116
5117         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5118
5119         /* Find the vlan filter for this id */
5120         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5121                 reg = rd32(E1000_VLVF(i));
5122
5123                 /* remove the vf from the pool */
5124                 reg &= ~pool_mask;
5125
5126                 /* if pool is empty then remove entry from vfta */
5127                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5128                     (reg & E1000_VLVF_VLANID_ENABLE)) {
5129                         reg = 0;
5130                         vid = reg & E1000_VLVF_VLANID_MASK;
5131                         igb_vfta_set(hw, vid, false);
5132                 }
5133
5134                 wr32(E1000_VLVF(i), reg);
5135         }
5136
5137         adapter->vf_data[vf].vlans_enabled = 0;
5138 }
5139
5140 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5141 {
5142         struct e1000_hw *hw = &adapter->hw;
5143         u32 reg, i;
5144
5145         /* The vlvf table only exists on 82576 hardware and newer */
5146         if (hw->mac.type < e1000_82576)
5147                 return -1;
5148
5149         /* we only need to do this if VMDq is enabled */
5150         if (!adapter->vfs_allocated_count)
5151                 return -1;
5152
5153         /* Find the vlan filter for this id */
5154         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5155                 reg = rd32(E1000_VLVF(i));
5156                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5157                     vid == (reg & E1000_VLVF_VLANID_MASK))
5158                         break;
5159         }
5160
5161         if (add) {
5162                 if (i == E1000_VLVF_ARRAY_SIZE) {
5163                         /* Did not find a matching VLAN ID entry that was
5164                          * enabled.  Search for a free filter entry, i.e.
5165                          * one without the enable bit set
5166                          */
5167                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5168                                 reg = rd32(E1000_VLVF(i));
5169                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5170                                         break;
5171                         }
5172                 }
5173                 if (i < E1000_VLVF_ARRAY_SIZE) {
5174                         /* Found an enabled/available entry */
5175                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5176
5177                         /* if !enabled we need to set this up in vfta */
5178                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5179                                 /* add VID to filter table */
5180                                 igb_vfta_set(hw, vid, true);
5181                                 reg |= E1000_VLVF_VLANID_ENABLE;
5182                         }
5183                         reg &= ~E1000_VLVF_VLANID_MASK;
5184                         reg |= vid;
5185                         wr32(E1000_VLVF(i), reg);
5186
5187                         /* do not modify RLPML for PF devices */
5188                         if (vf >= adapter->vfs_allocated_count)
5189                                 return 0;
5190
5191                         if (!adapter->vf_data[vf].vlans_enabled) {
5192                                 u32 size;
5193                                 reg = rd32(E1000_VMOLR(vf));
5194                                 size = reg & E1000_VMOLR_RLPML_MASK;
5195                                 size += 4;
5196                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5197                                 reg |= size;
5198                                 wr32(E1000_VMOLR(vf), reg);
5199                         }
5200
5201                         adapter->vf_data[vf].vlans_enabled++;
5202                 }
5203         } else {
5204                 if (i < E1000_VLVF_ARRAY_SIZE) {
5205                         /* remove vf from the pool */
5206                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5207                         /* if pool is empty then remove entry from vfta */
5208                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5209                                 reg = 0;
5210                                 igb_vfta_set(hw, vid, false);
5211                         }
5212                         wr32(E1000_VLVF(i), reg);
5213
5214                         /* do not modify RLPML for PF devices */
5215                         if (vf >= adapter->vfs_allocated_count)
5216                                 return 0;
5217
5218                         adapter->vf_data[vf].vlans_enabled--;
5219                         if (!adapter->vf_data[vf].vlans_enabled) {
5220                                 u32 size;
5221                                 reg = rd32(E1000_VMOLR(vf));
5222                                 size = reg & E1000_VMOLR_RLPML_MASK;
5223                                 size -= 4;
5224                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5225                                 reg |= size;
5226                                 wr32(E1000_VMOLR(vf), reg);
5227                         }
5228                 }
5229         }
5230         return 0;
5231 }
5232
5233 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5234 {
5235         struct e1000_hw *hw = &adapter->hw;
5236
5237         if (vid)
5238                 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5239         else
5240                 wr32(E1000_VMVIR(vf), 0);
5241 }
5242
5243 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5244                                int vf, u16 vlan, u8 qos)
5245 {
5246         int err = 0;
5247         struct igb_adapter *adapter = netdev_priv(netdev);
5248
5249         if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5250                 return -EINVAL;
5251         if (vlan || qos) {
5252                 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5253                 if (err)
5254                         goto out;
5255                 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5256                 igb_set_vmolr(adapter, vf, !vlan);
5257                 adapter->vf_data[vf].pf_vlan = vlan;
5258                 adapter->vf_data[vf].pf_qos = qos;
5259                 dev_info(&adapter->pdev->dev,
5260                          "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5261                 if (test_bit(__IGB_DOWN, &adapter->state)) {
5262                         dev_warn(&adapter->pdev->dev,
5263                                  "The VF VLAN has been set,"
5264                                  " but the PF device is not up.\n");
5265                         dev_warn(&adapter->pdev->dev,
5266                                  "Bring the PF device up before"
5267                                  " attempting to use the VF device.\n");
5268                 }
5269         } else {
5270                 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5271                                    false, vf);
5272                 igb_set_vmvir(adapter, vlan, vf);
5273                 igb_set_vmolr(adapter, vf, true);
5274                 adapter->vf_data[vf].pf_vlan = 0;
5275                 adapter->vf_data[vf].pf_qos = 0;
5276        }
5277 out:
5278        return err;
5279 }
5280
5281 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5282 {
5283         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5284         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5285
5286         return igb_vlvf_set(adapter, vid, add, vf);
5287 }
5288
5289 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5290 {
5291         /* clear flags - except flag that indicates PF has set the MAC */
5292         adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5293         adapter->vf_data[vf].last_nack = jiffies;
5294
5295         /* reset offloads to defaults */
5296         igb_set_vmolr(adapter, vf, true);
5297
5298         /* reset vlans for device */
5299         igb_clear_vf_vfta(adapter, vf);
5300         if (adapter->vf_data[vf].pf_vlan)
5301                 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5302                                     adapter->vf_data[vf].pf_vlan,
5303                                     adapter->vf_data[vf].pf_qos);
5304         else
5305                 igb_clear_vf_vfta(adapter, vf);
5306
5307         /* reset multicast table array for vf */
5308         adapter->vf_data[vf].num_vf_mc_hashes = 0;
5309
5310         /* Flush and reset the mta with the new values */
5311         igb_set_rx_mode(adapter->netdev);
5312 }
5313
5314 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5315 {
5316         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5317
5318         /* generate a new mac address as we were hotplug removed/added */
5319         if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5320                 eth_random_addr(vf_mac);
5321
5322         /* process remaining reset events */
5323         igb_vf_reset(adapter, vf);
5324 }
5325
5326 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5327 {
5328         struct e1000_hw *hw = &adapter->hw;
5329         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5330         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5331         u32 reg, msgbuf[3];
5332         u8 *addr = (u8 *)(&msgbuf[1]);
5333
5334         /* process all the same items cleared in a function level reset */
5335         igb_vf_reset(adapter, vf);
5336
5337         /* set vf mac address */
5338         igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5339
5340         /* enable transmit and receive for vf */
5341         reg = rd32(E1000_VFTE);
5342         wr32(E1000_VFTE, reg | (1 << vf));
5343         reg = rd32(E1000_VFRE);
5344         wr32(E1000_VFRE, reg | (1 << vf));
5345
5346         adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5347
5348         /* reply to reset with ack and vf mac address */
5349         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5350         memcpy(addr, vf_mac, 6);
5351         igb_write_mbx(hw, msgbuf, 3, vf);
5352 }
5353
5354 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5355 {
5356         /*
5357          * The VF MAC Address is stored in a packed array of bytes
5358          * starting at the second 32 bit word of the msg array
5359          */
5360         unsigned char *addr = (char *)&msg[1];
5361         int err = -1;
5362
5363         if (is_valid_ether_addr(addr))
5364                 err = igb_set_vf_mac(adapter, vf, addr);
5365
5366         return err;
5367 }
5368
5369 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5370 {
5371         struct e1000_hw *hw = &adapter->hw;
5372         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5373         u32 msg = E1000_VT_MSGTYPE_NACK;
5374
5375         /* if device isn't clear to send it shouldn't be reading either */
5376         if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5377             time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5378                 igb_write_mbx(hw, &msg, 1, vf);
5379                 vf_data->last_nack = jiffies;
5380         }
5381 }
5382
5383 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5384 {
5385         struct pci_dev *pdev = adapter->pdev;
5386         u32 msgbuf[E1000_VFMAILBOX_SIZE];
5387         struct e1000_hw *hw = &adapter->hw;
5388         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5389         s32 retval;
5390
5391         retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5392
5393         if (retval) {
5394                 /* if receive failed revoke VF CTS stats and restart init */
5395                 dev_err(&pdev->dev, "Error receiving message from VF\n");
5396                 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5397                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5398                         return;
5399                 goto out;
5400         }
5401
5402         /* this is a message we already processed, do nothing */
5403         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5404                 return;
5405
5406         /*
5407          * until the vf completes a reset it should not be
5408          * allowed to start any configuration.
5409          */
5410
5411         if (msgbuf[0] == E1000_VF_RESET) {
5412                 igb_vf_reset_msg(adapter, vf);
5413                 return;
5414         }
5415
5416         if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5417                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5418                         return;
5419                 retval = -1;
5420                 goto out;
5421         }
5422
5423         switch ((msgbuf[0] & 0xFFFF)) {
5424         case E1000_VF_SET_MAC_ADDR:
5425                 retval = -EINVAL;
5426                 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5427                         retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5428                 else
5429                         dev_warn(&pdev->dev,
5430                                  "VF %d attempted to override administratively "
5431                                  "set MAC address\nReload the VF driver to "
5432                                  "resume operations\n", vf);
5433                 break;
5434         case E1000_VF_SET_PROMISC:
5435                 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5436                 break;
5437         case E1000_VF_SET_MULTICAST:
5438                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5439                 break;
5440         case E1000_VF_SET_LPE:
5441                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5442                 break;
5443         case E1000_VF_SET_VLAN:
5444                 retval = -1;
5445                 if (vf_data->pf_vlan)
5446                         dev_warn(&pdev->dev,
5447                                  "VF %d attempted to override administratively "
5448                                  "set VLAN tag\nReload the VF driver to "
5449                                  "resume operations\n", vf);
5450                 else
5451                         retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5452                 break;
5453         default:
5454                 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5455                 retval = -1;
5456                 break;
5457         }
5458
5459         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5460 out:
5461         /* notify the VF of the results of what it sent us */
5462         if (retval)
5463                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5464         else
5465                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5466
5467         igb_write_mbx(hw, msgbuf, 1, vf);
5468 }
5469
5470 static void igb_msg_task(struct igb_adapter *adapter)
5471 {
5472         struct e1000_hw *hw = &adapter->hw;
5473         u32 vf;
5474
5475         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5476                 /* process any reset requests */
5477                 if (!igb_check_for_rst(hw, vf))
5478                         igb_vf_reset_event(adapter, vf);
5479
5480                 /* process any messages pending */
5481                 if (!igb_check_for_msg(hw, vf))
5482                         igb_rcv_msg_from_vf(adapter, vf);
5483
5484                 /* process any acks */
5485                 if (!igb_check_for_ack(hw, vf))
5486                         igb_rcv_ack_from_vf(adapter, vf);
5487         }
5488 }
5489
5490 /**
5491  *  igb_set_uta - Set unicast filter table address
5492  *  @adapter: board private structure
5493  *
5494  *  The unicast table address is a register array of 32-bit registers.
5495  *  The table is meant to be used in a way similar to how the MTA is used
5496  *  however due to certain limitations in the hardware it is necessary to
5497  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5498  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
5499  **/
5500 static void igb_set_uta(struct igb_adapter *adapter)
5501 {
5502         struct e1000_hw *hw = &adapter->hw;
5503         int i;
5504
5505         /* The UTA table only exists on 82576 hardware and newer */
5506         if (hw->mac.type < e1000_82576)
5507                 return;
5508
5509         /* we only need to do this if VMDq is enabled */
5510         if (!adapter->vfs_allocated_count)
5511                 return;
5512
5513         for (i = 0; i < hw->mac.uta_reg_count; i++)
5514                 array_wr32(E1000_UTA, i, ~0);
5515 }
5516
5517 /**
5518  * igb_intr_msi - Interrupt Handler
5519  * @irq: interrupt number
5520  * @data: pointer to a network interface device structure
5521  **/
5522 static irqreturn_t igb_intr_msi(int irq, void *data)
5523 {
5524         struct igb_adapter *adapter = data;
5525         struct igb_q_vector *q_vector = adapter->q_vector[0];
5526         struct e1000_hw *hw = &adapter->hw;
5527         /* read ICR disables interrupts using IAM */
5528         u32 icr = rd32(E1000_ICR);
5529
5530         igb_write_itr(q_vector);
5531
5532         if (icr & E1000_ICR_DRSTA)
5533                 schedule_work(&adapter->reset_task);
5534
5535         if (icr & E1000_ICR_DOUTSYNC) {
5536                 /* HW is reporting DMA is out of sync */
5537                 adapter->stats.doosync++;
5538         }
5539
5540         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5541                 hw->mac.get_link_status = 1;
5542                 if (!test_bit(__IGB_DOWN, &adapter->state))
5543                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5544         }
5545
5546         if (icr & E1000_ICR_TS) {
5547                 u32 tsicr = rd32(E1000_TSICR);
5548
5549                 if (tsicr & E1000_TSICR_TXTS) {
5550                         /* acknowledge the interrupt */
5551                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5552                         /* retrieve hardware timestamp */
5553                         schedule_work(&adapter->ptp_tx_work);
5554                 }
5555         }
5556
5557         napi_schedule(&q_vector->napi);
5558
5559         return IRQ_HANDLED;
5560 }
5561
5562 /**
5563  * igb_intr - Legacy Interrupt Handler
5564  * @irq: interrupt number
5565  * @data: pointer to a network interface device structure
5566  **/
5567 static irqreturn_t igb_intr(int irq, void *data)
5568 {
5569         struct igb_adapter *adapter = data;
5570         struct igb_q_vector *q_vector = adapter->q_vector[0];
5571         struct e1000_hw *hw = &adapter->hw;
5572         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
5573          * need for the IMC write */
5574         u32 icr = rd32(E1000_ICR);
5575
5576         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5577          * not set, then the adapter didn't send an interrupt */
5578         if (!(icr & E1000_ICR_INT_ASSERTED))
5579                 return IRQ_NONE;
5580
5581         igb_write_itr(q_vector);
5582
5583         if (icr & E1000_ICR_DRSTA)
5584                 schedule_work(&adapter->reset_task);
5585
5586         if (icr & E1000_ICR_DOUTSYNC) {
5587                 /* HW is reporting DMA is out of sync */
5588                 adapter->stats.doosync++;
5589         }
5590
5591         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5592                 hw->mac.get_link_status = 1;
5593                 /* guard against interrupt when we're going down */
5594                 if (!test_bit(__IGB_DOWN, &adapter->state))
5595                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5596         }
5597
5598         if (icr & E1000_ICR_TS) {
5599                 u32 tsicr = rd32(E1000_TSICR);
5600
5601                 if (tsicr & E1000_TSICR_TXTS) {
5602                         /* acknowledge the interrupt */
5603                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5604                         /* retrieve hardware timestamp */
5605                         schedule_work(&adapter->ptp_tx_work);
5606                 }
5607         }
5608
5609         napi_schedule(&q_vector->napi);
5610
5611         return IRQ_HANDLED;
5612 }
5613
5614 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5615 {
5616         struct igb_adapter *adapter = q_vector->adapter;
5617         struct e1000_hw *hw = &adapter->hw;
5618
5619         if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5620             (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5621                 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5622                         igb_set_itr(q_vector);
5623                 else
5624                         igb_update_ring_itr(q_vector);
5625         }
5626
5627         if (!test_bit(__IGB_DOWN, &adapter->state)) {
5628                 if (adapter->msix_entries)
5629                         wr32(E1000_EIMS, q_vector->eims_value);
5630                 else
5631                         igb_irq_enable(adapter);
5632         }
5633 }
5634
5635 /**
5636  * igb_poll - NAPI Rx polling callback
5637  * @napi: napi polling structure
5638  * @budget: count of how many packets we should handle
5639  **/
5640 static int igb_poll(struct napi_struct *napi, int budget)
5641 {
5642         struct igb_q_vector *q_vector = container_of(napi,
5643                                                      struct igb_q_vector,
5644                                                      napi);
5645         bool clean_complete = true;
5646
5647 #ifdef CONFIG_IGB_DCA
5648         if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5649                 igb_update_dca(q_vector);
5650 #endif
5651         if (q_vector->tx.ring)
5652                 clean_complete = igb_clean_tx_irq(q_vector);
5653
5654         if (q_vector->rx.ring)
5655                 clean_complete &= igb_clean_rx_irq(q_vector, budget);
5656
5657         /* If all work not completed, return budget and keep polling */
5658         if (!clean_complete)
5659                 return budget;
5660
5661         /* If not enough Rx work done, exit the polling mode */
5662         napi_complete(napi);
5663         igb_ring_irq_enable(q_vector);
5664
5665         return 0;
5666 }
5667
5668 /**
5669  * igb_clean_tx_irq - Reclaim resources after transmit completes
5670  * @q_vector: pointer to q_vector containing needed info
5671  *
5672  * returns true if ring is completely cleaned
5673  **/
5674 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
5675 {
5676         struct igb_adapter *adapter = q_vector->adapter;
5677         struct igb_ring *tx_ring = q_vector->tx.ring;
5678         struct igb_tx_buffer *tx_buffer;
5679         union e1000_adv_tx_desc *tx_desc;
5680         unsigned int total_bytes = 0, total_packets = 0;
5681         unsigned int budget = q_vector->tx.work_limit;
5682         unsigned int i = tx_ring->next_to_clean;
5683
5684         if (test_bit(__IGB_DOWN, &adapter->state))
5685                 return true;
5686
5687         tx_buffer = &tx_ring->tx_buffer_info[i];
5688         tx_desc = IGB_TX_DESC(tx_ring, i);
5689         i -= tx_ring->count;
5690
5691         do {
5692                 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
5693
5694                 /* if next_to_watch is not set then there is no work pending */
5695                 if (!eop_desc)
5696                         break;
5697
5698                 /* prevent any other reads prior to eop_desc */
5699                 rmb();
5700
5701                 /* if DD is not set pending work has not been completed */
5702                 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5703                         break;
5704
5705                 /* clear next_to_watch to prevent false hangs */
5706                 tx_buffer->next_to_watch = NULL;
5707
5708                 /* update the statistics for this packet */
5709                 total_bytes += tx_buffer->bytecount;
5710                 total_packets += tx_buffer->gso_segs;
5711
5712                 /* free the skb */
5713                 dev_kfree_skb_any(tx_buffer->skb);
5714
5715                 /* unmap skb header data */
5716                 dma_unmap_single(tx_ring->dev,
5717                                  dma_unmap_addr(tx_buffer, dma),
5718                                  dma_unmap_len(tx_buffer, len),
5719                                  DMA_TO_DEVICE);
5720
5721                 /* clear tx_buffer data */
5722                 tx_buffer->skb = NULL;
5723                 dma_unmap_len_set(tx_buffer, len, 0);
5724
5725                 /* clear last DMA location and unmap remaining buffers */
5726                 while (tx_desc != eop_desc) {
5727                         tx_buffer++;
5728                         tx_desc++;
5729                         i++;
5730                         if (unlikely(!i)) {
5731                                 i -= tx_ring->count;
5732                                 tx_buffer = tx_ring->tx_buffer_info;
5733                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
5734                         }
5735
5736                         /* unmap any remaining paged data */
5737                         if (dma_unmap_len(tx_buffer, len)) {
5738                                 dma_unmap_page(tx_ring->dev,
5739                                                dma_unmap_addr(tx_buffer, dma),
5740                                                dma_unmap_len(tx_buffer, len),
5741                                                DMA_TO_DEVICE);
5742                                 dma_unmap_len_set(tx_buffer, len, 0);
5743                         }
5744                 }
5745
5746                 /* move us one more past the eop_desc for start of next pkt */
5747                 tx_buffer++;
5748                 tx_desc++;
5749                 i++;
5750                 if (unlikely(!i)) {
5751                         i -= tx_ring->count;
5752                         tx_buffer = tx_ring->tx_buffer_info;
5753                         tx_desc = IGB_TX_DESC(tx_ring, 0);
5754                 }
5755
5756                 /* issue prefetch for next Tx descriptor */
5757                 prefetch(tx_desc);
5758
5759                 /* update budget accounting */
5760                 budget--;
5761         } while (likely(budget));
5762
5763         netdev_tx_completed_queue(txring_txq(tx_ring),
5764                                   total_packets, total_bytes);
5765         i += tx_ring->count;
5766         tx_ring->next_to_clean = i;
5767         u64_stats_update_begin(&tx_ring->tx_syncp);
5768         tx_ring->tx_stats.bytes += total_bytes;
5769         tx_ring->tx_stats.packets += total_packets;
5770         u64_stats_update_end(&tx_ring->tx_syncp);
5771         q_vector->tx.total_bytes += total_bytes;
5772         q_vector->tx.total_packets += total_packets;
5773
5774         if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
5775                 struct e1000_hw *hw = &adapter->hw;
5776
5777                 /* Detect a transmit hang in hardware, this serializes the
5778                  * check with the clearing of time_stamp and movement of i */
5779                 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5780                 if (tx_buffer->next_to_watch &&
5781                     time_after(jiffies, tx_buffer->time_stamp +
5782                                (adapter->tx_timeout_factor * HZ)) &&
5783                     !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
5784
5785                         /* detected Tx unit hang */
5786                         dev_err(tx_ring->dev,
5787                                 "Detected Tx Unit Hang\n"
5788                                 "  Tx Queue             <%d>\n"
5789                                 "  TDH                  <%x>\n"
5790                                 "  TDT                  <%x>\n"
5791                                 "  next_to_use          <%x>\n"
5792                                 "  next_to_clean        <%x>\n"
5793                                 "buffer_info[next_to_clean]\n"
5794                                 "  time_stamp           <%lx>\n"
5795                                 "  next_to_watch        <%p>\n"
5796                                 "  jiffies              <%lx>\n"
5797                                 "  desc.status          <%x>\n",
5798                                 tx_ring->queue_index,
5799                                 rd32(E1000_TDH(tx_ring->reg_idx)),
5800                                 readl(tx_ring->tail),
5801                                 tx_ring->next_to_use,
5802                                 tx_ring->next_to_clean,
5803                                 tx_buffer->time_stamp,
5804                                 tx_buffer->next_to_watch,
5805                                 jiffies,
5806                                 tx_buffer->next_to_watch->wb.status);
5807                         netif_stop_subqueue(tx_ring->netdev,
5808                                             tx_ring->queue_index);
5809
5810                         /* we are about to reset, no point in enabling stuff */
5811                         return true;
5812                 }
5813         }
5814
5815         if (unlikely(total_packets &&
5816                      netif_carrier_ok(tx_ring->netdev) &&
5817                      igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5818                 /* Make sure that anybody stopping the queue after this
5819                  * sees the new next_to_clean.
5820                  */
5821                 smp_mb();
5822                 if (__netif_subqueue_stopped(tx_ring->netdev,
5823                                              tx_ring->queue_index) &&
5824                     !(test_bit(__IGB_DOWN, &adapter->state))) {
5825                         netif_wake_subqueue(tx_ring->netdev,
5826                                             tx_ring->queue_index);
5827
5828                         u64_stats_update_begin(&tx_ring->tx_syncp);
5829                         tx_ring->tx_stats.restart_queue++;
5830                         u64_stats_update_end(&tx_ring->tx_syncp);
5831                 }
5832         }
5833
5834         return !!budget;
5835 }
5836
5837 /**
5838  * igb_reuse_rx_page - page flip buffer and store it back on the ring
5839  * @rx_ring: rx descriptor ring to store buffers on
5840  * @old_buff: donor buffer to have page reused
5841  *
5842  * Synchronizes page for reuse by the adapter
5843  **/
5844 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
5845                               struct igb_rx_buffer *old_buff)
5846 {
5847         struct igb_rx_buffer *new_buff;
5848         u16 nta = rx_ring->next_to_alloc;
5849
5850         new_buff = &rx_ring->rx_buffer_info[nta];
5851
5852         /* update, and store next to alloc */
5853         nta++;
5854         rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
5855
5856         /* transfer page from old buffer to new buffer */
5857         memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
5858
5859         /* sync the buffer for use by the device */
5860         dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
5861                                          old_buff->page_offset,
5862                                          IGB_RX_BUFSZ,
5863                                          DMA_FROM_DEVICE);
5864 }
5865
5866 /**
5867  * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
5868  * @rx_ring: rx descriptor ring to transact packets on
5869  * @rx_buffer: buffer containing page to add
5870  * @rx_desc: descriptor containing length of buffer written by hardware
5871  * @skb: sk_buff to place the data into
5872  *
5873  * This function will add the data contained in rx_buffer->page to the skb.
5874  * This is done either through a direct copy if the data in the buffer is
5875  * less than the skb header size, otherwise it will just attach the page as
5876  * a frag to the skb.
5877  *
5878  * The function will then update the page offset if necessary and return
5879  * true if the buffer can be reused by the adapter.
5880  **/
5881 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
5882                             struct igb_rx_buffer *rx_buffer,
5883                             union e1000_adv_rx_desc *rx_desc,
5884                             struct sk_buff *skb)
5885 {
5886         struct page *page = rx_buffer->page;
5887         unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
5888
5889         if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
5890                 unsigned char *va = page_address(page) + rx_buffer->page_offset;
5891
5892                 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
5893                         igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
5894                         va += IGB_TS_HDR_LEN;
5895                         size -= IGB_TS_HDR_LEN;
5896                 }
5897
5898                 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
5899
5900                 /* we can reuse buffer as-is, just make sure it is local */
5901                 if (likely(page_to_nid(page) == numa_node_id()))
5902                         return true;
5903
5904                 /* this page cannot be reused so discard it */
5905                 put_page(page);
5906                 return false;
5907         }
5908
5909         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
5910                         rx_buffer->page_offset, size, IGB_RX_BUFSZ);
5911
5912         /* avoid re-using remote pages */
5913         if (unlikely(page_to_nid(page) != numa_node_id()))
5914                 return false;
5915
5916 #if (PAGE_SIZE < 8192)
5917         /* if we are only owner of page we can reuse it */
5918         if (unlikely(page_count(page) != 1))
5919                 return false;
5920
5921         /* flip page offset to other buffer */
5922         rx_buffer->page_offset ^= IGB_RX_BUFSZ;
5923
5924         /*
5925          * since we are the only owner of the page and we need to
5926          * increment it, just set the value to 2 in order to avoid
5927          * an unnecessary locked operation
5928          */
5929         atomic_set(&page->_count, 2);
5930 #else
5931         /* move offset up to the next cache line */
5932         rx_buffer->page_offset += SKB_DATA_ALIGN(size);
5933
5934         if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
5935                 return false;
5936
5937         /* bump ref count on page before it is given to the stack */
5938         get_page(page);
5939 #endif
5940
5941         return true;
5942 }
5943
5944 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
5945                                            union e1000_adv_rx_desc *rx_desc,
5946                                            struct sk_buff *skb)
5947 {
5948         struct igb_rx_buffer *rx_buffer;
5949         struct page *page;
5950
5951         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
5952
5953         /*
5954          * This memory barrier is needed to keep us from reading
5955          * any other fields out of the rx_desc until we know the
5956          * RXD_STAT_DD bit is set
5957          */
5958         rmb();
5959
5960         page = rx_buffer->page;
5961         prefetchw(page);
5962
5963         if (likely(!skb)) {
5964                 void *page_addr = page_address(page) +
5965                                   rx_buffer->page_offset;
5966
5967                 /* prefetch first cache line of first page */
5968                 prefetch(page_addr);
5969 #if L1_CACHE_BYTES < 128
5970                 prefetch(page_addr + L1_CACHE_BYTES);
5971 #endif
5972
5973                 /* allocate a skb to store the frags */
5974                 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
5975                                                 IGB_RX_HDR_LEN);
5976                 if (unlikely(!skb)) {
5977                         rx_ring->rx_stats.alloc_failed++;
5978                         return NULL;
5979                 }
5980
5981                 /*
5982                  * we will be copying header into skb->data in
5983                  * pskb_may_pull so it is in our interest to prefetch
5984                  * it now to avoid a possible cache miss
5985                  */
5986                 prefetchw(skb->data);
5987         }
5988
5989         /* we are reusing so sync this buffer for CPU use */
5990         dma_sync_single_range_for_cpu(rx_ring->dev,
5991                                       rx_buffer->dma,
5992                                       rx_buffer->page_offset,
5993                                       IGB_RX_BUFSZ,
5994                                       DMA_FROM_DEVICE);
5995
5996         /* pull page into skb */
5997         if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
5998                 /* hand second half of page back to the ring */
5999                 igb_reuse_rx_page(rx_ring, rx_buffer);
6000         } else {
6001                 /* we are not reusing the buffer so unmap it */
6002                 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6003                                PAGE_SIZE, DMA_FROM_DEVICE);
6004         }
6005
6006         /* clear contents of rx_buffer */
6007         rx_buffer->page = NULL;
6008
6009         return skb;
6010 }
6011
6012 static inline void igb_rx_checksum(struct igb_ring *ring,
6013                                    union e1000_adv_rx_desc *rx_desc,
6014                                    struct sk_buff *skb)
6015 {
6016         skb_checksum_none_assert(skb);
6017
6018         /* Ignore Checksum bit is set */
6019         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6020                 return;
6021
6022         /* Rx checksum disabled via ethtool */
6023         if (!(ring->netdev->features & NETIF_F_RXCSUM))
6024                 return;
6025
6026         /* TCP/UDP checksum error bit is set */
6027         if (igb_test_staterr(rx_desc,
6028                              E1000_RXDEXT_STATERR_TCPE |
6029                              E1000_RXDEXT_STATERR_IPE)) {
6030                 /*
6031                  * work around errata with sctp packets where the TCPE aka
6032                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6033                  * packets, (aka let the stack check the crc32c)
6034                  */
6035                 if (!((skb->len == 60) &&
6036                       test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6037                         u64_stats_update_begin(&ring->rx_syncp);
6038                         ring->rx_stats.csum_err++;
6039                         u64_stats_update_end(&ring->rx_syncp);
6040                 }
6041                 /* let the stack verify checksum errors */
6042                 return;
6043         }
6044         /* It must be a TCP or UDP packet with a valid checksum */
6045         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6046                                       E1000_RXD_STAT_UDPCS))
6047                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6048
6049         dev_dbg(ring->dev, "cksum success: bits %08X\n",
6050                 le32_to_cpu(rx_desc->wb.upper.status_error));
6051 }
6052
6053 static inline void igb_rx_hash(struct igb_ring *ring,
6054                                union e1000_adv_rx_desc *rx_desc,
6055                                struct sk_buff *skb)
6056 {
6057         if (ring->netdev->features & NETIF_F_RXHASH)
6058                 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6059 }
6060
6061 /**
6062  * igb_is_non_eop - process handling of non-EOP buffers
6063  * @rx_ring: Rx ring being processed
6064  * @rx_desc: Rx descriptor for current buffer
6065  * @skb: current socket buffer containing buffer in progress
6066  *
6067  * This function updates next to clean.  If the buffer is an EOP buffer
6068  * this function exits returning false, otherwise it will place the
6069  * sk_buff in the next buffer to be chained and return true indicating
6070  * that this is in fact a non-EOP buffer.
6071  **/
6072 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6073                            union e1000_adv_rx_desc *rx_desc)
6074 {
6075         u32 ntc = rx_ring->next_to_clean + 1;
6076
6077         /* fetch, update, and store next to clean */
6078         ntc = (ntc < rx_ring->count) ? ntc : 0;
6079         rx_ring->next_to_clean = ntc;
6080
6081         prefetch(IGB_RX_DESC(rx_ring, ntc));
6082
6083         if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6084                 return false;
6085
6086         return true;
6087 }
6088
6089 /**
6090  * igb_get_headlen - determine size of header for LRO/GRO
6091  * @data: pointer to the start of the headers
6092  * @max_len: total length of section to find headers in
6093  *
6094  * This function is meant to determine the length of headers that will
6095  * be recognized by hardware for LRO, and GRO offloads.  The main
6096  * motivation of doing this is to only perform one pull for IPv4 TCP
6097  * packets so that we can do basic things like calculating the gso_size
6098  * based on the average data per packet.
6099  **/
6100 static unsigned int igb_get_headlen(unsigned char *data,
6101                                     unsigned int max_len)
6102 {
6103         union {
6104                 unsigned char *network;
6105                 /* l2 headers */
6106                 struct ethhdr *eth;
6107                 struct vlan_hdr *vlan;
6108                 /* l3 headers */
6109                 struct iphdr *ipv4;
6110                 struct ipv6hdr *ipv6;
6111         } hdr;
6112         __be16 protocol;
6113         u8 nexthdr = 0; /* default to not TCP */
6114         u8 hlen;
6115
6116         /* this should never happen, but better safe than sorry */
6117         if (max_len < ETH_HLEN)
6118                 return max_len;
6119
6120         /* initialize network frame pointer */
6121         hdr.network = data;
6122
6123         /* set first protocol and move network header forward */
6124         protocol = hdr.eth->h_proto;
6125         hdr.network += ETH_HLEN;
6126
6127         /* handle any vlan tag if present */
6128         if (protocol == __constant_htons(ETH_P_8021Q)) {
6129                 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6130                         return max_len;
6131
6132                 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6133                 hdr.network += VLAN_HLEN;
6134         }
6135
6136         /* handle L3 protocols */
6137         if (protocol == __constant_htons(ETH_P_IP)) {
6138                 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6139                         return max_len;
6140
6141                 /* access ihl as a u8 to avoid unaligned access on ia64 */
6142                 hlen = (hdr.network[0] & 0x0F) << 2;
6143
6144                 /* verify hlen meets minimum size requirements */
6145                 if (hlen < sizeof(struct iphdr))
6146                         return hdr.network - data;
6147
6148                 /* record next protocol if header is present */
6149                 if (!hdr.ipv4->frag_off)
6150                         nexthdr = hdr.ipv4->protocol;
6151         } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6152                 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6153                         return max_len;
6154
6155                 /* record next protocol */
6156                 nexthdr = hdr.ipv6->nexthdr;
6157                 hlen = sizeof(struct ipv6hdr);
6158         } else {
6159                 return hdr.network - data;
6160         }
6161
6162         /* relocate pointer to start of L4 header */
6163         hdr.network += hlen;
6164
6165         /* finally sort out TCP */
6166         if (nexthdr == IPPROTO_TCP) {
6167                 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6168                         return max_len;
6169
6170                 /* access doff as a u8 to avoid unaligned access on ia64 */
6171                 hlen = (hdr.network[12] & 0xF0) >> 2;
6172
6173                 /* verify hlen meets minimum size requirements */
6174                 if (hlen < sizeof(struct tcphdr))
6175                         return hdr.network - data;
6176
6177                 hdr.network += hlen;
6178         } else if (nexthdr == IPPROTO_UDP) {
6179                 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6180                         return max_len;
6181
6182                 hdr.network += sizeof(struct udphdr);
6183         }
6184
6185         /*
6186          * If everything has gone correctly hdr.network should be the
6187          * data section of the packet and will be the end of the header.
6188          * If not then it probably represents the end of the last recognized
6189          * header.
6190          */
6191         if ((hdr.network - data) < max_len)
6192                 return hdr.network - data;
6193         else
6194                 return max_len;
6195 }
6196
6197 /**
6198  * igb_pull_tail - igb specific version of skb_pull_tail
6199  * @rx_ring: rx descriptor ring packet is being transacted on
6200  * @rx_desc: pointer to the EOP Rx descriptor
6201  * @skb: pointer to current skb being adjusted
6202  *
6203  * This function is an igb specific version of __pskb_pull_tail.  The
6204  * main difference between this version and the original function is that
6205  * this function can make several assumptions about the state of things
6206  * that allow for significant optimizations versus the standard function.
6207  * As a result we can do things like drop a frag and maintain an accurate
6208  * truesize for the skb.
6209  */
6210 static void igb_pull_tail(struct igb_ring *rx_ring,
6211                           union e1000_adv_rx_desc *rx_desc,
6212                           struct sk_buff *skb)
6213 {
6214         struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6215         unsigned char *va;
6216         unsigned int pull_len;
6217
6218         /*
6219          * it is valid to use page_address instead of kmap since we are
6220          * working with pages allocated out of the lomem pool per
6221          * alloc_page(GFP_ATOMIC)
6222          */
6223         va = skb_frag_address(frag);
6224
6225         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6226                 /* retrieve timestamp from buffer */
6227                 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6228
6229                 /* update pointers to remove timestamp header */
6230                 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6231                 frag->page_offset += IGB_TS_HDR_LEN;
6232                 skb->data_len -= IGB_TS_HDR_LEN;
6233                 skb->len -= IGB_TS_HDR_LEN;
6234
6235                 /* move va to start of packet data */
6236                 va += IGB_TS_HDR_LEN;
6237         }
6238
6239         /*
6240          * we need the header to contain the greater of either ETH_HLEN or
6241          * 60 bytes if the skb->len is less than 60 for skb_pad.
6242          */
6243         pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6244
6245         /* align pull length to size of long to optimize memcpy performance */
6246         skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6247
6248         /* update all of the pointers */
6249         skb_frag_size_sub(frag, pull_len);
6250         frag->page_offset += pull_len;
6251         skb->data_len -= pull_len;
6252         skb->tail += pull_len;
6253 }
6254
6255 /**
6256  * igb_cleanup_headers - Correct corrupted or empty headers
6257  * @rx_ring: rx descriptor ring packet is being transacted on
6258  * @rx_desc: pointer to the EOP Rx descriptor
6259  * @skb: pointer to current skb being fixed
6260  *
6261  * Address the case where we are pulling data in on pages only
6262  * and as such no data is present in the skb header.
6263  *
6264  * In addition if skb is not at least 60 bytes we need to pad it so that
6265  * it is large enough to qualify as a valid Ethernet frame.
6266  *
6267  * Returns true if an error was encountered and skb was freed.
6268  **/
6269 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6270                                 union e1000_adv_rx_desc *rx_desc,
6271                                 struct sk_buff *skb)
6272 {
6273
6274         if (unlikely((igb_test_staterr(rx_desc,
6275                                        E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6276                 struct net_device *netdev = rx_ring->netdev;
6277                 if (!(netdev->features & NETIF_F_RXALL)) {
6278                         dev_kfree_skb_any(skb);
6279                         return true;
6280                 }
6281         }
6282
6283         /* place header in linear portion of buffer */
6284         if (skb_is_nonlinear(skb))
6285                 igb_pull_tail(rx_ring, rx_desc, skb);
6286
6287         /* if skb_pad returns an error the skb was freed */
6288         if (unlikely(skb->len < 60)) {
6289                 int pad_len = 60 - skb->len;
6290
6291                 if (skb_pad(skb, pad_len))
6292                         return true;
6293                 __skb_put(skb, pad_len);
6294         }
6295
6296         return false;
6297 }
6298
6299 /**
6300  * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6301  * @rx_ring: rx descriptor ring packet is being transacted on
6302  * @rx_desc: pointer to the EOP Rx descriptor
6303  * @skb: pointer to current skb being populated
6304  *
6305  * This function checks the ring, descriptor, and packet information in
6306  * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6307  * other fields within the skb.
6308  **/
6309 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6310                                    union e1000_adv_rx_desc *rx_desc,
6311                                    struct sk_buff *skb)
6312 {
6313         struct net_device *dev = rx_ring->netdev;
6314
6315         igb_rx_hash(rx_ring, rx_desc, skb);
6316
6317         igb_rx_checksum(rx_ring, rx_desc, skb);
6318
6319         igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
6320
6321         if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6322             igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6323                 u16 vid;
6324                 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6325                     test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6326                         vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6327                 else
6328                         vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6329
6330                 __vlan_hwaccel_put_tag(skb, vid);
6331         }
6332
6333         skb_record_rx_queue(skb, rx_ring->queue_index);
6334
6335         skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6336 }
6337
6338 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6339 {
6340         struct igb_ring *rx_ring = q_vector->rx.ring;
6341         struct sk_buff *skb = rx_ring->skb;
6342         unsigned int total_bytes = 0, total_packets = 0;
6343         u16 cleaned_count = igb_desc_unused(rx_ring);
6344
6345         do {
6346                 union e1000_adv_rx_desc *rx_desc;
6347
6348                 /* return some buffers to hardware, one at a time is too slow */
6349                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6350                         igb_alloc_rx_buffers(rx_ring, cleaned_count);
6351                         cleaned_count = 0;
6352                 }
6353
6354                 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6355
6356                 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6357                         break;
6358
6359                 /* retrieve a buffer from the ring */
6360                 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6361
6362                 /* exit if we failed to retrieve a buffer */
6363                 if (!skb)
6364                         break;
6365
6366                 cleaned_count++;
6367
6368                 /* fetch next buffer in frame if non-eop */
6369                 if (igb_is_non_eop(rx_ring, rx_desc))
6370                         continue;
6371
6372                 /* verify the packet layout is correct */
6373                 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6374                         skb = NULL;
6375                         continue;
6376                 }
6377
6378                 /* probably a little skewed due to removing CRC */
6379                 total_bytes += skb->len;
6380
6381                 /* populate checksum, timestamp, VLAN, and protocol */
6382                 igb_process_skb_fields(rx_ring, rx_desc, skb);
6383
6384                 napi_gro_receive(&q_vector->napi, skb);
6385
6386                 /* reset skb pointer */
6387                 skb = NULL;
6388
6389                 /* update budget accounting */
6390                 total_packets++;
6391         } while (likely(total_packets < budget));
6392
6393         /* place incomplete frames back on ring for completion */
6394         rx_ring->skb = skb;
6395
6396         u64_stats_update_begin(&rx_ring->rx_syncp);
6397         rx_ring->rx_stats.packets += total_packets;
6398         rx_ring->rx_stats.bytes += total_bytes;
6399         u64_stats_update_end(&rx_ring->rx_syncp);
6400         q_vector->rx.total_packets += total_packets;
6401         q_vector->rx.total_bytes += total_bytes;
6402
6403         if (cleaned_count)
6404                 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6405
6406         return (total_packets < budget);
6407 }
6408
6409 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6410                                   struct igb_rx_buffer *bi)
6411 {
6412         struct page *page = bi->page;
6413         dma_addr_t dma;
6414
6415         /* since we are recycling buffers we should seldom need to alloc */
6416         if (likely(page))
6417                 return true;
6418
6419         /* alloc new page for storage */
6420         page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6421         if (unlikely(!page)) {
6422                 rx_ring->rx_stats.alloc_failed++;
6423                 return false;
6424         }
6425
6426         /* map page for use */
6427         dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6428
6429         /*
6430          * if mapping failed free memory back to system since
6431          * there isn't much point in holding memory we can't use
6432          */
6433         if (dma_mapping_error(rx_ring->dev, dma)) {
6434                 __free_page(page);
6435
6436                 rx_ring->rx_stats.alloc_failed++;
6437                 return false;
6438         }
6439
6440         bi->dma = dma;
6441         bi->page = page;
6442         bi->page_offset = 0;
6443
6444         return true;
6445 }
6446
6447 /**
6448  * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6449  * @adapter: address of board private structure
6450  **/
6451 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6452 {
6453         union e1000_adv_rx_desc *rx_desc;
6454         struct igb_rx_buffer *bi;
6455         u16 i = rx_ring->next_to_use;
6456
6457         /* nothing to do */
6458         if (!cleaned_count)
6459                 return;
6460
6461         rx_desc = IGB_RX_DESC(rx_ring, i);
6462         bi = &rx_ring->rx_buffer_info[i];
6463         i -= rx_ring->count;
6464
6465         do {
6466                 if (!igb_alloc_mapped_page(rx_ring, bi))
6467                         break;
6468
6469                 /*
6470                  * Refresh the desc even if buffer_addrs didn't change
6471                  * because each write-back erases this info.
6472                  */
6473                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
6474
6475                 rx_desc++;
6476                 bi++;
6477                 i++;
6478                 if (unlikely(!i)) {
6479                         rx_desc = IGB_RX_DESC(rx_ring, 0);
6480                         bi = rx_ring->rx_buffer_info;
6481                         i -= rx_ring->count;
6482                 }
6483
6484                 /* clear the hdr_addr for the next_to_use descriptor */
6485                 rx_desc->read.hdr_addr = 0;
6486
6487                 cleaned_count--;
6488         } while (cleaned_count);
6489
6490         i += rx_ring->count;
6491
6492         if (rx_ring->next_to_use != i) {
6493                 /* record the next descriptor to use */
6494                 rx_ring->next_to_use = i;
6495
6496                 /* update next to alloc since we have filled the ring */
6497                 rx_ring->next_to_alloc = i;
6498
6499                 /*
6500                  * Force memory writes to complete before letting h/w
6501                  * know there are new descriptors to fetch.  (Only
6502                  * applicable for weak-ordered memory model archs,
6503                  * such as IA-64).
6504                  */
6505                 wmb();
6506                 writel(i, rx_ring->tail);
6507         }
6508 }
6509
6510 /**
6511  * igb_mii_ioctl -
6512  * @netdev:
6513  * @ifreq:
6514  * @cmd:
6515  **/
6516 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6517 {
6518         struct igb_adapter *adapter = netdev_priv(netdev);
6519         struct mii_ioctl_data *data = if_mii(ifr);
6520
6521         if (adapter->hw.phy.media_type != e1000_media_type_copper)
6522                 return -EOPNOTSUPP;
6523
6524         switch (cmd) {
6525         case SIOCGMIIPHY:
6526                 data->phy_id = adapter->hw.phy.addr;
6527                 break;
6528         case SIOCGMIIREG:
6529                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6530                                      &data->val_out))
6531                         return -EIO;
6532                 break;
6533         case SIOCSMIIREG:
6534         default:
6535                 return -EOPNOTSUPP;
6536         }
6537         return 0;
6538 }
6539
6540 /**
6541  * igb_ioctl -
6542  * @netdev:
6543  * @ifreq:
6544  * @cmd:
6545  **/
6546 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6547 {
6548         switch (cmd) {
6549         case SIOCGMIIPHY:
6550         case SIOCGMIIREG:
6551         case SIOCSMIIREG:
6552                 return igb_mii_ioctl(netdev, ifr, cmd);
6553         case SIOCSHWTSTAMP:
6554                 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
6555         default:
6556                 return -EOPNOTSUPP;
6557         }
6558 }
6559
6560 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6561 {
6562         struct igb_adapter *adapter = hw->back;
6563
6564         if (pcie_capability_read_word(adapter->pdev, reg, value))
6565                 return -E1000_ERR_CONFIG;
6566
6567         return 0;
6568 }
6569
6570 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6571 {
6572         struct igb_adapter *adapter = hw->back;
6573
6574         if (pcie_capability_write_word(adapter->pdev, reg, *value))
6575                 return -E1000_ERR_CONFIG;
6576
6577         return 0;
6578 }
6579
6580 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
6581 {
6582         struct igb_adapter *adapter = netdev_priv(netdev);
6583         struct e1000_hw *hw = &adapter->hw;
6584         u32 ctrl, rctl;
6585         bool enable = !!(features & NETIF_F_HW_VLAN_RX);
6586
6587         if (enable) {
6588                 /* enable VLAN tag insert/strip */
6589                 ctrl = rd32(E1000_CTRL);
6590                 ctrl |= E1000_CTRL_VME;
6591                 wr32(E1000_CTRL, ctrl);
6592
6593                 /* Disable CFI check */
6594                 rctl = rd32(E1000_RCTL);
6595                 rctl &= ~E1000_RCTL_CFIEN;
6596                 wr32(E1000_RCTL, rctl);
6597         } else {
6598                 /* disable VLAN tag insert/strip */
6599                 ctrl = rd32(E1000_CTRL);
6600                 ctrl &= ~E1000_CTRL_VME;
6601                 wr32(E1000_CTRL, ctrl);
6602         }
6603
6604         igb_rlpml_set(adapter);
6605 }
6606
6607 static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
6608 {
6609         struct igb_adapter *adapter = netdev_priv(netdev);
6610         struct e1000_hw *hw = &adapter->hw;
6611         int pf_id = adapter->vfs_allocated_count;
6612
6613         /* attempt to add filter to vlvf array */
6614         igb_vlvf_set(adapter, vid, true, pf_id);
6615
6616         /* add the filter since PF can receive vlans w/o entry in vlvf */
6617         igb_vfta_set(hw, vid, true);
6618
6619         set_bit(vid, adapter->active_vlans);
6620
6621         return 0;
6622 }
6623
6624 static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
6625 {
6626         struct igb_adapter *adapter = netdev_priv(netdev);
6627         struct e1000_hw *hw = &adapter->hw;
6628         int pf_id = adapter->vfs_allocated_count;
6629         s32 err;
6630
6631         /* remove vlan from VLVF table array */
6632         err = igb_vlvf_set(adapter, vid, false, pf_id);
6633
6634         /* if vid was not present in VLVF just remove it from table */
6635         if (err)
6636                 igb_vfta_set(hw, vid, false);
6637
6638         clear_bit(vid, adapter->active_vlans);
6639
6640         return 0;
6641 }
6642
6643 static void igb_restore_vlan(struct igb_adapter *adapter)
6644 {
6645         u16 vid;
6646
6647         igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6648
6649         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6650                 igb_vlan_rx_add_vid(adapter->netdev, vid);
6651 }
6652
6653 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
6654 {
6655         struct pci_dev *pdev = adapter->pdev;
6656         struct e1000_mac_info *mac = &adapter->hw.mac;
6657
6658         mac->autoneg = 0;
6659
6660         /* Make sure dplx is at most 1 bit and lsb of speed is not set
6661          * for the switch() below to work */
6662         if ((spd & 1) || (dplx & ~1))
6663                 goto err_inval;
6664
6665         /* Fiber NIC's only allow 1000 Gbps Full duplex */
6666         if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
6667             spd != SPEED_1000 &&
6668             dplx != DUPLEX_FULL)
6669                 goto err_inval;
6670
6671         switch (spd + dplx) {
6672         case SPEED_10 + DUPLEX_HALF:
6673                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6674                 break;
6675         case SPEED_10 + DUPLEX_FULL:
6676                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6677                 break;
6678         case SPEED_100 + DUPLEX_HALF:
6679                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6680                 break;
6681         case SPEED_100 + DUPLEX_FULL:
6682                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6683                 break;
6684         case SPEED_1000 + DUPLEX_FULL:
6685                 mac->autoneg = 1;
6686                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6687                 break;
6688         case SPEED_1000 + DUPLEX_HALF: /* not supported */
6689         default:
6690                 goto err_inval;
6691         }
6692
6693         /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6694         adapter->hw.phy.mdix = AUTO_ALL_MODES;
6695
6696         return 0;
6697
6698 err_inval:
6699         dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6700         return -EINVAL;
6701 }
6702
6703 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6704                           bool runtime)
6705 {
6706         struct net_device *netdev = pci_get_drvdata(pdev);
6707         struct igb_adapter *adapter = netdev_priv(netdev);
6708         struct e1000_hw *hw = &adapter->hw;
6709         u32 ctrl, rctl, status;
6710         u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6711 #ifdef CONFIG_PM
6712         int retval = 0;
6713 #endif
6714
6715         netif_device_detach(netdev);
6716
6717         if (netif_running(netdev))
6718                 __igb_close(netdev, true);
6719
6720         igb_clear_interrupt_scheme(adapter);
6721
6722 #ifdef CONFIG_PM
6723         retval = pci_save_state(pdev);
6724         if (retval)
6725                 return retval;
6726 #endif
6727
6728         status = rd32(E1000_STATUS);
6729         if (status & E1000_STATUS_LU)
6730                 wufc &= ~E1000_WUFC_LNKC;
6731
6732         if (wufc) {
6733                 igb_setup_rctl(adapter);
6734                 igb_set_rx_mode(netdev);
6735
6736                 /* turn on all-multi mode if wake on multicast is enabled */
6737                 if (wufc & E1000_WUFC_MC) {
6738                         rctl = rd32(E1000_RCTL);
6739                         rctl |= E1000_RCTL_MPE;
6740                         wr32(E1000_RCTL, rctl);
6741                 }
6742
6743                 ctrl = rd32(E1000_CTRL);
6744                 /* advertise wake from D3Cold */
6745                 #define E1000_CTRL_ADVD3WUC 0x00100000
6746                 /* phy power management enable */
6747                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6748                 ctrl |= E1000_CTRL_ADVD3WUC;
6749                 wr32(E1000_CTRL, ctrl);
6750
6751                 /* Allow time for pending master requests to run */
6752                 igb_disable_pcie_master(hw);
6753
6754                 wr32(E1000_WUC, E1000_WUC_PME_EN);
6755                 wr32(E1000_WUFC, wufc);
6756         } else {
6757                 wr32(E1000_WUC, 0);
6758                 wr32(E1000_WUFC, 0);
6759         }
6760
6761         *enable_wake = wufc || adapter->en_mng_pt;
6762         if (!*enable_wake)
6763                 igb_power_down_link(adapter);
6764         else
6765                 igb_power_up_link(adapter);
6766
6767         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
6768          * would have already happened in close and is redundant. */
6769         igb_release_hw_control(adapter);
6770
6771         pci_disable_device(pdev);
6772
6773         return 0;
6774 }
6775
6776 #ifdef CONFIG_PM
6777 #ifdef CONFIG_PM_SLEEP
6778 static int igb_suspend(struct device *dev)
6779 {
6780         int retval;
6781         bool wake;
6782         struct pci_dev *pdev = to_pci_dev(dev);
6783
6784         retval = __igb_shutdown(pdev, &wake, 0);
6785         if (retval)
6786                 return retval;
6787
6788         if (wake) {
6789                 pci_prepare_to_sleep(pdev);
6790         } else {
6791                 pci_wake_from_d3(pdev, false);
6792                 pci_set_power_state(pdev, PCI_D3hot);
6793         }
6794
6795         return 0;
6796 }
6797 #endif /* CONFIG_PM_SLEEP */
6798
6799 static int igb_resume(struct device *dev)
6800 {
6801         struct pci_dev *pdev = to_pci_dev(dev);
6802         struct net_device *netdev = pci_get_drvdata(pdev);
6803         struct igb_adapter *adapter = netdev_priv(netdev);
6804         struct e1000_hw *hw = &adapter->hw;
6805         u32 err;
6806
6807         pci_set_power_state(pdev, PCI_D0);
6808         pci_restore_state(pdev);
6809         pci_save_state(pdev);
6810
6811         err = pci_enable_device_mem(pdev);
6812         if (err) {
6813                 dev_err(&pdev->dev,
6814                         "igb: Cannot enable PCI device from suspend\n");
6815                 return err;
6816         }
6817         pci_set_master(pdev);
6818
6819         pci_enable_wake(pdev, PCI_D3hot, 0);
6820         pci_enable_wake(pdev, PCI_D3cold, 0);
6821
6822         if (igb_init_interrupt_scheme(adapter)) {
6823                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6824                 return -ENOMEM;
6825         }
6826
6827         igb_reset(adapter);
6828
6829         /* let the f/w know that the h/w is now under the control of the
6830          * driver. */
6831         igb_get_hw_control(adapter);
6832
6833         wr32(E1000_WUS, ~0);
6834
6835         if (netdev->flags & IFF_UP) {
6836                 rtnl_lock();
6837                 err = __igb_open(netdev, true);
6838                 rtnl_unlock();
6839                 if (err)
6840                         return err;
6841         }
6842
6843         netif_device_attach(netdev);
6844         return 0;
6845 }
6846
6847 #ifdef CONFIG_PM_RUNTIME
6848 static int igb_runtime_idle(struct device *dev)
6849 {
6850         struct pci_dev *pdev = to_pci_dev(dev);
6851         struct net_device *netdev = pci_get_drvdata(pdev);
6852         struct igb_adapter *adapter = netdev_priv(netdev);
6853
6854         if (!igb_has_link(adapter))
6855                 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
6856
6857         return -EBUSY;
6858 }
6859
6860 static int igb_runtime_suspend(struct device *dev)
6861 {
6862         struct pci_dev *pdev = to_pci_dev(dev);
6863         int retval;
6864         bool wake;
6865
6866         retval = __igb_shutdown(pdev, &wake, 1);
6867         if (retval)
6868                 return retval;
6869
6870         if (wake) {
6871                 pci_prepare_to_sleep(pdev);
6872         } else {
6873                 pci_wake_from_d3(pdev, false);
6874                 pci_set_power_state(pdev, PCI_D3hot);
6875         }
6876
6877         return 0;
6878 }
6879
6880 static int igb_runtime_resume(struct device *dev)
6881 {
6882         return igb_resume(dev);
6883 }
6884 #endif /* CONFIG_PM_RUNTIME */
6885 #endif
6886
6887 static void igb_shutdown(struct pci_dev *pdev)
6888 {
6889         bool wake;
6890
6891         __igb_shutdown(pdev, &wake, 0);
6892
6893         if (system_state == SYSTEM_POWER_OFF) {
6894                 pci_wake_from_d3(pdev, wake);
6895                 pci_set_power_state(pdev, PCI_D3hot);
6896         }
6897 }
6898
6899 #ifdef CONFIG_NET_POLL_CONTROLLER
6900 /*
6901  * Polling 'interrupt' - used by things like netconsole to send skbs
6902  * without having to re-enable interrupts. It's not called while
6903  * the interrupt routine is executing.
6904  */
6905 static void igb_netpoll(struct net_device *netdev)
6906 {
6907         struct igb_adapter *adapter = netdev_priv(netdev);
6908         struct e1000_hw *hw = &adapter->hw;
6909         struct igb_q_vector *q_vector;
6910         int i;
6911
6912         for (i = 0; i < adapter->num_q_vectors; i++) {
6913                 q_vector = adapter->q_vector[i];
6914                 if (adapter->msix_entries)
6915                         wr32(E1000_EIMC, q_vector->eims_value);
6916                 else
6917                         igb_irq_disable(adapter);
6918                 napi_schedule(&q_vector->napi);
6919         }
6920 }
6921 #endif /* CONFIG_NET_POLL_CONTROLLER */
6922
6923 /**
6924  * igb_io_error_detected - called when PCI error is detected
6925  * @pdev: Pointer to PCI device
6926  * @state: The current pci connection state
6927  *
6928  * This function is called after a PCI bus error affecting
6929  * this device has been detected.
6930  */
6931 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6932                                               pci_channel_state_t state)
6933 {
6934         struct net_device *netdev = pci_get_drvdata(pdev);
6935         struct igb_adapter *adapter = netdev_priv(netdev);
6936
6937         netif_device_detach(netdev);
6938
6939         if (state == pci_channel_io_perm_failure)
6940                 return PCI_ERS_RESULT_DISCONNECT;
6941
6942         if (netif_running(netdev))
6943                 igb_down(adapter);
6944         pci_disable_device(pdev);
6945
6946         /* Request a slot slot reset. */
6947         return PCI_ERS_RESULT_NEED_RESET;
6948 }
6949
6950 /**
6951  * igb_io_slot_reset - called after the pci bus has been reset.
6952  * @pdev: Pointer to PCI device
6953  *
6954  * Restart the card from scratch, as if from a cold-boot. Implementation
6955  * resembles the first-half of the igb_resume routine.
6956  */
6957 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6958 {
6959         struct net_device *netdev = pci_get_drvdata(pdev);
6960         struct igb_adapter *adapter = netdev_priv(netdev);
6961         struct e1000_hw *hw = &adapter->hw;
6962         pci_ers_result_t result;
6963         int err;
6964
6965         if (pci_enable_device_mem(pdev)) {
6966                 dev_err(&pdev->dev,
6967                         "Cannot re-enable PCI device after reset.\n");
6968                 result = PCI_ERS_RESULT_DISCONNECT;
6969         } else {
6970                 pci_set_master(pdev);
6971                 pci_restore_state(pdev);
6972                 pci_save_state(pdev);
6973
6974                 pci_enable_wake(pdev, PCI_D3hot, 0);
6975                 pci_enable_wake(pdev, PCI_D3cold, 0);
6976
6977                 igb_reset(adapter);
6978                 wr32(E1000_WUS, ~0);
6979                 result = PCI_ERS_RESULT_RECOVERED;
6980         }
6981
6982         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6983         if (err) {
6984                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6985                         "failed 0x%0x\n", err);
6986                 /* non-fatal, continue */
6987         }
6988
6989         return result;
6990 }
6991
6992 /**
6993  * igb_io_resume - called when traffic can start flowing again.
6994  * @pdev: Pointer to PCI device
6995  *
6996  * This callback is called when the error recovery driver tells us that
6997  * its OK to resume normal operation. Implementation resembles the
6998  * second-half of the igb_resume routine.
6999  */
7000 static void igb_io_resume(struct pci_dev *pdev)
7001 {
7002         struct net_device *netdev = pci_get_drvdata(pdev);
7003         struct igb_adapter *adapter = netdev_priv(netdev);
7004
7005         if (netif_running(netdev)) {
7006                 if (igb_up(adapter)) {
7007                         dev_err(&pdev->dev, "igb_up failed after reset\n");
7008                         return;
7009                 }
7010         }
7011
7012         netif_device_attach(netdev);
7013
7014         /* let the f/w know that the h/w is now under the control of the
7015          * driver. */
7016         igb_get_hw_control(adapter);
7017 }
7018
7019 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7020                              u8 qsel)
7021 {
7022         u32 rar_low, rar_high;
7023         struct e1000_hw *hw = &adapter->hw;
7024
7025         /* HW expects these in little endian so we reverse the byte order
7026          * from network order (big endian) to little endian
7027          */
7028         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7029                   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7030         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7031
7032         /* Indicate to hardware the Address is Valid. */
7033         rar_high |= E1000_RAH_AV;
7034
7035         if (hw->mac.type == e1000_82575)
7036                 rar_high |= E1000_RAH_POOL_1 * qsel;
7037         else
7038                 rar_high |= E1000_RAH_POOL_1 << qsel;
7039
7040         wr32(E1000_RAL(index), rar_low);
7041         wrfl();
7042         wr32(E1000_RAH(index), rar_high);
7043         wrfl();
7044 }
7045
7046 static int igb_set_vf_mac(struct igb_adapter *adapter,
7047                           int vf, unsigned char *mac_addr)
7048 {
7049         struct e1000_hw *hw = &adapter->hw;
7050         /* VF MAC addresses start at end of receive addresses and moves
7051          * torwards the first, as a result a collision should not be possible */
7052         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7053
7054         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7055
7056         igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7057
7058         return 0;
7059 }
7060
7061 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7062 {
7063         struct igb_adapter *adapter = netdev_priv(netdev);
7064         if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7065                 return -EINVAL;
7066         adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7067         dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7068         dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7069                                       " change effective.");
7070         if (test_bit(__IGB_DOWN, &adapter->state)) {
7071                 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7072                          " but the PF device is not up.\n");
7073                 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7074                          " attempting to use the VF device.\n");
7075         }
7076         return igb_set_vf_mac(adapter, vf, mac);
7077 }
7078
7079 static int igb_link_mbps(int internal_link_speed)
7080 {
7081         switch (internal_link_speed) {
7082         case SPEED_100:
7083                 return 100;
7084         case SPEED_1000:
7085                 return 1000;
7086         default:
7087                 return 0;
7088         }
7089 }
7090
7091 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7092                                   int link_speed)
7093 {
7094         int rf_dec, rf_int;
7095         u32 bcnrc_val;
7096
7097         if (tx_rate != 0) {
7098                 /* Calculate the rate factor values to set */
7099                 rf_int = link_speed / tx_rate;
7100                 rf_dec = (link_speed - (rf_int * tx_rate));
7101                 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7102
7103                 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7104                 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7105                                E1000_RTTBCNRC_RF_INT_MASK);
7106                 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7107         } else {
7108                 bcnrc_val = 0;
7109         }
7110
7111         wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7112         /*
7113          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7114          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7115          */
7116         wr32(E1000_RTTBCNRM, 0x14);
7117         wr32(E1000_RTTBCNRC, bcnrc_val);
7118 }
7119
7120 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7121 {
7122         int actual_link_speed, i;
7123         bool reset_rate = false;
7124
7125         /* VF TX rate limit was not set or not supported */
7126         if ((adapter->vf_rate_link_speed == 0) ||
7127             (adapter->hw.mac.type != e1000_82576))
7128                 return;
7129
7130         actual_link_speed = igb_link_mbps(adapter->link_speed);
7131         if (actual_link_speed != adapter->vf_rate_link_speed) {
7132                 reset_rate = true;
7133                 adapter->vf_rate_link_speed = 0;
7134                 dev_info(&adapter->pdev->dev,
7135                          "Link speed has been changed. VF Transmit "
7136                          "rate is disabled\n");
7137         }
7138
7139         for (i = 0; i < adapter->vfs_allocated_count; i++) {
7140                 if (reset_rate)
7141                         adapter->vf_data[i].tx_rate = 0;
7142
7143                 igb_set_vf_rate_limit(&adapter->hw, i,
7144                                       adapter->vf_data[i].tx_rate,
7145                                       actual_link_speed);
7146         }
7147 }
7148
7149 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7150 {
7151         struct igb_adapter *adapter = netdev_priv(netdev);
7152         struct e1000_hw *hw = &adapter->hw;
7153         int actual_link_speed;
7154
7155         if (hw->mac.type != e1000_82576)
7156                 return -EOPNOTSUPP;
7157
7158         actual_link_speed = igb_link_mbps(adapter->link_speed);
7159         if ((vf >= adapter->vfs_allocated_count) ||
7160             (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7161             (tx_rate < 0) || (tx_rate > actual_link_speed))
7162                 return -EINVAL;
7163
7164         adapter->vf_rate_link_speed = actual_link_speed;
7165         adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7166         igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7167
7168         return 0;
7169 }
7170
7171 static int igb_ndo_get_vf_config(struct net_device *netdev,
7172                                  int vf, struct ifla_vf_info *ivi)
7173 {
7174         struct igb_adapter *adapter = netdev_priv(netdev);
7175         if (vf >= adapter->vfs_allocated_count)
7176                 return -EINVAL;
7177         ivi->vf = vf;
7178         memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7179         ivi->tx_rate = adapter->vf_data[vf].tx_rate;
7180         ivi->vlan = adapter->vf_data[vf].pf_vlan;
7181         ivi->qos = adapter->vf_data[vf].pf_qos;
7182         return 0;
7183 }
7184
7185 static void igb_vmm_control(struct igb_adapter *adapter)
7186 {
7187         struct e1000_hw *hw = &adapter->hw;
7188         u32 reg;
7189
7190         switch (hw->mac.type) {
7191         case e1000_82575:
7192         case e1000_i210:
7193         case e1000_i211:
7194         default:
7195                 /* replication is not supported for 82575 */
7196                 return;
7197         case e1000_82576:
7198                 /* notify HW that the MAC is adding vlan tags */
7199                 reg = rd32(E1000_DTXCTL);
7200                 reg |= E1000_DTXCTL_VLAN_ADDED;
7201                 wr32(E1000_DTXCTL, reg);
7202         case e1000_82580:
7203                 /* enable replication vlan tag stripping */
7204                 reg = rd32(E1000_RPLOLR);
7205                 reg |= E1000_RPLOLR_STRVLAN;
7206                 wr32(E1000_RPLOLR, reg);
7207         case e1000_i350:
7208                 /* none of the above registers are supported by i350 */
7209                 break;
7210         }
7211
7212         if (adapter->vfs_allocated_count) {
7213                 igb_vmdq_set_loopback_pf(hw, true);
7214                 igb_vmdq_set_replication_pf(hw, true);
7215                 igb_vmdq_set_anti_spoofing_pf(hw, true,
7216                                                 adapter->vfs_allocated_count);
7217         } else {
7218                 igb_vmdq_set_loopback_pf(hw, false);
7219                 igb_vmdq_set_replication_pf(hw, false);
7220         }
7221 }
7222
7223 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7224 {
7225         struct e1000_hw *hw = &adapter->hw;
7226         u32 dmac_thr;
7227         u16 hwm;
7228
7229         if (hw->mac.type > e1000_82580) {
7230                 if (adapter->flags & IGB_FLAG_DMAC) {
7231                         u32 reg;
7232
7233                         /* force threshold to 0. */
7234                         wr32(E1000_DMCTXTH, 0);
7235
7236                         /*
7237                          * DMA Coalescing high water mark needs to be greater
7238                          * than the Rx threshold. Set hwm to PBA - max frame
7239                          * size in 16B units, capping it at PBA - 6KB.
7240                          */
7241                         hwm = 64 * pba - adapter->max_frame_size / 16;
7242                         if (hwm < 64 * (pba - 6))
7243                                 hwm = 64 * (pba - 6);
7244                         reg = rd32(E1000_FCRTC);
7245                         reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7246                         reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7247                                 & E1000_FCRTC_RTH_COAL_MASK);
7248                         wr32(E1000_FCRTC, reg);
7249
7250                         /*
7251                          * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7252                          * frame size, capping it at PBA - 10KB.
7253                          */
7254                         dmac_thr = pba - adapter->max_frame_size / 512;
7255                         if (dmac_thr < pba - 10)
7256                                 dmac_thr = pba - 10;
7257                         reg = rd32(E1000_DMACR);
7258                         reg &= ~E1000_DMACR_DMACTHR_MASK;
7259                         reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7260                                 & E1000_DMACR_DMACTHR_MASK);
7261
7262                         /* transition to L0x or L1 if available..*/
7263                         reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7264
7265                         /* watchdog timer= +-1000 usec in 32usec intervals */
7266                         reg |= (1000 >> 5);
7267
7268                         /* Disable BMC-to-OS Watchdog Enable */
7269                         reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7270                         wr32(E1000_DMACR, reg);
7271
7272                         /*
7273                          * no lower threshold to disable
7274                          * coalescing(smart fifb)-UTRESH=0
7275                          */
7276                         wr32(E1000_DMCRTRH, 0);
7277
7278                         reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7279
7280                         wr32(E1000_DMCTLX, reg);
7281
7282                         /*
7283                          * free space in tx packet buffer to wake from
7284                          * DMA coal
7285                          */
7286                         wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7287                              (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7288
7289                         /*
7290                          * make low power state decision controlled
7291                          * by DMA coal
7292                          */
7293                         reg = rd32(E1000_PCIEMISC);
7294                         reg &= ~E1000_PCIEMISC_LX_DECISION;
7295                         wr32(E1000_PCIEMISC, reg);
7296                 } /* endif adapter->dmac is not disabled */
7297         } else if (hw->mac.type == e1000_82580) {
7298                 u32 reg = rd32(E1000_PCIEMISC);
7299                 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7300                 wr32(E1000_DMACR, 0);
7301         }
7302 }
7303
7304 /* igb_main.c */