Pileus Git - ~andy/linux/blob - drivers/net/ethernet/intel/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29
  30 #include <linux/module.h>
  31 #include <linux/types.h>
  32 #include <linux/init.h>
  33 #include <linux/bitops.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/ipv6.h>
  38 #include <linux/slab.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/net_tstamp.h>
  42 #include <linux/mii.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/pci.h>
  47 #include <linux/pci-aspm.h>
  48 #include <linux/delay.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/ip.h>
  51 #include <linux/tcp.h>
  52 #include <linux/sctp.h>
  53 #include <linux/if_ether.h>
  54 #include <linux/aer.h>
  55 #include <linux/prefetch.h>
  56 #include <linux/pm_runtime.h>
  57 #ifdef CONFIG_IGB_DCA
  58 #include <linux/dca.h>
  59 #endif
  60 #include "igb.h"
  61
  62 #define MAJ 4
  63 #define MIN 0
  64 #define BUILD 17
  65 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  66 __stringify(BUILD) "-k"
  67 char igb_driver_name[] = "igb";
  68 char igb_driver_version[] = DRV_VERSION;
  69 static const char igb_driver_string[] =
  70                                 "Intel(R) Gigabit Ethernet Network Driver";
  71 static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation.";
  72
  73 static const struct e1000_info *igb_info_tbl[] = {
  74         [board_82575] = &e1000_82575_info,
  75 };
  76
  77 static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
  78         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
  79         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
  80         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
  81         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
  82         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
  83         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
  84         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
  85         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
  86         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
  87         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
  88         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
  89         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
  90         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
  91         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
  92         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
  93         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
  94         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
  95         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
  96         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
  97         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  98         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  99         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
 100         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
 101         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
 102         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
 103         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
 104         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
 105         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
 106         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
 107         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
 108         /* required last entry */
 109         {0, }
 110 };
 111
 112 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
 113
 114 void igb_reset(struct igb_adapter *);
 115 static int igb_setup_all_tx_resources(struct igb_adapter *);
 116 static int igb_setup_all_rx_resources(struct igb_adapter *);
 117 static void igb_free_all_tx_resources(struct igb_adapter *);
 118 static void igb_free_all_rx_resources(struct igb_adapter *);
 119 static void igb_setup_mrqc(struct igb_adapter *);
 120 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
 121 static void __devexit igb_remove(struct pci_dev *pdev);
 122 static int igb_sw_init(struct igb_adapter *);
 123 static int igb_open(struct net_device *);
 124 static int igb_close(struct net_device *);
 125 static void igb_configure_tx(struct igb_adapter *);
 126 static void igb_configure_rx(struct igb_adapter *);
 127 static void igb_clean_all_tx_rings(struct igb_adapter *);
 128 static void igb_clean_all_rx_rings(struct igb_adapter *);
 129 static void igb_clean_tx_ring(struct igb_ring *);
 130 static void igb_clean_rx_ring(struct igb_ring *);
 131 static void igb_set_rx_mode(struct net_device *);
 132 static void igb_update_phy_info(unsigned long);
 133 static void igb_watchdog(unsigned long);
 134 static void igb_watchdog_task(struct work_struct *);
 135 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
 136 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
 137                                                  struct rtnl_link_stats64 *stats);
 138 static int igb_change_mtu(struct net_device *, int);
 139 static int igb_set_mac(struct net_device *, void *);
 140 static void igb_set_uta(struct igb_adapter *adapter);
 141 static irqreturn_t igb_intr(int irq, void *);
 142 static irqreturn_t igb_intr_msi(int irq, void *);
 143 static irqreturn_t igb_msix_other(int irq, void *);
 144 static irqreturn_t igb_msix_ring(int irq, void *);
 145 #ifdef CONFIG_IGB_DCA
 146 static void igb_update_dca(struct igb_q_vector *);
 147 static void igb_setup_dca(struct igb_adapter *);
 148 #endif /* CONFIG_IGB_DCA */
 149 static int igb_poll(struct napi_struct *, int);
 150 static bool igb_clean_tx_irq(struct igb_q_vector *);
 151 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
 152 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 153 static void igb_tx_timeout(struct net_device *);
 154 static void igb_reset_task(struct work_struct *);
 155 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
 156 static int igb_vlan_rx_add_vid(struct net_device *, u16);
 157 static int igb_vlan_rx_kill_vid(struct net_device *, u16);
 158 static void igb_restore_vlan(struct igb_adapter *);
 159 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
 160 static void igb_ping_all_vfs(struct igb_adapter *);
 161 static void igb_msg_task(struct igb_adapter *);
 162 static void igb_vmm_control(struct igb_adapter *);
 163 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
 164 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 165 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
 166 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
 167                                int vf, u16 vlan, u8 qos);
 168 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
 169 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
 170                                  struct ifla_vf_info *ivi);
 171 static void igb_check_vf_rate_limit(struct igb_adapter *);
 172
 173 #ifdef CONFIG_PCI_IOV
 174 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
 175 static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
 176 #endif
 177
 178 #ifdef CONFIG_PM
 179 #ifdef CONFIG_PM_SLEEP
 180 static int igb_suspend(struct device *);
 181 #endif
 182 static int igb_resume(struct device *);
 183 #ifdef CONFIG_PM_RUNTIME
 184 static int igb_runtime_suspend(struct device *dev);
 185 static int igb_runtime_resume(struct device *dev);
 186 static int igb_runtime_idle(struct device *dev);
 187 #endif
 188 static const struct dev_pm_ops igb_pm_ops = {
 189         SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
 190         SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
 191                         igb_runtime_idle)
 192 };
 193 #endif
 194 static void igb_shutdown(struct pci_dev *);
 195 #ifdef CONFIG_IGB_DCA
 196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 197 static struct notifier_block dca_notifier = {
 198         .notifier_call  = igb_notify_dca,
 199         .next           = NULL,
 200         .priority       = 0
 201 };
 202 #endif
 203 #ifdef CONFIG_NET_POLL_CONTROLLER
 204 /* for netdump / net console */
 205 static void igb_netpoll(struct net_device *);
 206 #endif
 207 #ifdef CONFIG_PCI_IOV
 208 static unsigned int max_vfs = 0;
 209 module_param(max_vfs, uint, 0);
 210 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 211                  "per physical function");
 212 #endif /* CONFIG_PCI_IOV */
 213
 214 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 215                      pci_channel_state_t);
 216 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 217 static void igb_io_resume(struct pci_dev *);
 218
 219 static const struct pci_error_handlers igb_err_handler = {
 220         .error_detected = igb_io_error_detected,
 221         .slot_reset = igb_io_slot_reset,
 222         .resume = igb_io_resume,
 223 };
 224
 225 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
 226
 227 static struct pci_driver igb_driver = {
 228         .name     = igb_driver_name,
 229         .id_table = igb_pci_tbl,
 230         .probe    = igb_probe,
 231         .remove   = __devexit_p(igb_remove),
 232 #ifdef CONFIG_PM
 233         .driver.pm = &igb_pm_ops,
 234 #endif
 235         .shutdown = igb_shutdown,
 236         .err_handler = &igb_err_handler
 237 };
 238
 239 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 240 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 241 MODULE_LICENSE("GPL");
 242 MODULE_VERSION(DRV_VERSION);
 243
 244 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
 245 static int debug = -1;
 246 module_param(debug, int, 0);
 247 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 248
 249 struct igb_reg_info {
 250         u32 ofs;
 251         char *name;
 252 };
 253
 254 static const struct igb_reg_info igb_reg_info_tbl[] = {
 255
 256         /* General Registers */
 257         {E1000_CTRL, "CTRL"},
 258         {E1000_STATUS, "STATUS"},
 259         {E1000_CTRL_EXT, "CTRL_EXT"},
 260
 261         /* Interrupt Registers */
 262         {E1000_ICR, "ICR"},
 263
 264         /* RX Registers */
 265         {E1000_RCTL, "RCTL"},
 266         {E1000_RDLEN(0), "RDLEN"},
 267         {E1000_RDH(0), "RDH"},
 268         {E1000_RDT(0), "RDT"},
 269         {E1000_RXDCTL(0), "RXDCTL"},
 270         {E1000_RDBAL(0), "RDBAL"},
 271         {E1000_RDBAH(0), "RDBAH"},
 272
 273         /* TX Registers */
 274         {E1000_TCTL, "TCTL"},
 275         {E1000_TDBAL(0), "TDBAL"},
 276         {E1000_TDBAH(0), "TDBAH"},
 277         {E1000_TDLEN(0), "TDLEN"},
 278         {E1000_TDH(0), "TDH"},
 279         {E1000_TDT(0), "TDT"},
 280         {E1000_TXDCTL(0), "TXDCTL"},
 281         {E1000_TDFH, "TDFH"},
 282         {E1000_TDFT, "TDFT"},
 283         {E1000_TDFHS, "TDFHS"},
 284         {E1000_TDFPC, "TDFPC"},
 285
 286         /* List Terminator */
 287         {}
 288 };
 289
 290 /*
 291  * igb_regdump - register printout routine
 292  */
 293 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
 294 {
 295         int n = 0;
 296         char rname[16];
 297         u32 regs[8];
 298
 299         switch (reginfo->ofs) {
 300         case E1000_RDLEN(0):
 301                 for (n = 0; n < 4; n++)
 302                         regs[n] = rd32(E1000_RDLEN(n));
 303                 break;
 304         case E1000_RDH(0):
 305                 for (n = 0; n < 4; n++)
 306                         regs[n] = rd32(E1000_RDH(n));
 307                 break;
 308         case E1000_RDT(0):
 309                 for (n = 0; n < 4; n++)
 310                         regs[n] = rd32(E1000_RDT(n));
 311                 break;
 312         case E1000_RXDCTL(0):
 313                 for (n = 0; n < 4; n++)
 314                         regs[n] = rd32(E1000_RXDCTL(n));
 315                 break;
 316         case E1000_RDBAL(0):
 317                 for (n = 0; n < 4; n++)
 318                         regs[n] = rd32(E1000_RDBAL(n));
 319                 break;
 320         case E1000_RDBAH(0):
 321                 for (n = 0; n < 4; n++)
 322                         regs[n] = rd32(E1000_RDBAH(n));
 323                 break;
 324         case E1000_TDBAL(0):
 325                 for (n = 0; n < 4; n++)
 326                         regs[n] = rd32(E1000_RDBAL(n));
 327                 break;
 328         case E1000_TDBAH(0):
 329                 for (n = 0; n < 4; n++)
 330                         regs[n] = rd32(E1000_TDBAH(n));
 331                 break;
 332         case E1000_TDLEN(0):
 333                 for (n = 0; n < 4; n++)
 334                         regs[n] = rd32(E1000_TDLEN(n));
 335                 break;
 336         case E1000_TDH(0):
 337                 for (n = 0; n < 4; n++)
 338                         regs[n] = rd32(E1000_TDH(n));
 339                 break;
 340         case E1000_TDT(0):
 341                 for (n = 0; n < 4; n++)
 342                         regs[n] = rd32(E1000_TDT(n));
 343                 break;
 344         case E1000_TXDCTL(0):
 345                 for (n = 0; n < 4; n++)
 346                         regs[n] = rd32(E1000_TXDCTL(n));
 347                 break;
 348         default:
 349                 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
 350                 return;
 351         }
 352
 353         snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
 354         pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
 355                 regs[2], regs[3]);
 356 }
 357
 358 /*
 359  * igb_dump - Print registers, tx-rings and rx-rings
 360  */
 361 static void igb_dump(struct igb_adapter *adapter)
 362 {
 363         struct net_device *netdev = adapter->netdev;
 364         struct e1000_hw *hw = &adapter->hw;
 365         struct igb_reg_info *reginfo;
 366         struct igb_ring *tx_ring;
 367         union e1000_adv_tx_desc *tx_desc;
 368         struct my_u0 { u64 a; u64 b; } *u0;
 369         struct igb_ring *rx_ring;
 370         union e1000_adv_rx_desc *rx_desc;
 371         u32 staterr;
 372         u16 i, n;
 373
 374         if (!netif_msg_hw(adapter))
 375                 return;
 376
 377         /* Print netdevice Info */
 378         if (netdev) {
 379                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 380                 pr_info("Device Name     state            trans_start      "
 381                         "last_rx\n");
 382                 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
 383                         netdev->state, netdev->trans_start, netdev->last_rx);
 384         }
 385
 386         /* Print Registers */
 387         dev_info(&adapter->pdev->dev, "Register Dump\n");
 388         pr_info(" Register Name   Value\n");
 389         for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
 390              reginfo->name; reginfo++) {
 391                 igb_regdump(hw, reginfo);
 392         }
 393
 394         /* Print TX Ring Summary */
 395         if (!netdev || !netif_running(netdev))
 396                 goto exit;
 397
 398         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 399         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 400         for (n = 0; n < adapter->num_tx_queues; n++) {
 401                 struct igb_tx_buffer *buffer_info;
 402                 tx_ring = adapter->tx_ring[n];
 403                 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 404                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 405                         n, tx_ring->next_to_use, tx_ring->next_to_clean,
 406                         (u64)dma_unmap_addr(buffer_info, dma),
 407                         dma_unmap_len(buffer_info, len),
 408                         buffer_info->next_to_watch,
 409                         (u64)buffer_info->time_stamp);
 410         }
 411
 412         /* Print TX Rings */
 413         if (!netif_msg_tx_done(adapter))
 414                 goto rx_ring_summary;
 415
 416         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 417
 418         /* Transmit Descriptor Formats
 419          *
 420          * Advanced Transmit Descriptor
 421          *   +--------------------------------------------------------------+
 422          * 0 |         Buffer Address [63:0]                                |
 423          *   +--------------------------------------------------------------+
 424          * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
 425          *   +--------------------------------------------------------------+
 426          *   63      46 45    40 39 38 36 35 32 31   24             15       0
 427          */
 428
 429         for (n = 0; n < adapter->num_tx_queues; n++) {
 430                 tx_ring = adapter->tx_ring[n];
 431                 pr_info("------------------------------------\n");
 432                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 433                 pr_info("------------------------------------\n");
 434                 pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] "
 435                         "[bi->dma       ] leng  ntw timestamp        "
 436                         "bi->skb\n");
 437
 438                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 439                         const char *next_desc;
 440                         struct igb_tx_buffer *buffer_info;
 441                         tx_desc = IGB_TX_DESC(tx_ring, i);
 442                         buffer_info = &tx_ring->tx_buffer_info[i];
 443                         u0 = (struct my_u0 *)tx_desc;
 444                         if (i == tx_ring->next_to_use &&
 445                             i == tx_ring->next_to_clean)
 446                                 next_desc = " NTC/U";
 447                         else if (i == tx_ring->next_to_use)
 448                                 next_desc = " NTU";
 449                         else if (i == tx_ring->next_to_clean)
 450                                 next_desc = " NTC";
 451                         else
 452                                 next_desc = "";
 453
 454                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 455                                 " %04X  %p %016llX %p%s\n", i,
 456                                 le64_to_cpu(u0->a),
 457                                 le64_to_cpu(u0->b),
 458                                 (u64)dma_unmap_addr(buffer_info, dma),
 459                                 dma_unmap_len(buffer_info, len),
 460                                 buffer_info->next_to_watch,
 461                                 (u64)buffer_info->time_stamp,
 462                                 buffer_info->skb, next_desc);
 463
 464                         if (netif_msg_pktdata(adapter) && buffer_info->skb)
 465                                 print_hex_dump(KERN_INFO, "",
 466                                         DUMP_PREFIX_ADDRESS,
 467                                         16, 1, buffer_info->skb->data,
 468                                         dma_unmap_len(buffer_info, len),
 469                                         true);
 470                 }
 471         }
 472
 473         /* Print RX Rings Summary */
 474 rx_ring_summary:
 475         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 476         pr_info("Queue [NTU] [NTC]\n");
 477         for (n = 0; n < adapter->num_rx_queues; n++) {
 478                 rx_ring = adapter->rx_ring[n];
 479                 pr_info(" %5d %5X %5X\n",
 480                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 481         }
 482
 483         /* Print RX Rings */
 484         if (!netif_msg_rx_status(adapter))
 485                 goto exit;
 486
 487         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 488
 489         /* Advanced Receive Descriptor (Read) Format
 490          *    63                                           1        0
 491          *    +-----------------------------------------------------+
 492          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 493          *    +----------------------------------------------+------+
 494          *  8 |       Header Buffer Address [63:1]           |  DD  |
 495          *    +-----------------------------------------------------+
 496          *
 497          *
 498          * Advanced Receive Descriptor (Write-Back) Format
 499          *
 500          *   63       48 47    32 31  30      21 20 17 16   4 3     0
 501          *   +------------------------------------------------------+
 502          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 503          *   | Checksum   Ident  |   |           |    | Type | Type |
 504          *   +------------------------------------------------------+
 505          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 506          *   +------------------------------------------------------+
 507          *   63       48 47    32 31            20 19               0
 508          */
 509
 510         for (n = 0; n < adapter->num_rx_queues; n++) {
 511                 rx_ring = adapter->rx_ring[n];
 512                 pr_info("------------------------------------\n");
 513                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 514                 pr_info("------------------------------------\n");
 515                 pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] "
 516                         "[bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
 517                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] -----"
 518                         "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
 519
 520                 for (i = 0; i < rx_ring->count; i++) {
 521                         const char *next_desc;
 522                         struct igb_rx_buffer *buffer_info;
 523                         buffer_info = &rx_ring->rx_buffer_info[i];
 524                         rx_desc = IGB_RX_DESC(rx_ring, i);
 525                         u0 = (struct my_u0 *)rx_desc;
 526                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 527
 528                         if (i == rx_ring->next_to_use)
 529                                 next_desc = " NTU";
 530                         else if (i == rx_ring->next_to_clean)
 531                                 next_desc = " NTC";
 532                         else
 533                                 next_desc = "";
 534
 535                         if (staterr & E1000_RXD_STAT_DD) {
 536                                 /* Descriptor Done */
 537                                 pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
 538                                         "RWB", i,
 539                                         le64_to_cpu(u0->a),
 540                                         le64_to_cpu(u0->b),
 541                                         next_desc);
 542                         } else {
 543                                 pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
 544                                         "R  ", i,
 545                                         le64_to_cpu(u0->a),
 546                                         le64_to_cpu(u0->b),
 547                                         (u64)buffer_info->dma,
 548                                         next_desc);
 549
 550                                 if (netif_msg_pktdata(adapter) &&
 551                                     buffer_info->dma && buffer_info->page) {
 552                                         print_hex_dump(KERN_INFO, "",
 553                                           DUMP_PREFIX_ADDRESS,
 554                                           16, 1,
 555                                           page_address(buffer_info->page) +
 556                                                       buffer_info->page_offset,
 557                                           IGB_RX_BUFSZ, true);
 558                                 }
 559                         }
 560                 }
 561         }
 562
 563 exit:
 564         return;
 565 }
 566
 567 /**
 568  * igb_get_hw_dev - return device
 569  * used by hardware layer to print debugging information
 570  **/
 571 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
 572 {
 573         struct igb_adapter *adapter = hw->back;
 574         return adapter->netdev;
 575 }
 576
 577 /**
 578  * igb_init_module - Driver Registration Routine
 579  *
 580  * igb_init_module is the first routine called when the driver is
 581  * loaded. All it does is register with the PCI subsystem.
 582  **/
 583 static int __init igb_init_module(void)
 584 {
 585         int ret;
 586         pr_info("%s - version %s\n",
 587                igb_driver_string, igb_driver_version);
 588
 589         pr_info("%s\n", igb_copyright);
 590
 591 #ifdef CONFIG_IGB_DCA
 592         dca_register_notify(&dca_notifier);
 593 #endif
 594         ret = pci_register_driver(&igb_driver);
 595         return ret;
 596 }
 597
 598 module_init(igb_init_module);
 599
 600 /**
 601  * igb_exit_module - Driver Exit Cleanup Routine
 602  *
 603  * igb_exit_module is called just before the driver is removed
 604  * from memory.
 605  **/
 606 static void __exit igb_exit_module(void)
 607 {
 608 #ifdef CONFIG_IGB_DCA
 609         dca_unregister_notify(&dca_notifier);
 610 #endif
 611         pci_unregister_driver(&igb_driver);
 612 }
 613
 614 module_exit(igb_exit_module);
 615
 616 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 617 /**
 618  * igb_cache_ring_register - Descriptor ring to register mapping
 619  * @adapter: board private structure to initialize
 620  *
 621  * Once we know the feature-set enabled for the device, we'll cache
 622  * the register offset the descriptor ring is assigned to.
 623  **/
 624 static void igb_cache_ring_register(struct igb_adapter *adapter)
 625 {
 626         int i = 0, j = 0;
 627         u32 rbase_offset = adapter->vfs_allocated_count;
 628
 629         switch (adapter->hw.mac.type) {
 630         case e1000_82576:
 631                 /* The queues are allocated for virtualization such that VF 0
 632                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 633                  * In order to avoid collision we start at the first free queue
 634                  * and continue consuming queues in the same sequence
 635                  */
 636                 if (adapter->vfs_allocated_count) {
 637                         for (; i < adapter->rss_queues; i++)
 638                                 adapter->rx_ring[i]->reg_idx = rbase_offset +
 639                                                                Q_IDX_82576(i);
 640                 }
 641         case e1000_82575:
 642         case e1000_82580:
 643         case e1000_i350:
 644         case e1000_i210:
 645         case e1000_i211:
 646         default:
 647                 for (; i < adapter->num_rx_queues; i++)
 648                         adapter->rx_ring[i]->reg_idx = rbase_offset + i;
 649                 for (; j < adapter->num_tx_queues; j++)
 650                         adapter->tx_ring[j]->reg_idx = rbase_offset + j;
 651                 break;
 652         }
 653 }
 654
 655 /**
 656  *  igb_write_ivar - configure ivar for given MSI-X vector
 657  *  @hw: pointer to the HW structure
 658  *  @msix_vector: vector number we are allocating to a given ring
 659  *  @index: row index of IVAR register to write within IVAR table
 660  *  @offset: column offset of in IVAR, should be multiple of 8
 661  *
 662  *  This function is intended to handle the writing of the IVAR register
 663  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
 664  *  each containing an cause allocation for an Rx and Tx ring, and a
 665  *  variable number of rows depending on the number of queues supported.
 666  **/
 667 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
 668                            int index, int offset)
 669 {
 670         u32 ivar = array_rd32(E1000_IVAR0, index);
 671
 672         /* clear any bits that are currently set */
 673         ivar &= ~((u32)0xFF << offset);
 674
 675         /* write vector and valid bit */
 676         ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
 677
 678         array_wr32(E1000_IVAR0, index, ivar);
 679 }
 680
 681 #define IGB_N0_QUEUE -1
 682 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
 683 {
 684         struct igb_adapter *adapter = q_vector->adapter;
 685         struct e1000_hw *hw = &adapter->hw;
 686         int rx_queue = IGB_N0_QUEUE;
 687         int tx_queue = IGB_N0_QUEUE;
 688         u32 msixbm = 0;
 689
 690         if (q_vector->rx.ring)
 691                 rx_queue = q_vector->rx.ring->reg_idx;
 692         if (q_vector->tx.ring)
 693                 tx_queue = q_vector->tx.ring->reg_idx;
 694
 695         switch (hw->mac.type) {
 696         case e1000_82575:
 697                 /* The 82575 assigns vectors using a bitmask, which matches the
 698                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 699                    or more queues to a vector, we write the appropriate bits
 700                    into the MSIXBM register for that vector. */
 701                 if (rx_queue > IGB_N0_QUEUE)
 702                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 703                 if (tx_queue > IGB_N0_QUEUE)
 704                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 705                 if (!adapter->msix_entries && msix_vector == 0)
 706                         msixbm |= E1000_EIMS_OTHER;
 707                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 708                 q_vector->eims_value = msixbm;
 709                 break;
 710         case e1000_82576:
 711                 /*
 712                  * 82576 uses a table that essentially consists of 2 columns
 713                  * with 8 rows.  The ordering is column-major so we use the
 714                  * lower 3 bits as the row index, and the 4th bit as the
 715                  * column offset.
 716                  */
 717                 if (rx_queue > IGB_N0_QUEUE)
 718                         igb_write_ivar(hw, msix_vector,
 719                                        rx_queue & 0x7,
 720                                        (rx_queue & 0x8) << 1);
 721                 if (tx_queue > IGB_N0_QUEUE)
 722                         igb_write_ivar(hw, msix_vector,
 723                                        tx_queue & 0x7,
 724                                        ((tx_queue & 0x8) << 1) + 8);
 725                 q_vector->eims_value = 1 << msix_vector;
 726                 break;
 727         case e1000_82580:
 728         case e1000_i350:
 729         case e1000_i210:
 730         case e1000_i211:
 731                 /*
 732                  * On 82580 and newer adapters the scheme is similar to 82576
 733                  * however instead of ordering column-major we have things
 734                  * ordered row-major.  So we traverse the table by using
 735                  * bit 0 as the column offset, and the remaining bits as the
 736                  * row index.
 737                  */
 738                 if (rx_queue > IGB_N0_QUEUE)
 739                         igb_write_ivar(hw, msix_vector,
 740                                        rx_queue >> 1,
 741                                        (rx_queue & 0x1) << 4);
 742                 if (tx_queue > IGB_N0_QUEUE)
 743                         igb_write_ivar(hw, msix_vector,
 744                                        tx_queue >> 1,
 745                                        ((tx_queue & 0x1) << 4) + 8);
 746                 q_vector->eims_value = 1 << msix_vector;
 747                 break;
 748         default:
 749                 BUG();
 750                 break;
 751         }
 752
 753         /* add q_vector eims value to global eims_enable_mask */
 754         adapter->eims_enable_mask |= q_vector->eims_value;
 755
 756         /* configure q_vector to set itr on first interrupt */
 757         q_vector->set_itr = 1;
 758 }
 759
 760 /**
 761  * igb_configure_msix - Configure MSI-X hardware
 762  *
 763  * igb_configure_msix sets up the hardware to properly
 764  * generate MSI-X interrupts.
 765  **/
 766 static void igb_configure_msix(struct igb_adapter *adapter)
 767 {
 768         u32 tmp;
 769         int i, vector = 0;
 770         struct e1000_hw *hw = &adapter->hw;
 771
 772         adapter->eims_enable_mask = 0;
 773
 774         /* set vector for other causes, i.e. link changes */
 775         switch (hw->mac.type) {
 776         case e1000_82575:
 777                 tmp = rd32(E1000_CTRL_EXT);
 778                 /* enable MSI-X PBA support*/
 779                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 780
 781                 /* Auto-Mask interrupts upon ICR read. */
 782                 tmp |= E1000_CTRL_EXT_EIAME;
 783                 tmp |= E1000_CTRL_EXT_IRCA;
 784
 785                 wr32(E1000_CTRL_EXT, tmp);
 786
 787                 /* enable msix_other interrupt */
 788                 array_wr32(E1000_MSIXBM(0), vector++,
 789                                       E1000_EIMS_OTHER);
 790                 adapter->eims_other = E1000_EIMS_OTHER;
 791
 792                 break;
 793
 794         case e1000_82576:
 795         case e1000_82580:
 796         case e1000_i350:
 797         case e1000_i210:
 798         case e1000_i211:
 799                 /* Turn on MSI-X capability first, or our settings
 800                  * won't stick.  And it will take days to debug. */
 801                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 802                                 E1000_GPIE_PBA | E1000_GPIE_EIAME |
 803                                 E1000_GPIE_NSICR);
 804
 805                 /* enable msix_other interrupt */
 806                 adapter->eims_other = 1 << vector;
 807                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 808
 809                 wr32(E1000_IVAR_MISC, tmp);
 810                 break;
 811         default:
 812                 /* do nothing, since nothing else supports MSI-X */
 813                 break;
 814         } /* switch (hw->mac.type) */
 815
 816         adapter->eims_enable_mask |= adapter->eims_other;
 817
 818         for (i = 0; i < adapter->num_q_vectors; i++)
 819                 igb_assign_vector(adapter->q_vector[i], vector++);
 820
 821         wrfl();
 822 }
 823
 824 /**
 825  * igb_request_msix - Initialize MSI-X interrupts
 826  *
 827  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 828  * kernel.
 829  **/
 830 static int igb_request_msix(struct igb_adapter *adapter)
 831 {
 832         struct net_device *netdev = adapter->netdev;
 833         struct e1000_hw *hw = &adapter->hw;
 834         int i, err = 0, vector = 0;
 835
 836         err = request_irq(adapter->msix_entries[vector].vector,
 837                           igb_msix_other, 0, netdev->name, adapter);
 838         if (err)
 839                 goto out;
 840         vector++;
 841
 842         for (i = 0; i < adapter->num_q_vectors; i++) {
 843                 struct igb_q_vector *q_vector = adapter->q_vector[i];
 844
 845                 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
 846
 847                 if (q_vector->rx.ring && q_vector->tx.ring)
 848                         sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
 849                                 q_vector->rx.ring->queue_index);
 850                 else if (q_vector->tx.ring)
 851                         sprintf(q_vector->name, "%s-tx-%u", netdev->name,
 852                                 q_vector->tx.ring->queue_index);
 853                 else if (q_vector->rx.ring)
 854                         sprintf(q_vector->name, "%s-rx-%u", netdev->name,
 855                                 q_vector->rx.ring->queue_index);
 856                 else
 857                         sprintf(q_vector->name, "%s-unused", netdev->name);
 858
 859                 err = request_irq(adapter->msix_entries[vector].vector,
 860                                   igb_msix_ring, 0, q_vector->name,
 861                                   q_vector);
 862                 if (err)
 863                         goto out;
 864                 vector++;
 865         }
 866
 867         igb_configure_msix(adapter);
 868         return 0;
 869 out:
 870         return err;
 871 }
 872
 873 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 874 {
 875         if (adapter->msix_entries) {
 876                 pci_disable_msix(adapter->pdev);
 877                 kfree(adapter->msix_entries);
 878                 adapter->msix_entries = NULL;
 879         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
 880                 pci_disable_msi(adapter->pdev);
 881         }
 882 }
 883
 884 /**
 885  * igb_free_q_vector - Free memory allocated for specific interrupt vector
 886  * @adapter: board private structure to initialize
 887  * @v_idx: Index of vector to be freed
 888  *
 889  * This function frees the memory allocated to the q_vector.  In addition if
 890  * NAPI is enabled it will delete any references to the NAPI struct prior
 891  * to freeing the q_vector.
 892  **/
 893 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
 894 {
 895         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
 896
 897         if (q_vector->tx.ring)
 898                 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
 899
 900         if (q_vector->rx.ring)
 901                 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
 902
 903         adapter->q_vector[v_idx] = NULL;
 904         netif_napi_del(&q_vector->napi);
 905
 906         /*
 907          * ixgbe_get_stats64() might access the rings on this vector,
 908          * we must wait a grace period before freeing it.
 909          */
 910         kfree_rcu(q_vector, rcu);
 911 }
 912
 913 /**
 914  * igb_free_q_vectors - Free memory allocated for interrupt vectors
 915  * @adapter: board private structure to initialize
 916  *
 917  * This function frees the memory allocated to the q_vectors.  In addition if
 918  * NAPI is enabled it will delete any references to the NAPI struct prior
 919  * to freeing the q_vector.
 920  **/
 921 static void igb_free_q_vectors(struct igb_adapter *adapter)
 922 {
 923         int v_idx = adapter->num_q_vectors;
 924
 925         adapter->num_tx_queues = 0;
 926         adapter->num_rx_queues = 0;
 927         adapter->num_q_vectors = 0;
 928
 929         while (v_idx--)
 930                 igb_free_q_vector(adapter, v_idx);
 931 }
 932
 933 /**
 934  * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
 935  *
 936  * This function resets the device so that it has 0 rx queues, tx queues, and
 937  * MSI-X interrupts allocated.
 938  */
 939 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
 940 {
 941         igb_free_q_vectors(adapter);
 942         igb_reset_interrupt_capability(adapter);
 943 }
 944
 945 /**
 946  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 947  *
 948  * Attempt to configure interrupts using the best available
 949  * capabilities of the hardware and kernel.
 950  **/
 951 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 952 {
 953         int err;
 954         int numvecs, i;
 955
 956         /* Number of supported queues. */
 957         adapter->num_rx_queues = adapter->rss_queues;
 958         if (adapter->vfs_allocated_count)
 959                 adapter->num_tx_queues = 1;
 960         else
 961                 adapter->num_tx_queues = adapter->rss_queues;
 962
 963         /* start with one vector for every rx queue */
 964         numvecs = adapter->num_rx_queues;
 965
 966         /* if tx handler is separate add 1 for every tx queue */
 967         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
 968                 numvecs += adapter->num_tx_queues;
 969
 970         /* store the number of vectors reserved for queues */
 971         adapter->num_q_vectors = numvecs;
 972
 973         /* add 1 vector for link status interrupts */
 974         numvecs++;
 975         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 976                                         GFP_KERNEL);
 977
 978         if (!adapter->msix_entries)
 979                 goto msi_only;
 980
 981         for (i = 0; i < numvecs; i++)
 982                 adapter->msix_entries[i].entry = i;
 983
 984         err = pci_enable_msix(adapter->pdev,
 985                               adapter->msix_entries,
 986                               numvecs);
 987         if (err == 0)
 988                 return;
 989
 990         igb_reset_interrupt_capability(adapter);
 991
 992         /* If we can't do MSI-X, try MSI */
 993 msi_only:
 994 #ifdef CONFIG_PCI_IOV
 995         /* disable SR-IOV for non MSI-X configurations */
 996         if (adapter->vf_data) {
 997                 struct e1000_hw *hw = &adapter->hw;
 998                 /* disable iov and allow time for transactions to clear */
 999                 pci_disable_sriov(adapter->pdev);
1000                 msleep(500);
1001
1002                 kfree(adapter->vf_data);
1003                 adapter->vf_data = NULL;
1004                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1005                 wrfl();
1006                 msleep(100);
1007                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1008         }
1009 #endif
1010         adapter->vfs_allocated_count = 0;
1011         adapter->rss_queues = 1;
1012         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1013         adapter->num_rx_queues = 1;
1014         adapter->num_tx_queues = 1;
1015         adapter->num_q_vectors = 1;
1016         if (!pci_enable_msi(adapter->pdev))
1017                 adapter->flags |= IGB_FLAG_HAS_MSI;
1018 }
1019
1020 static void igb_add_ring(struct igb_ring *ring,
1021                          struct igb_ring_container *head)
1022 {
1023         head->ring = ring;
1024         head->count++;
1025 }
1026
1027 /**
1028  * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1029  * @adapter: board private structure to initialize
1030  * @v_count: q_vectors allocated on adapter, used for ring interleaving
1031  * @v_idx: index of vector in adapter struct
1032  * @txr_count: total number of Tx rings to allocate
1033  * @txr_idx: index of first Tx ring to allocate
1034  * @rxr_count: total number of Rx rings to allocate
1035  * @rxr_idx: index of first Rx ring to allocate
1036  *
1037  * We allocate one q_vector.  If allocation fails we return -ENOMEM.
1038  **/
1039 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1040                               int v_count, int v_idx,
1041                               int txr_count, int txr_idx,
1042                               int rxr_count, int rxr_idx)
1043 {
1044         struct igb_q_vector *q_vector;
1045         struct igb_ring *ring;
1046         int ring_count, size;
1047
1048         /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1049         if (txr_count > 1 || rxr_count > 1)
1050                 return -ENOMEM;
1051
1052         ring_count = txr_count + rxr_count;
1053         size = sizeof(struct igb_q_vector) +
1054                (sizeof(struct igb_ring) * ring_count);
1055
1056         /* allocate q_vector and rings */
1057         q_vector = kzalloc(size, GFP_KERNEL);
1058         if (!q_vector)
1059                 return -ENOMEM;
1060
1061         /* initialize NAPI */
1062         netif_napi_add(adapter->netdev, &q_vector->napi,
1063                        igb_poll, 64);
1064
1065         /* tie q_vector and adapter together */
1066         adapter->q_vector[v_idx] = q_vector;
1067         q_vector->adapter = adapter;
1068
1069         /* initialize work limits */
1070         q_vector->tx.work_limit = adapter->tx_work_limit;
1071
1072         /* initialize ITR configuration */
1073         q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1074         q_vector->itr_val = IGB_START_ITR;
1075
1076         /* initialize pointer to rings */
1077         ring = q_vector->ring;
1078
1079         if (txr_count) {
1080                 /* assign generic ring traits */
1081                 ring->dev = &adapter->pdev->dev;
1082                 ring->netdev = adapter->netdev;
1083
1084                 /* configure backlink on ring */
1085                 ring->q_vector = q_vector;
1086
1087                 /* update q_vector Tx values */
1088                 igb_add_ring(ring, &q_vector->tx);
1089
1090                 /* For 82575, context index must be unique per ring. */
1091                 if (adapter->hw.mac.type == e1000_82575)
1092                         set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1093
1094                 /* apply Tx specific ring traits */
1095                 ring->count = adapter->tx_ring_count;
1096                 ring->queue_index = txr_idx;
1097
1098                 /* assign ring to adapter */
1099                 adapter->tx_ring[txr_idx] = ring;
1100
1101                 /* push pointer to next ring */
1102                 ring++;
1103         }
1104
1105         if (rxr_count) {
1106                 /* assign generic ring traits */
1107                 ring->dev = &adapter->pdev->dev;
1108                 ring->netdev = adapter->netdev;
1109
1110                 /* configure backlink on ring */
1111                 ring->q_vector = q_vector;
1112
1113                 /* update q_vector Rx values */
1114                 igb_add_ring(ring, &q_vector->rx);
1115
1116                 /* set flag indicating ring supports SCTP checksum offload */
1117                 if (adapter->hw.mac.type >= e1000_82576)
1118                         set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1119
1120                 /*
1121                  * On i350, i210, and i211, loopback VLAN packets
1122                  * have the tag byte-swapped.
1123                  * */
1124                 if (adapter->hw.mac.type >= e1000_i350)
1125                         set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1126
1127                 /* apply Rx specific ring traits */
1128                 ring->count = adapter->rx_ring_count;
1129                 ring->queue_index = rxr_idx;
1130
1131                 /* assign ring to adapter */
1132                 adapter->rx_ring[rxr_idx] = ring;
1133         }
1134
1135         return 0;
1136 }
1137
1138
1139 /**
1140  * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1141  * @adapter: board private structure to initialize
1142  *
1143  * We allocate one q_vector per queue interrupt.  If allocation fails we
1144  * return -ENOMEM.
1145  **/
1146 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1147 {
1148         int q_vectors = adapter->num_q_vectors;
1149         int rxr_remaining = adapter->num_rx_queues;
1150         int txr_remaining = adapter->num_tx_queues;
1151         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1152         int err;
1153
1154         if (q_vectors >= (rxr_remaining + txr_remaining)) {
1155                 for (; rxr_remaining; v_idx++) {
1156                         err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1157                                                  0, 0, 1, rxr_idx);
1158
1159                         if (err)
1160                                 goto err_out;
1161
1162                         /* update counts and index */
1163                         rxr_remaining--;
1164                         rxr_idx++;
1165                 }
1166         }
1167
1168         for (; v_idx < q_vectors; v_idx++) {
1169                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1170                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1171                 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1172                                          tqpv, txr_idx, rqpv, rxr_idx);
1173
1174                 if (err)
1175                         goto err_out;
1176
1177                 /* update counts and index */
1178                 rxr_remaining -= rqpv;
1179                 txr_remaining -= tqpv;
1180                 rxr_idx++;
1181                 txr_idx++;
1182         }
1183
1184         return 0;
1185
1186 err_out:
1187         adapter->num_tx_queues = 0;
1188         adapter->num_rx_queues = 0;
1189         adapter->num_q_vectors = 0;
1190
1191         while (v_idx--)
1192                 igb_free_q_vector(adapter, v_idx);
1193
1194         return -ENOMEM;
1195 }
1196
1197 /**
1198  * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1199  *
1200  * This function initializes the interrupts and allocates all of the queues.
1201  **/
1202 static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
1203 {
1204         struct pci_dev *pdev = adapter->pdev;
1205         int err;
1206
1207         igb_set_interrupt_capability(adapter);
1208
1209         err = igb_alloc_q_vectors(adapter);
1210         if (err) {
1211                 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1212                 goto err_alloc_q_vectors;
1213         }
1214
1215         igb_cache_ring_register(adapter);
1216
1217         return 0;
1218
1219 err_alloc_q_vectors:
1220         igb_reset_interrupt_capability(adapter);
1221         return err;
1222 }
1223
1224 /**
1225  * igb_request_irq - initialize interrupts
1226  *
1227  * Attempts to configure interrupts using the best available
1228  * capabilities of the hardware and kernel.
1229  **/
1230 static int igb_request_irq(struct igb_adapter *adapter)
1231 {
1232         struct net_device *netdev = adapter->netdev;
1233         struct pci_dev *pdev = adapter->pdev;
1234         int err = 0;
1235
1236         if (adapter->msix_entries) {
1237                 err = igb_request_msix(adapter);
1238                 if (!err)
1239                         goto request_done;
1240                 /* fall back to MSI */
1241                 igb_free_all_tx_resources(adapter);
1242                 igb_free_all_rx_resources(adapter);
1243                 igb_clear_interrupt_scheme(adapter);
1244                 if (!pci_enable_msi(pdev))
1245                         adapter->flags |= IGB_FLAG_HAS_MSI;
1246                 adapter->num_tx_queues = 1;
1247                 adapter->num_rx_queues = 1;
1248                 adapter->num_q_vectors = 1;
1249                 err = igb_alloc_q_vectors(adapter);
1250                 if (err) {
1251                         dev_err(&pdev->dev,
1252                                 "Unable to allocate memory for vectors\n");
1253                         goto request_done;
1254                 }
1255                 igb_setup_all_tx_resources(adapter);
1256                 igb_setup_all_rx_resources(adapter);
1257         }
1258
1259         igb_assign_vector(adapter->q_vector[0], 0);
1260
1261         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1262                 err = request_irq(pdev->irq, igb_intr_msi, 0,
1263                                   netdev->name, adapter);
1264                 if (!err)
1265                         goto request_done;
1266
1267                 /* fall back to legacy interrupts */
1268                 igb_reset_interrupt_capability(adapter);
1269                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1270         }
1271
1272         err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1273                           netdev->name, adapter);
1274
1275         if (err)
1276                 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1277                         err);
1278
1279 request_done:
1280         return err;
1281 }
1282
1283 static void igb_free_irq(struct igb_adapter *adapter)
1284 {
1285         if (adapter->msix_entries) {
1286                 int vector = 0, i;
1287
1288                 free_irq(adapter->msix_entries[vector++].vector, adapter);
1289
1290                 for (i = 0; i < adapter->num_q_vectors; i++)
1291                         free_irq(adapter->msix_entries[vector++].vector,
1292                                  adapter->q_vector[i]);
1293         } else {
1294                 free_irq(adapter->pdev->irq, adapter);
1295         }
1296 }
1297
1298 /**
1299  * igb_irq_disable - Mask off interrupt generation on the NIC
1300  * @adapter: board private structure
1301  **/
1302 static void igb_irq_disable(struct igb_adapter *adapter)
1303 {
1304         struct e1000_hw *hw = &adapter->hw;
1305
1306         /*
1307          * we need to be careful when disabling interrupts.  The VFs are also
1308          * mapped into these registers and so clearing the bits can cause
1309          * issues on the VF drivers so we only need to clear what we set
1310          */
1311         if (adapter->msix_entries) {
1312                 u32 regval = rd32(E1000_EIAM);
1313                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1314                 wr32(E1000_EIMC, adapter->eims_enable_mask);
1315                 regval = rd32(E1000_EIAC);
1316                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1317         }
1318
1319         wr32(E1000_IAM, 0);
1320         wr32(E1000_IMC, ~0);
1321         wrfl();
1322         if (adapter->msix_entries) {
1323                 int i;
1324                 for (i = 0; i < adapter->num_q_vectors; i++)
1325                         synchronize_irq(adapter->msix_entries[i].vector);
1326         } else {
1327                 synchronize_irq(adapter->pdev->irq);
1328         }
1329 }
1330
1331 /**
1332  * igb_irq_enable - Enable default interrupt generation settings
1333  * @adapter: board private structure
1334  **/
1335 static void igb_irq_enable(struct igb_adapter *adapter)
1336 {
1337         struct e1000_hw *hw = &adapter->hw;
1338
1339         if (adapter->msix_entries) {
1340                 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1341                 u32 regval = rd32(E1000_EIAC);
1342                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1343                 regval = rd32(E1000_EIAM);
1344                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1345                 wr32(E1000_EIMS, adapter->eims_enable_mask);
1346                 if (adapter->vfs_allocated_count) {
1347                         wr32(E1000_MBVFIMR, 0xFF);
1348                         ims |= E1000_IMS_VMMB;
1349                 }
1350                 wr32(E1000_IMS, ims);
1351         } else {
1352                 wr32(E1000_IMS, IMS_ENABLE_MASK |
1353                                 E1000_IMS_DRSTA);
1354                 wr32(E1000_IAM, IMS_ENABLE_MASK |
1355                                 E1000_IMS_DRSTA);
1356         }
1357 }
1358
1359 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1360 {
1361         struct e1000_hw *hw = &adapter->hw;
1362         u16 vid = adapter->hw.mng_cookie.vlan_id;
1363         u16 old_vid = adapter->mng_vlan_id;
1364
1365         if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1366                 /* add VID to filter table */
1367                 igb_vfta_set(hw, vid, true);
1368                 adapter->mng_vlan_id = vid;
1369         } else {
1370                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1371         }
1372
1373         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1374             (vid != old_vid) &&
1375             !test_bit(old_vid, adapter->active_vlans)) {
1376                 /* remove VID from filter table */
1377                 igb_vfta_set(hw, old_vid, false);
1378         }
1379 }
1380
1381 /**
1382  * igb_release_hw_control - release control of the h/w to f/w
1383  * @adapter: address of board private structure
1384  *
1385  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1386  * For ASF and Pass Through versions of f/w this means that the
1387  * driver is no longer loaded.
1388  *
1389  **/
1390 static void igb_release_hw_control(struct igb_adapter *adapter)
1391 {
1392         struct e1000_hw *hw = &adapter->hw;
1393         u32 ctrl_ext;
1394
1395         /* Let firmware take over control of h/w */
1396         ctrl_ext = rd32(E1000_CTRL_EXT);
1397         wr32(E1000_CTRL_EXT,
1398                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1399 }
1400
1401 /**
1402  * igb_get_hw_control - get control of the h/w from f/w
1403  * @adapter: address of board private structure
1404  *
1405  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1406  * For ASF and Pass Through versions of f/w this means that
1407  * the driver is loaded.
1408  *
1409  **/
1410 static void igb_get_hw_control(struct igb_adapter *adapter)
1411 {
1412         struct e1000_hw *hw = &adapter->hw;
1413         u32 ctrl_ext;
1414
1415         /* Let firmware know the driver has taken over */
1416         ctrl_ext = rd32(E1000_CTRL_EXT);
1417         wr32(E1000_CTRL_EXT,
1418                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1419 }
1420
1421 /**
1422  * igb_configure - configure the hardware for RX and TX
1423  * @adapter: private board structure
1424  **/
1425 static void igb_configure(struct igb_adapter *adapter)
1426 {
1427         struct net_device *netdev = adapter->netdev;
1428         int i;
1429
1430         igb_get_hw_control(adapter);
1431         igb_set_rx_mode(netdev);
1432
1433         igb_restore_vlan(adapter);
1434
1435         igb_setup_tctl(adapter);
1436         igb_setup_mrqc(adapter);
1437         igb_setup_rctl(adapter);
1438
1439         igb_configure_tx(adapter);
1440         igb_configure_rx(adapter);
1441
1442         igb_rx_fifo_flush_82575(&adapter->hw);
1443
1444         /* call igb_desc_unused which always leaves
1445          * at least 1 descriptor unused to make sure
1446          * next_to_use != next_to_clean */
1447         for (i = 0; i < adapter->num_rx_queues; i++) {
1448                 struct igb_ring *ring = adapter->rx_ring[i];
1449                 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1450         }
1451 }
1452
1453 /**
1454  * igb_power_up_link - Power up the phy/serdes link
1455  * @adapter: address of board private structure
1456  **/
1457 void igb_power_up_link(struct igb_adapter *adapter)
1458 {
1459         igb_reset_phy(&adapter->hw);
1460
1461         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1462                 igb_power_up_phy_copper(&adapter->hw);
1463         else
1464                 igb_power_up_serdes_link_82575(&adapter->hw);
1465 }
1466
1467 /**
1468  * igb_power_down_link - Power down the phy/serdes link
1469  * @adapter: address of board private structure
1470  */
1471 static void igb_power_down_link(struct igb_adapter *adapter)
1472 {
1473         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1474                 igb_power_down_phy_copper_82575(&adapter->hw);
1475         else
1476                 igb_shutdown_serdes_link_82575(&adapter->hw);
1477 }
1478
1479 /**
1480  * igb_up - Open the interface and prepare it to handle traffic
1481  * @adapter: board private structure
1482  **/
1483 int igb_up(struct igb_adapter *adapter)
1484 {
1485         struct e1000_hw *hw = &adapter->hw;
1486         int i;
1487
1488         /* hardware has been reset, we need to reload some things */
1489         igb_configure(adapter);
1490
1491         clear_bit(__IGB_DOWN, &adapter->state);
1492
1493         for (i = 0; i < adapter->num_q_vectors; i++)
1494                 napi_enable(&(adapter->q_vector[i]->napi));
1495
1496         if (adapter->msix_entries)
1497                 igb_configure_msix(adapter);
1498         else
1499                 igb_assign_vector(adapter->q_vector[0], 0);
1500
1501         /* Clear any pending interrupts. */
1502         rd32(E1000_ICR);
1503         igb_irq_enable(adapter);
1504
1505         /* notify VFs that reset has been completed */
1506         if (adapter->vfs_allocated_count) {
1507                 u32 reg_data = rd32(E1000_CTRL_EXT);
1508                 reg_data |= E1000_CTRL_EXT_PFRSTD;
1509                 wr32(E1000_CTRL_EXT, reg_data);
1510         }
1511
1512         netif_tx_start_all_queues(adapter->netdev);
1513
1514         /* start the watchdog. */
1515         hw->mac.get_link_status = 1;
1516         schedule_work(&adapter->watchdog_task);
1517
1518         return 0;
1519 }
1520
1521 void igb_down(struct igb_adapter *adapter)
1522 {
1523         struct net_device *netdev = adapter->netdev;
1524         struct e1000_hw *hw = &adapter->hw;
1525         u32 tctl, rctl;
1526         int i;
1527
1528         /* signal that we're down so the interrupt handler does not
1529          * reschedule our watchdog timer */
1530         set_bit(__IGB_DOWN, &adapter->state);
1531
1532         /* disable receives in the hardware */
1533         rctl = rd32(E1000_RCTL);
1534         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1535         /* flush and sleep below */
1536
1537         netif_tx_stop_all_queues(netdev);
1538
1539         /* disable transmits in the hardware */
1540         tctl = rd32(E1000_TCTL);
1541         tctl &= ~E1000_TCTL_EN;
1542         wr32(E1000_TCTL, tctl);
1543         /* flush both disables and wait for them to finish */
1544         wrfl();
1545         msleep(10);
1546
1547         for (i = 0; i < adapter->num_q_vectors; i++)
1548                 napi_disable(&(adapter->q_vector[i]->napi));
1549
1550         igb_irq_disable(adapter);
1551
1552         del_timer_sync(&adapter->watchdog_timer);
1553         del_timer_sync(&adapter->phy_info_timer);
1554
1555         netif_carrier_off(netdev);
1556
1557         /* record the stats before reset*/
1558         spin_lock(&adapter->stats64_lock);
1559         igb_update_stats(adapter, &adapter->stats64);
1560         spin_unlock(&adapter->stats64_lock);
1561
1562         adapter->link_speed = 0;
1563         adapter->link_duplex = 0;
1564
1565         if (!pci_channel_offline(adapter->pdev))
1566                 igb_reset(adapter);
1567         igb_clean_all_tx_rings(adapter);
1568         igb_clean_all_rx_rings(adapter);
1569 #ifdef CONFIG_IGB_DCA
1570
1571         /* since we reset the hardware DCA settings were cleared */
1572         igb_setup_dca(adapter);
1573 #endif
1574 }
1575
1576 void igb_reinit_locked(struct igb_adapter *adapter)
1577 {
1578         WARN_ON(in_interrupt());
1579         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1580                 msleep(1);
1581         igb_down(adapter);
1582         igb_up(adapter);
1583         clear_bit(__IGB_RESETTING, &adapter->state);
1584 }
1585
1586 void igb_reset(struct igb_adapter *adapter)
1587 {
1588         struct pci_dev *pdev = adapter->pdev;
1589         struct e1000_hw *hw = &adapter->hw;
1590         struct e1000_mac_info *mac = &hw->mac;
1591         struct e1000_fc_info *fc = &hw->fc;
1592         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1593         u16 hwm;
1594
1595         /* Repartition Pba for greater than 9k mtu
1596          * To take effect CTRL.RST is required.
1597          */
1598         switch (mac->type) {
1599         case e1000_i350:
1600         case e1000_82580:
1601                 pba = rd32(E1000_RXPBS);
1602                 pba = igb_rxpbs_adjust_82580(pba);
1603                 break;
1604         case e1000_82576:
1605                 pba = rd32(E1000_RXPBS);
1606                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1607                 break;
1608         case e1000_82575:
1609         case e1000_i210:
1610         case e1000_i211:
1611         default:
1612                 pba = E1000_PBA_34K;
1613                 break;
1614         }
1615
1616         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1617             (mac->type < e1000_82576)) {
1618                 /* adjust PBA for jumbo frames */
1619                 wr32(E1000_PBA, pba);
1620
1621                 /* To maintain wire speed transmits, the Tx FIFO should be
1622                  * large enough to accommodate two full transmit packets,
1623                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1624                  * the Rx FIFO should be large enough to accommodate at least
1625                  * one full receive packet and is similarly rounded up and
1626                  * expressed in KB. */
1627                 pba = rd32(E1000_PBA);
1628                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1629                 tx_space = pba >> 16;
1630                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1631                 pba &= 0xffff;
1632                 /* the tx fifo also stores 16 bytes of information about the tx
1633                  * but don't include ethernet FCS because hardware appends it */
1634                 min_tx_space = (adapter->max_frame_size +
1635                                 sizeof(union e1000_adv_tx_desc) -
1636                                 ETH_FCS_LEN) * 2;
1637                 min_tx_space = ALIGN(min_tx_space, 1024);
1638                 min_tx_space >>= 10;
1639                 /* software strips receive CRC, so leave room for it */
1640                 min_rx_space = adapter->max_frame_size;
1641                 min_rx_space = ALIGN(min_rx_space, 1024);
1642                 min_rx_space >>= 10;
1643
1644                 /* If current Tx allocation is less than the min Tx FIFO size,
1645                  * and the min Tx FIFO size is less than the current Rx FIFO
1646                  * allocation, take space away from current Rx allocation */
1647                 if (tx_space < min_tx_space &&
1648                     ((min_tx_space - tx_space) < pba)) {
1649                         pba = pba - (min_tx_space - tx_space);
1650
1651                         /* if short on rx space, rx wins and must trump tx
1652                          * adjustment */
1653                         if (pba < min_rx_space)
1654                                 pba = min_rx_space;
1655                 }
1656                 wr32(E1000_PBA, pba);
1657         }
1658
1659         /* flow control settings */
1660         /* The high water mark must be low enough to fit one full frame
1661          * (or the size used for early receive) above it in the Rx FIFO.
1662          * Set it to the lower of:
1663          * - 90% of the Rx FIFO size, or
1664          * - the full Rx FIFO size minus one full frame */
1665         hwm = min(((pba << 10) * 9 / 10),
1666                         ((pba << 10) - 2 * adapter->max_frame_size));
1667
1668         fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
1669         fc->low_water = fc->high_water - 16;
1670         fc->pause_time = 0xFFFF;
1671         fc->send_xon = 1;
1672         fc->current_mode = fc->requested_mode;
1673
1674         /* disable receive for all VFs and wait one second */
1675         if (adapter->vfs_allocated_count) {
1676                 int i;
1677                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1678                         adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1679
1680                 /* ping all the active vfs to let them know we are going down */
1681                 igb_ping_all_vfs(adapter);
1682
1683                 /* disable transmits and receives */
1684                 wr32(E1000_VFRE, 0);
1685                 wr32(E1000_VFTE, 0);
1686         }
1687
1688         /* Allow time for pending master requests to run */
1689         hw->mac.ops.reset_hw(hw);
1690         wr32(E1000_WUC, 0);
1691
1692         if (hw->mac.ops.init_hw(hw))
1693                 dev_err(&pdev->dev, "Hardware Error\n");
1694
1695         /*
1696          * Flow control settings reset on hardware reset, so guarantee flow
1697          * control is off when forcing speed.
1698          */
1699         if (!hw->mac.autoneg)
1700                 igb_force_mac_fc(hw);
1701
1702         igb_init_dmac(adapter, pba);
1703         if (!netif_running(adapter->netdev))
1704                 igb_power_down_link(adapter);
1705
1706         igb_update_mng_vlan(adapter);
1707
1708         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1709         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1710
1711         /* Re-enable PTP, where applicable. */
1712         igb_ptp_reset(adapter);
1713
1714         igb_get_phy_info(hw);
1715 }
1716
1717 static netdev_features_t igb_fix_features(struct net_device *netdev,
1718         netdev_features_t features)
1719 {
1720         /*
1721          * Since there is no support for separate rx/tx vlan accel
1722          * enable/disable make sure tx flag is always in same state as rx.
1723          */
1724         if (features & NETIF_F_HW_VLAN_RX)
1725                 features |= NETIF_F_HW_VLAN_TX;
1726         else
1727                 features &= ~NETIF_F_HW_VLAN_TX;
1728
1729         return features;
1730 }
1731
1732 static int igb_set_features(struct net_device *netdev,
1733         netdev_features_t features)
1734 {
1735         netdev_features_t changed = netdev->features ^ features;
1736         struct igb_adapter *adapter = netdev_priv(netdev);
1737
1738         if (changed & NETIF_F_HW_VLAN_RX)
1739                 igb_vlan_mode(netdev, features);
1740
1741         if (!(changed & NETIF_F_RXALL))
1742                 return 0;
1743
1744         netdev->features = features;
1745
1746         if (netif_running(netdev))
1747                 igb_reinit_locked(adapter);
1748         else
1749                 igb_reset(adapter);
1750
1751         return 0;
1752 }
1753
1754 static const struct net_device_ops igb_netdev_ops = {
1755         .ndo_open               = igb_open,
1756         .ndo_stop               = igb_close,
1757         .ndo_start_xmit         = igb_xmit_frame,
1758         .ndo_get_stats64        = igb_get_stats64,
1759         .ndo_set_rx_mode        = igb_set_rx_mode,
1760         .ndo_set_mac_address    = igb_set_mac,
1761         .ndo_change_mtu         = igb_change_mtu,
1762         .ndo_do_ioctl           = igb_ioctl,
1763         .ndo_tx_timeout         = igb_tx_timeout,
1764         .ndo_validate_addr      = eth_validate_addr,
1765         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1766         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1767         .ndo_set_vf_mac         = igb_ndo_set_vf_mac,
1768         .ndo_set_vf_vlan        = igb_ndo_set_vf_vlan,
1769         .ndo_set_vf_tx_rate     = igb_ndo_set_vf_bw,
1770         .ndo_get_vf_config      = igb_ndo_get_vf_config,
1771 #ifdef CONFIG_NET_POLL_CONTROLLER
1772         .ndo_poll_controller    = igb_netpoll,
1773 #endif
1774         .ndo_fix_features       = igb_fix_features,
1775         .ndo_set_features       = igb_set_features,
1776 };
1777
1778 /**
1779  * igb_set_fw_version - Configure version string for ethtool
1780  * @adapter: adapter struct
1781  *
1782  **/
1783 void igb_set_fw_version(struct igb_adapter *adapter)
1784 {
1785         struct e1000_hw *hw = &adapter->hw;
1786         struct e1000_fw_version fw;
1787
1788         igb_get_fw_version(hw, &fw);
1789
1790         switch (hw->mac.type) {
1791         case e1000_i211:
1792                 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
1793                          "%2d.%2d-%d",
1794                          fw.invm_major, fw.invm_minor, fw.invm_img_type);
1795                 break;
1796
1797         default:
1798                 /* if option is rom valid, display its version too */
1799                 if (fw.or_valid) {
1800                         snprintf(adapter->fw_version,
1801                                  sizeof(adapter->fw_version),
1802                                  "%d.%d, 0x%08x, %d.%d.%d",
1803                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
1804                                  fw.or_major, fw.or_build, fw.or_patch);
1805                 /* no option rom */
1806                 } else {
1807                         snprintf(adapter->fw_version,
1808                                  sizeof(adapter->fw_version),
1809                                  "%d.%d, 0x%08x",
1810                                  fw.eep_major, fw.eep_minor, fw.etrack_id);
1811                 }
1812                 break;
1813         }
1814         return;
1815 }
1816
1817 /**
1818  * igb_probe - Device Initialization Routine
1819  * @pdev: PCI device information struct
1820  * @ent: entry in igb_pci_tbl
1821  *
1822  * Returns 0 on success, negative on failure
1823  *
1824  * igb_probe initializes an adapter identified by a pci_dev structure.
1825  * The OS initialization, configuring of the adapter private structure,
1826  * and a hardware reset occur.
1827  **/
1828 static int __devinit igb_probe(struct pci_dev *pdev,
1829                                const struct pci_device_id *ent)
1830 {
1831         struct net_device *netdev;
1832         struct igb_adapter *adapter;
1833         struct e1000_hw *hw;
1834         u16 eeprom_data = 0;
1835         s32 ret_val;
1836         static int global_quad_port_a; /* global quad port a indication */
1837         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1838         unsigned long mmio_start, mmio_len;
1839         int err, pci_using_dac;
1840         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1841         u8 part_str[E1000_PBANUM_LENGTH];
1842
1843         /* Catch broken hardware that put the wrong VF device ID in
1844          * the PCIe SR-IOV capability.
1845          */
1846         if (pdev->is_virtfn) {
1847                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1848                         pci_name(pdev), pdev->vendor, pdev->device);
1849                 return -EINVAL;
1850         }
1851
1852         err = pci_enable_device_mem(pdev);
1853         if (err)
1854                 return err;
1855
1856         pci_using_dac = 0;
1857         err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1858         if (!err) {
1859                 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1860                 if (!err)
1861                         pci_using_dac = 1;
1862         } else {
1863                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1864                 if (err) {
1865                         err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1866                         if (err) {
1867                                 dev_err(&pdev->dev, "No usable DMA "
1868                                         "configuration, aborting\n");
1869                                 goto err_dma;
1870                         }
1871                 }
1872         }
1873
1874         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1875                                            IORESOURCE_MEM),
1876                                            igb_driver_name);
1877         if (err)
1878                 goto err_pci_reg;
1879
1880         pci_enable_pcie_error_reporting(pdev);
1881
1882         pci_set_master(pdev);
1883         pci_save_state(pdev);
1884
1885         err = -ENOMEM;
1886         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1887                                    IGB_MAX_TX_QUEUES);
1888         if (!netdev)
1889                 goto err_alloc_etherdev;
1890
1891         SET_NETDEV_DEV(netdev, &pdev->dev);
1892
1893         pci_set_drvdata(pdev, netdev);
1894         adapter = netdev_priv(netdev);
1895         adapter->netdev = netdev;
1896         adapter->pdev = pdev;
1897         hw = &adapter->hw;
1898         hw->back = adapter;
1899         adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1900
1901         mmio_start = pci_resource_start(pdev, 0);
1902         mmio_len = pci_resource_len(pdev, 0);
1903
1904         err = -EIO;
1905         hw->hw_addr = ioremap(mmio_start, mmio_len);
1906         if (!hw->hw_addr)
1907                 goto err_ioremap;
1908
1909         netdev->netdev_ops = &igb_netdev_ops;
1910         igb_set_ethtool_ops(netdev);
1911         netdev->watchdog_timeo = 5 * HZ;
1912
1913         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1914
1915         netdev->mem_start = mmio_start;
1916         netdev->mem_end = mmio_start + mmio_len;
1917
1918         /* PCI config space info */
1919         hw->vendor_id = pdev->vendor;
1920         hw->device_id = pdev->device;
1921         hw->revision_id = pdev->revision;
1922         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1923         hw->subsystem_device_id = pdev->subsystem_device;
1924
1925         /* Copy the default MAC, PHY and NVM function pointers */
1926         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1927         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1928         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1929         /* Initialize skew-specific constants */
1930         err = ei->get_invariants(hw);
1931         if (err)
1932                 goto err_sw_init;
1933
1934         /* setup the private structure */
1935         err = igb_sw_init(adapter);
1936         if (err)
1937                 goto err_sw_init;
1938
1939         igb_get_bus_info_pcie(hw);
1940
1941         hw->phy.autoneg_wait_to_complete = false;
1942
1943         /* Copper options */
1944         if (hw->phy.media_type == e1000_media_type_copper) {
1945                 hw->phy.mdix = AUTO_ALL_MODES;
1946                 hw->phy.disable_polarity_correction = false;
1947                 hw->phy.ms_type = e1000_ms_hw_default;
1948         }
1949
1950         if (igb_check_reset_block(hw))
1951                 dev_info(&pdev->dev,
1952                         "PHY reset is blocked due to SOL/IDER session.\n");
1953
1954         /*
1955          * features is initialized to 0 in allocation, it might have bits
1956          * set by igb_sw_init so we should use an or instead of an
1957          * assignment.
1958          */
1959         netdev->features |= NETIF_F_SG |
1960                             NETIF_F_IP_CSUM |
1961                             NETIF_F_IPV6_CSUM |
1962                             NETIF_F_TSO |
1963                             NETIF_F_TSO6 |
1964                             NETIF_F_RXHASH |
1965                             NETIF_F_RXCSUM |
1966                             NETIF_F_HW_VLAN_RX |
1967                             NETIF_F_HW_VLAN_TX;
1968
1969         /* copy netdev features into list of user selectable features */
1970         netdev->hw_features |= netdev->features;
1971         netdev->hw_features |= NETIF_F_RXALL;
1972
1973         /* set this bit last since it cannot be part of hw_features */
1974         netdev->features |= NETIF_F_HW_VLAN_FILTER;
1975
1976         netdev->vlan_features |= NETIF_F_TSO |
1977                                  NETIF_F_TSO6 |
1978                                  NETIF_F_IP_CSUM |
1979                                  NETIF_F_IPV6_CSUM |
1980                                  NETIF_F_SG;
1981
1982         netdev->priv_flags |= IFF_SUPP_NOFCS;
1983
1984         if (pci_using_dac) {
1985                 netdev->features |= NETIF_F_HIGHDMA;
1986                 netdev->vlan_features |= NETIF_F_HIGHDMA;
1987         }
1988
1989         if (hw->mac.type >= e1000_82576) {
1990                 netdev->hw_features |= NETIF_F_SCTP_CSUM;
1991                 netdev->features |= NETIF_F_SCTP_CSUM;
1992         }
1993
1994         netdev->priv_flags |= IFF_UNICAST_FLT;
1995
1996         adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
1997
1998         /* before reading the NVM, reset the controller to put the device in a
1999          * known good starting state */
2000         hw->mac.ops.reset_hw(hw);
2001
2002         /*
2003          * make sure the NVM is good , i211 parts have special NVM that
2004          * doesn't contain a checksum
2005          */
2006         if (hw->mac.type != e1000_i211) {
2007                 if (hw->nvm.ops.validate(hw) < 0) {
2008                         dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2009                         err = -EIO;
2010                         goto err_eeprom;
2011                 }
2012         }
2013
2014         /* copy the MAC address out of the NVM */
2015         if (hw->mac.ops.read_mac_addr(hw))
2016                 dev_err(&pdev->dev, "NVM Read Error\n");
2017
2018         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2019         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
2020
2021         if (!is_valid_ether_addr(netdev->perm_addr)) {
2022                 dev_err(&pdev->dev, "Invalid MAC Address\n");
2023                 err = -EIO;
2024                 goto err_eeprom;
2025         }
2026
2027         /* get firmware version for ethtool -i */
2028         igb_set_fw_version(adapter);
2029
2030         setup_timer(&adapter->watchdog_timer, igb_watchdog,
2031                     (unsigned long) adapter);
2032         setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2033                     (unsigned long) adapter);
2034
2035         INIT_WORK(&adapter->reset_task, igb_reset_task);
2036         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2037
2038         /* Initialize link properties that are user-changeable */
2039         adapter->fc_autoneg = true;
2040         hw->mac.autoneg = true;
2041         hw->phy.autoneg_advertised = 0x2f;
2042
2043         hw->fc.requested_mode = e1000_fc_default;
2044         hw->fc.current_mode = e1000_fc_default;
2045
2046         igb_validate_mdi_setting(hw);
2047
2048         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
2049          * enable the ACPI Magic Packet filter
2050          */
2051
2052         if (hw->bus.func == 0)
2053                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
2054         else if (hw->mac.type >= e1000_82580)
2055                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2056                                  NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2057                                  &eeprom_data);
2058         else if (hw->bus.func == 1)
2059                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2060
2061         if (eeprom_data & eeprom_apme_mask)
2062                 adapter->eeprom_wol |= E1000_WUFC_MAG;
2063
2064         /* now that we have the eeprom settings, apply the special cases where
2065          * the eeprom may be wrong or the board simply won't support wake on
2066          * lan on a particular port */
2067         switch (pdev->device) {
2068         case E1000_DEV_ID_82575GB_QUAD_COPPER:
2069                 adapter->eeprom_wol = 0;
2070                 break;
2071         case E1000_DEV_ID_82575EB_FIBER_SERDES:
2072         case E1000_DEV_ID_82576_FIBER:
2073         case E1000_DEV_ID_82576_SERDES:
2074                 /* Wake events only supported on port A for dual fiber
2075                  * regardless of eeprom setting */
2076                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2077                         adapter->eeprom_wol = 0;
2078                 break;
2079         case E1000_DEV_ID_82576_QUAD_COPPER:
2080         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2081                 /* if quad port adapter, disable WoL on all but port A */
2082                 if (global_quad_port_a != 0)
2083                         adapter->eeprom_wol = 0;
2084                 else
2085                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2086                 /* Reset for multiple quad port adapters */
2087                 if (++global_quad_port_a == 4)
2088                         global_quad_port_a = 0;
2089                 break;
2090         }
2091
2092         /* initialize the wol settings based on the eeprom settings */
2093         adapter->wol = adapter->eeprom_wol;
2094         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2095
2096         /* reset the hardware with the new settings */
2097         igb_reset(adapter);
2098
2099         /* let the f/w know that the h/w is now under the control of the
2100          * driver. */
2101         igb_get_hw_control(adapter);
2102
2103         strcpy(netdev->name, "eth%d");
2104         err = register_netdev(netdev);
2105         if (err)
2106                 goto err_register;
2107
2108         /* carrier off reporting is important to ethtool even BEFORE open */
2109         netif_carrier_off(netdev);
2110
2111 #ifdef CONFIG_IGB_DCA
2112         if (dca_add_requester(&pdev->dev) == 0) {
2113                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2114                 dev_info(&pdev->dev, "DCA enabled\n");
2115                 igb_setup_dca(adapter);
2116         }
2117
2118 #endif
2119
2120         /* do hw tstamp init after resetting */
2121         igb_ptp_init(adapter);
2122
2123         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2124         /* print bus type/speed/width info */
2125         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2126                  netdev->name,
2127                  ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2128                   (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2129                                                             "unknown"),
2130                  ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2131                   (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2132                   (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2133                    "unknown"),
2134                  netdev->dev_addr);
2135
2136         ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2137         if (ret_val)
2138                 strcpy(part_str, "Unknown");
2139         dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2140         dev_info(&pdev->dev,
2141                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2142                 adapter->msix_entries ? "MSI-X" :
2143                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2144                 adapter->num_rx_queues, adapter->num_tx_queues);
2145         switch (hw->mac.type) {
2146         case e1000_i350:
2147         case e1000_i210:
2148         case e1000_i211:
2149                 igb_set_eee_i350(hw);
2150                 break;
2151         default:
2152                 break;
2153         }
2154
2155         pm_runtime_put_noidle(&pdev->dev);
2156         return 0;
2157
2158 err_register:
2159         igb_release_hw_control(adapter);
2160 err_eeprom:
2161         if (!igb_check_reset_block(hw))
2162                 igb_reset_phy(hw);
2163
2164         if (hw->flash_address)
2165                 iounmap(hw->flash_address);
2166 err_sw_init:
2167         igb_clear_interrupt_scheme(adapter);
2168         iounmap(hw->hw_addr);
2169 err_ioremap:
2170         free_netdev(netdev);
2171 err_alloc_etherdev:
2172         pci_release_selected_regions(pdev,
2173                                      pci_select_bars(pdev, IORESOURCE_MEM));
2174 err_pci_reg:
2175 err_dma:
2176         pci_disable_device(pdev);
2177         return err;
2178 }
2179
2180 /**
2181  * igb_remove - Device Removal Routine
2182  * @pdev: PCI device information struct
2183  *
2184  * igb_remove is called by the PCI subsystem to alert the driver
2185  * that it should release a PCI device.  The could be caused by a
2186  * Hot-Plug event, or because the driver is going to be removed from
2187  * memory.
2188  **/
2189 static void __devexit igb_remove(struct pci_dev *pdev)
2190 {
2191         struct net_device *netdev = pci_get_drvdata(pdev);
2192         struct igb_adapter *adapter = netdev_priv(netdev);
2193         struct e1000_hw *hw = &adapter->hw;
2194
2195         pm_runtime_get_noresume(&pdev->dev);
2196         igb_ptp_stop(adapter);
2197
2198         /*
2199          * The watchdog timer may be rescheduled, so explicitly
2200          * disable watchdog from being rescheduled.
2201          */
2202         set_bit(__IGB_DOWN, &adapter->state);
2203         del_timer_sync(&adapter->watchdog_timer);
2204         del_timer_sync(&adapter->phy_info_timer);
2205
2206         cancel_work_sync(&adapter->reset_task);
2207         cancel_work_sync(&adapter->watchdog_task);
2208
2209 #ifdef CONFIG_IGB_DCA
2210         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2211                 dev_info(&pdev->dev, "DCA disabled\n");
2212                 dca_remove_requester(&pdev->dev);
2213                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2214                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2215         }
2216 #endif
2217
2218         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
2219          * would have already happened in close and is redundant. */
2220         igb_release_hw_control(adapter);
2221
2222         unregister_netdev(netdev);
2223
2224         igb_clear_interrupt_scheme(adapter);
2225
2226 #ifdef CONFIG_PCI_IOV
2227         /* reclaim resources allocated to VFs */
2228         if (adapter->vf_data) {
2229                 /* disable iov and allow time for transactions to clear */
2230                 if (igb_vfs_are_assigned(adapter)) {
2231                         dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n");
2232                 } else {
2233                         pci_disable_sriov(pdev);
2234                         msleep(500);
2235                 }
2236
2237                 kfree(adapter->vf_data);
2238                 adapter->vf_data = NULL;
2239                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2240                 wrfl();
2241                 msleep(100);
2242                 dev_info(&pdev->dev, "IOV Disabled\n");
2243         }
2244 #endif
2245
2246         iounmap(hw->hw_addr);
2247         if (hw->flash_address)
2248                 iounmap(hw->flash_address);
2249         pci_release_selected_regions(pdev,
2250                                      pci_select_bars(pdev, IORESOURCE_MEM));
2251
2252         kfree(adapter->shadow_vfta);
2253         free_netdev(netdev);
2254
2255         pci_disable_pcie_error_reporting(pdev);
2256
2257         pci_disable_device(pdev);
2258 }
2259
2260 /**
2261  * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2262  * @adapter: board private structure to initialize
2263  *
2264  * This function initializes the vf specific data storage and then attempts to
2265  * allocate the VFs.  The reason for ordering it this way is because it is much
2266  * mor expensive time wise to disable SR-IOV than it is to allocate and free
2267  * the memory for the VFs.
2268  **/
2269 static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2270 {
2271 #ifdef CONFIG_PCI_IOV
2272         struct pci_dev *pdev = adapter->pdev;
2273         struct e1000_hw *hw = &adapter->hw;
2274         int old_vfs = pci_num_vf(adapter->pdev);
2275         int i;
2276
2277         /* Virtualization features not supported on i210 family. */
2278         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2279                 return;
2280
2281         if (old_vfs) {
2282                 dev_info(&pdev->dev, "%d pre-allocated VFs found - override "
2283                          "max_vfs setting of %d\n", old_vfs, max_vfs);
2284                 adapter->vfs_allocated_count = old_vfs;
2285         }
2286
2287         if (!adapter->vfs_allocated_count)
2288                 return;
2289
2290         adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2291                                 sizeof(struct vf_data_storage), GFP_KERNEL);
2292
2293         /* if allocation failed then we do not support SR-IOV */
2294         if (!adapter->vf_data) {
2295                 adapter->vfs_allocated_count = 0;
2296                 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2297                         "Data Storage\n");
2298                 goto out;
2299         }
2300
2301         if (!old_vfs) {
2302                 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count))
2303                         goto err_out;
2304         }
2305         dev_info(&pdev->dev, "%d VFs allocated\n",
2306                  adapter->vfs_allocated_count);
2307         for (i = 0; i < adapter->vfs_allocated_count; i++)
2308                 igb_vf_configure(adapter, i);
2309
2310         /* DMA Coalescing is not supported in IOV mode. */
2311         adapter->flags &= ~IGB_FLAG_DMAC;
2312         goto out;
2313 err_out:
2314         kfree(adapter->vf_data);
2315         adapter->vf_data = NULL;
2316         adapter->vfs_allocated_count = 0;
2317 out:
2318         return;
2319 #endif /* CONFIG_PCI_IOV */
2320 }
2321
2322 /**
2323  * igb_sw_init - Initialize general software structures (struct igb_adapter)
2324  * @adapter: board private structure to initialize
2325  *
2326  * igb_sw_init initializes the Adapter private data structure.
2327  * Fields are initialized based on PCI device information and
2328  * OS network device settings (MTU size).
2329  **/
2330 static int __devinit igb_sw_init(struct igb_adapter *adapter)
2331 {
2332         struct e1000_hw *hw = &adapter->hw;
2333         struct net_device *netdev = adapter->netdev;
2334         struct pci_dev *pdev = adapter->pdev;
2335         u32 max_rss_queues;
2336
2337         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2338
2339         /* set default ring sizes */
2340         adapter->tx_ring_count = IGB_DEFAULT_TXD;
2341         adapter->rx_ring_count = IGB_DEFAULT_RXD;
2342
2343         /* set default ITR values */
2344         adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2345         adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2346
2347         /* set default work limits */
2348         adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2349
2350         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2351                                   VLAN_HLEN;
2352         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2353
2354         spin_lock_init(&adapter->stats64_lock);
2355 #ifdef CONFIG_PCI_IOV
2356         switch (hw->mac.type) {
2357         case e1000_82576:
2358         case e1000_i350:
2359                 if (max_vfs > 7) {
2360                         dev_warn(&pdev->dev,
2361                                  "Maximum of 7 VFs per PF, using max\n");
2362                         adapter->vfs_allocated_count = 7;
2363                 } else
2364                         adapter->vfs_allocated_count = max_vfs;
2365                 break;
2366         default:
2367                 break;
2368         }
2369 #endif /* CONFIG_PCI_IOV */
2370
2371         /* Determine the maximum number of RSS queues supported. */
2372         switch (hw->mac.type) {
2373         case e1000_i211:
2374                 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2375                 break;
2376         case e1000_82575:
2377         case e1000_i210:
2378                 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2379                 break;
2380         case e1000_i350:
2381                 /* I350 cannot do RSS and SR-IOV at the same time */
2382                 if (!!adapter->vfs_allocated_count) {
2383                         max_rss_queues = 1;
2384                         break;
2385                 }
2386                 /* fall through */
2387         case e1000_82576:
2388                 if (!!adapter->vfs_allocated_count) {
2389                         max_rss_queues = 2;
2390                         break;
2391                 }
2392                 /* fall through */
2393         case e1000_82580:
2394         default:
2395                 max_rss_queues = IGB_MAX_RX_QUEUES;
2396                 break;
2397         }
2398
2399         adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2400
2401         /* Determine if we need to pair queues. */
2402         switch (hw->mac.type) {
2403         case e1000_82575:
2404         case e1000_i211:
2405                 /* Device supports enough interrupts without queue pairing. */
2406                 break;
2407         case e1000_82576:
2408                 /*
2409                  * If VFs are going to be allocated with RSS queues then we
2410                  * should pair the queues in order to conserve interrupts due
2411                  * to limited supply.
2412                  */
2413                 if ((adapter->rss_queues > 1) &&
2414                     (adapter->vfs_allocated_count > 6))
2415                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2416                 /* fall through */
2417         case e1000_82580:
2418         case e1000_i350:
2419         case e1000_i210:
2420         default:
2421                 /*
2422                  * If rss_queues > half of max_rss_queues, pair the queues in
2423                  * order to conserve interrupts due to limited supply.
2424                  */
2425                 if (adapter->rss_queues > (max_rss_queues / 2))
2426                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2427                 break;
2428         }
2429
2430         /* Setup and initialize a copy of the hw vlan table array */
2431         adapter->shadow_vfta = kzalloc(sizeof(u32) *
2432                                 E1000_VLAN_FILTER_TBL_SIZE,
2433                                 GFP_ATOMIC);
2434
2435         /* This call may decrease the number of queues */
2436         if (igb_init_interrupt_scheme(adapter)) {
2437                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2438                 return -ENOMEM;
2439         }
2440
2441         igb_probe_vfs(adapter);
2442
2443         /* Explicitly disable IRQ since the NIC can be in any state. */
2444         igb_irq_disable(adapter);
2445
2446         if (hw->mac.type >= e1000_i350)
2447                 adapter->flags &= ~IGB_FLAG_DMAC;
2448
2449         set_bit(__IGB_DOWN, &adapter->state);
2450         return 0;
2451 }
2452
2453 /**
2454  * igb_open - Called when a network interface is made active
2455  * @netdev: network interface device structure
2456  *
2457  * Returns 0 on success, negative value on failure
2458  *
2459  * The open entry point is called when a network interface is made
2460  * active by the system (IFF_UP).  At this point all resources needed
2461  * for transmit and receive operations are allocated, the interrupt
2462  * handler is registered with the OS, the watchdog timer is started,
2463  * and the stack is notified that the interface is ready.
2464  **/
2465 static int __igb_open(struct net_device *netdev, bool resuming)
2466 {
2467         struct igb_adapter *adapter = netdev_priv(netdev);
2468         struct e1000_hw *hw = &adapter->hw;
2469         struct pci_dev *pdev = adapter->pdev;
2470         int err;
2471         int i;
2472
2473         /* disallow open during test */
2474         if (test_bit(__IGB_TESTING, &adapter->state)) {
2475                 WARN_ON(resuming);
2476                 return -EBUSY;
2477         }
2478
2479         if (!resuming)
2480                 pm_runtime_get_sync(&pdev->dev);
2481
2482         netif_carrier_off(netdev);
2483
2484         /* allocate transmit descriptors */
2485         err = igb_setup_all_tx_resources(adapter);
2486         if (err)
2487                 goto err_setup_tx;
2488
2489         /* allocate receive descriptors */
2490         err = igb_setup_all_rx_resources(adapter);
2491         if (err)
2492                 goto err_setup_rx;
2493
2494         igb_power_up_link(adapter);
2495
2496         /* before we allocate an interrupt, we must be ready to handle it.
2497          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2498          * as soon as we call pci_request_irq, so we have to setup our
2499          * clean_rx handler before we do so.  */
2500         igb_configure(adapter);
2501
2502         err = igb_request_irq(adapter);
2503         if (err)
2504                 goto err_req_irq;
2505
2506         /* Notify the stack of the actual queue counts. */
2507         err = netif_set_real_num_tx_queues(adapter->netdev,
2508                                            adapter->num_tx_queues);
2509         if (err)
2510                 goto err_set_queues;
2511
2512         err = netif_set_real_num_rx_queues(adapter->netdev,
2513                                            adapter->num_rx_queues);
2514         if (err)
2515                 goto err_set_queues;
2516
2517         /* From here on the code is the same as igb_up() */
2518         clear_bit(__IGB_DOWN, &adapter->state);
2519
2520         for (i = 0; i < adapter->num_q_vectors; i++)
2521                 napi_enable(&(adapter->q_vector[i]->napi));
2522
2523         /* Clear any pending interrupts. */
2524         rd32(E1000_ICR);
2525
2526         igb_irq_enable(adapter);
2527
2528         /* notify VFs that reset has been completed */
2529         if (adapter->vfs_allocated_count) {
2530                 u32 reg_data = rd32(E1000_CTRL_EXT);
2531                 reg_data |= E1000_CTRL_EXT_PFRSTD;
2532                 wr32(E1000_CTRL_EXT, reg_data);
2533         }
2534
2535         netif_tx_start_all_queues(netdev);
2536
2537         if (!resuming)
2538                 pm_runtime_put(&pdev->dev);
2539
2540         /* start the watchdog. */
2541         hw->mac.get_link_status = 1;
2542         schedule_work(&adapter->watchdog_task);
2543
2544         return 0;
2545
2546 err_set_queues:
2547         igb_free_irq(adapter);
2548 err_req_irq:
2549         igb_release_hw_control(adapter);
2550         igb_power_down_link(adapter);
2551         igb_free_all_rx_resources(adapter);
2552 err_setup_rx:
2553         igb_free_all_tx_resources(adapter);
2554 err_setup_tx:
2555         igb_reset(adapter);
2556         if (!resuming)
2557                 pm_runtime_put(&pdev->dev);
2558
2559         return err;
2560 }
2561
2562 static int igb_open(struct net_device *netdev)
2563 {
2564         return __igb_open(netdev, false);
2565 }
2566
2567 /**
2568  * igb_close - Disables a network interface
2569  * @netdev: network interface device structure
2570  *
2571  * Returns 0, this is not allowed to fail
2572  *
2573  * The close entry point is called when an interface is de-activated
2574  * by the OS.  The hardware is still under the driver's control, but
2575  * needs to be disabled.  A global MAC reset is issued to stop the
2576  * hardware, and all transmit and receive resources are freed.
2577  **/
2578 static int __igb_close(struct net_device *netdev, bool suspending)
2579 {
2580         struct igb_adapter *adapter = netdev_priv(netdev);
2581         struct pci_dev *pdev = adapter->pdev;
2582
2583         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2584
2585         if (!suspending)
2586                 pm_runtime_get_sync(&pdev->dev);
2587
2588         igb_down(adapter);
2589         igb_free_irq(adapter);
2590
2591         igb_free_all_tx_resources(adapter);
2592         igb_free_all_rx_resources(adapter);
2593
2594         if (!suspending)
2595                 pm_runtime_put_sync(&pdev->dev);
2596         return 0;
2597 }
2598
2599 static int igb_close(struct net_device *netdev)
2600 {
2601         return __igb_close(netdev, false);
2602 }
2603
2604 /**
2605  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2606  * @tx_ring: tx descriptor ring (for a specific queue) to setup
2607  *
2608  * Return 0 on success, negative on failure
2609  **/
2610 int igb_setup_tx_resources(struct igb_ring *tx_ring)
2611 {
2612         struct device *dev = tx_ring->dev;
2613         int size;
2614
2615         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2616
2617         tx_ring->tx_buffer_info = vzalloc(size);
2618         if (!tx_ring->tx_buffer_info)
2619                 goto err;
2620
2621         /* round up to nearest 4K */
2622         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2623         tx_ring->size = ALIGN(tx_ring->size, 4096);
2624
2625         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2626                                            &tx_ring->dma, GFP_KERNEL);
2627         if (!tx_ring->desc)
2628                 goto err;
2629
2630         tx_ring->next_to_use = 0;
2631         tx_ring->next_to_clean = 0;
2632
2633         return 0;
2634
2635 err:
2636         vfree(tx_ring->tx_buffer_info);
2637         tx_ring->tx_buffer_info = NULL;
2638         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2639         return -ENOMEM;
2640 }
2641
2642 /**
2643  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2644  *                                (Descriptors) for all queues
2645  * @adapter: board private structure
2646  *
2647  * Return 0 on success, negative on failure
2648  **/
2649 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2650 {
2651         struct pci_dev *pdev = adapter->pdev;
2652         int i, err = 0;
2653
2654         for (i = 0; i < adapter->num_tx_queues; i++) {
2655                 err = igb_setup_tx_resources(adapter->tx_ring[i]);
2656                 if (err) {
2657                         dev_err(&pdev->dev,
2658                                 "Allocation for Tx Queue %u failed\n", i);
2659                         for (i--; i >= 0; i--)
2660                                 igb_free_tx_resources(adapter->tx_ring[i]);
2661                         break;
2662                 }
2663         }
2664
2665         return err;
2666 }
2667
2668 /**
2669  * igb_setup_tctl - configure the transmit control registers
2670  * @adapter: Board private structure
2671  **/
2672 void igb_setup_tctl(struct igb_adapter *adapter)
2673 {
2674         struct e1000_hw *hw = &adapter->hw;
2675         u32 tctl;
2676
2677         /* disable queue 0 which is enabled by default on 82575 and 82576 */
2678         wr32(E1000_TXDCTL(0), 0);
2679
2680         /* Program the Transmit Control Register */
2681         tctl = rd32(E1000_TCTL);
2682         tctl &= ~E1000_TCTL_CT;
2683         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2684                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2685
2686         igb_config_collision_dist(hw);
2687
2688         /* Enable transmits */
2689         tctl |= E1000_TCTL_EN;
2690
2691         wr32(E1000_TCTL, tctl);
2692 }
2693
2694 /**
2695  * igb_configure_tx_ring - Configure transmit ring after Reset
2696  * @adapter: board private structure
2697  * @ring: tx ring to configure
2698  *
2699  * Configure a transmit ring after a reset.
2700  **/
2701 void igb_configure_tx_ring(struct igb_adapter *adapter,
2702                            struct igb_ring *ring)
2703 {
2704         struct e1000_hw *hw = &adapter->hw;
2705         u32 txdctl = 0;
2706         u64 tdba = ring->dma;
2707         int reg_idx = ring->reg_idx;
2708
2709         /* disable the queue */
2710         wr32(E1000_TXDCTL(reg_idx), 0);
2711         wrfl();
2712         mdelay(10);
2713
2714         wr32(E1000_TDLEN(reg_idx),
2715                         ring->count * sizeof(union e1000_adv_tx_desc));
2716         wr32(E1000_TDBAL(reg_idx),
2717                         tdba & 0x00000000ffffffffULL);
2718         wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2719
2720         ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2721         wr32(E1000_TDH(reg_idx), 0);
2722         writel(0, ring->tail);
2723
2724         txdctl |= IGB_TX_PTHRESH;
2725         txdctl |= IGB_TX_HTHRESH << 8;
2726         txdctl |= IGB_TX_WTHRESH << 16;
2727
2728         txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2729         wr32(E1000_TXDCTL(reg_idx), txdctl);
2730 }
2731
2732 /**
2733  * igb_configure_tx - Configure transmit Unit after Reset
2734  * @adapter: board private structure
2735  *
2736  * Configure the Tx unit of the MAC after a reset.
2737  **/
2738 static void igb_configure_tx(struct igb_adapter *adapter)
2739 {
2740         int i;
2741
2742         for (i = 0; i < adapter->num_tx_queues; i++)
2743                 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
2744 }
2745
2746 /**
2747  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
2748  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
2749  *
2750  * Returns 0 on success, negative on failure
2751  **/
2752 int igb_setup_rx_resources(struct igb_ring *rx_ring)
2753 {
2754         struct device *dev = rx_ring->dev;
2755         int size;
2756
2757         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
2758
2759         rx_ring->rx_buffer_info = vzalloc(size);
2760         if (!rx_ring->rx_buffer_info)
2761                 goto err;
2762
2763         /* Round up to nearest 4K */
2764         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
2765         rx_ring->size = ALIGN(rx_ring->size, 4096);
2766
2767         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2768                                            &rx_ring->dma, GFP_KERNEL);
2769         if (!rx_ring->desc)
2770                 goto err;
2771
2772         rx_ring->next_to_alloc = 0;
2773         rx_ring->next_to_clean = 0;
2774         rx_ring->next_to_use = 0;
2775
2776         return 0;
2777
2778 err:
2779         vfree(rx_ring->rx_buffer_info);
2780         rx_ring->rx_buffer_info = NULL;
2781         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
2782         return -ENOMEM;
2783 }
2784
2785 /**
2786  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2787  *                                (Descriptors) for all queues
2788  * @adapter: board private structure
2789  *
2790  * Return 0 on success, negative on failure
2791  **/
2792 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2793 {
2794         struct pci_dev *pdev = adapter->pdev;
2795         int i, err = 0;
2796
2797         for (i = 0; i < adapter->num_rx_queues; i++) {
2798                 err = igb_setup_rx_resources(adapter->rx_ring[i]);
2799                 if (err) {
2800                         dev_err(&pdev->dev,
2801                                 "Allocation for Rx Queue %u failed\n", i);
2802                         for (i--; i >= 0; i--)
2803                                 igb_free_rx_resources(adapter->rx_ring[i]);
2804                         break;
2805                 }
2806         }
2807
2808         return err;
2809 }
2810
2811 /**
2812  * igb_setup_mrqc - configure the multiple receive queue control registers
2813  * @adapter: Board private structure
2814  **/
2815 static void igb_setup_mrqc(struct igb_adapter *adapter)
2816 {
2817         struct e1000_hw *hw = &adapter->hw;
2818         u32 mrqc, rxcsum;
2819         u32 j, num_rx_queues, shift = 0;
2820         static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
2821                                         0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
2822                                         0xA32DCB77, 0x0CF23080, 0x3BB7426A,
2823                                         0xFA01ACBE };
2824
2825         /* Fill out hash function seeds */
2826         for (j = 0; j < 10; j++)
2827                 wr32(E1000_RSSRK(j), rsskey[j]);
2828
2829         num_rx_queues = adapter->rss_queues;
2830
2831         switch (hw->mac.type) {
2832         case e1000_82575:
2833                 shift = 6;
2834                 break;
2835         case e1000_82576:
2836                 /* 82576 supports 2 RSS queues for SR-IOV */
2837                 if (adapter->vfs_allocated_count) {
2838                         shift = 3;
2839                         num_rx_queues = 2;
2840                 }
2841                 break;
2842         default:
2843                 break;
2844         }
2845
2846         /*
2847          * Populate the indirection table 4 entries at a time.  To do this
2848          * we are generating the results for n and n+2 and then interleaving
2849          * those with the results with n+1 and n+3.
2850          */
2851         for (j = 0; j < 32; j++) {
2852                 /* first pass generates n and n+2 */
2853                 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
2854                 u32 reta = (base & 0x07800780) >> (7 - shift);
2855
2856                 /* second pass generates n+1 and n+3 */
2857                 base += 0x00010001 * num_rx_queues;
2858                 reta |= (base & 0x07800780) << (1 + shift);
2859
2860                 wr32(E1000_RETA(j), reta);
2861         }
2862
2863         /*
2864          * Disable raw packet checksumming so that RSS hash is placed in
2865          * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
2866          * offloads as they are enabled by default
2867          */
2868         rxcsum = rd32(E1000_RXCSUM);
2869         rxcsum |= E1000_RXCSUM_PCSD;
2870
2871         if (adapter->hw.mac.type >= e1000_82576)
2872                 /* Enable Receive Checksum Offload for SCTP */
2873                 rxcsum |= E1000_RXCSUM_CRCOFL;
2874
2875         /* Don't need to set TUOFL or IPOFL, they default to 1 */
2876         wr32(E1000_RXCSUM, rxcsum);
2877
2878         /* Generate RSS hash based on packet types, TCP/UDP
2879          * port numbers and/or IPv4/v6 src and dst addresses
2880          */
2881         mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
2882                E1000_MRQC_RSS_FIELD_IPV4_TCP |
2883                E1000_MRQC_RSS_FIELD_IPV6 |
2884                E1000_MRQC_RSS_FIELD_IPV6_TCP |
2885                E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
2886
2887         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2888                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2889         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2890                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2891
2892         /* If VMDq is enabled then we set the appropriate mode for that, else
2893          * we default to RSS so that an RSS hash is calculated per packet even
2894          * if we are only using one queue */
2895         if (adapter->vfs_allocated_count) {
2896                 if (hw->mac.type > e1000_82575) {
2897                         /* Set the default pool for the PF's first queue */
2898                         u32 vtctl = rd32(E1000_VT_CTL);
2899                         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2900                                    E1000_VT_CTL_DISABLE_DEF_POOL);
2901                         vtctl |= adapter->vfs_allocated_count <<
2902                                 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2903                         wr32(E1000_VT_CTL, vtctl);
2904                 }
2905                 if (adapter->rss_queues > 1)
2906                         mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2907                 else
2908                         mrqc |= E1000_MRQC_ENABLE_VMDQ;
2909         } else {
2910                 if (hw->mac.type != e1000_i211)
2911                         mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
2912         }
2913         igb_vmm_control(adapter);
2914
2915         wr32(E1000_MRQC, mrqc);
2916 }
2917
2918 /**
2919  * igb_setup_rctl - configure the receive control registers
2920  * @adapter: Board private structure
2921  **/
2922 void igb_setup_rctl(struct igb_adapter *adapter)
2923 {
2924         struct e1000_hw *hw = &adapter->hw;
2925         u32 rctl;
2926
2927         rctl = rd32(E1000_RCTL);
2928
2929         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2930         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2931
2932         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2933                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2934
2935         /*
2936          * enable stripping of CRC. It's unlikely this will break BMC
2937          * redirection as it did with e1000. Newer features require
2938          * that the HW strips the CRC.
2939          */
2940         rctl |= E1000_RCTL_SECRC;
2941
2942         /* disable store bad packets and clear size bits. */
2943         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2944
2945         /* enable LPE to prevent packets larger than max_frame_size */
2946         rctl |= E1000_RCTL_LPE;
2947
2948         /* disable queue 0 to prevent tail write w/o re-config */
2949         wr32(E1000_RXDCTL(0), 0);
2950
2951         /* Attention!!!  For SR-IOV PF driver operations you must enable
2952          * queue drop for all VF and PF queues to prevent head of line blocking
2953          * if an un-trusted VF does not provide descriptors to hardware.
2954          */
2955         if (adapter->vfs_allocated_count) {
2956                 /* set all queue drop enable bits */
2957                 wr32(E1000_QDE, ALL_QUEUES);
2958         }
2959
2960         /* This is useful for sniffing bad packets. */
2961         if (adapter->netdev->features & NETIF_F_RXALL) {
2962                 /* UPE and MPE will be handled by normal PROMISC logic
2963                  * in e1000e_set_rx_mode */
2964                 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
2965                          E1000_RCTL_BAM | /* RX All Bcast Pkts */
2966                          E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
2967
2968                 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
2969                           E1000_RCTL_DPF | /* Allow filtered pause */
2970                           E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
2971                 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
2972                  * and that breaks VLANs.
2973                  */
2974         }
2975
2976         wr32(E1000_RCTL, rctl);
2977 }
2978
2979 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2980                                    int vfn)
2981 {
2982         struct e1000_hw *hw = &adapter->hw;
2983         u32 vmolr;
2984
2985         /* if it isn't the PF check to see if VFs are enabled and
2986          * increase the size to support vlan tags */
2987         if (vfn < adapter->vfs_allocated_count &&
2988             adapter->vf_data[vfn].vlans_enabled)
2989                 size += VLAN_TAG_SIZE;
2990
2991         vmolr = rd32(E1000_VMOLR(vfn));
2992         vmolr &= ~E1000_VMOLR_RLPML_MASK;
2993         vmolr |= size | E1000_VMOLR_LPE;
2994         wr32(E1000_VMOLR(vfn), vmolr);
2995
2996         return 0;
2997 }
2998
2999 /**
3000  * igb_rlpml_set - set maximum receive packet size
3001  * @adapter: board private structure
3002  *
3003  * Configure maximum receivable packet size.
3004  **/
3005 static void igb_rlpml_set(struct igb_adapter *adapter)
3006 {
3007         u32 max_frame_size = adapter->max_frame_size;
3008         struct e1000_hw *hw = &adapter->hw;
3009         u16 pf_id = adapter->vfs_allocated_count;
3010
3011         if (pf_id) {
3012                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3013                 /*
3014                  * If we're in VMDQ or SR-IOV mode, then set global RLPML
3015                  * to our max jumbo frame size, in case we need to enable
3016                  * jumbo frames on one of the rings later.
3017                  * This will not pass over-length frames into the default
3018                  * queue because it's gated by the VMOLR.RLPML.
3019                  */
3020                 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3021         }
3022
3023         wr32(E1000_RLPML, max_frame_size);
3024 }
3025
3026 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3027                                  int vfn, bool aupe)
3028 {
3029         struct e1000_hw *hw = &adapter->hw;
3030         u32 vmolr;
3031
3032         /*
3033          * This register exists only on 82576 and newer so if we are older then
3034          * we should exit and do nothing
3035          */
3036         if (hw->mac.type < e1000_82576)
3037                 return;
3038
3039         vmolr = rd32(E1000_VMOLR(vfn));
3040         vmolr |= E1000_VMOLR_STRVLAN;      /* Strip vlan tags */
3041         if (aupe)
3042                 vmolr |= E1000_VMOLR_AUPE;        /* Accept untagged packets */
3043         else
3044                 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3045
3046         /* clear all bits that might not be set */
3047         vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3048
3049         if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3050                 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3051         /*
3052          * for VMDq only allow the VFs and pool 0 to accept broadcast and
3053          * multicast packets
3054          */
3055         if (vfn <= adapter->vfs_allocated_count)
3056                 vmolr |= E1000_VMOLR_BAM;          /* Accept broadcast */
3057
3058         wr32(E1000_VMOLR(vfn), vmolr);
3059 }
3060
3061 /**
3062  * igb_configure_rx_ring - Configure a receive ring after Reset
3063  * @adapter: board private structure
3064  * @ring: receive ring to be configured
3065  *
3066  * Configure the Rx unit of the MAC after a reset.
3067  **/
3068 void igb_configure_rx_ring(struct igb_adapter *adapter,
3069                            struct igb_ring *ring)
3070 {
3071         struct e1000_hw *hw = &adapter->hw;
3072         u64 rdba = ring->dma;
3073         int reg_idx = ring->reg_idx;
3074         u32 srrctl = 0, rxdctl = 0;
3075
3076         /* disable the queue */
3077         wr32(E1000_RXDCTL(reg_idx), 0);
3078
3079         /* Set DMA base address registers */
3080         wr32(E1000_RDBAL(reg_idx),
3081              rdba & 0x00000000ffffffffULL);
3082         wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3083         wr32(E1000_RDLEN(reg_idx),
3084                        ring->count * sizeof(union e1000_adv_rx_desc));
3085
3086         /* initialize head and tail */
3087         ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3088         wr32(E1000_RDH(reg_idx), 0);
3089         writel(0, ring->tail);
3090
3091         /* set descriptor configuration */
3092         srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3093         srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3094         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3095         if (hw->mac.type >= e1000_82580)
3096                 srrctl |= E1000_SRRCTL_TIMESTAMP;
3097         /* Only set Drop Enable if we are supporting multiple queues */
3098         if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3099                 srrctl |= E1000_SRRCTL_DROP_EN;
3100
3101         wr32(E1000_SRRCTL(reg_idx), srrctl);
3102
3103         /* set filtering for VMDQ pools */
3104         igb_set_vmolr(adapter, reg_idx & 0x7, true);
3105
3106         rxdctl |= IGB_RX_PTHRESH;
3107         rxdctl |= IGB_RX_HTHRESH << 8;
3108         rxdctl |= IGB_RX_WTHRESH << 16;
3109
3110         /* enable receive descriptor fetching */
3111         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3112         wr32(E1000_RXDCTL(reg_idx), rxdctl);
3113 }
3114
3115 /**
3116  * igb_configure_rx - Configure receive Unit after Reset
3117  * @adapter: board private structure
3118  *
3119  * Configure the Rx unit of the MAC after a reset.
3120  **/
3121 static void igb_configure_rx(struct igb_adapter *adapter)
3122 {
3123         int i;
3124
3125         /* set UTA to appropriate mode */
3126         igb_set_uta(adapter);
3127
3128         /* set the correct pool for the PF default MAC address in entry 0 */
3129         igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3130                          adapter->vfs_allocated_count);
3131
3132         /* Setup the HW Rx Head and Tail Descriptor Pointers and
3133          * the Base and Length of the Rx Descriptor Ring */
3134         for (i = 0; i < adapter->num_rx_queues; i++)
3135                 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3136 }
3137
3138 /**
3139  * igb_free_tx_resources - Free Tx Resources per Queue
3140  * @tx_ring: Tx descriptor ring for a specific queue
3141  *
3142  * Free all transmit software resources
3143  **/
3144 void igb_free_tx_resources(struct igb_ring *tx_ring)
3145 {
3146         igb_clean_tx_ring(tx_ring);
3147
3148         vfree(tx_ring->tx_buffer_info);
3149         tx_ring->tx_buffer_info = NULL;
3150
3151         /* if not set, then don't free */
3152         if (!tx_ring->desc)
3153                 return;
3154
3155         dma_free_coherent(tx_ring->dev, tx_ring->size,
3156                           tx_ring->desc, tx_ring->dma);
3157
3158         tx_ring->desc = NULL;
3159 }
3160
3161 /**
3162  * igb_free_all_tx_resources - Free Tx Resources for All Queues
3163  * @adapter: board private structure
3164  *
3165  * Free all transmit software resources
3166  **/
3167 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3168 {
3169         int i;
3170
3171         for (i = 0; i < adapter->num_tx_queues; i++)
3172                 igb_free_tx_resources(adapter->tx_ring[i]);
3173 }
3174
3175 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3176                                     struct igb_tx_buffer *tx_buffer)
3177 {
3178         if (tx_buffer->skb) {
3179                 dev_kfree_skb_any(tx_buffer->skb);
3180                 if (dma_unmap_len(tx_buffer, len))
3181                         dma_unmap_single(ring->dev,
3182                                          dma_unmap_addr(tx_buffer, dma),
3183                                          dma_unmap_len(tx_buffer, len),
3184                                          DMA_TO_DEVICE);
3185         } else if (dma_unmap_len(tx_buffer, len)) {
3186                 dma_unmap_page(ring->dev,
3187                                dma_unmap_addr(tx_buffer, dma),
3188                                dma_unmap_len(tx_buffer, len),
3189                                DMA_TO_DEVICE);
3190         }
3191         tx_buffer->next_to_watch = NULL;
3192         tx_buffer->skb = NULL;
3193         dma_unmap_len_set(tx_buffer, len, 0);
3194         /* buffer_info must be completely set up in the transmit path */
3195 }
3196
3197 /**
3198  * igb_clean_tx_ring - Free Tx Buffers
3199  * @tx_ring: ring to be cleaned
3200  **/
3201 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3202 {
3203         struct igb_tx_buffer *buffer_info;
3204         unsigned long size;
3205         u16 i;
3206
3207         if (!tx_ring->tx_buffer_info)
3208                 return;
3209         /* Free all the Tx ring sk_buffs */
3210
3211         for (i = 0; i < tx_ring->count; i++) {
3212                 buffer_info = &tx_ring->tx_buffer_info[i];
3213                 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3214         }
3215
3216         netdev_tx_reset_queue(txring_txq(tx_ring));
3217
3218         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3219         memset(tx_ring->tx_buffer_info, 0, size);
3220
3221         /* Zero out the descriptor ring */
3222         memset(tx_ring->desc, 0, tx_ring->size);
3223
3224         tx_ring->next_to_use = 0;
3225         tx_ring->next_to_clean = 0;
3226 }
3227
3228 /**
3229  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3230  * @adapter: board private structure
3231  **/
3232 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3233 {
3234         int i;
3235
3236         for (i = 0; i < adapter->num_tx_queues; i++)
3237                 igb_clean_tx_ring(adapter->tx_ring[i]);
3238 }
3239
3240 /**
3241  * igb_free_rx_resources - Free Rx Resources
3242  * @rx_ring: ring to clean the resources from
3243  *
3244  * Free all receive software resources
3245  **/
3246 void igb_free_rx_resources(struct igb_ring *rx_ring)
3247 {
3248         igb_clean_rx_ring(rx_ring);
3249
3250         vfree(rx_ring->rx_buffer_info);
3251         rx_ring->rx_buffer_info = NULL;
3252
3253         /* if not set, then don't free */
3254         if (!rx_ring->desc)
3255                 return;
3256
3257         dma_free_coherent(rx_ring->dev, rx_ring->size,
3258                           rx_ring->desc, rx_ring->dma);
3259
3260         rx_ring->desc = NULL;
3261 }
3262
3263 /**
3264  * igb_free_all_rx_resources - Free Rx Resources for All Queues
3265  * @adapter: board private structure
3266  *
3267  * Free all receive software resources
3268  **/
3269 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3270 {
3271         int i;
3272
3273         for (i = 0; i < adapter->num_rx_queues; i++)
3274                 igb_free_rx_resources(adapter->rx_ring[i]);
3275 }
3276
3277 /**
3278  * igb_clean_rx_ring - Free Rx Buffers per Queue
3279  * @rx_ring: ring to free buffers from
3280  **/
3281 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3282 {
3283         unsigned long size;
3284         u16 i;
3285
3286         if (rx_ring->skb)
3287                 dev_kfree_skb(rx_ring->skb);
3288         rx_ring->skb = NULL;
3289
3290         if (!rx_ring->rx_buffer_info)
3291                 return;
3292
3293         /* Free all the Rx ring sk_buffs */
3294         for (i = 0; i < rx_ring->count; i++) {
3295                 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3296
3297                 if (!buffer_info->page)
3298                         continue;
3299
3300                 dma_unmap_page(rx_ring->dev,
3301                                buffer_info->dma,
3302                                PAGE_SIZE,
3303                                DMA_FROM_DEVICE);
3304                 __free_page(buffer_info->page);
3305
3306                 buffer_info->page = NULL;
3307         }
3308
3309         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3310         memset(rx_ring->rx_buffer_info, 0, size);
3311
3312         /* Zero out the descriptor ring */
3313         memset(rx_ring->desc, 0, rx_ring->size);
3314
3315         rx_ring->next_to_alloc = 0;
3316         rx_ring->next_to_clean = 0;
3317         rx_ring->next_to_use = 0;
3318 }
3319
3320 /**
3321  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3322  * @adapter: board private structure
3323  **/
3324 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3325 {
3326         int i;
3327
3328         for (i = 0; i < adapter->num_rx_queues; i++)
3329                 igb_clean_rx_ring(adapter->rx_ring[i]);
3330 }
3331
3332 /**
3333  * igb_set_mac - Change the Ethernet Address of the NIC
3334  * @netdev: network interface device structure
3335  * @p: pointer to an address structure
3336  *
3337  * Returns 0 on success, negative on failure
3338  **/
3339 static int igb_set_mac(struct net_device *netdev, void *p)
3340 {
3341         struct igb_adapter *adapter = netdev_priv(netdev);
3342         struct e1000_hw *hw = &adapter->hw;
3343         struct sockaddr *addr = p;
3344
3345         if (!is_valid_ether_addr(addr->sa_data))
3346                 return -EADDRNOTAVAIL;
3347
3348         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3349         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3350
3351         /* set the correct pool for the new PF MAC address in entry 0 */
3352         igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3353                          adapter->vfs_allocated_count);
3354
3355         return 0;
3356 }
3357
3358 /**
3359  * igb_write_mc_addr_list - write multicast addresses to MTA
3360  * @netdev: network interface device structure
3361  *
3362  * Writes multicast address list to the MTA hash table.
3363  * Returns: -ENOMEM on failure
3364  *                0 on no addresses written
3365  *                X on writing X addresses to MTA
3366  **/
3367 static int igb_write_mc_addr_list(struct net_device *netdev)
3368 {
3369         struct igb_adapter *adapter = netdev_priv(netdev);
3370         struct e1000_hw *hw = &adapter->hw;
3371         struct netdev_hw_addr *ha;
3372         u8  *mta_list;
3373         int i;
3374
3375         if (netdev_mc_empty(netdev)) {
3376                 /* nothing to program, so clear mc list */
3377                 igb_update_mc_addr_list(hw, NULL, 0);
3378                 igb_restore_vf_multicasts(adapter);
3379                 return 0;
3380         }
3381
3382         mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3383         if (!mta_list)
3384                 return -ENOMEM;
3385
3386         /* The shared function expects a packed array of only addresses. */
3387         i = 0;
3388         netdev_for_each_mc_addr(ha, netdev)
3389                 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3390
3391         igb_update_mc_addr_list(hw, mta_list, i);
3392         kfree(mta_list);
3393
3394         return netdev_mc_count(netdev);
3395 }
3396
3397 /**
3398  * igb_write_uc_addr_list - write unicast addresses to RAR table
3399  * @netdev: network interface device structure
3400  *
3401  * Writes unicast address list to the RAR table.
3402  * Returns: -ENOMEM on failure/insufficient address space
3403  *                0 on no addresses written
3404  *                X on writing X addresses to the RAR table
3405  **/
3406 static int igb_write_uc_addr_list(struct net_device *netdev)
3407 {
3408         struct igb_adapter *adapter = netdev_priv(netdev);
3409         struct e1000_hw *hw = &adapter->hw;
3410         unsigned int vfn = adapter->vfs_allocated_count;
3411         unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3412         int count = 0;
3413
3414         /* return ENOMEM indicating insufficient memory for addresses */
3415         if (netdev_uc_count(netdev) > rar_entries)
3416                 return -ENOMEM;
3417
3418         if (!netdev_uc_empty(netdev) && rar_entries) {
3419                 struct netdev_hw_addr *ha;
3420
3421                 netdev_for_each_uc_addr(ha, netdev) {
3422                         if (!rar_entries)
3423                                 break;
3424                         igb_rar_set_qsel(adapter, ha->addr,
3425                                          rar_entries--,
3426                                          vfn);
3427                         count++;
3428                 }
3429         }
3430         /* write the addresses in reverse order to avoid write combining */
3431         for (; rar_entries > 0 ; rar_entries--) {
3432                 wr32(E1000_RAH(rar_entries), 0);
3433                 wr32(E1000_RAL(rar_entries), 0);
3434         }
3435         wrfl();
3436
3437         return count;
3438 }
3439
3440 /**
3441  * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3442  * @netdev: network interface device structure
3443  *
3444  * The set_rx_mode entry point is called whenever the unicast or multicast
3445  * address lists or the network interface flags are updated.  This routine is
3446  * responsible for configuring the hardware for proper unicast, multicast,
3447  * promiscuous mode, and all-multi behavior.
3448  **/
3449 static void igb_set_rx_mode(struct net_device *netdev)
3450 {
3451         struct igb_adapter *adapter = netdev_priv(netdev);
3452         struct e1000_hw *hw = &adapter->hw;
3453         unsigned int vfn = adapter->vfs_allocated_count;
3454         u32 rctl, vmolr = 0;
3455         int count;
3456
3457         /* Check for Promiscuous and All Multicast modes */
3458         rctl = rd32(E1000_RCTL);
3459
3460         /* clear the effected bits */
3461         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3462
3463         if (netdev->flags & IFF_PROMISC) {
3464                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3465                 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3466         } else {
3467                 if (netdev->flags & IFF_ALLMULTI) {
3468                         rctl |= E1000_RCTL_MPE;
3469                         vmolr |= E1000_VMOLR_MPME;
3470                 } else {
3471                         /*
3472                          * Write addresses to the MTA, if the attempt fails
3473                          * then we should just turn on promiscuous mode so
3474                          * that we can at least receive multicast traffic
3475                          */
3476                         count = igb_write_mc_addr_list(netdev);
3477                         if (count < 0) {
3478                                 rctl |= E1000_RCTL_MPE;
3479                                 vmolr |= E1000_VMOLR_MPME;
3480                         } else if (count) {
3481                                 vmolr |= E1000_VMOLR_ROMPE;
3482                         }
3483                 }
3484                 /*
3485                  * Write addresses to available RAR registers, if there is not
3486                  * sufficient space to store all the addresses then enable
3487                  * unicast promiscuous mode
3488                  */
3489                 count = igb_write_uc_addr_list(netdev);
3490                 if (count < 0) {
3491                         rctl |= E1000_RCTL_UPE;
3492                         vmolr |= E1000_VMOLR_ROPE;
3493                 }
3494                 rctl |= E1000_RCTL_VFE;
3495         }
3496         wr32(E1000_RCTL, rctl);
3497
3498         /*
3499          * In order to support SR-IOV and eventually VMDq it is necessary to set
3500          * the VMOLR to enable the appropriate modes.  Without this workaround
3501          * we will have issues with VLAN tag stripping not being done for frames
3502          * that are only arriving because we are the default pool
3503          */
3504         if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
3505                 return;
3506
3507         vmolr |= rd32(E1000_VMOLR(vfn)) &
3508                  ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3509         wr32(E1000_VMOLR(vfn), vmolr);
3510         igb_restore_vf_multicasts(adapter);
3511 }
3512
3513 static void igb_check_wvbr(struct igb_adapter *adapter)
3514 {
3515         struct e1000_hw *hw = &adapter->hw;
3516         u32 wvbr = 0;
3517
3518         switch (hw->mac.type) {
3519         case e1000_82576:
3520         case e1000_i350:
3521                 if (!(wvbr = rd32(E1000_WVBR)))
3522                         return;
3523                 break;
3524         default:
3525                 break;
3526         }
3527
3528         adapter->wvbr |= wvbr;
3529 }
3530
3531 #define IGB_STAGGERED_QUEUE_OFFSET 8
3532
3533 static void igb_spoof_check(struct igb_adapter *adapter)
3534 {
3535         int j;
3536
3537         if (!adapter->wvbr)
3538                 return;
3539
3540         for(j = 0; j < adapter->vfs_allocated_count; j++) {
3541                 if (adapter->wvbr & (1 << j) ||
3542                     adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3543                         dev_warn(&adapter->pdev->dev,
3544                                 "Spoof event(s) detected on VF %d\n", j);
3545                         adapter->wvbr &=
3546                                 ~((1 << j) |
3547                                   (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3548                 }
3549         }
3550 }
3551
3552 /* Need to wait a few seconds after link up to get diagnostic information from
3553  * the phy */
3554 static void igb_update_phy_info(unsigned long data)
3555 {
3556         struct igb_adapter *adapter = (struct igb_adapter *) data;
3557         igb_get_phy_info(&adapter->hw);
3558 }
3559
3560 /**
3561  * igb_has_link - check shared code for link and determine up/down
3562  * @adapter: pointer to driver private info
3563  **/
3564 bool igb_has_link(struct igb_adapter *adapter)
3565 {
3566         struct e1000_hw *hw = &adapter->hw;
3567         bool link_active = false;
3568         s32 ret_val = 0;
3569
3570         /* get_link_status is set on LSC (link status) interrupt or
3571          * rx sequence error interrupt.  get_link_status will stay
3572          * false until the e1000_check_for_link establishes link
3573          * for copper adapters ONLY
3574          */
3575         switch (hw->phy.media_type) {
3576         case e1000_media_type_copper:
3577                 if (hw->mac.get_link_status) {
3578                         ret_val = hw->mac.ops.check_for_link(hw);
3579                         link_active = !hw->mac.get_link_status;
3580                 } else {
3581                         link_active = true;
3582                 }
3583                 break;
3584         case e1000_media_type_internal_serdes:
3585                 ret_val = hw->mac.ops.check_for_link(hw);
3586                 link_active = hw->mac.serdes_has_link;
3587                 break;
3588         default:
3589         case e1000_media_type_unknown:
3590                 break;
3591         }
3592
3593         return link_active;
3594 }
3595
3596 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3597 {
3598         bool ret = false;
3599         u32 ctrl_ext, thstat;
3600
3601         /* check for thermal sensor event on i350 copper only */
3602         if (hw->mac.type == e1000_i350) {
3603                 thstat = rd32(E1000_THSTAT);
3604                 ctrl_ext = rd32(E1000_CTRL_EXT);
3605
3606                 if ((hw->phy.media_type == e1000_media_type_copper) &&
3607                     !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3608                         ret = !!(thstat & event);
3609                 }
3610         }
3611
3612         return ret;
3613 }
3614
3615 /**
3616  * igb_watchdog - Timer Call-back
3617  * @data: pointer to adapter cast into an unsigned long
3618  **/
3619 static void igb_watchdog(unsigned long data)
3620 {
3621         struct igb_adapter *adapter = (struct igb_adapter *)data;
3622         /* Do the rest outside of interrupt context */
3623         schedule_work(&adapter->watchdog_task);
3624 }
3625
3626 static void igb_watchdog_task(struct work_struct *work)
3627 {
3628         struct igb_adapter *adapter = container_of(work,
3629                                                    struct igb_adapter,
3630                                                    watchdog_task);
3631         struct e1000_hw *hw = &adapter->hw;
3632         struct net_device *netdev = adapter->netdev;
3633         u32 link;
3634         int i;
3635
3636         link = igb_has_link(adapter);
3637         if (link) {
3638                 /* Cancel scheduled suspend requests. */
3639                 pm_runtime_resume(netdev->dev.parent);
3640
3641                 if (!netif_carrier_ok(netdev)) {
3642                         u32 ctrl;
3643                         hw->mac.ops.get_speed_and_duplex(hw,
3644                                                          &adapter->link_speed,
3645                                                          &adapter->link_duplex);
3646
3647                         ctrl = rd32(E1000_CTRL);
3648                         /* Links status message must follow this format */
3649                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3650                                "Duplex, Flow Control: %s\n",
3651                                netdev->name,
3652                                adapter->link_speed,
3653                                adapter->link_duplex == FULL_DUPLEX ?
3654                                "Full" : "Half",
3655                                (ctrl & E1000_CTRL_TFCE) &&
3656                                (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3657                                (ctrl & E1000_CTRL_RFCE) ?  "RX" :
3658                                (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
3659
3660                         /* check for thermal sensor event */
3661                         if (igb_thermal_sensor_event(hw,
3662                             E1000_THSTAT_LINK_THROTTLE)) {
3663                                 netdev_info(netdev, "The network adapter link "
3664                                             "speed was downshifted because it "
3665                                             "overheated\n");
3666                         }
3667
3668                         /* adjust timeout factor according to speed/duplex */
3669                         adapter->tx_timeout_factor = 1;
3670                         switch (adapter->link_speed) {
3671                         case SPEED_10:
3672                                 adapter->tx_timeout_factor = 14;
3673                                 break;
3674                         case SPEED_100:
3675                                 /* maybe add some timeout factor ? */
3676                                 break;
3677                         }
3678
3679                         netif_carrier_on(netdev);
3680
3681                         igb_ping_all_vfs(adapter);
3682                         igb_check_vf_rate_limit(adapter);
3683
3684                         /* link state has changed, schedule phy info update */
3685                         if (!test_bit(__IGB_DOWN, &adapter->state))
3686                                 mod_timer(&adapter->phy_info_timer,
3687                                           round_jiffies(jiffies + 2 * HZ));
3688                 }
3689         } else {
3690                 if (netif_carrier_ok(netdev)) {
3691                         adapter->link_speed = 0;
3692                         adapter->link_duplex = 0;
3693
3694                         /* check for thermal sensor event */
3695                         if (igb_thermal_sensor_event(hw,
3696                             E1000_THSTAT_PWR_DOWN)) {
3697                                 netdev_err(netdev, "The network adapter was "
3698                                            "stopped because it overheated\n");
3699                         }
3700
3701                         /* Links status message must follow this format */
3702                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
3703                                netdev->name);
3704                         netif_carrier_off(netdev);
3705
3706                         igb_ping_all_vfs(adapter);
3707
3708                         /* link state has changed, schedule phy info update */
3709                         if (!test_bit(__IGB_DOWN, &adapter->state))
3710                                 mod_timer(&adapter->phy_info_timer,
3711                                           round_jiffies(jiffies + 2 * HZ));
3712
3713                         pm_schedule_suspend(netdev->dev.parent,
3714                                             MSEC_PER_SEC * 5);
3715                 }
3716         }
3717
3718         spin_lock(&adapter->stats64_lock);
3719         igb_update_stats(adapter, &adapter->stats64);
3720         spin_unlock(&adapter->stats64_lock);
3721
3722         for (i = 0; i < adapter->num_tx_queues; i++) {
3723                 struct igb_ring *tx_ring = adapter->tx_ring[i];
3724                 if (!netif_carrier_ok(netdev)) {
3725                         /* We've lost link, so the controller stops DMA,
3726                          * but we've got queued Tx work that's never going
3727                          * to get done, so reset controller to flush Tx.
3728                          * (Do the reset outside of interrupt context). */
3729                         if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3730                                 adapter->tx_timeout_count++;
3731                                 schedule_work(&adapter->reset_task);
3732                                 /* return immediately since reset is imminent */
3733                                 return;
3734                         }
3735                 }
3736
3737                 /* Force detection of hung controller every watchdog period */
3738                 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
3739         }
3740
3741         /* Cause software interrupt to ensure rx ring is cleaned */
3742         if (adapter->msix_entries) {
3743                 u32 eics = 0;
3744                 for (i = 0; i < adapter->num_q_vectors; i++)
3745                         eics |= adapter->q_vector[i]->eims_value;
3746                 wr32(E1000_EICS, eics);
3747         } else {
3748                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3749         }
3750
3751         igb_spoof_check(adapter);
3752
3753         /* Reset the timer */
3754         if (!test_bit(__IGB_DOWN, &adapter->state))
3755                 mod_timer(&adapter->watchdog_timer,
3756                           round_jiffies(jiffies + 2 * HZ));
3757 }
3758
3759 enum latency_range {
3760         lowest_latency = 0,
3761         low_latency = 1,
3762         bulk_latency = 2,
3763         latency_invalid = 255
3764 };
3765
3766 /**
3767  * igb_update_ring_itr - update the dynamic ITR value based on packet size
3768  *
3769  *      Stores a new ITR value based on strictly on packet size.  This
3770  *      algorithm is less sophisticated than that used in igb_update_itr,
3771  *      due to the difficulty of synchronizing statistics across multiple
3772  *      receive rings.  The divisors and thresholds used by this function
3773  *      were determined based on theoretical maximum wire speed and testing
3774  *      data, in order to minimize response time while increasing bulk
3775  *      throughput.
3776  *      This functionality is controlled by the InterruptThrottleRate module
3777  *      parameter (see igb_param.c)
3778  *      NOTE:  This function is called only when operating in a multiqueue
3779  *             receive environment.
3780  * @q_vector: pointer to q_vector
3781  **/
3782 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
3783 {
3784         int new_val = q_vector->itr_val;
3785         int avg_wire_size = 0;
3786         struct igb_adapter *adapter = q_vector->adapter;
3787         unsigned int packets;
3788
3789         /* For non-gigabit speeds, just fix the interrupt rate at 4000
3790          * ints/sec - ITR timer value of 120 ticks.
3791          */
3792         if (adapter->link_speed != SPEED_1000) {
3793                 new_val = IGB_4K_ITR;
3794                 goto set_itr_val;
3795         }
3796
3797         packets = q_vector->rx.total_packets;
3798         if (packets)
3799                 avg_wire_size = q_vector->rx.total_bytes / packets;
3800
3801         packets = q_vector->tx.total_packets;
3802         if (packets)
3803                 avg_wire_size = max_t(u32, avg_wire_size,
3804                                       q_vector->tx.total_bytes / packets);
3805
3806         /* if avg_wire_size isn't set no work was done */
3807         if (!avg_wire_size)
3808                 goto clear_counts;
3809
3810         /* Add 24 bytes to size to account for CRC, preamble, and gap */
3811         avg_wire_size += 24;
3812
3813         /* Don't starve jumbo frames */
3814         avg_wire_size = min(avg_wire_size, 3000);
3815
3816         /* Give a little boost to mid-size frames */
3817         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3818                 new_val = avg_wire_size / 3;
3819         else
3820                 new_val = avg_wire_size / 2;
3821
3822         /* conservative mode (itr 3) eliminates the lowest_latency setting */
3823         if (new_val < IGB_20K_ITR &&
3824             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3825              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3826                 new_val = IGB_20K_ITR;
3827
3828 set_itr_val:
3829         if (new_val != q_vector->itr_val) {
3830                 q_vector->itr_val = new_val;
3831                 q_vector->set_itr = 1;
3832         }
3833 clear_counts:
3834         q_vector->rx.total_bytes = 0;
3835         q_vector->rx.total_packets = 0;
3836         q_vector->tx.total_bytes = 0;
3837         q_vector->tx.total_packets = 0;
3838 }
3839
3840 /**
3841  * igb_update_itr - update the dynamic ITR value based on statistics
3842  *      Stores a new ITR value based on packets and byte
3843  *      counts during the last interrupt.  The advantage of per interrupt
3844  *      computation is faster updates and more accurate ITR for the current
3845  *      traffic pattern.  Constants in this function were computed
3846  *      based on theoretical maximum wire speed and thresholds were set based
3847  *      on testing data as well as attempting to minimize response time
3848  *      while increasing bulk throughput.
3849  *      this functionality is controlled by the InterruptThrottleRate module
3850  *      parameter (see igb_param.c)
3851  *      NOTE:  These calculations are only valid when operating in a single-
3852  *             queue environment.
3853  * @q_vector: pointer to q_vector
3854  * @ring_container: ring info to update the itr for
3855  **/
3856 static void igb_update_itr(struct igb_q_vector *q_vector,
3857                            struct igb_ring_container *ring_container)
3858 {
3859         unsigned int packets = ring_container->total_packets;
3860         unsigned int bytes = ring_container->total_bytes;
3861         u8 itrval = ring_container->itr;
3862
3863         /* no packets, exit with status unchanged */
3864         if (packets == 0)
3865                 return;
3866
3867         switch (itrval) {
3868         case lowest_latency:
3869                 /* handle TSO and jumbo frames */
3870                 if (bytes/packets > 8000)
3871                         itrval = bulk_latency;
3872                 else if ((packets < 5) && (bytes > 512))
3873                         itrval = low_latency;
3874                 break;
3875         case low_latency:  /* 50 usec aka 20000 ints/s */
3876                 if (bytes > 10000) {
3877                         /* this if handles the TSO accounting */
3878                         if (bytes/packets > 8000) {
3879                                 itrval = bulk_latency;
3880                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3881                                 itrval = bulk_latency;
3882                         } else if ((packets > 35)) {
3883                                 itrval = lowest_latency;
3884                         }
3885                 } else if (bytes/packets > 2000) {
3886                         itrval = bulk_latency;
3887                 } else if (packets <= 2 && bytes < 512) {
3888                         itrval = lowest_latency;
3889                 }
3890                 break;
3891         case bulk_latency: /* 250 usec aka 4000 ints/s */
3892                 if (bytes > 25000) {
3893                         if (packets > 35)
3894                                 itrval = low_latency;
3895                 } else if (bytes < 1500) {
3896                         itrval = low_latency;
3897                 }
3898                 break;
3899         }
3900
3901         /* clear work counters since we have the values we need */
3902         ring_container->total_bytes = 0;
3903         ring_container->total_packets = 0;
3904
3905         /* write updated itr to ring container */
3906         ring_container->itr = itrval;
3907 }
3908
3909 static void igb_set_itr(struct igb_q_vector *q_vector)
3910 {
3911         struct igb_adapter *adapter = q_vector->adapter;
3912         u32 new_itr = q_vector->itr_val;
3913         u8 current_itr = 0;
3914
3915         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3916         if (adapter->link_speed != SPEED_1000) {
3917                 current_itr = 0;
3918                 new_itr = IGB_4K_ITR;
3919                 goto set_itr_now;
3920         }
3921
3922         igb_update_itr(q_vector, &q_vector->tx);
3923         igb_update_itr(q_vector, &q_vector->rx);
3924
3925         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
3926
3927         /* conservative mode (itr 3) eliminates the lowest_latency setting */
3928         if (current_itr == lowest_latency &&
3929             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3930              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3931                 current_itr = low_latency;
3932
3933         switch (current_itr) {
3934         /* counts and packets in update_itr are dependent on these numbers */
3935         case lowest_latency:
3936                 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
3937                 break;
3938         case low_latency:
3939                 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
3940                 break;
3941         case bulk_latency:
3942                 new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
3943                 break;
3944         default:
3945                 break;
3946         }
3947
3948 set_itr_now:
3949         if (new_itr != q_vector->itr_val) {
3950                 /* this attempts to bias the interrupt rate towards Bulk
3951                  * by adding intermediate steps when interrupt rate is
3952                  * increasing */
3953                 new_itr = new_itr > q_vector->itr_val ?
3954                              max((new_itr * q_vector->itr_val) /
3955                                  (new_itr + (q_vector->itr_val >> 2)),
3956                                  new_itr) :
3957                              new_itr;
3958                 /* Don't write the value here; it resets the adapter's
3959                  * internal timer, and causes us to delay far longer than
3960                  * we should between interrupts.  Instead, we write the ITR
3961                  * value at the beginning of the next interrupt so the timing
3962                  * ends up being correct.
3963                  */
3964                 q_vector->itr_val = new_itr;
3965                 q_vector->set_itr = 1;
3966         }
3967 }
3968
3969 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
3970                             u32 type_tucmd, u32 mss_l4len_idx)
3971 {
3972         struct e1000_adv_tx_context_desc *context_desc;
3973         u16 i = tx_ring->next_to_use;
3974
3975         context_desc = IGB_TX_CTXTDESC(tx_ring, i);
3976
3977         i++;
3978         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3979
3980         /* set bits to identify this as an advanced context descriptor */
3981         type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
3982
3983         /* For 82575, context index must be unique per ring. */
3984         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
3985                 mss_l4len_idx |= tx_ring->reg_idx << 4;
3986
3987         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
3988         context_desc->seqnum_seed       = 0;
3989         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
3990         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
3991 }
3992
3993 static int igb_tso(struct igb_ring *tx_ring,
3994                    struct igb_tx_buffer *first,
3995                    u8 *hdr_len)
3996 {
3997         struct sk_buff *skb = first->skb;
3998         u32 vlan_macip_lens, type_tucmd;
3999         u32 mss_l4len_idx, l4len;
4000
4001         if (skb->ip_summed != CHECKSUM_PARTIAL)
4002                 return 0;
4003
4004         if (!skb_is_gso(skb))
4005                 return 0;
4006
4007         if (skb_header_cloned(skb)) {
4008                 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4009                 if (err)
4010                         return err;
4011         }
4012
4013         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4014         type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4015
4016         if (first->protocol == __constant_htons(ETH_P_IP)) {
4017                 struct iphdr *iph = ip_hdr(skb);
4018                 iph->tot_len = 0;
4019                 iph->check = 0;
4020                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4021                                                          iph->daddr, 0,
4022                                                          IPPROTO_TCP,
4023                                                          0);
4024                 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4025                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4026                                    IGB_TX_FLAGS_CSUM |
4027                                    IGB_TX_FLAGS_IPV4;
4028         } else if (skb_is_gso_v6(skb)) {
4029                 ipv6_hdr(skb)->payload_len = 0;
4030                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4031                                                        &ipv6_hdr(skb)->daddr,
4032                                                        0, IPPROTO_TCP, 0);
4033                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4034                                    IGB_TX_FLAGS_CSUM;
4035         }
4036
4037         /* compute header lengths */
4038         l4len = tcp_hdrlen(skb);
4039         *hdr_len = skb_transport_offset(skb) + l4len;
4040
4041         /* update gso size and bytecount with header size */
4042         first->gso_segs = skb_shinfo(skb)->gso_segs;
4043         first->bytecount += (first->gso_segs - 1) * *hdr_len;
4044
4045         /* MSS L4LEN IDX */
4046         mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4047         mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4048
4049         /* VLAN MACLEN IPLEN */
4050         vlan_macip_lens = skb_network_header_len(skb);
4051         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4052         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4053
4054         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4055
4056         return 1;
4057 }
4058
4059 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4060 {
4061         struct sk_buff *skb = first->skb;
4062         u32 vlan_macip_lens = 0;
4063         u32 mss_l4len_idx = 0;
4064         u32 type_tucmd = 0;
4065
4066         if (skb->ip_summed != CHECKSUM_PARTIAL) {
4067                 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4068                         return;
4069         } else {
4070                 u8 l4_hdr = 0;
4071                 switch (first->protocol) {
4072                 case __constant_htons(ETH_P_IP):
4073                         vlan_macip_lens |= skb_network_header_len(skb);
4074                         type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4075                         l4_hdr = ip_hdr(skb)->protocol;
4076                         break;
4077                 case __constant_htons(ETH_P_IPV6):
4078                         vlan_macip_lens |= skb_network_header_len(skb);
4079                         l4_hdr = ipv6_hdr(skb)->nexthdr;
4080                         break;
4081                 default:
4082                         if (unlikely(net_ratelimit())) {
4083                                 dev_warn(tx_ring->dev,
4084                                  "partial checksum but proto=%x!\n",
4085                                  first->protocol);
4086                         }
4087                         break;
4088                 }
4089
4090                 switch (l4_hdr) {
4091                 case IPPROTO_TCP:
4092                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4093                         mss_l4len_idx = tcp_hdrlen(skb) <<
4094                                         E1000_ADVTXD_L4LEN_SHIFT;
4095                         break;
4096                 case IPPROTO_SCTP:
4097                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4098                         mss_l4len_idx = sizeof(struct sctphdr) <<
4099                                         E1000_ADVTXD_L4LEN_SHIFT;
4100                         break;
4101                 case IPPROTO_UDP:
4102                         mss_l4len_idx = sizeof(struct udphdr) <<
4103                                         E1000_ADVTXD_L4LEN_SHIFT;
4104                         break;
4105                 default:
4106                         if (unlikely(net_ratelimit())) {
4107                                 dev_warn(tx_ring->dev,
4108                                  "partial checksum but l4 proto=%x!\n",
4109                                  l4_hdr);
4110                         }
4111                         break;
4112                 }
4113
4114                 /* update TX checksum flag */
4115                 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4116         }
4117
4118         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4119         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4120
4121         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4122 }
4123
4124 #define IGB_SET_FLAG(_input, _flag, _result) \
4125         ((_flag <= _result) ? \
4126          ((u32)(_input & _flag) * (_result / _flag)) : \
4127          ((u32)(_input & _flag) / (_flag / _result)))
4128
4129 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4130 {
4131         /* set type for advanced descriptor with frame checksum insertion */
4132         u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4133                        E1000_ADVTXD_DCMD_DEXT |
4134                        E1000_ADVTXD_DCMD_IFCS;
4135
4136         /* set HW vlan bit if vlan is present */
4137         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4138                                  (E1000_ADVTXD_DCMD_VLE));
4139
4140         /* set segmentation bits for TSO */
4141         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4142                                  (E1000_ADVTXD_DCMD_TSE));
4143
4144         /* set timestamp bit if present */
4145         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4146                                  (E1000_ADVTXD_MAC_TSTAMP));
4147
4148         /* insert frame checksum */
4149         cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4150
4151         return cmd_type;
4152 }
4153
4154 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4155                                  union e1000_adv_tx_desc *tx_desc,
4156                                  u32 tx_flags, unsigned int paylen)
4157 {
4158         u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4159
4160         /* 82575 requires a unique index per ring */
4161         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4162                 olinfo_status |= tx_ring->reg_idx << 4;
4163
4164         /* insert L4 checksum */
4165         olinfo_status |= IGB_SET_FLAG(tx_flags,
4166                                       IGB_TX_FLAGS_CSUM,
4167                                       (E1000_TXD_POPTS_TXSM << 8));
4168
4169         /* insert IPv4 checksum */
4170         olinfo_status |= IGB_SET_FLAG(tx_flags,
4171                                       IGB_TX_FLAGS_IPV4,
4172                                       (E1000_TXD_POPTS_IXSM << 8));
4173
4174         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4175 }
4176
4177 /*
4178  * The largest size we can write to the descriptor is 65535.  In order to
4179  * maintain a power of two alignment we have to limit ourselves to 32K.
4180  */
4181 #define IGB_MAX_TXD_PWR 15
4182 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
4183
4184 static void igb_tx_map(struct igb_ring *tx_ring,
4185                        struct igb_tx_buffer *first,
4186                        const u8 hdr_len)
4187 {
4188         struct sk_buff *skb = first->skb;
4189         struct igb_tx_buffer *tx_buffer;
4190         union e1000_adv_tx_desc *tx_desc;
4191         dma_addr_t dma;
4192         struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
4193         unsigned int data_len = skb->data_len;
4194         unsigned int size = skb_headlen(skb);
4195         unsigned int paylen = skb->len - hdr_len;
4196         u32 tx_flags = first->tx_flags;
4197         u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4198         u16 i = tx_ring->next_to_use;
4199
4200         tx_desc = IGB_TX_DESC(tx_ring, i);
4201
4202         igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, paylen);
4203
4204         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4205         if (dma_mapping_error(tx_ring->dev, dma))
4206                 goto dma_error;
4207
4208         /* record length, and DMA address */
4209         dma_unmap_len_set(first, len, size);
4210         dma_unmap_addr_set(first, dma, dma);
4211         tx_desc->read.buffer_addr = cpu_to_le64(dma);
4212
4213         for (;;) {
4214                 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4215                         tx_desc->read.cmd_type_len =
4216                                 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4217
4218                         i++;
4219                         tx_desc++;
4220                         if (i == tx_ring->count) {
4221                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
4222                                 i = 0;
4223                         }
4224
4225                         dma += IGB_MAX_DATA_PER_TXD;
4226                         size -= IGB_MAX_DATA_PER_TXD;
4227
4228                         tx_desc->read.olinfo_status = 0;
4229                         tx_desc->read.buffer_addr = cpu_to_le64(dma);
4230                 }
4231
4232                 if (likely(!data_len))
4233                         break;
4234
4235                 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4236
4237                 i++;
4238                 tx_desc++;
4239                 if (i == tx_ring->count) {
4240                         tx_desc = IGB_TX_DESC(tx_ring, 0);
4241                         i = 0;
4242                 }
4243
4244                 size = skb_frag_size(frag);
4245                 data_len -= size;
4246
4247                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4248                                    size, DMA_TO_DEVICE);
4249                 if (dma_mapping_error(tx_ring->dev, dma))
4250                         goto dma_error;
4251
4252                 tx_buffer = &tx_ring->tx_buffer_info[i];
4253                 dma_unmap_len_set(tx_buffer, len, size);
4254                 dma_unmap_addr_set(tx_buffer, dma, dma);
4255
4256                 tx_desc->read.olinfo_status = 0;
4257                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4258
4259                 frag++;
4260         }
4261
4262         netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4263
4264         /* write last descriptor with RS and EOP bits */
4265         cmd_type |= size | IGB_TXD_DCMD;
4266         tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4267
4268         /* set the timestamp */
4269         first->time_stamp = jiffies;
4270
4271         /*
4272          * Force memory writes to complete before letting h/w know there
4273          * are new descriptors to fetch.  (Only applicable for weak-ordered
4274          * memory model archs, such as IA-64).
4275          *
4276          * We also need this memory barrier to make certain all of the
4277          * status bits have been updated before next_to_watch is written.
4278          */
4279         wmb();
4280
4281         /* set next_to_watch value indicating a packet is present */
4282         first->next_to_watch = tx_desc;
4283
4284         i++;
4285         if (i == tx_ring->count)
4286                 i = 0;
4287
4288         tx_ring->next_to_use = i;
4289
4290         writel(i, tx_ring->tail);
4291
4292         /* we need this if more than one processor can write to our tail
4293          * at a time, it syncronizes IO on IA64/Altix systems */
4294         mmiowb();
4295
4296         return;
4297
4298 dma_error:
4299         dev_err(tx_ring->dev, "TX DMA map failed\n");
4300
4301         /* clear dma mappings for failed tx_buffer_info map */
4302         for (;;) {
4303                 tx_buffer = &tx_ring->tx_buffer_info[i];
4304                 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4305                 if (tx_buffer == first)
4306                         break;
4307                 if (i == 0)
4308                         i = tx_ring->count;
4309                 i--;
4310         }
4311
4312         tx_ring->next_to_use = i;
4313 }
4314
4315 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4316 {
4317         struct net_device *netdev = tx_ring->netdev;
4318
4319         netif_stop_subqueue(netdev, tx_ring->queue_index);
4320
4321         /* Herbert's original patch had:
4322          *  smp_mb__after_netif_stop_queue();
4323          * but since that doesn't exist yet, just open code it. */
4324         smp_mb();
4325
4326         /* We need to check again in a case another CPU has just
4327          * made room available. */
4328         if (igb_desc_unused(tx_ring) < size)
4329                 return -EBUSY;
4330
4331         /* A reprieve! */
4332         netif_wake_subqueue(netdev, tx_ring->queue_index);
4333
4334         u64_stats_update_begin(&tx_ring->tx_syncp2);
4335         tx_ring->tx_stats.restart_queue2++;
4336         u64_stats_update_end(&tx_ring->tx_syncp2);
4337
4338         return 0;
4339 }
4340
4341 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4342 {
4343         if (igb_desc_unused(tx_ring) >= size)
4344                 return 0;
4345         return __igb_maybe_stop_tx(tx_ring, size);
4346 }
4347
4348 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4349                                 struct igb_ring *tx_ring)
4350 {
4351         struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
4352         struct igb_tx_buffer *first;
4353         int tso;
4354         u32 tx_flags = 0;
4355         __be16 protocol = vlan_get_protocol(skb);
4356         u8 hdr_len = 0;
4357
4358         /* need: 1 descriptor per page,
4359          *       + 2 desc gap to keep tail from touching head,
4360          *       + 1 desc for skb->data,
4361          *       + 1 desc for context descriptor,
4362          * otherwise try next time */
4363         if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
4364                 /* this is a hard error */
4365                 return NETDEV_TX_BUSY;
4366         }
4367
4368         /* record the location of the first descriptor for this packet */
4369         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4370         first->skb = skb;
4371         first->bytecount = skb->len;
4372         first->gso_segs = 1;
4373
4374         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4375                      !(adapter->ptp_tx_skb))) {
4376                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4377                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4378
4379                 adapter->ptp_tx_skb = skb_get(skb);
4380                 if (adapter->hw.mac.type == e1000_82576)
4381                         schedule_work(&adapter->ptp_tx_work);
4382         }
4383
4384         if (vlan_tx_tag_present(skb)) {
4385                 tx_flags |= IGB_TX_FLAGS_VLAN;
4386                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4387         }
4388
4389         /* record initial flags and protocol */
4390         first->tx_flags = tx_flags;
4391         first->protocol = protocol;
4392
4393         tso = igb_tso(tx_ring, first, &hdr_len);
4394         if (tso < 0)
4395                 goto out_drop;
4396         else if (!tso)
4397                 igb_tx_csum(tx_ring, first);
4398
4399         igb_tx_map(tx_ring, first, hdr_len);
4400
4401         /* Make sure there is space in the ring for the next send. */
4402         igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
4403
4404         return NETDEV_TX_OK;
4405
4406 out_drop:
4407         igb_unmap_and_free_tx_resource(tx_ring, first);
4408
4409         return NETDEV_TX_OK;
4410 }
4411
4412 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4413                                                     struct sk_buff *skb)
4414 {
4415         unsigned int r_idx = skb->queue_mapping;
4416
4417         if (r_idx >= adapter->num_tx_queues)
4418                 r_idx = r_idx % adapter->num_tx_queues;
4419
4420         return adapter->tx_ring[r_idx];
4421 }
4422
4423 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4424                                   struct net_device *netdev)
4425 {
4426         struct igb_adapter *adapter = netdev_priv(netdev);
4427
4428         if (test_bit(__IGB_DOWN, &adapter->state)) {
4429                 dev_kfree_skb_any(skb);
4430                 return NETDEV_TX_OK;
4431         }
4432
4433         if (skb->len <= 0) {
4434                 dev_kfree_skb_any(skb);
4435                 return NETDEV_TX_OK;
4436         }
4437
4438         /*
4439          * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4440          * in order to meet this minimum size requirement.
4441          */
4442         if (unlikely(skb->len < 17)) {
4443                 if (skb_pad(skb, 17 - skb->len))
4444                         return NETDEV_TX_OK;
4445                 skb->len = 17;
4446                 skb_set_tail_pointer(skb, 17);
4447         }
4448
4449         return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4450 }
4451
4452 /**
4453  * igb_tx_timeout - Respond to a Tx Hang
4454  * @netdev: network interface device structure
4455  **/
4456 static void igb_tx_timeout(struct net_device *netdev)
4457 {
4458         struct igb_adapter *adapter = netdev_priv(netdev);
4459         struct e1000_hw *hw = &adapter->hw;
4460
4461         /* Do the reset outside of interrupt context */
4462         adapter->tx_timeout_count++;
4463
4464         if (hw->mac.type >= e1000_82580)
4465                 hw->dev_spec._82575.global_device_reset = true;
4466
4467         schedule_work(&adapter->reset_task);
4468         wr32(E1000_EICS,
4469              (adapter->eims_enable_mask & ~adapter->eims_other));
4470 }
4471
4472 static void igb_reset_task(struct work_struct *work)
4473 {
4474         struct igb_adapter *adapter;
4475         adapter = container_of(work, struct igb_adapter, reset_task);
4476
4477         igb_dump(adapter);
4478         netdev_err(adapter->netdev, "Reset adapter\n");
4479         igb_reinit_locked(adapter);
4480 }
4481
4482 /**
4483  * igb_get_stats64 - Get System Network Statistics
4484  * @netdev: network interface device structure
4485  * @stats: rtnl_link_stats64 pointer
4486  *
4487  **/
4488 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4489                                                  struct rtnl_link_stats64 *stats)
4490 {
4491         struct igb_adapter *adapter = netdev_priv(netdev);
4492
4493         spin_lock(&adapter->stats64_lock);
4494         igb_update_stats(adapter, &adapter->stats64);
4495         memcpy(stats, &adapter->stats64, sizeof(*stats));
4496         spin_unlock(&adapter->stats64_lock);
4497
4498         return stats;
4499 }
4500
4501 /**
4502  * igb_change_mtu - Change the Maximum Transfer Unit
4503  * @netdev: network interface device structure
4504  * @new_mtu: new value for maximum frame size
4505  *
4506  * Returns 0 on success, negative on failure
4507  **/
4508 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4509 {
4510         struct igb_adapter *adapter = netdev_priv(netdev);
4511         struct pci_dev *pdev = adapter->pdev;
4512         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4513
4514         if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4515                 dev_err(&pdev->dev, "Invalid MTU setting\n");
4516                 return -EINVAL;
4517         }
4518
4519 #define MAX_STD_JUMBO_FRAME_SIZE 9238
4520         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4521                 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4522                 return -EINVAL;
4523         }
4524
4525         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4526                 msleep(1);
4527
4528         /* igb_down has a dependency on max_frame_size */
4529         adapter->max_frame_size = max_frame;
4530
4531         if (netif_running(netdev))
4532                 igb_down(adapter);
4533
4534         dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4535                  netdev->mtu, new_mtu);
4536         netdev->mtu = new_mtu;
4537
4538         if (netif_running(netdev))
4539                 igb_up(adapter);
4540         else
4541                 igb_reset(adapter);
4542
4543         clear_bit(__IGB_RESETTING, &adapter->state);
4544
4545         return 0;
4546 }
4547
4548 /**
4549  * igb_update_stats - Update the board statistics counters
4550  * @adapter: board private structure
4551  **/
4552
4553 void igb_update_stats(struct igb_adapter *adapter,
4554                       struct rtnl_link_stats64 *net_stats)
4555 {
4556         struct e1000_hw *hw = &adapter->hw;
4557         struct pci_dev *pdev = adapter->pdev;
4558         u32 reg, mpc;
4559         u16 phy_tmp;
4560         int i;
4561         u64 bytes, packets;
4562         unsigned int start;
4563         u64 _bytes, _packets;
4564
4565 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4566
4567         /*
4568          * Prevent stats update while adapter is being reset, or if the pci
4569          * connection is down.
4570          */
4571         if (adapter->link_speed == 0)
4572                 return;
4573         if (pci_channel_offline(pdev))
4574                 return;
4575
4576         bytes = 0;
4577         packets = 0;
4578         for (i = 0; i < adapter->num_rx_queues; i++) {
4579                 u32 rqdpc = rd32(E1000_RQDPC(i));
4580                 struct igb_ring *ring = adapter->rx_ring[i];
4581
4582                 if (rqdpc) {
4583                         ring->rx_stats.drops += rqdpc;
4584                         net_stats->rx_fifo_errors += rqdpc;
4585                 }
4586
4587                 do {
4588                         start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4589                         _bytes = ring->rx_stats.bytes;
4590                         _packets = ring->rx_stats.packets;
4591                 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4592                 bytes += _bytes;
4593                 packets += _packets;
4594         }
4595
4596         net_stats->rx_bytes = bytes;
4597         net_stats->rx_packets = packets;
4598
4599         bytes = 0;
4600         packets = 0;
4601         for (i = 0; i < adapter->num_tx_queues; i++) {
4602                 struct igb_ring *ring = adapter->tx_ring[i];
4603                 do {
4604                         start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4605                         _bytes = ring->tx_stats.bytes;
4606                         _packets = ring->tx_stats.packets;
4607                 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4608                 bytes += _bytes;
4609                 packets += _packets;
4610         }
4611         net_stats->tx_bytes = bytes;
4612         net_stats->tx_packets = packets;
4613
4614         /* read stats registers */
4615         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4616         adapter->stats.gprc += rd32(E1000_GPRC);
4617         adapter->stats.gorc += rd32(E1000_GORCL);
4618         rd32(E1000_GORCH); /* clear GORCL */
4619         adapter->stats.bprc += rd32(E1000_BPRC);
4620         adapter->stats.mprc += rd32(E1000_MPRC);
4621         adapter->stats.roc += rd32(E1000_ROC);
4622
4623         adapter->stats.prc64 += rd32(E1000_PRC64);
4624         adapter->stats.prc127 += rd32(E1000_PRC127);
4625         adapter->stats.prc255 += rd32(E1000_PRC255);
4626         adapter->stats.prc511 += rd32(E1000_PRC511);
4627         adapter->stats.prc1023 += rd32(E1000_PRC1023);
4628         adapter->stats.prc1522 += rd32(E1000_PRC1522);
4629         adapter->stats.symerrs += rd32(E1000_SYMERRS);
4630         adapter->stats.sec += rd32(E1000_SEC);
4631
4632         mpc = rd32(E1000_MPC);
4633         adapter->stats.mpc += mpc;
4634         net_stats->rx_fifo_errors += mpc;
4635         adapter->stats.scc += rd32(E1000_SCC);
4636         adapter->stats.ecol += rd32(E1000_ECOL);
4637         adapter->stats.mcc += rd32(E1000_MCC);
4638         adapter->stats.latecol += rd32(E1000_LATECOL);
4639         adapter->stats.dc += rd32(E1000_DC);
4640         adapter->stats.rlec += rd32(E1000_RLEC);
4641         adapter->stats.xonrxc += rd32(E1000_XONRXC);
4642         adapter->stats.xontxc += rd32(E1000_XONTXC);
4643         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4644         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4645         adapter->stats.fcruc += rd32(E1000_FCRUC);
4646         adapter->stats.gptc += rd32(E1000_GPTC);
4647         adapter->stats.gotc += rd32(E1000_GOTCL);
4648         rd32(E1000_GOTCH); /* clear GOTCL */
4649         adapter->stats.rnbc += rd32(E1000_RNBC);
4650         adapter->stats.ruc += rd32(E1000_RUC);
4651         adapter->stats.rfc += rd32(E1000_RFC);
4652         adapter->stats.rjc += rd32(E1000_RJC);
4653         adapter->stats.tor += rd32(E1000_TORH);
4654         adapter->stats.tot += rd32(E1000_TOTH);
4655         adapter->stats.tpr += rd32(E1000_TPR);
4656
4657         adapter->stats.ptc64 += rd32(E1000_PTC64);
4658         adapter->stats.ptc127 += rd32(E1000_PTC127);
4659         adapter->stats.ptc255 += rd32(E1000_PTC255);
4660         adapter->stats.ptc511 += rd32(E1000_PTC511);
4661         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4662         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4663
4664         adapter->stats.mptc += rd32(E1000_MPTC);
4665         adapter->stats.bptc += rd32(E1000_BPTC);
4666
4667         adapter->stats.tpt += rd32(E1000_TPT);
4668         adapter->stats.colc += rd32(E1000_COLC);
4669
4670         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4671         /* read internal phy specific stats */
4672         reg = rd32(E1000_CTRL_EXT);
4673         if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4674                 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4675
4676                 /* this stat has invalid values on i210/i211 */
4677                 if ((hw->mac.type != e1000_i210) &&
4678                     (hw->mac.type != e1000_i211))
4679                         adapter->stats.tncrs += rd32(E1000_TNCRS);
4680         }
4681
4682         adapter->stats.tsctc += rd32(E1000_TSCTC);
4683         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4684
4685         adapter->stats.iac += rd32(E1000_IAC);
4686         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4687         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4688         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4689         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4690         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4691         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4692         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4693         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4694
4695         /* Fill out the OS statistics structure */
4696         net_stats->multicast = adapter->stats.mprc;
4697         net_stats->collisions = adapter->stats.colc;
4698
4699         /* Rx Errors */
4700
4701         /* RLEC on some newer hardware can be incorrect so build
4702          * our own version based on RUC and ROC */
4703         net_stats->rx_errors = adapter->stats.rxerrc +
4704                 adapter->stats.crcerrs + adapter->stats.algnerrc +
4705                 adapter->stats.ruc + adapter->stats.roc +
4706                 adapter->stats.cexterr;
4707         net_stats->rx_length_errors = adapter->stats.ruc +
4708                                       adapter->stats.roc;
4709         net_stats->rx_crc_errors = adapter->stats.crcerrs;
4710         net_stats->rx_frame_errors = adapter->stats.algnerrc;
4711         net_stats->rx_missed_errors = adapter->stats.mpc;
4712
4713         /* Tx Errors */
4714         net_stats->tx_errors = adapter->stats.ecol +
4715                                adapter->stats.latecol;
4716         net_stats->tx_aborted_errors = adapter->stats.ecol;
4717         net_stats->tx_window_errors = adapter->stats.latecol;
4718         net_stats->tx_carrier_errors = adapter->stats.tncrs;
4719
4720         /* Tx Dropped needs to be maintained elsewhere */
4721
4722         /* Phy Stats */
4723         if (hw->phy.media_type == e1000_media_type_copper) {
4724                 if ((adapter->link_speed == SPEED_1000) &&
4725                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
4726                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4727                         adapter->phy_stats.idle_errors += phy_tmp;
4728                 }
4729         }
4730
4731         /* Management Stats */
4732         adapter->stats.mgptc += rd32(E1000_MGTPTC);
4733         adapter->stats.mgprc += rd32(E1000_MGTPRC);
4734         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4735
4736         /* OS2BMC Stats */
4737         reg = rd32(E1000_MANC);
4738         if (reg & E1000_MANC_EN_BMC2OS) {
4739                 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4740                 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4741                 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4742                 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4743         }
4744 }
4745
4746 static irqreturn_t igb_msix_other(int irq, void *data)
4747 {
4748         struct igb_adapter *adapter = data;
4749         struct e1000_hw *hw = &adapter->hw;
4750         u32 icr = rd32(E1000_ICR);
4751         /* reading ICR causes bit 31 of EICR to be cleared */
4752
4753         if (icr & E1000_ICR_DRSTA)
4754                 schedule_work(&adapter->reset_task);
4755
4756         if (icr & E1000_ICR_DOUTSYNC) {
4757                 /* HW is reporting DMA is out of sync */
4758                 adapter->stats.doosync++;
4759                 /* The DMA Out of Sync is also indication of a spoof event
4760                  * in IOV mode. Check the Wrong VM Behavior register to
4761                  * see if it is really a spoof event. */
4762                 igb_check_wvbr(adapter);
4763         }
4764
4765         /* Check for a mailbox event */
4766         if (icr & E1000_ICR_VMMB)
4767                 igb_msg_task(adapter);
4768
4769         if (icr & E1000_ICR_LSC) {
4770                 hw->mac.get_link_status = 1;
4771                 /* guard against interrupt when we're going down */
4772                 if (!test_bit(__IGB_DOWN, &adapter->state))
4773                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4774         }
4775
4776         if (icr & E1000_ICR_TS) {
4777                 u32 tsicr = rd32(E1000_TSICR);
4778
4779                 if (tsicr & E1000_TSICR_TXTS) {
4780                         /* acknowledge the interrupt */
4781                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
4782                         /* retrieve hardware timestamp */
4783                         schedule_work(&adapter->ptp_tx_work);
4784                 }
4785         }
4786
4787         wr32(E1000_EIMS, adapter->eims_other);
4788
4789         return IRQ_HANDLED;
4790 }
4791
4792 static void igb_write_itr(struct igb_q_vector *q_vector)
4793 {
4794         struct igb_adapter *adapter = q_vector->adapter;
4795         u32 itr_val = q_vector->itr_val & 0x7FFC;
4796
4797         if (!q_vector->set_itr)
4798                 return;
4799
4800         if (!itr_val)
4801                 itr_val = 0x4;
4802
4803         if (adapter->hw.mac.type == e1000_82575)
4804                 itr_val |= itr_val << 16;
4805         else
4806                 itr_val |= E1000_EITR_CNT_IGNR;
4807
4808         writel(itr_val, q_vector->itr_register);
4809         q_vector->set_itr = 0;
4810 }
4811
4812 static irqreturn_t igb_msix_ring(int irq, void *data)
4813 {
4814         struct igb_q_vector *q_vector = data;
4815
4816         /* Write the ITR value calculated from the previous interrupt. */
4817         igb_write_itr(q_vector);
4818
4819         napi_schedule(&q_vector->napi);
4820
4821         return IRQ_HANDLED;
4822 }
4823
4824 #ifdef CONFIG_IGB_DCA
4825 static void igb_update_tx_dca(struct igb_adapter *adapter,
4826                               struct igb_ring *tx_ring,
4827                               int cpu)
4828 {
4829         struct e1000_hw *hw = &adapter->hw;
4830         u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
4831
4832         if (hw->mac.type != e1000_82575)
4833                 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
4834
4835         /*
4836          * We can enable relaxed ordering for reads, but not writes when
4837          * DCA is enabled.  This is due to a known issue in some chipsets
4838          * which will cause the DCA tag to be cleared.
4839          */
4840         txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
4841                   E1000_DCA_TXCTRL_DATA_RRO_EN |
4842                   E1000_DCA_TXCTRL_DESC_DCA_EN;
4843
4844         wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
4845 }
4846
4847 static void igb_update_rx_dca(struct igb_adapter *adapter,
4848                               struct igb_ring *rx_ring,
4849                               int cpu)
4850 {
4851         struct e1000_hw *hw = &adapter->hw;
4852         u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
4853
4854         if (hw->mac.type != e1000_82575)
4855                 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
4856
4857         /*
4858          * We can enable relaxed ordering for reads, but not writes when
4859          * DCA is enabled.  This is due to a known issue in some chipsets
4860          * which will cause the DCA tag to be cleared.
4861          */
4862         rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
4863                   E1000_DCA_RXCTRL_DESC_DCA_EN;
4864
4865         wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
4866 }
4867
4868 static void igb_update_dca(struct igb_q_vector *q_vector)
4869 {
4870         struct igb_adapter *adapter = q_vector->adapter;
4871         int cpu = get_cpu();
4872
4873         if (q_vector->cpu == cpu)
4874                 goto out_no_update;
4875
4876         if (q_vector->tx.ring)
4877                 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
4878
4879         if (q_vector->rx.ring)
4880                 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
4881
4882         q_vector->cpu = cpu;
4883 out_no_update:
4884         put_cpu();
4885 }
4886
4887 static void igb_setup_dca(struct igb_adapter *adapter)
4888 {
4889         struct e1000_hw *hw = &adapter->hw;
4890         int i;
4891
4892         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
4893                 return;
4894
4895         /* Always use CB2 mode, difference is masked in the CB driver. */
4896         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4897
4898         for (i = 0; i < adapter->num_q_vectors; i++) {
4899                 adapter->q_vector[i]->cpu = -1;
4900                 igb_update_dca(adapter->q_vector[i]);
4901         }
4902 }
4903
4904 static int __igb_notify_dca(struct device *dev, void *data)
4905 {
4906         struct net_device *netdev = dev_get_drvdata(dev);
4907         struct igb_adapter *adapter = netdev_priv(netdev);
4908         struct pci_dev *pdev = adapter->pdev;
4909         struct e1000_hw *hw = &adapter->hw;
4910         unsigned long event = *(unsigned long *)data;
4911
4912         switch (event) {
4913         case DCA_PROVIDER_ADD:
4914                 /* if already enabled, don't do it again */
4915                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
4916                         break;
4917                 if (dca_add_requester(dev) == 0) {
4918                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
4919                         dev_info(&pdev->dev, "DCA enabled\n");
4920                         igb_setup_dca(adapter);
4921                         break;
4922                 }
4923                 /* Fall Through since DCA is disabled. */
4924         case DCA_PROVIDER_REMOVE:
4925                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
4926                         /* without this a class_device is left
4927                          * hanging around in the sysfs model */
4928                         dca_remove_requester(dev);
4929                         dev_info(&pdev->dev, "DCA disabled\n");
4930                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
4931                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
4932                 }
4933                 break;
4934         }
4935
4936         return 0;
4937 }
4938
4939 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4940                           void *p)
4941 {
4942         int ret_val;
4943
4944         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4945                                          __igb_notify_dca);
4946
4947         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4948 }
4949 #endif /* CONFIG_IGB_DCA */
4950
4951 #ifdef CONFIG_PCI_IOV
4952 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
4953 {
4954         unsigned char mac_addr[ETH_ALEN];
4955
4956         eth_random_addr(mac_addr);
4957         igb_set_vf_mac(adapter, vf, mac_addr);
4958
4959         return 0;
4960 }
4961
4962 static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
4963 {
4964         struct pci_dev *pdev = adapter->pdev;
4965         struct pci_dev *vfdev;
4966         int dev_id;
4967
4968         switch (adapter->hw.mac.type) {
4969         case e1000_82576:
4970                 dev_id = IGB_82576_VF_DEV_ID;
4971                 break;
4972         case e1000_i350:
4973                 dev_id = IGB_I350_VF_DEV_ID;
4974                 break;
4975         default:
4976                 return false;
4977         }
4978
4979         /* loop through all the VFs to see if we own any that are assigned */
4980         vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
4981         while (vfdev) {
4982                 /* if we don't own it we don't care */
4983                 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
4984                         /* if it is assigned we cannot release it */
4985                         if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
4986                                 return true;
4987                 }
4988
4989                 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
4990         }
4991
4992         return false;
4993 }
4994
4995 #endif
4996 static void igb_ping_all_vfs(struct igb_adapter *adapter)
4997 {
4998         struct e1000_hw *hw = &adapter->hw;
4999         u32 ping;
5000         int i;
5001
5002         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5003                 ping = E1000_PF_CONTROL_MSG;
5004                 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5005                         ping |= E1000_VT_MSGTYPE_CTS;
5006                 igb_write_mbx(hw, &ping, 1, i);
5007         }
5008 }
5009
5010 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5011 {
5012         struct e1000_hw *hw = &adapter->hw;
5013         u32 vmolr = rd32(E1000_VMOLR(vf));
5014         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5015
5016         vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5017                             IGB_VF_FLAG_MULTI_PROMISC);
5018         vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5019
5020         if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5021                 vmolr |= E1000_VMOLR_MPME;
5022                 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5023                 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5024         } else {
5025                 /*
5026                  * if we have hashes and we are clearing a multicast promisc
5027                  * flag we need to write the hashes to the MTA as this step
5028                  * was previously skipped
5029                  */
5030                 if (vf_data->num_vf_mc_hashes > 30) {
5031                         vmolr |= E1000_VMOLR_MPME;
5032                 } else if (vf_data->num_vf_mc_hashes) {
5033                         int j;
5034                         vmolr |= E1000_VMOLR_ROMPE;
5035                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5036                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5037                 }
5038         }
5039
5040         wr32(E1000_VMOLR(vf), vmolr);
5041
5042         /* there are flags left unprocessed, likely not supported */
5043         if (*msgbuf & E1000_VT_MSGINFO_MASK)
5044                 return -EINVAL;
5045
5046         return 0;
5047
5048 }
5049
5050 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5051                                   u32 *msgbuf, u32 vf)
5052 {
5053         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5054         u16 *hash_list = (u16 *)&msgbuf[1];
5055         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5056         int i;
5057
5058         /* salt away the number of multicast addresses assigned
5059          * to this VF for later use to restore when the PF multi cast
5060          * list changes
5061          */
5062         vf_data->num_vf_mc_hashes = n;
5063
5064         /* only up to 30 hash values supported */
5065         if (n > 30)
5066                 n = 30;
5067
5068         /* store the hashes for later use */
5069         for (i = 0; i < n; i++)
5070                 vf_data->vf_mc_hashes[i] = hash_list[i];
5071
5072         /* Flush and reset the mta with the new values */
5073         igb_set_rx_mode(adapter->netdev);
5074
5075         return 0;
5076 }
5077
5078 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5079 {
5080         struct e1000_hw *hw = &adapter->hw;
5081         struct vf_data_storage *vf_data;
5082         int i, j;
5083
5084         for (i = 0; i < adapter->vfs_allocated_count; i++) {
5085                 u32 vmolr = rd32(E1000_VMOLR(i));
5086                 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5087
5088                 vf_data = &adapter->vf_data[i];
5089
5090                 if ((vf_data->num_vf_mc_hashes > 30) ||
5091                     (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5092                         vmolr |= E1000_VMOLR_MPME;
5093                 } else if (vf_data->num_vf_mc_hashes) {
5094                         vmolr |= E1000_VMOLR_ROMPE;
5095                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5096                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5097                 }
5098                 wr32(E1000_VMOLR(i), vmolr);
5099         }
5100 }
5101
5102 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5103 {
5104         struct e1000_hw *hw = &adapter->hw;
5105         u32 pool_mask, reg, vid;
5106         int i;
5107
5108         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5109
5110         /* Find the vlan filter for this id */
5111         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5112                 reg = rd32(E1000_VLVF(i));
5113
5114                 /* remove the vf from the pool */
5115                 reg &= ~pool_mask;
5116
5117                 /* if pool is empty then remove entry from vfta */
5118                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5119                     (reg & E1000_VLVF_VLANID_ENABLE)) {
5120                         reg = 0;
5121                         vid = reg & E1000_VLVF_VLANID_MASK;
5122                         igb_vfta_set(hw, vid, false);
5123                 }
5124
5125                 wr32(E1000_VLVF(i), reg);
5126         }
5127
5128         adapter->vf_data[vf].vlans_enabled = 0;
5129 }
5130
5131 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5132 {
5133         struct e1000_hw *hw = &adapter->hw;
5134         u32 reg, i;
5135
5136         /* The vlvf table only exists on 82576 hardware and newer */
5137         if (hw->mac.type < e1000_82576)
5138                 return -1;
5139
5140         /* we only need to do this if VMDq is enabled */
5141         if (!adapter->vfs_allocated_count)
5142                 return -1;
5143
5144         /* Find the vlan filter for this id */
5145         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5146                 reg = rd32(E1000_VLVF(i));
5147                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5148                     vid == (reg & E1000_VLVF_VLANID_MASK))
5149                         break;
5150         }
5151
5152         if (add) {
5153                 if (i == E1000_VLVF_ARRAY_SIZE) {
5154                         /* Did not find a matching VLAN ID entry that was
5155                          * enabled.  Search for a free filter entry, i.e.
5156                          * one without the enable bit set
5157                          */
5158                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5159                                 reg = rd32(E1000_VLVF(i));
5160                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5161                                         break;
5162                         }
5163                 }
5164                 if (i < E1000_VLVF_ARRAY_SIZE) {
5165                         /* Found an enabled/available entry */
5166                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5167
5168                         /* if !enabled we need to set this up in vfta */
5169                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5170                                 /* add VID to filter table */
5171                                 igb_vfta_set(hw, vid, true);
5172                                 reg |= E1000_VLVF_VLANID_ENABLE;
5173                         }
5174                         reg &= ~E1000_VLVF_VLANID_MASK;
5175                         reg |= vid;
5176                         wr32(E1000_VLVF(i), reg);
5177
5178                         /* do not modify RLPML for PF devices */
5179                         if (vf >= adapter->vfs_allocated_count)
5180                                 return 0;
5181
5182                         if (!adapter->vf_data[vf].vlans_enabled) {
5183                                 u32 size;
5184                                 reg = rd32(E1000_VMOLR(vf));
5185                                 size = reg & E1000_VMOLR_RLPML_MASK;
5186                                 size += 4;
5187                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5188                                 reg |= size;
5189                                 wr32(E1000_VMOLR(vf), reg);
5190                         }
5191
5192                         adapter->vf_data[vf].vlans_enabled++;
5193                 }
5194         } else {
5195                 if (i < E1000_VLVF_ARRAY_SIZE) {
5196                         /* remove vf from the pool */
5197                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5198                         /* if pool is empty then remove entry from vfta */
5199                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5200                                 reg = 0;
5201                                 igb_vfta_set(hw, vid, false);
5202                         }
5203                         wr32(E1000_VLVF(i), reg);
5204
5205                         /* do not modify RLPML for PF devices */
5206                         if (vf >= adapter->vfs_allocated_count)
5207                                 return 0;
5208
5209                         adapter->vf_data[vf].vlans_enabled--;
5210                         if (!adapter->vf_data[vf].vlans_enabled) {
5211                                 u32 size;
5212                                 reg = rd32(E1000_VMOLR(vf));
5213                                 size = reg & E1000_VMOLR_RLPML_MASK;
5214                                 size -= 4;
5215                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5216                                 reg |= size;
5217                                 wr32(E1000_VMOLR(vf), reg);
5218                         }
5219                 }
5220         }
5221         return 0;
5222 }
5223
5224 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5225 {
5226         struct e1000_hw *hw = &adapter->hw;
5227
5228         if (vid)
5229                 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5230         else
5231                 wr32(E1000_VMVIR(vf), 0);
5232 }
5233
5234 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5235                                int vf, u16 vlan, u8 qos)
5236 {
5237         int err = 0;
5238         struct igb_adapter *adapter = netdev_priv(netdev);
5239
5240         if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5241                 return -EINVAL;
5242         if (vlan || qos) {
5243                 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5244                 if (err)
5245                         goto out;
5246                 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5247                 igb_set_vmolr(adapter, vf, !vlan);
5248                 adapter->vf_data[vf].pf_vlan = vlan;
5249                 adapter->vf_data[vf].pf_qos = qos;
5250                 dev_info(&adapter->pdev->dev,
5251                          "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5252                 if (test_bit(__IGB_DOWN, &adapter->state)) {
5253                         dev_warn(&adapter->pdev->dev,
5254                                  "The VF VLAN has been set,"
5255                                  " but the PF device is not up.\n");
5256                         dev_warn(&adapter->pdev->dev,
5257                                  "Bring the PF device up before"
5258                                  " attempting to use the VF device.\n");
5259                 }
5260         } else {
5261                 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5262                                    false, vf);
5263                 igb_set_vmvir(adapter, vlan, vf);
5264                 igb_set_vmolr(adapter, vf, true);
5265                 adapter->vf_data[vf].pf_vlan = 0;
5266                 adapter->vf_data[vf].pf_qos = 0;
5267        }
5268 out:
5269        return err;
5270 }
5271
5272 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5273 {
5274         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5275         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5276
5277         return igb_vlvf_set(adapter, vid, add, vf);
5278 }
5279
5280 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5281 {
5282         /* clear flags - except flag that indicates PF has set the MAC */
5283         adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5284         adapter->vf_data[vf].last_nack = jiffies;
5285
5286         /* reset offloads to defaults */
5287         igb_set_vmolr(adapter, vf, true);
5288
5289         /* reset vlans for device */
5290         igb_clear_vf_vfta(adapter, vf);
5291         if (adapter->vf_data[vf].pf_vlan)
5292                 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5293                                     adapter->vf_data[vf].pf_vlan,
5294                                     adapter->vf_data[vf].pf_qos);
5295         else
5296                 igb_clear_vf_vfta(adapter, vf);
5297
5298         /* reset multicast table array for vf */
5299         adapter->vf_data[vf].num_vf_mc_hashes = 0;
5300
5301         /* Flush and reset the mta with the new values */
5302         igb_set_rx_mode(adapter->netdev);
5303 }
5304
5305 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5306 {
5307         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5308
5309         /* generate a new mac address as we were hotplug removed/added */
5310         if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5311                 eth_random_addr(vf_mac);
5312
5313         /* process remaining reset events */
5314         igb_vf_reset(adapter, vf);
5315 }
5316
5317 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5318 {
5319         struct e1000_hw *hw = &adapter->hw;
5320         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5321         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5322         u32 reg, msgbuf[3];
5323         u8 *addr = (u8 *)(&msgbuf[1]);
5324
5325         /* process all the same items cleared in a function level reset */
5326         igb_vf_reset(adapter, vf);
5327
5328         /* set vf mac address */
5329         igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5330
5331         /* enable transmit and receive for vf */
5332         reg = rd32(E1000_VFTE);
5333         wr32(E1000_VFTE, reg | (1 << vf));
5334         reg = rd32(E1000_VFRE);
5335         wr32(E1000_VFRE, reg | (1 << vf));
5336
5337         adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5338
5339         /* reply to reset with ack and vf mac address */
5340         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5341         memcpy(addr, vf_mac, 6);
5342         igb_write_mbx(hw, msgbuf, 3, vf);
5343 }
5344
5345 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5346 {
5347         /*
5348          * The VF MAC Address is stored in a packed array of bytes
5349          * starting at the second 32 bit word of the msg array
5350          */
5351         unsigned char *addr = (char *)&msg[1];
5352         int err = -1;
5353
5354         if (is_valid_ether_addr(addr))
5355                 err = igb_set_vf_mac(adapter, vf, addr);
5356
5357         return err;
5358 }
5359
5360 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5361 {
5362         struct e1000_hw *hw = &adapter->hw;
5363         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5364         u32 msg = E1000_VT_MSGTYPE_NACK;
5365
5366         /* if device isn't clear to send it shouldn't be reading either */
5367         if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5368             time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5369                 igb_write_mbx(hw, &msg, 1, vf);
5370                 vf_data->last_nack = jiffies;
5371         }
5372 }
5373
5374 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5375 {
5376         struct pci_dev *pdev = adapter->pdev;
5377         u32 msgbuf[E1000_VFMAILBOX_SIZE];
5378         struct e1000_hw *hw = &adapter->hw;
5379         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5380         s32 retval;
5381
5382         retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5383
5384         if (retval) {
5385                 /* if receive failed revoke VF CTS stats and restart init */
5386                 dev_err(&pdev->dev, "Error receiving message from VF\n");
5387                 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5388                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5389                         return;
5390                 goto out;
5391         }
5392
5393         /* this is a message we already processed, do nothing */
5394         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5395                 return;
5396
5397         /*
5398          * until the vf completes a reset it should not be
5399          * allowed to start any configuration.
5400          */
5401
5402         if (msgbuf[0] == E1000_VF_RESET) {
5403                 igb_vf_reset_msg(adapter, vf);
5404                 return;
5405         }
5406
5407         if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5408                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5409                         return;
5410                 retval = -1;
5411                 goto out;
5412         }
5413
5414         switch ((msgbuf[0] & 0xFFFF)) {
5415         case E1000_VF_SET_MAC_ADDR:
5416                 retval = -EINVAL;
5417                 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5418                         retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5419                 else
5420                         dev_warn(&pdev->dev,
5421                                  "VF %d attempted to override administratively "
5422                                  "set MAC address\nReload the VF driver to "
5423                                  "resume operations\n", vf);
5424                 break;
5425         case E1000_VF_SET_PROMISC:
5426                 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5427                 break;
5428         case E1000_VF_SET_MULTICAST:
5429                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5430                 break;
5431         case E1000_VF_SET_LPE:
5432                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5433                 break;
5434         case E1000_VF_SET_VLAN:
5435                 retval = -1;
5436                 if (vf_data->pf_vlan)
5437                         dev_warn(&pdev->dev,
5438                                  "VF %d attempted to override administratively "
5439                                  "set VLAN tag\nReload the VF driver to "
5440                                  "resume operations\n", vf);
5441                 else
5442                         retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5443                 break;
5444         default:
5445                 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5446                 retval = -1;
5447                 break;
5448         }
5449
5450         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5451 out:
5452         /* notify the VF of the results of what it sent us */
5453         if (retval)
5454                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5455         else
5456                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5457
5458         igb_write_mbx(hw, msgbuf, 1, vf);
5459 }
5460
5461 static void igb_msg_task(struct igb_adapter *adapter)
5462 {
5463         struct e1000_hw *hw = &adapter->hw;
5464         u32 vf;
5465
5466         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5467                 /* process any reset requests */
5468                 if (!igb_check_for_rst(hw, vf))
5469                         igb_vf_reset_event(adapter, vf);
5470
5471                 /* process any messages pending */
5472                 if (!igb_check_for_msg(hw, vf))
5473                         igb_rcv_msg_from_vf(adapter, vf);
5474
5475                 /* process any acks */
5476                 if (!igb_check_for_ack(hw, vf))
5477                         igb_rcv_ack_from_vf(adapter, vf);
5478         }
5479 }
5480
5481 /**
5482  *  igb_set_uta - Set unicast filter table address
5483  *  @adapter: board private structure
5484  *
5485  *  The unicast table address is a register array of 32-bit registers.
5486  *  The table is meant to be used in a way similar to how the MTA is used
5487  *  however due to certain limitations in the hardware it is necessary to
5488  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5489  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
5490  **/
5491 static void igb_set_uta(struct igb_adapter *adapter)
5492 {
5493         struct e1000_hw *hw = &adapter->hw;
5494         int i;
5495
5496         /* The UTA table only exists on 82576 hardware and newer */
5497         if (hw->mac.type < e1000_82576)
5498                 return;
5499
5500         /* we only need to do this if VMDq is enabled */
5501         if (!adapter->vfs_allocated_count)
5502                 return;
5503
5504         for (i = 0; i < hw->mac.uta_reg_count; i++)
5505                 array_wr32(E1000_UTA, i, ~0);
5506 }
5507
5508 /**
5509  * igb_intr_msi - Interrupt Handler
5510  * @irq: interrupt number
5511  * @data: pointer to a network interface device structure
5512  **/
5513 static irqreturn_t igb_intr_msi(int irq, void *data)
5514 {
5515         struct igb_adapter *adapter = data;
5516         struct igb_q_vector *q_vector = adapter->q_vector[0];
5517         struct e1000_hw *hw = &adapter->hw;
5518         /* read ICR disables interrupts using IAM */
5519         u32 icr = rd32(E1000_ICR);
5520
5521         igb_write_itr(q_vector);
5522
5523         if (icr & E1000_ICR_DRSTA)
5524                 schedule_work(&adapter->reset_task);
5525
5526         if (icr & E1000_ICR_DOUTSYNC) {
5527                 /* HW is reporting DMA is out of sync */
5528                 adapter->stats.doosync++;
5529         }
5530
5531         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5532                 hw->mac.get_link_status = 1;
5533                 if (!test_bit(__IGB_DOWN, &adapter->state))
5534                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5535         }
5536
5537         if (icr & E1000_ICR_TS) {
5538                 u32 tsicr = rd32(E1000_TSICR);
5539
5540                 if (tsicr & E1000_TSICR_TXTS) {
5541                         /* acknowledge the interrupt */
5542                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5543                         /* retrieve hardware timestamp */
5544                         schedule_work(&adapter->ptp_tx_work);
5545                 }
5546         }
5547
5548         napi_schedule(&q_vector->napi);
5549
5550         return IRQ_HANDLED;
5551 }
5552
5553 /**
5554  * igb_intr - Legacy Interrupt Handler
5555  * @irq: interrupt number
5556  * @data: pointer to a network interface device structure
5557  **/
5558 static irqreturn_t igb_intr(int irq, void *data)
5559 {
5560         struct igb_adapter *adapter = data;
5561         struct igb_q_vector *q_vector = adapter->q_vector[0];
5562         struct e1000_hw *hw = &adapter->hw;
5563         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
5564          * need for the IMC write */
5565         u32 icr = rd32(E1000_ICR);
5566
5567         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5568          * not set, then the adapter didn't send an interrupt */
5569         if (!(icr & E1000_ICR_INT_ASSERTED))
5570                 return IRQ_NONE;
5571
5572         igb_write_itr(q_vector);
5573
5574         if (icr & E1000_ICR_DRSTA)
5575                 schedule_work(&adapter->reset_task);
5576
5577         if (icr & E1000_ICR_DOUTSYNC) {
5578                 /* HW is reporting DMA is out of sync */
5579                 adapter->stats.doosync++;
5580         }
5581
5582         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5583                 hw->mac.get_link_status = 1;
5584                 /* guard against interrupt when we're going down */
5585                 if (!test_bit(__IGB_DOWN, &adapter->state))
5586                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5587         }
5588
5589         if (icr & E1000_ICR_TS) {
5590                 u32 tsicr = rd32(E1000_TSICR);
5591
5592                 if (tsicr & E1000_TSICR_TXTS) {
5593                         /* acknowledge the interrupt */
5594                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5595                         /* retrieve hardware timestamp */
5596                         schedule_work(&adapter->ptp_tx_work);
5597                 }
5598         }
5599
5600         napi_schedule(&q_vector->napi);
5601
5602         return IRQ_HANDLED;
5603 }
5604
5605 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5606 {
5607         struct igb_adapter *adapter = q_vector->adapter;
5608         struct e1000_hw *hw = &adapter->hw;
5609
5610         if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5611             (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5612                 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5613                         igb_set_itr(q_vector);
5614                 else
5615                         igb_update_ring_itr(q_vector);
5616         }
5617
5618         if (!test_bit(__IGB_DOWN, &adapter->state)) {
5619                 if (adapter->msix_entries)
5620                         wr32(E1000_EIMS, q_vector->eims_value);
5621                 else
5622                         igb_irq_enable(adapter);
5623         }
5624 }
5625
5626 /**
5627  * igb_poll - NAPI Rx polling callback
5628  * @napi: napi polling structure
5629  * @budget: count of how many packets we should handle
5630  **/
5631 static int igb_poll(struct napi_struct *napi, int budget)
5632 {
5633         struct igb_q_vector *q_vector = container_of(napi,
5634                                                      struct igb_q_vector,
5635                                                      napi);
5636         bool clean_complete = true;
5637
5638 #ifdef CONFIG_IGB_DCA
5639         if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5640                 igb_update_dca(q_vector);
5641 #endif
5642         if (q_vector->tx.ring)
5643                 clean_complete = igb_clean_tx_irq(q_vector);
5644
5645         if (q_vector->rx.ring)
5646                 clean_complete &= igb_clean_rx_irq(q_vector, budget);
5647
5648         /* If all work not completed, return budget and keep polling */
5649         if (!clean_complete)
5650                 return budget;
5651
5652         /* If not enough Rx work done, exit the polling mode */
5653         napi_complete(napi);
5654         igb_ring_irq_enable(q_vector);
5655
5656         return 0;
5657 }
5658
5659 /**
5660  * igb_clean_tx_irq - Reclaim resources after transmit completes
5661  * @q_vector: pointer to q_vector containing needed info
5662  *
5663  * returns true if ring is completely cleaned
5664  **/
5665 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
5666 {
5667         struct igb_adapter *adapter = q_vector->adapter;
5668         struct igb_ring *tx_ring = q_vector->tx.ring;
5669         struct igb_tx_buffer *tx_buffer;
5670         union e1000_adv_tx_desc *tx_desc;
5671         unsigned int total_bytes = 0, total_packets = 0;
5672         unsigned int budget = q_vector->tx.work_limit;
5673         unsigned int i = tx_ring->next_to_clean;
5674
5675         if (test_bit(__IGB_DOWN, &adapter->state))
5676                 return true;
5677
5678         tx_buffer = &tx_ring->tx_buffer_info[i];
5679         tx_desc = IGB_TX_DESC(tx_ring, i);
5680         i -= tx_ring->count;
5681
5682         do {
5683                 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
5684
5685                 /* if next_to_watch is not set then there is no work pending */
5686                 if (!eop_desc)
5687                         break;
5688
5689                 /* prevent any other reads prior to eop_desc */
5690                 rmb();
5691
5692                 /* if DD is not set pending work has not been completed */
5693                 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5694                         break;
5695
5696                 /* clear next_to_watch to prevent false hangs */
5697                 tx_buffer->next_to_watch = NULL;
5698
5699                 /* update the statistics for this packet */
5700                 total_bytes += tx_buffer->bytecount;
5701                 total_packets += tx_buffer->gso_segs;
5702
5703                 /* free the skb */
5704                 dev_kfree_skb_any(tx_buffer->skb);
5705
5706                 /* unmap skb header data */
5707                 dma_unmap_single(tx_ring->dev,
5708                                  dma_unmap_addr(tx_buffer, dma),
5709                                  dma_unmap_len(tx_buffer, len),
5710                                  DMA_TO_DEVICE);
5711
5712                 /* clear tx_buffer data */
5713                 tx_buffer->skb = NULL;
5714                 dma_unmap_len_set(tx_buffer, len, 0);
5715
5716                 /* clear last DMA location and unmap remaining buffers */
5717                 while (tx_desc != eop_desc) {
5718                         tx_buffer++;
5719                         tx_desc++;
5720                         i++;
5721                         if (unlikely(!i)) {
5722                                 i -= tx_ring->count;
5723                                 tx_buffer = tx_ring->tx_buffer_info;
5724                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
5725                         }
5726
5727                         /* unmap any remaining paged data */
5728                         if (dma_unmap_len(tx_buffer, len)) {
5729                                 dma_unmap_page(tx_ring->dev,
5730                                                dma_unmap_addr(tx_buffer, dma),
5731                                                dma_unmap_len(tx_buffer, len),
5732                                                DMA_TO_DEVICE);
5733                                 dma_unmap_len_set(tx_buffer, len, 0);
5734                         }
5735                 }
5736
5737                 /* move us one more past the eop_desc for start of next pkt */
5738                 tx_buffer++;
5739                 tx_desc++;
5740                 i++;
5741                 if (unlikely(!i)) {
5742                         i -= tx_ring->count;
5743                         tx_buffer = tx_ring->tx_buffer_info;
5744                         tx_desc = IGB_TX_DESC(tx_ring, 0);
5745                 }
5746
5747                 /* issue prefetch for next Tx descriptor */
5748                 prefetch(tx_desc);
5749
5750                 /* update budget accounting */
5751                 budget--;
5752         } while (likely(budget));
5753
5754         netdev_tx_completed_queue(txring_txq(tx_ring),
5755                                   total_packets, total_bytes);
5756         i += tx_ring->count;
5757         tx_ring->next_to_clean = i;
5758         u64_stats_update_begin(&tx_ring->tx_syncp);
5759         tx_ring->tx_stats.bytes += total_bytes;
5760         tx_ring->tx_stats.packets += total_packets;
5761         u64_stats_update_end(&tx_ring->tx_syncp);
5762         q_vector->tx.total_bytes += total_bytes;
5763         q_vector->tx.total_packets += total_packets;
5764
5765         if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
5766                 struct e1000_hw *hw = &adapter->hw;
5767
5768                 /* Detect a transmit hang in hardware, this serializes the
5769                  * check with the clearing of time_stamp and movement of i */
5770                 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5771                 if (tx_buffer->next_to_watch &&
5772                     time_after(jiffies, tx_buffer->time_stamp +
5773                                (adapter->tx_timeout_factor * HZ)) &&
5774                     !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
5775
5776                         /* detected Tx unit hang */
5777                         dev_err(tx_ring->dev,
5778                                 "Detected Tx Unit Hang\n"
5779                                 "  Tx Queue             <%d>\n"
5780                                 "  TDH                  <%x>\n"
5781                                 "  TDT                  <%x>\n"
5782                                 "  next_to_use          <%x>\n"
5783                                 "  next_to_clean        <%x>\n"
5784                                 "buffer_info[next_to_clean]\n"
5785                                 "  time_stamp           <%lx>\n"
5786                                 "  next_to_watch        <%p>\n"
5787                                 "  jiffies              <%lx>\n"
5788                                 "  desc.status          <%x>\n",
5789                                 tx_ring->queue_index,
5790                                 rd32(E1000_TDH(tx_ring->reg_idx)),
5791                                 readl(tx_ring->tail),
5792                                 tx_ring->next_to_use,
5793                                 tx_ring->next_to_clean,
5794                                 tx_buffer->time_stamp,
5795                                 tx_buffer->next_to_watch,
5796                                 jiffies,
5797                                 tx_buffer->next_to_watch->wb.status);
5798                         netif_stop_subqueue(tx_ring->netdev,
5799                                             tx_ring->queue_index);
5800
5801                         /* we are about to reset, no point in enabling stuff */
5802                         return true;
5803                 }
5804         }
5805
5806         if (unlikely(total_packets &&
5807                      netif_carrier_ok(tx_ring->netdev) &&
5808                      igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5809                 /* Make sure that anybody stopping the queue after this
5810                  * sees the new next_to_clean.
5811                  */
5812                 smp_mb();
5813                 if (__netif_subqueue_stopped(tx_ring->netdev,
5814                                              tx_ring->queue_index) &&
5815                     !(test_bit(__IGB_DOWN, &adapter->state))) {
5816                         netif_wake_subqueue(tx_ring->netdev,
5817                                             tx_ring->queue_index);
5818
5819                         u64_stats_update_begin(&tx_ring->tx_syncp);
5820                         tx_ring->tx_stats.restart_queue++;
5821                         u64_stats_update_end(&tx_ring->tx_syncp);
5822                 }
5823         }
5824
5825         return !!budget;
5826 }
5827
5828 /**
5829  * igb_reuse_rx_page - page flip buffer and store it back on the ring
5830  * @rx_ring: rx descriptor ring to store buffers on
5831  * @old_buff: donor buffer to have page reused
5832  *
5833  * Synchronizes page for reuse by the adapter
5834  **/
5835 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
5836                               struct igb_rx_buffer *old_buff)
5837 {
5838         struct igb_rx_buffer *new_buff;
5839         u16 nta = rx_ring->next_to_alloc;
5840
5841         new_buff = &rx_ring->rx_buffer_info[nta];
5842
5843         /* update, and store next to alloc */
5844         nta++;
5845         rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
5846
5847         /* transfer page from old buffer to new buffer */
5848         memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
5849
5850         /* sync the buffer for use by the device */
5851         dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
5852                                          old_buff->page_offset,
5853                                          IGB_RX_BUFSZ,
5854                                          DMA_FROM_DEVICE);
5855 }
5856
5857 /**
5858  * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
5859  * @rx_ring: rx descriptor ring to transact packets on
5860  * @rx_buffer: buffer containing page to add
5861  * @rx_desc: descriptor containing length of buffer written by hardware
5862  * @skb: sk_buff to place the data into
5863  *
5864  * This function will add the data contained in rx_buffer->page to the skb.
5865  * This is done either through a direct copy if the data in the buffer is
5866  * less than the skb header size, otherwise it will just attach the page as
5867  * a frag to the skb.
5868  *
5869  * The function will then update the page offset if necessary and return
5870  * true if the buffer can be reused by the adapter.
5871  **/
5872 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
5873                             struct igb_rx_buffer *rx_buffer,
5874                             union e1000_adv_rx_desc *rx_desc,
5875                             struct sk_buff *skb)
5876 {
5877         struct page *page = rx_buffer->page;
5878         unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
5879
5880         if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
5881                 unsigned char *va = page_address(page) + rx_buffer->page_offset;
5882
5883                 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
5884                         igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
5885                         va += IGB_TS_HDR_LEN;
5886                         size -= IGB_TS_HDR_LEN;
5887                 }
5888
5889                 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
5890
5891                 /* we can reuse buffer as-is, just make sure it is local */
5892                 if (likely(page_to_nid(page) == numa_node_id()))
5893                         return true;
5894
5895                 /* this page cannot be reused so discard it */
5896                 put_page(page);
5897                 return false;
5898         }
5899
5900         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
5901                         rx_buffer->page_offset, size, IGB_RX_BUFSZ);
5902
5903         /* avoid re-using remote pages */
5904         if (unlikely(page_to_nid(page) != numa_node_id()))
5905                 return false;
5906
5907 #if (PAGE_SIZE < 8192)
5908         /* if we are only owner of page we can reuse it */
5909         if (unlikely(page_count(page) != 1))
5910                 return false;
5911
5912         /* flip page offset to other buffer */
5913         rx_buffer->page_offset ^= IGB_RX_BUFSZ;
5914
5915         /*
5916          * since we are the only owner of the page and we need to
5917          * increment it, just set the value to 2 in order to avoid
5918          * an unnecessary locked operation
5919          */
5920         atomic_set(&page->_count, 2);
5921 #else
5922         /* move offset up to the next cache line */
5923         rx_buffer->page_offset += SKB_DATA_ALIGN(size);
5924
5925         if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
5926                 return false;
5927
5928         /* bump ref count on page before it is given to the stack */
5929         get_page(page);
5930 #endif
5931
5932         return true;
5933 }
5934
5935 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
5936                                            union e1000_adv_rx_desc *rx_desc,
5937                                            struct sk_buff *skb)
5938 {
5939         struct igb_rx_buffer *rx_buffer;
5940         struct page *page;
5941
5942         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
5943
5944         /*
5945          * This memory barrier is needed to keep us from reading
5946          * any other fields out of the rx_desc until we know the
5947          * RXD_STAT_DD bit is set
5948          */
5949         rmb();
5950
5951         page = rx_buffer->page;
5952         prefetchw(page);
5953
5954         if (likely(!skb)) {
5955                 void *page_addr = page_address(page) +
5956                                   rx_buffer->page_offset;
5957
5958                 /* prefetch first cache line of first page */
5959                 prefetch(page_addr);
5960 #if L1_CACHE_BYTES < 128
5961                 prefetch(page_addr + L1_CACHE_BYTES);
5962 #endif
5963
5964                 /* allocate a skb to store the frags */
5965                 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
5966                                                 IGB_RX_HDR_LEN);
5967                 if (unlikely(!skb)) {
5968                         rx_ring->rx_stats.alloc_failed++;
5969                         return NULL;
5970                 }
5971
5972                 /*
5973                  * we will be copying header into skb->data in
5974                  * pskb_may_pull so it is in our interest to prefetch
5975                  * it now to avoid a possible cache miss
5976                  */
5977                 prefetchw(skb->data);
5978         }
5979
5980         /* we are reusing so sync this buffer for CPU use */
5981         dma_sync_single_range_for_cpu(rx_ring->dev,
5982                                       rx_buffer->dma,
5983                                       rx_buffer->page_offset,
5984                                       IGB_RX_BUFSZ,
5985                                       DMA_FROM_DEVICE);
5986
5987         /* pull page into skb */
5988         if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
5989                 /* hand second half of page back to the ring */
5990                 igb_reuse_rx_page(rx_ring, rx_buffer);
5991         } else {
5992                 /* we are not reusing the buffer so unmap it */
5993                 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
5994                                PAGE_SIZE, DMA_FROM_DEVICE);
5995         }
5996
5997         /* clear contents of rx_buffer */
5998         rx_buffer->page = NULL;
5999
6000         return skb;
6001 }
6002
6003 static inline void igb_rx_checksum(struct igb_ring *ring,
6004                                    union e1000_adv_rx_desc *rx_desc,
6005                                    struct sk_buff *skb)
6006 {
6007         skb_checksum_none_assert(skb);
6008
6009         /* Ignore Checksum bit is set */
6010         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6011                 return;
6012
6013         /* Rx checksum disabled via ethtool */
6014         if (!(ring->netdev->features & NETIF_F_RXCSUM))
6015                 return;
6016
6017         /* TCP/UDP checksum error bit is set */
6018         if (igb_test_staterr(rx_desc,
6019                              E1000_RXDEXT_STATERR_TCPE |
6020                              E1000_RXDEXT_STATERR_IPE)) {
6021                 /*
6022                  * work around errata with sctp packets where the TCPE aka
6023                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6024                  * packets, (aka let the stack check the crc32c)
6025                  */
6026                 if (!((skb->len == 60) &&
6027                       test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6028                         u64_stats_update_begin(&ring->rx_syncp);
6029                         ring->rx_stats.csum_err++;
6030                         u64_stats_update_end(&ring->rx_syncp);
6031                 }
6032                 /* let the stack verify checksum errors */
6033                 return;
6034         }
6035         /* It must be a TCP or UDP packet with a valid checksum */
6036         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6037                                       E1000_RXD_STAT_UDPCS))
6038                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6039
6040         dev_dbg(ring->dev, "cksum success: bits %08X\n",
6041                 le32_to_cpu(rx_desc->wb.upper.status_error));
6042 }
6043
6044 static inline void igb_rx_hash(struct igb_ring *ring,
6045                                union e1000_adv_rx_desc *rx_desc,
6046                                struct sk_buff *skb)
6047 {
6048         if (ring->netdev->features & NETIF_F_RXHASH)
6049                 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6050 }
6051
6052 /**
6053  * igb_is_non_eop - process handling of non-EOP buffers
6054  * @rx_ring: Rx ring being processed
6055  * @rx_desc: Rx descriptor for current buffer
6056  * @skb: current socket buffer containing buffer in progress
6057  *
6058  * This function updates next to clean.  If the buffer is an EOP buffer
6059  * this function exits returning false, otherwise it will place the
6060  * sk_buff in the next buffer to be chained and return true indicating
6061  * that this is in fact a non-EOP buffer.
6062  **/
6063 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6064                            union e1000_adv_rx_desc *rx_desc)
6065 {
6066         u32 ntc = rx_ring->next_to_clean + 1;
6067
6068         /* fetch, update, and store next to clean */
6069         ntc = (ntc < rx_ring->count) ? ntc : 0;
6070         rx_ring->next_to_clean = ntc;
6071
6072         prefetch(IGB_RX_DESC(rx_ring, ntc));
6073
6074         if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6075                 return false;
6076
6077         return true;
6078 }
6079
6080 /**
6081  * igb_get_headlen - determine size of header for LRO/GRO
6082  * @data: pointer to the start of the headers
6083  * @max_len: total length of section to find headers in
6084  *
6085  * This function is meant to determine the length of headers that will
6086  * be recognized by hardware for LRO, and GRO offloads.  The main
6087  * motivation of doing this is to only perform one pull for IPv4 TCP
6088  * packets so that we can do basic things like calculating the gso_size
6089  * based on the average data per packet.
6090  **/
6091 static unsigned int igb_get_headlen(unsigned char *data,
6092                                     unsigned int max_len)
6093 {
6094         union {
6095                 unsigned char *network;
6096                 /* l2 headers */
6097                 struct ethhdr *eth;
6098                 struct vlan_hdr *vlan;
6099                 /* l3 headers */
6100                 struct iphdr *ipv4;
6101                 struct ipv6hdr *ipv6;
6102         } hdr;
6103         __be16 protocol;
6104         u8 nexthdr = 0; /* default to not TCP */
6105         u8 hlen;
6106
6107         /* this should never happen, but better safe than sorry */
6108         if (max_len < ETH_HLEN)
6109                 return max_len;
6110
6111         /* initialize network frame pointer */
6112         hdr.network = data;
6113
6114         /* set first protocol and move network header forward */
6115         protocol = hdr.eth->h_proto;
6116         hdr.network += ETH_HLEN;
6117
6118         /* handle any vlan tag if present */
6119         if (protocol == __constant_htons(ETH_P_8021Q)) {
6120                 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6121                         return max_len;
6122
6123                 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6124                 hdr.network += VLAN_HLEN;
6125         }
6126
6127         /* handle L3 protocols */
6128         if (protocol == __constant_htons(ETH_P_IP)) {
6129                 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6130                         return max_len;
6131
6132                 /* access ihl as a u8 to avoid unaligned access on ia64 */
6133                 hlen = (hdr.network[0] & 0x0F) << 2;
6134
6135                 /* verify hlen meets minimum size requirements */
6136                 if (hlen < sizeof(struct iphdr))
6137                         return hdr.network - data;
6138
6139                 /* record next protocol */
6140                 nexthdr = hdr.ipv4->protocol;
6141                 hdr.network += hlen;
6142         } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6143                 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6144                         return max_len;
6145
6146                 /* record next protocol */
6147                 nexthdr = hdr.ipv6->nexthdr;
6148                 hdr.network += sizeof(struct ipv6hdr);
6149         } else {
6150                 return hdr.network - data;
6151         }
6152
6153         /* finally sort out TCP */
6154         if (nexthdr == IPPROTO_TCP) {
6155                 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6156                         return max_len;
6157
6158                 /* access doff as a u8 to avoid unaligned access on ia64 */
6159                 hlen = (hdr.network[12] & 0xF0) >> 2;
6160
6161                 /* verify hlen meets minimum size requirements */
6162                 if (hlen < sizeof(struct tcphdr))
6163                         return hdr.network - data;
6164
6165                 hdr.network += hlen;
6166         } else if (nexthdr == IPPROTO_UDP) {
6167                 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6168                         return max_len;
6169
6170                 hdr.network += sizeof(struct udphdr);
6171         }
6172
6173         /*
6174          * If everything has gone correctly hdr.network should be the
6175          * data section of the packet and will be the end of the header.
6176          * If not then it probably represents the end of the last recognized
6177          * header.
6178          */
6179         if ((hdr.network - data) < max_len)
6180                 return hdr.network - data;
6181         else
6182                 return max_len;
6183 }
6184
6185 /**
6186  * igb_pull_tail - igb specific version of skb_pull_tail
6187  * @rx_ring: rx descriptor ring packet is being transacted on
6188  * @rx_desc: pointer to the EOP Rx descriptor
6189  * @skb: pointer to current skb being adjusted
6190  *
6191  * This function is an igb specific version of __pskb_pull_tail.  The
6192  * main difference between this version and the original function is that
6193  * this function can make several assumptions about the state of things
6194  * that allow for significant optimizations versus the standard function.
6195  * As a result we can do things like drop a frag and maintain an accurate
6196  * truesize for the skb.
6197  */
6198 static void igb_pull_tail(struct igb_ring *rx_ring,
6199                           union e1000_adv_rx_desc *rx_desc,
6200                           struct sk_buff *skb)
6201 {
6202         struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6203         unsigned char *va;
6204         unsigned int pull_len;
6205
6206         /*
6207          * it is valid to use page_address instead of kmap since we are
6208          * working with pages allocated out of the lomem pool per
6209          * alloc_page(GFP_ATOMIC)
6210          */
6211         va = skb_frag_address(frag);
6212
6213         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6214                 /* retrieve timestamp from buffer */
6215                 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6216
6217                 /* update pointers to remove timestamp header */
6218                 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6219                 frag->page_offset += IGB_TS_HDR_LEN;
6220                 skb->data_len -= IGB_TS_HDR_LEN;
6221                 skb->len -= IGB_TS_HDR_LEN;
6222
6223                 /* move va to start of packet data */
6224                 va += IGB_TS_HDR_LEN;
6225         }
6226
6227         /*
6228          * we need the header to contain the greater of either ETH_HLEN or
6229          * 60 bytes if the skb->len is less than 60 for skb_pad.
6230          */
6231         pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6232
6233         /* align pull length to size of long to optimize memcpy performance */
6234         skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6235
6236         /* update all of the pointers */
6237         skb_frag_size_sub(frag, pull_len);
6238         frag->page_offset += pull_len;
6239         skb->data_len -= pull_len;
6240         skb->tail += pull_len;
6241 }
6242
6243 /**
6244  * igb_cleanup_headers - Correct corrupted or empty headers
6245  * @rx_ring: rx descriptor ring packet is being transacted on
6246  * @rx_desc: pointer to the EOP Rx descriptor
6247  * @skb: pointer to current skb being fixed
6248  *
6249  * Address the case where we are pulling data in on pages only
6250  * and as such no data is present in the skb header.
6251  *
6252  * In addition if skb is not at least 60 bytes we need to pad it so that
6253  * it is large enough to qualify as a valid Ethernet frame.
6254  *
6255  * Returns true if an error was encountered and skb was freed.
6256  **/
6257 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6258                                 union e1000_adv_rx_desc *rx_desc,
6259                                 struct sk_buff *skb)
6260 {
6261
6262         if (unlikely((igb_test_staterr(rx_desc,
6263                                        E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6264                 struct net_device *netdev = rx_ring->netdev;
6265                 if (!(netdev->features & NETIF_F_RXALL)) {
6266                         dev_kfree_skb_any(skb);
6267                         return true;
6268                 }
6269         }
6270
6271         /* place header in linear portion of buffer */
6272         if (skb_is_nonlinear(skb))
6273                 igb_pull_tail(rx_ring, rx_desc, skb);
6274
6275         /* if skb_pad returns an error the skb was freed */
6276         if (unlikely(skb->len < 60)) {
6277                 int pad_len = 60 - skb->len;
6278
6279                 if (skb_pad(skb, pad_len))
6280                         return true;
6281                 __skb_put(skb, pad_len);
6282         }
6283
6284         return false;
6285 }
6286
6287 /**
6288  * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6289  * @rx_ring: rx descriptor ring packet is being transacted on
6290  * @rx_desc: pointer to the EOP Rx descriptor
6291  * @skb: pointer to current skb being populated
6292  *
6293  * This function checks the ring, descriptor, and packet information in
6294  * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6295  * other fields within the skb.
6296  **/
6297 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6298                                    union e1000_adv_rx_desc *rx_desc,
6299                                    struct sk_buff *skb)
6300 {
6301         struct net_device *dev = rx_ring->netdev;
6302
6303         igb_rx_hash(rx_ring, rx_desc, skb);
6304
6305         igb_rx_checksum(rx_ring, rx_desc, skb);
6306
6307         igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
6308
6309         if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6310             igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6311                 u16 vid;
6312                 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6313                     test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6314                         vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6315                 else
6316                         vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6317
6318                 __vlan_hwaccel_put_tag(skb, vid);
6319         }
6320
6321         skb_record_rx_queue(skb, rx_ring->queue_index);
6322
6323         skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6324 }
6325
6326 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6327 {
6328         struct igb_ring *rx_ring = q_vector->rx.ring;
6329         struct sk_buff *skb = rx_ring->skb;
6330         unsigned int total_bytes = 0, total_packets = 0;
6331         u16 cleaned_count = igb_desc_unused(rx_ring);
6332
6333         do {
6334                 union e1000_adv_rx_desc *rx_desc;
6335
6336                 /* return some buffers to hardware, one at a time is too slow */
6337                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6338                         igb_alloc_rx_buffers(rx_ring, cleaned_count);
6339                         cleaned_count = 0;
6340                 }
6341
6342                 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6343
6344                 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6345                         break;
6346
6347                 /* retrieve a buffer from the ring */
6348                 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6349
6350                 /* exit if we failed to retrieve a buffer */
6351                 if (!skb)
6352                         break;
6353
6354                 cleaned_count++;
6355
6356                 /* fetch next buffer in frame if non-eop */
6357                 if (igb_is_non_eop(rx_ring, rx_desc))
6358                         continue;
6359
6360                 /* verify the packet layout is correct */
6361                 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6362                         skb = NULL;
6363                         continue;
6364                 }
6365
6366                 /* probably a little skewed due to removing CRC */
6367                 total_bytes += skb->len;
6368
6369                 /* populate checksum, timestamp, VLAN, and protocol */
6370                 igb_process_skb_fields(rx_ring, rx_desc, skb);
6371
6372                 napi_gro_receive(&q_vector->napi, skb);
6373
6374                 /* reset skb pointer */
6375                 skb = NULL;
6376
6377                 /* update budget accounting */
6378                 total_packets++;
6379         } while (likely(total_packets < budget));
6380
6381         /* place incomplete frames back on ring for completion */
6382         rx_ring->skb = skb;
6383
6384         u64_stats_update_begin(&rx_ring->rx_syncp);
6385         rx_ring->rx_stats.packets += total_packets;
6386         rx_ring->rx_stats.bytes += total_bytes;
6387         u64_stats_update_end(&rx_ring->rx_syncp);
6388         q_vector->rx.total_packets += total_packets;
6389         q_vector->rx.total_bytes += total_bytes;
6390
6391         if (cleaned_count)
6392                 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6393
6394         return (total_packets < budget);
6395 }
6396
6397 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6398                                   struct igb_rx_buffer *bi)
6399 {
6400         struct page *page = bi->page;
6401         dma_addr_t dma;
6402
6403         /* since we are recycling buffers we should seldom need to alloc */
6404         if (likely(page))
6405                 return true;
6406
6407         /* alloc new page for storage */
6408         page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6409         if (unlikely(!page)) {
6410                 rx_ring->rx_stats.alloc_failed++;
6411                 return false;
6412         }
6413
6414         /* map page for use */
6415         dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6416
6417         /*
6418          * if mapping failed free memory back to system since
6419          * there isn't much point in holding memory we can't use
6420          */
6421         if (dma_mapping_error(rx_ring->dev, dma)) {
6422                 __free_page(page);
6423
6424                 rx_ring->rx_stats.alloc_failed++;
6425                 return false;
6426         }
6427
6428         bi->dma = dma;
6429         bi->page = page;
6430         bi->page_offset = 0;
6431
6432         return true;
6433 }
6434
6435 /**
6436  * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6437  * @adapter: address of board private structure
6438  **/
6439 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6440 {
6441         union e1000_adv_rx_desc *rx_desc;
6442         struct igb_rx_buffer *bi;
6443         u16 i = rx_ring->next_to_use;
6444
6445         /* nothing to do */
6446         if (!cleaned_count)
6447                 return;
6448
6449         rx_desc = IGB_RX_DESC(rx_ring, i);
6450         bi = &rx_ring->rx_buffer_info[i];
6451         i -= rx_ring->count;
6452
6453         do {
6454                 if (!igb_alloc_mapped_page(rx_ring, bi))
6455                         break;
6456
6457                 /*
6458                  * Refresh the desc even if buffer_addrs didn't change
6459                  * because each write-back erases this info.
6460                  */
6461                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
6462
6463                 rx_desc++;
6464                 bi++;
6465                 i++;
6466                 if (unlikely(!i)) {
6467                         rx_desc = IGB_RX_DESC(rx_ring, 0);
6468                         bi = rx_ring->rx_buffer_info;
6469                         i -= rx_ring->count;
6470                 }
6471
6472                 /* clear the hdr_addr for the next_to_use descriptor */
6473                 rx_desc->read.hdr_addr = 0;
6474
6475                 cleaned_count--;
6476         } while (cleaned_count);
6477
6478         i += rx_ring->count;
6479
6480         if (rx_ring->next_to_use != i) {
6481                 /* record the next descriptor to use */
6482                 rx_ring->next_to_use = i;
6483
6484                 /* update next to alloc since we have filled the ring */
6485                 rx_ring->next_to_alloc = i;
6486
6487                 /*
6488                  * Force memory writes to complete before letting h/w
6489                  * know there are new descriptors to fetch.  (Only
6490                  * applicable for weak-ordered memory model archs,
6491                  * such as IA-64).
6492                  */
6493                 wmb();
6494                 writel(i, rx_ring->tail);
6495         }
6496 }
6497
6498 /**
6499  * igb_mii_ioctl -
6500  * @netdev:
6501  * @ifreq:
6502  * @cmd:
6503  **/
6504 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6505 {
6506         struct igb_adapter *adapter = netdev_priv(netdev);
6507         struct mii_ioctl_data *data = if_mii(ifr);
6508
6509         if (adapter->hw.phy.media_type != e1000_media_type_copper)
6510                 return -EOPNOTSUPP;
6511
6512         switch (cmd) {
6513         case SIOCGMIIPHY:
6514                 data->phy_id = adapter->hw.phy.addr;
6515                 break;
6516         case SIOCGMIIREG:
6517                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6518                                      &data->val_out))
6519                         return -EIO;
6520                 break;
6521         case SIOCSMIIREG:
6522         default:
6523                 return -EOPNOTSUPP;
6524         }
6525         return 0;
6526 }
6527
6528 /**
6529  * igb_ioctl -
6530  * @netdev:
6531  * @ifreq:
6532  * @cmd:
6533  **/
6534 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6535 {
6536         switch (cmd) {
6537         case SIOCGMIIPHY:
6538         case SIOCGMIIREG:
6539         case SIOCSMIIREG:
6540                 return igb_mii_ioctl(netdev, ifr, cmd);
6541         case SIOCSHWTSTAMP:
6542                 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
6543         default:
6544                 return -EOPNOTSUPP;
6545         }
6546 }
6547
6548 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6549 {
6550         struct igb_adapter *adapter = hw->back;
6551
6552         if (pcie_capability_read_word(adapter->pdev, reg, value))
6553                 return -E1000_ERR_CONFIG;
6554
6555         return 0;
6556 }
6557
6558 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6559 {
6560         struct igb_adapter *adapter = hw->back;
6561
6562         if (pcie_capability_write_word(adapter->pdev, reg, *value))
6563                 return -E1000_ERR_CONFIG;
6564
6565         return 0;
6566 }
6567
6568 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
6569 {
6570         struct igb_adapter *adapter = netdev_priv(netdev);
6571         struct e1000_hw *hw = &adapter->hw;
6572         u32 ctrl, rctl;
6573         bool enable = !!(features & NETIF_F_HW_VLAN_RX);
6574
6575         if (enable) {
6576                 /* enable VLAN tag insert/strip */
6577                 ctrl = rd32(E1000_CTRL);
6578                 ctrl |= E1000_CTRL_VME;
6579                 wr32(E1000_CTRL, ctrl);
6580
6581                 /* Disable CFI check */
6582                 rctl = rd32(E1000_RCTL);
6583                 rctl &= ~E1000_RCTL_CFIEN;
6584                 wr32(E1000_RCTL, rctl);
6585         } else {
6586                 /* disable VLAN tag insert/strip */
6587                 ctrl = rd32(E1000_CTRL);
6588                 ctrl &= ~E1000_CTRL_VME;
6589                 wr32(E1000_CTRL, ctrl);
6590         }
6591
6592         igb_rlpml_set(adapter);
6593 }
6594
6595 static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
6596 {
6597         struct igb_adapter *adapter = netdev_priv(netdev);
6598         struct e1000_hw *hw = &adapter->hw;
6599         int pf_id = adapter->vfs_allocated_count;
6600
6601         /* attempt to add filter to vlvf array */
6602         igb_vlvf_set(adapter, vid, true, pf_id);
6603
6604         /* add the filter since PF can receive vlans w/o entry in vlvf */
6605         igb_vfta_set(hw, vid, true);
6606
6607         set_bit(vid, adapter->active_vlans);
6608
6609         return 0;
6610 }
6611
6612 static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
6613 {
6614         struct igb_adapter *adapter = netdev_priv(netdev);
6615         struct e1000_hw *hw = &adapter->hw;
6616         int pf_id = adapter->vfs_allocated_count;
6617         s32 err;
6618
6619         /* remove vlan from VLVF table array */
6620         err = igb_vlvf_set(adapter, vid, false, pf_id);
6621
6622         /* if vid was not present in VLVF just remove it from table */
6623         if (err)
6624                 igb_vfta_set(hw, vid, false);
6625
6626         clear_bit(vid, adapter->active_vlans);
6627
6628         return 0;
6629 }
6630
6631 static void igb_restore_vlan(struct igb_adapter *adapter)
6632 {
6633         u16 vid;
6634
6635         igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6636
6637         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6638                 igb_vlan_rx_add_vid(adapter->netdev, vid);
6639 }
6640
6641 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
6642 {
6643         struct pci_dev *pdev = adapter->pdev;
6644         struct e1000_mac_info *mac = &adapter->hw.mac;
6645
6646         mac->autoneg = 0;
6647
6648         /* Make sure dplx is at most 1 bit and lsb of speed is not set
6649          * for the switch() below to work */
6650         if ((spd & 1) || (dplx & ~1))
6651                 goto err_inval;
6652
6653         /* Fiber NIC's only allow 1000 Gbps Full duplex */
6654         if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
6655             spd != SPEED_1000 &&
6656             dplx != DUPLEX_FULL)
6657                 goto err_inval;
6658
6659         switch (spd + dplx) {
6660         case SPEED_10 + DUPLEX_HALF:
6661                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6662                 break;
6663         case SPEED_10 + DUPLEX_FULL:
6664                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6665                 break;
6666         case SPEED_100 + DUPLEX_HALF:
6667                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6668                 break;
6669         case SPEED_100 + DUPLEX_FULL:
6670                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6671                 break;
6672         case SPEED_1000 + DUPLEX_FULL:
6673                 mac->autoneg = 1;
6674                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6675                 break;
6676         case SPEED_1000 + DUPLEX_HALF: /* not supported */
6677         default:
6678                 goto err_inval;
6679         }
6680
6681         /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6682         adapter->hw.phy.mdix = AUTO_ALL_MODES;
6683
6684         return 0;
6685
6686 err_inval:
6687         dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6688         return -EINVAL;
6689 }
6690
6691 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6692                           bool runtime)
6693 {
6694         struct net_device *netdev = pci_get_drvdata(pdev);
6695         struct igb_adapter *adapter = netdev_priv(netdev);
6696         struct e1000_hw *hw = &adapter->hw;
6697         u32 ctrl, rctl, status;
6698         u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6699 #ifdef CONFIG_PM
6700         int retval = 0;
6701 #endif
6702
6703         netif_device_detach(netdev);
6704
6705         if (netif_running(netdev))
6706                 __igb_close(netdev, true);
6707
6708         igb_clear_interrupt_scheme(adapter);
6709
6710 #ifdef CONFIG_PM
6711         retval = pci_save_state(pdev);
6712         if (retval)
6713                 return retval;
6714 #endif
6715
6716         status = rd32(E1000_STATUS);
6717         if (status & E1000_STATUS_LU)
6718                 wufc &= ~E1000_WUFC_LNKC;
6719
6720         if (wufc) {
6721                 igb_setup_rctl(adapter);
6722                 igb_set_rx_mode(netdev);
6723
6724                 /* turn on all-multi mode if wake on multicast is enabled */
6725                 if (wufc & E1000_WUFC_MC) {
6726                         rctl = rd32(E1000_RCTL);
6727                         rctl |= E1000_RCTL_MPE;
6728                         wr32(E1000_RCTL, rctl);
6729                 }
6730
6731                 ctrl = rd32(E1000_CTRL);
6732                 /* advertise wake from D3Cold */
6733                 #define E1000_CTRL_ADVD3WUC 0x00100000
6734                 /* phy power management enable */
6735                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6736                 ctrl |= E1000_CTRL_ADVD3WUC;
6737                 wr32(E1000_CTRL, ctrl);
6738
6739                 /* Allow time for pending master requests to run */
6740                 igb_disable_pcie_master(hw);
6741
6742                 wr32(E1000_WUC, E1000_WUC_PME_EN);
6743                 wr32(E1000_WUFC, wufc);
6744         } else {
6745                 wr32(E1000_WUC, 0);
6746                 wr32(E1000_WUFC, 0);
6747         }
6748
6749         *enable_wake = wufc || adapter->en_mng_pt;
6750         if (!*enable_wake)
6751                 igb_power_down_link(adapter);
6752         else
6753                 igb_power_up_link(adapter);
6754
6755         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
6756          * would have already happened in close and is redundant. */
6757         igb_release_hw_control(adapter);
6758
6759         pci_disable_device(pdev);
6760
6761         return 0;
6762 }
6763
6764 #ifdef CONFIG_PM
6765 #ifdef CONFIG_PM_SLEEP
6766 static int igb_suspend(struct device *dev)
6767 {
6768         int retval;
6769         bool wake;
6770         struct pci_dev *pdev = to_pci_dev(dev);
6771
6772         retval = __igb_shutdown(pdev, &wake, 0);
6773         if (retval)
6774                 return retval;
6775
6776         if (wake) {
6777                 pci_prepare_to_sleep(pdev);
6778         } else {
6779                 pci_wake_from_d3(pdev, false);
6780                 pci_set_power_state(pdev, PCI_D3hot);
6781         }
6782
6783         return 0;
6784 }
6785 #endif /* CONFIG_PM_SLEEP */
6786
6787 static int igb_resume(struct device *dev)
6788 {
6789         struct pci_dev *pdev = to_pci_dev(dev);
6790         struct net_device *netdev = pci_get_drvdata(pdev);
6791         struct igb_adapter *adapter = netdev_priv(netdev);
6792         struct e1000_hw *hw = &adapter->hw;
6793         u32 err;
6794
6795         pci_set_power_state(pdev, PCI_D0);
6796         pci_restore_state(pdev);
6797         pci_save_state(pdev);
6798
6799         err = pci_enable_device_mem(pdev);
6800         if (err) {
6801                 dev_err(&pdev->dev,
6802                         "igb: Cannot enable PCI device from suspend\n");
6803                 return err;
6804         }
6805         pci_set_master(pdev);
6806
6807         pci_enable_wake(pdev, PCI_D3hot, 0);
6808         pci_enable_wake(pdev, PCI_D3cold, 0);
6809
6810         if (igb_init_interrupt_scheme(adapter)) {
6811                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6812                 return -ENOMEM;
6813         }
6814
6815         igb_reset(adapter);
6816
6817         /* let the f/w know that the h/w is now under the control of the
6818          * driver. */
6819         igb_get_hw_control(adapter);
6820
6821         wr32(E1000_WUS, ~0);
6822
6823         if (netdev->flags & IFF_UP) {
6824                 rtnl_lock();
6825                 err = __igb_open(netdev, true);
6826                 rtnl_unlock();
6827                 if (err)
6828                         return err;
6829         }
6830
6831         netif_device_attach(netdev);
6832         return 0;
6833 }
6834
6835 #ifdef CONFIG_PM_RUNTIME
6836 static int igb_runtime_idle(struct device *dev)
6837 {
6838         struct pci_dev *pdev = to_pci_dev(dev);
6839         struct net_device *netdev = pci_get_drvdata(pdev);
6840         struct igb_adapter *adapter = netdev_priv(netdev);
6841
6842         if (!igb_has_link(adapter))
6843                 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
6844
6845         return -EBUSY;
6846 }
6847
6848 static int igb_runtime_suspend(struct device *dev)
6849 {
6850         struct pci_dev *pdev = to_pci_dev(dev);
6851         int retval;
6852         bool wake;
6853
6854         retval = __igb_shutdown(pdev, &wake, 1);
6855         if (retval)
6856                 return retval;
6857
6858         if (wake) {
6859                 pci_prepare_to_sleep(pdev);
6860         } else {
6861                 pci_wake_from_d3(pdev, false);
6862                 pci_set_power_state(pdev, PCI_D3hot);
6863         }
6864
6865         return 0;
6866 }
6867
6868 static int igb_runtime_resume(struct device *dev)
6869 {
6870         return igb_resume(dev);
6871 }
6872 #endif /* CONFIG_PM_RUNTIME */
6873 #endif
6874
6875 static void igb_shutdown(struct pci_dev *pdev)
6876 {
6877         bool wake;
6878
6879         __igb_shutdown(pdev, &wake, 0);
6880
6881         if (system_state == SYSTEM_POWER_OFF) {
6882                 pci_wake_from_d3(pdev, wake);
6883                 pci_set_power_state(pdev, PCI_D3hot);
6884         }
6885 }
6886
6887 #ifdef CONFIG_NET_POLL_CONTROLLER
6888 /*
6889  * Polling 'interrupt' - used by things like netconsole to send skbs
6890  * without having to re-enable interrupts. It's not called while
6891  * the interrupt routine is executing.
6892  */
6893 static void igb_netpoll(struct net_device *netdev)
6894 {
6895         struct igb_adapter *adapter = netdev_priv(netdev);
6896         struct e1000_hw *hw = &adapter->hw;
6897         struct igb_q_vector *q_vector;
6898         int i;
6899
6900         for (i = 0; i < adapter->num_q_vectors; i++) {
6901                 q_vector = adapter->q_vector[i];
6902                 if (adapter->msix_entries)
6903                         wr32(E1000_EIMC, q_vector->eims_value);
6904                 else
6905                         igb_irq_disable(adapter);
6906                 napi_schedule(&q_vector->napi);
6907         }
6908 }
6909 #endif /* CONFIG_NET_POLL_CONTROLLER */
6910
6911 /**
6912  * igb_io_error_detected - called when PCI error is detected
6913  * @pdev: Pointer to PCI device
6914  * @state: The current pci connection state
6915  *
6916  * This function is called after a PCI bus error affecting
6917  * this device has been detected.
6918  */
6919 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6920                                               pci_channel_state_t state)
6921 {
6922         struct net_device *netdev = pci_get_drvdata(pdev);
6923         struct igb_adapter *adapter = netdev_priv(netdev);
6924
6925         netif_device_detach(netdev);
6926
6927         if (state == pci_channel_io_perm_failure)
6928                 return PCI_ERS_RESULT_DISCONNECT;
6929
6930         if (netif_running(netdev))
6931                 igb_down(adapter);
6932         pci_disable_device(pdev);
6933
6934         /* Request a slot slot reset. */
6935         return PCI_ERS_RESULT_NEED_RESET;
6936 }
6937
6938 /**
6939  * igb_io_slot_reset - called after the pci bus has been reset.
6940  * @pdev: Pointer to PCI device
6941  *
6942  * Restart the card from scratch, as if from a cold-boot. Implementation
6943  * resembles the first-half of the igb_resume routine.
6944  */
6945 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6946 {
6947         struct net_device *netdev = pci_get_drvdata(pdev);
6948         struct igb_adapter *adapter = netdev_priv(netdev);
6949         struct e1000_hw *hw = &adapter->hw;
6950         pci_ers_result_t result;
6951         int err;
6952
6953         if (pci_enable_device_mem(pdev)) {
6954                 dev_err(&pdev->dev,
6955                         "Cannot re-enable PCI device after reset.\n");
6956                 result = PCI_ERS_RESULT_DISCONNECT;
6957         } else {
6958                 pci_set_master(pdev);
6959                 pci_restore_state(pdev);
6960                 pci_save_state(pdev);
6961
6962                 pci_enable_wake(pdev, PCI_D3hot, 0);
6963                 pci_enable_wake(pdev, PCI_D3cold, 0);
6964
6965                 igb_reset(adapter);
6966                 wr32(E1000_WUS, ~0);
6967                 result = PCI_ERS_RESULT_RECOVERED;
6968         }
6969
6970         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6971         if (err) {
6972                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6973                         "failed 0x%0x\n", err);
6974                 /* non-fatal, continue */
6975         }
6976
6977         return result;
6978 }
6979
6980 /**
6981  * igb_io_resume - called when traffic can start flowing again.
6982  * @pdev: Pointer to PCI device
6983  *
6984  * This callback is called when the error recovery driver tells us that
6985  * its OK to resume normal operation. Implementation resembles the
6986  * second-half of the igb_resume routine.
6987  */
6988 static void igb_io_resume(struct pci_dev *pdev)
6989 {
6990         struct net_device *netdev = pci_get_drvdata(pdev);
6991         struct igb_adapter *adapter = netdev_priv(netdev);
6992
6993         if (netif_running(netdev)) {
6994                 if (igb_up(adapter)) {
6995                         dev_err(&pdev->dev, "igb_up failed after reset\n");
6996                         return;
6997                 }
6998         }
6999
7000         netif_device_attach(netdev);
7001
7002         /* let the f/w know that the h/w is now under the control of the
7003          * driver. */
7004         igb_get_hw_control(adapter);
7005 }
7006
7007 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7008                              u8 qsel)
7009 {
7010         u32 rar_low, rar_high;
7011         struct e1000_hw *hw = &adapter->hw;
7012
7013         /* HW expects these in little endian so we reverse the byte order
7014          * from network order (big endian) to little endian
7015          */
7016         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7017                   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7018         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7019
7020         /* Indicate to hardware the Address is Valid. */
7021         rar_high |= E1000_RAH_AV;
7022
7023         if (hw->mac.type == e1000_82575)
7024                 rar_high |= E1000_RAH_POOL_1 * qsel;
7025         else
7026                 rar_high |= E1000_RAH_POOL_1 << qsel;
7027
7028         wr32(E1000_RAL(index), rar_low);
7029         wrfl();
7030         wr32(E1000_RAH(index), rar_high);
7031         wrfl();
7032 }
7033
7034 static int igb_set_vf_mac(struct igb_adapter *adapter,
7035                           int vf, unsigned char *mac_addr)
7036 {
7037         struct e1000_hw *hw = &adapter->hw;
7038         /* VF MAC addresses start at end of receive addresses and moves
7039          * torwards the first, as a result a collision should not be possible */
7040         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7041
7042         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7043
7044         igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7045
7046         return 0;
7047 }
7048
7049 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7050 {
7051         struct igb_adapter *adapter = netdev_priv(netdev);
7052         if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7053                 return -EINVAL;
7054         adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7055         dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7056         dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7057                                       " change effective.");
7058         if (test_bit(__IGB_DOWN, &adapter->state)) {
7059                 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7060                          " but the PF device is not up.\n");
7061                 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7062                          " attempting to use the VF device.\n");
7063         }
7064         return igb_set_vf_mac(adapter, vf, mac);
7065 }
7066
7067 static int igb_link_mbps(int internal_link_speed)
7068 {
7069         switch (internal_link_speed) {
7070         case SPEED_100:
7071                 return 100;
7072         case SPEED_1000:
7073                 return 1000;
7074         default:
7075                 return 0;
7076         }
7077 }
7078
7079 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7080                                   int link_speed)
7081 {
7082         int rf_dec, rf_int;
7083         u32 bcnrc_val;
7084
7085         if (tx_rate != 0) {
7086                 /* Calculate the rate factor values to set */
7087                 rf_int = link_speed / tx_rate;
7088                 rf_dec = (link_speed - (rf_int * tx_rate));
7089                 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7090
7091                 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7092                 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7093                                E1000_RTTBCNRC_RF_INT_MASK);
7094                 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7095         } else {
7096                 bcnrc_val = 0;
7097         }
7098
7099         wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7100         /*
7101          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7102          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7103          */
7104         wr32(E1000_RTTBCNRM, 0x14);
7105         wr32(E1000_RTTBCNRC, bcnrc_val);
7106 }
7107
7108 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7109 {
7110         int actual_link_speed, i;
7111         bool reset_rate = false;
7112
7113         /* VF TX rate limit was not set or not supported */
7114         if ((adapter->vf_rate_link_speed == 0) ||
7115             (adapter->hw.mac.type != e1000_82576))
7116                 return;
7117
7118         actual_link_speed = igb_link_mbps(adapter->link_speed);
7119         if (actual_link_speed != adapter->vf_rate_link_speed) {
7120                 reset_rate = true;
7121                 adapter->vf_rate_link_speed = 0;
7122                 dev_info(&adapter->pdev->dev,
7123                          "Link speed has been changed. VF Transmit "
7124                          "rate is disabled\n");
7125         }
7126
7127         for (i = 0; i < adapter->vfs_allocated_count; i++) {
7128                 if (reset_rate)
7129                         adapter->vf_data[i].tx_rate = 0;
7130
7131                 igb_set_vf_rate_limit(&adapter->hw, i,
7132                                       adapter->vf_data[i].tx_rate,
7133                                       actual_link_speed);
7134         }
7135 }
7136
7137 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7138 {
7139         struct igb_adapter *adapter = netdev_priv(netdev);
7140         struct e1000_hw *hw = &adapter->hw;
7141         int actual_link_speed;
7142
7143         if (hw->mac.type != e1000_82576)
7144                 return -EOPNOTSUPP;
7145
7146         actual_link_speed = igb_link_mbps(adapter->link_speed);
7147         if ((vf >= adapter->vfs_allocated_count) ||
7148             (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7149             (tx_rate < 0) || (tx_rate > actual_link_speed))
7150                 return -EINVAL;
7151
7152         adapter->vf_rate_link_speed = actual_link_speed;
7153         adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7154         igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7155
7156         return 0;
7157 }
7158
7159 static int igb_ndo_get_vf_config(struct net_device *netdev,
7160                                  int vf, struct ifla_vf_info *ivi)
7161 {
7162         struct igb_adapter *adapter = netdev_priv(netdev);
7163         if (vf >= adapter->vfs_allocated_count)
7164                 return -EINVAL;
7165         ivi->vf = vf;
7166         memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7167         ivi->tx_rate = adapter->vf_data[vf].tx_rate;
7168         ivi->vlan = adapter->vf_data[vf].pf_vlan;
7169         ivi->qos = adapter->vf_data[vf].pf_qos;
7170         return 0;
7171 }
7172
7173 static void igb_vmm_control(struct igb_adapter *adapter)
7174 {
7175         struct e1000_hw *hw = &adapter->hw;
7176         u32 reg;
7177
7178         switch (hw->mac.type) {
7179         case e1000_82575:
7180         case e1000_i210:
7181         case e1000_i211:
7182         default:
7183                 /* replication is not supported for 82575 */
7184                 return;
7185         case e1000_82576:
7186                 /* notify HW that the MAC is adding vlan tags */
7187                 reg = rd32(E1000_DTXCTL);
7188                 reg |= E1000_DTXCTL_VLAN_ADDED;
7189                 wr32(E1000_DTXCTL, reg);
7190         case e1000_82580:
7191                 /* enable replication vlan tag stripping */
7192                 reg = rd32(E1000_RPLOLR);
7193                 reg |= E1000_RPLOLR_STRVLAN;
7194                 wr32(E1000_RPLOLR, reg);
7195         case e1000_i350:
7196                 /* none of the above registers are supported by i350 */
7197                 break;
7198         }
7199
7200         if (adapter->vfs_allocated_count) {
7201                 igb_vmdq_set_loopback_pf(hw, true);
7202                 igb_vmdq_set_replication_pf(hw, true);
7203                 igb_vmdq_set_anti_spoofing_pf(hw, true,
7204                                                 adapter->vfs_allocated_count);
7205         } else {
7206                 igb_vmdq_set_loopback_pf(hw, false);
7207                 igb_vmdq_set_replication_pf(hw, false);
7208         }
7209 }
7210
7211 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7212 {
7213         struct e1000_hw *hw = &adapter->hw;
7214         u32 dmac_thr;
7215         u16 hwm;
7216
7217         if (hw->mac.type > e1000_82580) {
7218                 if (adapter->flags & IGB_FLAG_DMAC) {
7219                         u32 reg;
7220
7221                         /* force threshold to 0. */
7222                         wr32(E1000_DMCTXTH, 0);
7223
7224                         /*
7225                          * DMA Coalescing high water mark needs to be greater
7226                          * than the Rx threshold. Set hwm to PBA - max frame
7227                          * size in 16B units, capping it at PBA - 6KB.
7228                          */
7229                         hwm = 64 * pba - adapter->max_frame_size / 16;
7230                         if (hwm < 64 * (pba - 6))
7231                                 hwm = 64 * (pba - 6);
7232                         reg = rd32(E1000_FCRTC);
7233                         reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7234                         reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7235                                 & E1000_FCRTC_RTH_COAL_MASK);
7236                         wr32(E1000_FCRTC, reg);
7237
7238                         /*
7239                          * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7240                          * frame size, capping it at PBA - 10KB.
7241                          */
7242                         dmac_thr = pba - adapter->max_frame_size / 512;
7243                         if (dmac_thr < pba - 10)
7244                                 dmac_thr = pba - 10;
7245                         reg = rd32(E1000_DMACR);
7246                         reg &= ~E1000_DMACR_DMACTHR_MASK;
7247                         reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7248                                 & E1000_DMACR_DMACTHR_MASK);
7249
7250                         /* transition to L0x or L1 if available..*/
7251                         reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7252
7253                         /* watchdog timer= +-1000 usec in 32usec intervals */
7254                         reg |= (1000 >> 5);
7255
7256                         /* Disable BMC-to-OS Watchdog Enable */
7257                         reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7258                         wr32(E1000_DMACR, reg);
7259
7260                         /*
7261                          * no lower threshold to disable
7262                          * coalescing(smart fifb)-UTRESH=0
7263                          */
7264                         wr32(E1000_DMCRTRH, 0);
7265
7266                         reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7267
7268                         wr32(E1000_DMCTLX, reg);
7269
7270                         /*
7271                          * free space in tx packet buffer to wake from
7272                          * DMA coal
7273                          */
7274                         wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7275                              (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7276
7277                         /*
7278                          * make low power state decision controlled
7279                          * by DMA coal
7280                          */
7281                         reg = rd32(E1000_PCIEMISC);
7282                         reg &= ~E1000_PCIEMISC_LX_DECISION;
7283                         wr32(E1000_PCIEMISC, reg);
7284                 } /* endif adapter->dmac is not disabled */
7285         } else if (hw->mac.type == e1000_82580) {
7286                 u32 reg = rd32(E1000_PCIEMISC);
7287                 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7288                 wr32(E1000_DMACR, 0);
7289         }
7290 }
7291
7292 /* igb_main.c */