Pileus Git - ~andy/linux/blob - drivers/net/ethernet/intel/i40e/i40e_type.h

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * The full GNU General Public License is included in this distribution in
  20  * the file called "COPYING".
  21  *
  22  * Contact Information:
  23  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25  *
  26  ******************************************************************************/
  27
  28 #ifndef _I40E_TYPE_H_
  29 #define _I40E_TYPE_H_
  30
  31 #include "i40e_status.h"
  32 #include "i40e_osdep.h"
  33 #include "i40e_register.h"
  34 #include "i40e_adminq.h"
  35 #include "i40e_hmc.h"
  36 #include "i40e_lan_hmc.h"
  37
  38 /* Device IDs */
  39 #define I40E_SFP_XL710_DEVICE_ID        0x1572
  40 #define I40E_SFP_X710_DEVICE_ID         0x1573
  41 #define I40E_QEMU_DEVICE_ID             0x1574
  42 #define I40E_KX_A_DEVICE_ID             0x157F
  43 #define I40E_KX_B_DEVICE_ID             0x1580
  44 #define I40E_KX_C_DEVICE_ID             0x1581
  45 #define I40E_KX_D_DEVICE_ID             0x1582
  46 #define I40E_QSFP_A_DEVICE_ID           0x1583
  47 #define I40E_QSFP_B_DEVICE_ID           0x1584
  48 #define I40E_QSFP_C_DEVICE_ID           0x1585
  49 #define I40E_VF_DEVICE_ID               0x154C
  50 #define I40E_VF_HV_DEVICE_ID            0x1571
  51
  52 #define i40e_is_40G_device(d)           ((d) == I40E_QSFP_A_DEVICE_ID  || \
  53                                          (d) == I40E_QSFP_B_DEVICE_ID  || \
  54                                          (d) == I40E_QSFP_C_DEVICE_ID)
  55
  56 #define I40E_FW_API_VERSION_MAJOR  0x0001
  57 #define I40E_FW_API_VERSION_MINOR  0x0000
  58
  59 #define I40E_MAX_VSI_QP                 16
  60 #define I40E_MAX_VF_VSI                 3
  61 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  62 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  63
  64 /* Max default timeout in ms, */
  65 #define I40E_MAX_NVM_TIMEOUT            18000
  66
  67 /* Check whether address is multicast.  This is little-endian specific check.*/
  68 #define I40E_IS_MULTICAST(address)      \
  69         (bool)(((u8 *)(address))[0] & ((u8)0x01))
  70
  71 /* Check whether an address is broadcast. */
  72 #define I40E_IS_BROADCAST(address)      \
  73         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  74         (((u8 *)(address))[1] == ((u8)0xff)))
  75
  76 /* Switch from mc to the 2usec global time (this is the GTIME resolution) */
  77 #define I40E_MS_TO_GTIME(time)          (((time) * 1000) / 2)
  78
  79 /* forward declaration */
  80 struct i40e_hw;
  81 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  82
  83 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  84
  85 /* Data type manipulation macros. */
  86
  87 #define I40E_DESC_UNUSED(R)     \
  88         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  89         (R)->next_to_clean - (R)->next_to_use - 1)
  90
  91 /* bitfields for Tx queue mapping in QTX_CTL */
  92 #define I40E_QTX_CTL_VF_QUEUE   0x0
  93 #define I40E_QTX_CTL_PF_QUEUE   0x2
  94
  95 /* debug masks */
  96 enum i40e_debug_mask {
  97         I40E_DEBUG_INIT                 = 0x00000001,
  98         I40E_DEBUG_RELEASE              = 0x00000002,
  99
 100         I40E_DEBUG_LINK                 = 0x00000010,
 101         I40E_DEBUG_PHY                  = 0x00000020,
 102         I40E_DEBUG_HMC                  = 0x00000040,
 103         I40E_DEBUG_NVM                  = 0x00000080,
 104         I40E_DEBUG_LAN                  = 0x00000100,
 105         I40E_DEBUG_FLOW                 = 0x00000200,
 106         I40E_DEBUG_DCB                  = 0x00000400,
 107         I40E_DEBUG_DIAG                 = 0x00000800,
 108
 109         I40E_DEBUG_AQ_MESSAGE           = 0x01000000, /* for i40e_debug() */
 110         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 111         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 112         I40E_DEBUG_AQ_COMMAND           = 0x06000000, /* for i40e_debug_aq() */
 113         I40E_DEBUG_AQ                   = 0x0F000000,
 114
 115         I40E_DEBUG_USER                 = 0xF0000000,
 116
 117         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 118 };
 119
 120 /* These are structs for managing the hardware information and the operations.
 121  * The structures of function pointers are filled out at init time when we
 122  * know for sure exactly which hardware we're working with.  This gives us the
 123  * flexibility of using the same main driver code but adapting to slightly
 124  * different hardware needs as new parts are developed.  For this architecture,
 125  * the Firmware and AdminQ are intended to insulate the driver from most of the
 126  * future changes, but these structures will also do part of the job.
 127  */
 128 enum i40e_mac_type {
 129         I40E_MAC_UNKNOWN = 0,
 130         I40E_MAC_X710,
 131         I40E_MAC_XL710,
 132         I40E_MAC_VF,
 133         I40E_MAC_GENERIC,
 134 };
 135
 136 enum i40e_media_type {
 137         I40E_MEDIA_TYPE_UNKNOWN = 0,
 138         I40E_MEDIA_TYPE_FIBER,
 139         I40E_MEDIA_TYPE_BASET,
 140         I40E_MEDIA_TYPE_BACKPLANE,
 141         I40E_MEDIA_TYPE_CX4,
 142         I40E_MEDIA_TYPE_DA,
 143         I40E_MEDIA_TYPE_VIRTUAL
 144 };
 145
 146 enum i40e_fc_mode {
 147         I40E_FC_NONE = 0,
 148         I40E_FC_RX_PAUSE,
 149         I40E_FC_TX_PAUSE,
 150         I40E_FC_FULL,
 151         I40E_FC_PFC,
 152         I40E_FC_DEFAULT
 153 };
 154
 155 enum i40e_vsi_type {
 156         I40E_VSI_MAIN = 0,
 157         I40E_VSI_VMDQ1,
 158         I40E_VSI_VMDQ2,
 159         I40E_VSI_CTRL,
 160         I40E_VSI_FCOE,
 161         I40E_VSI_MIRROR,
 162         I40E_VSI_SRIOV,
 163         I40E_VSI_FDIR,
 164         I40E_VSI_TYPE_UNKNOWN
 165 };
 166
 167 enum i40e_queue_type {
 168         I40E_QUEUE_TYPE_RX = 0,
 169         I40E_QUEUE_TYPE_TX,
 170         I40E_QUEUE_TYPE_PE_CEQ,
 171         I40E_QUEUE_TYPE_UNKNOWN
 172 };
 173
 174 struct i40e_link_status {
 175         enum i40e_aq_phy_type phy_type;
 176         enum i40e_aq_link_speed link_speed;
 177         u8 link_info;
 178         u8 an_info;
 179         u8 ext_info;
 180         u8 loopback;
 181         /* is Link Status Event notification to SW enabled */
 182         bool lse_enable;
 183 };
 184
 185 struct i40e_phy_info {
 186         struct i40e_link_status link_info;
 187         struct i40e_link_status link_info_old;
 188         u32 autoneg_advertised;
 189         u32 phy_id;
 190         u32 module_type;
 191         bool get_link_info;
 192         enum i40e_media_type media_type;
 193 };
 194
 195 #define I40E_HW_CAP_MAX_GPIO                    30
 196 /* Capabilities of a PF or a VF or the whole device */
 197 struct i40e_hw_capabilities {
 198         u32  switch_mode;
 199 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 200 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 201 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 202
 203         u32  management_mode;
 204         u32  npar_enable;
 205         u32  os2bmc;
 206         u32  valid_functions;
 207         bool sr_iov_1_1;
 208         bool vmdq;
 209         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 210         bool evb_802_1_qbh; /* Bridge Port Extension */
 211         bool dcb;
 212         bool fcoe;
 213         bool mfp_mode_1;
 214         bool mgmt_cem;
 215         bool ieee_1588;
 216         bool iwarp;
 217         bool fd;
 218         u32 fd_filters_guaranteed;
 219         u32 fd_filters_best_effort;
 220         bool rss;
 221         u32 rss_table_size;
 222         u32 rss_table_entry_width;
 223         bool led[I40E_HW_CAP_MAX_GPIO];
 224         bool sdp[I40E_HW_CAP_MAX_GPIO];
 225         u32 nvm_image_type;
 226         u32 num_flow_director_filters;
 227         u32 num_vfs;
 228         u32 vf_base_id;
 229         u32 num_vsis;
 230         u32 num_rx_qp;
 231         u32 num_tx_qp;
 232         u32 base_queue;
 233         u32 num_msix_vectors;
 234         u32 num_msix_vectors_vf;
 235         u32 led_pin_num;
 236         u32 sdp_pin_num;
 237         u32 mdio_port_num;
 238         u32 mdio_port_mode;
 239         u8 rx_buf_chain_len;
 240         u32 enabled_tcmap;
 241         u32 maxtc;
 242 };
 243
 244 struct i40e_mac_info {
 245         enum i40e_mac_type type;
 246         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 247         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 248         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 249         u16 max_fcoeq;
 250 };
 251
 252 enum i40e_aq_resources_ids {
 253         I40E_NVM_RESOURCE_ID = 1
 254 };
 255
 256 enum i40e_aq_resource_access_type {
 257         I40E_RESOURCE_READ = 1,
 258         I40E_RESOURCE_WRITE
 259 };
 260
 261 struct i40e_nvm_info {
 262         u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
 263         u64 hw_semaphore_wait;    /* - || - */
 264         u32 timeout;              /* [ms] */
 265         u16 sr_size;              /* Shadow RAM size in words */
 266         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 267         u16 version;              /* NVM package version */
 268         u32 eetrack;              /* NVM data version */
 269 };
 270
 271 /* PCI bus types */
 272 enum i40e_bus_type {
 273         i40e_bus_type_unknown = 0,
 274         i40e_bus_type_pci,
 275         i40e_bus_type_pcix,
 276         i40e_bus_type_pci_express,
 277         i40e_bus_type_reserved
 278 };
 279
 280 /* PCI bus speeds */
 281 enum i40e_bus_speed {
 282         i40e_bus_speed_unknown  = 0,
 283         i40e_bus_speed_33       = 33,
 284         i40e_bus_speed_66       = 66,
 285         i40e_bus_speed_100      = 100,
 286         i40e_bus_speed_120      = 120,
 287         i40e_bus_speed_133      = 133,
 288         i40e_bus_speed_2500     = 2500,
 289         i40e_bus_speed_5000     = 5000,
 290         i40e_bus_speed_8000     = 8000,
 291         i40e_bus_speed_reserved
 292 };
 293
 294 /* PCI bus widths */
 295 enum i40e_bus_width {
 296         i40e_bus_width_unknown  = 0,
 297         i40e_bus_width_pcie_x1  = 1,
 298         i40e_bus_width_pcie_x2  = 2,
 299         i40e_bus_width_pcie_x4  = 4,
 300         i40e_bus_width_pcie_x8  = 8,
 301         i40e_bus_width_32       = 32,
 302         i40e_bus_width_64       = 64,
 303         i40e_bus_width_reserved
 304 };
 305
 306 /* Bus parameters */
 307 struct i40e_bus_info {
 308         enum i40e_bus_speed speed;
 309         enum i40e_bus_width width;
 310         enum i40e_bus_type type;
 311
 312         u16 func;
 313         u16 device;
 314         u16 lan_id;
 315 };
 316
 317 /* Flow control (FC) parameters */
 318 struct i40e_fc_info {
 319         enum i40e_fc_mode current_mode; /* FC mode in effect */
 320         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 321 };
 322
 323 #define I40E_MAX_TRAFFIC_CLASS          8
 324 #define I40E_MAX_USER_PRIORITY          8
 325 #define I40E_DCBX_MAX_APPS              32
 326 #define I40E_LLDPDU_SIZE                1500
 327
 328 /* IEEE 802.1Qaz ETS Configuration data */
 329 struct i40e_ieee_ets_config {
 330         u8 willing;
 331         u8 cbs;
 332         u8 maxtcs;
 333         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 334         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 335         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 336 };
 337
 338 /* IEEE 802.1Qaz ETS Recommendation data */
 339 struct i40e_ieee_ets_recommend {
 340         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 341         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 342         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 343 };
 344
 345 /* IEEE 802.1Qaz PFC Configuration data */
 346 struct i40e_ieee_pfc_config {
 347         u8 willing;
 348         u8 mbc;
 349         u8 pfccap;
 350         u8 pfcenable;
 351 };
 352
 353 /* IEEE 802.1Qaz Application Priority data */
 354 struct i40e_ieee_app_priority_table {
 355         u8  priority;
 356         u8  selector;
 357         u16 protocolid;
 358 };
 359
 360 struct i40e_dcbx_config {
 361         u32 numapps;
 362         struct i40e_ieee_ets_config etscfg;
 363         struct i40e_ieee_ets_recommend etsrec;
 364         struct i40e_ieee_pfc_config pfc;
 365         struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
 366 };
 367
 368 /* Port hardware description */
 369 struct i40e_hw {
 370         u8 __iomem *hw_addr;
 371         void *back;
 372
 373         /* function pointer structs */
 374         struct i40e_phy_info phy;
 375         struct i40e_mac_info mac;
 376         struct i40e_bus_info bus;
 377         struct i40e_nvm_info nvm;
 378         struct i40e_fc_info fc;
 379
 380         /* pci info */
 381         u16 device_id;
 382         u16 vendor_id;
 383         u16 subsystem_device_id;
 384         u16 subsystem_vendor_id;
 385         u8 revision_id;
 386         u8 port;
 387         bool adapter_stopped;
 388
 389         /* capabilities for entire device and PCI func */
 390         struct i40e_hw_capabilities dev_caps;
 391         struct i40e_hw_capabilities func_caps;
 392
 393         /* Flow Director shared filter space */
 394         u16 fdir_shared_filter_count;
 395
 396         /* device profile info */
 397         u8  pf_id;
 398         u16 main_vsi_seid;
 399
 400         /* Closest numa node to the device */
 401         u16 numa_node;
 402
 403         /* Admin Queue info */
 404         struct i40e_adminq_info aq;
 405
 406         /* HMC info */
 407         struct i40e_hmc_info hmc; /* HMC info struct */
 408
 409         /* LLDP/DCBX Status */
 410         u16 dcbx_status;
 411
 412         /* DCBX info */
 413         struct i40e_dcbx_config local_dcbx_config;
 414         struct i40e_dcbx_config remote_dcbx_config;
 415
 416         /* debug mask */
 417         u32 debug_mask;
 418 };
 419
 420 struct i40e_driver_version {
 421         u8 major_version;
 422         u8 minor_version;
 423         u8 build_version;
 424         u8 subbuild_version;
 425 };
 426
 427 /* RX Descriptors */
 428 union i40e_16byte_rx_desc {
 429         struct {
 430                 __le64 pkt_addr; /* Packet buffer address */
 431                 __le64 hdr_addr; /* Header buffer address */
 432         } read;
 433         struct {
 434                 struct {
 435                         struct {
 436                                 union {
 437                                         __le16 mirroring_status;
 438                                         __le16 fcoe_ctx_id;
 439                                 } mirr_fcoe;
 440                                 __le16 l2tag1;
 441                         } lo_dword;
 442                         union {
 443                                 __le32 rss; /* RSS Hash */
 444                                 __le32 fd_id; /* Flow director filter id */
 445                                 __le32 fcoe_param; /* FCoE DDP Context id */
 446                         } hi_dword;
 447                 } qword0;
 448                 struct {
 449                         /* ext status/error/pktype/length */
 450                         __le64 status_error_len;
 451                 } qword1;
 452         } wb;  /* writeback */
 453 };
 454
 455 union i40e_32byte_rx_desc {
 456         struct {
 457                 __le64  pkt_addr; /* Packet buffer address */
 458                 __le64  hdr_addr; /* Header buffer address */
 459                         /* bit 0 of hdr_buffer_addr is DD bit */
 460                 __le64  rsvd1;
 461                 __le64  rsvd2;
 462         } read;
 463         struct {
 464                 struct {
 465                         struct {
 466                                 union {
 467                                         __le16 mirroring_status;
 468                                         __le16 fcoe_ctx_id;
 469                                 } mirr_fcoe;
 470                                 __le16 l2tag1;
 471                         } lo_dword;
 472                         union {
 473                                 __le32 rss; /* RSS Hash */
 474                                 __le32 fcoe_param; /* FCoE DDP Context id */
 475                         } hi_dword;
 476                 } qword0;
 477                 struct {
 478                         /* status/error/pktype/length */
 479                         __le64 status_error_len;
 480                 } qword1;
 481                 struct {
 482                         __le16 ext_status; /* extended status */
 483                         __le16 rsvd;
 484                         __le16 l2tag2_1;
 485                         __le16 l2tag2_2;
 486                 } qword2;
 487                 struct {
 488                         union {
 489                                 __le32 flex_bytes_lo;
 490                                 __le32 pe_status;
 491                         } lo_dword;
 492                         union {
 493                                 __le32 flex_bytes_hi;
 494                                 __le32 fd_id;
 495                         } hi_dword;
 496                 } qword3;
 497         } wb;  /* writeback */
 498 };
 499
 500 #define I40E_RXD_QW1_STATUS_SHIFT       0
 501 #define I40E_RXD_QW1_STATUS_MASK        (0x7FFFUL << I40E_RXD_QW1_STATUS_SHIFT)
 502
 503 enum i40e_rx_desc_status_bits {
 504         /* Note: These are predefined bit offsets */
 505         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 506         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 507         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 508         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 509         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 510         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 511         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 512         I40E_RX_DESC_STATUS_PIF_SHIFT           = 8,
 513         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 514         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 515         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 516         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 517         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 16
 518 };
 519
 520 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 521 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 522                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 523
 524 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 525 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK      (0x1UL << \
 526                                              I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 527
 528 enum i40e_rx_desc_fltstat_values {
 529         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 530         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 531         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 532         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 533 };
 534
 535 #define I40E_RXD_QW1_ERROR_SHIFT        19
 536 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 537
 538 enum i40e_rx_desc_error_bits {
 539         /* Note: These are predefined bit offsets */
 540         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 541         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 542         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 543         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 544         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 545         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 546         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 547         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6
 548 };
 549
 550 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 551         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 552         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 553         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 554         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 555         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 556 };
 557
 558 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 559 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 560
 561 /* Packet type non-ip values */
 562 enum i40e_rx_l2_ptype {
 563         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 564         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 565         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 566         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 567         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 568         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 569         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 570         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 571         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 572         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 573         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 574         I40E_RX_PTYPE_L2_ARP                            = 11,
 575         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 576         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 577         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 578         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 579         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 580         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 581         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 582         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 583         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 584         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 585         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 586         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 587         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 588         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 589 };
 590
 591 struct i40e_rx_ptype_decoded {
 592         u32 ptype:8;
 593         u32 known:1;
 594         u32 outer_ip:1;
 595         u32 outer_ip_ver:1;
 596         u32 outer_frag:1;
 597         u32 tunnel_type:3;
 598         u32 tunnel_end_prot:2;
 599         u32 tunnel_end_frag:1;
 600         u32 inner_prot:4;
 601         u32 payload_layer:3;
 602 };
 603
 604 enum i40e_rx_ptype_outer_ip {
 605         I40E_RX_PTYPE_OUTER_L2  = 0,
 606         I40E_RX_PTYPE_OUTER_IP  = 1
 607 };
 608
 609 enum i40e_rx_ptype_outer_ip_ver {
 610         I40E_RX_PTYPE_OUTER_NONE        = 0,
 611         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 612         I40E_RX_PTYPE_OUTER_IPV6        = 1
 613 };
 614
 615 enum i40e_rx_ptype_outer_fragmented {
 616         I40E_RX_PTYPE_NOT_FRAG  = 0,
 617         I40E_RX_PTYPE_FRAG      = 1
 618 };
 619
 620 enum i40e_rx_ptype_tunnel_type {
 621         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 622         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 623         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 624         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 625         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 626 };
 627
 628 enum i40e_rx_ptype_tunnel_end_prot {
 629         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 630         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 631         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 632 };
 633
 634 enum i40e_rx_ptype_inner_prot {
 635         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 636         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 637         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 638         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 639         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 640         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 641 };
 642
 643 enum i40e_rx_ptype_payload_layer {
 644         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 645         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 646         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 647         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 648 };
 649
 650 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 651 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 652                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 653
 654 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 655 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 656                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 657
 658 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 659 #define I40E_RXD_QW1_LENGTH_SPH_MASK    (0x1ULL << \
 660                                          I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 661
 662 enum i40e_rx_desc_ext_status_bits {
 663         /* Note: These are predefined bit offsets */
 664         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 665         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 666         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 667         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 668         I40E_RX_DESC_EXT_STATUS_FTYPE_SHIFT     = 6, /* 3 BITS */
 669         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 670         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 671         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 672 };
 673
 674 enum i40e_rx_desc_pe_status_bits {
 675         /* Note: These are predefined bit offsets */
 676         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 677         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 678         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 679         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 680         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 681         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 682         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 683         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 684         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 685 };
 686
 687 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 688 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 689
 690 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 691 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 692                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 693
 694 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 695 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 696                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 697
 698 enum i40e_rx_prog_status_desc_status_bits {
 699         /* Note: These are predefined bit offsets */
 700         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 701         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 702 };
 703
 704 enum i40e_rx_prog_status_desc_prog_id_masks {
 705         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 706         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 707         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 708 };
 709
 710 enum i40e_rx_prog_status_desc_error_bits {
 711         /* Note: These are predefined bit offsets */
 712         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 713         I40E_RX_PROG_STATUS_DESC_NO_FD_QUOTA_SHIFT      = 1,
 714         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 715         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 716 };
 717
 718 /* TX Descriptor */
 719 struct i40e_tx_desc {
 720         __le64 buffer_addr; /* Address of descriptor's data buf */
 721         __le64 cmd_type_offset_bsz;
 722 };
 723
 724 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 725 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 726
 727 enum i40e_tx_desc_dtype_value {
 728         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 729         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 730         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 731         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 732         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 733         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 734         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 735         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 736         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 737         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 738 };
 739
 740 #define I40E_TXD_QW1_CMD_SHIFT  4
 741 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 742
 743 enum i40e_tx_desc_cmd_bits {
 744         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 745         I40E_TX_DESC_CMD_RS                     = 0x0002,
 746         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 747         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 748         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 749         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 750         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 751         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 752         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 753         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 754         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 755         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 756         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 757         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 758         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 759         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 760         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 761         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 762 };
 763
 764 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 765 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 766                                          I40E_TXD_QW1_OFFSET_SHIFT)
 767
 768 enum i40e_tx_desc_length_fields {
 769         /* Note: These are predefined bit offsets */
 770         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 771         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 772         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 773 };
 774
 775 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 776 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 777                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 778
 779 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 780 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 781
 782 /* Context descriptors */
 783 struct i40e_tx_context_desc {
 784         __le32 tunneling_params;
 785         __le16 l2tag2;
 786         __le16 rsvd;
 787         __le64 type_cmd_tso_mss;
 788 };
 789
 790 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 791 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 792
 793 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 794 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 795
 796 enum i40e_tx_ctx_desc_cmd_bits {
 797         I40E_TX_CTX_DESC_TSO            = 0x01,
 798         I40E_TX_CTX_DESC_TSYN           = 0x02,
 799         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 800         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 801         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 802         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 803         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 804         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 805         I40E_TX_CTX_DESC_SWPE           = 0x40
 806 };
 807
 808 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 809 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 810                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
 811
 812 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 813 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 814                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
 815
 816 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
 817 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
 818
 819 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
 820 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 821                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
 822
 823 enum i40e_tx_ctx_desc_eipt_offload {
 824         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
 825         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
 826         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 827         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
 828 };
 829
 830 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 831 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
 832                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
 833
 834 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
 835 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 836
 837 #define I40E_TXD_CTX_UDP_TUNNELING      (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 838 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 839
 840 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
 841 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
 842                                          I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
 843
 844 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
 845
 846 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
 847 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
 848                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
 849
 850 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
 851 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
 852                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 853
 854 struct i40e_filter_program_desc {
 855         __le32 qindex_flex_ptype_vsi;
 856         __le32 rsvd;
 857         __le32 dtype_cmd_cntindex;
 858         __le32 fd_id;
 859 };
 860 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
 861 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
 862                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
 863 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
 864 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
 865                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
 866 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
 867 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
 868                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
 869
 870 /* Packet Classifier Types for filters */
 871 enum i40e_filter_pctype {
 872         /* Note: Values 0-28 are reserved for future use */
 873         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
 874         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
 875         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
 876         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN            = 32,
 877         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
 878         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
 879         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
 880         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
 881         /* Note: Values 37-38 are reserved for future use */
 882         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
 883         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
 884         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
 885         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN            = 42,
 886         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
 887         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
 888         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
 889         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
 890         /* Note: Value 47 is reserved for future use */
 891         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
 892         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
 893         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
 894         /* Note: Values 51-62 are reserved for future use */
 895         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
 896 };
 897
 898 enum i40e_filter_program_desc_dest {
 899         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
 900         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
 901         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
 902 };
 903
 904 enum i40e_filter_program_desc_fd_status {
 905         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
 906         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
 907         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
 908         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
 909 };
 910
 911 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
 912 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
 913                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
 914
 915 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
 916 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
 917                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
 918
 919 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 920 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
 921
 922 enum i40e_filter_program_desc_pcmd {
 923         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
 924         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
 925 };
 926
 927 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 928 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
 929
 930 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 931 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  (0x1ULL << \
 932                                          I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
 933
 934 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
 935                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
 936 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
 937                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
 938
 939 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
 940 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
 941                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
 942
 943 enum i40e_filter_type {
 944         I40E_FLOW_DIRECTOR_FLTR = 0,
 945         I40E_PE_QUAD_HASH_FLTR = 1,
 946         I40E_ETHERTYPE_FLTR,
 947         I40E_FCOE_CTX_FLTR,
 948         I40E_MAC_VLAN_FLTR,
 949         I40E_HASH_FLTR
 950 };
 951
 952 struct i40e_vsi_context {
 953         u16 seid;
 954         u16 uplink_seid;
 955         u16 vsi_number;
 956         u16 vsis_allocated;
 957         u16 vsis_unallocated;
 958         u16 flags;
 959         u8 pf_num;
 960         u8 vf_num;
 961         u8 connection_type;
 962         struct i40e_aqc_vsi_properties_data info;
 963 };
 964
 965 /* Statistics collected by each port, VSI, VEB, and S-channel */
 966 struct i40e_eth_stats {
 967         u64 rx_bytes;                   /* gorc */
 968         u64 rx_unicast;                 /* uprc */
 969         u64 rx_multicast;               /* mprc */
 970         u64 rx_broadcast;               /* bprc */
 971         u64 rx_discards;                /* rdpc */
 972         u64 rx_errors;                  /* repc */
 973         u64 rx_missed;                  /* rmpc */
 974         u64 rx_unknown_protocol;        /* rupp */
 975         u64 tx_bytes;                   /* gotc */
 976         u64 tx_unicast;                 /* uptc */
 977         u64 tx_multicast;               /* mptc */
 978         u64 tx_broadcast;               /* bptc */
 979         u64 tx_discards;                /* tdpc */
 980         u64 tx_errors;                  /* tepc */
 981 };
 982
 983 /* Statistics collected by the MAC */
 984 struct i40e_hw_port_stats {
 985         /* eth stats collected by the port */
 986         struct i40e_eth_stats eth;
 987
 988         /* additional port specific stats */
 989         u64 tx_dropped_link_down;       /* tdold */
 990         u64 crc_errors;                 /* crcerrs */
 991         u64 illegal_bytes;              /* illerrc */
 992         u64 error_bytes;                /* errbc */
 993         u64 mac_local_faults;           /* mlfc */
 994         u64 mac_remote_faults;          /* mrfc */
 995         u64 rx_length_errors;           /* rlec */
 996         u64 link_xon_rx;                /* lxonrxc */
 997         u64 link_xoff_rx;               /* lxoffrxc */
 998         u64 priority_xon_rx[8];         /* pxonrxc[8] */
 999         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1000         u64 link_xon_tx;                /* lxontxc */
1001         u64 link_xoff_tx;               /* lxofftxc */
1002         u64 priority_xon_tx[8];         /* pxontxc[8] */
1003         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1004         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1005         u64 rx_size_64;                 /* prc64 */
1006         u64 rx_size_127;                /* prc127 */
1007         u64 rx_size_255;                /* prc255 */
1008         u64 rx_size_511;                /* prc511 */
1009         u64 rx_size_1023;               /* prc1023 */
1010         u64 rx_size_1522;               /* prc1522 */
1011         u64 rx_size_big;                /* prc9522 */
1012         u64 rx_undersize;               /* ruc */
1013         u64 rx_fragments;               /* rfc */
1014         u64 rx_oversize;                /* roc */
1015         u64 rx_jabber;                  /* rjc */
1016         u64 tx_size_64;                 /* ptc64 */
1017         u64 tx_size_127;                /* ptc127 */
1018         u64 tx_size_255;                /* ptc255 */
1019         u64 tx_size_511;                /* ptc511 */
1020         u64 tx_size_1023;               /* ptc1023 */
1021         u64 tx_size_1522;               /* ptc1522 */
1022         u64 tx_size_big;                /* ptc9522 */
1023         u64 mac_short_packet_dropped;   /* mspdc */
1024         u64 checksum_error;             /* xec */
1025 };
1026
1027 /* Checksum and Shadow RAM pointers */
1028 #define I40E_SR_NVM_CONTROL_WORD                0x00
1029 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1030 #define I40E_SR_NVM_IMAGE_VERSION               0x18
1031 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1032 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1033 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1034 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1035 #define I40E_SR_VPD_PTR                         0x2F
1036 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1037 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1038
1039 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1040 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1041 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1042 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1043 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1044
1045 /* Shadow RAM related */
1046 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1047 #define I40E_SR_WORDS_IN_1KB            512
1048 /* Checksum should be calculated such that after adding all the words,
1049  * including the checksum word itself, the sum should be 0xBABA.
1050  */
1051 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1052
1053 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1054
1055 enum i40e_switch_element_types {
1056         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1057         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1058         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1059         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1060         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1061         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1062         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1063         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1064         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1065 };
1066
1067 /* Supported EtherType filters */
1068 enum i40e_ether_type_index {
1069         I40E_ETHER_TYPE_1588            = 0,
1070         I40E_ETHER_TYPE_FIP             = 1,
1071         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1072         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1073         I40E_ETHER_TYPE_LLDP            = 4,
1074         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1075         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1076         I40E_ETHER_TYPE_QCN_CNM         = 7,
1077         I40E_ETHER_TYPE_8021X           = 8,
1078         I40E_ETHER_TYPE_ARP             = 9,
1079         I40E_ETHER_TYPE_RSV1            = 10,
1080         I40E_ETHER_TYPE_RSV2            = 11,
1081 };
1082
1083 /* Filter context base size is 1K */
1084 #define I40E_HASH_FILTER_BASE_SIZE      1024
1085 /* Supported Hash filter values */
1086 enum i40e_hash_filter_size {
1087         I40E_HASH_FILTER_SIZE_1K        = 0,
1088         I40E_HASH_FILTER_SIZE_2K        = 1,
1089         I40E_HASH_FILTER_SIZE_4K        = 2,
1090         I40E_HASH_FILTER_SIZE_8K        = 3,
1091         I40E_HASH_FILTER_SIZE_16K       = 4,
1092         I40E_HASH_FILTER_SIZE_32K       = 5,
1093         I40E_HASH_FILTER_SIZE_64K       = 6,
1094         I40E_HASH_FILTER_SIZE_128K      = 7,
1095         I40E_HASH_FILTER_SIZE_256K      = 8,
1096         I40E_HASH_FILTER_SIZE_512K      = 9,
1097         I40E_HASH_FILTER_SIZE_1M        = 10,
1098 };
1099
1100 /* DMA context base size is 0.5K */
1101 #define I40E_DMA_CNTX_BASE_SIZE         512
1102 /* Supported DMA context values */
1103 enum i40e_dma_cntx_size {
1104         I40E_DMA_CNTX_SIZE_512          = 0,
1105         I40E_DMA_CNTX_SIZE_1K           = 1,
1106         I40E_DMA_CNTX_SIZE_2K           = 2,
1107         I40E_DMA_CNTX_SIZE_4K           = 3,
1108         I40E_DMA_CNTX_SIZE_8K           = 4,
1109         I40E_DMA_CNTX_SIZE_16K          = 5,
1110         I40E_DMA_CNTX_SIZE_32K          = 6,
1111         I40E_DMA_CNTX_SIZE_64K          = 7,
1112         I40E_DMA_CNTX_SIZE_128K         = 8,
1113         I40E_DMA_CNTX_SIZE_256K         = 9,
1114 };
1115
1116 /* Supported Hash look up table (LUT) sizes */
1117 enum i40e_hash_lut_size {
1118         I40E_HASH_LUT_SIZE_128          = 0,
1119         I40E_HASH_LUT_SIZE_512          = 1,
1120 };
1121
1122 /* Structure to hold a per PF filter control settings */
1123 struct i40e_filter_control_settings {
1124         /* number of PE Quad Hash filter buckets */
1125         enum i40e_hash_filter_size pe_filt_num;
1126         /* number of PE Quad Hash contexts */
1127         enum i40e_dma_cntx_size pe_cntx_num;
1128         /* number of FCoE filter buckets */
1129         enum i40e_hash_filter_size fcoe_filt_num;
1130         /* number of FCoE DDP contexts */
1131         enum i40e_dma_cntx_size fcoe_cntx_num;
1132         /* size of the Hash LUT */
1133         enum i40e_hash_lut_size hash_lut_size;
1134         /* enable FDIR filters for PF and its VFs */
1135         bool enable_fdir;
1136         /* enable Ethertype filters for PF and its VFs */
1137         bool enable_ethtype;
1138         /* enable MAC/VLAN filters for PF and its VFs */
1139         bool enable_macvlan;
1140 };
1141
1142 /* Structure to hold device level control filter counts */
1143 struct i40e_control_filter_stats {
1144         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1145         u16 etype_used;       /* Used perfect EtherType filters */
1146         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1147         u16 etype_free;       /* Un-used perfect EtherType filters */
1148 };
1149
1150 enum i40e_reset_type {
1151         I40E_RESET_POR          = 0,
1152         I40E_RESET_CORER        = 1,
1153         I40E_RESET_GLOBR        = 2,
1154         I40E_RESET_EMPR         = 3,
1155 };
1156
1157 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1158 #define I40E_NVM_LLDP_CFG_PTR           0xF
1159 struct i40e_lldp_variables {
1160         u16 length;
1161         u16 adminstatus;
1162         u16 msgfasttx;
1163         u16 msgtxinterval;
1164         u16 txparams;
1165         u16 timers;
1166         u16 crc8;
1167 };
1168
1169 #endif /* _I40E_TYPE_H_ */